main.c revision 02a588a2e3b9e0156f306a542bb6cd29ba42e1b9
1/* 2 * Copyright (c) 2010 Broadcom Corporation 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17#include <linux/pci_ids.h> 18#include <linux/if_ether.h> 19#include <net/mac80211.h> 20#include <brcm_hw_ids.h> 21#include <aiutils.h> 22#include <chipcommon.h> 23#include "rate.h" 24#include "scb.h" 25#include "phy/phy_hal.h" 26#include "channel.h" 27#include "antsel.h" 28#include "stf.h" 29#include "ampdu.h" 30#include "mac80211_if.h" 31#include "ucode_loader.h" 32#include "main.h" 33#include "soc.h" 34 35/* 36 * Indication for txflowcontrol that all priority bits in 37 * TXQ_STOP_FOR_PRIOFC_MASK are to be considered. 38 */ 39#define ALLPRIO -1 40 41/* watchdog timer, in unit of ms */ 42#define TIMER_INTERVAL_WATCHDOG 1000 43/* radio monitor timer, in unit of ms */ 44#define TIMER_INTERVAL_RADIOCHK 800 45 46/* beacon interval, in unit of 1024TU */ 47#define BEACON_INTERVAL_DEFAULT 100 48 49/* n-mode support capability */ 50/* 2x2 includes both 1x1 & 2x2 devices 51 * reserved #define 2 for future when we want to separate 1x1 & 2x2 and 52 * control it independently 53 */ 54#define WL_11N_2x2 1 55#define WL_11N_3x3 3 56#define WL_11N_4x4 4 57 58#define EDCF_ACI_MASK 0x60 59#define EDCF_ACI_SHIFT 5 60#define EDCF_ECWMIN_MASK 0x0f 61#define EDCF_ECWMAX_SHIFT 4 62#define EDCF_AIFSN_MASK 0x0f 63#define EDCF_AIFSN_MAX 15 64#define EDCF_ECWMAX_MASK 0xf0 65 66#define EDCF_AC_BE_TXOP_STA 0x0000 67#define EDCF_AC_BK_TXOP_STA 0x0000 68#define EDCF_AC_VO_ACI_STA 0x62 69#define EDCF_AC_VO_ECW_STA 0x32 70#define EDCF_AC_VI_ACI_STA 0x42 71#define EDCF_AC_VI_ECW_STA 0x43 72#define EDCF_AC_BK_ECW_STA 0xA4 73#define EDCF_AC_VI_TXOP_STA 0x005e 74#define EDCF_AC_VO_TXOP_STA 0x002f 75#define EDCF_AC_BE_ACI_STA 0x03 76#define EDCF_AC_BE_ECW_STA 0xA4 77#define EDCF_AC_BK_ACI_STA 0x27 78#define EDCF_AC_VO_TXOP_AP 0x002f 79 80#define EDCF_TXOP2USEC(txop) ((txop) << 5) 81#define EDCF_ECW2CW(exp) ((1 << (exp)) - 1) 82 83#define APHY_SYMBOL_TIME 4 84#define APHY_PREAMBLE_TIME 16 85#define APHY_SIGNAL_TIME 4 86#define APHY_SIFS_TIME 16 87#define APHY_SERVICE_NBITS 16 88#define APHY_TAIL_NBITS 6 89#define BPHY_SIFS_TIME 10 90#define BPHY_PLCP_SHORT_TIME 96 91 92#define PREN_PREAMBLE 24 93#define PREN_MM_EXT 12 94#define PREN_PREAMBLE_EXT 4 95 96#define DOT11_MAC_HDR_LEN 24 97#define DOT11_ACK_LEN 10 98#define DOT11_BA_LEN 4 99#define DOT11_OFDM_SIGNAL_EXTENSION 6 100#define DOT11_MIN_FRAG_LEN 256 101#define DOT11_RTS_LEN 16 102#define DOT11_CTS_LEN 10 103#define DOT11_BA_BITMAP_LEN 128 104#define DOT11_MIN_BEACON_PERIOD 1 105#define DOT11_MAX_BEACON_PERIOD 0xFFFF 106#define DOT11_MAXNUMFRAGS 16 107#define DOT11_MAX_FRAG_LEN 2346 108 109#define BPHY_PLCP_TIME 192 110#define RIFS_11N_TIME 2 111 112/* length of the BCN template area */ 113#define BCN_TMPL_LEN 512 114 115/* brcms_bss_info flag bit values */ 116#define BRCMS_BSS_HT 0x0020 /* BSS is HT (MIMO) capable */ 117 118/* chip rx buffer offset */ 119#define BRCMS_HWRXOFF 38 120 121/* rfdisable delay timer 500 ms, runs of ALP clock */ 122#define RFDISABLE_DEFAULT 10000000 123 124#define BRCMS_TEMPSENSE_PERIOD 10 /* 10 second timeout */ 125 126/* precedences numbers for wlc queues. These are twice as may levels as 127 * 802.1D priorities. 128 * Odd numbers are used for HI priority traffic at same precedence levels 129 * These constants are used ONLY by wlc_prio2prec_map. Do not use them 130 * elsewhere. 131 */ 132#define _BRCMS_PREC_NONE 0 /* None = - */ 133#define _BRCMS_PREC_BK 2 /* BK - Background */ 134#define _BRCMS_PREC_BE 4 /* BE - Best-effort */ 135#define _BRCMS_PREC_EE 6 /* EE - Excellent-effort */ 136#define _BRCMS_PREC_CL 8 /* CL - Controlled Load */ 137#define _BRCMS_PREC_VI 10 /* Vi - Video */ 138#define _BRCMS_PREC_VO 12 /* Vo - Voice */ 139#define _BRCMS_PREC_NC 14 /* NC - Network Control */ 140 141/* synthpu_dly times in us */ 142#define SYNTHPU_DLY_APHY_US 3700 143#define SYNTHPU_DLY_BPHY_US 1050 144#define SYNTHPU_DLY_NPHY_US 2048 145#define SYNTHPU_DLY_LPPHY_US 300 146 147#define ANTCNT 10 /* vanilla M_MAX_ANTCNT val */ 148 149/* Per-AC retry limit register definitions; uses defs.h bitfield macros */ 150#define EDCF_SHORT_S 0 151#define EDCF_SFB_S 4 152#define EDCF_LONG_S 8 153#define EDCF_LFB_S 12 154#define EDCF_SHORT_M BITFIELD_MASK(4) 155#define EDCF_SFB_M BITFIELD_MASK(4) 156#define EDCF_LONG_M BITFIELD_MASK(4) 157#define EDCF_LFB_M BITFIELD_MASK(4) 158 159#define RETRY_SHORT_DEF 7 /* Default Short retry Limit */ 160#define RETRY_SHORT_MAX 255 /* Maximum Short retry Limit */ 161#define RETRY_LONG_DEF 4 /* Default Long retry count */ 162#define RETRY_SHORT_FB 3 /* Short count for fb rate */ 163#define RETRY_LONG_FB 2 /* Long count for fb rate */ 164 165#define APHY_CWMIN 15 166#define PHY_CWMAX 1023 167 168#define EDCF_AIFSN_MIN 1 169 170#define FRAGNUM_MASK 0xF 171 172#define APHY_SLOT_TIME 9 173#define BPHY_SLOT_TIME 20 174 175#define WL_SPURAVOID_OFF 0 176#define WL_SPURAVOID_ON1 1 177#define WL_SPURAVOID_ON2 2 178 179/* invalid core flags, use the saved coreflags */ 180#define BRCMS_USE_COREFLAGS 0xffffffff 181 182/* values for PLCPHdr_override */ 183#define BRCMS_PLCP_AUTO -1 184#define BRCMS_PLCP_SHORT 0 185#define BRCMS_PLCP_LONG 1 186 187/* values for g_protection_override and n_protection_override */ 188#define BRCMS_PROTECTION_AUTO -1 189#define BRCMS_PROTECTION_OFF 0 190#define BRCMS_PROTECTION_ON 1 191#define BRCMS_PROTECTION_MMHDR_ONLY 2 192#define BRCMS_PROTECTION_CTS_ONLY 3 193 194/* values for g_protection_control and n_protection_control */ 195#define BRCMS_PROTECTION_CTL_OFF 0 196#define BRCMS_PROTECTION_CTL_LOCAL 1 197#define BRCMS_PROTECTION_CTL_OVERLAP 2 198 199/* values for n_protection */ 200#define BRCMS_N_PROTECTION_OFF 0 201#define BRCMS_N_PROTECTION_OPTIONAL 1 202#define BRCMS_N_PROTECTION_20IN40 2 203#define BRCMS_N_PROTECTION_MIXEDMODE 3 204 205/* values for band specific 40MHz capabilities */ 206#define BRCMS_N_BW_20ALL 0 207#define BRCMS_N_BW_40ALL 1 208#define BRCMS_N_BW_20IN2G_40IN5G 2 209 210/* bitflags for SGI support (sgi_rx iovar) */ 211#define BRCMS_N_SGI_20 0x01 212#define BRCMS_N_SGI_40 0x02 213 214/* defines used by the nrate iovar */ 215/* MSC in use,indicates b0-6 holds an mcs */ 216#define NRATE_MCS_INUSE 0x00000080 217/* rate/mcs value */ 218#define NRATE_RATE_MASK 0x0000007f 219/* stf mode mask: siso, cdd, stbc, sdm */ 220#define NRATE_STF_MASK 0x0000ff00 221/* stf mode shift */ 222#define NRATE_STF_SHIFT 8 223/* bit indicate to override mcs only */ 224#define NRATE_OVERRIDE_MCS_ONLY 0x40000000 225#define NRATE_SGI_MASK 0x00800000 /* sgi mode */ 226#define NRATE_SGI_SHIFT 23 /* sgi mode */ 227#define NRATE_LDPC_CODING 0x00400000 /* adv coding in use */ 228#define NRATE_LDPC_SHIFT 22 /* ldpc shift */ 229 230#define NRATE_STF_SISO 0 /* stf mode SISO */ 231#define NRATE_STF_CDD 1 /* stf mode CDD */ 232#define NRATE_STF_STBC 2 /* stf mode STBC */ 233#define NRATE_STF_SDM 3 /* stf mode SDM */ 234 235#define MAX_DMA_SEGS 4 236 237/* Max # of entries in Tx FIFO based on 4kb page size */ 238#define NTXD 256 239/* Max # of entries in Rx FIFO based on 4kb page size */ 240#define NRXD 256 241 242/* try to keep this # rbufs posted to the chip */ 243#define NRXBUFPOST 32 244 245/* data msg txq hiwat mark */ 246#define BRCMS_DATAHIWAT 50 247 248/* max # frames to process in brcms_c_recv() */ 249#define RXBND 8 250/* max # tx status to process in wlc_txstatus() */ 251#define TXSBND 8 252 253/* brcmu_format_flags() bit description structure */ 254struct brcms_c_bit_desc { 255 u32 bit; 256 const char *name; 257}; 258 259/* 260 * The following table lists the buffer memory allocated to xmt fifos in HW. 261 * the size is in units of 256bytes(one block), total size is HW dependent 262 * ucode has default fifo partition, sw can overwrite if necessary 263 * 264 * This is documented in twiki under the topic UcodeTxFifo. Please ensure 265 * the twiki is updated before making changes. 266 */ 267 268/* Starting corerev for the fifo size table */ 269#define XMTFIFOTBL_STARTREV 20 270 271struct d11init { 272 __le16 addr; 273 __le16 size; 274 __le32 value; 275}; 276 277struct edcf_acparam { 278 u8 ACI; 279 u8 ECW; 280 u16 TXOP; 281} __packed; 282 283const u8 prio2fifo[NUMPRIO] = { 284 TX_AC_BE_FIFO, /* 0 BE AC_BE Best Effort */ 285 TX_AC_BK_FIFO, /* 1 BK AC_BK Background */ 286 TX_AC_BK_FIFO, /* 2 -- AC_BK Background */ 287 TX_AC_BE_FIFO, /* 3 EE AC_BE Best Effort */ 288 TX_AC_VI_FIFO, /* 4 CL AC_VI Video */ 289 TX_AC_VI_FIFO, /* 5 VI AC_VI Video */ 290 TX_AC_VO_FIFO, /* 6 VO AC_VO Voice */ 291 TX_AC_VO_FIFO /* 7 NC AC_VO Voice */ 292}; 293 294/* debug/trace */ 295uint brcm_msg_level = 296#if defined(BCMDBG) 297 LOG_ERROR_VAL; 298#else 299 0; 300#endif /* BCMDBG */ 301 302/* TX FIFO number to WME/802.1E Access Category */ 303static const u8 wme_fifo2ac[] = { 304 IEEE80211_AC_BK, 305 IEEE80211_AC_BE, 306 IEEE80211_AC_VI, 307 IEEE80211_AC_VO, 308 IEEE80211_AC_BE, 309 IEEE80211_AC_BE 310}; 311 312/* ieee80211 Access Category to TX FIFO number */ 313static const u8 wme_ac2fifo[] = { 314 TX_AC_VO_FIFO, 315 TX_AC_VI_FIFO, 316 TX_AC_BE_FIFO, 317 TX_AC_BK_FIFO 318}; 319 320/* 802.1D Priority to precedence queue mapping */ 321const u8 wlc_prio2prec_map[] = { 322 _BRCMS_PREC_BE, /* 0 BE - Best-effort */ 323 _BRCMS_PREC_BK, /* 1 BK - Background */ 324 _BRCMS_PREC_NONE, /* 2 None = - */ 325 _BRCMS_PREC_EE, /* 3 EE - Excellent-effort */ 326 _BRCMS_PREC_CL, /* 4 CL - Controlled Load */ 327 _BRCMS_PREC_VI, /* 5 Vi - Video */ 328 _BRCMS_PREC_VO, /* 6 Vo - Voice */ 329 _BRCMS_PREC_NC, /* 7 NC - Network Control */ 330}; 331 332static const u16 xmtfifo_sz[][NFIFO] = { 333 /* corerev 20: 5120, 49152, 49152, 5376, 4352, 1280 */ 334 {20, 192, 192, 21, 17, 5}, 335 /* corerev 21: 2304, 14848, 5632, 3584, 3584, 1280 */ 336 {9, 58, 22, 14, 14, 5}, 337 /* corerev 22: 5120, 49152, 49152, 5376, 4352, 1280 */ 338 {20, 192, 192, 21, 17, 5}, 339 /* corerev 23: 5120, 49152, 49152, 5376, 4352, 1280 */ 340 {20, 192, 192, 21, 17, 5}, 341 /* corerev 24: 2304, 14848, 5632, 3584, 3584, 1280 */ 342 {9, 58, 22, 14, 14, 5}, 343}; 344 345#ifdef BCMDBG 346static const char * const fifo_names[] = { 347 "AC_BK", "AC_BE", "AC_VI", "AC_VO", "BCMC", "ATIM" }; 348#else 349static const char fifo_names[6][0]; 350#endif 351 352#ifdef BCMDBG 353/* pointer to most recently allocated wl/wlc */ 354static struct brcms_c_info *wlc_info_dbg = (struct brcms_c_info *) (NULL); 355#endif 356 357/* Find basic rate for a given rate */ 358static u8 brcms_basic_rate(struct brcms_c_info *wlc, u32 rspec) 359{ 360 if (is_mcs_rate(rspec)) 361 return wlc->band->basic_rate[mcs_table[rspec & RSPEC_RATE_MASK] 362 .leg_ofdm]; 363 return wlc->band->basic_rate[rspec & RSPEC_RATE_MASK]; 364} 365 366static u16 frametype(u32 rspec, u8 mimoframe) 367{ 368 if (is_mcs_rate(rspec)) 369 return mimoframe; 370 return is_cck_rate(rspec) ? FT_CCK : FT_OFDM; 371} 372 373/* currently the best mechanism for determining SIFS is the band in use */ 374static u16 get_sifs(struct brcms_band *band) 375{ 376 return band->bandtype == BRCM_BAND_5G ? APHY_SIFS_TIME : 377 BPHY_SIFS_TIME; 378} 379 380/* 381 * Detect Card removed. 382 * Even checking an sbconfig register read will not false trigger when the core 383 * is in reset it breaks CF address mechanism. Accessing gphy phyversion will 384 * cause SB error if aphy is in reset on 4306B0-DB. Need a simple accessible 385 * reg with fixed 0/1 pattern (some platforms return all 0). 386 * If clocks are present, call the sb routine which will figure out if the 387 * device is removed. 388 */ 389static bool brcms_deviceremoved(struct brcms_c_info *wlc) 390{ 391 if (!wlc->hw->clk) 392 return ai_deviceremoved(wlc->hw->sih); 393 return (R_REG(&wlc->hw->regs->maccontrol) & 394 (MCTL_PSM_JMP_0 | MCTL_IHR_EN)) != MCTL_IHR_EN; 395} 396 397/* sum the individual fifo tx pending packet counts */ 398static s16 brcms_txpktpendtot(struct brcms_c_info *wlc) 399{ 400 return wlc->core->txpktpend[0] + wlc->core->txpktpend[1] + 401 wlc->core->txpktpend[2] + wlc->core->txpktpend[3]; 402} 403 404static bool brcms_is_mband_unlocked(struct brcms_c_info *wlc) 405{ 406 return wlc->pub->_nbands > 1 && !wlc->bandlocked; 407} 408 409static int brcms_chspec_bw(u16 chanspec) 410{ 411 if (CHSPEC_IS40(chanspec)) 412 return BRCMS_40_MHZ; 413 if (CHSPEC_IS20(chanspec)) 414 return BRCMS_20_MHZ; 415 416 return BRCMS_10_MHZ; 417} 418 419static void brcms_c_bsscfg_mfree(struct brcms_bss_cfg *cfg) 420{ 421 if (cfg == NULL) 422 return; 423 424 kfree(cfg->current_bss); 425 kfree(cfg); 426} 427 428static void brcms_c_detach_mfree(struct brcms_c_info *wlc) 429{ 430 if (wlc == NULL) 431 return; 432 433 brcms_c_bsscfg_mfree(wlc->bsscfg); 434 kfree(wlc->pub); 435 kfree(wlc->modulecb); 436 kfree(wlc->default_bss); 437 kfree(wlc->protection); 438 kfree(wlc->stf); 439 kfree(wlc->bandstate[0]); 440 kfree(wlc->corestate->macstat_snapshot); 441 kfree(wlc->corestate); 442 kfree(wlc->hw->bandstate[0]); 443 kfree(wlc->hw); 444 445 /* free the wlc */ 446 kfree(wlc); 447 wlc = NULL; 448} 449 450static struct brcms_bss_cfg *brcms_c_bsscfg_malloc(uint unit) 451{ 452 struct brcms_bss_cfg *cfg; 453 454 cfg = kzalloc(sizeof(struct brcms_bss_cfg), GFP_ATOMIC); 455 if (cfg == NULL) 456 goto fail; 457 458 cfg->current_bss = kzalloc(sizeof(struct brcms_bss_info), GFP_ATOMIC); 459 if (cfg->current_bss == NULL) 460 goto fail; 461 462 return cfg; 463 464 fail: 465 brcms_c_bsscfg_mfree(cfg); 466 return NULL; 467} 468 469static struct brcms_c_info * 470brcms_c_attach_malloc(uint unit, uint *err, uint devid) 471{ 472 struct brcms_c_info *wlc; 473 474 wlc = kzalloc(sizeof(struct brcms_c_info), GFP_ATOMIC); 475 if (wlc == NULL) { 476 *err = 1002; 477 goto fail; 478 } 479 480 /* allocate struct brcms_c_pub state structure */ 481 wlc->pub = kzalloc(sizeof(struct brcms_pub), GFP_ATOMIC); 482 if (wlc->pub == NULL) { 483 *err = 1003; 484 goto fail; 485 } 486 wlc->pub->wlc = wlc; 487 488 /* allocate struct brcms_hardware state structure */ 489 490 wlc->hw = kzalloc(sizeof(struct brcms_hardware), GFP_ATOMIC); 491 if (wlc->hw == NULL) { 492 *err = 1005; 493 goto fail; 494 } 495 wlc->hw->wlc = wlc; 496 497 wlc->hw->bandstate[0] = 498 kzalloc(sizeof(struct brcms_hw_band) * MAXBANDS, GFP_ATOMIC); 499 if (wlc->hw->bandstate[0] == NULL) { 500 *err = 1006; 501 goto fail; 502 } else { 503 int i; 504 505 for (i = 1; i < MAXBANDS; i++) 506 wlc->hw->bandstate[i] = (struct brcms_hw_band *) 507 ((unsigned long)wlc->hw->bandstate[0] + 508 (sizeof(struct brcms_hw_band) * i)); 509 } 510 511 wlc->modulecb = 512 kzalloc(sizeof(struct modulecb) * BRCMS_MAXMODULES, GFP_ATOMIC); 513 if (wlc->modulecb == NULL) { 514 *err = 1009; 515 goto fail; 516 } 517 518 wlc->default_bss = kzalloc(sizeof(struct brcms_bss_info), GFP_ATOMIC); 519 if (wlc->default_bss == NULL) { 520 *err = 1010; 521 goto fail; 522 } 523 524 wlc->bsscfg = brcms_c_bsscfg_malloc(unit); 525 if (wlc->bsscfg == NULL) { 526 *err = 1011; 527 goto fail; 528 } 529 530 wlc->protection = kzalloc(sizeof(struct brcms_protection), 531 GFP_ATOMIC); 532 if (wlc->protection == NULL) { 533 *err = 1016; 534 goto fail; 535 } 536 537 wlc->stf = kzalloc(sizeof(struct brcms_stf), GFP_ATOMIC); 538 if (wlc->stf == NULL) { 539 *err = 1017; 540 goto fail; 541 } 542 543 wlc->bandstate[0] = 544 kzalloc(sizeof(struct brcms_band)*MAXBANDS, GFP_ATOMIC); 545 if (wlc->bandstate[0] == NULL) { 546 *err = 1025; 547 goto fail; 548 } else { 549 int i; 550 551 for (i = 1; i < MAXBANDS; i++) 552 wlc->bandstate[i] = (struct brcms_band *) 553 ((unsigned long)wlc->bandstate[0] 554 + (sizeof(struct brcms_band)*i)); 555 } 556 557 wlc->corestate = kzalloc(sizeof(struct brcms_core), GFP_ATOMIC); 558 if (wlc->corestate == NULL) { 559 *err = 1026; 560 goto fail; 561 } 562 563 wlc->corestate->macstat_snapshot = 564 kzalloc(sizeof(struct macstat), GFP_ATOMIC); 565 if (wlc->corestate->macstat_snapshot == NULL) { 566 *err = 1027; 567 goto fail; 568 } 569 570 return wlc; 571 572 fail: 573 brcms_c_detach_mfree(wlc); 574 return NULL; 575} 576 577/* 578 * Update the slot timing for standard 11b/g (20us slots) 579 * or shortslot 11g (9us slots) 580 * The PSM needs to be suspended for this call. 581 */ 582static void brcms_b_update_slot_timing(struct brcms_hardware *wlc_hw, 583 bool shortslot) 584{ 585 struct d11regs __iomem *regs; 586 587 regs = wlc_hw->regs; 588 589 if (shortslot) { 590 /* 11g short slot: 11a timing */ 591 W_REG(®s->ifs_slot, 0x0207); /* APHY_SLOT_TIME */ 592 brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, APHY_SLOT_TIME); 593 } else { 594 /* 11g long slot: 11b timing */ 595 W_REG(®s->ifs_slot, 0x0212); /* BPHY_SLOT_TIME */ 596 brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, BPHY_SLOT_TIME); 597 } 598} 599 600/* 601 * calculate frame duration of a given rate and length, return 602 * time in usec unit 603 */ 604static uint brcms_c_calc_frame_time(struct brcms_c_info *wlc, u32 ratespec, 605 u8 preamble_type, uint mac_len) 606{ 607 uint nsyms, dur = 0, Ndps, kNdps; 608 uint rate = rspec2rate(ratespec); 609 610 if (rate == 0) { 611 wiphy_err(wlc->wiphy, "wl%d: WAR: using rate of 1 mbps\n", 612 wlc->pub->unit); 613 rate = BRCM_RATE_1M; 614 } 615 616 BCMMSG(wlc->wiphy, "wl%d: rspec 0x%x, preamble_type %d, len%d\n", 617 wlc->pub->unit, ratespec, preamble_type, mac_len); 618 619 if (is_mcs_rate(ratespec)) { 620 uint mcs = ratespec & RSPEC_RATE_MASK; 621 int tot_streams = mcs_2_txstreams(mcs) + rspec_stc(ratespec); 622 623 dur = PREN_PREAMBLE + (tot_streams * PREN_PREAMBLE_EXT); 624 if (preamble_type == BRCMS_MM_PREAMBLE) 625 dur += PREN_MM_EXT; 626 /* 1000Ndbps = kbps * 4 */ 627 kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec), 628 rspec_issgi(ratespec)) * 4; 629 630 if (rspec_stc(ratespec) == 0) 631 nsyms = 632 CEIL((APHY_SERVICE_NBITS + 8 * mac_len + 633 APHY_TAIL_NBITS) * 1000, kNdps); 634 else 635 /* STBC needs to have even number of symbols */ 636 nsyms = 637 2 * 638 CEIL((APHY_SERVICE_NBITS + 8 * mac_len + 639 APHY_TAIL_NBITS) * 1000, 2 * kNdps); 640 641 dur += APHY_SYMBOL_TIME * nsyms; 642 if (wlc->band->bandtype == BRCM_BAND_2G) 643 dur += DOT11_OFDM_SIGNAL_EXTENSION; 644 } else if (is_ofdm_rate(rate)) { 645 dur = APHY_PREAMBLE_TIME; 646 dur += APHY_SIGNAL_TIME; 647 /* Ndbps = Mbps * 4 = rate(500Kbps) * 2 */ 648 Ndps = rate * 2; 649 /* NSyms = CEILING((SERVICE + 8*NBytes + TAIL) / Ndbps) */ 650 nsyms = 651 CEIL((APHY_SERVICE_NBITS + 8 * mac_len + APHY_TAIL_NBITS), 652 Ndps); 653 dur += APHY_SYMBOL_TIME * nsyms; 654 if (wlc->band->bandtype == BRCM_BAND_2G) 655 dur += DOT11_OFDM_SIGNAL_EXTENSION; 656 } else { 657 /* 658 * calc # bits * 2 so factor of 2 in rate (1/2 mbps) 659 * will divide out 660 */ 661 mac_len = mac_len * 8 * 2; 662 /* calc ceiling of bits/rate = microseconds of air time */ 663 dur = (mac_len + rate - 1) / rate; 664 if (preamble_type & BRCMS_SHORT_PREAMBLE) 665 dur += BPHY_PLCP_SHORT_TIME; 666 else 667 dur += BPHY_PLCP_TIME; 668 } 669 return dur; 670} 671 672static void brcms_c_write_inits(struct brcms_hardware *wlc_hw, 673 const struct d11init *inits) 674{ 675 int i; 676 u8 __iomem *base; 677 u8 __iomem *addr; 678 u16 size; 679 u32 value; 680 681 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit); 682 683 base = (u8 __iomem *)wlc_hw->regs; 684 685 for (i = 0; inits[i].addr != cpu_to_le16(0xffff); i++) { 686 size = le16_to_cpu(inits[i].size); 687 addr = base + le16_to_cpu(inits[i].addr); 688 value = le32_to_cpu(inits[i].value); 689 if (size == 2) 690 W_REG((u16 __iomem *)addr, value); 691 else if (size == 4) 692 W_REG((u32 __iomem *)addr, value); 693 else 694 break; 695 } 696} 697 698static void brcms_c_write_mhf(struct brcms_hardware *wlc_hw, u16 *mhfs) 699{ 700 u8 idx; 701 u16 addr[] = { 702 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4, 703 M_HOST_FLAGS5 704 }; 705 706 for (idx = 0; idx < MHFMAX; idx++) 707 brcms_b_write_shm(wlc_hw, addr[idx], mhfs[idx]); 708} 709 710static void brcms_c_ucode_bsinit(struct brcms_hardware *wlc_hw) 711{ 712 struct wiphy *wiphy = wlc_hw->wlc->wiphy; 713 struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode; 714 715 /* init microcode host flags */ 716 brcms_c_write_mhf(wlc_hw, wlc_hw->band->mhfs); 717 718 /* do band-specific ucode IHR, SHM, and SCR inits */ 719 if (D11REV_IS(wlc_hw->corerev, 23)) { 720 if (BRCMS_ISNPHY(wlc_hw->band)) 721 brcms_c_write_inits(wlc_hw, ucode->d11n0bsinitvals16); 722 else 723 wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev" 724 " %d\n", __func__, wlc_hw->unit, 725 wlc_hw->corerev); 726 } else { 727 if (D11REV_IS(wlc_hw->corerev, 24)) { 728 if (BRCMS_ISLCNPHY(wlc_hw->band)) 729 brcms_c_write_inits(wlc_hw, 730 ucode->d11lcn0bsinitvals24); 731 else 732 wiphy_err(wiphy, "%s: wl%d: unsupported phy in" 733 " core rev %d\n", __func__, 734 wlc_hw->unit, wlc_hw->corerev); 735 } else { 736 wiphy_err(wiphy, "%s: wl%d: unsupported corerev %d\n", 737 __func__, wlc_hw->unit, wlc_hw->corerev); 738 } 739 } 740} 741 742static void brcms_b_core_phy_clk(struct brcms_hardware *wlc_hw, bool clk) 743{ 744 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: clk %d\n", wlc_hw->unit, clk); 745 746 wlc_hw->phyclk = clk; 747 748 if (OFF == clk) { /* clear gmode bit, put phy into reset */ 749 750 ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC | SICF_GMODE), 751 (SICF_PRST | SICF_FGC)); 752 udelay(1); 753 ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_PRST); 754 udelay(1); 755 756 } else { /* take phy out of reset */ 757 758 ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_FGC); 759 udelay(1); 760 ai_core_cflags(wlc_hw->sih, (SICF_FGC), 0); 761 udelay(1); 762 763 } 764} 765 766/* low-level band switch utility routine */ 767static void brcms_c_setxband(struct brcms_hardware *wlc_hw, uint bandunit) 768{ 769 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit, 770 bandunit); 771 772 wlc_hw->band = wlc_hw->bandstate[bandunit]; 773 774 /* 775 * BMAC_NOTE: 776 * until we eliminate need for wlc->band refs in low level code 777 */ 778 wlc_hw->wlc->band = wlc_hw->wlc->bandstate[bandunit]; 779 780 /* set gmode core flag */ 781 if (wlc_hw->sbclk && !wlc_hw->noreset) 782 ai_core_cflags(wlc_hw->sih, SICF_GMODE, 783 ((bandunit == 0) ? SICF_GMODE : 0)); 784} 785 786/* switch to new band but leave it inactive */ 787static u32 brcms_c_setband_inact(struct brcms_c_info *wlc, uint bandunit) 788{ 789 struct brcms_hardware *wlc_hw = wlc->hw; 790 u32 macintmask; 791 792 BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit); 793 794 WARN_ON((R_REG(&wlc_hw->regs->maccontrol) & MCTL_EN_MAC) != 0); 795 796 /* disable interrupts */ 797 macintmask = brcms_intrsoff(wlc->wl); 798 799 /* radio off */ 800 wlc_phy_switch_radio(wlc_hw->band->pi, OFF); 801 802 brcms_b_core_phy_clk(wlc_hw, OFF); 803 804 brcms_c_setxband(wlc_hw, bandunit); 805 806 return macintmask; 807} 808 809/* process an individual struct tx_status */ 810static bool 811brcms_c_dotxstatus(struct brcms_c_info *wlc, struct tx_status *txs) 812{ 813 struct sk_buff *p; 814 uint queue; 815 struct d11txh *txh; 816 struct scb *scb = NULL; 817 bool free_pdu; 818 int tx_rts, tx_frame_count, tx_rts_count; 819 uint totlen, supr_status; 820 bool lastframe; 821 struct ieee80211_hdr *h; 822 u16 mcl; 823 struct ieee80211_tx_info *tx_info; 824 struct ieee80211_tx_rate *txrate; 825 int i; 826 827 /* discard intermediate indications for ucode with one legitimate case: 828 * e.g. if "useRTS" is set. ucode did a successful rts/cts exchange, 829 * but the subsequent tx of DATA failed. so it will start rts/cts 830 * from the beginning (resetting the rts transmission count) 831 */ 832 if (!(txs->status & TX_STATUS_AMPDU) 833 && (txs->status & TX_STATUS_INTERMEDIATE)) { 834 wiphy_err(wlc->wiphy, "%s: INTERMEDIATE but not AMPDU\n", 835 __func__); 836 return false; 837 } 838 839 queue = txs->frameid & TXFID_QUEUE_MASK; 840 if (queue >= NFIFO) { 841 p = NULL; 842 goto fatal; 843 } 844 845 p = dma_getnexttxp(wlc->hw->di[queue], DMA_RANGE_TRANSMITTED); 846 if (p == NULL) 847 goto fatal; 848 849 txh = (struct d11txh *) (p->data); 850 mcl = le16_to_cpu(txh->MacTxControlLow); 851 852 if (txs->phyerr) { 853 if (brcm_msg_level & LOG_ERROR_VAL) { 854 wiphy_err(wlc->wiphy, "phyerr 0x%x, rate 0x%x\n", 855 txs->phyerr, txh->MainRates); 856 brcms_c_print_txdesc(txh); 857 } 858 brcms_c_print_txstatus(txs); 859 } 860 861 if (txs->frameid != le16_to_cpu(txh->TxFrameID)) 862 goto fatal; 863 tx_info = IEEE80211_SKB_CB(p); 864 h = (struct ieee80211_hdr *)((u8 *) (txh + 1) + D11_PHY_HDR_LEN); 865 866 if (tx_info->control.sta) 867 scb = &wlc->pri_scb; 868 869 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) { 870 brcms_c_ampdu_dotxstatus(wlc->ampdu, scb, p, txs); 871 return false; 872 } 873 874 supr_status = txs->status & TX_STATUS_SUPR_MASK; 875 if (supr_status == TX_STATUS_SUPR_BADCH) 876 BCMMSG(wlc->wiphy, 877 "%s: Pkt tx suppressed, possibly channel %d\n", 878 __func__, CHSPEC_CHANNEL(wlc->default_bss->chanspec)); 879 880 tx_rts = le16_to_cpu(txh->MacTxControlLow) & TXC_SENDRTS; 881 tx_frame_count = 882 (txs->status & TX_STATUS_FRM_RTX_MASK) >> TX_STATUS_FRM_RTX_SHIFT; 883 tx_rts_count = 884 (txs->status & TX_STATUS_RTS_RTX_MASK) >> TX_STATUS_RTS_RTX_SHIFT; 885 886 lastframe = !ieee80211_has_morefrags(h->frame_control); 887 888 if (!lastframe) { 889 wiphy_err(wlc->wiphy, "Not last frame!\n"); 890 } else { 891 /* 892 * Set information to be consumed by Minstrel ht. 893 * 894 * The "fallback limit" is the number of tx attempts a given 895 * MPDU is sent at the "primary" rate. Tx attempts beyond that 896 * limit are sent at the "secondary" rate. 897 * A 'short frame' does not exceed RTS treshold. 898 */ 899 u16 sfbl, /* Short Frame Rate Fallback Limit */ 900 lfbl, /* Long Frame Rate Fallback Limit */ 901 fbl; 902 903 if (queue < IEEE80211_NUM_ACS) { 904 sfbl = GFIELD(wlc->wme_retries[wme_fifo2ac[queue]], 905 EDCF_SFB); 906 lfbl = GFIELD(wlc->wme_retries[wme_fifo2ac[queue]], 907 EDCF_LFB); 908 } else { 909 sfbl = wlc->SFBL; 910 lfbl = wlc->LFBL; 911 } 912 913 txrate = tx_info->status.rates; 914 if (txrate[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) 915 fbl = lfbl; 916 else 917 fbl = sfbl; 918 919 ieee80211_tx_info_clear_status(tx_info); 920 921 if ((tx_frame_count > fbl) && (txrate[1].idx >= 0)) { 922 /* 923 * rate selection requested a fallback rate 924 * and we used it 925 */ 926 txrate[0].count = fbl; 927 txrate[1].count = tx_frame_count - fbl; 928 } else { 929 /* 930 * rate selection did not request fallback rate, or 931 * we didn't need it 932 */ 933 txrate[0].count = tx_frame_count; 934 /* 935 * rc80211_minstrel.c:minstrel_tx_status() expects 936 * unused rates to be marked with idx = -1 937 */ 938 txrate[1].idx = -1; 939 txrate[1].count = 0; 940 } 941 942 /* clear the rest of the rates */ 943 for (i = 2; i < IEEE80211_TX_MAX_RATES; i++) { 944 txrate[i].idx = -1; 945 txrate[i].count = 0; 946 } 947 948 if (txs->status & TX_STATUS_ACK_RCV) 949 tx_info->flags |= IEEE80211_TX_STAT_ACK; 950 } 951 952 totlen = p->len; 953 free_pdu = true; 954 955 brcms_c_txfifo_complete(wlc, queue, 1); 956 957 if (lastframe) { 958 p->next = NULL; 959 p->prev = NULL; 960 /* remove PLCP & Broadcom tx descriptor header */ 961 skb_pull(p, D11_PHY_HDR_LEN); 962 skb_pull(p, D11_TXH_LEN); 963 ieee80211_tx_status_irqsafe(wlc->pub->ieee_hw, p); 964 } else { 965 wiphy_err(wlc->wiphy, "%s: Not last frame => not calling " 966 "tx_status\n", __func__); 967 } 968 969 return false; 970 971 fatal: 972 if (p) 973 brcmu_pkt_buf_free_skb(p); 974 975 return true; 976 977} 978 979/* process tx completion events in BMAC 980 * Return true if more tx status need to be processed. false otherwise. 981 */ 982static bool 983brcms_b_txstatus(struct brcms_hardware *wlc_hw, bool bound, bool *fatal) 984{ 985 bool morepending = false; 986 struct brcms_c_info *wlc = wlc_hw->wlc; 987 struct d11regs __iomem *regs; 988 struct tx_status txstatus, *txs; 989 u32 s1, s2; 990 uint n = 0; 991 /* 992 * Param 'max_tx_num' indicates max. # tx status to process before 993 * break out. 994 */ 995 uint max_tx_num = bound ? TXSBND : -1; 996 997 BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit); 998 999 txs = &txstatus; 1000 regs = wlc_hw->regs; 1001 *fatal = false; 1002 while (!(*fatal) 1003 && (s1 = R_REG(®s->frmtxstatus)) & TXS_V) { 1004 1005 if (s1 == 0xffffffff) { 1006 wiphy_err(wlc->wiphy, "wl%d: %s: dead chip\n", 1007 wlc_hw->unit, __func__); 1008 return morepending; 1009 } 1010 1011 s2 = R_REG(®s->frmtxstatus2); 1012 1013 txs->status = s1 & TXS_STATUS_MASK; 1014 txs->frameid = (s1 & TXS_FID_MASK) >> TXS_FID_SHIFT; 1015 txs->sequence = s2 & TXS_SEQ_MASK; 1016 txs->phyerr = (s2 & TXS_PTX_MASK) >> TXS_PTX_SHIFT; 1017 txs->lasttxtime = 0; 1018 1019 *fatal = brcms_c_dotxstatus(wlc_hw->wlc, txs); 1020 1021 /* !give others some time to run! */ 1022 if (++n >= max_tx_num) 1023 break; 1024 } 1025 1026 if (*fatal) 1027 return 0; 1028 1029 if (n >= max_tx_num) 1030 morepending = true; 1031 1032 if (!pktq_empty(&wlc->pkt_queue->q)) 1033 brcms_c_send_q(wlc); 1034 1035 return morepending; 1036} 1037 1038static void brcms_c_tbtt(struct brcms_c_info *wlc) 1039{ 1040 if (!wlc->bsscfg->BSS) 1041 /* 1042 * DirFrmQ is now valid...defer setting until end 1043 * of ATIM window 1044 */ 1045 wlc->qvalid |= MCMD_DIRFRMQVAL; 1046} 1047 1048/* set initial host flags value */ 1049static void 1050brcms_c_mhfdef(struct brcms_c_info *wlc, u16 *mhfs, u16 mhf2_init) 1051{ 1052 struct brcms_hardware *wlc_hw = wlc->hw; 1053 1054 memset(mhfs, 0, MHFMAX * sizeof(u16)); 1055 1056 mhfs[MHF2] |= mhf2_init; 1057 1058 /* prohibit use of slowclock on multifunction boards */ 1059 if (wlc_hw->boardflags & BFL_NOPLLDOWN) 1060 mhfs[MHF1] |= MHF1_FORCEFASTCLK; 1061 1062 if (BRCMS_ISNPHY(wlc_hw->band) && NREV_LT(wlc_hw->band->phyrev, 2)) { 1063 mhfs[MHF2] |= MHF2_NPHY40MHZ_WAR; 1064 mhfs[MHF1] |= MHF1_IQSWAP_WAR; 1065 } 1066} 1067 1068static struct dma64regs __iomem * 1069dmareg(struct brcms_hardware *hw, uint direction, uint fifonum) 1070{ 1071 if (direction == DMA_TX) 1072 return &(hw->regs->fifo64regs[fifonum].dmaxmt); 1073 return &(hw->regs->fifo64regs[fifonum].dmarcv); 1074} 1075 1076static bool brcms_b_attach_dmapio(struct brcms_c_info *wlc, uint j, bool wme) 1077{ 1078 uint i; 1079 char name[8]; 1080 /* 1081 * ucode host flag 2 needed for pio mode, independent of band and fifo 1082 */ 1083 u16 pio_mhf2 = 0; 1084 struct brcms_hardware *wlc_hw = wlc->hw; 1085 uint unit = wlc_hw->unit; 1086 struct wiphy *wiphy = wlc->wiphy; 1087 1088 /* name and offsets for dma_attach */ 1089 snprintf(name, sizeof(name), "wl%d", unit); 1090 1091 if (wlc_hw->di[0] == NULL) { /* Init FIFOs */ 1092 int dma_attach_err = 0; 1093 1094 /* 1095 * FIFO 0 1096 * TX: TX_AC_BK_FIFO (TX AC Background data packets) 1097 * RX: RX_FIFO (RX data packets) 1098 */ 1099 wlc_hw->di[0] = dma_attach(name, wlc_hw->sih, 1100 (wme ? dmareg(wlc_hw, DMA_TX, 0) : 1101 NULL), dmareg(wlc_hw, DMA_RX, 0), 1102 (wme ? NTXD : 0), NRXD, 1103 RXBUFSZ, -1, NRXBUFPOST, 1104 BRCMS_HWRXOFF, &brcm_msg_level); 1105 dma_attach_err |= (NULL == wlc_hw->di[0]); 1106 1107 /* 1108 * FIFO 1 1109 * TX: TX_AC_BE_FIFO (TX AC Best-Effort data packets) 1110 * (legacy) TX_DATA_FIFO (TX data packets) 1111 * RX: UNUSED 1112 */ 1113 wlc_hw->di[1] = dma_attach(name, wlc_hw->sih, 1114 dmareg(wlc_hw, DMA_TX, 1), NULL, 1115 NTXD, 0, 0, -1, 0, 0, 1116 &brcm_msg_level); 1117 dma_attach_err |= (NULL == wlc_hw->di[1]); 1118 1119 /* 1120 * FIFO 2 1121 * TX: TX_AC_VI_FIFO (TX AC Video data packets) 1122 * RX: UNUSED 1123 */ 1124 wlc_hw->di[2] = dma_attach(name, wlc_hw->sih, 1125 dmareg(wlc_hw, DMA_TX, 2), NULL, 1126 NTXD, 0, 0, -1, 0, 0, 1127 &brcm_msg_level); 1128 dma_attach_err |= (NULL == wlc_hw->di[2]); 1129 /* 1130 * FIFO 3 1131 * TX: TX_AC_VO_FIFO (TX AC Voice data packets) 1132 * (legacy) TX_CTL_FIFO (TX control & mgmt packets) 1133 */ 1134 wlc_hw->di[3] = dma_attach(name, wlc_hw->sih, 1135 dmareg(wlc_hw, DMA_TX, 3), 1136 NULL, NTXD, 0, 0, -1, 1137 0, 0, &brcm_msg_level); 1138 dma_attach_err |= (NULL == wlc_hw->di[3]); 1139/* Cleaner to leave this as if with AP defined */ 1140 1141 if (dma_attach_err) { 1142 wiphy_err(wiphy, "wl%d: wlc_attach: dma_attach failed" 1143 "\n", unit); 1144 return false; 1145 } 1146 1147 /* get pointer to dma engine tx flow control variable */ 1148 for (i = 0; i < NFIFO; i++) 1149 if (wlc_hw->di[i]) 1150 wlc_hw->txavail[i] = 1151 (uint *) dma_getvar(wlc_hw->di[i], 1152 "&txavail"); 1153 } 1154 1155 /* initial ucode host flags */ 1156 brcms_c_mhfdef(wlc, wlc_hw->band->mhfs, pio_mhf2); 1157 1158 return true; 1159} 1160 1161static void brcms_b_detach_dmapio(struct brcms_hardware *wlc_hw) 1162{ 1163 uint j; 1164 1165 for (j = 0; j < NFIFO; j++) { 1166 if (wlc_hw->di[j]) { 1167 dma_detach(wlc_hw->di[j]); 1168 wlc_hw->di[j] = NULL; 1169 } 1170 } 1171} 1172 1173/* 1174 * Initialize brcms_c_info default values ... 1175 * may get overrides later in this function 1176 * BMAC_NOTES, move low out and resolve the dangling ones 1177 */ 1178static void brcms_b_info_init(struct brcms_hardware *wlc_hw) 1179{ 1180 struct brcms_c_info *wlc = wlc_hw->wlc; 1181 1182 /* set default sw macintmask value */ 1183 wlc->defmacintmask = DEF_MACINTMASK; 1184 1185 /* various 802.11g modes */ 1186 wlc_hw->shortslot = false; 1187 1188 wlc_hw->SFBL = RETRY_SHORT_FB; 1189 wlc_hw->LFBL = RETRY_LONG_FB; 1190 1191 /* default mac retry limits */ 1192 wlc_hw->SRL = RETRY_SHORT_DEF; 1193 wlc_hw->LRL = RETRY_LONG_DEF; 1194 wlc_hw->chanspec = ch20mhz_chspec(1); 1195} 1196 1197static void brcms_b_wait_for_wake(struct brcms_hardware *wlc_hw) 1198{ 1199 /* delay before first read of ucode state */ 1200 udelay(40); 1201 1202 /* wait until ucode is no longer asleep */ 1203 SPINWAIT((brcms_b_read_shm(wlc_hw, M_UCODE_DBGST) == 1204 DBGST_ASLEEP), wlc_hw->wlc->fastpwrup_dly); 1205} 1206 1207/* control chip clock to save power, enable dynamic clock or force fast clock */ 1208static void brcms_b_clkctl_clk(struct brcms_hardware *wlc_hw, uint mode) 1209{ 1210 if (wlc_hw->sih->cccaps & CC_CAP_PMU) { 1211 /* new chips with PMU, CCS_FORCEHT will distribute the HT clock 1212 * on backplane, but mac core will still run on ALP(not HT) when 1213 * it enters powersave mode, which means the FCA bit may not be 1214 * set. Should wakeup mac if driver wants it to run on HT. 1215 */ 1216 1217 if (wlc_hw->clk) { 1218 if (mode == CLK_FAST) { 1219 OR_REG(&wlc_hw->regs->clk_ctl_st, 1220 CCS_FORCEHT); 1221 1222 udelay(64); 1223 1224 SPINWAIT(((R_REG 1225 (&wlc_hw->regs-> 1226 clk_ctl_st) & CCS_HTAVAIL) == 0), 1227 PMU_MAX_TRANSITION_DLY); 1228 WARN_ON(!(R_REG 1229 (&wlc_hw->regs-> 1230 clk_ctl_st) & CCS_HTAVAIL)); 1231 } else { 1232 if ((wlc_hw->sih->pmurev == 0) && 1233 (R_REG 1234 (&wlc_hw->regs-> 1235 clk_ctl_st) & (CCS_FORCEHT | CCS_HTAREQ))) 1236 SPINWAIT(((R_REG 1237 (&wlc_hw->regs-> 1238 clk_ctl_st) & CCS_HTAVAIL) 1239 == 0), 1240 PMU_MAX_TRANSITION_DLY); 1241 AND_REG(&wlc_hw->regs->clk_ctl_st, 1242 ~CCS_FORCEHT); 1243 } 1244 } 1245 wlc_hw->forcefastclk = (mode == CLK_FAST); 1246 } else { 1247 1248 /* old chips w/o PMU, force HT through cc, 1249 * then use FCA to verify mac is running fast clock 1250 */ 1251 1252 wlc_hw->forcefastclk = ai_clkctl_cc(wlc_hw->sih, mode); 1253 1254 /* check fast clock is available (if core is not in reset) */ 1255 if (wlc_hw->forcefastclk && wlc_hw->clk) 1256 WARN_ON(!(ai_core_sflags(wlc_hw->sih, 0, 0) & 1257 SISF_FCLKA)); 1258 1259 /* 1260 * keep the ucode wake bit on if forcefastclk is on since we 1261 * do not want ucode to put us back to slow clock when it dozes 1262 * for PM mode. Code below matches the wake override bit with 1263 * current forcefastclk state. Only setting bit in wake_override 1264 * instead of waking ucode immediately since old code had this 1265 * behavior. Older code set wlc->forcefastclk but only had the 1266 * wake happen if the wakup_ucode work (protected by an up 1267 * check) was executed just below. 1268 */ 1269 if (wlc_hw->forcefastclk) 1270 mboolset(wlc_hw->wake_override, 1271 BRCMS_WAKE_OVERRIDE_FORCEFAST); 1272 else 1273 mboolclr(wlc_hw->wake_override, 1274 BRCMS_WAKE_OVERRIDE_FORCEFAST); 1275 } 1276} 1277 1278/* set or clear ucode host flag bits 1279 * it has an optimization for no-change write 1280 * it only writes through shared memory when the core has clock; 1281 * pre-CLK changes should use wlc_write_mhf to get around the optimization 1282 * 1283 * 1284 * bands values are: BRCM_BAND_AUTO <--- Current band only 1285 * BRCM_BAND_5G <--- 5G band only 1286 * BRCM_BAND_2G <--- 2G band only 1287 * BRCM_BAND_ALL <--- All bands 1288 */ 1289void 1290brcms_b_mhf(struct brcms_hardware *wlc_hw, u8 idx, u16 mask, u16 val, 1291 int bands) 1292{ 1293 u16 save; 1294 u16 addr[MHFMAX] = { 1295 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4, 1296 M_HOST_FLAGS5 1297 }; 1298 struct brcms_hw_band *band; 1299 1300 if ((val & ~mask) || idx >= MHFMAX) 1301 return; /* error condition */ 1302 1303 switch (bands) { 1304 /* Current band only or all bands, 1305 * then set the band to current band 1306 */ 1307 case BRCM_BAND_AUTO: 1308 case BRCM_BAND_ALL: 1309 band = wlc_hw->band; 1310 break; 1311 case BRCM_BAND_5G: 1312 band = wlc_hw->bandstate[BAND_5G_INDEX]; 1313 break; 1314 case BRCM_BAND_2G: 1315 band = wlc_hw->bandstate[BAND_2G_INDEX]; 1316 break; 1317 default: 1318 band = NULL; /* error condition */ 1319 } 1320 1321 if (band) { 1322 save = band->mhfs[idx]; 1323 band->mhfs[idx] = (band->mhfs[idx] & ~mask) | val; 1324 1325 /* optimization: only write through if changed, and 1326 * changed band is the current band 1327 */ 1328 if (wlc_hw->clk && (band->mhfs[idx] != save) 1329 && (band == wlc_hw->band)) 1330 brcms_b_write_shm(wlc_hw, addr[idx], 1331 (u16) band->mhfs[idx]); 1332 } 1333 1334 if (bands == BRCM_BAND_ALL) { 1335 wlc_hw->bandstate[0]->mhfs[idx] = 1336 (wlc_hw->bandstate[0]->mhfs[idx] & ~mask) | val; 1337 wlc_hw->bandstate[1]->mhfs[idx] = 1338 (wlc_hw->bandstate[1]->mhfs[idx] & ~mask) | val; 1339 } 1340} 1341 1342/* set the maccontrol register to desired reset state and 1343 * initialize the sw cache of the register 1344 */ 1345static void brcms_c_mctrl_reset(struct brcms_hardware *wlc_hw) 1346{ 1347 /* IHR accesses are always enabled, PSM disabled, HPS off and WAKE on */ 1348 wlc_hw->maccontrol = 0; 1349 wlc_hw->suspended_fifos = 0; 1350 wlc_hw->wake_override = 0; 1351 wlc_hw->mute_override = 0; 1352 brcms_b_mctrl(wlc_hw, ~0, MCTL_IHR_EN | MCTL_WAKE); 1353} 1354 1355/* 1356 * write the software state of maccontrol and 1357 * overrides to the maccontrol register 1358 */ 1359static void brcms_c_mctrl_write(struct brcms_hardware *wlc_hw) 1360{ 1361 u32 maccontrol = wlc_hw->maccontrol; 1362 1363 /* OR in the wake bit if overridden */ 1364 if (wlc_hw->wake_override) 1365 maccontrol |= MCTL_WAKE; 1366 1367 /* set AP and INFRA bits for mute if needed */ 1368 if (wlc_hw->mute_override) { 1369 maccontrol &= ~(MCTL_AP); 1370 maccontrol |= MCTL_INFRA; 1371 } 1372 1373 W_REG(&wlc_hw->regs->maccontrol, maccontrol); 1374} 1375 1376/* set or clear maccontrol bits */ 1377void brcms_b_mctrl(struct brcms_hardware *wlc_hw, u32 mask, u32 val) 1378{ 1379 u32 maccontrol; 1380 u32 new_maccontrol; 1381 1382 if (val & ~mask) 1383 return; /* error condition */ 1384 maccontrol = wlc_hw->maccontrol; 1385 new_maccontrol = (maccontrol & ~mask) | val; 1386 1387 /* if the new maccontrol value is the same as the old, nothing to do */ 1388 if (new_maccontrol == maccontrol) 1389 return; 1390 1391 /* something changed, cache the new value */ 1392 wlc_hw->maccontrol = new_maccontrol; 1393 1394 /* write the new values with overrides applied */ 1395 brcms_c_mctrl_write(wlc_hw); 1396} 1397 1398void brcms_c_ucode_wake_override_set(struct brcms_hardware *wlc_hw, 1399 u32 override_bit) 1400{ 1401 if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE)) { 1402 mboolset(wlc_hw->wake_override, override_bit); 1403 return; 1404 } 1405 1406 mboolset(wlc_hw->wake_override, override_bit); 1407 1408 brcms_c_mctrl_write(wlc_hw); 1409 brcms_b_wait_for_wake(wlc_hw); 1410} 1411 1412void brcms_c_ucode_wake_override_clear(struct brcms_hardware *wlc_hw, 1413 u32 override_bit) 1414{ 1415 mboolclr(wlc_hw->wake_override, override_bit); 1416 1417 if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE)) 1418 return; 1419 1420 brcms_c_mctrl_write(wlc_hw); 1421} 1422 1423/* When driver needs ucode to stop beaconing, it has to make sure that 1424 * MCTL_AP is clear and MCTL_INFRA is set 1425 * Mode MCTL_AP MCTL_INFRA 1426 * AP 1 1 1427 * STA 0 1 <--- This will ensure no beacons 1428 * IBSS 0 0 1429 */ 1430static void brcms_c_ucode_mute_override_set(struct brcms_hardware *wlc_hw) 1431{ 1432 wlc_hw->mute_override = 1; 1433 1434 /* if maccontrol already has AP == 0 and INFRA == 1 without this 1435 * override, then there is no change to write 1436 */ 1437 if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA) 1438 return; 1439 1440 brcms_c_mctrl_write(wlc_hw); 1441} 1442 1443/* Clear the override on AP and INFRA bits */ 1444static void brcms_c_ucode_mute_override_clear(struct brcms_hardware *wlc_hw) 1445{ 1446 if (wlc_hw->mute_override == 0) 1447 return; 1448 1449 wlc_hw->mute_override = 0; 1450 1451 /* if maccontrol already has AP == 0 and INFRA == 1 without this 1452 * override, then there is no change to write 1453 */ 1454 if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA) 1455 return; 1456 1457 brcms_c_mctrl_write(wlc_hw); 1458} 1459 1460/* 1461 * Write a MAC address to the given match reg offset in the RXE match engine. 1462 */ 1463static void 1464brcms_b_set_addrmatch(struct brcms_hardware *wlc_hw, int match_reg_offset, 1465 const u8 *addr) 1466{ 1467 struct d11regs __iomem *regs; 1468 u16 mac_l; 1469 u16 mac_m; 1470 u16 mac_h; 1471 1472 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: brcms_b_set_addrmatch\n", 1473 wlc_hw->unit); 1474 1475 regs = wlc_hw->regs; 1476 mac_l = addr[0] | (addr[1] << 8); 1477 mac_m = addr[2] | (addr[3] << 8); 1478 mac_h = addr[4] | (addr[5] << 8); 1479 1480 /* enter the MAC addr into the RXE match registers */ 1481 W_REG(®s->rcm_ctl, RCM_INC_DATA | match_reg_offset); 1482 W_REG(®s->rcm_mat_data, mac_l); 1483 W_REG(®s->rcm_mat_data, mac_m); 1484 W_REG(®s->rcm_mat_data, mac_h); 1485 1486} 1487 1488void 1489brcms_b_write_template_ram(struct brcms_hardware *wlc_hw, int offset, int len, 1490 void *buf) 1491{ 1492 struct d11regs __iomem *regs; 1493 u32 word; 1494 __le32 word_le; 1495 __be32 word_be; 1496 bool be_bit; 1497 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit); 1498 1499 regs = wlc_hw->regs; 1500 W_REG(®s->tplatewrptr, offset); 1501 1502 /* if MCTL_BIGEND bit set in mac control register, 1503 * the chip swaps data in fifo, as well as data in 1504 * template ram 1505 */ 1506 be_bit = (R_REG(®s->maccontrol) & MCTL_BIGEND) != 0; 1507 1508 while (len > 0) { 1509 memcpy(&word, buf, sizeof(u32)); 1510 1511 if (be_bit) { 1512 word_be = cpu_to_be32(word); 1513 word = *(u32 *)&word_be; 1514 } else { 1515 word_le = cpu_to_le32(word); 1516 word = *(u32 *)&word_le; 1517 } 1518 1519 W_REG(®s->tplatewrdata, word); 1520 1521 buf = (u8 *) buf + sizeof(u32); 1522 len -= sizeof(u32); 1523 } 1524} 1525 1526static void brcms_b_set_cwmin(struct brcms_hardware *wlc_hw, u16 newmin) 1527{ 1528 wlc_hw->band->CWmin = newmin; 1529 1530 W_REG(&wlc_hw->regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_CWMIN); 1531 (void)R_REG(&wlc_hw->regs->objaddr); 1532 W_REG(&wlc_hw->regs->objdata, newmin); 1533} 1534 1535static void brcms_b_set_cwmax(struct brcms_hardware *wlc_hw, u16 newmax) 1536{ 1537 wlc_hw->band->CWmax = newmax; 1538 1539 W_REG(&wlc_hw->regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_CWMAX); 1540 (void)R_REG(&wlc_hw->regs->objaddr); 1541 W_REG(&wlc_hw->regs->objdata, newmax); 1542} 1543 1544void brcms_b_bw_set(struct brcms_hardware *wlc_hw, u16 bw) 1545{ 1546 bool fastclk; 1547 1548 /* request FAST clock if not on */ 1549 fastclk = wlc_hw->forcefastclk; 1550 if (!fastclk) 1551 brcms_b_clkctl_clk(wlc_hw, CLK_FAST); 1552 1553 wlc_phy_bw_state_set(wlc_hw->band->pi, bw); 1554 1555 brcms_b_phy_reset(wlc_hw); 1556 wlc_phy_init(wlc_hw->band->pi, wlc_phy_chanspec_get(wlc_hw->band->pi)); 1557 1558 /* restore the clk */ 1559 if (!fastclk) 1560 brcms_b_clkctl_clk(wlc_hw, CLK_DYNAMIC); 1561} 1562 1563static void brcms_b_upd_synthpu(struct brcms_hardware *wlc_hw) 1564{ 1565 u16 v; 1566 struct brcms_c_info *wlc = wlc_hw->wlc; 1567 /* update SYNTHPU_DLY */ 1568 1569 if (BRCMS_ISLCNPHY(wlc->band)) 1570 v = SYNTHPU_DLY_LPPHY_US; 1571 else if (BRCMS_ISNPHY(wlc->band) && (NREV_GE(wlc->band->phyrev, 3))) 1572 v = SYNTHPU_DLY_NPHY_US; 1573 else 1574 v = SYNTHPU_DLY_BPHY_US; 1575 1576 brcms_b_write_shm(wlc_hw, M_SYNTHPU_DLY, v); 1577} 1578 1579static void brcms_c_ucode_txant_set(struct brcms_hardware *wlc_hw) 1580{ 1581 u16 phyctl; 1582 u16 phytxant = wlc_hw->bmac_phytxant; 1583 u16 mask = PHY_TXC_ANT_MASK; 1584 1585 /* set the Probe Response frame phy control word */ 1586 phyctl = brcms_b_read_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS); 1587 phyctl = (phyctl & ~mask) | phytxant; 1588 brcms_b_write_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS, phyctl); 1589 1590 /* set the Response (ACK/CTS) frame phy control word */ 1591 phyctl = brcms_b_read_shm(wlc_hw, M_RSP_PCTLWD); 1592 phyctl = (phyctl & ~mask) | phytxant; 1593 brcms_b_write_shm(wlc_hw, M_RSP_PCTLWD, phyctl); 1594} 1595 1596static u16 brcms_b_ofdm_ratetable_offset(struct brcms_hardware *wlc_hw, 1597 u8 rate) 1598{ 1599 uint i; 1600 u8 plcp_rate = 0; 1601 struct plcp_signal_rate_lookup { 1602 u8 rate; 1603 u8 signal_rate; 1604 }; 1605 /* OFDM RATE sub-field of PLCP SIGNAL field, per 802.11 sec 17.3.4.1 */ 1606 const struct plcp_signal_rate_lookup rate_lookup[] = { 1607 {BRCM_RATE_6M, 0xB}, 1608 {BRCM_RATE_9M, 0xF}, 1609 {BRCM_RATE_12M, 0xA}, 1610 {BRCM_RATE_18M, 0xE}, 1611 {BRCM_RATE_24M, 0x9}, 1612 {BRCM_RATE_36M, 0xD}, 1613 {BRCM_RATE_48M, 0x8}, 1614 {BRCM_RATE_54M, 0xC} 1615 }; 1616 1617 for (i = 0; i < ARRAY_SIZE(rate_lookup); i++) { 1618 if (rate == rate_lookup[i].rate) { 1619 plcp_rate = rate_lookup[i].signal_rate; 1620 break; 1621 } 1622 } 1623 1624 /* Find the SHM pointer to the rate table entry by looking in the 1625 * Direct-map Table 1626 */ 1627 return 2 * brcms_b_read_shm(wlc_hw, M_RT_DIRMAP_A + (plcp_rate * 2)); 1628} 1629 1630static void brcms_upd_ofdm_pctl1_table(struct brcms_hardware *wlc_hw) 1631{ 1632 u8 rate; 1633 u8 rates[8] = { 1634 BRCM_RATE_6M, BRCM_RATE_9M, BRCM_RATE_12M, BRCM_RATE_18M, 1635 BRCM_RATE_24M, BRCM_RATE_36M, BRCM_RATE_48M, BRCM_RATE_54M 1636 }; 1637 u16 entry_ptr; 1638 u16 pctl1; 1639 uint i; 1640 1641 if (!BRCMS_PHY_11N_CAP(wlc_hw->band)) 1642 return; 1643 1644 /* walk the phy rate table and update the entries */ 1645 for (i = 0; i < ARRAY_SIZE(rates); i++) { 1646 rate = rates[i]; 1647 1648 entry_ptr = brcms_b_ofdm_ratetable_offset(wlc_hw, rate); 1649 1650 /* read the SHM Rate Table entry OFDM PCTL1 values */ 1651 pctl1 = 1652 brcms_b_read_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS); 1653 1654 /* modify the value */ 1655 pctl1 &= ~PHY_TXC1_MODE_MASK; 1656 pctl1 |= (wlc_hw->hw_stf_ss_opmode << PHY_TXC1_MODE_SHIFT); 1657 1658 /* Update the SHM Rate Table entry OFDM PCTL1 values */ 1659 brcms_b_write_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS, 1660 pctl1); 1661 } 1662} 1663 1664/* band-specific init */ 1665static void brcms_b_bsinit(struct brcms_c_info *wlc, u16 chanspec) 1666{ 1667 struct brcms_hardware *wlc_hw = wlc->hw; 1668 1669 BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit, 1670 wlc_hw->band->bandunit); 1671 1672 brcms_c_ucode_bsinit(wlc_hw); 1673 1674 wlc_phy_init(wlc_hw->band->pi, chanspec); 1675 1676 brcms_c_ucode_txant_set(wlc_hw); 1677 1678 /* 1679 * cwmin is band-specific, update hardware 1680 * with value for current band 1681 */ 1682 brcms_b_set_cwmin(wlc_hw, wlc_hw->band->CWmin); 1683 brcms_b_set_cwmax(wlc_hw, wlc_hw->band->CWmax); 1684 1685 brcms_b_update_slot_timing(wlc_hw, 1686 wlc_hw->band->bandtype == BRCM_BAND_5G ? 1687 true : wlc_hw->shortslot); 1688 1689 /* write phytype and phyvers */ 1690 brcms_b_write_shm(wlc_hw, M_PHYTYPE, (u16) wlc_hw->band->phytype); 1691 brcms_b_write_shm(wlc_hw, M_PHYVER, (u16) wlc_hw->band->phyrev); 1692 1693 /* 1694 * initialize the txphyctl1 rate table since 1695 * shmem is shared between bands 1696 */ 1697 brcms_upd_ofdm_pctl1_table(wlc_hw); 1698 1699 brcms_b_upd_synthpu(wlc_hw); 1700} 1701 1702/* Perform a soft reset of the PHY PLL */ 1703void brcms_b_core_phypll_reset(struct brcms_hardware *wlc_hw) 1704{ 1705 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit); 1706 1707 ai_corereg(wlc_hw->sih, SI_CC_IDX, 1708 offsetof(struct chipcregs, chipcontrol_addr), ~0, 0); 1709 udelay(1); 1710 ai_corereg(wlc_hw->sih, SI_CC_IDX, 1711 offsetof(struct chipcregs, chipcontrol_data), 0x4, 0); 1712 udelay(1); 1713 ai_corereg(wlc_hw->sih, SI_CC_IDX, 1714 offsetof(struct chipcregs, chipcontrol_data), 0x4, 4); 1715 udelay(1); 1716 ai_corereg(wlc_hw->sih, SI_CC_IDX, 1717 offsetof(struct chipcregs, chipcontrol_data), 0x4, 0); 1718 udelay(1); 1719} 1720 1721/* light way to turn on phy clock without reset for NPHY only 1722 * refer to brcms_b_core_phy_clk for full version 1723 */ 1724void brcms_b_phyclk_fgc(struct brcms_hardware *wlc_hw, bool clk) 1725{ 1726 /* support(necessary for NPHY and HYPHY) only */ 1727 if (!BRCMS_ISNPHY(wlc_hw->band)) 1728 return; 1729 1730 if (ON == clk) 1731 ai_core_cflags(wlc_hw->sih, SICF_FGC, SICF_FGC); 1732 else 1733 ai_core_cflags(wlc_hw->sih, SICF_FGC, 0); 1734 1735} 1736 1737void brcms_b_macphyclk_set(struct brcms_hardware *wlc_hw, bool clk) 1738{ 1739 if (ON == clk) 1740 ai_core_cflags(wlc_hw->sih, SICF_MPCLKE, SICF_MPCLKE); 1741 else 1742 ai_core_cflags(wlc_hw->sih, SICF_MPCLKE, 0); 1743} 1744 1745void brcms_b_phy_reset(struct brcms_hardware *wlc_hw) 1746{ 1747 struct brcms_phy_pub *pih = wlc_hw->band->pi; 1748 u32 phy_bw_clkbits; 1749 bool phy_in_reset = false; 1750 1751 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit); 1752 1753 if (pih == NULL) 1754 return; 1755 1756 phy_bw_clkbits = wlc_phy_clk_bwbits(wlc_hw->band->pi); 1757 1758 /* Specific reset sequence required for NPHY rev 3 and 4 */ 1759 if (BRCMS_ISNPHY(wlc_hw->band) && NREV_GE(wlc_hw->band->phyrev, 3) && 1760 NREV_LE(wlc_hw->band->phyrev, 4)) { 1761 /* Set the PHY bandwidth */ 1762 ai_core_cflags(wlc_hw->sih, SICF_BWMASK, phy_bw_clkbits); 1763 1764 udelay(1); 1765 1766 /* Perform a soft reset of the PHY PLL */ 1767 brcms_b_core_phypll_reset(wlc_hw); 1768 1769 /* reset the PHY */ 1770 ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_PCLKE), 1771 (SICF_PRST | SICF_PCLKE)); 1772 phy_in_reset = true; 1773 } else { 1774 ai_core_cflags(wlc_hw->sih, 1775 (SICF_PRST | SICF_PCLKE | SICF_BWMASK), 1776 (SICF_PRST | SICF_PCLKE | phy_bw_clkbits)); 1777 } 1778 1779 udelay(2); 1780 brcms_b_core_phy_clk(wlc_hw, ON); 1781 1782 if (pih) 1783 wlc_phy_anacore(pih, ON); 1784} 1785 1786/* switch to and initialize new band */ 1787static void brcms_b_setband(struct brcms_hardware *wlc_hw, uint bandunit, 1788 u16 chanspec) { 1789 struct brcms_c_info *wlc = wlc_hw->wlc; 1790 u32 macintmask; 1791 1792 /* Enable the d11 core before accessing it */ 1793 if (!ai_iscoreup(wlc_hw->sih)) { 1794 ai_core_reset(wlc_hw->sih, 0, 0); 1795 brcms_c_mctrl_reset(wlc_hw); 1796 } 1797 1798 macintmask = brcms_c_setband_inact(wlc, bandunit); 1799 1800 if (!wlc_hw->up) 1801 return; 1802 1803 brcms_b_core_phy_clk(wlc_hw, ON); 1804 1805 /* band-specific initializations */ 1806 brcms_b_bsinit(wlc, chanspec); 1807 1808 /* 1809 * If there are any pending software interrupt bits, 1810 * then replace these with a harmless nonzero value 1811 * so brcms_c_dpc() will re-enable interrupts when done. 1812 */ 1813 if (wlc->macintstatus) 1814 wlc->macintstatus = MI_DMAINT; 1815 1816 /* restore macintmask */ 1817 brcms_intrsrestore(wlc->wl, macintmask); 1818 1819 /* ucode should still be suspended.. */ 1820 WARN_ON((R_REG(&wlc_hw->regs->maccontrol) & MCTL_EN_MAC) != 0); 1821} 1822 1823static bool brcms_c_isgoodchip(struct brcms_hardware *wlc_hw) 1824{ 1825 1826 /* reject unsupported corerev */ 1827 if (!CONF_HAS(D11CONF, wlc_hw->corerev)) { 1828 wiphy_err(wlc_hw->wlc->wiphy, "unsupported core rev %d\n", 1829 wlc_hw->corerev); 1830 return false; 1831 } 1832 1833 return true; 1834} 1835 1836/* Validate some board info parameters */ 1837static bool brcms_c_validboardtype(struct brcms_hardware *wlc_hw) 1838{ 1839 uint boardrev = wlc_hw->boardrev; 1840 1841 /* 4 bits each for board type, major, minor, and tiny version */ 1842 uint brt = (boardrev & 0xf000) >> 12; 1843 uint b0 = (boardrev & 0xf00) >> 8; 1844 uint b1 = (boardrev & 0xf0) >> 4; 1845 uint b2 = boardrev & 0xf; 1846 1847 /* voards from other vendors are always considered valid */ 1848 if (wlc_hw->sih->boardvendor != PCI_VENDOR_ID_BROADCOM) 1849 return true; 1850 1851 /* do some boardrev sanity checks when boardvendor is Broadcom */ 1852 if (boardrev == 0) 1853 return false; 1854 1855 if (boardrev <= 0xff) 1856 return true; 1857 1858 if ((brt > 2) || (brt == 0) || (b0 > 9) || (b0 == 0) || (b1 > 9) 1859 || (b2 > 9)) 1860 return false; 1861 1862 return true; 1863} 1864 1865static char *brcms_c_get_macaddr(struct brcms_hardware *wlc_hw) 1866{ 1867 enum brcms_srom_id var_id = BRCMS_SROM_MACADDR; 1868 char *macaddr; 1869 1870 /* If macaddr exists, use it (Sromrev4, CIS, ...). */ 1871 macaddr = getvar(wlc_hw->sih, var_id); 1872 if (macaddr != NULL) 1873 return macaddr; 1874 1875 if (wlc_hw->_nbands > 1) 1876 var_id = BRCMS_SROM_ET1MACADDR; 1877 else 1878 var_id = BRCMS_SROM_IL0MACADDR; 1879 1880 macaddr = getvar(wlc_hw->sih, var_id); 1881 if (macaddr == NULL) 1882 wiphy_err(wlc_hw->wlc->wiphy, "wl%d: wlc_get_macaddr: macaddr " 1883 "getvar(%d) not found\n", wlc_hw->unit, var_id); 1884 1885 return macaddr; 1886} 1887 1888/* power both the pll and external oscillator on/off */ 1889static void brcms_b_xtal(struct brcms_hardware *wlc_hw, bool want) 1890{ 1891 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: want %d\n", wlc_hw->unit, want); 1892 1893 /* 1894 * dont power down if plldown is false or 1895 * we must poll hw radio disable 1896 */ 1897 if (!want && wlc_hw->pllreq) 1898 return; 1899 1900 if (wlc_hw->sih) 1901 ai_clkctl_xtal(wlc_hw->sih, XTAL | PLL, want); 1902 1903 wlc_hw->sbclk = want; 1904 if (!wlc_hw->sbclk) { 1905 wlc_hw->clk = false; 1906 if (wlc_hw->band && wlc_hw->band->pi) 1907 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false); 1908 } 1909} 1910 1911/* 1912 * Return true if radio is disabled, otherwise false. 1913 * hw radio disable signal is an external pin, users activate it asynchronously 1914 * this function could be called when driver is down and w/o clock 1915 * it operates on different registers depending on corerev and boardflag. 1916 */ 1917static bool brcms_b_radio_read_hwdisabled(struct brcms_hardware *wlc_hw) 1918{ 1919 bool v, clk, xtal; 1920 u32 resetbits = 0, flags = 0; 1921 1922 xtal = wlc_hw->sbclk; 1923 if (!xtal) 1924 brcms_b_xtal(wlc_hw, ON); 1925 1926 /* may need to take core out of reset first */ 1927 clk = wlc_hw->clk; 1928 if (!clk) { 1929 /* 1930 * mac no longer enables phyclk automatically when driver 1931 * accesses phyreg throughput mac. This can be skipped since 1932 * only mac reg is accessed below 1933 */ 1934 flags |= SICF_PCLKE; 1935 1936 /* 1937 * AI chip doesn't restore bar0win2 on 1938 * hibernation/resume, need sw fixup 1939 */ 1940 if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) || 1941 (wlc_hw->sih->chip == BCM43225_CHIP_ID)) 1942 wlc_hw->regs = (struct d11regs __iomem *) 1943 ai_setcore(wlc_hw->sih, D11_CORE_ID, 0); 1944 ai_core_reset(wlc_hw->sih, flags, resetbits); 1945 brcms_c_mctrl_reset(wlc_hw); 1946 } 1947 1948 v = ((R_REG(&wlc_hw->regs->phydebug) & PDBG_RFD) != 0); 1949 1950 /* put core back into reset */ 1951 if (!clk) 1952 ai_core_disable(wlc_hw->sih, 0); 1953 1954 if (!xtal) 1955 brcms_b_xtal(wlc_hw, OFF); 1956 1957 return v; 1958} 1959 1960static bool wlc_dma_rxreset(struct brcms_hardware *wlc_hw, uint fifo) 1961{ 1962 struct dma_pub *di = wlc_hw->di[fifo]; 1963 return dma_rxreset(di); 1964} 1965 1966/* d11 core reset 1967 * ensure fask clock during reset 1968 * reset dma 1969 * reset d11(out of reset) 1970 * reset phy(out of reset) 1971 * clear software macintstatus for fresh new start 1972 * one testing hack wlc_hw->noreset will bypass the d11/phy reset 1973 */ 1974void brcms_b_corereset(struct brcms_hardware *wlc_hw, u32 flags) 1975{ 1976 struct d11regs __iomem *regs; 1977 uint i; 1978 bool fastclk; 1979 u32 resetbits = 0; 1980 1981 if (flags == BRCMS_USE_COREFLAGS) 1982 flags = (wlc_hw->band->pi ? wlc_hw->band->core_flags : 0); 1983 1984 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit); 1985 1986 regs = wlc_hw->regs; 1987 1988 /* request FAST clock if not on */ 1989 fastclk = wlc_hw->forcefastclk; 1990 if (!fastclk) 1991 brcms_b_clkctl_clk(wlc_hw, CLK_FAST); 1992 1993 /* reset the dma engines except first time thru */ 1994 if (ai_iscoreup(wlc_hw->sih)) { 1995 for (i = 0; i < NFIFO; i++) 1996 if ((wlc_hw->di[i]) && (!dma_txreset(wlc_hw->di[i]))) 1997 wiphy_err(wlc_hw->wlc->wiphy, "wl%d: %s: " 1998 "dma_txreset[%d]: cannot stop dma\n", 1999 wlc_hw->unit, __func__, i); 2000 2001 if ((wlc_hw->di[RX_FIFO]) 2002 && (!wlc_dma_rxreset(wlc_hw, RX_FIFO))) 2003 wiphy_err(wlc_hw->wlc->wiphy, "wl%d: %s: dma_rxreset" 2004 "[%d]: cannot stop dma\n", 2005 wlc_hw->unit, __func__, RX_FIFO); 2006 } 2007 /* if noreset, just stop the psm and return */ 2008 if (wlc_hw->noreset) { 2009 wlc_hw->wlc->macintstatus = 0; /* skip wl_dpc after down */ 2010 brcms_b_mctrl(wlc_hw, MCTL_PSM_RUN | MCTL_EN_MAC, 0); 2011 return; 2012 } 2013 2014 /* 2015 * mac no longer enables phyclk automatically when driver accesses 2016 * phyreg throughput mac, AND phy_reset is skipped at early stage when 2017 * band->pi is invalid. need to enable PHY CLK 2018 */ 2019 flags |= SICF_PCLKE; 2020 2021 /* 2022 * reset the core 2023 * In chips with PMU, the fastclk request goes through d11 core 2024 * reg 0x1e0, which is cleared by the core_reset. have to re-request it. 2025 * 2026 * This adds some delay and we can optimize it by also requesting 2027 * fastclk through chipcommon during this period if necessary. But 2028 * that has to work coordinate with other driver like mips/arm since 2029 * they may touch chipcommon as well. 2030 */ 2031 wlc_hw->clk = false; 2032 ai_core_reset(wlc_hw->sih, flags, resetbits); 2033 wlc_hw->clk = true; 2034 if (wlc_hw->band && wlc_hw->band->pi) 2035 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, true); 2036 2037 brcms_c_mctrl_reset(wlc_hw); 2038 2039 if (wlc_hw->sih->cccaps & CC_CAP_PMU) 2040 brcms_b_clkctl_clk(wlc_hw, CLK_FAST); 2041 2042 brcms_b_phy_reset(wlc_hw); 2043 2044 /* turn on PHY_PLL */ 2045 brcms_b_core_phypll_ctl(wlc_hw, true); 2046 2047 /* clear sw intstatus */ 2048 wlc_hw->wlc->macintstatus = 0; 2049 2050 /* restore the clk setting */ 2051 if (!fastclk) 2052 brcms_b_clkctl_clk(wlc_hw, CLK_DYNAMIC); 2053} 2054 2055/* txfifo sizes needs to be modified(increased) since the newer cores 2056 * have more memory. 2057 */ 2058static void brcms_b_corerev_fifofixup(struct brcms_hardware *wlc_hw) 2059{ 2060 struct d11regs __iomem *regs = wlc_hw->regs; 2061 u16 fifo_nu; 2062 u16 txfifo_startblk = TXFIFO_START_BLK, txfifo_endblk; 2063 u16 txfifo_def, txfifo_def1; 2064 u16 txfifo_cmd; 2065 2066 /* tx fifos start at TXFIFO_START_BLK from the Base address */ 2067 txfifo_startblk = TXFIFO_START_BLK; 2068 2069 /* sequence of operations: reset fifo, set fifo size, reset fifo */ 2070 for (fifo_nu = 0; fifo_nu < NFIFO; fifo_nu++) { 2071 2072 txfifo_endblk = txfifo_startblk + wlc_hw->xmtfifo_sz[fifo_nu]; 2073 txfifo_def = (txfifo_startblk & 0xff) | 2074 (((txfifo_endblk - 1) & 0xff) << TXFIFO_FIFOTOP_SHIFT); 2075 txfifo_def1 = ((txfifo_startblk >> 8) & 0x1) | 2076 ((((txfifo_endblk - 2077 1) >> 8) & 0x1) << TXFIFO_FIFOTOP_SHIFT); 2078 txfifo_cmd = 2079 TXFIFOCMD_RESET_MASK | (fifo_nu << TXFIFOCMD_FIFOSEL_SHIFT); 2080 2081 W_REG(®s->xmtfifocmd, txfifo_cmd); 2082 W_REG(®s->xmtfifodef, txfifo_def); 2083 W_REG(®s->xmtfifodef1, txfifo_def1); 2084 2085 W_REG(®s->xmtfifocmd, txfifo_cmd); 2086 2087 txfifo_startblk += wlc_hw->xmtfifo_sz[fifo_nu]; 2088 } 2089 /* 2090 * need to propagate to shm location to be in sync since ucode/hw won't 2091 * do this 2092 */ 2093 brcms_b_write_shm(wlc_hw, M_FIFOSIZE0, 2094 wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]); 2095 brcms_b_write_shm(wlc_hw, M_FIFOSIZE1, 2096 wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]); 2097 brcms_b_write_shm(wlc_hw, M_FIFOSIZE2, 2098 ((wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO] << 8) | wlc_hw-> 2099 xmtfifo_sz[TX_AC_BK_FIFO])); 2100 brcms_b_write_shm(wlc_hw, M_FIFOSIZE3, 2101 ((wlc_hw->xmtfifo_sz[TX_ATIM_FIFO] << 8) | wlc_hw-> 2102 xmtfifo_sz[TX_BCMC_FIFO])); 2103} 2104 2105/* This function is used for changing the tsf frac register 2106 * If spur avoidance mode is off, the mac freq will be 80/120/160Mhz 2107 * If spur avoidance mode is on1, the mac freq will be 82/123/164Mhz 2108 * If spur avoidance mode is on2, the mac freq will be 84/126/168Mhz 2109 * HTPHY Formula is 2^26/freq(MHz) e.g. 2110 * For spuron2 - 126MHz -> 2^26/126 = 532610.0 2111 * - 532610 = 0x82082 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x2082 2112 * For spuron: 123MHz -> 2^26/123 = 545600.5 2113 * - 545601 = 0x85341 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x5341 2114 * For spur off: 120MHz -> 2^26/120 = 559240.5 2115 * - 559241 = 0x88889 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x8889 2116 */ 2117 2118void brcms_b_switch_macfreq(struct brcms_hardware *wlc_hw, u8 spurmode) 2119{ 2120 struct d11regs __iomem *regs = wlc_hw->regs; 2121 2122 if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) || 2123 (wlc_hw->sih->chip == BCM43225_CHIP_ID)) { 2124 if (spurmode == WL_SPURAVOID_ON2) { /* 126Mhz */ 2125 W_REG(®s->tsf_clk_frac_l, 0x2082); 2126 W_REG(®s->tsf_clk_frac_h, 0x8); 2127 } else if (spurmode == WL_SPURAVOID_ON1) { /* 123Mhz */ 2128 W_REG(®s->tsf_clk_frac_l, 0x5341); 2129 W_REG(®s->tsf_clk_frac_h, 0x8); 2130 } else { /* 120Mhz */ 2131 W_REG(®s->tsf_clk_frac_l, 0x8889); 2132 W_REG(®s->tsf_clk_frac_h, 0x8); 2133 } 2134 } else if (BRCMS_ISLCNPHY(wlc_hw->band)) { 2135 if (spurmode == WL_SPURAVOID_ON1) { /* 82Mhz */ 2136 W_REG(®s->tsf_clk_frac_l, 0x7CE0); 2137 W_REG(®s->tsf_clk_frac_h, 0xC); 2138 } else { /* 80Mhz */ 2139 W_REG(®s->tsf_clk_frac_l, 0xCCCD); 2140 W_REG(®s->tsf_clk_frac_h, 0xC); 2141 } 2142 } 2143} 2144 2145/* Initialize GPIOs that are controlled by D11 core */ 2146static void brcms_c_gpio_init(struct brcms_c_info *wlc) 2147{ 2148 struct brcms_hardware *wlc_hw = wlc->hw; 2149 struct d11regs __iomem *regs; 2150 u32 gc, gm; 2151 2152 regs = wlc_hw->regs; 2153 2154 /* use GPIO select 0 to get all gpio signals from the gpio out reg */ 2155 brcms_b_mctrl(wlc_hw, MCTL_GPOUT_SEL_MASK, 0); 2156 2157 /* 2158 * Common GPIO setup: 2159 * G0 = LED 0 = WLAN Activity 2160 * G1 = LED 1 = WLAN 2.4 GHz Radio State 2161 * G2 = LED 2 = WLAN 5 GHz Radio State 2162 * G4 = radio disable input (HI enabled, LO disabled) 2163 */ 2164 2165 gc = gm = 0; 2166 2167 /* Allocate GPIOs for mimo antenna diversity feature */ 2168 if (wlc_hw->antsel_type == ANTSEL_2x3) { 2169 /* Enable antenna diversity, use 2x3 mode */ 2170 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN, 2171 MHF3_ANTSEL_EN, BRCM_BAND_ALL); 2172 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE, 2173 MHF3_ANTSEL_MODE, BRCM_BAND_ALL); 2174 2175 /* init superswitch control */ 2176 wlc_phy_antsel_init(wlc_hw->band->pi, false); 2177 2178 } else if (wlc_hw->antsel_type == ANTSEL_2x4) { 2179 gm |= gc |= (BOARD_GPIO_12 | BOARD_GPIO_13); 2180 /* 2181 * The board itself is powered by these GPIOs 2182 * (when not sending pattern) so set them high 2183 */ 2184 OR_REG(®s->psm_gpio_oe, 2185 (BOARD_GPIO_12 | BOARD_GPIO_13)); 2186 OR_REG(®s->psm_gpio_out, 2187 (BOARD_GPIO_12 | BOARD_GPIO_13)); 2188 2189 /* Enable antenna diversity, use 2x4 mode */ 2190 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN, 2191 MHF3_ANTSEL_EN, BRCM_BAND_ALL); 2192 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE, 0, 2193 BRCM_BAND_ALL); 2194 2195 /* Configure the desired clock to be 4Mhz */ 2196 brcms_b_write_shm(wlc_hw, M_ANTSEL_CLKDIV, 2197 ANTSEL_CLKDIV_4MHZ); 2198 } 2199 2200 /* 2201 * gpio 9 controls the PA. ucode is responsible 2202 * for wiggling out and oe 2203 */ 2204 if (wlc_hw->boardflags & BFL_PACTRL) 2205 gm |= gc |= BOARD_GPIO_PACTRL; 2206 2207 /* apply to gpiocontrol register */ 2208 ai_gpiocontrol(wlc_hw->sih, gm, gc, GPIO_DRV_PRIORITY); 2209} 2210 2211static void brcms_ucode_write(struct brcms_hardware *wlc_hw, 2212 const __le32 ucode[], const size_t nbytes) 2213{ 2214 struct d11regs __iomem *regs = wlc_hw->regs; 2215 uint i; 2216 uint count; 2217 2218 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit); 2219 2220 count = (nbytes / sizeof(u32)); 2221 2222 W_REG(®s->objaddr, (OBJADDR_AUTO_INC | OBJADDR_UCM_SEL)); 2223 (void)R_REG(®s->objaddr); 2224 for (i = 0; i < count; i++) 2225 W_REG(®s->objdata, le32_to_cpu(ucode[i])); 2226 2227} 2228 2229static void brcms_ucode_download(struct brcms_hardware *wlc_hw) 2230{ 2231 struct brcms_c_info *wlc; 2232 struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode; 2233 2234 wlc = wlc_hw->wlc; 2235 2236 if (wlc_hw->ucode_loaded) 2237 return; 2238 2239 if (D11REV_IS(wlc_hw->corerev, 23)) { 2240 if (BRCMS_ISNPHY(wlc_hw->band)) { 2241 brcms_ucode_write(wlc_hw, ucode->bcm43xx_16_mimo, 2242 ucode->bcm43xx_16_mimosz); 2243 wlc_hw->ucode_loaded = true; 2244 } else 2245 wiphy_err(wlc->wiphy, "%s: wl%d: unsupported phy in " 2246 "corerev %d\n", 2247 __func__, wlc_hw->unit, wlc_hw->corerev); 2248 } else if (D11REV_IS(wlc_hw->corerev, 24)) { 2249 if (BRCMS_ISLCNPHY(wlc_hw->band)) { 2250 brcms_ucode_write(wlc_hw, ucode->bcm43xx_24_lcn, 2251 ucode->bcm43xx_24_lcnsz); 2252 wlc_hw->ucode_loaded = true; 2253 } else { 2254 wiphy_err(wlc->wiphy, "%s: wl%d: unsupported phy in " 2255 "corerev %d\n", 2256 __func__, wlc_hw->unit, wlc_hw->corerev); 2257 } 2258 } 2259} 2260 2261void brcms_b_txant_set(struct brcms_hardware *wlc_hw, u16 phytxant) 2262{ 2263 /* update sw state */ 2264 wlc_hw->bmac_phytxant = phytxant; 2265 2266 /* push to ucode if up */ 2267 if (!wlc_hw->up) 2268 return; 2269 brcms_c_ucode_txant_set(wlc_hw); 2270 2271} 2272 2273u16 brcms_b_get_txant(struct brcms_hardware *wlc_hw) 2274{ 2275 return (u16) wlc_hw->wlc->stf->txant; 2276} 2277 2278void brcms_b_antsel_type_set(struct brcms_hardware *wlc_hw, u8 antsel_type) 2279{ 2280 wlc_hw->antsel_type = antsel_type; 2281 2282 /* Update the antsel type for phy module to use */ 2283 wlc_phy_antsel_type_set(wlc_hw->band->pi, antsel_type); 2284} 2285 2286static void brcms_b_fifoerrors(struct brcms_hardware *wlc_hw) 2287{ 2288 bool fatal = false; 2289 uint unit; 2290 uint intstatus, idx; 2291 struct d11regs __iomem *regs = wlc_hw->regs; 2292 struct wiphy *wiphy = wlc_hw->wlc->wiphy; 2293 2294 unit = wlc_hw->unit; 2295 2296 for (idx = 0; idx < NFIFO; idx++) { 2297 /* read intstatus register and ignore any non-error bits */ 2298 intstatus = 2299 R_REG(®s->intctrlregs[idx].intstatus) & I_ERRORS; 2300 if (!intstatus) 2301 continue; 2302 2303 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: intstatus%d 0x%x\n", 2304 unit, idx, intstatus); 2305 2306 if (intstatus & I_RO) { 2307 wiphy_err(wiphy, "wl%d: fifo %d: receive fifo " 2308 "overflow\n", unit, idx); 2309 fatal = true; 2310 } 2311 2312 if (intstatus & I_PC) { 2313 wiphy_err(wiphy, "wl%d: fifo %d: descriptor error\n", 2314 unit, idx); 2315 fatal = true; 2316 } 2317 2318 if (intstatus & I_PD) { 2319 wiphy_err(wiphy, "wl%d: fifo %d: data error\n", unit, 2320 idx); 2321 fatal = true; 2322 } 2323 2324 if (intstatus & I_DE) { 2325 wiphy_err(wiphy, "wl%d: fifo %d: descriptor protocol " 2326 "error\n", unit, idx); 2327 fatal = true; 2328 } 2329 2330 if (intstatus & I_RU) 2331 wiphy_err(wiphy, "wl%d: fifo %d: receive descriptor " 2332 "underflow\n", idx, unit); 2333 2334 if (intstatus & I_XU) { 2335 wiphy_err(wiphy, "wl%d: fifo %d: transmit fifo " 2336 "underflow\n", idx, unit); 2337 fatal = true; 2338 } 2339 2340 if (fatal) { 2341 brcms_fatal_error(wlc_hw->wlc->wl); /* big hammer */ 2342 break; 2343 } else 2344 W_REG(®s->intctrlregs[idx].intstatus, 2345 intstatus); 2346 } 2347} 2348 2349void brcms_c_intrson(struct brcms_c_info *wlc) 2350{ 2351 struct brcms_hardware *wlc_hw = wlc->hw; 2352 wlc->macintmask = wlc->defmacintmask; 2353 W_REG(&wlc_hw->regs->macintmask, wlc->macintmask); 2354} 2355 2356/* 2357 * callback for siutils.c, which has only wlc handler, no wl they both check 2358 * up, not only because there is no need to off/restore d11 interrupt but also 2359 * because per-port code may require sync with valid interrupt. 2360 */ 2361static u32 brcms_c_wlintrsoff(struct brcms_c_info *wlc) 2362{ 2363 if (!wlc->hw->up) 2364 return 0; 2365 2366 return brcms_intrsoff(wlc->wl); 2367} 2368 2369static void brcms_c_wlintrsrestore(struct brcms_c_info *wlc, u32 macintmask) 2370{ 2371 if (!wlc->hw->up) 2372 return; 2373 2374 brcms_intrsrestore(wlc->wl, macintmask); 2375} 2376 2377u32 brcms_c_intrsoff(struct brcms_c_info *wlc) 2378{ 2379 struct brcms_hardware *wlc_hw = wlc->hw; 2380 u32 macintmask; 2381 2382 if (!wlc_hw->clk) 2383 return 0; 2384 2385 macintmask = wlc->macintmask; /* isr can still happen */ 2386 2387 W_REG(&wlc_hw->regs->macintmask, 0); 2388 (void)R_REG(&wlc_hw->regs->macintmask); /* sync readback */ 2389 udelay(1); /* ensure int line is no longer driven */ 2390 wlc->macintmask = 0; 2391 2392 /* return previous macintmask; resolve race between us and our isr */ 2393 return wlc->macintstatus ? 0 : macintmask; 2394} 2395 2396void brcms_c_intrsrestore(struct brcms_c_info *wlc, u32 macintmask) 2397{ 2398 struct brcms_hardware *wlc_hw = wlc->hw; 2399 if (!wlc_hw->clk) 2400 return; 2401 2402 wlc->macintmask = macintmask; 2403 W_REG(&wlc_hw->regs->macintmask, wlc->macintmask); 2404} 2405 2406/* assumes that the d11 MAC is enabled */ 2407static void brcms_b_tx_fifo_suspend(struct brcms_hardware *wlc_hw, 2408 uint tx_fifo) 2409{ 2410 u8 fifo = 1 << tx_fifo; 2411 2412 /* Two clients of this code, 11h Quiet period and scanning. */ 2413 2414 /* only suspend if not already suspended */ 2415 if ((wlc_hw->suspended_fifos & fifo) == fifo) 2416 return; 2417 2418 /* force the core awake only if not already */ 2419 if (wlc_hw->suspended_fifos == 0) 2420 brcms_c_ucode_wake_override_set(wlc_hw, 2421 BRCMS_WAKE_OVERRIDE_TXFIFO); 2422 2423 wlc_hw->suspended_fifos |= fifo; 2424 2425 if (wlc_hw->di[tx_fifo]) { 2426 /* 2427 * Suspending AMPDU transmissions in the middle can cause 2428 * underflow which may result in mismatch between ucode and 2429 * driver so suspend the mac before suspending the FIFO 2430 */ 2431 if (BRCMS_PHY_11N_CAP(wlc_hw->band)) 2432 brcms_c_suspend_mac_and_wait(wlc_hw->wlc); 2433 2434 dma_txsuspend(wlc_hw->di[tx_fifo]); 2435 2436 if (BRCMS_PHY_11N_CAP(wlc_hw->band)) 2437 brcms_c_enable_mac(wlc_hw->wlc); 2438 } 2439} 2440 2441static void brcms_b_tx_fifo_resume(struct brcms_hardware *wlc_hw, 2442 uint tx_fifo) 2443{ 2444 /* BMAC_NOTE: BRCMS_TX_FIFO_ENAB is done in brcms_c_dpc() for DMA case 2445 * but need to be done here for PIO otherwise the watchdog will catch 2446 * the inconsistency and fire 2447 */ 2448 /* Two clients of this code, 11h Quiet period and scanning. */ 2449 if (wlc_hw->di[tx_fifo]) 2450 dma_txresume(wlc_hw->di[tx_fifo]); 2451 2452 /* allow core to sleep again */ 2453 if (wlc_hw->suspended_fifos == 0) 2454 return; 2455 else { 2456 wlc_hw->suspended_fifos &= ~(1 << tx_fifo); 2457 if (wlc_hw->suspended_fifos == 0) 2458 brcms_c_ucode_wake_override_clear(wlc_hw, 2459 BRCMS_WAKE_OVERRIDE_TXFIFO); 2460 } 2461} 2462 2463/* precondition: requires the mac core to be enabled */ 2464static void brcms_b_mute(struct brcms_hardware *wlc_hw, bool mute_tx) 2465{ 2466 static const u8 null_ether_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0}; 2467 2468 if (mute_tx) { 2469 /* suspend tx fifos */ 2470 brcms_b_tx_fifo_suspend(wlc_hw, TX_DATA_FIFO); 2471 brcms_b_tx_fifo_suspend(wlc_hw, TX_CTL_FIFO); 2472 brcms_b_tx_fifo_suspend(wlc_hw, TX_AC_BK_FIFO); 2473 brcms_b_tx_fifo_suspend(wlc_hw, TX_AC_VI_FIFO); 2474 2475 /* zero the address match register so we do not send ACKs */ 2476 brcms_b_set_addrmatch(wlc_hw, RCM_MAC_OFFSET, 2477 null_ether_addr); 2478 } else { 2479 /* resume tx fifos */ 2480 brcms_b_tx_fifo_resume(wlc_hw, TX_DATA_FIFO); 2481 brcms_b_tx_fifo_resume(wlc_hw, TX_CTL_FIFO); 2482 brcms_b_tx_fifo_resume(wlc_hw, TX_AC_BK_FIFO); 2483 brcms_b_tx_fifo_resume(wlc_hw, TX_AC_VI_FIFO); 2484 2485 /* Restore address */ 2486 brcms_b_set_addrmatch(wlc_hw, RCM_MAC_OFFSET, 2487 wlc_hw->etheraddr); 2488 } 2489 2490 wlc_phy_mute_upd(wlc_hw->band->pi, mute_tx, 0); 2491 2492 if (mute_tx) 2493 brcms_c_ucode_mute_override_set(wlc_hw); 2494 else 2495 brcms_c_ucode_mute_override_clear(wlc_hw); 2496} 2497 2498void 2499brcms_c_mute(struct brcms_c_info *wlc, bool mute_tx) 2500{ 2501 brcms_b_mute(wlc->hw, mute_tx); 2502} 2503 2504/* 2505 * Read and clear macintmask and macintstatus and intstatus registers. 2506 * This routine should be called with interrupts off 2507 * Return: 2508 * -1 if brcms_deviceremoved(wlc) evaluates to true; 2509 * 0 if the interrupt is not for us, or we are in some special cases; 2510 * device interrupt status bits otherwise. 2511 */ 2512static inline u32 wlc_intstatus(struct brcms_c_info *wlc, bool in_isr) 2513{ 2514 struct brcms_hardware *wlc_hw = wlc->hw; 2515 struct d11regs __iomem *regs = wlc_hw->regs; 2516 u32 macintstatus; 2517 2518 /* macintstatus includes a DMA interrupt summary bit */ 2519 macintstatus = R_REG(®s->macintstatus); 2520 2521 BCMMSG(wlc->wiphy, "wl%d: macintstatus: 0x%x\n", wlc_hw->unit, 2522 macintstatus); 2523 2524 /* detect cardbus removed, in power down(suspend) and in reset */ 2525 if (brcms_deviceremoved(wlc)) 2526 return -1; 2527 2528 /* brcms_deviceremoved() succeeds even when the core is still resetting, 2529 * handle that case here. 2530 */ 2531 if (macintstatus == 0xffffffff) 2532 return 0; 2533 2534 /* defer unsolicited interrupts */ 2535 macintstatus &= (in_isr ? wlc->macintmask : wlc->defmacintmask); 2536 2537 /* if not for us */ 2538 if (macintstatus == 0) 2539 return 0; 2540 2541 /* interrupts are already turned off for CFE build 2542 * Caution: For CFE Turning off the interrupts again has some undesired 2543 * consequences 2544 */ 2545 /* turn off the interrupts */ 2546 W_REG(®s->macintmask, 0); 2547 (void)R_REG(®s->macintmask); /* sync readback */ 2548 wlc->macintmask = 0; 2549 2550 /* clear device interrupts */ 2551 W_REG(®s->macintstatus, macintstatus); 2552 2553 /* MI_DMAINT is indication of non-zero intstatus */ 2554 if (macintstatus & MI_DMAINT) 2555 /* 2556 * only fifo interrupt enabled is I_RI in 2557 * RX_FIFO. If MI_DMAINT is set, assume it 2558 * is set and clear the interrupt. 2559 */ 2560 W_REG(®s->intctrlregs[RX_FIFO].intstatus, 2561 DEF_RXINTMASK); 2562 2563 return macintstatus; 2564} 2565 2566/* Update wlc->macintstatus and wlc->intstatus[]. */ 2567/* Return true if they are updated successfully. false otherwise */ 2568bool brcms_c_intrsupd(struct brcms_c_info *wlc) 2569{ 2570 u32 macintstatus; 2571 2572 /* read and clear macintstatus and intstatus registers */ 2573 macintstatus = wlc_intstatus(wlc, false); 2574 2575 /* device is removed */ 2576 if (macintstatus == 0xffffffff) 2577 return false; 2578 2579 /* update interrupt status in software */ 2580 wlc->macintstatus |= macintstatus; 2581 2582 return true; 2583} 2584 2585/* 2586 * First-level interrupt processing. 2587 * Return true if this was our interrupt, false otherwise. 2588 * *wantdpc will be set to true if further brcms_c_dpc() processing is required, 2589 * false otherwise. 2590 */ 2591bool brcms_c_isr(struct brcms_c_info *wlc, bool *wantdpc) 2592{ 2593 struct brcms_hardware *wlc_hw = wlc->hw; 2594 u32 macintstatus; 2595 2596 *wantdpc = false; 2597 2598 if (!wlc_hw->up || !wlc->macintmask) 2599 return false; 2600 2601 /* read and clear macintstatus and intstatus registers */ 2602 macintstatus = wlc_intstatus(wlc, true); 2603 2604 if (macintstatus == 0xffffffff) 2605 wiphy_err(wlc->wiphy, "DEVICEREMOVED detected in the ISR code" 2606 " path\n"); 2607 2608 /* it is not for us */ 2609 if (macintstatus == 0) 2610 return false; 2611 2612 *wantdpc = true; 2613 2614 /* save interrupt status bits */ 2615 wlc->macintstatus = macintstatus; 2616 2617 return true; 2618 2619} 2620 2621void brcms_c_suspend_mac_and_wait(struct brcms_c_info *wlc) 2622{ 2623 struct brcms_hardware *wlc_hw = wlc->hw; 2624 struct d11regs __iomem *regs = wlc_hw->regs; 2625 u32 mc, mi; 2626 struct wiphy *wiphy = wlc->wiphy; 2627 2628 BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit, 2629 wlc_hw->band->bandunit); 2630 2631 /* 2632 * Track overlapping suspend requests 2633 */ 2634 wlc_hw->mac_suspend_depth++; 2635 if (wlc_hw->mac_suspend_depth > 1) 2636 return; 2637 2638 /* force the core awake */ 2639 brcms_c_ucode_wake_override_set(wlc_hw, BRCMS_WAKE_OVERRIDE_MACSUSPEND); 2640 2641 mc = R_REG(®s->maccontrol); 2642 2643 if (mc == 0xffffffff) { 2644 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit, 2645 __func__); 2646 brcms_down(wlc->wl); 2647 return; 2648 } 2649 WARN_ON(mc & MCTL_PSM_JMP_0); 2650 WARN_ON(!(mc & MCTL_PSM_RUN)); 2651 WARN_ON(!(mc & MCTL_EN_MAC)); 2652 2653 mi = R_REG(®s->macintstatus); 2654 if (mi == 0xffffffff) { 2655 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit, 2656 __func__); 2657 brcms_down(wlc->wl); 2658 return; 2659 } 2660 WARN_ON(mi & MI_MACSSPNDD); 2661 2662 brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, 0); 2663 2664 SPINWAIT(!(R_REG(®s->macintstatus) & MI_MACSSPNDD), 2665 BRCMS_MAX_MAC_SUSPEND); 2666 2667 if (!(R_REG(®s->macintstatus) & MI_MACSSPNDD)) { 2668 wiphy_err(wiphy, "wl%d: wlc_suspend_mac_and_wait: waited %d uS" 2669 " and MI_MACSSPNDD is still not on.\n", 2670 wlc_hw->unit, BRCMS_MAX_MAC_SUSPEND); 2671 wiphy_err(wiphy, "wl%d: psmdebug 0x%08x, phydebug 0x%08x, " 2672 "psm_brc 0x%04x\n", wlc_hw->unit, 2673 R_REG(®s->psmdebug), 2674 R_REG(®s->phydebug), 2675 R_REG(®s->psm_brc)); 2676 } 2677 2678 mc = R_REG(®s->maccontrol); 2679 if (mc == 0xffffffff) { 2680 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit, 2681 __func__); 2682 brcms_down(wlc->wl); 2683 return; 2684 } 2685 WARN_ON(mc & MCTL_PSM_JMP_0); 2686 WARN_ON(!(mc & MCTL_PSM_RUN)); 2687 WARN_ON(mc & MCTL_EN_MAC); 2688} 2689 2690void brcms_c_enable_mac(struct brcms_c_info *wlc) 2691{ 2692 struct brcms_hardware *wlc_hw = wlc->hw; 2693 struct d11regs __iomem *regs = wlc_hw->regs; 2694 u32 mc, mi; 2695 2696 BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit, 2697 wlc->band->bandunit); 2698 2699 /* 2700 * Track overlapping suspend requests 2701 */ 2702 wlc_hw->mac_suspend_depth--; 2703 if (wlc_hw->mac_suspend_depth > 0) 2704 return; 2705 2706 mc = R_REG(®s->maccontrol); 2707 WARN_ON(mc & MCTL_PSM_JMP_0); 2708 WARN_ON(mc & MCTL_EN_MAC); 2709 WARN_ON(!(mc & MCTL_PSM_RUN)); 2710 2711 brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, MCTL_EN_MAC); 2712 W_REG(®s->macintstatus, MI_MACSSPNDD); 2713 2714 mc = R_REG(®s->maccontrol); 2715 WARN_ON(mc & MCTL_PSM_JMP_0); 2716 WARN_ON(!(mc & MCTL_EN_MAC)); 2717 WARN_ON(!(mc & MCTL_PSM_RUN)); 2718 2719 mi = R_REG(®s->macintstatus); 2720 WARN_ON(mi & MI_MACSSPNDD); 2721 2722 brcms_c_ucode_wake_override_clear(wlc_hw, 2723 BRCMS_WAKE_OVERRIDE_MACSUSPEND); 2724} 2725 2726void brcms_b_band_stf_ss_set(struct brcms_hardware *wlc_hw, u8 stf_mode) 2727{ 2728 wlc_hw->hw_stf_ss_opmode = stf_mode; 2729 2730 if (wlc_hw->clk) 2731 brcms_upd_ofdm_pctl1_table(wlc_hw); 2732} 2733 2734static bool brcms_b_validate_chip_access(struct brcms_hardware *wlc_hw) 2735{ 2736 struct d11regs __iomem *regs; 2737 u32 w, val; 2738 struct wiphy *wiphy = wlc_hw->wlc->wiphy; 2739 2740 BCMMSG(wiphy, "wl%d\n", wlc_hw->unit); 2741 2742 regs = wlc_hw->regs; 2743 2744 /* Validate dchip register access */ 2745 2746 W_REG(®s->objaddr, OBJADDR_SHM_SEL | 0); 2747 (void)R_REG(®s->objaddr); 2748 w = R_REG(®s->objdata); 2749 2750 /* Can we write and read back a 32bit register? */ 2751 W_REG(®s->objaddr, OBJADDR_SHM_SEL | 0); 2752 (void)R_REG(®s->objaddr); 2753 W_REG(®s->objdata, (u32) 0xaa5555aa); 2754 2755 W_REG(®s->objaddr, OBJADDR_SHM_SEL | 0); 2756 (void)R_REG(®s->objaddr); 2757 val = R_REG(®s->objdata); 2758 if (val != (u32) 0xaa5555aa) { 2759 wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, " 2760 "expected 0xaa5555aa\n", wlc_hw->unit, val); 2761 return false; 2762 } 2763 2764 W_REG(®s->objaddr, OBJADDR_SHM_SEL | 0); 2765 (void)R_REG(®s->objaddr); 2766 W_REG(®s->objdata, (u32) 0x55aaaa55); 2767 2768 W_REG(®s->objaddr, OBJADDR_SHM_SEL | 0); 2769 (void)R_REG(®s->objaddr); 2770 val = R_REG(®s->objdata); 2771 if (val != (u32) 0x55aaaa55) { 2772 wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, " 2773 "expected 0x55aaaa55\n", wlc_hw->unit, val); 2774 return false; 2775 } 2776 2777 W_REG(®s->objaddr, OBJADDR_SHM_SEL | 0); 2778 (void)R_REG(®s->objaddr); 2779 W_REG(®s->objdata, w); 2780 2781 /* clear CFPStart */ 2782 W_REG(®s->tsf_cfpstart, 0); 2783 2784 w = R_REG(®s->maccontrol); 2785 if ((w != (MCTL_IHR_EN | MCTL_WAKE)) && 2786 (w != (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE))) { 2787 wiphy_err(wiphy, "wl%d: validate_chip_access: maccontrol = " 2788 "0x%x, expected 0x%x or 0x%x\n", wlc_hw->unit, w, 2789 (MCTL_IHR_EN | MCTL_WAKE), 2790 (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE)); 2791 return false; 2792 } 2793 2794 return true; 2795} 2796 2797#define PHYPLL_WAIT_US 100000 2798 2799void brcms_b_core_phypll_ctl(struct brcms_hardware *wlc_hw, bool on) 2800{ 2801 struct d11regs __iomem *regs; 2802 u32 tmp; 2803 2804 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit); 2805 2806 tmp = 0; 2807 regs = wlc_hw->regs; 2808 2809 if (on) { 2810 if ((wlc_hw->sih->chip == BCM4313_CHIP_ID)) { 2811 OR_REG(®s->clk_ctl_st, 2812 (CCS_ERSRC_REQ_HT | CCS_ERSRC_REQ_D11PLL | 2813 CCS_ERSRC_REQ_PHYPLL)); 2814 SPINWAIT((R_REG(®s->clk_ctl_st) & 2815 (CCS_ERSRC_AVAIL_HT)) != (CCS_ERSRC_AVAIL_HT), 2816 PHYPLL_WAIT_US); 2817 2818 tmp = R_REG(®s->clk_ctl_st); 2819 if ((tmp & (CCS_ERSRC_AVAIL_HT)) != 2820 (CCS_ERSRC_AVAIL_HT)) 2821 wiphy_err(wlc_hw->wlc->wiphy, "%s: turn on PHY" 2822 " PLL failed\n", __func__); 2823 } else { 2824 OR_REG(®s->clk_ctl_st, 2825 (CCS_ERSRC_REQ_D11PLL | CCS_ERSRC_REQ_PHYPLL)); 2826 SPINWAIT((R_REG(®s->clk_ctl_st) & 2827 (CCS_ERSRC_AVAIL_D11PLL | 2828 CCS_ERSRC_AVAIL_PHYPLL)) != 2829 (CCS_ERSRC_AVAIL_D11PLL | 2830 CCS_ERSRC_AVAIL_PHYPLL), PHYPLL_WAIT_US); 2831 2832 tmp = R_REG(®s->clk_ctl_st); 2833 if ((tmp & 2834 (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL)) 2835 != 2836 (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL)) 2837 wiphy_err(wlc_hw->wlc->wiphy, "%s: turn on " 2838 "PHY PLL failed\n", __func__); 2839 } 2840 } else { 2841 /* 2842 * Since the PLL may be shared, other cores can still 2843 * be requesting it; so we'll deassert the request but 2844 * not wait for status to comply. 2845 */ 2846 AND_REG(®s->clk_ctl_st, ~CCS_ERSRC_REQ_PHYPLL); 2847 tmp = R_REG(®s->clk_ctl_st); 2848 } 2849} 2850 2851static void brcms_c_coredisable(struct brcms_hardware *wlc_hw) 2852{ 2853 bool dev_gone; 2854 2855 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit); 2856 2857 dev_gone = brcms_deviceremoved(wlc_hw->wlc); 2858 2859 if (dev_gone) 2860 return; 2861 2862 if (wlc_hw->noreset) 2863 return; 2864 2865 /* radio off */ 2866 wlc_phy_switch_radio(wlc_hw->band->pi, OFF); 2867 2868 /* turn off analog core */ 2869 wlc_phy_anacore(wlc_hw->band->pi, OFF); 2870 2871 /* turn off PHYPLL to save power */ 2872 brcms_b_core_phypll_ctl(wlc_hw, false); 2873 2874 wlc_hw->clk = false; 2875 ai_core_disable(wlc_hw->sih, 0); 2876 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false); 2877} 2878 2879static void brcms_c_flushqueues(struct brcms_c_info *wlc) 2880{ 2881 struct brcms_hardware *wlc_hw = wlc->hw; 2882 uint i; 2883 2884 /* free any posted tx packets */ 2885 for (i = 0; i < NFIFO; i++) 2886 if (wlc_hw->di[i]) { 2887 dma_txreclaim(wlc_hw->di[i], DMA_RANGE_ALL); 2888 wlc->core->txpktpend[i] = 0; 2889 BCMMSG(wlc->wiphy, "pktpend fifo %d clrd\n", i); 2890 } 2891 2892 /* free any posted rx packets */ 2893 dma_rxreclaim(wlc_hw->di[RX_FIFO]); 2894} 2895 2896static u16 2897brcms_b_read_objmem(struct brcms_hardware *wlc_hw, uint offset, u32 sel) 2898{ 2899 struct d11regs __iomem *regs = wlc_hw->regs; 2900 u16 __iomem *objdata_lo = (u16 __iomem *)®s->objdata; 2901 u16 __iomem *objdata_hi = objdata_lo + 1; 2902 u16 v; 2903 2904 W_REG(®s->objaddr, sel | (offset >> 2)); 2905 (void)R_REG(®s->objaddr); 2906 if (offset & 2) 2907 v = R_REG(objdata_hi); 2908 else 2909 v = R_REG(objdata_lo); 2910 2911 return v; 2912} 2913 2914static void 2915brcms_b_write_objmem(struct brcms_hardware *wlc_hw, uint offset, u16 v, 2916 u32 sel) 2917{ 2918 struct d11regs __iomem *regs = wlc_hw->regs; 2919 u16 __iomem *objdata_lo = (u16 __iomem *)®s->objdata; 2920 u16 __iomem *objdata_hi = objdata_lo + 1; 2921 2922 W_REG(®s->objaddr, sel | (offset >> 2)); 2923 (void)R_REG(®s->objaddr); 2924 if (offset & 2) 2925 W_REG(objdata_hi, v); 2926 else 2927 W_REG(objdata_lo, v); 2928} 2929 2930/* 2931 * Read a single u16 from shared memory. 2932 * SHM 'offset' needs to be an even address 2933 */ 2934u16 brcms_b_read_shm(struct brcms_hardware *wlc_hw, uint offset) 2935{ 2936 return brcms_b_read_objmem(wlc_hw, offset, OBJADDR_SHM_SEL); 2937} 2938 2939/* 2940 * Write a single u16 to shared memory. 2941 * SHM 'offset' needs to be an even address 2942 */ 2943void brcms_b_write_shm(struct brcms_hardware *wlc_hw, uint offset, u16 v) 2944{ 2945 brcms_b_write_objmem(wlc_hw, offset, v, OBJADDR_SHM_SEL); 2946} 2947 2948/* 2949 * Copy a buffer to shared memory of specified type . 2950 * SHM 'offset' needs to be an even address and 2951 * Buffer length 'len' must be an even number of bytes 2952 * 'sel' selects the type of memory 2953 */ 2954void 2955brcms_b_copyto_objmem(struct brcms_hardware *wlc_hw, uint offset, 2956 const void *buf, int len, u32 sel) 2957{ 2958 u16 v; 2959 const u8 *p = (const u8 *)buf; 2960 int i; 2961 2962 if (len <= 0 || (offset & 1) || (len & 1)) 2963 return; 2964 2965 for (i = 0; i < len; i += 2) { 2966 v = p[i] | (p[i + 1] << 8); 2967 brcms_b_write_objmem(wlc_hw, offset + i, v, sel); 2968 } 2969} 2970 2971/* 2972 * Copy a piece of shared memory of specified type to a buffer . 2973 * SHM 'offset' needs to be an even address and 2974 * Buffer length 'len' must be an even number of bytes 2975 * 'sel' selects the type of memory 2976 */ 2977void 2978brcms_b_copyfrom_objmem(struct brcms_hardware *wlc_hw, uint offset, void *buf, 2979 int len, u32 sel) 2980{ 2981 u16 v; 2982 u8 *p = (u8 *) buf; 2983 int i; 2984 2985 if (len <= 0 || (offset & 1) || (len & 1)) 2986 return; 2987 2988 for (i = 0; i < len; i += 2) { 2989 v = brcms_b_read_objmem(wlc_hw, offset + i, sel); 2990 p[i] = v & 0xFF; 2991 p[i + 1] = (v >> 8) & 0xFF; 2992 } 2993} 2994 2995/* Copy a buffer to shared memory. 2996 * SHM 'offset' needs to be an even address and 2997 * Buffer length 'len' must be an even number of bytes 2998 */ 2999static void brcms_c_copyto_shm(struct brcms_c_info *wlc, uint offset, 3000 const void *buf, int len) 3001{ 3002 brcms_b_copyto_objmem(wlc->hw, offset, buf, len, OBJADDR_SHM_SEL); 3003} 3004 3005static void brcms_b_retrylimit_upd(struct brcms_hardware *wlc_hw, 3006 u16 SRL, u16 LRL) 3007{ 3008 wlc_hw->SRL = SRL; 3009 wlc_hw->LRL = LRL; 3010 3011 /* write retry limit to SCR, shouldn't need to suspend */ 3012 if (wlc_hw->up) { 3013 W_REG(&wlc_hw->regs->objaddr, 3014 OBJADDR_SCR_SEL | S_DOT11_SRC_LMT); 3015 (void)R_REG(&wlc_hw->regs->objaddr); 3016 W_REG(&wlc_hw->regs->objdata, wlc_hw->SRL); 3017 W_REG(&wlc_hw->regs->objaddr, 3018 OBJADDR_SCR_SEL | S_DOT11_LRC_LMT); 3019 (void)R_REG(&wlc_hw->regs->objaddr); 3020 W_REG(&wlc_hw->regs->objdata, wlc_hw->LRL); 3021 } 3022} 3023 3024static void brcms_b_pllreq(struct brcms_hardware *wlc_hw, bool set, u32 req_bit) 3025{ 3026 if (set) { 3027 if (mboolisset(wlc_hw->pllreq, req_bit)) 3028 return; 3029 3030 mboolset(wlc_hw->pllreq, req_bit); 3031 3032 if (mboolisset(wlc_hw->pllreq, BRCMS_PLLREQ_FLIP)) { 3033 if (!wlc_hw->sbclk) 3034 brcms_b_xtal(wlc_hw, ON); 3035 } 3036 } else { 3037 if (!mboolisset(wlc_hw->pllreq, req_bit)) 3038 return; 3039 3040 mboolclr(wlc_hw->pllreq, req_bit); 3041 3042 if (mboolisset(wlc_hw->pllreq, BRCMS_PLLREQ_FLIP)) { 3043 if (wlc_hw->sbclk) 3044 brcms_b_xtal(wlc_hw, OFF); 3045 } 3046 } 3047} 3048 3049static void brcms_b_antsel_set(struct brcms_hardware *wlc_hw, u32 antsel_avail) 3050{ 3051 wlc_hw->antsel_avail = antsel_avail; 3052} 3053 3054/* 3055 * conditions under which the PM bit should be set in outgoing frames 3056 * and STAY_AWAKE is meaningful 3057 */ 3058static bool brcms_c_ps_allowed(struct brcms_c_info *wlc) 3059{ 3060 struct brcms_bss_cfg *cfg = wlc->bsscfg; 3061 3062 /* disallow PS when one of the following global conditions meets */ 3063 if (!wlc->pub->associated) 3064 return false; 3065 3066 /* disallow PS when one of these meets when not scanning */ 3067 if (wlc->monitor) 3068 return false; 3069 3070 if (cfg->associated) { 3071 /* 3072 * disallow PS when one of the following 3073 * bsscfg specific conditions meets 3074 */ 3075 if (!cfg->BSS) 3076 return false; 3077 3078 return false; 3079 } 3080 3081 return true; 3082} 3083 3084static void brcms_c_statsupd(struct brcms_c_info *wlc) 3085{ 3086 int i; 3087 struct macstat macstats; 3088#ifdef BCMDBG 3089 u16 delta; 3090 u16 rxf0ovfl; 3091 u16 txfunfl[NFIFO]; 3092#endif /* BCMDBG */ 3093 3094 /* if driver down, make no sense to update stats */ 3095 if (!wlc->pub->up) 3096 return; 3097 3098#ifdef BCMDBG 3099 /* save last rx fifo 0 overflow count */ 3100 rxf0ovfl = wlc->core->macstat_snapshot->rxf0ovfl; 3101 3102 /* save last tx fifo underflow count */ 3103 for (i = 0; i < NFIFO; i++) 3104 txfunfl[i] = wlc->core->macstat_snapshot->txfunfl[i]; 3105#endif /* BCMDBG */ 3106 3107 /* Read mac stats from contiguous shared memory */ 3108 brcms_b_copyfrom_objmem(wlc->hw, M_UCODE_MACSTAT, &macstats, 3109 sizeof(struct macstat), OBJADDR_SHM_SEL); 3110 3111#ifdef BCMDBG 3112 /* check for rx fifo 0 overflow */ 3113 delta = (u16) (wlc->core->macstat_snapshot->rxf0ovfl - rxf0ovfl); 3114 if (delta) 3115 wiphy_err(wlc->wiphy, "wl%d: %u rx fifo 0 overflows!\n", 3116 wlc->pub->unit, delta); 3117 3118 /* check for tx fifo underflows */ 3119 for (i = 0; i < NFIFO; i++) { 3120 delta = 3121 (u16) (wlc->core->macstat_snapshot->txfunfl[i] - 3122 txfunfl[i]); 3123 if (delta) 3124 wiphy_err(wlc->wiphy, "wl%d: %u tx fifo %d underflows!" 3125 "\n", wlc->pub->unit, delta, i); 3126 } 3127#endif /* BCMDBG */ 3128 3129 /* merge counters from dma module */ 3130 for (i = 0; i < NFIFO; i++) { 3131 if (wlc->hw->di[i]) 3132 dma_counterreset(wlc->hw->di[i]); 3133 } 3134} 3135 3136static void brcms_b_reset(struct brcms_hardware *wlc_hw) 3137{ 3138 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit); 3139 3140 /* reset the core */ 3141 if (!brcms_deviceremoved(wlc_hw->wlc)) 3142 brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS); 3143 3144 /* purge the dma rings */ 3145 brcms_c_flushqueues(wlc_hw->wlc); 3146} 3147 3148void brcms_c_reset(struct brcms_c_info *wlc) 3149{ 3150 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit); 3151 3152 /* slurp up hw mac counters before core reset */ 3153 brcms_c_statsupd(wlc); 3154 3155 /* reset our snapshot of macstat counters */ 3156 memset((char *)wlc->core->macstat_snapshot, 0, 3157 sizeof(struct macstat)); 3158 3159 brcms_b_reset(wlc->hw); 3160} 3161 3162/* Return the channel the driver should initialize during brcms_c_init. 3163 * the channel may have to be changed from the currently configured channel 3164 * if other configurations are in conflict (bandlocked, 11n mode disabled, 3165 * invalid channel for current country, etc.) 3166 */ 3167static u16 brcms_c_init_chanspec(struct brcms_c_info *wlc) 3168{ 3169 u16 chanspec = 3170 1 | WL_CHANSPEC_BW_20 | WL_CHANSPEC_CTL_SB_NONE | 3171 WL_CHANSPEC_BAND_2G; 3172 3173 return chanspec; 3174} 3175 3176void brcms_c_init_scb(struct scb *scb) 3177{ 3178 int i; 3179 3180 memset(scb, 0, sizeof(struct scb)); 3181 scb->flags = SCB_WMECAP | SCB_HTCAP; 3182 for (i = 0; i < NUMPRIO; i++) { 3183 scb->seqnum[i] = 0; 3184 scb->seqctl[i] = 0xFFFF; 3185 } 3186 3187 scb->seqctl_nonqos = 0xFFFF; 3188 scb->magic = SCB_MAGIC; 3189} 3190 3191/* d11 core init 3192 * reset PSM 3193 * download ucode/PCM 3194 * let ucode run to suspended 3195 * download ucode inits 3196 * config other core registers 3197 * init dma 3198 */ 3199static void brcms_b_coreinit(struct brcms_c_info *wlc) 3200{ 3201 struct brcms_hardware *wlc_hw = wlc->hw; 3202 struct d11regs __iomem *regs; 3203 u32 sflags; 3204 uint bcnint_us; 3205 uint i = 0; 3206 bool fifosz_fixup = false; 3207 int err = 0; 3208 u16 buf[NFIFO]; 3209 struct wiphy *wiphy = wlc->wiphy; 3210 struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode; 3211 3212 regs = wlc_hw->regs; 3213 3214 BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit); 3215 3216 /* reset PSM */ 3217 brcms_b_mctrl(wlc_hw, ~0, (MCTL_IHR_EN | MCTL_PSM_JMP_0 | MCTL_WAKE)); 3218 3219 brcms_ucode_download(wlc_hw); 3220 /* 3221 * FIFOSZ fixup. driver wants to controls the fifo allocation. 3222 */ 3223 fifosz_fixup = true; 3224 3225 /* let the PSM run to the suspended state, set mode to BSS STA */ 3226 W_REG(®s->macintstatus, -1); 3227 brcms_b_mctrl(wlc_hw, ~0, 3228 (MCTL_IHR_EN | MCTL_INFRA | MCTL_PSM_RUN | MCTL_WAKE)); 3229 3230 /* wait for ucode to self-suspend after auto-init */ 3231 SPINWAIT(((R_REG(®s->macintstatus) & MI_MACSSPNDD) == 0), 3232 1000 * 1000); 3233 if ((R_REG(®s->macintstatus) & MI_MACSSPNDD) == 0) 3234 wiphy_err(wiphy, "wl%d: wlc_coreinit: ucode did not self-" 3235 "suspend!\n", wlc_hw->unit); 3236 3237 brcms_c_gpio_init(wlc); 3238 3239 sflags = ai_core_sflags(wlc_hw->sih, 0, 0); 3240 3241 if (D11REV_IS(wlc_hw->corerev, 23)) { 3242 if (BRCMS_ISNPHY(wlc_hw->band)) 3243 brcms_c_write_inits(wlc_hw, ucode->d11n0initvals16); 3244 else 3245 wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev" 3246 " %d\n", __func__, wlc_hw->unit, 3247 wlc_hw->corerev); 3248 } else if (D11REV_IS(wlc_hw->corerev, 24)) { 3249 if (BRCMS_ISLCNPHY(wlc_hw->band)) 3250 brcms_c_write_inits(wlc_hw, ucode->d11lcn0initvals24); 3251 else 3252 wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev" 3253 " %d\n", __func__, wlc_hw->unit, 3254 wlc_hw->corerev); 3255 } else { 3256 wiphy_err(wiphy, "%s: wl%d: unsupported corerev %d\n", 3257 __func__, wlc_hw->unit, wlc_hw->corerev); 3258 } 3259 3260 /* For old ucode, txfifo sizes needs to be modified(increased) */ 3261 if (fifosz_fixup == true) 3262 brcms_b_corerev_fifofixup(wlc_hw); 3263 3264 /* check txfifo allocations match between ucode and driver */ 3265 buf[TX_AC_BE_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE0); 3266 if (buf[TX_AC_BE_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]) { 3267 i = TX_AC_BE_FIFO; 3268 err = -1; 3269 } 3270 buf[TX_AC_VI_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE1); 3271 if (buf[TX_AC_VI_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]) { 3272 i = TX_AC_VI_FIFO; 3273 err = -1; 3274 } 3275 buf[TX_AC_BK_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE2); 3276 buf[TX_AC_VO_FIFO] = (buf[TX_AC_BK_FIFO] >> 8) & 0xff; 3277 buf[TX_AC_BK_FIFO] &= 0xff; 3278 if (buf[TX_AC_BK_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BK_FIFO]) { 3279 i = TX_AC_BK_FIFO; 3280 err = -1; 3281 } 3282 if (buf[TX_AC_VO_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO]) { 3283 i = TX_AC_VO_FIFO; 3284 err = -1; 3285 } 3286 buf[TX_BCMC_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE3); 3287 buf[TX_ATIM_FIFO] = (buf[TX_BCMC_FIFO] >> 8) & 0xff; 3288 buf[TX_BCMC_FIFO] &= 0xff; 3289 if (buf[TX_BCMC_FIFO] != wlc_hw->xmtfifo_sz[TX_BCMC_FIFO]) { 3290 i = TX_BCMC_FIFO; 3291 err = -1; 3292 } 3293 if (buf[TX_ATIM_FIFO] != wlc_hw->xmtfifo_sz[TX_ATIM_FIFO]) { 3294 i = TX_ATIM_FIFO; 3295 err = -1; 3296 } 3297 if (err != 0) 3298 wiphy_err(wiphy, "wlc_coreinit: txfifo mismatch: ucode size %d" 3299 " driver size %d index %d\n", buf[i], 3300 wlc_hw->xmtfifo_sz[i], i); 3301 3302 /* make sure we can still talk to the mac */ 3303 WARN_ON(R_REG(®s->maccontrol) == 0xffffffff); 3304 3305 /* band-specific inits done by wlc_bsinit() */ 3306 3307 /* Set up frame burst size and antenna swap threshold init values */ 3308 brcms_b_write_shm(wlc_hw, M_MBURST_SIZE, MAXTXFRAMEBURST); 3309 brcms_b_write_shm(wlc_hw, M_MAX_ANTCNT, ANTCNT); 3310 3311 /* enable one rx interrupt per received frame */ 3312 W_REG(®s->intrcvlazy[0], (1 << IRL_FC_SHIFT)); 3313 3314 /* set the station mode (BSS STA) */ 3315 brcms_b_mctrl(wlc_hw, 3316 (MCTL_INFRA | MCTL_DISCARD_PMQ | MCTL_AP), 3317 (MCTL_INFRA | MCTL_DISCARD_PMQ)); 3318 3319 /* set up Beacon interval */ 3320 bcnint_us = 0x8000 << 10; 3321 W_REG(®s->tsf_cfprep, (bcnint_us << CFPREP_CBI_SHIFT)); 3322 W_REG(®s->tsf_cfpstart, bcnint_us); 3323 W_REG(®s->macintstatus, MI_GP1); 3324 3325 /* write interrupt mask */ 3326 W_REG(®s->intctrlregs[RX_FIFO].intmask, DEF_RXINTMASK); 3327 3328 /* allow the MAC to control the PHY clock (dynamic on/off) */ 3329 brcms_b_macphyclk_set(wlc_hw, ON); 3330 3331 /* program dynamic clock control fast powerup delay register */ 3332 wlc->fastpwrup_dly = ai_clkctl_fast_pwrup_delay(wlc_hw->sih); 3333 W_REG(®s->scc_fastpwrup_dly, wlc->fastpwrup_dly); 3334 3335 /* tell the ucode the corerev */ 3336 brcms_b_write_shm(wlc_hw, M_MACHW_VER, (u16) wlc_hw->corerev); 3337 3338 /* tell the ucode MAC capabilities */ 3339 brcms_b_write_shm(wlc_hw, M_MACHW_CAP_L, 3340 (u16) (wlc_hw->machwcap & 0xffff)); 3341 brcms_b_write_shm(wlc_hw, M_MACHW_CAP_H, 3342 (u16) ((wlc_hw-> 3343 machwcap >> 16) & 0xffff)); 3344 3345 /* write retry limits to SCR, this done after PSM init */ 3346 W_REG(®s->objaddr, OBJADDR_SCR_SEL | S_DOT11_SRC_LMT); 3347 (void)R_REG(®s->objaddr); 3348 W_REG(®s->objdata, wlc_hw->SRL); 3349 W_REG(®s->objaddr, OBJADDR_SCR_SEL | S_DOT11_LRC_LMT); 3350 (void)R_REG(®s->objaddr); 3351 W_REG(®s->objdata, wlc_hw->LRL); 3352 3353 /* write rate fallback retry limits */ 3354 brcms_b_write_shm(wlc_hw, M_SFRMTXCNTFBRTHSD, wlc_hw->SFBL); 3355 brcms_b_write_shm(wlc_hw, M_LFRMTXCNTFBRTHSD, wlc_hw->LFBL); 3356 3357 AND_REG(®s->ifs_ctl, 0x0FFF); 3358 W_REG(®s->ifs_aifsn, EDCF_AIFSN_MIN); 3359 3360 /* init the tx dma engines */ 3361 for (i = 0; i < NFIFO; i++) { 3362 if (wlc_hw->di[i]) 3363 dma_txinit(wlc_hw->di[i]); 3364 } 3365 3366 /* init the rx dma engine(s) and post receive buffers */ 3367 dma_rxinit(wlc_hw->di[RX_FIFO]); 3368 dma_rxfill(wlc_hw->di[RX_FIFO]); 3369} 3370 3371void 3372static brcms_b_init(struct brcms_hardware *wlc_hw, u16 chanspec) { 3373 u32 macintmask; 3374 bool fastclk; 3375 struct brcms_c_info *wlc = wlc_hw->wlc; 3376 3377 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit); 3378 3379 /* request FAST clock if not on */ 3380 fastclk = wlc_hw->forcefastclk; 3381 if (!fastclk) 3382 brcms_b_clkctl_clk(wlc_hw, CLK_FAST); 3383 3384 /* disable interrupts */ 3385 macintmask = brcms_intrsoff(wlc->wl); 3386 3387 /* set up the specified band and chanspec */ 3388 brcms_c_setxband(wlc_hw, chspec_bandunit(chanspec)); 3389 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec); 3390 3391 /* do one-time phy inits and calibration */ 3392 wlc_phy_cal_init(wlc_hw->band->pi); 3393 3394 /* core-specific initialization */ 3395 brcms_b_coreinit(wlc); 3396 3397 /* band-specific inits */ 3398 brcms_b_bsinit(wlc, chanspec); 3399 3400 /* restore macintmask */ 3401 brcms_intrsrestore(wlc->wl, macintmask); 3402 3403 /* seed wake_override with BRCMS_WAKE_OVERRIDE_MACSUSPEND since the mac 3404 * is suspended and brcms_c_enable_mac() will clear this override bit. 3405 */ 3406 mboolset(wlc_hw->wake_override, BRCMS_WAKE_OVERRIDE_MACSUSPEND); 3407 3408 /* 3409 * initialize mac_suspend_depth to 1 to match ucode 3410 * initial suspended state 3411 */ 3412 wlc_hw->mac_suspend_depth = 1; 3413 3414 /* restore the clk */ 3415 if (!fastclk) 3416 brcms_b_clkctl_clk(wlc_hw, CLK_DYNAMIC); 3417} 3418 3419static void brcms_c_set_phy_chanspec(struct brcms_c_info *wlc, 3420 u16 chanspec) 3421{ 3422 /* Save our copy of the chanspec */ 3423 wlc->chanspec = chanspec; 3424 3425 /* Set the chanspec and power limits for this locale */ 3426 brcms_c_channel_set_chanspec(wlc->cmi, chanspec, BRCMS_TXPWR_MAX); 3427 3428 if (wlc->stf->ss_algosel_auto) 3429 brcms_c_stf_ss_algo_channel_get(wlc, &wlc->stf->ss_algo_channel, 3430 chanspec); 3431 3432 brcms_c_stf_ss_update(wlc, wlc->band); 3433} 3434 3435static void 3436brcms_default_rateset(struct brcms_c_info *wlc, struct brcms_c_rateset *rs) 3437{ 3438 brcms_c_rateset_default(rs, NULL, wlc->band->phytype, 3439 wlc->band->bandtype, false, BRCMS_RATE_MASK_FULL, 3440 (bool) (wlc->pub->_n_enab & SUPPORT_11N), 3441 brcms_chspec_bw(wlc->default_bss->chanspec), 3442 wlc->stf->txstreams); 3443} 3444 3445/* derive wlc->band->basic_rate[] table from 'rateset' */ 3446static void brcms_c_rate_lookup_init(struct brcms_c_info *wlc, 3447 struct brcms_c_rateset *rateset) 3448{ 3449 u8 rate; 3450 u8 mandatory; 3451 u8 cck_basic = 0; 3452 u8 ofdm_basic = 0; 3453 u8 *br = wlc->band->basic_rate; 3454 uint i; 3455 3456 /* incoming rates are in 500kbps units as in 802.11 Supported Rates */ 3457 memset(br, 0, BRCM_MAXRATE + 1); 3458 3459 /* For each basic rate in the rates list, make an entry in the 3460 * best basic lookup. 3461 */ 3462 for (i = 0; i < rateset->count; i++) { 3463 /* only make an entry for a basic rate */ 3464 if (!(rateset->rates[i] & BRCMS_RATE_FLAG)) 3465 continue; 3466 3467 /* mask off basic bit */ 3468 rate = (rateset->rates[i] & BRCMS_RATE_MASK); 3469 3470 if (rate > BRCM_MAXRATE) { 3471 wiphy_err(wlc->wiphy, "brcms_c_rate_lookup_init: " 3472 "invalid rate 0x%X in rate set\n", 3473 rateset->rates[i]); 3474 continue; 3475 } 3476 3477 br[rate] = rate; 3478 } 3479 3480 /* The rate lookup table now has non-zero entries for each 3481 * basic rate, equal to the basic rate: br[basicN] = basicN 3482 * 3483 * To look up the best basic rate corresponding to any 3484 * particular rate, code can use the basic_rate table 3485 * like this 3486 * 3487 * basic_rate = wlc->band->basic_rate[tx_rate] 3488 * 3489 * Make sure there is a best basic rate entry for 3490 * every rate by walking up the table from low rates 3491 * to high, filling in holes in the lookup table 3492 */ 3493 3494 for (i = 0; i < wlc->band->hw_rateset.count; i++) { 3495 rate = wlc->band->hw_rateset.rates[i]; 3496 3497 if (br[rate] != 0) { 3498 /* This rate is a basic rate. 3499 * Keep track of the best basic rate so far by 3500 * modulation type. 3501 */ 3502 if (is_ofdm_rate(rate)) 3503 ofdm_basic = rate; 3504 else 3505 cck_basic = rate; 3506 3507 continue; 3508 } 3509 3510 /* This rate is not a basic rate so figure out the 3511 * best basic rate less than this rate and fill in 3512 * the hole in the table 3513 */ 3514 3515 br[rate] = is_ofdm_rate(rate) ? ofdm_basic : cck_basic; 3516 3517 if (br[rate] != 0) 3518 continue; 3519 3520 if (is_ofdm_rate(rate)) { 3521 /* 3522 * In 11g and 11a, the OFDM mandatory rates 3523 * are 6, 12, and 24 Mbps 3524 */ 3525 if (rate >= BRCM_RATE_24M) 3526 mandatory = BRCM_RATE_24M; 3527 else if (rate >= BRCM_RATE_12M) 3528 mandatory = BRCM_RATE_12M; 3529 else 3530 mandatory = BRCM_RATE_6M; 3531 } else { 3532 /* In 11b, all CCK rates are mandatory 1 - 11 Mbps */ 3533 mandatory = rate; 3534 } 3535 3536 br[rate] = mandatory; 3537 } 3538} 3539 3540static void brcms_c_bandinit_ordered(struct brcms_c_info *wlc, 3541 u16 chanspec) 3542{ 3543 struct brcms_c_rateset default_rateset; 3544 uint parkband; 3545 uint i, band_order[2]; 3546 3547 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit); 3548 /* 3549 * We might have been bandlocked during down and the chip 3550 * power-cycled (hibernate). Figure out the right band to park on 3551 */ 3552 if (wlc->bandlocked || wlc->pub->_nbands == 1) { 3553 /* updated in brcms_c_bandlock() */ 3554 parkband = wlc->band->bandunit; 3555 band_order[0] = band_order[1] = parkband; 3556 } else { 3557 /* park on the band of the specified chanspec */ 3558 parkband = chspec_bandunit(chanspec); 3559 3560 /* order so that parkband initialize last */ 3561 band_order[0] = parkband ^ 1; 3562 band_order[1] = parkband; 3563 } 3564 3565 /* make each band operational, software state init */ 3566 for (i = 0; i < wlc->pub->_nbands; i++) { 3567 uint j = band_order[i]; 3568 3569 wlc->band = wlc->bandstate[j]; 3570 3571 brcms_default_rateset(wlc, &default_rateset); 3572 3573 /* fill in hw_rate */ 3574 brcms_c_rateset_filter(&default_rateset, &wlc->band->hw_rateset, 3575 false, BRCMS_RATES_CCK_OFDM, BRCMS_RATE_MASK, 3576 (bool) (wlc->pub->_n_enab & SUPPORT_11N)); 3577 3578 /* init basic rate lookup */ 3579 brcms_c_rate_lookup_init(wlc, &default_rateset); 3580 } 3581 3582 /* sync up phy/radio chanspec */ 3583 brcms_c_set_phy_chanspec(wlc, chanspec); 3584} 3585 3586/* 3587 * Set or clear maccontrol bits MCTL_PROMISC, MCTL_BCNS_PROMISC and 3588 * MCTL_KEEPCONTROL 3589 */ 3590static void brcms_c_mac_promisc(struct brcms_c_info *wlc) 3591{ 3592 u32 promisc_bits = 0; 3593 3594 if (wlc->bcnmisc_monitor) 3595 promisc_bits |= MCTL_BCNS_PROMISC; 3596 3597 if (wlc->monitor) 3598 promisc_bits |= 3599 MCTL_PROMISC | MCTL_BCNS_PROMISC | MCTL_KEEPCONTROL; 3600 3601 brcms_b_mctrl(wlc->hw, 3602 MCTL_PROMISC | MCTL_BCNS_PROMISC | MCTL_KEEPCONTROL, 3603 promisc_bits); 3604} 3605 3606void brcms_c_mac_bcn_promisc_change(struct brcms_c_info *wlc, bool promisc) 3607{ 3608 wlc->bcnmisc_monitor = promisc; 3609 brcms_c_mac_promisc(wlc); 3610} 3611 3612/* 3613 * ucode, hwmac update 3614 * Channel dependent updates for ucode and hw 3615 */ 3616static void brcms_c_ucode_mac_upd(struct brcms_c_info *wlc) 3617{ 3618 /* enable or disable any active IBSSs depending on whether or not 3619 * we are on the home channel 3620 */ 3621 if (wlc->home_chanspec == wlc_phy_chanspec_get(wlc->band->pi)) { 3622 if (wlc->pub->associated) { 3623 /* 3624 * BMAC_NOTE: This is something that should be fixed 3625 * in ucode inits. I think that the ucode inits set 3626 * up the bcn templates and shm values with a bogus 3627 * beacon. This should not be done in the inits. If 3628 * ucode needs to set up a beacon for testing, the 3629 * test routines should write it down, not expect the 3630 * inits to populate a bogus beacon. 3631 */ 3632 if (BRCMS_PHY_11N_CAP(wlc->band)) 3633 brcms_b_write_shm(wlc->hw, 3634 M_BCN_TXTSF_OFFSET, 0); 3635 } 3636 } else { 3637 /* disable an active IBSS if we are not on the home channel */ 3638 } 3639 3640 /* update the various promisc bits */ 3641 brcms_c_mac_promisc(wlc); 3642} 3643 3644static void brcms_c_write_rate_shm(struct brcms_c_info *wlc, u8 rate, 3645 u8 basic_rate) 3646{ 3647 u8 phy_rate, index; 3648 u8 basic_phy_rate, basic_index; 3649 u16 dir_table, basic_table; 3650 u16 basic_ptr; 3651 3652 /* Shared memory address for the table we are reading */ 3653 dir_table = is_ofdm_rate(basic_rate) ? M_RT_DIRMAP_A : M_RT_DIRMAP_B; 3654 3655 /* Shared memory address for the table we are writing */ 3656 basic_table = is_ofdm_rate(rate) ? M_RT_BBRSMAP_A : M_RT_BBRSMAP_B; 3657 3658 /* 3659 * for a given rate, the LS-nibble of the PLCP SIGNAL field is 3660 * the index into the rate table. 3661 */ 3662 phy_rate = rate_info[rate] & BRCMS_RATE_MASK; 3663 basic_phy_rate = rate_info[basic_rate] & BRCMS_RATE_MASK; 3664 index = phy_rate & 0xf; 3665 basic_index = basic_phy_rate & 0xf; 3666 3667 /* Find the SHM pointer to the ACK rate entry by looking in the 3668 * Direct-map Table 3669 */ 3670 basic_ptr = brcms_b_read_shm(wlc->hw, (dir_table + basic_index * 2)); 3671 3672 /* Update the SHM BSS-basic-rate-set mapping table with the pointer 3673 * to the correct basic rate for the given incoming rate 3674 */ 3675 brcms_b_write_shm(wlc->hw, (basic_table + index * 2), basic_ptr); 3676} 3677 3678static const struct brcms_c_rateset * 3679brcms_c_rateset_get_hwrs(struct brcms_c_info *wlc) 3680{ 3681 const struct brcms_c_rateset *rs_dflt; 3682 3683 if (BRCMS_PHY_11N_CAP(wlc->band)) { 3684 if (wlc->band->bandtype == BRCM_BAND_5G) 3685 rs_dflt = &ofdm_mimo_rates; 3686 else 3687 rs_dflt = &cck_ofdm_mimo_rates; 3688 } else if (wlc->band->gmode) 3689 rs_dflt = &cck_ofdm_rates; 3690 else 3691 rs_dflt = &cck_rates; 3692 3693 return rs_dflt; 3694} 3695 3696static void brcms_c_set_ratetable(struct brcms_c_info *wlc) 3697{ 3698 const struct brcms_c_rateset *rs_dflt; 3699 struct brcms_c_rateset rs; 3700 u8 rate, basic_rate; 3701 uint i; 3702 3703 rs_dflt = brcms_c_rateset_get_hwrs(wlc); 3704 3705 brcms_c_rateset_copy(rs_dflt, &rs); 3706 brcms_c_rateset_mcs_upd(&rs, wlc->stf->txstreams); 3707 3708 /* walk the phy rate table and update SHM basic rate lookup table */ 3709 for (i = 0; i < rs.count; i++) { 3710 rate = rs.rates[i] & BRCMS_RATE_MASK; 3711 3712 /* for a given rate brcms_basic_rate returns the rate at 3713 * which a response ACK/CTS should be sent. 3714 */ 3715 basic_rate = brcms_basic_rate(wlc, rate); 3716 if (basic_rate == 0) 3717 /* This should only happen if we are using a 3718 * restricted rateset. 3719 */ 3720 basic_rate = rs.rates[0] & BRCMS_RATE_MASK; 3721 3722 brcms_c_write_rate_shm(wlc, rate, basic_rate); 3723 } 3724} 3725 3726/* band-specific init */ 3727static void brcms_c_bsinit(struct brcms_c_info *wlc) 3728{ 3729 BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", 3730 wlc->pub->unit, wlc->band->bandunit); 3731 3732 /* write ucode ACK/CTS rate table */ 3733 brcms_c_set_ratetable(wlc); 3734 3735 /* update some band specific mac configuration */ 3736 brcms_c_ucode_mac_upd(wlc); 3737 3738 /* init antenna selection */ 3739 brcms_c_antsel_init(wlc->asi); 3740 3741} 3742 3743/* formula: IDLE_BUSY_RATIO_X_16 = (100-duty_cycle)/duty_cycle*16 */ 3744static int 3745brcms_c_duty_cycle_set(struct brcms_c_info *wlc, int duty_cycle, bool isOFDM, 3746 bool writeToShm) 3747{ 3748 int idle_busy_ratio_x_16 = 0; 3749 uint offset = 3750 isOFDM ? M_TX_IDLE_BUSY_RATIO_X_16_OFDM : 3751 M_TX_IDLE_BUSY_RATIO_X_16_CCK; 3752 if (duty_cycle > 100 || duty_cycle < 0) { 3753 wiphy_err(wlc->wiphy, "wl%d: duty cycle value off limit\n", 3754 wlc->pub->unit); 3755 return -EINVAL; 3756 } 3757 if (duty_cycle) 3758 idle_busy_ratio_x_16 = (100 - duty_cycle) * 16 / duty_cycle; 3759 /* Only write to shared memory when wl is up */ 3760 if (writeToShm) 3761 brcms_b_write_shm(wlc->hw, offset, (u16) idle_busy_ratio_x_16); 3762 3763 if (isOFDM) 3764 wlc->tx_duty_cycle_ofdm = (u16) duty_cycle; 3765 else 3766 wlc->tx_duty_cycle_cck = (u16) duty_cycle; 3767 3768 return 0; 3769} 3770 3771/* 3772 * Initialize the base precedence map for dequeueing 3773 * from txq based on WME settings 3774 */ 3775static void brcms_c_tx_prec_map_init(struct brcms_c_info *wlc) 3776{ 3777 wlc->tx_prec_map = BRCMS_PREC_BMP_ALL; 3778 memset(wlc->fifo2prec_map, 0, NFIFO * sizeof(u16)); 3779 3780 wlc->fifo2prec_map[TX_AC_BK_FIFO] = BRCMS_PREC_BMP_AC_BK; 3781 wlc->fifo2prec_map[TX_AC_BE_FIFO] = BRCMS_PREC_BMP_AC_BE; 3782 wlc->fifo2prec_map[TX_AC_VI_FIFO] = BRCMS_PREC_BMP_AC_VI; 3783 wlc->fifo2prec_map[TX_AC_VO_FIFO] = BRCMS_PREC_BMP_AC_VO; 3784} 3785 3786static void 3787brcms_c_txflowcontrol_signal(struct brcms_c_info *wlc, 3788 struct brcms_txq_info *qi, bool on, int prio) 3789{ 3790 /* transmit flowcontrol is not yet implemented */ 3791} 3792 3793static void brcms_c_txflowcontrol_reset(struct brcms_c_info *wlc) 3794{ 3795 struct brcms_txq_info *qi; 3796 3797 for (qi = wlc->tx_queues; qi != NULL; qi = qi->next) { 3798 if (qi->stopped) { 3799 brcms_c_txflowcontrol_signal(wlc, qi, OFF, ALLPRIO); 3800 qi->stopped = 0; 3801 } 3802 } 3803} 3804 3805/* push sw hps and wake state through hardware */ 3806static void brcms_c_set_ps_ctrl(struct brcms_c_info *wlc) 3807{ 3808 u32 v1, v2; 3809 bool hps; 3810 bool awake_before; 3811 3812 hps = brcms_c_ps_allowed(wlc); 3813 3814 BCMMSG(wlc->wiphy, "wl%d: hps %d\n", wlc->pub->unit, hps); 3815 3816 v1 = R_REG(&wlc->regs->maccontrol); 3817 v2 = MCTL_WAKE; 3818 if (hps) 3819 v2 |= MCTL_HPS; 3820 3821 brcms_b_mctrl(wlc->hw, MCTL_WAKE | MCTL_HPS, v2); 3822 3823 awake_before = ((v1 & MCTL_WAKE) || ((v1 & MCTL_HPS) == 0)); 3824 3825 if (!awake_before) 3826 brcms_b_wait_for_wake(wlc->hw); 3827} 3828 3829/* 3830 * Write this BSS config's MAC address to core. 3831 * Updates RXE match engine. 3832 */ 3833static int brcms_c_set_mac(struct brcms_bss_cfg *bsscfg) 3834{ 3835 int err = 0; 3836 struct brcms_c_info *wlc = bsscfg->wlc; 3837 3838 /* enter the MAC addr into the RXE match registers */ 3839 brcms_c_set_addrmatch(wlc, RCM_MAC_OFFSET, bsscfg->cur_etheraddr); 3840 3841 brcms_c_ampdu_macaddr_upd(wlc); 3842 3843 return err; 3844} 3845 3846/* Write the BSS config's BSSID address to core (set_bssid in d11procs.tcl). 3847 * Updates RXE match engine. 3848 */ 3849static void brcms_c_set_bssid(struct brcms_bss_cfg *bsscfg) 3850{ 3851 /* we need to update BSSID in RXE match registers */ 3852 brcms_c_set_addrmatch(bsscfg->wlc, RCM_BSSID_OFFSET, bsscfg->BSSID); 3853} 3854 3855static void brcms_b_set_shortslot(struct brcms_hardware *wlc_hw, bool shortslot) 3856{ 3857 wlc_hw->shortslot = shortslot; 3858 3859 if (wlc_hw->band->bandtype == BRCM_BAND_2G && wlc_hw->up) { 3860 brcms_c_suspend_mac_and_wait(wlc_hw->wlc); 3861 brcms_b_update_slot_timing(wlc_hw, shortslot); 3862 brcms_c_enable_mac(wlc_hw->wlc); 3863 } 3864} 3865 3866/* 3867 * Suspend the the MAC and update the slot timing 3868 * for standard 11b/g (20us slots) or shortslot 11g (9us slots). 3869 */ 3870static void brcms_c_switch_shortslot(struct brcms_c_info *wlc, bool shortslot) 3871{ 3872 /* use the override if it is set */ 3873 if (wlc->shortslot_override != BRCMS_SHORTSLOT_AUTO) 3874 shortslot = (wlc->shortslot_override == BRCMS_SHORTSLOT_ON); 3875 3876 if (wlc->shortslot == shortslot) 3877 return; 3878 3879 wlc->shortslot = shortslot; 3880 3881 brcms_b_set_shortslot(wlc->hw, shortslot); 3882} 3883 3884static void brcms_c_set_home_chanspec(struct brcms_c_info *wlc, u16 chanspec) 3885{ 3886 if (wlc->home_chanspec != chanspec) { 3887 wlc->home_chanspec = chanspec; 3888 3889 if (wlc->bsscfg->associated) 3890 wlc->bsscfg->current_bss->chanspec = chanspec; 3891 } 3892} 3893 3894void 3895brcms_b_set_chanspec(struct brcms_hardware *wlc_hw, u16 chanspec, 3896 bool mute_tx, struct txpwr_limits *txpwr) 3897{ 3898 uint bandunit; 3899 3900 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: 0x%x\n", wlc_hw->unit, chanspec); 3901 3902 wlc_hw->chanspec = chanspec; 3903 3904 /* Switch bands if necessary */ 3905 if (wlc_hw->_nbands > 1) { 3906 bandunit = chspec_bandunit(chanspec); 3907 if (wlc_hw->band->bandunit != bandunit) { 3908 /* brcms_b_setband disables other bandunit, 3909 * use light band switch if not up yet 3910 */ 3911 if (wlc_hw->up) { 3912 wlc_phy_chanspec_radio_set(wlc_hw-> 3913 bandstate[bandunit]-> 3914 pi, chanspec); 3915 brcms_b_setband(wlc_hw, bandunit, chanspec); 3916 } else { 3917 brcms_c_setxband(wlc_hw, bandunit); 3918 } 3919 } 3920 } 3921 3922 wlc_phy_initcal_enable(wlc_hw->band->pi, !mute_tx); 3923 3924 if (!wlc_hw->up) { 3925 if (wlc_hw->clk) 3926 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr, 3927 chanspec); 3928 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec); 3929 } else { 3930 wlc_phy_chanspec_set(wlc_hw->band->pi, chanspec); 3931 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr, chanspec); 3932 3933 /* Update muting of the channel */ 3934 brcms_b_mute(wlc_hw, mute_tx); 3935 } 3936} 3937 3938/* switch to and initialize new band */ 3939static void brcms_c_setband(struct brcms_c_info *wlc, 3940 uint bandunit) 3941{ 3942 wlc->band = wlc->bandstate[bandunit]; 3943 3944 if (!wlc->pub->up) 3945 return; 3946 3947 /* wait for at least one beacon before entering sleeping state */ 3948 brcms_c_set_ps_ctrl(wlc); 3949 3950 /* band-specific initializations */ 3951 brcms_c_bsinit(wlc); 3952} 3953 3954static void brcms_c_set_chanspec(struct brcms_c_info *wlc, u16 chanspec) 3955{ 3956 uint bandunit; 3957 bool switchband = false; 3958 u16 old_chanspec = wlc->chanspec; 3959 3960 if (!brcms_c_valid_chanspec_db(wlc->cmi, chanspec)) { 3961 wiphy_err(wlc->wiphy, "wl%d: %s: Bad channel %d\n", 3962 wlc->pub->unit, __func__, CHSPEC_CHANNEL(chanspec)); 3963 return; 3964 } 3965 3966 /* Switch bands if necessary */ 3967 if (wlc->pub->_nbands > 1) { 3968 bandunit = chspec_bandunit(chanspec); 3969 if (wlc->band->bandunit != bandunit || wlc->bandinit_pending) { 3970 switchband = true; 3971 if (wlc->bandlocked) { 3972 wiphy_err(wlc->wiphy, "wl%d: %s: chspec %d " 3973 "band is locked!\n", 3974 wlc->pub->unit, __func__, 3975 CHSPEC_CHANNEL(chanspec)); 3976 return; 3977 } 3978 /* 3979 * should the setband call come after the 3980 * brcms_b_chanspec() ? if the setband updates 3981 * (brcms_c_bsinit) use low level calls to inspect and 3982 * set state, the state inspected may be from the wrong 3983 * band, or the following brcms_b_set_chanspec() may 3984 * undo the work. 3985 */ 3986 brcms_c_setband(wlc, bandunit); 3987 } 3988 } 3989 3990 /* sync up phy/radio chanspec */ 3991 brcms_c_set_phy_chanspec(wlc, chanspec); 3992 3993 /* init antenna selection */ 3994 if (brcms_chspec_bw(old_chanspec) != brcms_chspec_bw(chanspec)) { 3995 brcms_c_antsel_init(wlc->asi); 3996 3997 /* Fix the hardware rateset based on bw. 3998 * Mainly add MCS32 for 40Mhz, remove MCS 32 for 20Mhz 3999 */ 4000 brcms_c_rateset_bw_mcs_filter(&wlc->band->hw_rateset, 4001 wlc->band->mimo_cap_40 ? brcms_chspec_bw(chanspec) : 0); 4002 } 4003 4004 /* update some mac configuration since chanspec changed */ 4005 brcms_c_ucode_mac_upd(wlc); 4006} 4007 4008/* 4009 * This function changes the phytxctl for beacon based on current 4010 * beacon ratespec AND txant setting as per this table: 4011 * ratespec CCK ant = wlc->stf->txant 4012 * OFDM ant = 3 4013 */ 4014void brcms_c_beacon_phytxctl_txant_upd(struct brcms_c_info *wlc, 4015 u32 bcn_rspec) 4016{ 4017 u16 phyctl; 4018 u16 phytxant = wlc->stf->phytxant; 4019 u16 mask = PHY_TXC_ANT_MASK; 4020 4021 /* for non-siso rates or default setting, use the available chains */ 4022 if (BRCMS_PHY_11N_CAP(wlc->band)) 4023 phytxant = brcms_c_stf_phytxchain_sel(wlc, bcn_rspec); 4024 4025 phyctl = brcms_b_read_shm(wlc->hw, M_BCN_PCTLWD); 4026 phyctl = (phyctl & ~mask) | phytxant; 4027 brcms_b_write_shm(wlc->hw, M_BCN_PCTLWD, phyctl); 4028} 4029 4030/* 4031 * centralized protection config change function to simplify debugging, no 4032 * consistency checking this should be called only on changes to avoid overhead 4033 * in periodic function 4034 */ 4035void brcms_c_protection_upd(struct brcms_c_info *wlc, uint idx, int val) 4036{ 4037 BCMMSG(wlc->wiphy, "idx %d, val %d\n", idx, val); 4038 4039 switch (idx) { 4040 case BRCMS_PROT_G_SPEC: 4041 wlc->protection->_g = (bool) val; 4042 break; 4043 case BRCMS_PROT_G_OVR: 4044 wlc->protection->g_override = (s8) val; 4045 break; 4046 case BRCMS_PROT_G_USER: 4047 wlc->protection->gmode_user = (u8) val; 4048 break; 4049 case BRCMS_PROT_OVERLAP: 4050 wlc->protection->overlap = (s8) val; 4051 break; 4052 case BRCMS_PROT_N_USER: 4053 wlc->protection->nmode_user = (s8) val; 4054 break; 4055 case BRCMS_PROT_N_CFG: 4056 wlc->protection->n_cfg = (s8) val; 4057 break; 4058 case BRCMS_PROT_N_CFG_OVR: 4059 wlc->protection->n_cfg_override = (s8) val; 4060 break; 4061 case BRCMS_PROT_N_NONGF: 4062 wlc->protection->nongf = (bool) val; 4063 break; 4064 case BRCMS_PROT_N_NONGF_OVR: 4065 wlc->protection->nongf_override = (s8) val; 4066 break; 4067 case BRCMS_PROT_N_PAM_OVR: 4068 wlc->protection->n_pam_override = (s8) val; 4069 break; 4070 case BRCMS_PROT_N_OBSS: 4071 wlc->protection->n_obss = (bool) val; 4072 break; 4073 4074 default: 4075 break; 4076 } 4077 4078} 4079 4080static void brcms_c_ht_update_sgi_rx(struct brcms_c_info *wlc, int val) 4081{ 4082 if (wlc->pub->up) { 4083 brcms_c_update_beacon(wlc); 4084 brcms_c_update_probe_resp(wlc, true); 4085 } 4086} 4087 4088static void brcms_c_ht_update_ldpc(struct brcms_c_info *wlc, s8 val) 4089{ 4090 wlc->stf->ldpc = val; 4091 4092 if (wlc->pub->up) { 4093 brcms_c_update_beacon(wlc); 4094 brcms_c_update_probe_resp(wlc, true); 4095 wlc_phy_ldpc_override_set(wlc->band->pi, (val ? true : false)); 4096 } 4097} 4098 4099void brcms_c_wme_setparams(struct brcms_c_info *wlc, u16 aci, 4100 const struct ieee80211_tx_queue_params *params, 4101 bool suspend) 4102{ 4103 int i; 4104 struct shm_acparams acp_shm; 4105 u16 *shm_entry; 4106 4107 /* Only apply params if the core is out of reset and has clocks */ 4108 if (!wlc->clk) { 4109 wiphy_err(wlc->wiphy, "wl%d: %s : no-clock\n", wlc->pub->unit, 4110 __func__); 4111 return; 4112 } 4113 4114 memset((char *)&acp_shm, 0, sizeof(struct shm_acparams)); 4115 /* fill in shm ac params struct */ 4116 acp_shm.txop = params->txop; 4117 /* convert from units of 32us to us for ucode */ 4118 wlc->edcf_txop[aci & 0x3] = acp_shm.txop = 4119 EDCF_TXOP2USEC(acp_shm.txop); 4120 acp_shm.aifs = (params->aifs & EDCF_AIFSN_MASK); 4121 4122 if (aci == IEEE80211_AC_VI && acp_shm.txop == 0 4123 && acp_shm.aifs < EDCF_AIFSN_MAX) 4124 acp_shm.aifs++; 4125 4126 if (acp_shm.aifs < EDCF_AIFSN_MIN 4127 || acp_shm.aifs > EDCF_AIFSN_MAX) { 4128 wiphy_err(wlc->wiphy, "wl%d: edcf_setparams: bad " 4129 "aifs %d\n", wlc->pub->unit, acp_shm.aifs); 4130 } else { 4131 acp_shm.cwmin = params->cw_min; 4132 acp_shm.cwmax = params->cw_max; 4133 acp_shm.cwcur = acp_shm.cwmin; 4134 acp_shm.bslots = 4135 R_REG(&wlc->regs->tsf_random) & acp_shm.cwcur; 4136 acp_shm.reggap = acp_shm.bslots + acp_shm.aifs; 4137 /* Indicate the new params to the ucode */ 4138 acp_shm.status = brcms_b_read_shm(wlc->hw, (M_EDCF_QINFO + 4139 wme_ac2fifo[aci] * 4140 M_EDCF_QLEN + 4141 M_EDCF_STATUS_OFF)); 4142 acp_shm.status |= WME_STATUS_NEWAC; 4143 4144 /* Fill in shm acparam table */ 4145 shm_entry = (u16 *) &acp_shm; 4146 for (i = 0; i < (int)sizeof(struct shm_acparams); i += 2) 4147 brcms_b_write_shm(wlc->hw, 4148 M_EDCF_QINFO + 4149 wme_ac2fifo[aci] * M_EDCF_QLEN + i, 4150 *shm_entry++); 4151 } 4152 4153 if (suspend) { 4154 brcms_c_suspend_mac_and_wait(wlc); 4155 brcms_c_enable_mac(wlc); 4156 } 4157} 4158 4159static void brcms_c_edcf_setparams(struct brcms_c_info *wlc, bool suspend) 4160{ 4161 u16 aci; 4162 int i_ac; 4163 struct ieee80211_tx_queue_params txq_pars; 4164 static const struct edcf_acparam default_edcf_acparams[] = { 4165 {EDCF_AC_BE_ACI_STA, EDCF_AC_BE_ECW_STA, EDCF_AC_BE_TXOP_STA}, 4166 {EDCF_AC_BK_ACI_STA, EDCF_AC_BK_ECW_STA, EDCF_AC_BK_TXOP_STA}, 4167 {EDCF_AC_VI_ACI_STA, EDCF_AC_VI_ECW_STA, EDCF_AC_VI_TXOP_STA}, 4168 {EDCF_AC_VO_ACI_STA, EDCF_AC_VO_ECW_STA, EDCF_AC_VO_TXOP_STA} 4169 }; /* ucode needs these parameters during its initialization */ 4170 const struct edcf_acparam *edcf_acp = &default_edcf_acparams[0]; 4171 4172 for (i_ac = 0; i_ac < IEEE80211_NUM_ACS; i_ac++, edcf_acp++) { 4173 /* find out which ac this set of params applies to */ 4174 aci = (edcf_acp->ACI & EDCF_ACI_MASK) >> EDCF_ACI_SHIFT; 4175 4176 /* fill in shm ac params struct */ 4177 txq_pars.txop = edcf_acp->TXOP; 4178 txq_pars.aifs = edcf_acp->ACI; 4179 4180 /* CWmin = 2^(ECWmin) - 1 */ 4181 txq_pars.cw_min = EDCF_ECW2CW(edcf_acp->ECW & EDCF_ECWMIN_MASK); 4182 /* CWmax = 2^(ECWmax) - 1 */ 4183 txq_pars.cw_max = EDCF_ECW2CW((edcf_acp->ECW & EDCF_ECWMAX_MASK) 4184 >> EDCF_ECWMAX_SHIFT); 4185 brcms_c_wme_setparams(wlc, aci, &txq_pars, suspend); 4186 } 4187 4188 if (suspend) { 4189 brcms_c_suspend_mac_and_wait(wlc); 4190 brcms_c_enable_mac(wlc); 4191 } 4192} 4193 4194static void brcms_c_radio_monitor_start(struct brcms_c_info *wlc) 4195{ 4196 /* Don't start the timer if HWRADIO feature is disabled */ 4197 if (wlc->radio_monitor) 4198 return; 4199 4200 wlc->radio_monitor = true; 4201 brcms_b_pllreq(wlc->hw, true, BRCMS_PLLREQ_RADIO_MON); 4202 brcms_add_timer(wlc->radio_timer, TIMER_INTERVAL_RADIOCHK, true); 4203} 4204 4205static bool brcms_c_radio_monitor_stop(struct brcms_c_info *wlc) 4206{ 4207 if (!wlc->radio_monitor) 4208 return true; 4209 4210 wlc->radio_monitor = false; 4211 brcms_b_pllreq(wlc->hw, false, BRCMS_PLLREQ_RADIO_MON); 4212 return brcms_del_timer(wlc->radio_timer); 4213} 4214 4215/* read hwdisable state and propagate to wlc flag */ 4216static void brcms_c_radio_hwdisable_upd(struct brcms_c_info *wlc) 4217{ 4218 if (wlc->pub->hw_off) 4219 return; 4220 4221 if (brcms_b_radio_read_hwdisabled(wlc->hw)) 4222 mboolset(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE); 4223 else 4224 mboolclr(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE); 4225} 4226 4227/* update hwradio status and return it */ 4228bool brcms_c_check_radio_disabled(struct brcms_c_info *wlc) 4229{ 4230 brcms_c_radio_hwdisable_upd(wlc); 4231 4232 return mboolisset(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE) ? 4233 true : false; 4234} 4235 4236/* periodical query hw radio button while driver is "down" */ 4237static void brcms_c_radio_timer(void *arg) 4238{ 4239 struct brcms_c_info *wlc = (struct brcms_c_info *) arg; 4240 4241 if (brcms_deviceremoved(wlc)) { 4242 wiphy_err(wlc->wiphy, "wl%d: %s: dead chip\n", wlc->pub->unit, 4243 __func__); 4244 brcms_down(wlc->wl); 4245 return; 4246 } 4247 4248 brcms_c_radio_hwdisable_upd(wlc); 4249} 4250 4251/* common low-level watchdog code */ 4252static void brcms_b_watchdog(void *arg) 4253{ 4254 struct brcms_c_info *wlc = (struct brcms_c_info *) arg; 4255 struct brcms_hardware *wlc_hw = wlc->hw; 4256 4257 BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit); 4258 4259 if (!wlc_hw->up) 4260 return; 4261 4262 /* increment second count */ 4263 wlc_hw->now++; 4264 4265 /* Check for FIFO error interrupts */ 4266 brcms_b_fifoerrors(wlc_hw); 4267 4268 /* make sure RX dma has buffers */ 4269 dma_rxfill(wlc->hw->di[RX_FIFO]); 4270 4271 wlc_phy_watchdog(wlc_hw->band->pi); 4272} 4273 4274/* common watchdog code */ 4275static void brcms_c_watchdog(void *arg) 4276{ 4277 struct brcms_c_info *wlc = (struct brcms_c_info *) arg; 4278 4279 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit); 4280 4281 if (!wlc->pub->up) 4282 return; 4283 4284 if (brcms_deviceremoved(wlc)) { 4285 wiphy_err(wlc->wiphy, "wl%d: %s: dead chip\n", wlc->pub->unit, 4286 __func__); 4287 brcms_down(wlc->wl); 4288 return; 4289 } 4290 4291 /* increment second count */ 4292 wlc->pub->now++; 4293 4294 brcms_c_radio_hwdisable_upd(wlc); 4295 /* if radio is disable, driver may be down, quit here */ 4296 if (wlc->pub->radio_disabled) 4297 return; 4298 4299 brcms_b_watchdog(wlc); 4300 4301 /* 4302 * occasionally sample mac stat counters to 4303 * detect 16-bit counter wrap 4304 */ 4305 if ((wlc->pub->now % SW_TIMER_MAC_STAT_UPD) == 0) 4306 brcms_c_statsupd(wlc); 4307 4308 if (BRCMS_ISNPHY(wlc->band) && 4309 ((wlc->pub->now - wlc->tempsense_lasttime) >= 4310 BRCMS_TEMPSENSE_PERIOD)) { 4311 wlc->tempsense_lasttime = wlc->pub->now; 4312 brcms_c_tempsense_upd(wlc); 4313 } 4314} 4315 4316static void brcms_c_watchdog_by_timer(void *arg) 4317{ 4318 brcms_c_watchdog(arg); 4319} 4320 4321static bool brcms_c_timers_init(struct brcms_c_info *wlc, int unit) 4322{ 4323 wlc->wdtimer = brcms_init_timer(wlc->wl, brcms_c_watchdog_by_timer, 4324 wlc, "watchdog"); 4325 if (!wlc->wdtimer) { 4326 wiphy_err(wlc->wiphy, "wl%d: wl_init_timer for wdtimer " 4327 "failed\n", unit); 4328 goto fail; 4329 } 4330 4331 wlc->radio_timer = brcms_init_timer(wlc->wl, brcms_c_radio_timer, 4332 wlc, "radio"); 4333 if (!wlc->radio_timer) { 4334 wiphy_err(wlc->wiphy, "wl%d: wl_init_timer for radio_timer " 4335 "failed\n", unit); 4336 goto fail; 4337 } 4338 4339 return true; 4340 4341 fail: 4342 return false; 4343} 4344 4345/* 4346 * Initialize brcms_c_info default values ... 4347 * may get overrides later in this function 4348 */ 4349static void brcms_c_info_init(struct brcms_c_info *wlc, int unit) 4350{ 4351 int i; 4352 4353 /* Save our copy of the chanspec */ 4354 wlc->chanspec = ch20mhz_chspec(1); 4355 4356 /* various 802.11g modes */ 4357 wlc->shortslot = false; 4358 wlc->shortslot_override = BRCMS_SHORTSLOT_AUTO; 4359 4360 brcms_c_protection_upd(wlc, BRCMS_PROT_G_OVR, BRCMS_PROTECTION_AUTO); 4361 brcms_c_protection_upd(wlc, BRCMS_PROT_G_SPEC, false); 4362 4363 brcms_c_protection_upd(wlc, BRCMS_PROT_N_CFG_OVR, 4364 BRCMS_PROTECTION_AUTO); 4365 brcms_c_protection_upd(wlc, BRCMS_PROT_N_CFG, BRCMS_N_PROTECTION_OFF); 4366 brcms_c_protection_upd(wlc, BRCMS_PROT_N_NONGF_OVR, 4367 BRCMS_PROTECTION_AUTO); 4368 brcms_c_protection_upd(wlc, BRCMS_PROT_N_NONGF, false); 4369 brcms_c_protection_upd(wlc, BRCMS_PROT_N_PAM_OVR, AUTO); 4370 4371 brcms_c_protection_upd(wlc, BRCMS_PROT_OVERLAP, 4372 BRCMS_PROTECTION_CTL_OVERLAP); 4373 4374 /* 802.11g draft 4.0 NonERP elt advertisement */ 4375 wlc->include_legacy_erp = true; 4376 4377 wlc->stf->ant_rx_ovr = ANT_RX_DIV_DEF; 4378 wlc->stf->txant = ANT_TX_DEF; 4379 4380 wlc->prb_resp_timeout = BRCMS_PRB_RESP_TIMEOUT; 4381 4382 wlc->usr_fragthresh = DOT11_DEFAULT_FRAG_LEN; 4383 for (i = 0; i < NFIFO; i++) 4384 wlc->fragthresh[i] = DOT11_DEFAULT_FRAG_LEN; 4385 wlc->RTSThresh = DOT11_DEFAULT_RTS_LEN; 4386 4387 /* default rate fallback retry limits */ 4388 wlc->SFBL = RETRY_SHORT_FB; 4389 wlc->LFBL = RETRY_LONG_FB; 4390 4391 /* default mac retry limits */ 4392 wlc->SRL = RETRY_SHORT_DEF; 4393 wlc->LRL = RETRY_LONG_DEF; 4394 4395 /* WME QoS mode is Auto by default */ 4396 wlc->pub->_ampdu = AMPDU_AGG_HOST; 4397 wlc->pub->bcmerror = 0; 4398} 4399 4400static uint brcms_c_attach_module(struct brcms_c_info *wlc) 4401{ 4402 uint err = 0; 4403 uint unit; 4404 unit = wlc->pub->unit; 4405 4406 wlc->asi = brcms_c_antsel_attach(wlc); 4407 if (wlc->asi == NULL) { 4408 wiphy_err(wlc->wiphy, "wl%d: attach: antsel_attach " 4409 "failed\n", unit); 4410 err = 44; 4411 goto fail; 4412 } 4413 4414 wlc->ampdu = brcms_c_ampdu_attach(wlc); 4415 if (wlc->ampdu == NULL) { 4416 wiphy_err(wlc->wiphy, "wl%d: attach: ampdu_attach " 4417 "failed\n", unit); 4418 err = 50; 4419 goto fail; 4420 } 4421 4422 if ((brcms_c_stf_attach(wlc) != 0)) { 4423 wiphy_err(wlc->wiphy, "wl%d: attach: stf_attach " 4424 "failed\n", unit); 4425 err = 68; 4426 goto fail; 4427 } 4428 fail: 4429 return err; 4430} 4431 4432struct brcms_pub *brcms_c_pub(struct brcms_c_info *wlc) 4433{ 4434 return wlc->pub; 4435} 4436 4437/* low level attach 4438 * run backplane attach, init nvram 4439 * run phy attach 4440 * initialize software state for each core and band 4441 * put the whole chip in reset(driver down state), no clock 4442 */ 4443static int brcms_b_attach(struct brcms_c_info *wlc, u16 vendor, u16 device, 4444 uint unit, bool piomode, void __iomem *regsva, 4445 struct pci_dev *btparam) 4446{ 4447 struct brcms_hardware *wlc_hw; 4448 struct d11regs __iomem *regs; 4449 char *macaddr = NULL; 4450 uint err = 0; 4451 uint j; 4452 bool wme = false; 4453 struct shared_phy_params sha_params; 4454 struct wiphy *wiphy = wlc->wiphy; 4455 4456 BCMMSG(wlc->wiphy, "wl%d: vendor 0x%x device 0x%x\n", unit, vendor, 4457 device); 4458 4459 wme = true; 4460 4461 wlc_hw = wlc->hw; 4462 wlc_hw->wlc = wlc; 4463 wlc_hw->unit = unit; 4464 wlc_hw->band = wlc_hw->bandstate[0]; 4465 wlc_hw->_piomode = piomode; 4466 4467 /* populate struct brcms_hardware with default values */ 4468 brcms_b_info_init(wlc_hw); 4469 4470 /* 4471 * Do the hardware portion of the attach. Also initialize software 4472 * state that depends on the particular hardware we are running. 4473 */ 4474 wlc_hw->sih = ai_attach(regsva, btparam); 4475 if (wlc_hw->sih == NULL) { 4476 wiphy_err(wiphy, "wl%d: brcms_b_attach: si_attach failed\n", 4477 unit); 4478 err = 11; 4479 goto fail; 4480 } 4481 4482 /* verify again the device is supported */ 4483 if (!brcms_c_chipmatch(vendor, device)) { 4484 wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported " 4485 "vendor/device (0x%x/0x%x)\n", 4486 unit, vendor, device); 4487 err = 12; 4488 goto fail; 4489 } 4490 4491 wlc_hw->vendorid = vendor; 4492 wlc_hw->deviceid = device; 4493 4494 /* set bar0 window to point at D11 core */ 4495 wlc_hw->regs = (struct d11regs __iomem *) 4496 ai_setcore(wlc_hw->sih, D11_CORE_ID, 0); 4497 wlc_hw->corerev = ai_corerev(wlc_hw->sih); 4498 4499 regs = wlc_hw->regs; 4500 4501 wlc->regs = wlc_hw->regs; 4502 4503 /* validate chip, chiprev and corerev */ 4504 if (!brcms_c_isgoodchip(wlc_hw)) { 4505 err = 13; 4506 goto fail; 4507 } 4508 4509 /* initialize power control registers */ 4510 ai_clkctl_init(wlc_hw->sih); 4511 4512 /* request fastclock and force fastclock for the rest of attach 4513 * bring the d11 core out of reset. 4514 * For PMU chips, the first wlc_clkctl_clk is no-op since core-clk 4515 * is still false; But it will be called again inside wlc_corereset, 4516 * after d11 is out of reset. 4517 */ 4518 brcms_b_clkctl_clk(wlc_hw, CLK_FAST); 4519 brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS); 4520 4521 if (!brcms_b_validate_chip_access(wlc_hw)) { 4522 wiphy_err(wiphy, "wl%d: brcms_b_attach: validate_chip_access " 4523 "failed\n", unit); 4524 err = 14; 4525 goto fail; 4526 } 4527 4528 /* get the board rev, used just below */ 4529 j = getintvar(wlc_hw->sih, BRCMS_SROM_BOARDREV); 4530 /* promote srom boardrev of 0xFF to 1 */ 4531 if (j == BOARDREV_PROMOTABLE) 4532 j = BOARDREV_PROMOTED; 4533 wlc_hw->boardrev = (u16) j; 4534 if (!brcms_c_validboardtype(wlc_hw)) { 4535 wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported Broadcom " 4536 "board type (0x%x)" " or revision level (0x%x)\n", 4537 unit, wlc_hw->sih->boardtype, wlc_hw->boardrev); 4538 err = 15; 4539 goto fail; 4540 } 4541 wlc_hw->sromrev = (u8) getintvar(wlc_hw->sih, BRCMS_SROM_REV); 4542 wlc_hw->boardflags = (u32) getintvar(wlc_hw->sih, 4543 BRCMS_SROM_BOARDFLAGS); 4544 wlc_hw->boardflags2 = (u32) getintvar(wlc_hw->sih, 4545 BRCMS_SROM_BOARDFLAGS2); 4546 4547 if (wlc_hw->boardflags & BFL_NOPLLDOWN) 4548 brcms_b_pllreq(wlc_hw, true, BRCMS_PLLREQ_SHARED); 4549 4550 /* check device id(srom, nvram etc.) to set bands */ 4551 if (wlc_hw->deviceid == BCM43224_D11N_ID || 4552 wlc_hw->deviceid == BCM43224_D11N_ID_VEN1) 4553 /* Dualband boards */ 4554 wlc_hw->_nbands = 2; 4555 else 4556 wlc_hw->_nbands = 1; 4557 4558 if ((wlc_hw->sih->chip == BCM43225_CHIP_ID)) 4559 wlc_hw->_nbands = 1; 4560 4561 /* BMAC_NOTE: remove init of pub values when brcms_c_attach() 4562 * unconditionally does the init of these values 4563 */ 4564 wlc->vendorid = wlc_hw->vendorid; 4565 wlc->deviceid = wlc_hw->deviceid; 4566 wlc->pub->sih = wlc_hw->sih; 4567 wlc->pub->corerev = wlc_hw->corerev; 4568 wlc->pub->sromrev = wlc_hw->sromrev; 4569 wlc->pub->boardrev = wlc_hw->boardrev; 4570 wlc->pub->boardflags = wlc_hw->boardflags; 4571 wlc->pub->boardflags2 = wlc_hw->boardflags2; 4572 wlc->pub->_nbands = wlc_hw->_nbands; 4573 4574 wlc_hw->physhim = wlc_phy_shim_attach(wlc_hw, wlc->wl, wlc); 4575 4576 if (wlc_hw->physhim == NULL) { 4577 wiphy_err(wiphy, "wl%d: brcms_b_attach: wlc_phy_shim_attach " 4578 "failed\n", unit); 4579 err = 25; 4580 goto fail; 4581 } 4582 4583 /* pass all the parameters to wlc_phy_shared_attach in one struct */ 4584 sha_params.sih = wlc_hw->sih; 4585 sha_params.physhim = wlc_hw->physhim; 4586 sha_params.unit = unit; 4587 sha_params.corerev = wlc_hw->corerev; 4588 sha_params.vid = wlc_hw->vendorid; 4589 sha_params.did = wlc_hw->deviceid; 4590 sha_params.chip = wlc_hw->sih->chip; 4591 sha_params.chiprev = wlc_hw->sih->chiprev; 4592 sha_params.chippkg = wlc_hw->sih->chippkg; 4593 sha_params.sromrev = wlc_hw->sromrev; 4594 sha_params.boardtype = wlc_hw->sih->boardtype; 4595 sha_params.boardrev = wlc_hw->boardrev; 4596 sha_params.boardvendor = wlc_hw->sih->boardvendor; 4597 sha_params.boardflags = wlc_hw->boardflags; 4598 sha_params.boardflags2 = wlc_hw->boardflags2; 4599 sha_params.buscorerev = wlc_hw->sih->buscorerev; 4600 4601 /* alloc and save pointer to shared phy state area */ 4602 wlc_hw->phy_sh = wlc_phy_shared_attach(&sha_params); 4603 if (!wlc_hw->phy_sh) { 4604 err = 16; 4605 goto fail; 4606 } 4607 4608 /* initialize software state for each core and band */ 4609 for (j = 0; j < wlc_hw->_nbands; j++) { 4610 /* 4611 * band0 is always 2.4Ghz 4612 * band1, if present, is 5Ghz 4613 */ 4614 4615 brcms_c_setxband(wlc_hw, j); 4616 4617 wlc_hw->band->bandunit = j; 4618 wlc_hw->band->bandtype = j ? BRCM_BAND_5G : BRCM_BAND_2G; 4619 wlc->band->bandunit = j; 4620 wlc->band->bandtype = j ? BRCM_BAND_5G : BRCM_BAND_2G; 4621 wlc->core->coreidx = ai_coreidx(wlc_hw->sih); 4622 4623 wlc_hw->machwcap = R_REG(®s->machwcap); 4624 wlc_hw->machwcap_backup = wlc_hw->machwcap; 4625 4626 /* init tx fifo size */ 4627 wlc_hw->xmtfifo_sz = 4628 xmtfifo_sz[(wlc_hw->corerev - XMTFIFOTBL_STARTREV)]; 4629 4630 /* Get a phy for this band */ 4631 wlc_hw->band->pi = 4632 wlc_phy_attach(wlc_hw->phy_sh, regs, 4633 wlc_hw->band->bandtype, 4634 wlc->wiphy); 4635 if (wlc_hw->band->pi == NULL) { 4636 wiphy_err(wiphy, "wl%d: brcms_b_attach: wlc_phy_" 4637 "attach failed\n", unit); 4638 err = 17; 4639 goto fail; 4640 } 4641 4642 wlc_phy_machwcap_set(wlc_hw->band->pi, wlc_hw->machwcap); 4643 4644 wlc_phy_get_phyversion(wlc_hw->band->pi, &wlc_hw->band->phytype, 4645 &wlc_hw->band->phyrev, 4646 &wlc_hw->band->radioid, 4647 &wlc_hw->band->radiorev); 4648 wlc_hw->band->abgphy_encore = 4649 wlc_phy_get_encore(wlc_hw->band->pi); 4650 wlc->band->abgphy_encore = wlc_phy_get_encore(wlc_hw->band->pi); 4651 wlc_hw->band->core_flags = 4652 wlc_phy_get_coreflags(wlc_hw->band->pi); 4653 4654 /* verify good phy_type & supported phy revision */ 4655 if (BRCMS_ISNPHY(wlc_hw->band)) { 4656 if (NCONF_HAS(wlc_hw->band->phyrev)) 4657 goto good_phy; 4658 else 4659 goto bad_phy; 4660 } else if (BRCMS_ISLCNPHY(wlc_hw->band)) { 4661 if (LCNCONF_HAS(wlc_hw->band->phyrev)) 4662 goto good_phy; 4663 else 4664 goto bad_phy; 4665 } else { 4666 bad_phy: 4667 wiphy_err(wiphy, "wl%d: brcms_b_attach: unsupported " 4668 "phy type/rev (%d/%d)\n", unit, 4669 wlc_hw->band->phytype, wlc_hw->band->phyrev); 4670 err = 18; 4671 goto fail; 4672 } 4673 4674 good_phy: 4675 /* 4676 * BMAC_NOTE: wlc->band->pi should not be set below and should 4677 * be done in the high level attach. However we can not make 4678 * that change until all low level access is changed to 4679 * wlc_hw->band->pi. Instead do the wlc->band->pi init below, 4680 * keeping wlc_hw->band->pi as well for incremental update of 4681 * low level fns, and cut over low only init when all fns 4682 * updated. 4683 */ 4684 wlc->band->pi = wlc_hw->band->pi; 4685 wlc->band->phytype = wlc_hw->band->phytype; 4686 wlc->band->phyrev = wlc_hw->band->phyrev; 4687 wlc->band->radioid = wlc_hw->band->radioid; 4688 wlc->band->radiorev = wlc_hw->band->radiorev; 4689 4690 /* default contention windows size limits */ 4691 wlc_hw->band->CWmin = APHY_CWMIN; 4692 wlc_hw->band->CWmax = PHY_CWMAX; 4693 4694 if (!brcms_b_attach_dmapio(wlc, j, wme)) { 4695 err = 19; 4696 goto fail; 4697 } 4698 } 4699 4700 /* disable core to match driver "down" state */ 4701 brcms_c_coredisable(wlc_hw); 4702 4703 /* Match driver "down" state */ 4704 ai_pci_down(wlc_hw->sih); 4705 4706 /* register sb interrupt callback functions */ 4707 ai_register_intr_callback(wlc_hw->sih, (void *)brcms_c_wlintrsoff, 4708 (void *)brcms_c_wlintrsrestore, NULL, wlc); 4709 4710 /* turn off pll and xtal to match driver "down" state */ 4711 brcms_b_xtal(wlc_hw, OFF); 4712 4713 /* ******************************************************************* 4714 * The hardware is in the DOWN state at this point. D11 core 4715 * or cores are in reset with clocks off, and the board PLLs 4716 * are off if possible. 4717 * 4718 * Beyond this point, wlc->sbclk == false and chip registers 4719 * should not be touched. 4720 ********************************************************************* 4721 */ 4722 4723 /* init etheraddr state variables */ 4724 macaddr = brcms_c_get_macaddr(wlc_hw); 4725 if (macaddr == NULL) { 4726 wiphy_err(wiphy, "wl%d: brcms_b_attach: macaddr not found\n", 4727 unit); 4728 err = 21; 4729 goto fail; 4730 } 4731 if (!mac_pton(macaddr, wlc_hw->etheraddr) || 4732 is_broadcast_ether_addr(wlc_hw->etheraddr) || 4733 is_zero_ether_addr(wlc_hw->etheraddr)) { 4734 wiphy_err(wiphy, "wl%d: brcms_b_attach: bad macaddr %s\n", 4735 unit, macaddr); 4736 err = 22; 4737 goto fail; 4738 } 4739 4740 BCMMSG(wlc->wiphy, 4741 "deviceid 0x%x nbands %d board 0x%x macaddr: %s\n", 4742 wlc_hw->deviceid, wlc_hw->_nbands, 4743 wlc_hw->sih->boardtype, macaddr); 4744 4745 return err; 4746 4747 fail: 4748 wiphy_err(wiphy, "wl%d: brcms_b_attach: failed with err %d\n", unit, 4749 err); 4750 return err; 4751} 4752 4753static void brcms_c_attach_antgain_init(struct brcms_c_info *wlc) 4754{ 4755 uint unit; 4756 unit = wlc->pub->unit; 4757 4758 if ((wlc->band->antgain == -1) && (wlc->pub->sromrev == 1)) { 4759 /* default antenna gain for srom rev 1 is 2 dBm (8 qdbm) */ 4760 wlc->band->antgain = 8; 4761 } else if (wlc->band->antgain == -1) { 4762 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid antennas available in" 4763 " srom, using 2dB\n", unit, __func__); 4764 wlc->band->antgain = 8; 4765 } else { 4766 s8 gain, fract; 4767 /* Older sroms specified gain in whole dbm only. In order 4768 * be able to specify qdbm granularity and remain backward 4769 * compatible the whole dbms are now encoded in only 4770 * low 6 bits and remaining qdbms are encoded in the hi 2 bits. 4771 * 6 bit signed number ranges from -32 - 31. 4772 * 4773 * Examples: 4774 * 0x1 = 1 db, 4775 * 0xc1 = 1.75 db (1 + 3 quarters), 4776 * 0x3f = -1 (-1 + 0 quarters), 4777 * 0x7f = -.75 (-1 + 1 quarters) = -3 qdbm. 4778 * 0xbf = -.50 (-1 + 2 quarters) = -2 qdbm. 4779 */ 4780 gain = wlc->band->antgain & 0x3f; 4781 gain <<= 2; /* Sign extend */ 4782 gain >>= 2; 4783 fract = (wlc->band->antgain & 0xc0) >> 6; 4784 wlc->band->antgain = 4 * gain + fract; 4785 } 4786} 4787 4788static bool brcms_c_attach_stf_ant_init(struct brcms_c_info *wlc) 4789{ 4790 int aa; 4791 uint unit; 4792 int bandtype; 4793 struct si_pub *sih = wlc->hw->sih; 4794 4795 unit = wlc->pub->unit; 4796 bandtype = wlc->band->bandtype; 4797 4798 /* get antennas available */ 4799 if (bandtype == BRCM_BAND_5G) 4800 aa = (s8) getintvar(sih, BRCMS_SROM_AA5G); 4801 else 4802 aa = (s8) getintvar(sih, BRCMS_SROM_AA2G); 4803 4804 if ((aa < 1) || (aa > 15)) { 4805 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid antennas available in" 4806 " srom (0x%x), using 3\n", unit, __func__, aa); 4807 aa = 3; 4808 } 4809 4810 /* reset the defaults if we have a single antenna */ 4811 if (aa == 1) { 4812 wlc->stf->ant_rx_ovr = ANT_RX_DIV_FORCE_0; 4813 wlc->stf->txant = ANT_TX_FORCE_0; 4814 } else if (aa == 2) { 4815 wlc->stf->ant_rx_ovr = ANT_RX_DIV_FORCE_1; 4816 wlc->stf->txant = ANT_TX_FORCE_1; 4817 } else { 4818 } 4819 4820 /* Compute Antenna Gain */ 4821 if (bandtype == BRCM_BAND_5G) 4822 wlc->band->antgain = (s8) getintvar(sih, BRCMS_SROM_AG1); 4823 else 4824 wlc->band->antgain = (s8) getintvar(sih, BRCMS_SROM_AG0); 4825 4826 brcms_c_attach_antgain_init(wlc); 4827 4828 return true; 4829} 4830 4831static void brcms_c_bss_default_init(struct brcms_c_info *wlc) 4832{ 4833 u16 chanspec; 4834 struct brcms_band *band; 4835 struct brcms_bss_info *bi = wlc->default_bss; 4836 4837 /* init default and target BSS with some sane initial values */ 4838 memset((char *)(bi), 0, sizeof(struct brcms_bss_info)); 4839 bi->beacon_period = BEACON_INTERVAL_DEFAULT; 4840 4841 /* fill the default channel as the first valid channel 4842 * starting from the 2G channels 4843 */ 4844 chanspec = ch20mhz_chspec(1); 4845 wlc->home_chanspec = bi->chanspec = chanspec; 4846 4847 /* find the band of our default channel */ 4848 band = wlc->band; 4849 if (wlc->pub->_nbands > 1 && 4850 band->bandunit != chspec_bandunit(chanspec)) 4851 band = wlc->bandstate[OTHERBANDUNIT(wlc)]; 4852 4853 /* init bss rates to the band specific default rate set */ 4854 brcms_c_rateset_default(&bi->rateset, NULL, band->phytype, 4855 band->bandtype, false, BRCMS_RATE_MASK_FULL, 4856 (bool) (wlc->pub->_n_enab & SUPPORT_11N), 4857 brcms_chspec_bw(chanspec), wlc->stf->txstreams); 4858 4859 if (wlc->pub->_n_enab & SUPPORT_11N) 4860 bi->flags |= BRCMS_BSS_HT; 4861} 4862 4863static struct brcms_txq_info *brcms_c_txq_alloc(struct brcms_c_info *wlc) 4864{ 4865 struct brcms_txq_info *qi, *p; 4866 4867 qi = kzalloc(sizeof(struct brcms_txq_info), GFP_ATOMIC); 4868 if (qi != NULL) { 4869 /* 4870 * Have enough room for control packets along with HI watermark 4871 * Also, add room to txq for total psq packets if all the SCBs 4872 * leave PS mode. The watermark for flowcontrol to OS packets 4873 * will remain the same 4874 */ 4875 brcmu_pktq_init(&qi->q, BRCMS_PREC_COUNT, 4876 2 * BRCMS_DATAHIWAT + PKTQ_LEN_DEFAULT); 4877 4878 /* add this queue to the the global list */ 4879 p = wlc->tx_queues; 4880 if (p == NULL) { 4881 wlc->tx_queues = qi; 4882 } else { 4883 while (p->next != NULL) 4884 p = p->next; 4885 p->next = qi; 4886 } 4887 } 4888 return qi; 4889} 4890 4891static void brcms_c_txq_free(struct brcms_c_info *wlc, 4892 struct brcms_txq_info *qi) 4893{ 4894 struct brcms_txq_info *p; 4895 4896 if (qi == NULL) 4897 return; 4898 4899 /* remove the queue from the linked list */ 4900 p = wlc->tx_queues; 4901 if (p == qi) 4902 wlc->tx_queues = p->next; 4903 else { 4904 while (p != NULL && p->next != qi) 4905 p = p->next; 4906 if (p != NULL) 4907 p->next = p->next->next; 4908 } 4909 4910 kfree(qi); 4911} 4912 4913static void brcms_c_update_mimo_band_bwcap(struct brcms_c_info *wlc, u8 bwcap) 4914{ 4915 uint i; 4916 struct brcms_band *band; 4917 4918 for (i = 0; i < wlc->pub->_nbands; i++) { 4919 band = wlc->bandstate[i]; 4920 if (band->bandtype == BRCM_BAND_5G) { 4921 if ((bwcap == BRCMS_N_BW_40ALL) 4922 || (bwcap == BRCMS_N_BW_20IN2G_40IN5G)) 4923 band->mimo_cap_40 = true; 4924 else 4925 band->mimo_cap_40 = false; 4926 } else { 4927 if (bwcap == BRCMS_N_BW_40ALL) 4928 band->mimo_cap_40 = true; 4929 else 4930 band->mimo_cap_40 = false; 4931 } 4932 } 4933} 4934 4935static void brcms_c_timers_deinit(struct brcms_c_info *wlc) 4936{ 4937 /* free timer state */ 4938 if (wlc->wdtimer) { 4939 brcms_free_timer(wlc->wdtimer); 4940 wlc->wdtimer = NULL; 4941 } 4942 if (wlc->radio_timer) { 4943 brcms_free_timer(wlc->radio_timer); 4944 wlc->radio_timer = NULL; 4945 } 4946} 4947 4948static void brcms_c_detach_module(struct brcms_c_info *wlc) 4949{ 4950 if (wlc->asi) { 4951 brcms_c_antsel_detach(wlc->asi); 4952 wlc->asi = NULL; 4953 } 4954 4955 if (wlc->ampdu) { 4956 brcms_c_ampdu_detach(wlc->ampdu); 4957 wlc->ampdu = NULL; 4958 } 4959 4960 brcms_c_stf_detach(wlc); 4961} 4962 4963/* 4964 * low level detach 4965 */ 4966static int brcms_b_detach(struct brcms_c_info *wlc) 4967{ 4968 uint i; 4969 struct brcms_hw_band *band; 4970 struct brcms_hardware *wlc_hw = wlc->hw; 4971 int callbacks; 4972 4973 callbacks = 0; 4974 4975 if (wlc_hw->sih) { 4976 /* 4977 * detach interrupt sync mechanism since interrupt is disabled 4978 * and per-port interrupt object may has been freed. this must 4979 * be done before sb core switch 4980 */ 4981 ai_deregister_intr_callback(wlc_hw->sih); 4982 ai_pci_sleep(wlc_hw->sih); 4983 } 4984 4985 brcms_b_detach_dmapio(wlc_hw); 4986 4987 band = wlc_hw->band; 4988 for (i = 0; i < wlc_hw->_nbands; i++) { 4989 if (band->pi) { 4990 /* Detach this band's phy */ 4991 wlc_phy_detach(band->pi); 4992 band->pi = NULL; 4993 } 4994 band = wlc_hw->bandstate[OTHERBANDUNIT(wlc)]; 4995 } 4996 4997 /* Free shared phy state */ 4998 kfree(wlc_hw->phy_sh); 4999 5000 wlc_phy_shim_detach(wlc_hw->physhim); 5001 5002 if (wlc_hw->sih) { 5003 ai_detach(wlc_hw->sih); 5004 wlc_hw->sih = NULL; 5005 } 5006 5007 return callbacks; 5008 5009} 5010 5011/* 5012 * Return a count of the number of driver callbacks still pending. 5013 * 5014 * General policy is that brcms_c_detach can only dealloc/free software states. 5015 * It can NOT touch hardware registers since the d11core may be in reset and 5016 * clock may not be available. 5017 * One exception is sb register access, which is possible if crystal is turned 5018 * on after "down" state, driver should avoid software timer with the exception 5019 * of radio_monitor. 5020 */ 5021uint brcms_c_detach(struct brcms_c_info *wlc) 5022{ 5023 uint callbacks = 0; 5024 5025 if (wlc == NULL) 5026 return 0; 5027 5028 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit); 5029 5030 callbacks += brcms_b_detach(wlc); 5031 5032 /* delete software timers */ 5033 if (!brcms_c_radio_monitor_stop(wlc)) 5034 callbacks++; 5035 5036 brcms_c_channel_mgr_detach(wlc->cmi); 5037 5038 brcms_c_timers_deinit(wlc); 5039 5040 brcms_c_detach_module(wlc); 5041 5042 5043 while (wlc->tx_queues != NULL) 5044 brcms_c_txq_free(wlc, wlc->tx_queues); 5045 5046 brcms_c_detach_mfree(wlc); 5047 return callbacks; 5048} 5049 5050/* update state that depends on the current value of "ap" */ 5051static void brcms_c_ap_upd(struct brcms_c_info *wlc) 5052{ 5053 /* STA-BSS; short capable */ 5054 wlc->PLCPHdr_override = BRCMS_PLCP_SHORT; 5055} 5056 5057/* Initialize just the hardware when coming out of POR or S3/S5 system states */ 5058static void brcms_b_hw_up(struct brcms_hardware *wlc_hw) 5059{ 5060 if (wlc_hw->wlc->pub->hw_up) 5061 return; 5062 5063 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit); 5064 5065 /* 5066 * Enable pll and xtal, initialize the power control registers, 5067 * and force fastclock for the remainder of brcms_c_up(). 5068 */ 5069 brcms_b_xtal(wlc_hw, ON); 5070 ai_clkctl_init(wlc_hw->sih); 5071 brcms_b_clkctl_clk(wlc_hw, CLK_FAST); 5072 5073 ai_pci_fixcfg(wlc_hw->sih); 5074 5075 /* 5076 * AI chip doesn't restore bar0win2 on 5077 * hibernation/resume, need sw fixup 5078 */ 5079 if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) || 5080 (wlc_hw->sih->chip == BCM43225_CHIP_ID)) 5081 wlc_hw->regs = (struct d11regs __iomem *) 5082 ai_setcore(wlc_hw->sih, D11_CORE_ID, 0); 5083 5084 /* 5085 * Inform phy that a POR reset has occurred so 5086 * it does a complete phy init 5087 */ 5088 wlc_phy_por_inform(wlc_hw->band->pi); 5089 5090 wlc_hw->ucode_loaded = false; 5091 wlc_hw->wlc->pub->hw_up = true; 5092 5093 if ((wlc_hw->boardflags & BFL_FEM) 5094 && (wlc_hw->sih->chip == BCM4313_CHIP_ID)) { 5095 if (! 5096 (wlc_hw->boardrev >= 0x1250 5097 && (wlc_hw->boardflags & BFL_FEM_BT))) 5098 ai_epa_4313war(wlc_hw->sih); 5099 } 5100} 5101 5102static int brcms_b_up_prep(struct brcms_hardware *wlc_hw) 5103{ 5104 uint coremask; 5105 5106 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit); 5107 5108 /* 5109 * Enable pll and xtal, initialize the power control registers, 5110 * and force fastclock for the remainder of brcms_c_up(). 5111 */ 5112 brcms_b_xtal(wlc_hw, ON); 5113 ai_clkctl_init(wlc_hw->sih); 5114 brcms_b_clkctl_clk(wlc_hw, CLK_FAST); 5115 5116 /* 5117 * Configure pci/pcmcia here instead of in brcms_c_attach() 5118 * to allow mfg hotswap: down, hotswap (chip power cycle), up. 5119 */ 5120 coremask = (1 << wlc_hw->wlc->core->coreidx); 5121 5122 ai_pci_setup(wlc_hw->sih, coremask); 5123 5124 /* 5125 * Need to read the hwradio status here to cover the case where the 5126 * system is loaded with the hw radio disabled. We do not want to 5127 * bring the driver up in this case. 5128 */ 5129 if (brcms_b_radio_read_hwdisabled(wlc_hw)) { 5130 /* put SB PCI in down state again */ 5131 ai_pci_down(wlc_hw->sih); 5132 brcms_b_xtal(wlc_hw, OFF); 5133 return -ENOMEDIUM; 5134 } 5135 5136 ai_pci_up(wlc_hw->sih); 5137 5138 /* reset the d11 core */ 5139 brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS); 5140 5141 return 0; 5142} 5143 5144static int brcms_b_up_finish(struct brcms_hardware *wlc_hw) 5145{ 5146 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit); 5147 5148 wlc_hw->up = true; 5149 wlc_phy_hw_state_upd(wlc_hw->band->pi, true); 5150 5151 /* FULLY enable dynamic power control and d11 core interrupt */ 5152 brcms_b_clkctl_clk(wlc_hw, CLK_DYNAMIC); 5153 brcms_intrson(wlc_hw->wlc->wl); 5154 return 0; 5155} 5156 5157/* 5158 * Write WME tunable parameters for retransmit/max rate 5159 * from wlc struct to ucode 5160 */ 5161static void brcms_c_wme_retries_write(struct brcms_c_info *wlc) 5162{ 5163 int ac; 5164 5165 /* Need clock to do this */ 5166 if (!wlc->clk) 5167 return; 5168 5169 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) 5170 brcms_b_write_shm(wlc->hw, M_AC_TXLMT_ADDR(ac), 5171 wlc->wme_retries[ac]); 5172} 5173 5174/* make interface operational */ 5175int brcms_c_up(struct brcms_c_info *wlc) 5176{ 5177 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit); 5178 5179 /* HW is turned off so don't try to access it */ 5180 if (wlc->pub->hw_off || brcms_deviceremoved(wlc)) 5181 return -ENOMEDIUM; 5182 5183 if (!wlc->pub->hw_up) { 5184 brcms_b_hw_up(wlc->hw); 5185 wlc->pub->hw_up = true; 5186 } 5187 5188 if ((wlc->pub->boardflags & BFL_FEM) 5189 && (wlc->pub->sih->chip == BCM4313_CHIP_ID)) { 5190 if (wlc->pub->boardrev >= 0x1250 5191 && (wlc->pub->boardflags & BFL_FEM_BT)) 5192 brcms_b_mhf(wlc->hw, MHF5, MHF5_4313_GPIOCTRL, 5193 MHF5_4313_GPIOCTRL, BRCM_BAND_ALL); 5194 else 5195 brcms_b_mhf(wlc->hw, MHF4, MHF4_EXTPA_ENABLE, 5196 MHF4_EXTPA_ENABLE, BRCM_BAND_ALL); 5197 } 5198 5199 /* 5200 * Need to read the hwradio status here to cover the case where the 5201 * system is loaded with the hw radio disabled. We do not want to bring 5202 * the driver up in this case. If radio is disabled, abort up, lower 5203 * power, start radio timer and return 0(for NDIS) don't call 5204 * radio_update to avoid looping brcms_c_up. 5205 * 5206 * brcms_b_up_prep() returns either 0 or -BCME_RADIOOFF only 5207 */ 5208 if (!wlc->pub->radio_disabled) { 5209 int status = brcms_b_up_prep(wlc->hw); 5210 if (status == -ENOMEDIUM) { 5211 if (!mboolisset 5212 (wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE)) { 5213 struct brcms_bss_cfg *bsscfg = wlc->bsscfg; 5214 mboolset(wlc->pub->radio_disabled, 5215 WL_RADIO_HW_DISABLE); 5216 5217 if (bsscfg->enable && bsscfg->BSS) 5218 wiphy_err(wlc->wiphy, "wl%d: up" 5219 ": rfdisable -> " 5220 "bsscfg_disable()\n", 5221 wlc->pub->unit); 5222 } 5223 } 5224 } 5225 5226 if (wlc->pub->radio_disabled) { 5227 brcms_c_radio_monitor_start(wlc); 5228 return 0; 5229 } 5230 5231 /* brcms_b_up_prep has done brcms_c_corereset(). so clk is on, set it */ 5232 wlc->clk = true; 5233 5234 brcms_c_radio_monitor_stop(wlc); 5235 5236 /* Set EDCF hostflags */ 5237 brcms_b_mhf(wlc->hw, MHF1, MHF1_EDCF, MHF1_EDCF, BRCM_BAND_ALL); 5238 5239 brcms_init(wlc->wl); 5240 wlc->pub->up = true; 5241 5242 if (wlc->bandinit_pending) { 5243 brcms_c_suspend_mac_and_wait(wlc); 5244 brcms_c_set_chanspec(wlc, wlc->default_bss->chanspec); 5245 wlc->bandinit_pending = false; 5246 brcms_c_enable_mac(wlc); 5247 } 5248 5249 brcms_b_up_finish(wlc->hw); 5250 5251 /* Program the TX wme params with the current settings */ 5252 brcms_c_wme_retries_write(wlc); 5253 5254 /* start one second watchdog timer */ 5255 brcms_add_timer(wlc->wdtimer, TIMER_INTERVAL_WATCHDOG, true); 5256 wlc->WDarmed = true; 5257 5258 /* ensure antenna config is up to date */ 5259 brcms_c_stf_phy_txant_upd(wlc); 5260 /* ensure LDPC config is in sync */ 5261 brcms_c_ht_update_ldpc(wlc, wlc->stf->ldpc); 5262 5263 return 0; 5264} 5265 5266static uint brcms_c_down_del_timer(struct brcms_c_info *wlc) 5267{ 5268 uint callbacks = 0; 5269 5270 return callbacks; 5271} 5272 5273static int brcms_b_bmac_down_prep(struct brcms_hardware *wlc_hw) 5274{ 5275 bool dev_gone; 5276 uint callbacks = 0; 5277 5278 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit); 5279 5280 if (!wlc_hw->up) 5281 return callbacks; 5282 5283 dev_gone = brcms_deviceremoved(wlc_hw->wlc); 5284 5285 /* disable interrupts */ 5286 if (dev_gone) 5287 wlc_hw->wlc->macintmask = 0; 5288 else { 5289 /* now disable interrupts */ 5290 brcms_intrsoff(wlc_hw->wlc->wl); 5291 5292 /* ensure we're running on the pll clock again */ 5293 brcms_b_clkctl_clk(wlc_hw, CLK_FAST); 5294 } 5295 /* down phy at the last of this stage */ 5296 callbacks += wlc_phy_down(wlc_hw->band->pi); 5297 5298 return callbacks; 5299} 5300 5301static int brcms_b_down_finish(struct brcms_hardware *wlc_hw) 5302{ 5303 uint callbacks = 0; 5304 bool dev_gone; 5305 5306 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit); 5307 5308 if (!wlc_hw->up) 5309 return callbacks; 5310 5311 wlc_hw->up = false; 5312 wlc_phy_hw_state_upd(wlc_hw->band->pi, false); 5313 5314 dev_gone = brcms_deviceremoved(wlc_hw->wlc); 5315 5316 if (dev_gone) { 5317 wlc_hw->sbclk = false; 5318 wlc_hw->clk = false; 5319 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false); 5320 5321 /* reclaim any posted packets */ 5322 brcms_c_flushqueues(wlc_hw->wlc); 5323 } else { 5324 5325 /* Reset and disable the core */ 5326 if (ai_iscoreup(wlc_hw->sih)) { 5327 if (R_REG(&wlc_hw->regs->maccontrol) & 5328 MCTL_EN_MAC) 5329 brcms_c_suspend_mac_and_wait(wlc_hw->wlc); 5330 callbacks += brcms_reset(wlc_hw->wlc->wl); 5331 brcms_c_coredisable(wlc_hw); 5332 } 5333 5334 /* turn off primary xtal and pll */ 5335 if (!wlc_hw->noreset) { 5336 ai_pci_down(wlc_hw->sih); 5337 brcms_b_xtal(wlc_hw, OFF); 5338 } 5339 } 5340 5341 return callbacks; 5342} 5343 5344/* 5345 * Mark the interface nonoperational, stop the software mechanisms, 5346 * disable the hardware, free any transient buffer state. 5347 * Return a count of the number of driver callbacks still pending. 5348 */ 5349uint brcms_c_down(struct brcms_c_info *wlc) 5350{ 5351 5352 uint callbacks = 0; 5353 int i; 5354 bool dev_gone = false; 5355 struct brcms_txq_info *qi; 5356 5357 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit); 5358 5359 /* check if we are already in the going down path */ 5360 if (wlc->going_down) { 5361 wiphy_err(wlc->wiphy, "wl%d: %s: Driver going down so return" 5362 "\n", wlc->pub->unit, __func__); 5363 return 0; 5364 } 5365 if (!wlc->pub->up) 5366 return callbacks; 5367 5368 wlc->going_down = true; 5369 5370 callbacks += brcms_b_bmac_down_prep(wlc->hw); 5371 5372 dev_gone = brcms_deviceremoved(wlc); 5373 5374 /* Call any registered down handlers */ 5375 for (i = 0; i < BRCMS_MAXMODULES; i++) { 5376 if (wlc->modulecb[i].down_fn) 5377 callbacks += 5378 wlc->modulecb[i].down_fn(wlc->modulecb[i].hdl); 5379 } 5380 5381 /* cancel the watchdog timer */ 5382 if (wlc->WDarmed) { 5383 if (!brcms_del_timer(wlc->wdtimer)) 5384 callbacks++; 5385 wlc->WDarmed = false; 5386 } 5387 /* cancel all other timers */ 5388 callbacks += brcms_c_down_del_timer(wlc); 5389 5390 wlc->pub->up = false; 5391 5392 wlc_phy_mute_upd(wlc->band->pi, false, PHY_MUTE_ALL); 5393 5394 /* clear txq flow control */ 5395 brcms_c_txflowcontrol_reset(wlc); 5396 5397 /* flush tx queues */ 5398 for (qi = wlc->tx_queues; qi != NULL; qi = qi->next) 5399 brcmu_pktq_flush(&qi->q, true, NULL, NULL); 5400 5401 callbacks += brcms_b_down_finish(wlc->hw); 5402 5403 /* brcms_b_down_finish has done brcms_c_coredisable(). so clk is off */ 5404 wlc->clk = false; 5405 5406 wlc->going_down = false; 5407 return callbacks; 5408} 5409 5410/* Set the current gmode configuration */ 5411int brcms_c_set_gmode(struct brcms_c_info *wlc, u8 gmode, bool config) 5412{ 5413 int ret = 0; 5414 uint i; 5415 struct brcms_c_rateset rs; 5416 /* Default to 54g Auto */ 5417 /* Advertise and use shortslot (-1/0/1 Auto/Off/On) */ 5418 s8 shortslot = BRCMS_SHORTSLOT_AUTO; 5419 bool shortslot_restrict = false; /* Restrict association to stations 5420 * that support shortslot 5421 */ 5422 bool ofdm_basic = false; /* Make 6, 12, and 24 basic rates */ 5423 /* Advertise and use short preambles (-1/0/1 Auto/Off/On) */ 5424 int preamble = BRCMS_PLCP_LONG; 5425 bool preamble_restrict = false; /* Restrict association to stations 5426 * that support short preambles 5427 */ 5428 struct brcms_band *band; 5429 5430 /* if N-support is enabled, allow Gmode set as long as requested 5431 * Gmode is not GMODE_LEGACY_B 5432 */ 5433 if ((wlc->pub->_n_enab & SUPPORT_11N) && gmode == GMODE_LEGACY_B) 5434 return -ENOTSUPP; 5435 5436 /* verify that we are dealing with 2G band and grab the band pointer */ 5437 if (wlc->band->bandtype == BRCM_BAND_2G) 5438 band = wlc->band; 5439 else if ((wlc->pub->_nbands > 1) && 5440 (wlc->bandstate[OTHERBANDUNIT(wlc)]->bandtype == BRCM_BAND_2G)) 5441 band = wlc->bandstate[OTHERBANDUNIT(wlc)]; 5442 else 5443 return -EINVAL; 5444 5445 /* Legacy or bust when no OFDM is supported by regulatory */ 5446 if ((brcms_c_channel_locale_flags_in_band(wlc->cmi, band->bandunit) & 5447 BRCMS_NO_OFDM) && (gmode != GMODE_LEGACY_B)) 5448 return -EINVAL; 5449 5450 /* update configuration value */ 5451 if (config == true) 5452 brcms_c_protection_upd(wlc, BRCMS_PROT_G_USER, gmode); 5453 5454 /* Clear rateset override */ 5455 memset(&rs, 0, sizeof(struct brcms_c_rateset)); 5456 5457 switch (gmode) { 5458 case GMODE_LEGACY_B: 5459 shortslot = BRCMS_SHORTSLOT_OFF; 5460 brcms_c_rateset_copy(&gphy_legacy_rates, &rs); 5461 5462 break; 5463 5464 case GMODE_LRS: 5465 break; 5466 5467 case GMODE_AUTO: 5468 /* Accept defaults */ 5469 break; 5470 5471 case GMODE_ONLY: 5472 ofdm_basic = true; 5473 preamble = BRCMS_PLCP_SHORT; 5474 preamble_restrict = true; 5475 break; 5476 5477 case GMODE_PERFORMANCE: 5478 shortslot = BRCMS_SHORTSLOT_ON; 5479 shortslot_restrict = true; 5480 ofdm_basic = true; 5481 preamble = BRCMS_PLCP_SHORT; 5482 preamble_restrict = true; 5483 break; 5484 5485 default: 5486 /* Error */ 5487 wiphy_err(wlc->wiphy, "wl%d: %s: invalid gmode %d\n", 5488 wlc->pub->unit, __func__, gmode); 5489 return -ENOTSUPP; 5490 } 5491 5492 band->gmode = gmode; 5493 5494 wlc->shortslot_override = shortslot; 5495 5496 /* Use the default 11g rateset */ 5497 if (!rs.count) 5498 brcms_c_rateset_copy(&cck_ofdm_rates, &rs); 5499 5500 if (ofdm_basic) { 5501 for (i = 0; i < rs.count; i++) { 5502 if (rs.rates[i] == BRCM_RATE_6M 5503 || rs.rates[i] == BRCM_RATE_12M 5504 || rs.rates[i] == BRCM_RATE_24M) 5505 rs.rates[i] |= BRCMS_RATE_FLAG; 5506 } 5507 } 5508 5509 /* Set default bss rateset */ 5510 wlc->default_bss->rateset.count = rs.count; 5511 memcpy(wlc->default_bss->rateset.rates, rs.rates, 5512 sizeof(wlc->default_bss->rateset.rates)); 5513 5514 return ret; 5515} 5516 5517int brcms_c_set_nmode(struct brcms_c_info *wlc) 5518{ 5519 uint i; 5520 s32 nmode = AUTO; 5521 5522 if (wlc->stf->txstreams == WL_11N_3x3) 5523 nmode = WL_11N_3x3; 5524 else 5525 nmode = WL_11N_2x2; 5526 5527 /* force GMODE_AUTO if NMODE is ON */ 5528 brcms_c_set_gmode(wlc, GMODE_AUTO, true); 5529 if (nmode == WL_11N_3x3) 5530 wlc->pub->_n_enab = SUPPORT_HT; 5531 else 5532 wlc->pub->_n_enab = SUPPORT_11N; 5533 wlc->default_bss->flags |= BRCMS_BSS_HT; 5534 /* add the mcs rates to the default and hw ratesets */ 5535 brcms_c_rateset_mcs_build(&wlc->default_bss->rateset, 5536 wlc->stf->txstreams); 5537 for (i = 0; i < wlc->pub->_nbands; i++) 5538 memcpy(wlc->bandstate[i]->hw_rateset.mcs, 5539 wlc->default_bss->rateset.mcs, MCSSET_LEN); 5540 5541 return 0; 5542} 5543 5544static int 5545brcms_c_set_internal_rateset(struct brcms_c_info *wlc, 5546 struct brcms_c_rateset *rs_arg) 5547{ 5548 struct brcms_c_rateset rs, new; 5549 uint bandunit; 5550 5551 memcpy(&rs, rs_arg, sizeof(struct brcms_c_rateset)); 5552 5553 /* check for bad count value */ 5554 if ((rs.count == 0) || (rs.count > BRCMS_NUMRATES)) 5555 return -EINVAL; 5556 5557 /* try the current band */ 5558 bandunit = wlc->band->bandunit; 5559 memcpy(&new, &rs, sizeof(struct brcms_c_rateset)); 5560 if (brcms_c_rate_hwrs_filter_sort_validate 5561 (&new, &wlc->bandstate[bandunit]->hw_rateset, true, 5562 wlc->stf->txstreams)) 5563 goto good; 5564 5565 /* try the other band */ 5566 if (brcms_is_mband_unlocked(wlc)) { 5567 bandunit = OTHERBANDUNIT(wlc); 5568 memcpy(&new, &rs, sizeof(struct brcms_c_rateset)); 5569 if (brcms_c_rate_hwrs_filter_sort_validate(&new, 5570 &wlc-> 5571 bandstate[bandunit]-> 5572 hw_rateset, true, 5573 wlc->stf->txstreams)) 5574 goto good; 5575 } 5576 5577 return -EBADE; 5578 5579 good: 5580 /* apply new rateset */ 5581 memcpy(&wlc->default_bss->rateset, &new, 5582 sizeof(struct brcms_c_rateset)); 5583 memcpy(&wlc->bandstate[bandunit]->defrateset, &new, 5584 sizeof(struct brcms_c_rateset)); 5585 return 0; 5586} 5587 5588static void brcms_c_ofdm_rateset_war(struct brcms_c_info *wlc) 5589{ 5590 u8 r; 5591 bool war = false; 5592 5593 if (wlc->bsscfg->associated) 5594 r = wlc->bsscfg->current_bss->rateset.rates[0]; 5595 else 5596 r = wlc->default_bss->rateset.rates[0]; 5597 5598 wlc_phy_ofdm_rateset_war(wlc->band->pi, war); 5599} 5600 5601int brcms_c_set_channel(struct brcms_c_info *wlc, u16 channel) 5602{ 5603 u16 chspec = ch20mhz_chspec(channel); 5604 5605 if (channel < 0 || channel > MAXCHANNEL) 5606 return -EINVAL; 5607 5608 if (!brcms_c_valid_chanspec_db(wlc->cmi, chspec)) 5609 return -EINVAL; 5610 5611 5612 if (!wlc->pub->up && brcms_is_mband_unlocked(wlc)) { 5613 if (wlc->band->bandunit != chspec_bandunit(chspec)) 5614 wlc->bandinit_pending = true; 5615 else 5616 wlc->bandinit_pending = false; 5617 } 5618 5619 wlc->default_bss->chanspec = chspec; 5620 /* brcms_c_BSSinit() will sanitize the rateset before 5621 * using it.. */ 5622 if (wlc->pub->up && (wlc_phy_chanspec_get(wlc->band->pi) != chspec)) { 5623 brcms_c_set_home_chanspec(wlc, chspec); 5624 brcms_c_suspend_mac_and_wait(wlc); 5625 brcms_c_set_chanspec(wlc, chspec); 5626 brcms_c_enable_mac(wlc); 5627 } 5628 return 0; 5629} 5630 5631int brcms_c_set_rate_limit(struct brcms_c_info *wlc, u16 srl, u16 lrl) 5632{ 5633 int ac; 5634 5635 if (srl < 1 || srl > RETRY_SHORT_MAX || 5636 lrl < 1 || lrl > RETRY_SHORT_MAX) 5637 return -EINVAL; 5638 5639 wlc->SRL = srl; 5640 wlc->LRL = lrl; 5641 5642 brcms_b_retrylimit_upd(wlc->hw, wlc->SRL, wlc->LRL); 5643 5644 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) { 5645 wlc->wme_retries[ac] = SFIELD(wlc->wme_retries[ac], 5646 EDCF_SHORT, wlc->SRL); 5647 wlc->wme_retries[ac] = SFIELD(wlc->wme_retries[ac], 5648 EDCF_LONG, wlc->LRL); 5649 } 5650 brcms_c_wme_retries_write(wlc); 5651 5652 return 0; 5653} 5654 5655void brcms_c_get_current_rateset(struct brcms_c_info *wlc, 5656 struct brcm_rateset *currs) 5657{ 5658 struct brcms_c_rateset *rs; 5659 5660 if (wlc->pub->associated) 5661 rs = &wlc->bsscfg->current_bss->rateset; 5662 else 5663 rs = &wlc->default_bss->rateset; 5664 5665 /* Copy only legacy rateset section */ 5666 currs->count = rs->count; 5667 memcpy(&currs->rates, &rs->rates, rs->count); 5668} 5669 5670int brcms_c_set_rateset(struct brcms_c_info *wlc, struct brcm_rateset *rs) 5671{ 5672 struct brcms_c_rateset internal_rs; 5673 int bcmerror; 5674 5675 if (rs->count > BRCMS_NUMRATES) 5676 return -ENOBUFS; 5677 5678 memset(&internal_rs, 0, sizeof(struct brcms_c_rateset)); 5679 5680 /* Copy only legacy rateset section */ 5681 internal_rs.count = rs->count; 5682 memcpy(&internal_rs.rates, &rs->rates, internal_rs.count); 5683 5684 /* merge rateset coming in with the current mcsset */ 5685 if (wlc->pub->_n_enab & SUPPORT_11N) { 5686 struct brcms_bss_info *mcsset_bss; 5687 if (wlc->bsscfg->associated) 5688 mcsset_bss = wlc->bsscfg->current_bss; 5689 else 5690 mcsset_bss = wlc->default_bss; 5691 memcpy(internal_rs.mcs, &mcsset_bss->rateset.mcs[0], 5692 MCSSET_LEN); 5693 } 5694 5695 bcmerror = brcms_c_set_internal_rateset(wlc, &internal_rs); 5696 if (!bcmerror) 5697 brcms_c_ofdm_rateset_war(wlc); 5698 5699 return bcmerror; 5700} 5701 5702int brcms_c_set_beacon_period(struct brcms_c_info *wlc, u16 period) 5703{ 5704 if (period < DOT11_MIN_BEACON_PERIOD || 5705 period > DOT11_MAX_BEACON_PERIOD) 5706 return -EINVAL; 5707 5708 wlc->default_bss->beacon_period = period; 5709 return 0; 5710} 5711 5712u16 brcms_c_get_phy_type(struct brcms_c_info *wlc, int phyidx) 5713{ 5714 return wlc->band->phytype; 5715} 5716 5717void brcms_c_set_shortslot_override(struct brcms_c_info *wlc, s8 sslot_override) 5718{ 5719 wlc->shortslot_override = sslot_override; 5720 5721 /* 5722 * shortslot is an 11g feature, so no more work if we are 5723 * currently on the 5G band 5724 */ 5725 if (wlc->band->bandtype == BRCM_BAND_5G) 5726 return; 5727 5728 if (wlc->pub->up && wlc->pub->associated) { 5729 /* let watchdog or beacon processing update shortslot */ 5730 } else if (wlc->pub->up) { 5731 /* unassociated shortslot is off */ 5732 brcms_c_switch_shortslot(wlc, false); 5733 } else { 5734 /* driver is down, so just update the brcms_c_info 5735 * value */ 5736 if (wlc->shortslot_override == BRCMS_SHORTSLOT_AUTO) 5737 wlc->shortslot = false; 5738 else 5739 wlc->shortslot = 5740 (wlc->shortslot_override == 5741 BRCMS_SHORTSLOT_ON); 5742 } 5743} 5744 5745/* 5746 * register watchdog and down handlers. 5747 */ 5748int brcms_c_module_register(struct brcms_pub *pub, 5749 const char *name, struct brcms_info *hdl, 5750 int (*d_fn)(void *handle)) 5751{ 5752 struct brcms_c_info *wlc = (struct brcms_c_info *) pub->wlc; 5753 int i; 5754 5755 /* find an empty entry and just add, no duplication check! */ 5756 for (i = 0; i < BRCMS_MAXMODULES; i++) { 5757 if (wlc->modulecb[i].name[0] == '\0') { 5758 strncpy(wlc->modulecb[i].name, name, 5759 sizeof(wlc->modulecb[i].name) - 1); 5760 wlc->modulecb[i].hdl = hdl; 5761 wlc->modulecb[i].down_fn = d_fn; 5762 return 0; 5763 } 5764 } 5765 5766 return -ENOSR; 5767} 5768 5769/* unregister module callbacks */ 5770int brcms_c_module_unregister(struct brcms_pub *pub, const char *name, 5771 struct brcms_info *hdl) 5772{ 5773 struct brcms_c_info *wlc = (struct brcms_c_info *) pub->wlc; 5774 int i; 5775 5776 if (wlc == NULL) 5777 return -ENODATA; 5778 5779 for (i = 0; i < BRCMS_MAXMODULES; i++) { 5780 if (!strcmp(wlc->modulecb[i].name, name) && 5781 (wlc->modulecb[i].hdl == hdl)) { 5782 memset(&wlc->modulecb[i], 0, sizeof(struct modulecb)); 5783 return 0; 5784 } 5785 } 5786 5787 /* table not found! */ 5788 return -ENODATA; 5789} 5790 5791#ifdef BCMDBG 5792static const char * const supr_reason[] = { 5793 "None", "PMQ Entry", "Flush request", 5794 "Previous frag failure", "Channel mismatch", 5795 "Lifetime Expiry", "Underflow" 5796}; 5797 5798static void brcms_c_print_txs_status(u16 s) 5799{ 5800 printk(KERN_DEBUG "[15:12] %d frame attempts\n", 5801 (s & TX_STATUS_FRM_RTX_MASK) >> TX_STATUS_FRM_RTX_SHIFT); 5802 printk(KERN_DEBUG " [11:8] %d rts attempts\n", 5803 (s & TX_STATUS_RTS_RTX_MASK) >> TX_STATUS_RTS_RTX_SHIFT); 5804 printk(KERN_DEBUG " [7] %d PM mode indicated\n", 5805 ((s & TX_STATUS_PMINDCTD) ? 1 : 0)); 5806 printk(KERN_DEBUG " [6] %d intermediate status\n", 5807 ((s & TX_STATUS_INTERMEDIATE) ? 1 : 0)); 5808 printk(KERN_DEBUG " [5] %d AMPDU\n", 5809 (s & TX_STATUS_AMPDU) ? 1 : 0); 5810 printk(KERN_DEBUG " [4:2] %d Frame Suppressed Reason (%s)\n", 5811 ((s & TX_STATUS_SUPR_MASK) >> TX_STATUS_SUPR_SHIFT), 5812 supr_reason[(s & TX_STATUS_SUPR_MASK) >> TX_STATUS_SUPR_SHIFT]); 5813 printk(KERN_DEBUG " [1] %d acked\n", 5814 ((s & TX_STATUS_ACK_RCV) ? 1 : 0)); 5815} 5816#endif /* BCMDBG */ 5817 5818void brcms_c_print_txstatus(struct tx_status *txs) 5819{ 5820#if defined(BCMDBG) 5821 u16 s = txs->status; 5822 u16 ackphyrxsh = txs->ackphyrxsh; 5823 5824 printk(KERN_DEBUG "\ntxpkt (MPDU) Complete\n"); 5825 5826 printk(KERN_DEBUG "FrameID: %04x ", txs->frameid); 5827 printk(KERN_DEBUG "TxStatus: %04x", s); 5828 printk(KERN_DEBUG "\n"); 5829 5830 brcms_c_print_txs_status(s); 5831 5832 printk(KERN_DEBUG "LastTxTime: %04x ", txs->lasttxtime); 5833 printk(KERN_DEBUG "Seq: %04x ", txs->sequence); 5834 printk(KERN_DEBUG "PHYTxStatus: %04x ", txs->phyerr); 5835 printk(KERN_DEBUG "RxAckRSSI: %04x ", 5836 (ackphyrxsh & PRXS1_JSSI_MASK) >> PRXS1_JSSI_SHIFT); 5837 printk(KERN_DEBUG "RxAckSQ: %04x", 5838 (ackphyrxsh & PRXS1_SQ_MASK) >> PRXS1_SQ_SHIFT); 5839 printk(KERN_DEBUG "\n"); 5840#endif /* defined(BCMDBG) */ 5841} 5842 5843bool brcms_c_chipmatch(u16 vendor, u16 device) 5844{ 5845 if (vendor != PCI_VENDOR_ID_BROADCOM) { 5846 pr_err("chipmatch: unknown vendor id %04x\n", vendor); 5847 return false; 5848 } 5849 5850 if (device == BCM43224_D11N_ID_VEN1) 5851 return true; 5852 if ((device == BCM43224_D11N_ID) || (device == BCM43225_D11N2G_ID)) 5853 return true; 5854 if (device == BCM4313_D11N2G_ID) 5855 return true; 5856 if ((device == BCM43236_D11N_ID) || (device == BCM43236_D11N2G_ID)) 5857 return true; 5858 5859 pr_err("chipmatch: unknown device id %04x\n", device); 5860 return false; 5861} 5862 5863#if defined(BCMDBG) 5864void brcms_c_print_txdesc(struct d11txh *txh) 5865{ 5866 u16 mtcl = le16_to_cpu(txh->MacTxControlLow); 5867 u16 mtch = le16_to_cpu(txh->MacTxControlHigh); 5868 u16 mfc = le16_to_cpu(txh->MacFrameControl); 5869 u16 tfest = le16_to_cpu(txh->TxFesTimeNormal); 5870 u16 ptcw = le16_to_cpu(txh->PhyTxControlWord); 5871 u16 ptcw_1 = le16_to_cpu(txh->PhyTxControlWord_1); 5872 u16 ptcw_1_Fbr = le16_to_cpu(txh->PhyTxControlWord_1_Fbr); 5873 u16 ptcw_1_Rts = le16_to_cpu(txh->PhyTxControlWord_1_Rts); 5874 u16 ptcw_1_FbrRts = le16_to_cpu(txh->PhyTxControlWord_1_FbrRts); 5875 u16 mainrates = le16_to_cpu(txh->MainRates); 5876 u16 xtraft = le16_to_cpu(txh->XtraFrameTypes); 5877 u8 *iv = txh->IV; 5878 u8 *ra = txh->TxFrameRA; 5879 u16 tfestfb = le16_to_cpu(txh->TxFesTimeFallback); 5880 u8 *rtspfb = txh->RTSPLCPFallback; 5881 u16 rtsdfb = le16_to_cpu(txh->RTSDurFallback); 5882 u8 *fragpfb = txh->FragPLCPFallback; 5883 u16 fragdfb = le16_to_cpu(txh->FragDurFallback); 5884 u16 mmodelen = le16_to_cpu(txh->MModeLen); 5885 u16 mmodefbrlen = le16_to_cpu(txh->MModeFbrLen); 5886 u16 tfid = le16_to_cpu(txh->TxFrameID); 5887 u16 txs = le16_to_cpu(txh->TxStatus); 5888 u16 mnmpdu = le16_to_cpu(txh->MaxNMpdus); 5889 u16 mabyte = le16_to_cpu(txh->MaxABytes_MRT); 5890 u16 mabyte_f = le16_to_cpu(txh->MaxABytes_FBR); 5891 u16 mmbyte = le16_to_cpu(txh->MinMBytes); 5892 5893 u8 *rtsph = txh->RTSPhyHeader; 5894 struct ieee80211_rts rts = txh->rts_frame; 5895 5896 /* add plcp header along with txh descriptor */ 5897 printk(KERN_DEBUG "Raw TxDesc + plcp header:\n"); 5898 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, 5899 txh, sizeof(struct d11txh) + 48); 5900 5901 printk(KERN_DEBUG "TxCtlLow: %04x ", mtcl); 5902 printk(KERN_DEBUG "TxCtlHigh: %04x ", mtch); 5903 printk(KERN_DEBUG "FC: %04x ", mfc); 5904 printk(KERN_DEBUG "FES Time: %04x\n", tfest); 5905 printk(KERN_DEBUG "PhyCtl: %04x%s ", ptcw, 5906 (ptcw & PHY_TXC_SHORT_HDR) ? " short" : ""); 5907 printk(KERN_DEBUG "PhyCtl_1: %04x ", ptcw_1); 5908 printk(KERN_DEBUG "PhyCtl_1_Fbr: %04x\n", ptcw_1_Fbr); 5909 printk(KERN_DEBUG "PhyCtl_1_Rts: %04x ", ptcw_1_Rts); 5910 printk(KERN_DEBUG "PhyCtl_1_Fbr_Rts: %04x\n", ptcw_1_FbrRts); 5911 printk(KERN_DEBUG "MainRates: %04x ", mainrates); 5912 printk(KERN_DEBUG "XtraFrameTypes: %04x ", xtraft); 5913 printk(KERN_DEBUG "\n"); 5914 5915 print_hex_dump_bytes("SecIV:", DUMP_PREFIX_OFFSET, iv, sizeof(txh->IV)); 5916 print_hex_dump_bytes("RA:", DUMP_PREFIX_OFFSET, 5917 ra, sizeof(txh->TxFrameRA)); 5918 5919 printk(KERN_DEBUG "Fb FES Time: %04x ", tfestfb); 5920 print_hex_dump_bytes("Fb RTS PLCP:", DUMP_PREFIX_OFFSET, 5921 rtspfb, sizeof(txh->RTSPLCPFallback)); 5922 printk(KERN_DEBUG "RTS DUR: %04x ", rtsdfb); 5923 print_hex_dump_bytes("PLCP:", DUMP_PREFIX_OFFSET, 5924 fragpfb, sizeof(txh->FragPLCPFallback)); 5925 printk(KERN_DEBUG "DUR: %04x", fragdfb); 5926 printk(KERN_DEBUG "\n"); 5927 5928 printk(KERN_DEBUG "MModeLen: %04x ", mmodelen); 5929 printk(KERN_DEBUG "MModeFbrLen: %04x\n", mmodefbrlen); 5930 5931 printk(KERN_DEBUG "FrameID: %04x\n", tfid); 5932 printk(KERN_DEBUG "TxStatus: %04x\n", txs); 5933 5934 printk(KERN_DEBUG "MaxNumMpdu: %04x\n", mnmpdu); 5935 printk(KERN_DEBUG "MaxAggbyte: %04x\n", mabyte); 5936 printk(KERN_DEBUG "MaxAggbyte_fb: %04x\n", mabyte_f); 5937 printk(KERN_DEBUG "MinByte: %04x\n", mmbyte); 5938 5939 print_hex_dump_bytes("RTS PLCP:", DUMP_PREFIX_OFFSET, 5940 rtsph, sizeof(txh->RTSPhyHeader)); 5941 print_hex_dump_bytes("RTS Frame:", DUMP_PREFIX_OFFSET, 5942 (u8 *)&rts, sizeof(txh->rts_frame)); 5943 printk(KERN_DEBUG "\n"); 5944} 5945#endif /* defined(BCMDBG) */ 5946 5947#if defined(BCMDBG) 5948static int 5949brcms_c_format_flags(const struct brcms_c_bit_desc *bd, u32 flags, char *buf, 5950 int len) 5951{ 5952 int i; 5953 char *p = buf; 5954 char hexstr[16]; 5955 int slen = 0, nlen = 0; 5956 u32 bit; 5957 const char *name; 5958 5959 if (len < 2 || !buf) 5960 return 0; 5961 5962 buf[0] = '\0'; 5963 5964 for (i = 0; flags != 0; i++) { 5965 bit = bd[i].bit; 5966 name = bd[i].name; 5967 if (bit == 0 && flags != 0) { 5968 /* print any unnamed bits */ 5969 snprintf(hexstr, 16, "0x%X", flags); 5970 name = hexstr; 5971 flags = 0; /* exit loop */ 5972 } else if ((flags & bit) == 0) 5973 continue; 5974 flags &= ~bit; 5975 nlen = strlen(name); 5976 slen += nlen; 5977 /* count btwn flag space */ 5978 if (flags != 0) 5979 slen += 1; 5980 /* need NULL char as well */ 5981 if (len <= slen) 5982 break; 5983 /* copy NULL char but don't count it */ 5984 strncpy(p, name, nlen + 1); 5985 p += nlen; 5986 /* copy btwn flag space and NULL char */ 5987 if (flags != 0) 5988 p += snprintf(p, 2, " "); 5989 len -= slen; 5990 } 5991 5992 /* indicate the str was too short */ 5993 if (flags != 0) { 5994 if (len < 2) 5995 p -= 2 - len; /* overwrite last char */ 5996 p += snprintf(p, 2, ">"); 5997 } 5998 5999 return (int)(p - buf); 6000} 6001#endif /* defined(BCMDBG) */ 6002 6003#if defined(BCMDBG) 6004void brcms_c_print_rxh(struct d11rxhdr *rxh) 6005{ 6006 u16 len = rxh->RxFrameSize; 6007 u16 phystatus_0 = rxh->PhyRxStatus_0; 6008 u16 phystatus_1 = rxh->PhyRxStatus_1; 6009 u16 phystatus_2 = rxh->PhyRxStatus_2; 6010 u16 phystatus_3 = rxh->PhyRxStatus_3; 6011 u16 macstatus1 = rxh->RxStatus1; 6012 u16 macstatus2 = rxh->RxStatus2; 6013 char flagstr[64]; 6014 char lenbuf[20]; 6015 static const struct brcms_c_bit_desc macstat_flags[] = { 6016 {RXS_FCSERR, "FCSErr"}, 6017 {RXS_RESPFRAMETX, "Reply"}, 6018 {RXS_PBPRES, "PADDING"}, 6019 {RXS_DECATMPT, "DeCr"}, 6020 {RXS_DECERR, "DeCrErr"}, 6021 {RXS_BCNSENT, "Bcn"}, 6022 {0, NULL} 6023 }; 6024 6025 printk(KERN_DEBUG "Raw RxDesc:\n"); 6026 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, rxh, 6027 sizeof(struct d11rxhdr)); 6028 6029 brcms_c_format_flags(macstat_flags, macstatus1, flagstr, 64); 6030 6031 snprintf(lenbuf, sizeof(lenbuf), "0x%x", len); 6032 6033 printk(KERN_DEBUG "RxFrameSize: %6s (%d)%s\n", lenbuf, len, 6034 (rxh->PhyRxStatus_0 & PRXS0_SHORTH) ? " short preamble" : ""); 6035 printk(KERN_DEBUG "RxPHYStatus: %04x %04x %04x %04x\n", 6036 phystatus_0, phystatus_1, phystatus_2, phystatus_3); 6037 printk(KERN_DEBUG "RxMACStatus: %x %s\n", macstatus1, flagstr); 6038 printk(KERN_DEBUG "RXMACaggtype: %x\n", 6039 (macstatus2 & RXS_AGGTYPE_MASK)); 6040 printk(KERN_DEBUG "RxTSFTime: %04x\n", rxh->RxTSFTime); 6041} 6042#endif /* defined(BCMDBG) */ 6043 6044u16 brcms_b_rate_shm_offset(struct brcms_hardware *wlc_hw, u8 rate) 6045{ 6046 u16 table_ptr; 6047 u8 phy_rate, index; 6048 6049 /* get the phy specific rate encoding for the PLCP SIGNAL field */ 6050 if (is_ofdm_rate(rate)) 6051 table_ptr = M_RT_DIRMAP_A; 6052 else 6053 table_ptr = M_RT_DIRMAP_B; 6054 6055 /* for a given rate, the LS-nibble of the PLCP SIGNAL field is 6056 * the index into the rate table. 6057 */ 6058 phy_rate = rate_info[rate] & BRCMS_RATE_MASK; 6059 index = phy_rate & 0xf; 6060 6061 /* Find the SHM pointer to the rate table entry by looking in the 6062 * Direct-map Table 6063 */ 6064 return 2 * brcms_b_read_shm(wlc_hw, table_ptr + (index * 2)); 6065} 6066 6067static bool 6068brcms_c_prec_enq_head(struct brcms_c_info *wlc, struct pktq *q, 6069 struct sk_buff *pkt, int prec, bool head) 6070{ 6071 struct sk_buff *p; 6072 int eprec = -1; /* precedence to evict from */ 6073 6074 /* Determine precedence from which to evict packet, if any */ 6075 if (pktq_pfull(q, prec)) 6076 eprec = prec; 6077 else if (pktq_full(q)) { 6078 p = brcmu_pktq_peek_tail(q, &eprec); 6079 if (eprec > prec) { 6080 wiphy_err(wlc->wiphy, "%s: Failing: eprec %d > prec %d" 6081 "\n", __func__, eprec, prec); 6082 return false; 6083 } 6084 } 6085 6086 /* Evict if needed */ 6087 if (eprec >= 0) { 6088 bool discard_oldest; 6089 6090 discard_oldest = ac_bitmap_tst(0, eprec); 6091 6092 /* Refuse newer packet unless configured to discard oldest */ 6093 if (eprec == prec && !discard_oldest) { 6094 wiphy_err(wlc->wiphy, "%s: No where to go, prec == %d" 6095 "\n", __func__, prec); 6096 return false; 6097 } 6098 6099 /* Evict packet according to discard policy */ 6100 p = discard_oldest ? brcmu_pktq_pdeq(q, eprec) : 6101 brcmu_pktq_pdeq_tail(q, eprec); 6102 brcmu_pkt_buf_free_skb(p); 6103 } 6104 6105 /* Enqueue */ 6106 if (head) 6107 p = brcmu_pktq_penq_head(q, prec, pkt); 6108 else 6109 p = brcmu_pktq_penq(q, prec, pkt); 6110 6111 return true; 6112} 6113 6114/* 6115 * Attempts to queue a packet onto a multiple-precedence queue, 6116 * if necessary evicting a lower precedence packet from the queue. 6117 * 6118 * 'prec' is the precedence number that has already been mapped 6119 * from the packet priority. 6120 * 6121 * Returns true if packet consumed (queued), false if not. 6122 */ 6123static bool brcms_c_prec_enq(struct brcms_c_info *wlc, struct pktq *q, 6124 struct sk_buff *pkt, int prec) 6125{ 6126 return brcms_c_prec_enq_head(wlc, q, pkt, prec, false); 6127} 6128 6129void brcms_c_txq_enq(struct brcms_c_info *wlc, struct scb *scb, 6130 struct sk_buff *sdu, uint prec) 6131{ 6132 struct brcms_txq_info *qi = wlc->pkt_queue; /* Check me */ 6133 struct pktq *q = &qi->q; 6134 int prio; 6135 6136 prio = sdu->priority; 6137 6138 if (!brcms_c_prec_enq(wlc, q, sdu, prec)) { 6139 /* 6140 * we might hit this condtion in case 6141 * packet flooding from mac80211 stack 6142 */ 6143 brcmu_pkt_buf_free_skb(sdu); 6144 } 6145} 6146 6147/* 6148 * bcmc_fid_generate: 6149 * Generate frame ID for a BCMC packet. The frag field is not used 6150 * for MC frames so is used as part of the sequence number. 6151 */ 6152static inline u16 6153bcmc_fid_generate(struct brcms_c_info *wlc, struct brcms_bss_cfg *bsscfg, 6154 struct d11txh *txh) 6155{ 6156 u16 frameid; 6157 6158 frameid = le16_to_cpu(txh->TxFrameID) & ~(TXFID_SEQ_MASK | 6159 TXFID_QUEUE_MASK); 6160 frameid |= 6161 (((wlc-> 6162 mc_fid_counter++) << TXFID_SEQ_SHIFT) & TXFID_SEQ_MASK) | 6163 TX_BCMC_FIFO; 6164 6165 return frameid; 6166} 6167 6168static uint 6169brcms_c_calc_ack_time(struct brcms_c_info *wlc, u32 rspec, 6170 u8 preamble_type) 6171{ 6172 uint dur = 0; 6173 6174 BCMMSG(wlc->wiphy, "wl%d: rspec 0x%x, preamble_type %d\n", 6175 wlc->pub->unit, rspec, preamble_type); 6176 /* 6177 * Spec 9.6: ack rate is the highest rate in BSSBasicRateSet that 6178 * is less than or equal to the rate of the immediately previous 6179 * frame in the FES 6180 */ 6181 rspec = brcms_basic_rate(wlc, rspec); 6182 /* ACK frame len == 14 == 2(fc) + 2(dur) + 6(ra) + 4(fcs) */ 6183 dur = 6184 brcms_c_calc_frame_time(wlc, rspec, preamble_type, 6185 (DOT11_ACK_LEN + FCS_LEN)); 6186 return dur; 6187} 6188 6189static uint 6190brcms_c_calc_cts_time(struct brcms_c_info *wlc, u32 rspec, 6191 u8 preamble_type) 6192{ 6193 BCMMSG(wlc->wiphy, "wl%d: ratespec 0x%x, preamble_type %d\n", 6194 wlc->pub->unit, rspec, preamble_type); 6195 return brcms_c_calc_ack_time(wlc, rspec, preamble_type); 6196} 6197 6198static uint 6199brcms_c_calc_ba_time(struct brcms_c_info *wlc, u32 rspec, 6200 u8 preamble_type) 6201{ 6202 BCMMSG(wlc->wiphy, "wl%d: rspec 0x%x, " 6203 "preamble_type %d\n", wlc->pub->unit, rspec, preamble_type); 6204 /* 6205 * Spec 9.6: ack rate is the highest rate in BSSBasicRateSet that 6206 * is less than or equal to the rate of the immediately previous 6207 * frame in the FES 6208 */ 6209 rspec = brcms_basic_rate(wlc, rspec); 6210 /* BA len == 32 == 16(ctl hdr) + 4(ba len) + 8(bitmap) + 4(fcs) */ 6211 return brcms_c_calc_frame_time(wlc, rspec, preamble_type, 6212 (DOT11_BA_LEN + DOT11_BA_BITMAP_LEN + 6213 FCS_LEN)); 6214} 6215 6216/* brcms_c_compute_frame_dur() 6217 * 6218 * Calculate the 802.11 MAC header DUR field for MPDU 6219 * DUR for a single frame = 1 SIFS + 1 ACK 6220 * DUR for a frame with following frags = 3 SIFS + 2 ACK + next frag time 6221 * 6222 * rate MPDU rate in unit of 500kbps 6223 * next_frag_len next MPDU length in bytes 6224 * preamble_type use short/GF or long/MM PLCP header 6225 */ 6226static u16 6227brcms_c_compute_frame_dur(struct brcms_c_info *wlc, u32 rate, 6228 u8 preamble_type, uint next_frag_len) 6229{ 6230 u16 dur, sifs; 6231 6232 sifs = get_sifs(wlc->band); 6233 6234 dur = sifs; 6235 dur += (u16) brcms_c_calc_ack_time(wlc, rate, preamble_type); 6236 6237 if (next_frag_len) { 6238 /* Double the current DUR to get 2 SIFS + 2 ACKs */ 6239 dur *= 2; 6240 /* add another SIFS and the frag time */ 6241 dur += sifs; 6242 dur += 6243 (u16) brcms_c_calc_frame_time(wlc, rate, preamble_type, 6244 next_frag_len); 6245 } 6246 return dur; 6247} 6248 6249/* The opposite of brcms_c_calc_frame_time */ 6250static uint 6251brcms_c_calc_frame_len(struct brcms_c_info *wlc, u32 ratespec, 6252 u8 preamble_type, uint dur) 6253{ 6254 uint nsyms, mac_len, Ndps, kNdps; 6255 uint rate = rspec2rate(ratespec); 6256 6257 BCMMSG(wlc->wiphy, "wl%d: rspec 0x%x, preamble_type %d, dur %d\n", 6258 wlc->pub->unit, ratespec, preamble_type, dur); 6259 6260 if (is_mcs_rate(ratespec)) { 6261 uint mcs = ratespec & RSPEC_RATE_MASK; 6262 int tot_streams = mcs_2_txstreams(mcs) + rspec_stc(ratespec); 6263 dur -= PREN_PREAMBLE + (tot_streams * PREN_PREAMBLE_EXT); 6264 /* payload calculation matches that of regular ofdm */ 6265 if (wlc->band->bandtype == BRCM_BAND_2G) 6266 dur -= DOT11_OFDM_SIGNAL_EXTENSION; 6267 /* kNdbps = kbps * 4 */ 6268 kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec), 6269 rspec_issgi(ratespec)) * 4; 6270 nsyms = dur / APHY_SYMBOL_TIME; 6271 mac_len = 6272 ((nsyms * kNdps) - 6273 ((APHY_SERVICE_NBITS + APHY_TAIL_NBITS) * 1000)) / 8000; 6274 } else if (is_ofdm_rate(ratespec)) { 6275 dur -= APHY_PREAMBLE_TIME; 6276 dur -= APHY_SIGNAL_TIME; 6277 /* Ndbps = Mbps * 4 = rate(500Kbps) * 2 */ 6278 Ndps = rate * 2; 6279 nsyms = dur / APHY_SYMBOL_TIME; 6280 mac_len = 6281 ((nsyms * Ndps) - 6282 (APHY_SERVICE_NBITS + APHY_TAIL_NBITS)) / 8; 6283 } else { 6284 if (preamble_type & BRCMS_SHORT_PREAMBLE) 6285 dur -= BPHY_PLCP_SHORT_TIME; 6286 else 6287 dur -= BPHY_PLCP_TIME; 6288 mac_len = dur * rate; 6289 /* divide out factor of 2 in rate (1/2 mbps) */ 6290 mac_len = mac_len / 8 / 2; 6291 } 6292 return mac_len; 6293} 6294 6295/* 6296 * Return true if the specified rate is supported by the specified band. 6297 * BRCM_BAND_AUTO indicates the current band. 6298 */ 6299static bool brcms_c_valid_rate(struct brcms_c_info *wlc, u32 rspec, int band, 6300 bool verbose) 6301{ 6302 struct brcms_c_rateset *hw_rateset; 6303 uint i; 6304 6305 if ((band == BRCM_BAND_AUTO) || (band == wlc->band->bandtype)) 6306 hw_rateset = &wlc->band->hw_rateset; 6307 else if (wlc->pub->_nbands > 1) 6308 hw_rateset = &wlc->bandstate[OTHERBANDUNIT(wlc)]->hw_rateset; 6309 else 6310 /* other band specified and we are a single band device */ 6311 return false; 6312 6313 /* check if this is a mimo rate */ 6314 if (is_mcs_rate(rspec)) { 6315 if ((rspec & RSPEC_RATE_MASK) >= MCS_TABLE_SIZE) 6316 goto error; 6317 6318 return isset(hw_rateset->mcs, (rspec & RSPEC_RATE_MASK)); 6319 } 6320 6321 for (i = 0; i < hw_rateset->count; i++) 6322 if (hw_rateset->rates[i] == rspec2rate(rspec)) 6323 return true; 6324 error: 6325 if (verbose) 6326 wiphy_err(wlc->wiphy, "wl%d: valid_rate: rate spec 0x%x " 6327 "not in hw_rateset\n", wlc->pub->unit, rspec); 6328 6329 return false; 6330} 6331 6332static u32 6333mac80211_wlc_set_nrate(struct brcms_c_info *wlc, struct brcms_band *cur_band, 6334 u32 int_val) 6335{ 6336 u8 stf = (int_val & NRATE_STF_MASK) >> NRATE_STF_SHIFT; 6337 u8 rate = int_val & NRATE_RATE_MASK; 6338 u32 rspec; 6339 bool ismcs = ((int_val & NRATE_MCS_INUSE) == NRATE_MCS_INUSE); 6340 bool issgi = ((int_val & NRATE_SGI_MASK) >> NRATE_SGI_SHIFT); 6341 bool override_mcs_only = ((int_val & NRATE_OVERRIDE_MCS_ONLY) 6342 == NRATE_OVERRIDE_MCS_ONLY); 6343 int bcmerror = 0; 6344 6345 if (!ismcs) 6346 return (u32) rate; 6347 6348 /* validate the combination of rate/mcs/stf is allowed */ 6349 if ((wlc->pub->_n_enab & SUPPORT_11N) && ismcs) { 6350 /* mcs only allowed when nmode */ 6351 if (stf > PHY_TXC1_MODE_SDM) { 6352 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid stf\n", 6353 wlc->pub->unit, __func__); 6354 bcmerror = -EINVAL; 6355 goto done; 6356 } 6357 6358 /* mcs 32 is a special case, DUP mode 40 only */ 6359 if (rate == 32) { 6360 if (!CHSPEC_IS40(wlc->home_chanspec) || 6361 ((stf != PHY_TXC1_MODE_SISO) 6362 && (stf != PHY_TXC1_MODE_CDD))) { 6363 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid mcs " 6364 "32\n", wlc->pub->unit, __func__); 6365 bcmerror = -EINVAL; 6366 goto done; 6367 } 6368 /* mcs > 7 must use stf SDM */ 6369 } else if (rate > HIGHEST_SINGLE_STREAM_MCS) { 6370 /* mcs > 7 must use stf SDM */ 6371 if (stf != PHY_TXC1_MODE_SDM) { 6372 BCMMSG(wlc->wiphy, "wl%d: enabling " 6373 "SDM mode for mcs %d\n", 6374 wlc->pub->unit, rate); 6375 stf = PHY_TXC1_MODE_SDM; 6376 } 6377 } else { 6378 /* 6379 * MCS 0-7 may use SISO, CDD, and for 6380 * phy_rev >= 3 STBC 6381 */ 6382 if ((stf > PHY_TXC1_MODE_STBC) || 6383 (!BRCMS_STBC_CAP_PHY(wlc) 6384 && (stf == PHY_TXC1_MODE_STBC))) { 6385 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid STBC" 6386 "\n", wlc->pub->unit, __func__); 6387 bcmerror = -EINVAL; 6388 goto done; 6389 } 6390 } 6391 } else if (is_ofdm_rate(rate)) { 6392 if ((stf != PHY_TXC1_MODE_CDD) && (stf != PHY_TXC1_MODE_SISO)) { 6393 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid OFDM\n", 6394 wlc->pub->unit, __func__); 6395 bcmerror = -EINVAL; 6396 goto done; 6397 } 6398 } else if (is_cck_rate(rate)) { 6399 if ((cur_band->bandtype != BRCM_BAND_2G) 6400 || (stf != PHY_TXC1_MODE_SISO)) { 6401 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid CCK\n", 6402 wlc->pub->unit, __func__); 6403 bcmerror = -EINVAL; 6404 goto done; 6405 } 6406 } else { 6407 wiphy_err(wlc->wiphy, "wl%d: %s: Unknown rate type\n", 6408 wlc->pub->unit, __func__); 6409 bcmerror = -EINVAL; 6410 goto done; 6411 } 6412 /* make sure multiple antennae are available for non-siso rates */ 6413 if ((stf != PHY_TXC1_MODE_SISO) && (wlc->stf->txstreams == 1)) { 6414 wiphy_err(wlc->wiphy, "wl%d: %s: SISO antenna but !SISO " 6415 "request\n", wlc->pub->unit, __func__); 6416 bcmerror = -EINVAL; 6417 goto done; 6418 } 6419 6420 rspec = rate; 6421 if (ismcs) { 6422 rspec |= RSPEC_MIMORATE; 6423 /* For STBC populate the STC field of the ratespec */ 6424 if (stf == PHY_TXC1_MODE_STBC) { 6425 u8 stc; 6426 stc = 1; /* Nss for single stream is always 1 */ 6427 rspec |= (stc << RSPEC_STC_SHIFT); 6428 } 6429 } 6430 6431 rspec |= (stf << RSPEC_STF_SHIFT); 6432 6433 if (override_mcs_only) 6434 rspec |= RSPEC_OVERRIDE_MCS_ONLY; 6435 6436 if (issgi) 6437 rspec |= RSPEC_SHORT_GI; 6438 6439 if ((rate != 0) 6440 && !brcms_c_valid_rate(wlc, rspec, cur_band->bandtype, true)) 6441 return rate; 6442 6443 return rspec; 6444done: 6445 return rate; 6446} 6447 6448/* 6449 * Compute PLCP, but only requires actual rate and length of pkt. 6450 * Rate is given in the driver standard multiple of 500 kbps. 6451 * le is set for 11 Mbps rate if necessary. 6452 * Broken out for PRQ. 6453 */ 6454 6455static void brcms_c_cck_plcp_set(struct brcms_c_info *wlc, int rate_500, 6456 uint length, u8 *plcp) 6457{ 6458 u16 usec = 0; 6459 u8 le = 0; 6460 6461 switch (rate_500) { 6462 case BRCM_RATE_1M: 6463 usec = length << 3; 6464 break; 6465 case BRCM_RATE_2M: 6466 usec = length << 2; 6467 break; 6468 case BRCM_RATE_5M5: 6469 usec = (length << 4) / 11; 6470 if ((length << 4) - (usec * 11) > 0) 6471 usec++; 6472 break; 6473 case BRCM_RATE_11M: 6474 usec = (length << 3) / 11; 6475 if ((length << 3) - (usec * 11) > 0) { 6476 usec++; 6477 if ((usec * 11) - (length << 3) >= 8) 6478 le = D11B_PLCP_SIGNAL_LE; 6479 } 6480 break; 6481 6482 default: 6483 wiphy_err(wlc->wiphy, 6484 "brcms_c_cck_plcp_set: unsupported rate %d\n", 6485 rate_500); 6486 rate_500 = BRCM_RATE_1M; 6487 usec = length << 3; 6488 break; 6489 } 6490 /* PLCP signal byte */ 6491 plcp[0] = rate_500 * 5; /* r (500kbps) * 5 == r (100kbps) */ 6492 /* PLCP service byte */ 6493 plcp[1] = (u8) (le | D11B_PLCP_SIGNAL_LOCKED); 6494 /* PLCP length u16, little endian */ 6495 plcp[2] = usec & 0xff; 6496 plcp[3] = (usec >> 8) & 0xff; 6497 /* PLCP CRC16 */ 6498 plcp[4] = 0; 6499 plcp[5] = 0; 6500} 6501 6502/* Rate: 802.11 rate code, length: PSDU length in octets */ 6503static void brcms_c_compute_mimo_plcp(u32 rspec, uint length, u8 *plcp) 6504{ 6505 u8 mcs = (u8) (rspec & RSPEC_RATE_MASK); 6506 plcp[0] = mcs; 6507 if (rspec_is40mhz(rspec) || (mcs == 32)) 6508 plcp[0] |= MIMO_PLCP_40MHZ; 6509 BRCMS_SET_MIMO_PLCP_LEN(plcp, length); 6510 plcp[3] = rspec_mimoplcp3(rspec); /* rspec already holds this byte */ 6511 plcp[3] |= 0x7; /* set smoothing, not sounding ppdu & reserved */ 6512 plcp[4] = 0; /* number of extension spatial streams bit 0 & 1 */ 6513 plcp[5] = 0; 6514} 6515 6516/* Rate: 802.11 rate code, length: PSDU length in octets */ 6517static void 6518brcms_c_compute_ofdm_plcp(u32 rspec, u32 length, u8 *plcp) 6519{ 6520 u8 rate_signal; 6521 u32 tmp = 0; 6522 int rate = rspec2rate(rspec); 6523 6524 /* 6525 * encode rate per 802.11a-1999 sec 17.3.4.1, with lsb 6526 * transmitted first 6527 */ 6528 rate_signal = rate_info[rate] & BRCMS_RATE_MASK; 6529 memset(plcp, 0, D11_PHY_HDR_LEN); 6530 D11A_PHY_HDR_SRATE((struct ofdm_phy_hdr *) plcp, rate_signal); 6531 6532 tmp = (length & 0xfff) << 5; 6533 plcp[2] |= (tmp >> 16) & 0xff; 6534 plcp[1] |= (tmp >> 8) & 0xff; 6535 plcp[0] |= tmp & 0xff; 6536} 6537 6538/* Rate: 802.11 rate code, length: PSDU length in octets */ 6539static void brcms_c_compute_cck_plcp(struct brcms_c_info *wlc, u32 rspec, 6540 uint length, u8 *plcp) 6541{ 6542 int rate = rspec2rate(rspec); 6543 6544 brcms_c_cck_plcp_set(wlc, rate, length, plcp); 6545} 6546 6547static void 6548brcms_c_compute_plcp(struct brcms_c_info *wlc, u32 rspec, 6549 uint length, u8 *plcp) 6550{ 6551 if (is_mcs_rate(rspec)) 6552 brcms_c_compute_mimo_plcp(rspec, length, plcp); 6553 else if (is_ofdm_rate(rspec)) 6554 brcms_c_compute_ofdm_plcp(rspec, length, plcp); 6555 else 6556 brcms_c_compute_cck_plcp(wlc, rspec, length, plcp); 6557} 6558 6559/* brcms_c_compute_rtscts_dur() 6560 * 6561 * Calculate the 802.11 MAC header DUR field for an RTS or CTS frame 6562 * DUR for normal RTS/CTS w/ frame = 3 SIFS + 1 CTS + next frame time + 1 ACK 6563 * DUR for CTS-TO-SELF w/ frame = 2 SIFS + next frame time + 1 ACK 6564 * 6565 * cts cts-to-self or rts/cts 6566 * rts_rate rts or cts rate in unit of 500kbps 6567 * rate next MPDU rate in unit of 500kbps 6568 * frame_len next MPDU frame length in bytes 6569 */ 6570u16 6571brcms_c_compute_rtscts_dur(struct brcms_c_info *wlc, bool cts_only, 6572 u32 rts_rate, 6573 u32 frame_rate, u8 rts_preamble_type, 6574 u8 frame_preamble_type, uint frame_len, bool ba) 6575{ 6576 u16 dur, sifs; 6577 6578 sifs = get_sifs(wlc->band); 6579 6580 if (!cts_only) { 6581 /* RTS/CTS */ 6582 dur = 3 * sifs; 6583 dur += 6584 (u16) brcms_c_calc_cts_time(wlc, rts_rate, 6585 rts_preamble_type); 6586 } else { 6587 /* CTS-TO-SELF */ 6588 dur = 2 * sifs; 6589 } 6590 6591 dur += 6592 (u16) brcms_c_calc_frame_time(wlc, frame_rate, frame_preamble_type, 6593 frame_len); 6594 if (ba) 6595 dur += 6596 (u16) brcms_c_calc_ba_time(wlc, frame_rate, 6597 BRCMS_SHORT_PREAMBLE); 6598 else 6599 dur += 6600 (u16) brcms_c_calc_ack_time(wlc, frame_rate, 6601 frame_preamble_type); 6602 return dur; 6603} 6604 6605static u16 brcms_c_phytxctl1_calc(struct brcms_c_info *wlc, u32 rspec) 6606{ 6607 u16 phyctl1 = 0; 6608 u16 bw; 6609 6610 if (BRCMS_ISLCNPHY(wlc->band)) { 6611 bw = PHY_TXC1_BW_20MHZ; 6612 } else { 6613 bw = rspec_get_bw(rspec); 6614 /* 10Mhz is not supported yet */ 6615 if (bw < PHY_TXC1_BW_20MHZ) { 6616 wiphy_err(wlc->wiphy, "phytxctl1_calc: bw %d is " 6617 "not supported yet, set to 20L\n", bw); 6618 bw = PHY_TXC1_BW_20MHZ; 6619 } 6620 } 6621 6622 if (is_mcs_rate(rspec)) { 6623 uint mcs = rspec & RSPEC_RATE_MASK; 6624 6625 /* bw, stf, coding-type is part of rspec_phytxbyte2 returns */ 6626 phyctl1 = rspec_phytxbyte2(rspec); 6627 /* set the upper byte of phyctl1 */ 6628 phyctl1 |= (mcs_table[mcs].tx_phy_ctl3 << 8); 6629 } else if (is_cck_rate(rspec) && !BRCMS_ISLCNPHY(wlc->band) 6630 && !BRCMS_ISSSLPNPHY(wlc->band)) { 6631 /* 6632 * In CCK mode LPPHY overloads OFDM Modulation bits with CCK 6633 * Data Rate. Eventually MIMOPHY would also be converted to 6634 * this format 6635 */ 6636 /* 0 = 1Mbps; 1 = 2Mbps; 2 = 5.5Mbps; 3 = 11Mbps */ 6637 phyctl1 = (bw | (rspec_stf(rspec) << PHY_TXC1_MODE_SHIFT)); 6638 } else { /* legacy OFDM/CCK */ 6639 s16 phycfg; 6640 /* get the phyctl byte from rate phycfg table */ 6641 phycfg = brcms_c_rate_legacy_phyctl(rspec2rate(rspec)); 6642 if (phycfg == -1) { 6643 wiphy_err(wlc->wiphy, "phytxctl1_calc: wrong " 6644 "legacy OFDM/CCK rate\n"); 6645 phycfg = 0; 6646 } 6647 /* set the upper byte of phyctl1 */ 6648 phyctl1 = 6649 (bw | (phycfg << 8) | 6650 (rspec_stf(rspec) << PHY_TXC1_MODE_SHIFT)); 6651 } 6652 return phyctl1; 6653} 6654 6655/* 6656 * Add struct d11txh, struct cck_phy_hdr. 6657 * 6658 * 'p' data must start with 802.11 MAC header 6659 * 'p' must allow enough bytes of local headers to be "pushed" onto the packet 6660 * 6661 * headroom == D11_PHY_HDR_LEN + D11_TXH_LEN (D11_TXH_LEN is now 104 bytes) 6662 * 6663 */ 6664static u16 6665brcms_c_d11hdrs_mac80211(struct brcms_c_info *wlc, struct ieee80211_hw *hw, 6666 struct sk_buff *p, struct scb *scb, uint frag, 6667 uint nfrags, uint queue, uint next_frag_len) 6668{ 6669 struct ieee80211_hdr *h; 6670 struct d11txh *txh; 6671 u8 *plcp, plcp_fallback[D11_PHY_HDR_LEN]; 6672 int len, phylen, rts_phylen; 6673 u16 mch, phyctl, xfts, mainrates; 6674 u16 seq = 0, mcl = 0, status = 0, frameid = 0; 6675 u32 rspec[2] = { BRCM_RATE_1M, BRCM_RATE_1M }; 6676 u32 rts_rspec[2] = { BRCM_RATE_1M, BRCM_RATE_1M }; 6677 bool use_rts = false; 6678 bool use_cts = false; 6679 bool use_rifs = false; 6680 bool short_preamble[2] = { false, false }; 6681 u8 preamble_type[2] = { BRCMS_LONG_PREAMBLE, BRCMS_LONG_PREAMBLE }; 6682 u8 rts_preamble_type[2] = { BRCMS_LONG_PREAMBLE, BRCMS_LONG_PREAMBLE }; 6683 u8 *rts_plcp, rts_plcp_fallback[D11_PHY_HDR_LEN]; 6684 struct ieee80211_rts *rts = NULL; 6685 bool qos; 6686 uint ac; 6687 bool hwtkmic = false; 6688 u16 mimo_ctlchbw = PHY_TXC1_BW_20MHZ; 6689#define ANTCFG_NONE 0xFF 6690 u8 antcfg = ANTCFG_NONE; 6691 u8 fbantcfg = ANTCFG_NONE; 6692 uint phyctl1_stf = 0; 6693 u16 durid = 0; 6694 struct ieee80211_tx_rate *txrate[2]; 6695 int k; 6696 struct ieee80211_tx_info *tx_info; 6697 bool is_mcs; 6698 u16 mimo_txbw; 6699 u8 mimo_preamble_type; 6700 6701 /* locate 802.11 MAC header */ 6702 h = (struct ieee80211_hdr *)(p->data); 6703 qos = ieee80211_is_data_qos(h->frame_control); 6704 6705 /* compute length of frame in bytes for use in PLCP computations */ 6706 len = p->len; 6707 phylen = len + FCS_LEN; 6708 6709 /* Get tx_info */ 6710 tx_info = IEEE80211_SKB_CB(p); 6711 6712 /* add PLCP */ 6713 plcp = skb_push(p, D11_PHY_HDR_LEN); 6714 6715 /* add Broadcom tx descriptor header */ 6716 txh = (struct d11txh *) skb_push(p, D11_TXH_LEN); 6717 memset(txh, 0, D11_TXH_LEN); 6718 6719 /* setup frameid */ 6720 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { 6721 /* non-AP STA should never use BCMC queue */ 6722 if (queue == TX_BCMC_FIFO) { 6723 wiphy_err(wlc->wiphy, "wl%d: %s: ASSERT queue == " 6724 "TX_BCMC!\n", wlc->pub->unit, __func__); 6725 frameid = bcmc_fid_generate(wlc, NULL, txh); 6726 } else { 6727 /* Increment the counter for first fragment */ 6728 if (tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) 6729 scb->seqnum[p->priority]++; 6730 6731 /* extract fragment number from frame first */ 6732 seq = le16_to_cpu(h->seq_ctrl) & FRAGNUM_MASK; 6733 seq |= (scb->seqnum[p->priority] << SEQNUM_SHIFT); 6734 h->seq_ctrl = cpu_to_le16(seq); 6735 6736 frameid = ((seq << TXFID_SEQ_SHIFT) & TXFID_SEQ_MASK) | 6737 (queue & TXFID_QUEUE_MASK); 6738 } 6739 } 6740 frameid |= queue & TXFID_QUEUE_MASK; 6741 6742 /* set the ignpmq bit for all pkts tx'd in PS mode and for beacons */ 6743 if (ieee80211_is_beacon(h->frame_control)) 6744 mcl |= TXC_IGNOREPMQ; 6745 6746 txrate[0] = tx_info->control.rates; 6747 txrate[1] = txrate[0] + 1; 6748 6749 /* 6750 * if rate control algorithm didn't give us a fallback 6751 * rate, use the primary rate 6752 */ 6753 if (txrate[1]->idx < 0) 6754 txrate[1] = txrate[0]; 6755 6756 for (k = 0; k < hw->max_rates; k++) { 6757 is_mcs = txrate[k]->flags & IEEE80211_TX_RC_MCS ? true : false; 6758 if (!is_mcs) { 6759 if ((txrate[k]->idx >= 0) 6760 && (txrate[k]->idx < 6761 hw->wiphy->bands[tx_info->band]->n_bitrates)) { 6762 rspec[k] = 6763 hw->wiphy->bands[tx_info->band]-> 6764 bitrates[txrate[k]->idx].hw_value; 6765 short_preamble[k] = 6766 txrate[k]-> 6767 flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE ? 6768 true : false; 6769 } else { 6770 rspec[k] = BRCM_RATE_1M; 6771 } 6772 } else { 6773 rspec[k] = mac80211_wlc_set_nrate(wlc, wlc->band, 6774 NRATE_MCS_INUSE | txrate[k]->idx); 6775 } 6776 6777 /* 6778 * Currently only support same setting for primay and 6779 * fallback rates. Unify flags for each rate into a 6780 * single value for the frame 6781 */ 6782 use_rts |= 6783 txrate[k]-> 6784 flags & IEEE80211_TX_RC_USE_RTS_CTS ? true : false; 6785 use_cts |= 6786 txrate[k]-> 6787 flags & IEEE80211_TX_RC_USE_CTS_PROTECT ? true : false; 6788 6789 6790 /* 6791 * (1) RATE: 6792 * determine and validate primary rate 6793 * and fallback rates 6794 */ 6795 if (!rspec_active(rspec[k])) { 6796 rspec[k] = BRCM_RATE_1M; 6797 } else { 6798 if (!is_multicast_ether_addr(h->addr1)) { 6799 /* set tx antenna config */ 6800 brcms_c_antsel_antcfg_get(wlc->asi, false, 6801 false, 0, 0, &antcfg, &fbantcfg); 6802 } 6803 } 6804 } 6805 6806 phyctl1_stf = wlc->stf->ss_opmode; 6807 6808 if (wlc->pub->_n_enab & SUPPORT_11N) { 6809 for (k = 0; k < hw->max_rates; k++) { 6810 /* 6811 * apply siso/cdd to single stream mcs's or ofdm 6812 * if rspec is auto selected 6813 */ 6814 if (((is_mcs_rate(rspec[k]) && 6815 is_single_stream(rspec[k] & RSPEC_RATE_MASK)) || 6816 is_ofdm_rate(rspec[k])) 6817 && ((rspec[k] & RSPEC_OVERRIDE_MCS_ONLY) 6818 || !(rspec[k] & RSPEC_OVERRIDE))) { 6819 rspec[k] &= ~(RSPEC_STF_MASK | RSPEC_STC_MASK); 6820 6821 /* For SISO MCS use STBC if possible */ 6822 if (is_mcs_rate(rspec[k]) 6823 && BRCMS_STF_SS_STBC_TX(wlc, scb)) { 6824 u8 stc; 6825 6826 /* Nss for single stream is always 1 */ 6827 stc = 1; 6828 rspec[k] |= (PHY_TXC1_MODE_STBC << 6829 RSPEC_STF_SHIFT) | 6830 (stc << RSPEC_STC_SHIFT); 6831 } else 6832 rspec[k] |= 6833 (phyctl1_stf << RSPEC_STF_SHIFT); 6834 } 6835 6836 /* 6837 * Is the phy configured to use 40MHZ frames? If 6838 * so then pick the desired txbw 6839 */ 6840 if (brcms_chspec_bw(wlc->chanspec) == BRCMS_40_MHZ) { 6841 /* default txbw is 20in40 SB */ 6842 mimo_ctlchbw = mimo_txbw = 6843 CHSPEC_SB_UPPER(wlc_phy_chanspec_get( 6844 wlc->band->pi)) 6845 ? PHY_TXC1_BW_20MHZ_UP : PHY_TXC1_BW_20MHZ; 6846 6847 if (is_mcs_rate(rspec[k])) { 6848 /* mcs 32 must be 40b/w DUP */ 6849 if ((rspec[k] & RSPEC_RATE_MASK) 6850 == 32) { 6851 mimo_txbw = 6852 PHY_TXC1_BW_40MHZ_DUP; 6853 /* use override */ 6854 } else if (wlc->mimo_40txbw != AUTO) 6855 mimo_txbw = wlc->mimo_40txbw; 6856 /* else check if dst is using 40 Mhz */ 6857 else if (scb->flags & SCB_IS40) 6858 mimo_txbw = PHY_TXC1_BW_40MHZ; 6859 } else if (is_ofdm_rate(rspec[k])) { 6860 if (wlc->ofdm_40txbw != AUTO) 6861 mimo_txbw = wlc->ofdm_40txbw; 6862 } else if (wlc->cck_40txbw != AUTO) { 6863 mimo_txbw = wlc->cck_40txbw; 6864 } 6865 } else { 6866 /* 6867 * mcs32 is 40 b/w only. 6868 * This is possible for probe packets on 6869 * a STA during SCAN 6870 */ 6871 if ((rspec[k] & RSPEC_RATE_MASK) == 32) 6872 /* mcs 0 */ 6873 rspec[k] = RSPEC_MIMORATE; 6874 6875 mimo_txbw = PHY_TXC1_BW_20MHZ; 6876 } 6877 6878 /* Set channel width */ 6879 rspec[k] &= ~RSPEC_BW_MASK; 6880 if ((k == 0) || ((k > 0) && is_mcs_rate(rspec[k]))) 6881 rspec[k] |= (mimo_txbw << RSPEC_BW_SHIFT); 6882 else 6883 rspec[k] |= (mimo_ctlchbw << RSPEC_BW_SHIFT); 6884 6885 /* Disable short GI, not supported yet */ 6886 rspec[k] &= ~RSPEC_SHORT_GI; 6887 6888 mimo_preamble_type = BRCMS_MM_PREAMBLE; 6889 if (txrate[k]->flags & IEEE80211_TX_RC_GREEN_FIELD) 6890 mimo_preamble_type = BRCMS_GF_PREAMBLE; 6891 6892 if ((txrate[k]->flags & IEEE80211_TX_RC_MCS) 6893 && (!is_mcs_rate(rspec[k]))) { 6894 wiphy_err(wlc->wiphy, "wl%d: %s: IEEE80211_TX_" 6895 "RC_MCS != is_mcs_rate(rspec)\n", 6896 wlc->pub->unit, __func__); 6897 } 6898 6899 if (is_mcs_rate(rspec[k])) { 6900 preamble_type[k] = mimo_preamble_type; 6901 6902 /* 6903 * if SGI is selected, then forced mm 6904 * for single stream 6905 */ 6906 if ((rspec[k] & RSPEC_SHORT_GI) 6907 && is_single_stream(rspec[k] & 6908 RSPEC_RATE_MASK)) 6909 preamble_type[k] = BRCMS_MM_PREAMBLE; 6910 } 6911 6912 /* should be better conditionalized */ 6913 if (!is_mcs_rate(rspec[0]) 6914 && (tx_info->control.rates[0]. 6915 flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)) 6916 preamble_type[k] = BRCMS_SHORT_PREAMBLE; 6917 } 6918 } else { 6919 for (k = 0; k < hw->max_rates; k++) { 6920 /* Set ctrlchbw as 20Mhz */ 6921 rspec[k] &= ~RSPEC_BW_MASK; 6922 rspec[k] |= (PHY_TXC1_BW_20MHZ << RSPEC_BW_SHIFT); 6923 6924 /* for nphy, stf of ofdm frames must follow policies */ 6925 if (BRCMS_ISNPHY(wlc->band) && is_ofdm_rate(rspec[k])) { 6926 rspec[k] &= ~RSPEC_STF_MASK; 6927 rspec[k] |= phyctl1_stf << RSPEC_STF_SHIFT; 6928 } 6929 } 6930 } 6931 6932 /* Reset these for use with AMPDU's */ 6933 txrate[0]->count = 0; 6934 txrate[1]->count = 0; 6935 6936 /* (2) PROTECTION, may change rspec */ 6937 if ((ieee80211_is_data(h->frame_control) || 6938 ieee80211_is_mgmt(h->frame_control)) && 6939 (phylen > wlc->RTSThresh) && !is_multicast_ether_addr(h->addr1)) 6940 use_rts = true; 6941 6942 /* (3) PLCP: determine PLCP header and MAC duration, 6943 * fill struct d11txh */ 6944 brcms_c_compute_plcp(wlc, rspec[0], phylen, plcp); 6945 brcms_c_compute_plcp(wlc, rspec[1], phylen, plcp_fallback); 6946 memcpy(&txh->FragPLCPFallback, 6947 plcp_fallback, sizeof(txh->FragPLCPFallback)); 6948 6949 /* Length field now put in CCK FBR CRC field */ 6950 if (is_cck_rate(rspec[1])) { 6951 txh->FragPLCPFallback[4] = phylen & 0xff; 6952 txh->FragPLCPFallback[5] = (phylen & 0xff00) >> 8; 6953 } 6954 6955 /* MIMO-RATE: need validation ?? */ 6956 mainrates = is_ofdm_rate(rspec[0]) ? 6957 D11A_PHY_HDR_GRATE((struct ofdm_phy_hdr *) plcp) : 6958 plcp[0]; 6959 6960 /* DUR field for main rate */ 6961 if (!ieee80211_is_pspoll(h->frame_control) && 6962 !is_multicast_ether_addr(h->addr1) && !use_rifs) { 6963 durid = 6964 brcms_c_compute_frame_dur(wlc, rspec[0], preamble_type[0], 6965 next_frag_len); 6966 h->duration_id = cpu_to_le16(durid); 6967 } else if (use_rifs) { 6968 /* NAV protect to end of next max packet size */ 6969 durid = 6970 (u16) brcms_c_calc_frame_time(wlc, rspec[0], 6971 preamble_type[0], 6972 DOT11_MAX_FRAG_LEN); 6973 durid += RIFS_11N_TIME; 6974 h->duration_id = cpu_to_le16(durid); 6975 } 6976 6977 /* DUR field for fallback rate */ 6978 if (ieee80211_is_pspoll(h->frame_control)) 6979 txh->FragDurFallback = h->duration_id; 6980 else if (is_multicast_ether_addr(h->addr1) || use_rifs) 6981 txh->FragDurFallback = 0; 6982 else { 6983 durid = brcms_c_compute_frame_dur(wlc, rspec[1], 6984 preamble_type[1], next_frag_len); 6985 txh->FragDurFallback = cpu_to_le16(durid); 6986 } 6987 6988 /* (4) MAC-HDR: MacTxControlLow */ 6989 if (frag == 0) 6990 mcl |= TXC_STARTMSDU; 6991 6992 if (!is_multicast_ether_addr(h->addr1)) 6993 mcl |= TXC_IMMEDACK; 6994 6995 if (wlc->band->bandtype == BRCM_BAND_5G) 6996 mcl |= TXC_FREQBAND_5G; 6997 6998 if (CHSPEC_IS40(wlc_phy_chanspec_get(wlc->band->pi))) 6999 mcl |= TXC_BW_40; 7000 7001 /* set AMIC bit if using hardware TKIP MIC */ 7002 if (hwtkmic) 7003 mcl |= TXC_AMIC; 7004 7005 txh->MacTxControlLow = cpu_to_le16(mcl); 7006 7007 /* MacTxControlHigh */ 7008 mch = 0; 7009 7010 /* Set fallback rate preamble type */ 7011 if ((preamble_type[1] == BRCMS_SHORT_PREAMBLE) || 7012 (preamble_type[1] == BRCMS_GF_PREAMBLE)) { 7013 if (rspec2rate(rspec[1]) != BRCM_RATE_1M) 7014 mch |= TXC_PREAMBLE_DATA_FB_SHORT; 7015 } 7016 7017 /* MacFrameControl */ 7018 memcpy(&txh->MacFrameControl, &h->frame_control, sizeof(u16)); 7019 txh->TxFesTimeNormal = cpu_to_le16(0); 7020 7021 txh->TxFesTimeFallback = cpu_to_le16(0); 7022 7023 /* TxFrameRA */ 7024 memcpy(&txh->TxFrameRA, &h->addr1, ETH_ALEN); 7025 7026 /* TxFrameID */ 7027 txh->TxFrameID = cpu_to_le16(frameid); 7028 7029 /* 7030 * TxStatus, Note the case of recreating the first frag of a suppressed 7031 * frame then we may need to reset the retry cnt's via the status reg 7032 */ 7033 txh->TxStatus = cpu_to_le16(status); 7034 7035 /* 7036 * extra fields for ucode AMPDU aggregation, the new fields are added to 7037 * the END of previous structure so that it's compatible in driver. 7038 */ 7039 txh->MaxNMpdus = cpu_to_le16(0); 7040 txh->MaxABytes_MRT = cpu_to_le16(0); 7041 txh->MaxABytes_FBR = cpu_to_le16(0); 7042 txh->MinMBytes = cpu_to_le16(0); 7043 7044 /* (5) RTS/CTS: determine RTS/CTS PLCP header and MAC duration, 7045 * furnish struct d11txh */ 7046 /* RTS PLCP header and RTS frame */ 7047 if (use_rts || use_cts) { 7048 if (use_rts && use_cts) 7049 use_cts = false; 7050 7051 for (k = 0; k < 2; k++) { 7052 rts_rspec[k] = brcms_c_rspec_to_rts_rspec(wlc, rspec[k], 7053 false, 7054 mimo_ctlchbw); 7055 } 7056 7057 if (!is_ofdm_rate(rts_rspec[0]) && 7058 !((rspec2rate(rts_rspec[0]) == BRCM_RATE_1M) || 7059 (wlc->PLCPHdr_override == BRCMS_PLCP_LONG))) { 7060 rts_preamble_type[0] = BRCMS_SHORT_PREAMBLE; 7061 mch |= TXC_PREAMBLE_RTS_MAIN_SHORT; 7062 } 7063 7064 if (!is_ofdm_rate(rts_rspec[1]) && 7065 !((rspec2rate(rts_rspec[1]) == BRCM_RATE_1M) || 7066 (wlc->PLCPHdr_override == BRCMS_PLCP_LONG))) { 7067 rts_preamble_type[1] = BRCMS_SHORT_PREAMBLE; 7068 mch |= TXC_PREAMBLE_RTS_FB_SHORT; 7069 } 7070 7071 /* RTS/CTS additions to MacTxControlLow */ 7072 if (use_cts) { 7073 txh->MacTxControlLow |= cpu_to_le16(TXC_SENDCTS); 7074 } else { 7075 txh->MacTxControlLow |= cpu_to_le16(TXC_SENDRTS); 7076 txh->MacTxControlLow |= cpu_to_le16(TXC_LONGFRAME); 7077 } 7078 7079 /* RTS PLCP header */ 7080 rts_plcp = txh->RTSPhyHeader; 7081 if (use_cts) 7082 rts_phylen = DOT11_CTS_LEN + FCS_LEN; 7083 else 7084 rts_phylen = DOT11_RTS_LEN + FCS_LEN; 7085 7086 brcms_c_compute_plcp(wlc, rts_rspec[0], rts_phylen, rts_plcp); 7087 7088 /* fallback rate version of RTS PLCP header */ 7089 brcms_c_compute_plcp(wlc, rts_rspec[1], rts_phylen, 7090 rts_plcp_fallback); 7091 memcpy(&txh->RTSPLCPFallback, rts_plcp_fallback, 7092 sizeof(txh->RTSPLCPFallback)); 7093 7094 /* RTS frame fields... */ 7095 rts = (struct ieee80211_rts *)&txh->rts_frame; 7096 7097 durid = brcms_c_compute_rtscts_dur(wlc, use_cts, rts_rspec[0], 7098 rspec[0], rts_preamble_type[0], 7099 preamble_type[0], phylen, false); 7100 rts->duration = cpu_to_le16(durid); 7101 /* fallback rate version of RTS DUR field */ 7102 durid = brcms_c_compute_rtscts_dur(wlc, use_cts, 7103 rts_rspec[1], rspec[1], 7104 rts_preamble_type[1], 7105 preamble_type[1], phylen, false); 7106 txh->RTSDurFallback = cpu_to_le16(durid); 7107 7108 if (use_cts) { 7109 rts->frame_control = cpu_to_le16(IEEE80211_FTYPE_CTL | 7110 IEEE80211_STYPE_CTS); 7111 7112 memcpy(&rts->ra, &h->addr2, ETH_ALEN); 7113 } else { 7114 rts->frame_control = cpu_to_le16(IEEE80211_FTYPE_CTL | 7115 IEEE80211_STYPE_RTS); 7116 7117 memcpy(&rts->ra, &h->addr1, 2 * ETH_ALEN); 7118 } 7119 7120 /* mainrate 7121 * low 8 bits: main frag rate/mcs, 7122 * high 8 bits: rts/cts rate/mcs 7123 */ 7124 mainrates |= (is_ofdm_rate(rts_rspec[0]) ? 7125 D11A_PHY_HDR_GRATE( 7126 (struct ofdm_phy_hdr *) rts_plcp) : 7127 rts_plcp[0]) << 8; 7128 } else { 7129 memset((char *)txh->RTSPhyHeader, 0, D11_PHY_HDR_LEN); 7130 memset((char *)&txh->rts_frame, 0, 7131 sizeof(struct ieee80211_rts)); 7132 memset((char *)txh->RTSPLCPFallback, 0, 7133 sizeof(txh->RTSPLCPFallback)); 7134 txh->RTSDurFallback = 0; 7135 } 7136 7137#ifdef SUPPORT_40MHZ 7138 /* add null delimiter count */ 7139 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && is_mcs_rate(rspec)) 7140 txh->RTSPLCPFallback[AMPDU_FBR_NULL_DELIM] = 7141 brcm_c_ampdu_null_delim_cnt(wlc->ampdu, scb, rspec, phylen); 7142 7143#endif 7144 7145 /* 7146 * Now that RTS/RTS FB preamble types are updated, write 7147 * the final value 7148 */ 7149 txh->MacTxControlHigh = cpu_to_le16(mch); 7150 7151 /* 7152 * MainRates (both the rts and frag plcp rates have 7153 * been calculated now) 7154 */ 7155 txh->MainRates = cpu_to_le16(mainrates); 7156 7157 /* XtraFrameTypes */ 7158 xfts = frametype(rspec[1], wlc->mimoft); 7159 xfts |= (frametype(rts_rspec[0], wlc->mimoft) << XFTS_RTS_FT_SHIFT); 7160 xfts |= (frametype(rts_rspec[1], wlc->mimoft) << XFTS_FBRRTS_FT_SHIFT); 7161 xfts |= CHSPEC_CHANNEL(wlc_phy_chanspec_get(wlc->band->pi)) << 7162 XFTS_CHANNEL_SHIFT; 7163 txh->XtraFrameTypes = cpu_to_le16(xfts); 7164 7165 /* PhyTxControlWord */ 7166 phyctl = frametype(rspec[0], wlc->mimoft); 7167 if ((preamble_type[0] == BRCMS_SHORT_PREAMBLE) || 7168 (preamble_type[0] == BRCMS_GF_PREAMBLE)) { 7169 if (rspec2rate(rspec[0]) != BRCM_RATE_1M) 7170 phyctl |= PHY_TXC_SHORT_HDR; 7171 } 7172 7173 /* phytxant is properly bit shifted */ 7174 phyctl |= brcms_c_stf_d11hdrs_phyctl_txant(wlc, rspec[0]); 7175 txh->PhyTxControlWord = cpu_to_le16(phyctl); 7176 7177 /* PhyTxControlWord_1 */ 7178 if (BRCMS_PHY_11N_CAP(wlc->band)) { 7179 u16 phyctl1 = 0; 7180 7181 phyctl1 = brcms_c_phytxctl1_calc(wlc, rspec[0]); 7182 txh->PhyTxControlWord_1 = cpu_to_le16(phyctl1); 7183 phyctl1 = brcms_c_phytxctl1_calc(wlc, rspec[1]); 7184 txh->PhyTxControlWord_1_Fbr = cpu_to_le16(phyctl1); 7185 7186 if (use_rts || use_cts) { 7187 phyctl1 = brcms_c_phytxctl1_calc(wlc, rts_rspec[0]); 7188 txh->PhyTxControlWord_1_Rts = cpu_to_le16(phyctl1); 7189 phyctl1 = brcms_c_phytxctl1_calc(wlc, rts_rspec[1]); 7190 txh->PhyTxControlWord_1_FbrRts = cpu_to_le16(phyctl1); 7191 } 7192 7193 /* 7194 * For mcs frames, if mixedmode(overloaded with long preamble) 7195 * is going to be set, fill in non-zero MModeLen and/or 7196 * MModeFbrLen it will be unnecessary if they are separated 7197 */ 7198 if (is_mcs_rate(rspec[0]) && 7199 (preamble_type[0] == BRCMS_MM_PREAMBLE)) { 7200 u16 mmodelen = 7201 brcms_c_calc_lsig_len(wlc, rspec[0], phylen); 7202 txh->MModeLen = cpu_to_le16(mmodelen); 7203 } 7204 7205 if (is_mcs_rate(rspec[1]) && 7206 (preamble_type[1] == BRCMS_MM_PREAMBLE)) { 7207 u16 mmodefbrlen = 7208 brcms_c_calc_lsig_len(wlc, rspec[1], phylen); 7209 txh->MModeFbrLen = cpu_to_le16(mmodefbrlen); 7210 } 7211 } 7212 7213 ac = skb_get_queue_mapping(p); 7214 if ((scb->flags & SCB_WMECAP) && qos && wlc->edcf_txop[ac]) { 7215 uint frag_dur, dur, dur_fallback; 7216 7217 /* WME: Update TXOP threshold */ 7218 if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU) && frag == 0) { 7219 frag_dur = 7220 brcms_c_calc_frame_time(wlc, rspec[0], 7221 preamble_type[0], phylen); 7222 7223 if (rts) { 7224 /* 1 RTS or CTS-to-self frame */ 7225 dur = 7226 brcms_c_calc_cts_time(wlc, rts_rspec[0], 7227 rts_preamble_type[0]); 7228 dur_fallback = 7229 brcms_c_calc_cts_time(wlc, rts_rspec[1], 7230 rts_preamble_type[1]); 7231 /* (SIFS + CTS) + SIFS + frame + SIFS + ACK */ 7232 dur += le16_to_cpu(rts->duration); 7233 dur_fallback += 7234 le16_to_cpu(txh->RTSDurFallback); 7235 } else if (use_rifs) { 7236 dur = frag_dur; 7237 dur_fallback = 0; 7238 } else { 7239 /* frame + SIFS + ACK */ 7240 dur = frag_dur; 7241 dur += 7242 brcms_c_compute_frame_dur(wlc, rspec[0], 7243 preamble_type[0], 0); 7244 7245 dur_fallback = 7246 brcms_c_calc_frame_time(wlc, rspec[1], 7247 preamble_type[1], 7248 phylen); 7249 dur_fallback += 7250 brcms_c_compute_frame_dur(wlc, rspec[1], 7251 preamble_type[1], 0); 7252 } 7253 /* NEED to set TxFesTimeNormal (hard) */ 7254 txh->TxFesTimeNormal = cpu_to_le16((u16) dur); 7255 /* 7256 * NEED to set fallback rate version of 7257 * TxFesTimeNormal (hard) 7258 */ 7259 txh->TxFesTimeFallback = 7260 cpu_to_le16((u16) dur_fallback); 7261 7262 /* 7263 * update txop byte threshold (txop minus intraframe 7264 * overhead) 7265 */ 7266 if (wlc->edcf_txop[ac] >= (dur - frag_dur)) { 7267 uint newfragthresh; 7268 7269 newfragthresh = 7270 brcms_c_calc_frame_len(wlc, 7271 rspec[0], preamble_type[0], 7272 (wlc->edcf_txop[ac] - 7273 (dur - frag_dur))); 7274 /* range bound the fragthreshold */ 7275 if (newfragthresh < DOT11_MIN_FRAG_LEN) 7276 newfragthresh = 7277 DOT11_MIN_FRAG_LEN; 7278 else if (newfragthresh > 7279 wlc->usr_fragthresh) 7280 newfragthresh = 7281 wlc->usr_fragthresh; 7282 /* update the fragthresh and do txc update */ 7283 if (wlc->fragthresh[queue] != 7284 (u16) newfragthresh) 7285 wlc->fragthresh[queue] = 7286 (u16) newfragthresh; 7287 } else { 7288 wiphy_err(wlc->wiphy, "wl%d: %s txop invalid " 7289 "for rate %d\n", 7290 wlc->pub->unit, fifo_names[queue], 7291 rspec2rate(rspec[0])); 7292 } 7293 7294 if (dur > wlc->edcf_txop[ac]) 7295 wiphy_err(wlc->wiphy, "wl%d: %s: %s txop " 7296 "exceeded phylen %d/%d dur %d/%d\n", 7297 wlc->pub->unit, __func__, 7298 fifo_names[queue], 7299 phylen, wlc->fragthresh[queue], 7300 dur, wlc->edcf_txop[ac]); 7301 } 7302 } 7303 7304 return 0; 7305} 7306 7307void brcms_c_sendpkt_mac80211(struct brcms_c_info *wlc, struct sk_buff *sdu, 7308 struct ieee80211_hw *hw) 7309{ 7310 u8 prio; 7311 uint fifo; 7312 struct scb *scb = &wlc->pri_scb; 7313 struct ieee80211_hdr *d11_header = (struct ieee80211_hdr *)(sdu->data); 7314 7315 /* 7316 * 802.11 standard requires management traffic 7317 * to go at highest priority 7318 */ 7319 prio = ieee80211_is_data(d11_header->frame_control) ? sdu->priority : 7320 MAXPRIO; 7321 fifo = prio2fifo[prio]; 7322 if (brcms_c_d11hdrs_mac80211(wlc, hw, sdu, scb, 0, 1, fifo, 0)) 7323 return; 7324 brcms_c_txq_enq(wlc, scb, sdu, BRCMS_PRIO_TO_PREC(prio)); 7325 brcms_c_send_q(wlc); 7326} 7327 7328void brcms_c_send_q(struct brcms_c_info *wlc) 7329{ 7330 struct sk_buff *pkt[DOT11_MAXNUMFRAGS]; 7331 int prec; 7332 u16 prec_map; 7333 int err = 0, i, count; 7334 uint fifo; 7335 struct brcms_txq_info *qi = wlc->pkt_queue; 7336 struct pktq *q = &qi->q; 7337 struct ieee80211_tx_info *tx_info; 7338 7339 prec_map = wlc->tx_prec_map; 7340 7341 /* Send all the enq'd pkts that we can. 7342 * Dequeue packets with precedence with empty HW fifo only 7343 */ 7344 while (prec_map && (pkt[0] = brcmu_pktq_mdeq(q, prec_map, &prec))) { 7345 tx_info = IEEE80211_SKB_CB(pkt[0]); 7346 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) { 7347 err = brcms_c_sendampdu(wlc->ampdu, qi, pkt, prec); 7348 } else { 7349 count = 1; 7350 err = brcms_c_prep_pdu(wlc, pkt[0], &fifo); 7351 if (!err) { 7352 for (i = 0; i < count; i++) 7353 brcms_c_txfifo(wlc, fifo, pkt[i], true, 7354 1); 7355 } 7356 } 7357 7358 if (err == -EBUSY) { 7359 brcmu_pktq_penq_head(q, prec, pkt[0]); 7360 /* 7361 * If send failed due to any other reason than a 7362 * change in HW FIFO condition, quit. Otherwise, 7363 * read the new prec_map! 7364 */ 7365 if (prec_map == wlc->tx_prec_map) 7366 break; 7367 prec_map = wlc->tx_prec_map; 7368 } 7369 } 7370} 7371 7372void 7373brcms_c_txfifo(struct brcms_c_info *wlc, uint fifo, struct sk_buff *p, 7374 bool commit, s8 txpktpend) 7375{ 7376 u16 frameid = INVALIDFID; 7377 struct d11txh *txh; 7378 7379 txh = (struct d11txh *) (p->data); 7380 7381 /* When a BC/MC frame is being committed to the BCMC fifo 7382 * via DMA (NOT PIO), update ucode or BSS info as appropriate. 7383 */ 7384 if (fifo == TX_BCMC_FIFO) 7385 frameid = le16_to_cpu(txh->TxFrameID); 7386 7387 /* 7388 * Bump up pending count for if not using rpc. If rpc is 7389 * used, this will be handled in brcms_b_txfifo() 7390 */ 7391 if (commit) { 7392 wlc->core->txpktpend[fifo] += txpktpend; 7393 BCMMSG(wlc->wiphy, "pktpend inc %d to %d\n", 7394 txpktpend, wlc->core->txpktpend[fifo]); 7395 } 7396 7397 /* Commit BCMC sequence number in the SHM frame ID location */ 7398 if (frameid != INVALIDFID) { 7399 /* 7400 * To inform the ucode of the last mcast frame posted 7401 * so that it can clear moredata bit 7402 */ 7403 brcms_b_write_shm(wlc->hw, M_BCMC_FID, frameid); 7404 } 7405 7406 if (dma_txfast(wlc->hw->di[fifo], p, commit) < 0) 7407 wiphy_err(wlc->wiphy, "txfifo: fatal, toss frames !!!\n"); 7408} 7409 7410u32 7411brcms_c_rspec_to_rts_rspec(struct brcms_c_info *wlc, u32 rspec, 7412 bool use_rspec, u16 mimo_ctlchbw) 7413{ 7414 u32 rts_rspec = 0; 7415 7416 if (use_rspec) 7417 /* use frame rate as rts rate */ 7418 rts_rspec = rspec; 7419 else if (wlc->band->gmode && wlc->protection->_g && !is_cck_rate(rspec)) 7420 /* Use 11Mbps as the g protection RTS target rate and fallback. 7421 * Use the brcms_basic_rate() lookup to find the best basic rate 7422 * under the target in case 11 Mbps is not Basic. 7423 * 6 and 9 Mbps are not usually selected by rate selection, but 7424 * even if the OFDM rate we are protecting is 6 or 9 Mbps, 11 7425 * is more robust. 7426 */ 7427 rts_rspec = brcms_basic_rate(wlc, BRCM_RATE_11M); 7428 else 7429 /* calculate RTS rate and fallback rate based on the frame rate 7430 * RTS must be sent at a basic rate since it is a 7431 * control frame, sec 9.6 of 802.11 spec 7432 */ 7433 rts_rspec = brcms_basic_rate(wlc, rspec); 7434 7435 if (BRCMS_PHY_11N_CAP(wlc->band)) { 7436 /* set rts txbw to correct side band */ 7437 rts_rspec &= ~RSPEC_BW_MASK; 7438 7439 /* 7440 * if rspec/rspec_fallback is 40MHz, then send RTS on both 7441 * 20MHz channel (DUP), otherwise send RTS on control channel 7442 */ 7443 if (rspec_is40mhz(rspec) && !is_cck_rate(rts_rspec)) 7444 rts_rspec |= (PHY_TXC1_BW_40MHZ_DUP << RSPEC_BW_SHIFT); 7445 else 7446 rts_rspec |= (mimo_ctlchbw << RSPEC_BW_SHIFT); 7447 7448 /* pick siso/cdd as default for ofdm */ 7449 if (is_ofdm_rate(rts_rspec)) { 7450 rts_rspec &= ~RSPEC_STF_MASK; 7451 rts_rspec |= (wlc->stf->ss_opmode << RSPEC_STF_SHIFT); 7452 } 7453 } 7454 return rts_rspec; 7455} 7456 7457void 7458brcms_c_txfifo_complete(struct brcms_c_info *wlc, uint fifo, s8 txpktpend) 7459{ 7460 wlc->core->txpktpend[fifo] -= txpktpend; 7461 BCMMSG(wlc->wiphy, "pktpend dec %d to %d\n", txpktpend, 7462 wlc->core->txpktpend[fifo]); 7463 7464 /* There is more room; mark precedences related to this FIFO sendable */ 7465 wlc->tx_prec_map |= wlc->fifo2prec_map[fifo]; 7466 7467 /* figure out which bsscfg is being worked on... */ 7468} 7469 7470/* Update beacon listen interval in shared memory */ 7471static void brcms_c_bcn_li_upd(struct brcms_c_info *wlc) 7472{ 7473 /* wake up every DTIM is the default */ 7474 if (wlc->bcn_li_dtim == 1) 7475 brcms_b_write_shm(wlc->hw, M_BCN_LI, 0); 7476 else 7477 brcms_b_write_shm(wlc->hw, M_BCN_LI, 7478 (wlc->bcn_li_dtim << 8) | wlc->bcn_li_bcn); 7479} 7480 7481static void 7482brcms_b_read_tsf(struct brcms_hardware *wlc_hw, u32 *tsf_l_ptr, 7483 u32 *tsf_h_ptr) 7484{ 7485 struct d11regs __iomem *regs = wlc_hw->regs; 7486 7487 /* read the tsf timer low, then high to get an atomic read */ 7488 *tsf_l_ptr = R_REG(®s->tsf_timerlow); 7489 *tsf_h_ptr = R_REG(®s->tsf_timerhigh); 7490} 7491 7492/* 7493 * recover 64bit TSF value from the 16bit TSF value in the rx header 7494 * given the assumption that the TSF passed in header is within 65ms 7495 * of the current tsf. 7496 * 7497 * 6 5 4 4 3 2 1 7498 * 3.......6.......8.......0.......2.......4.......6.......8......0 7499 * |<---------- tsf_h ----------->||<--- tsf_l -->||<-RxTSFTime ->| 7500 * 7501 * The RxTSFTime are the lowest 16 bits and provided by the ucode. The 7502 * tsf_l is filled in by brcms_b_recv, which is done earlier in the 7503 * receive call sequence after rx interrupt. Only the higher 16 bits 7504 * are used. Finally, the tsf_h is read from the tsf register. 7505 */ 7506static u64 brcms_c_recover_tsf64(struct brcms_c_info *wlc, 7507 struct d11rxhdr *rxh) 7508{ 7509 u32 tsf_h, tsf_l; 7510 u16 rx_tsf_0_15, rx_tsf_16_31; 7511 7512 brcms_b_read_tsf(wlc->hw, &tsf_l, &tsf_h); 7513 7514 rx_tsf_16_31 = (u16)(tsf_l >> 16); 7515 rx_tsf_0_15 = rxh->RxTSFTime; 7516 7517 /* 7518 * a greater tsf time indicates the low 16 bits of 7519 * tsf_l wrapped, so decrement the high 16 bits. 7520 */ 7521 if ((u16)tsf_l < rx_tsf_0_15) { 7522 rx_tsf_16_31 -= 1; 7523 if (rx_tsf_16_31 == 0xffff) 7524 tsf_h -= 1; 7525 } 7526 7527 return ((u64)tsf_h << 32) | (((u32)rx_tsf_16_31 << 16) + rx_tsf_0_15); 7528} 7529 7530static void 7531prep_mac80211_status(struct brcms_c_info *wlc, struct d11rxhdr *rxh, 7532 struct sk_buff *p, 7533 struct ieee80211_rx_status *rx_status) 7534{ 7535 int preamble; 7536 int channel; 7537 u32 rspec; 7538 unsigned char *plcp; 7539 7540 /* fill in TSF and flag its presence */ 7541 rx_status->mactime = brcms_c_recover_tsf64(wlc, rxh); 7542 rx_status->flag |= RX_FLAG_MACTIME_MPDU; 7543 7544 channel = BRCMS_CHAN_CHANNEL(rxh->RxChan); 7545 7546 if (channel > 14) { 7547 rx_status->band = IEEE80211_BAND_5GHZ; 7548 rx_status->freq = ieee80211_ofdm_chan_to_freq( 7549 WF_CHAN_FACTOR_5_G/2, channel); 7550 7551 } else { 7552 rx_status->band = IEEE80211_BAND_2GHZ; 7553 rx_status->freq = ieee80211_dsss_chan_to_freq(channel); 7554 } 7555 7556 rx_status->signal = wlc_phy_rssi_compute(wlc->hw->band->pi, rxh); 7557 7558 /* noise */ 7559 /* qual */ 7560 rx_status->antenna = 7561 (rxh->PhyRxStatus_0 & PRXS0_RXANT_UPSUBBAND) ? 1 : 0; 7562 7563 plcp = p->data; 7564 7565 rspec = brcms_c_compute_rspec(rxh, plcp); 7566 if (is_mcs_rate(rspec)) { 7567 rx_status->rate_idx = rspec & RSPEC_RATE_MASK; 7568 rx_status->flag |= RX_FLAG_HT; 7569 if (rspec_is40mhz(rspec)) 7570 rx_status->flag |= RX_FLAG_40MHZ; 7571 } else { 7572 switch (rspec2rate(rspec)) { 7573 case BRCM_RATE_1M: 7574 rx_status->rate_idx = 0; 7575 break; 7576 case BRCM_RATE_2M: 7577 rx_status->rate_idx = 1; 7578 break; 7579 case BRCM_RATE_5M5: 7580 rx_status->rate_idx = 2; 7581 break; 7582 case BRCM_RATE_11M: 7583 rx_status->rate_idx = 3; 7584 break; 7585 case BRCM_RATE_6M: 7586 rx_status->rate_idx = 4; 7587 break; 7588 case BRCM_RATE_9M: 7589 rx_status->rate_idx = 5; 7590 break; 7591 case BRCM_RATE_12M: 7592 rx_status->rate_idx = 6; 7593 break; 7594 case BRCM_RATE_18M: 7595 rx_status->rate_idx = 7; 7596 break; 7597 case BRCM_RATE_24M: 7598 rx_status->rate_idx = 8; 7599 break; 7600 case BRCM_RATE_36M: 7601 rx_status->rate_idx = 9; 7602 break; 7603 case BRCM_RATE_48M: 7604 rx_status->rate_idx = 10; 7605 break; 7606 case BRCM_RATE_54M: 7607 rx_status->rate_idx = 11; 7608 break; 7609 default: 7610 wiphy_err(wlc->wiphy, "%s: Unknown rate\n", __func__); 7611 } 7612 7613 /* 7614 * For 5GHz, we should decrease the index as it is 7615 * a subset of the 2.4G rates. See bitrates field 7616 * of brcms_band_5GHz_nphy (in mac80211_if.c). 7617 */ 7618 if (rx_status->band == IEEE80211_BAND_5GHZ) 7619 rx_status->rate_idx -= BRCMS_LEGACY_5G_RATE_OFFSET; 7620 7621 /* Determine short preamble and rate_idx */ 7622 preamble = 0; 7623 if (is_cck_rate(rspec)) { 7624 if (rxh->PhyRxStatus_0 & PRXS0_SHORTH) 7625 rx_status->flag |= RX_FLAG_SHORTPRE; 7626 } else if (is_ofdm_rate(rspec)) { 7627 rx_status->flag |= RX_FLAG_SHORTPRE; 7628 } else { 7629 wiphy_err(wlc->wiphy, "%s: Unknown modulation\n", 7630 __func__); 7631 } 7632 } 7633 7634 if (plcp3_issgi(plcp[3])) 7635 rx_status->flag |= RX_FLAG_SHORT_GI; 7636 7637 if (rxh->RxStatus1 & RXS_DECERR) { 7638 rx_status->flag |= RX_FLAG_FAILED_PLCP_CRC; 7639 wiphy_err(wlc->wiphy, "%s: RX_FLAG_FAILED_PLCP_CRC\n", 7640 __func__); 7641 } 7642 if (rxh->RxStatus1 & RXS_FCSERR) { 7643 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; 7644 wiphy_err(wlc->wiphy, "%s: RX_FLAG_FAILED_FCS_CRC\n", 7645 __func__); 7646 } 7647} 7648 7649static void 7650brcms_c_recvctl(struct brcms_c_info *wlc, struct d11rxhdr *rxh, 7651 struct sk_buff *p) 7652{ 7653 int len_mpdu; 7654 struct ieee80211_rx_status rx_status; 7655 7656 memset(&rx_status, 0, sizeof(rx_status)); 7657 prep_mac80211_status(wlc, rxh, p, &rx_status); 7658 7659 /* mac header+body length, exclude CRC and plcp header */ 7660 len_mpdu = p->len - D11_PHY_HDR_LEN - FCS_LEN; 7661 skb_pull(p, D11_PHY_HDR_LEN); 7662 __skb_trim(p, len_mpdu); 7663 7664 memcpy(IEEE80211_SKB_RXCB(p), &rx_status, sizeof(rx_status)); 7665 ieee80211_rx_irqsafe(wlc->pub->ieee_hw, p); 7666} 7667 7668/* calculate frame duration for Mixed-mode L-SIG spoofing, return 7669 * number of bytes goes in the length field 7670 * 7671 * Formula given by HT PHY Spec v 1.13 7672 * len = 3(nsyms + nstream + 3) - 3 7673 */ 7674u16 7675brcms_c_calc_lsig_len(struct brcms_c_info *wlc, u32 ratespec, 7676 uint mac_len) 7677{ 7678 uint nsyms, len = 0, kNdps; 7679 7680 BCMMSG(wlc->wiphy, "wl%d: rate %d, len%d\n", 7681 wlc->pub->unit, rspec2rate(ratespec), mac_len); 7682 7683 if (is_mcs_rate(ratespec)) { 7684 uint mcs = ratespec & RSPEC_RATE_MASK; 7685 int tot_streams = (mcs_2_txstreams(mcs) + 1) + 7686 rspec_stc(ratespec); 7687 7688 /* 7689 * the payload duration calculation matches that 7690 * of regular ofdm 7691 */ 7692 /* 1000Ndbps = kbps * 4 */ 7693 kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec), 7694 rspec_issgi(ratespec)) * 4; 7695 7696 if (rspec_stc(ratespec) == 0) 7697 nsyms = 7698 CEIL((APHY_SERVICE_NBITS + 8 * mac_len + 7699 APHY_TAIL_NBITS) * 1000, kNdps); 7700 else 7701 /* STBC needs to have even number of symbols */ 7702 nsyms = 7703 2 * 7704 CEIL((APHY_SERVICE_NBITS + 8 * mac_len + 7705 APHY_TAIL_NBITS) * 1000, 2 * kNdps); 7706 7707 /* (+3) account for HT-SIG(2) and HT-STF(1) */ 7708 nsyms += (tot_streams + 3); 7709 /* 7710 * 3 bytes/symbol @ legacy 6Mbps rate 7711 * (-3) excluding service bits and tail bits 7712 */ 7713 len = (3 * nsyms) - 3; 7714 } 7715 7716 return (u16) len; 7717} 7718 7719static void 7720brcms_c_mod_prb_rsp_rate_table(struct brcms_c_info *wlc, uint frame_len) 7721{ 7722 const struct brcms_c_rateset *rs_dflt; 7723 struct brcms_c_rateset rs; 7724 u8 rate; 7725 u16 entry_ptr; 7726 u8 plcp[D11_PHY_HDR_LEN]; 7727 u16 dur, sifs; 7728 uint i; 7729 7730 sifs = get_sifs(wlc->band); 7731 7732 rs_dflt = brcms_c_rateset_get_hwrs(wlc); 7733 7734 brcms_c_rateset_copy(rs_dflt, &rs); 7735 brcms_c_rateset_mcs_upd(&rs, wlc->stf->txstreams); 7736 7737 /* 7738 * walk the phy rate table and update MAC core SHM 7739 * basic rate table entries 7740 */ 7741 for (i = 0; i < rs.count; i++) { 7742 rate = rs.rates[i] & BRCMS_RATE_MASK; 7743 7744 entry_ptr = brcms_b_rate_shm_offset(wlc->hw, rate); 7745 7746 /* Calculate the Probe Response PLCP for the given rate */ 7747 brcms_c_compute_plcp(wlc, rate, frame_len, plcp); 7748 7749 /* 7750 * Calculate the duration of the Probe Response 7751 * frame plus SIFS for the MAC 7752 */ 7753 dur = (u16) brcms_c_calc_frame_time(wlc, rate, 7754 BRCMS_LONG_PREAMBLE, frame_len); 7755 dur += sifs; 7756 7757 /* Update the SHM Rate Table entry Probe Response values */ 7758 brcms_b_write_shm(wlc->hw, entry_ptr + M_RT_PRS_PLCP_POS, 7759 (u16) (plcp[0] + (plcp[1] << 8))); 7760 brcms_b_write_shm(wlc->hw, entry_ptr + M_RT_PRS_PLCP_POS + 2, 7761 (u16) (plcp[2] + (plcp[3] << 8))); 7762 brcms_b_write_shm(wlc->hw, entry_ptr + M_RT_PRS_DUR_POS, dur); 7763 } 7764} 7765 7766/* Max buffering needed for beacon template/prb resp template is 142 bytes. 7767 * 7768 * PLCP header is 6 bytes. 7769 * 802.11 A3 header is 24 bytes. 7770 * Max beacon frame body template length is 112 bytes. 7771 * Max probe resp frame body template length is 110 bytes. 7772 * 7773 * *len on input contains the max length of the packet available. 7774 * 7775 * The *len value is set to the number of bytes in buf used, and starts 7776 * with the PLCP and included up to, but not including, the 4 byte FCS. 7777 */ 7778static void 7779brcms_c_bcn_prb_template(struct brcms_c_info *wlc, u16 type, 7780 u32 bcn_rspec, 7781 struct brcms_bss_cfg *cfg, u16 *buf, int *len) 7782{ 7783 static const u8 ether_bcast[ETH_ALEN] = {255, 255, 255, 255, 255, 255}; 7784 struct cck_phy_hdr *plcp; 7785 struct ieee80211_mgmt *h; 7786 int hdr_len, body_len; 7787 7788 hdr_len = D11_PHY_HDR_LEN + DOT11_MAC_HDR_LEN; 7789 7790 /* calc buffer size provided for frame body */ 7791 body_len = *len - hdr_len; 7792 /* return actual size */ 7793 *len = hdr_len + body_len; 7794 7795 /* format PHY and MAC headers */ 7796 memset((char *)buf, 0, hdr_len); 7797 7798 plcp = (struct cck_phy_hdr *) buf; 7799 7800 /* 7801 * PLCP for Probe Response frames are filled in from 7802 * core's rate table 7803 */ 7804 if (type == IEEE80211_STYPE_BEACON) 7805 /* fill in PLCP */ 7806 brcms_c_compute_plcp(wlc, bcn_rspec, 7807 (DOT11_MAC_HDR_LEN + body_len + FCS_LEN), 7808 (u8 *) plcp); 7809 7810 /* "Regular" and 16 MBSS but not for 4 MBSS */ 7811 /* Update the phytxctl for the beacon based on the rspec */ 7812 brcms_c_beacon_phytxctl_txant_upd(wlc, bcn_rspec); 7813 7814 h = (struct ieee80211_mgmt *)&plcp[1]; 7815 7816 /* fill in 802.11 header */ 7817 h->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT | type); 7818 7819 /* DUR is 0 for multicast bcn, or filled in by MAC for prb resp */ 7820 /* A1 filled in by MAC for prb resp, broadcast for bcn */ 7821 if (type == IEEE80211_STYPE_BEACON) 7822 memcpy(&h->da, ðer_bcast, ETH_ALEN); 7823 memcpy(&h->sa, &cfg->cur_etheraddr, ETH_ALEN); 7824 memcpy(&h->bssid, &cfg->BSSID, ETH_ALEN); 7825 7826 /* SEQ filled in by MAC */ 7827} 7828 7829int brcms_c_get_header_len(void) 7830{ 7831 return TXOFF; 7832} 7833 7834/* 7835 * Update all beacons for the system. 7836 */ 7837void brcms_c_update_beacon(struct brcms_c_info *wlc) 7838{ 7839 struct brcms_bss_cfg *bsscfg = wlc->bsscfg; 7840 7841 if (bsscfg->up && !bsscfg->BSS) 7842 /* Clear the soft intmask */ 7843 wlc->defmacintmask &= ~MI_BCNTPL; 7844} 7845 7846/* Write ssid into shared memory */ 7847static void 7848brcms_c_shm_ssid_upd(struct brcms_c_info *wlc, struct brcms_bss_cfg *cfg) 7849{ 7850 u8 *ssidptr = cfg->SSID; 7851 u16 base = M_SSID; 7852 u8 ssidbuf[IEEE80211_MAX_SSID_LEN]; 7853 7854 /* padding the ssid with zero and copy it into shm */ 7855 memset(ssidbuf, 0, IEEE80211_MAX_SSID_LEN); 7856 memcpy(ssidbuf, ssidptr, cfg->SSID_len); 7857 7858 brcms_c_copyto_shm(wlc, base, ssidbuf, IEEE80211_MAX_SSID_LEN); 7859 brcms_b_write_shm(wlc->hw, M_SSIDLEN, (u16) cfg->SSID_len); 7860} 7861 7862static void 7863brcms_c_bss_update_probe_resp(struct brcms_c_info *wlc, 7864 struct brcms_bss_cfg *cfg, 7865 bool suspend) 7866{ 7867 u16 prb_resp[BCN_TMPL_LEN / 2]; 7868 int len = BCN_TMPL_LEN; 7869 7870 /* 7871 * write the probe response to hardware, or save in 7872 * the config structure 7873 */ 7874 7875 /* create the probe response template */ 7876 brcms_c_bcn_prb_template(wlc, IEEE80211_STYPE_PROBE_RESP, 0, 7877 cfg, prb_resp, &len); 7878 7879 if (suspend) 7880 brcms_c_suspend_mac_and_wait(wlc); 7881 7882 /* write the probe response into the template region */ 7883 brcms_b_write_template_ram(wlc->hw, T_PRS_TPL_BASE, 7884 (len + 3) & ~3, prb_resp); 7885 7886 /* write the length of the probe response frame (+PLCP/-FCS) */ 7887 brcms_b_write_shm(wlc->hw, M_PRB_RESP_FRM_LEN, (u16) len); 7888 7889 /* write the SSID and SSID length */ 7890 brcms_c_shm_ssid_upd(wlc, cfg); 7891 7892 /* 7893 * Write PLCP headers and durations for probe response frames 7894 * at all rates. Use the actual frame length covered by the 7895 * PLCP header for the call to brcms_c_mod_prb_rsp_rate_table() 7896 * by subtracting the PLCP len and adding the FCS. 7897 */ 7898 len += (-D11_PHY_HDR_LEN + FCS_LEN); 7899 brcms_c_mod_prb_rsp_rate_table(wlc, (u16) len); 7900 7901 if (suspend) 7902 brcms_c_enable_mac(wlc); 7903} 7904 7905void brcms_c_update_probe_resp(struct brcms_c_info *wlc, bool suspend) 7906{ 7907 struct brcms_bss_cfg *bsscfg = wlc->bsscfg; 7908 7909 /* update AP or IBSS probe responses */ 7910 if (bsscfg->up && !bsscfg->BSS) 7911 brcms_c_bss_update_probe_resp(wlc, bsscfg, suspend); 7912} 7913 7914/* prepares pdu for transmission. returns BCM error codes */ 7915int brcms_c_prep_pdu(struct brcms_c_info *wlc, struct sk_buff *pdu, uint *fifop) 7916{ 7917 uint fifo; 7918 struct d11txh *txh; 7919 struct ieee80211_hdr *h; 7920 struct scb *scb; 7921 7922 txh = (struct d11txh *) (pdu->data); 7923 h = (struct ieee80211_hdr *)((u8 *) (txh + 1) + D11_PHY_HDR_LEN); 7924 7925 /* get the pkt queue info. This was put at brcms_c_sendctl or 7926 * brcms_c_send for PDU */ 7927 fifo = le16_to_cpu(txh->TxFrameID) & TXFID_QUEUE_MASK; 7928 7929 scb = NULL; 7930 7931 *fifop = fifo; 7932 7933 /* return if insufficient dma resources */ 7934 if (*wlc->core->txavail[fifo] < MAX_DMA_SEGS) { 7935 /* Mark precedences related to this FIFO, unsendable */ 7936 /* A fifo is full. Clear precedences related to that FIFO */ 7937 wlc->tx_prec_map &= ~(wlc->fifo2prec_map[fifo]); 7938 return -EBUSY; 7939 } 7940 return 0; 7941} 7942 7943int brcms_b_xmtfifo_sz_get(struct brcms_hardware *wlc_hw, uint fifo, 7944 uint *blocks) 7945{ 7946 if (fifo >= NFIFO) 7947 return -EINVAL; 7948 7949 *blocks = wlc_hw->xmtfifo_sz[fifo]; 7950 7951 return 0; 7952} 7953 7954void 7955brcms_c_set_addrmatch(struct brcms_c_info *wlc, int match_reg_offset, 7956 const u8 *addr) 7957{ 7958 brcms_b_set_addrmatch(wlc->hw, match_reg_offset, addr); 7959 if (match_reg_offset == RCM_BSSID_OFFSET) 7960 memcpy(wlc->bsscfg->BSSID, addr, ETH_ALEN); 7961} 7962 7963/* 7964 * Flag 'scan in progress' to withhold dynamic phy calibration 7965 */ 7966void brcms_c_scan_start(struct brcms_c_info *wlc) 7967{ 7968 wlc_phy_hold_upd(wlc->band->pi, PHY_HOLD_FOR_SCAN, true); 7969} 7970 7971void brcms_c_scan_stop(struct brcms_c_info *wlc) 7972{ 7973 wlc_phy_hold_upd(wlc->band->pi, PHY_HOLD_FOR_SCAN, false); 7974} 7975 7976void brcms_c_associate_upd(struct brcms_c_info *wlc, bool state) 7977{ 7978 wlc->pub->associated = state; 7979 wlc->bsscfg->associated = state; 7980} 7981 7982/* 7983 * When a remote STA/AP is removed by Mac80211, or when it can no longer accept 7984 * AMPDU traffic, packets pending in hardware have to be invalidated so that 7985 * when later on hardware releases them, they can be handled appropriately. 7986 */ 7987void brcms_c_inval_dma_pkts(struct brcms_hardware *hw, 7988 struct ieee80211_sta *sta, 7989 void (*dma_callback_fn)) 7990{ 7991 struct dma_pub *dmah; 7992 int i; 7993 for (i = 0; i < NFIFO; i++) { 7994 dmah = hw->di[i]; 7995 if (dmah != NULL) 7996 dma_walk_packets(dmah, dma_callback_fn, sta); 7997 } 7998} 7999 8000int brcms_c_get_curband(struct brcms_c_info *wlc) 8001{ 8002 return wlc->band->bandunit; 8003} 8004 8005void brcms_c_wait_for_tx_completion(struct brcms_c_info *wlc, bool drop) 8006{ 8007 /* flush packet queue when requested */ 8008 if (drop) 8009 brcmu_pktq_flush(&wlc->pkt_queue->q, false, NULL, NULL); 8010 8011 /* wait for queue and DMA fifos to run dry */ 8012 while (!pktq_empty(&wlc->pkt_queue->q) || brcms_txpktpendtot(wlc) > 0) 8013 brcms_msleep(wlc->wl, 1); 8014} 8015 8016void brcms_c_set_beacon_listen_interval(struct brcms_c_info *wlc, u8 interval) 8017{ 8018 wlc->bcn_li_bcn = interval; 8019 if (wlc->pub->up) 8020 brcms_c_bcn_li_upd(wlc); 8021} 8022 8023int brcms_c_set_tx_power(struct brcms_c_info *wlc, int txpwr) 8024{ 8025 uint qdbm; 8026 8027 /* Remove override bit and clip to max qdbm value */ 8028 qdbm = min_t(uint, txpwr * BRCMS_TXPWR_DB_FACTOR, 0xff); 8029 return wlc_phy_txpower_set(wlc->band->pi, qdbm, false); 8030} 8031 8032int brcms_c_get_tx_power(struct brcms_c_info *wlc) 8033{ 8034 uint qdbm; 8035 bool override; 8036 8037 wlc_phy_txpower_get(wlc->band->pi, &qdbm, &override); 8038 8039 /* Return qdbm units */ 8040 return (int)(qdbm / BRCMS_TXPWR_DB_FACTOR); 8041} 8042 8043/* Process received frames */ 8044/* 8045 * Return true if more frames need to be processed. false otherwise. 8046 * Param 'bound' indicates max. # frames to process before break out. 8047 */ 8048static void brcms_c_recv(struct brcms_c_info *wlc, struct sk_buff *p) 8049{ 8050 struct d11rxhdr *rxh; 8051 struct ieee80211_hdr *h; 8052 uint len; 8053 bool is_amsdu; 8054 8055 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit); 8056 8057 /* frame starts with rxhdr */ 8058 rxh = (struct d11rxhdr *) (p->data); 8059 8060 /* strip off rxhdr */ 8061 skb_pull(p, BRCMS_HWRXOFF); 8062 8063 /* MAC inserts 2 pad bytes for a4 headers or QoS or A-MSDU subframes */ 8064 if (rxh->RxStatus1 & RXS_PBPRES) { 8065 if (p->len < 2) { 8066 wiphy_err(wlc->wiphy, "wl%d: recv: rcvd runt of " 8067 "len %d\n", wlc->pub->unit, p->len); 8068 goto toss; 8069 } 8070 skb_pull(p, 2); 8071 } 8072 8073 h = (struct ieee80211_hdr *)(p->data + D11_PHY_HDR_LEN); 8074 len = p->len; 8075 8076 if (rxh->RxStatus1 & RXS_FCSERR) { 8077 if (wlc->pub->mac80211_state & MAC80211_PROMISC_BCNS) { 8078 wiphy_err(wlc->wiphy, "FCSERR while scanning******* -" 8079 " tossing\n"); 8080 goto toss; 8081 } else { 8082 wiphy_err(wlc->wiphy, "RCSERR!!!\n"); 8083 goto toss; 8084 } 8085 } 8086 8087 /* check received pkt has at least frame control field */ 8088 if (len < D11_PHY_HDR_LEN + sizeof(h->frame_control)) 8089 goto toss; 8090 8091 /* not supporting A-MSDU */ 8092 is_amsdu = rxh->RxStatus2 & RXS_AMSDU_MASK; 8093 if (is_amsdu) 8094 goto toss; 8095 8096 brcms_c_recvctl(wlc, rxh, p); 8097 return; 8098 8099 toss: 8100 brcmu_pkt_buf_free_skb(p); 8101} 8102 8103/* Process received frames */ 8104/* 8105 * Return true if more frames need to be processed. false otherwise. 8106 * Param 'bound' indicates max. # frames to process before break out. 8107 */ 8108static bool 8109brcms_b_recv(struct brcms_hardware *wlc_hw, uint fifo, bool bound) 8110{ 8111 struct sk_buff *p; 8112 struct sk_buff *next = NULL; 8113 struct sk_buff_head recv_frames; 8114 8115 uint n = 0; 8116 uint bound_limit = bound ? RXBND : -1; 8117 8118 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit); 8119 skb_queue_head_init(&recv_frames); 8120 8121 /* gather received frames */ 8122 while (dma_rx(wlc_hw->di[fifo], &recv_frames)) { 8123 8124 /* !give others some time to run! */ 8125 if (++n >= bound_limit) 8126 break; 8127 } 8128 8129 /* post more rbufs */ 8130 dma_rxfill(wlc_hw->di[fifo]); 8131 8132 /* process each frame */ 8133 skb_queue_walk_safe(&recv_frames, p, next) { 8134 struct d11rxhdr_le *rxh_le; 8135 struct d11rxhdr *rxh; 8136 8137 skb_unlink(p, &recv_frames); 8138 rxh_le = (struct d11rxhdr_le *)p->data; 8139 rxh = (struct d11rxhdr *)p->data; 8140 8141 /* fixup rx header endianness */ 8142 rxh->RxFrameSize = le16_to_cpu(rxh_le->RxFrameSize); 8143 rxh->PhyRxStatus_0 = le16_to_cpu(rxh_le->PhyRxStatus_0); 8144 rxh->PhyRxStatus_1 = le16_to_cpu(rxh_le->PhyRxStatus_1); 8145 rxh->PhyRxStatus_2 = le16_to_cpu(rxh_le->PhyRxStatus_2); 8146 rxh->PhyRxStatus_3 = le16_to_cpu(rxh_le->PhyRxStatus_3); 8147 rxh->PhyRxStatus_4 = le16_to_cpu(rxh_le->PhyRxStatus_4); 8148 rxh->PhyRxStatus_5 = le16_to_cpu(rxh_le->PhyRxStatus_5); 8149 rxh->RxStatus1 = le16_to_cpu(rxh_le->RxStatus1); 8150 rxh->RxStatus2 = le16_to_cpu(rxh_le->RxStatus2); 8151 rxh->RxTSFTime = le16_to_cpu(rxh_le->RxTSFTime); 8152 rxh->RxChan = le16_to_cpu(rxh_le->RxChan); 8153 8154 brcms_c_recv(wlc_hw->wlc, p); 8155 } 8156 8157 return n >= bound_limit; 8158} 8159 8160/* second-level interrupt processing 8161 * Return true if another dpc needs to be re-scheduled. false otherwise. 8162 * Param 'bounded' indicates if applicable loops should be bounded. 8163 */ 8164bool brcms_c_dpc(struct brcms_c_info *wlc, bool bounded) 8165{ 8166 u32 macintstatus; 8167 struct brcms_hardware *wlc_hw = wlc->hw; 8168 struct d11regs __iomem *regs = wlc_hw->regs; 8169 struct wiphy *wiphy = wlc->wiphy; 8170 8171 if (brcms_deviceremoved(wlc)) { 8172 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit, 8173 __func__); 8174 brcms_down(wlc->wl); 8175 return false; 8176 } 8177 8178 /* grab and clear the saved software intstatus bits */ 8179 macintstatus = wlc->macintstatus; 8180 wlc->macintstatus = 0; 8181 8182 BCMMSG(wlc->wiphy, "wl%d: macintstatus 0x%x\n", 8183 wlc_hw->unit, macintstatus); 8184 8185 WARN_ON(macintstatus & MI_PRQ); /* PRQ Interrupt in non-MBSS */ 8186 8187 /* tx status */ 8188 if (macintstatus & MI_TFS) { 8189 bool fatal; 8190 if (brcms_b_txstatus(wlc->hw, bounded, &fatal)) 8191 wlc->macintstatus |= MI_TFS; 8192 if (fatal) { 8193 wiphy_err(wiphy, "MI_TFS: fatal\n"); 8194 goto fatal; 8195 } 8196 } 8197 8198 if (macintstatus & (MI_TBTT | MI_DTIM_TBTT)) 8199 brcms_c_tbtt(wlc); 8200 8201 /* ATIM window end */ 8202 if (macintstatus & MI_ATIMWINEND) { 8203 BCMMSG(wlc->wiphy, "end of ATIM window\n"); 8204 OR_REG(®s->maccommand, wlc->qvalid); 8205 wlc->qvalid = 0; 8206 } 8207 8208 /* 8209 * received data or control frame, MI_DMAINT is 8210 * indication of RX_FIFO interrupt 8211 */ 8212 if (macintstatus & MI_DMAINT) 8213 if (brcms_b_recv(wlc_hw, RX_FIFO, bounded)) 8214 wlc->macintstatus |= MI_DMAINT; 8215 8216 /* noise sample collected */ 8217 if (macintstatus & MI_BG_NOISE) 8218 wlc_phy_noise_sample_intr(wlc_hw->band->pi); 8219 8220 if (macintstatus & MI_GP0) { 8221 wiphy_err(wiphy, "wl%d: PSM microcode watchdog fired at %d " 8222 "(seconds). Resetting.\n", wlc_hw->unit, wlc_hw->now); 8223 8224 printk_once("%s : PSM Watchdog, chipid 0x%x, chiprev 0x%x\n", 8225 __func__, wlc_hw->sih->chip, 8226 wlc_hw->sih->chiprev); 8227 brcms_fatal_error(wlc_hw->wlc->wl); 8228 } 8229 8230 /* gptimer timeout */ 8231 if (macintstatus & MI_TO) 8232 W_REG(®s->gptimer, 0); 8233 8234 if (macintstatus & MI_RFDISABLE) { 8235 BCMMSG(wlc->wiphy, "wl%d: BMAC Detected a change on the" 8236 " RF Disable Input\n", wlc_hw->unit); 8237 brcms_rfkill_set_hw_state(wlc->wl); 8238 } 8239 8240 /* send any enq'd tx packets. Just makes sure to jump start tx */ 8241 if (!pktq_empty(&wlc->pkt_queue->q)) 8242 brcms_c_send_q(wlc); 8243 8244 /* it isn't done and needs to be resched if macintstatus is non-zero */ 8245 return wlc->macintstatus != 0; 8246 8247 fatal: 8248 brcms_fatal_error(wlc_hw->wlc->wl); 8249 return wlc->macintstatus != 0; 8250} 8251 8252void brcms_c_init(struct brcms_c_info *wlc, bool mute_tx) 8253{ 8254 struct d11regs __iomem *regs; 8255 u16 chanspec; 8256 8257 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit); 8258 8259 regs = wlc->regs; 8260 8261 /* 8262 * This will happen if a big-hammer was executed. In 8263 * that case, we want to go back to the channel that 8264 * we were on and not new channel 8265 */ 8266 if (wlc->pub->associated) 8267 chanspec = wlc->home_chanspec; 8268 else 8269 chanspec = brcms_c_init_chanspec(wlc); 8270 8271 brcms_b_init(wlc->hw, chanspec); 8272 8273 /* update beacon listen interval */ 8274 brcms_c_bcn_li_upd(wlc); 8275 8276 /* write ethernet address to core */ 8277 brcms_c_set_mac(wlc->bsscfg); 8278 brcms_c_set_bssid(wlc->bsscfg); 8279 8280 /* Update tsf_cfprep if associated and up */ 8281 if (wlc->pub->associated && wlc->bsscfg->up) { 8282 u32 bi; 8283 8284 /* get beacon period and convert to uS */ 8285 bi = wlc->bsscfg->current_bss->beacon_period << 10; 8286 /* 8287 * update since init path would reset 8288 * to default value 8289 */ 8290 W_REG(®s->tsf_cfprep, 8291 (bi << CFPREP_CBI_SHIFT)); 8292 8293 /* Update maccontrol PM related bits */ 8294 brcms_c_set_ps_ctrl(wlc); 8295 } 8296 8297 brcms_c_bandinit_ordered(wlc, chanspec); 8298 8299 /* init probe response timeout */ 8300 brcms_b_write_shm(wlc->hw, M_PRS_MAXTIME, wlc->prb_resp_timeout); 8301 8302 /* init max burst txop (framebursting) */ 8303 brcms_b_write_shm(wlc->hw, M_MBURST_TXOP, 8304 (wlc-> 8305 _rifs ? (EDCF_AC_VO_TXOP_AP << 5) : MAXFRAMEBURST_TXOP)); 8306 8307 /* initialize maximum allowed duty cycle */ 8308 brcms_c_duty_cycle_set(wlc, wlc->tx_duty_cycle_ofdm, true, true); 8309 brcms_c_duty_cycle_set(wlc, wlc->tx_duty_cycle_cck, false, true); 8310 8311 /* 8312 * Update some shared memory locations related to 8313 * max AMPDU size allowed to received 8314 */ 8315 brcms_c_ampdu_shm_upd(wlc->ampdu); 8316 8317 /* band-specific inits */ 8318 brcms_c_bsinit(wlc); 8319 8320 /* Enable EDCF mode (while the MAC is suspended) */ 8321 OR_REG(®s->ifs_ctl, IFS_USEEDCF); 8322 brcms_c_edcf_setparams(wlc, false); 8323 8324 /* Init precedence maps for empty FIFOs */ 8325 brcms_c_tx_prec_map_init(wlc); 8326 8327 /* read the ucode version if we have not yet done so */ 8328 if (wlc->ucode_rev == 0) { 8329 wlc->ucode_rev = 8330 brcms_b_read_shm(wlc->hw, M_BOM_REV_MAJOR) << NBITS(u16); 8331 wlc->ucode_rev |= brcms_b_read_shm(wlc->hw, M_BOM_REV_MINOR); 8332 } 8333 8334 /* ..now really unleash hell (allow the MAC out of suspend) */ 8335 brcms_c_enable_mac(wlc); 8336 8337 /* suspend the tx fifos and mute the phy for preism cac time */ 8338 if (mute_tx) 8339 brcms_b_mute(wlc->hw, true); 8340 8341 /* clear tx flow control */ 8342 brcms_c_txflowcontrol_reset(wlc); 8343 8344 /* enable the RF Disable Delay timer */ 8345 W_REG(&wlc->regs->rfdisabledly, RFDISABLE_DEFAULT); 8346 8347 /* 8348 * Initialize WME parameters; if they haven't been set by some other 8349 * mechanism (IOVar, etc) then read them from the hardware. 8350 */ 8351 if (GFIELD(wlc->wme_retries[0], EDCF_SHORT) == 0) { 8352 /* Uninitialized; read from HW */ 8353 int ac; 8354 8355 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) 8356 wlc->wme_retries[ac] = 8357 brcms_b_read_shm(wlc->hw, M_AC_TXLMT_ADDR(ac)); 8358 } 8359} 8360 8361/* 8362 * The common driver entry routine. Error codes should be unique 8363 */ 8364struct brcms_c_info * 8365brcms_c_attach(struct brcms_info *wl, u16 vendor, u16 device, uint unit, 8366 bool piomode, void __iomem *regsva, struct pci_dev *btparam, 8367 uint *perr) 8368{ 8369 struct brcms_c_info *wlc; 8370 uint err = 0; 8371 uint i, j; 8372 struct brcms_pub *pub; 8373 8374 /* allocate struct brcms_c_info state and its substructures */ 8375 wlc = (struct brcms_c_info *) brcms_c_attach_malloc(unit, &err, device); 8376 if (wlc == NULL) 8377 goto fail; 8378 wlc->wiphy = wl->wiphy; 8379 pub = wlc->pub; 8380 8381#if defined(BCMDBG) 8382 wlc_info_dbg = wlc; 8383#endif 8384 8385 wlc->band = wlc->bandstate[0]; 8386 wlc->core = wlc->corestate; 8387 wlc->wl = wl; 8388 pub->unit = unit; 8389 pub->_piomode = piomode; 8390 wlc->bandinit_pending = false; 8391 8392 /* populate struct brcms_c_info with default values */ 8393 brcms_c_info_init(wlc, unit); 8394 8395 /* update sta/ap related parameters */ 8396 brcms_c_ap_upd(wlc); 8397 8398 /* 8399 * low level attach steps(all hw accesses go 8400 * inside, no more in rest of the attach) 8401 */ 8402 err = brcms_b_attach(wlc, vendor, device, unit, piomode, regsva, 8403 btparam); 8404 if (err) 8405 goto fail; 8406 8407 brcms_c_protection_upd(wlc, BRCMS_PROT_N_PAM_OVR, OFF); 8408 8409 pub->phy_11ncapable = BRCMS_PHY_11N_CAP(wlc->band); 8410 8411 /* disable allowed duty cycle */ 8412 wlc->tx_duty_cycle_ofdm = 0; 8413 wlc->tx_duty_cycle_cck = 0; 8414 8415 brcms_c_stf_phy_chain_calc(wlc); 8416 8417 /* txchain 1: txant 0, txchain 2: txant 1 */ 8418 if (BRCMS_ISNPHY(wlc->band) && (wlc->stf->txstreams == 1)) 8419 wlc->stf->txant = wlc->stf->hw_txchain - 1; 8420 8421 /* push to BMAC driver */ 8422 wlc_phy_stf_chain_init(wlc->band->pi, wlc->stf->hw_txchain, 8423 wlc->stf->hw_rxchain); 8424 8425 /* pull up some info resulting from the low attach */ 8426 for (i = 0; i < NFIFO; i++) 8427 wlc->core->txavail[i] = wlc->hw->txavail[i]; 8428 8429 memcpy(&wlc->perm_etheraddr, &wlc->hw->etheraddr, ETH_ALEN); 8430 memcpy(&pub->cur_etheraddr, &wlc->hw->etheraddr, ETH_ALEN); 8431 8432 for (j = 0; j < wlc->pub->_nbands; j++) { 8433 wlc->band = wlc->bandstate[j]; 8434 8435 if (!brcms_c_attach_stf_ant_init(wlc)) { 8436 err = 24; 8437 goto fail; 8438 } 8439 8440 /* default contention windows size limits */ 8441 wlc->band->CWmin = APHY_CWMIN; 8442 wlc->band->CWmax = PHY_CWMAX; 8443 8444 /* init gmode value */ 8445 if (wlc->band->bandtype == BRCM_BAND_2G) { 8446 wlc->band->gmode = GMODE_AUTO; 8447 brcms_c_protection_upd(wlc, BRCMS_PROT_G_USER, 8448 wlc->band->gmode); 8449 } 8450 8451 /* init _n_enab supported mode */ 8452 if (BRCMS_PHY_11N_CAP(wlc->band)) { 8453 pub->_n_enab = SUPPORT_11N; 8454 brcms_c_protection_upd(wlc, BRCMS_PROT_N_USER, 8455 ((pub->_n_enab == 8456 SUPPORT_11N) ? WL_11N_2x2 : 8457 WL_11N_3x3)); 8458 } 8459 8460 /* init per-band default rateset, depend on band->gmode */ 8461 brcms_default_rateset(wlc, &wlc->band->defrateset); 8462 8463 /* fill in hw_rateset */ 8464 brcms_c_rateset_filter(&wlc->band->defrateset, 8465 &wlc->band->hw_rateset, false, 8466 BRCMS_RATES_CCK_OFDM, BRCMS_RATE_MASK, 8467 (bool) (wlc->pub->_n_enab & SUPPORT_11N)); 8468 } 8469 8470 /* 8471 * update antenna config due to 8472 * wlc->stf->txant/txchain/ant_rx_ovr change 8473 */ 8474 brcms_c_stf_phy_txant_upd(wlc); 8475 8476 /* attach each modules */ 8477 err = brcms_c_attach_module(wlc); 8478 if (err != 0) 8479 goto fail; 8480 8481 if (!brcms_c_timers_init(wlc, unit)) { 8482 wiphy_err(wl->wiphy, "wl%d: %s: init_timer failed\n", unit, 8483 __func__); 8484 err = 32; 8485 goto fail; 8486 } 8487 8488 /* depend on rateset, gmode */ 8489 wlc->cmi = brcms_c_channel_mgr_attach(wlc); 8490 if (!wlc->cmi) { 8491 wiphy_err(wl->wiphy, "wl%d: %s: channel_mgr_attach failed" 8492 "\n", unit, __func__); 8493 err = 33; 8494 goto fail; 8495 } 8496 8497 /* init default when all parameters are ready, i.e. ->rateset */ 8498 brcms_c_bss_default_init(wlc); 8499 8500 /* 8501 * Complete the wlc default state initializations.. 8502 */ 8503 8504 /* allocate our initial queue */ 8505 wlc->pkt_queue = brcms_c_txq_alloc(wlc); 8506 if (wlc->pkt_queue == NULL) { 8507 wiphy_err(wl->wiphy, "wl%d: %s: failed to malloc tx queue\n", 8508 unit, __func__); 8509 err = 100; 8510 goto fail; 8511 } 8512 8513 wlc->bsscfg->wlc = wlc; 8514 8515 wlc->mimoft = FT_HT; 8516 wlc->mimo_40txbw = AUTO; 8517 wlc->ofdm_40txbw = AUTO; 8518 wlc->cck_40txbw = AUTO; 8519 brcms_c_update_mimo_band_bwcap(wlc, BRCMS_N_BW_20IN2G_40IN5G); 8520 8521 /* Set default values of SGI */ 8522 if (BRCMS_SGI_CAP_PHY(wlc)) { 8523 brcms_c_ht_update_sgi_rx(wlc, (BRCMS_N_SGI_20 | 8524 BRCMS_N_SGI_40)); 8525 } else if (BRCMS_ISSSLPNPHY(wlc->band)) { 8526 brcms_c_ht_update_sgi_rx(wlc, (BRCMS_N_SGI_20 | 8527 BRCMS_N_SGI_40)); 8528 } else { 8529 brcms_c_ht_update_sgi_rx(wlc, 0); 8530 } 8531 8532 brcms_b_antsel_set(wlc->hw, wlc->asi->antsel_avail); 8533 8534 if (perr) 8535 *perr = 0; 8536 8537 return wlc; 8538 8539 fail: 8540 wiphy_err(wl->wiphy, "wl%d: %s: failed with err %d\n", 8541 unit, __func__, err); 8542 if (wlc) 8543 brcms_c_detach(wlc); 8544 8545 if (perr) 8546 *perr = err; 8547 return NULL; 8548} 8549