main.c revision 913911f47b510ea3bfa468b43e7d43ee52d2de10
1/* 2 * Copyright (c) 2010 Broadcom Corporation 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 18 19#include <linux/pci_ids.h> 20#include <linux/if_ether.h> 21#include <net/cfg80211.h> 22#include <net/mac80211.h> 23#include <brcm_hw_ids.h> 24#include <aiutils.h> 25#include <chipcommon.h> 26#include "rate.h" 27#include "scb.h" 28#include "phy/phy_hal.h" 29#include "channel.h" 30#include "antsel.h" 31#include "stf.h" 32#include "ampdu.h" 33#include "mac80211_if.h" 34#include "ucode_loader.h" 35#include "main.h" 36#include "soc.h" 37#include "dma.h" 38#include "debug.h" 39 40/* watchdog timer, in unit of ms */ 41#define TIMER_INTERVAL_WATCHDOG 1000 42/* radio monitor timer, in unit of ms */ 43#define TIMER_INTERVAL_RADIOCHK 800 44 45/* beacon interval, in unit of 1024TU */ 46#define BEACON_INTERVAL_DEFAULT 100 47 48/* n-mode support capability */ 49/* 2x2 includes both 1x1 & 2x2 devices 50 * reserved #define 2 for future when we want to separate 1x1 & 2x2 and 51 * control it independently 52 */ 53#define WL_11N_2x2 1 54#define WL_11N_3x3 3 55#define WL_11N_4x4 4 56 57#define EDCF_ACI_MASK 0x60 58#define EDCF_ACI_SHIFT 5 59#define EDCF_ECWMIN_MASK 0x0f 60#define EDCF_ECWMAX_SHIFT 4 61#define EDCF_AIFSN_MASK 0x0f 62#define EDCF_AIFSN_MAX 15 63#define EDCF_ECWMAX_MASK 0xf0 64 65#define EDCF_AC_BE_TXOP_STA 0x0000 66#define EDCF_AC_BK_TXOP_STA 0x0000 67#define EDCF_AC_VO_ACI_STA 0x62 68#define EDCF_AC_VO_ECW_STA 0x32 69#define EDCF_AC_VI_ACI_STA 0x42 70#define EDCF_AC_VI_ECW_STA 0x43 71#define EDCF_AC_BK_ECW_STA 0xA4 72#define EDCF_AC_VI_TXOP_STA 0x005e 73#define EDCF_AC_VO_TXOP_STA 0x002f 74#define EDCF_AC_BE_ACI_STA 0x03 75#define EDCF_AC_BE_ECW_STA 0xA4 76#define EDCF_AC_BK_ACI_STA 0x27 77#define EDCF_AC_VO_TXOP_AP 0x002f 78 79#define EDCF_TXOP2USEC(txop) ((txop) << 5) 80#define EDCF_ECW2CW(exp) ((1 << (exp)) - 1) 81 82#define APHY_SYMBOL_TIME 4 83#define APHY_PREAMBLE_TIME 16 84#define APHY_SIGNAL_TIME 4 85#define APHY_SIFS_TIME 16 86#define APHY_SERVICE_NBITS 16 87#define APHY_TAIL_NBITS 6 88#define BPHY_SIFS_TIME 10 89#define BPHY_PLCP_SHORT_TIME 96 90 91#define PREN_PREAMBLE 24 92#define PREN_MM_EXT 12 93#define PREN_PREAMBLE_EXT 4 94 95#define DOT11_MAC_HDR_LEN 24 96#define DOT11_ACK_LEN 10 97#define DOT11_BA_LEN 4 98#define DOT11_OFDM_SIGNAL_EXTENSION 6 99#define DOT11_MIN_FRAG_LEN 256 100#define DOT11_RTS_LEN 16 101#define DOT11_CTS_LEN 10 102#define DOT11_BA_BITMAP_LEN 128 103#define DOT11_MIN_BEACON_PERIOD 1 104#define DOT11_MAX_BEACON_PERIOD 0xFFFF 105#define DOT11_MAXNUMFRAGS 16 106#define DOT11_MAX_FRAG_LEN 2346 107 108#define BPHY_PLCP_TIME 192 109#define RIFS_11N_TIME 2 110 111/* length of the BCN template area */ 112#define BCN_TMPL_LEN 512 113 114/* brcms_bss_info flag bit values */ 115#define BRCMS_BSS_HT 0x0020 /* BSS is HT (MIMO) capable */ 116 117/* chip rx buffer offset */ 118#define BRCMS_HWRXOFF 38 119 120/* rfdisable delay timer 500 ms, runs of ALP clock */ 121#define RFDISABLE_DEFAULT 10000000 122 123#define BRCMS_TEMPSENSE_PERIOD 10 /* 10 second timeout */ 124 125/* precedences numbers for wlc queues. These are twice as may levels as 126 * 802.1D priorities. 127 * Odd numbers are used for HI priority traffic at same precedence levels 128 * These constants are used ONLY by wlc_prio2prec_map. Do not use them 129 * elsewhere. 130 */ 131#define _BRCMS_PREC_NONE 0 /* None = - */ 132#define _BRCMS_PREC_BK 2 /* BK - Background */ 133#define _BRCMS_PREC_BE 4 /* BE - Best-effort */ 134#define _BRCMS_PREC_EE 6 /* EE - Excellent-effort */ 135#define _BRCMS_PREC_CL 8 /* CL - Controlled Load */ 136#define _BRCMS_PREC_VI 10 /* Vi - Video */ 137#define _BRCMS_PREC_VO 12 /* Vo - Voice */ 138#define _BRCMS_PREC_NC 14 /* NC - Network Control */ 139 140/* synthpu_dly times in us */ 141#define SYNTHPU_DLY_APHY_US 3700 142#define SYNTHPU_DLY_BPHY_US 1050 143#define SYNTHPU_DLY_NPHY_US 2048 144#define SYNTHPU_DLY_LPPHY_US 300 145 146#define ANTCNT 10 /* vanilla M_MAX_ANTCNT val */ 147 148/* Per-AC retry limit register definitions; uses defs.h bitfield macros */ 149#define EDCF_SHORT_S 0 150#define EDCF_SFB_S 4 151#define EDCF_LONG_S 8 152#define EDCF_LFB_S 12 153#define EDCF_SHORT_M BITFIELD_MASK(4) 154#define EDCF_SFB_M BITFIELD_MASK(4) 155#define EDCF_LONG_M BITFIELD_MASK(4) 156#define EDCF_LFB_M BITFIELD_MASK(4) 157 158#define RETRY_SHORT_DEF 7 /* Default Short retry Limit */ 159#define RETRY_SHORT_MAX 255 /* Maximum Short retry Limit */ 160#define RETRY_LONG_DEF 4 /* Default Long retry count */ 161#define RETRY_SHORT_FB 3 /* Short count for fb rate */ 162#define RETRY_LONG_FB 2 /* Long count for fb rate */ 163 164#define APHY_CWMIN 15 165#define PHY_CWMAX 1023 166 167#define EDCF_AIFSN_MIN 1 168 169#define FRAGNUM_MASK 0xF 170 171#define APHY_SLOT_TIME 9 172#define BPHY_SLOT_TIME 20 173 174#define WL_SPURAVOID_OFF 0 175#define WL_SPURAVOID_ON1 1 176#define WL_SPURAVOID_ON2 2 177 178/* invalid core flags, use the saved coreflags */ 179#define BRCMS_USE_COREFLAGS 0xffffffff 180 181/* values for PLCPHdr_override */ 182#define BRCMS_PLCP_AUTO -1 183#define BRCMS_PLCP_SHORT 0 184#define BRCMS_PLCP_LONG 1 185 186/* values for g_protection_override and n_protection_override */ 187#define BRCMS_PROTECTION_AUTO -1 188#define BRCMS_PROTECTION_OFF 0 189#define BRCMS_PROTECTION_ON 1 190#define BRCMS_PROTECTION_MMHDR_ONLY 2 191#define BRCMS_PROTECTION_CTS_ONLY 3 192 193/* values for g_protection_control and n_protection_control */ 194#define BRCMS_PROTECTION_CTL_OFF 0 195#define BRCMS_PROTECTION_CTL_LOCAL 1 196#define BRCMS_PROTECTION_CTL_OVERLAP 2 197 198/* values for n_protection */ 199#define BRCMS_N_PROTECTION_OFF 0 200#define BRCMS_N_PROTECTION_OPTIONAL 1 201#define BRCMS_N_PROTECTION_20IN40 2 202#define BRCMS_N_PROTECTION_MIXEDMODE 3 203 204/* values for band specific 40MHz capabilities */ 205#define BRCMS_N_BW_20ALL 0 206#define BRCMS_N_BW_40ALL 1 207#define BRCMS_N_BW_20IN2G_40IN5G 2 208 209/* bitflags for SGI support (sgi_rx iovar) */ 210#define BRCMS_N_SGI_20 0x01 211#define BRCMS_N_SGI_40 0x02 212 213/* defines used by the nrate iovar */ 214/* MSC in use,indicates b0-6 holds an mcs */ 215#define NRATE_MCS_INUSE 0x00000080 216/* rate/mcs value */ 217#define NRATE_RATE_MASK 0x0000007f 218/* stf mode mask: siso, cdd, stbc, sdm */ 219#define NRATE_STF_MASK 0x0000ff00 220/* stf mode shift */ 221#define NRATE_STF_SHIFT 8 222/* bit indicate to override mcs only */ 223#define NRATE_OVERRIDE_MCS_ONLY 0x40000000 224#define NRATE_SGI_MASK 0x00800000 /* sgi mode */ 225#define NRATE_SGI_SHIFT 23 /* sgi mode */ 226#define NRATE_LDPC_CODING 0x00400000 /* adv coding in use */ 227#define NRATE_LDPC_SHIFT 22 /* ldpc shift */ 228 229#define NRATE_STF_SISO 0 /* stf mode SISO */ 230#define NRATE_STF_CDD 1 /* stf mode CDD */ 231#define NRATE_STF_STBC 2 /* stf mode STBC */ 232#define NRATE_STF_SDM 3 /* stf mode SDM */ 233 234#define MAX_DMA_SEGS 4 235 236/* # of entries in Tx FIFO */ 237#define NTXD 64 238/* Max # of entries in Rx FIFO based on 4kb page size */ 239#define NRXD 256 240 241/* Amount of headroom to leave in Tx FIFO */ 242#define TX_HEADROOM 4 243 244/* try to keep this # rbufs posted to the chip */ 245#define NRXBUFPOST 32 246 247/* max # frames to process in brcms_c_recv() */ 248#define RXBND 8 249/* max # tx status to process in wlc_txstatus() */ 250#define TXSBND 8 251 252/* brcmu_format_flags() bit description structure */ 253struct brcms_c_bit_desc { 254 u32 bit; 255 const char *name; 256}; 257 258/* 259 * The following table lists the buffer memory allocated to xmt fifos in HW. 260 * the size is in units of 256bytes(one block), total size is HW dependent 261 * ucode has default fifo partition, sw can overwrite if necessary 262 * 263 * This is documented in twiki under the topic UcodeTxFifo. Please ensure 264 * the twiki is updated before making changes. 265 */ 266 267/* Starting corerev for the fifo size table */ 268#define XMTFIFOTBL_STARTREV 17 269 270struct d11init { 271 __le16 addr; 272 __le16 size; 273 __le32 value; 274}; 275 276struct edcf_acparam { 277 u8 ACI; 278 u8 ECW; 279 u16 TXOP; 280} __packed; 281 282/* debug/trace */ 283uint brcm_msg_level; 284 285/* TX FIFO number to WME/802.1E Access Category */ 286static const u8 wme_fifo2ac[] = { 287 IEEE80211_AC_BK, 288 IEEE80211_AC_BE, 289 IEEE80211_AC_VI, 290 IEEE80211_AC_VO, 291 IEEE80211_AC_BE, 292 IEEE80211_AC_BE 293}; 294 295/* ieee80211 Access Category to TX FIFO number */ 296static const u8 wme_ac2fifo[] = { 297 TX_AC_VO_FIFO, 298 TX_AC_VI_FIFO, 299 TX_AC_BE_FIFO, 300 TX_AC_BK_FIFO 301}; 302 303/* 802.1D Priority to precedence queue mapping */ 304const u8 wlc_prio2prec_map[] = { 305 _BRCMS_PREC_BE, /* 0 BE - Best-effort */ 306 _BRCMS_PREC_BK, /* 1 BK - Background */ 307 _BRCMS_PREC_NONE, /* 2 None = - */ 308 _BRCMS_PREC_EE, /* 3 EE - Excellent-effort */ 309 _BRCMS_PREC_CL, /* 4 CL - Controlled Load */ 310 _BRCMS_PREC_VI, /* 5 Vi - Video */ 311 _BRCMS_PREC_VO, /* 6 Vo - Voice */ 312 _BRCMS_PREC_NC, /* 7 NC - Network Control */ 313}; 314 315static const u16 xmtfifo_sz[][NFIFO] = { 316 /* corerev 17: 5120, 49152, 49152, 5376, 4352, 1280 */ 317 {20, 192, 192, 21, 17, 5}, 318 /* corerev 18: */ 319 {0, 0, 0, 0, 0, 0}, 320 /* corerev 19: */ 321 {0, 0, 0, 0, 0, 0}, 322 /* corerev 20: 5120, 49152, 49152, 5376, 4352, 1280 */ 323 {20, 192, 192, 21, 17, 5}, 324 /* corerev 21: 2304, 14848, 5632, 3584, 3584, 1280 */ 325 {9, 58, 22, 14, 14, 5}, 326 /* corerev 22: 5120, 49152, 49152, 5376, 4352, 1280 */ 327 {20, 192, 192, 21, 17, 5}, 328 /* corerev 23: 5120, 49152, 49152, 5376, 4352, 1280 */ 329 {20, 192, 192, 21, 17, 5}, 330 /* corerev 24: 2304, 14848, 5632, 3584, 3584, 1280 */ 331 {9, 58, 22, 14, 14, 5}, 332 /* corerev 25: */ 333 {0, 0, 0, 0, 0, 0}, 334 /* corerev 26: */ 335 {0, 0, 0, 0, 0, 0}, 336 /* corerev 27: */ 337 {0, 0, 0, 0, 0, 0}, 338 /* corerev 28: 2304, 14848, 5632, 3584, 3584, 1280 */ 339 {9, 58, 22, 14, 14, 5}, 340}; 341 342#ifdef DEBUG 343static const char * const fifo_names[] = { 344 "AC_BK", "AC_BE", "AC_VI", "AC_VO", "BCMC", "ATIM" }; 345#else 346static const char fifo_names[6][0]; 347#endif 348 349#ifdef DEBUG 350/* pointer to most recently allocated wl/wlc */ 351static struct brcms_c_info *wlc_info_dbg = (struct brcms_c_info *) (NULL); 352#endif 353 354/* Mapping of ieee80211 AC numbers to tx fifos */ 355static const u8 ac_to_fifo_mapping[IEEE80211_NUM_ACS] = { 356 [IEEE80211_AC_VO] = TX_AC_VO_FIFO, 357 [IEEE80211_AC_VI] = TX_AC_VI_FIFO, 358 [IEEE80211_AC_BE] = TX_AC_BE_FIFO, 359 [IEEE80211_AC_BK] = TX_AC_BK_FIFO, 360}; 361 362/* Mapping of tx fifos to ieee80211 AC numbers */ 363static const u8 fifo_to_ac_mapping[IEEE80211_NUM_ACS] = { 364 [TX_AC_BK_FIFO] = IEEE80211_AC_BK, 365 [TX_AC_BE_FIFO] = IEEE80211_AC_BE, 366 [TX_AC_VI_FIFO] = IEEE80211_AC_VI, 367 [TX_AC_VO_FIFO] = IEEE80211_AC_VO, 368}; 369 370static u8 brcms_ac_to_fifo(u8 ac) 371{ 372 if (ac >= ARRAY_SIZE(ac_to_fifo_mapping)) 373 return TX_AC_BE_FIFO; 374 return ac_to_fifo_mapping[ac]; 375} 376 377static u8 brcms_fifo_to_ac(u8 fifo) 378{ 379 if (fifo >= ARRAY_SIZE(fifo_to_ac_mapping)) 380 return IEEE80211_AC_BE; 381 return fifo_to_ac_mapping[fifo]; 382} 383 384/* Find basic rate for a given rate */ 385static u8 brcms_basic_rate(struct brcms_c_info *wlc, u32 rspec) 386{ 387 if (is_mcs_rate(rspec)) 388 return wlc->band->basic_rate[mcs_table[rspec & RSPEC_RATE_MASK] 389 .leg_ofdm]; 390 return wlc->band->basic_rate[rspec & RSPEC_RATE_MASK]; 391} 392 393static u16 frametype(u32 rspec, u8 mimoframe) 394{ 395 if (is_mcs_rate(rspec)) 396 return mimoframe; 397 return is_cck_rate(rspec) ? FT_CCK : FT_OFDM; 398} 399 400/* currently the best mechanism for determining SIFS is the band in use */ 401static u16 get_sifs(struct brcms_band *band) 402{ 403 return band->bandtype == BRCM_BAND_5G ? APHY_SIFS_TIME : 404 BPHY_SIFS_TIME; 405} 406 407/* 408 * Detect Card removed. 409 * Even checking an sbconfig register read will not false trigger when the core 410 * is in reset it breaks CF address mechanism. Accessing gphy phyversion will 411 * cause SB error if aphy is in reset on 4306B0-DB. Need a simple accessible 412 * reg with fixed 0/1 pattern (some platforms return all 0). 413 * If clocks are present, call the sb routine which will figure out if the 414 * device is removed. 415 */ 416static bool brcms_deviceremoved(struct brcms_c_info *wlc) 417{ 418 u32 macctrl; 419 420 if (!wlc->hw->clk) 421 return ai_deviceremoved(wlc->hw->sih); 422 macctrl = bcma_read32(wlc->hw->d11core, 423 D11REGOFFS(maccontrol)); 424 return (macctrl & (MCTL_PSM_JMP_0 | MCTL_IHR_EN)) != MCTL_IHR_EN; 425} 426 427/* sum the individual fifo tx pending packet counts */ 428static int brcms_txpktpendtot(struct brcms_c_info *wlc) 429{ 430 int i; 431 int pending = 0; 432 433 for (i = 0; i < ARRAY_SIZE(wlc->hw->di); i++) 434 if (wlc->hw->di[i]) 435 pending += dma_txpending(wlc->hw->di[i]); 436 return pending; 437} 438 439static bool brcms_is_mband_unlocked(struct brcms_c_info *wlc) 440{ 441 return wlc->pub->_nbands > 1 && !wlc->bandlocked; 442} 443 444static int brcms_chspec_bw(u16 chanspec) 445{ 446 if (CHSPEC_IS40(chanspec)) 447 return BRCMS_40_MHZ; 448 if (CHSPEC_IS20(chanspec)) 449 return BRCMS_20_MHZ; 450 451 return BRCMS_10_MHZ; 452} 453 454static void brcms_c_bsscfg_mfree(struct brcms_bss_cfg *cfg) 455{ 456 if (cfg == NULL) 457 return; 458 459 kfree(cfg->current_bss); 460 kfree(cfg); 461} 462 463static void brcms_c_detach_mfree(struct brcms_c_info *wlc) 464{ 465 if (wlc == NULL) 466 return; 467 468 brcms_c_bsscfg_mfree(wlc->bsscfg); 469 kfree(wlc->pub); 470 kfree(wlc->modulecb); 471 kfree(wlc->default_bss); 472 kfree(wlc->protection); 473 kfree(wlc->stf); 474 kfree(wlc->bandstate[0]); 475 kfree(wlc->corestate->macstat_snapshot); 476 kfree(wlc->corestate); 477 kfree(wlc->hw->bandstate[0]); 478 kfree(wlc->hw); 479 480 /* free the wlc */ 481 kfree(wlc); 482 wlc = NULL; 483} 484 485static struct brcms_bss_cfg *brcms_c_bsscfg_malloc(uint unit) 486{ 487 struct brcms_bss_cfg *cfg; 488 489 cfg = kzalloc(sizeof(struct brcms_bss_cfg), GFP_ATOMIC); 490 if (cfg == NULL) 491 goto fail; 492 493 cfg->current_bss = kzalloc(sizeof(struct brcms_bss_info), GFP_ATOMIC); 494 if (cfg->current_bss == NULL) 495 goto fail; 496 497 return cfg; 498 499 fail: 500 brcms_c_bsscfg_mfree(cfg); 501 return NULL; 502} 503 504static struct brcms_c_info * 505brcms_c_attach_malloc(uint unit, uint *err, uint devid) 506{ 507 struct brcms_c_info *wlc; 508 509 wlc = kzalloc(sizeof(struct brcms_c_info), GFP_ATOMIC); 510 if (wlc == NULL) { 511 *err = 1002; 512 goto fail; 513 } 514 515 /* allocate struct brcms_c_pub state structure */ 516 wlc->pub = kzalloc(sizeof(struct brcms_pub), GFP_ATOMIC); 517 if (wlc->pub == NULL) { 518 *err = 1003; 519 goto fail; 520 } 521 wlc->pub->wlc = wlc; 522 523 /* allocate struct brcms_hardware state structure */ 524 525 wlc->hw = kzalloc(sizeof(struct brcms_hardware), GFP_ATOMIC); 526 if (wlc->hw == NULL) { 527 *err = 1005; 528 goto fail; 529 } 530 wlc->hw->wlc = wlc; 531 532 wlc->hw->bandstate[0] = 533 kzalloc(sizeof(struct brcms_hw_band) * MAXBANDS, GFP_ATOMIC); 534 if (wlc->hw->bandstate[0] == NULL) { 535 *err = 1006; 536 goto fail; 537 } else { 538 int i; 539 540 for (i = 1; i < MAXBANDS; i++) 541 wlc->hw->bandstate[i] = (struct brcms_hw_band *) 542 ((unsigned long)wlc->hw->bandstate[0] + 543 (sizeof(struct brcms_hw_band) * i)); 544 } 545 546 wlc->modulecb = 547 kzalloc(sizeof(struct modulecb) * BRCMS_MAXMODULES, GFP_ATOMIC); 548 if (wlc->modulecb == NULL) { 549 *err = 1009; 550 goto fail; 551 } 552 553 wlc->default_bss = kzalloc(sizeof(struct brcms_bss_info), GFP_ATOMIC); 554 if (wlc->default_bss == NULL) { 555 *err = 1010; 556 goto fail; 557 } 558 559 wlc->bsscfg = brcms_c_bsscfg_malloc(unit); 560 if (wlc->bsscfg == NULL) { 561 *err = 1011; 562 goto fail; 563 } 564 565 wlc->protection = kzalloc(sizeof(struct brcms_protection), 566 GFP_ATOMIC); 567 if (wlc->protection == NULL) { 568 *err = 1016; 569 goto fail; 570 } 571 572 wlc->stf = kzalloc(sizeof(struct brcms_stf), GFP_ATOMIC); 573 if (wlc->stf == NULL) { 574 *err = 1017; 575 goto fail; 576 } 577 578 wlc->bandstate[0] = 579 kzalloc(sizeof(struct brcms_band)*MAXBANDS, GFP_ATOMIC); 580 if (wlc->bandstate[0] == NULL) { 581 *err = 1025; 582 goto fail; 583 } else { 584 int i; 585 586 for (i = 1; i < MAXBANDS; i++) 587 wlc->bandstate[i] = (struct brcms_band *) 588 ((unsigned long)wlc->bandstate[0] 589 + (sizeof(struct brcms_band)*i)); 590 } 591 592 wlc->corestate = kzalloc(sizeof(struct brcms_core), GFP_ATOMIC); 593 if (wlc->corestate == NULL) { 594 *err = 1026; 595 goto fail; 596 } 597 598 wlc->corestate->macstat_snapshot = 599 kzalloc(sizeof(struct macstat), GFP_ATOMIC); 600 if (wlc->corestate->macstat_snapshot == NULL) { 601 *err = 1027; 602 goto fail; 603 } 604 605 return wlc; 606 607 fail: 608 brcms_c_detach_mfree(wlc); 609 return NULL; 610} 611 612/* 613 * Update the slot timing for standard 11b/g (20us slots) 614 * or shortslot 11g (9us slots) 615 * The PSM needs to be suspended for this call. 616 */ 617static void brcms_b_update_slot_timing(struct brcms_hardware *wlc_hw, 618 bool shortslot) 619{ 620 struct bcma_device *core = wlc_hw->d11core; 621 622 if (shortslot) { 623 /* 11g short slot: 11a timing */ 624 bcma_write16(core, D11REGOFFS(ifs_slot), 0x0207); 625 brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, APHY_SLOT_TIME); 626 } else { 627 /* 11g long slot: 11b timing */ 628 bcma_write16(core, D11REGOFFS(ifs_slot), 0x0212); 629 brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, BPHY_SLOT_TIME); 630 } 631} 632 633/* 634 * calculate frame duration of a given rate and length, return 635 * time in usec unit 636 */ 637static uint brcms_c_calc_frame_time(struct brcms_c_info *wlc, u32 ratespec, 638 u8 preamble_type, uint mac_len) 639{ 640 uint nsyms, dur = 0, Ndps, kNdps; 641 uint rate = rspec2rate(ratespec); 642 643 if (rate == 0) { 644 brcms_err(wlc->hw->d11core, "wl%d: WAR: using rate of 1 mbps\n", 645 wlc->pub->unit); 646 rate = BRCM_RATE_1M; 647 } 648 649 brcms_dbg_mac80211(wlc->hw->d11core, 650 "wl%d: rspec 0x%x, preamble_type %d, len%d\n", 651 wlc->pub->unit, ratespec, preamble_type, mac_len); 652 653 if (is_mcs_rate(ratespec)) { 654 uint mcs = ratespec & RSPEC_RATE_MASK; 655 int tot_streams = mcs_2_txstreams(mcs) + rspec_stc(ratespec); 656 657 dur = PREN_PREAMBLE + (tot_streams * PREN_PREAMBLE_EXT); 658 if (preamble_type == BRCMS_MM_PREAMBLE) 659 dur += PREN_MM_EXT; 660 /* 1000Ndbps = kbps * 4 */ 661 kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec), 662 rspec_issgi(ratespec)) * 4; 663 664 if (rspec_stc(ratespec) == 0) 665 nsyms = 666 CEIL((APHY_SERVICE_NBITS + 8 * mac_len + 667 APHY_TAIL_NBITS) * 1000, kNdps); 668 else 669 /* STBC needs to have even number of symbols */ 670 nsyms = 671 2 * 672 CEIL((APHY_SERVICE_NBITS + 8 * mac_len + 673 APHY_TAIL_NBITS) * 1000, 2 * kNdps); 674 675 dur += APHY_SYMBOL_TIME * nsyms; 676 if (wlc->band->bandtype == BRCM_BAND_2G) 677 dur += DOT11_OFDM_SIGNAL_EXTENSION; 678 } else if (is_ofdm_rate(rate)) { 679 dur = APHY_PREAMBLE_TIME; 680 dur += APHY_SIGNAL_TIME; 681 /* Ndbps = Mbps * 4 = rate(500Kbps) * 2 */ 682 Ndps = rate * 2; 683 /* NSyms = CEILING((SERVICE + 8*NBytes + TAIL) / Ndbps) */ 684 nsyms = 685 CEIL((APHY_SERVICE_NBITS + 8 * mac_len + APHY_TAIL_NBITS), 686 Ndps); 687 dur += APHY_SYMBOL_TIME * nsyms; 688 if (wlc->band->bandtype == BRCM_BAND_2G) 689 dur += DOT11_OFDM_SIGNAL_EXTENSION; 690 } else { 691 /* 692 * calc # bits * 2 so factor of 2 in rate (1/2 mbps) 693 * will divide out 694 */ 695 mac_len = mac_len * 8 * 2; 696 /* calc ceiling of bits/rate = microseconds of air time */ 697 dur = (mac_len + rate - 1) / rate; 698 if (preamble_type & BRCMS_SHORT_PREAMBLE) 699 dur += BPHY_PLCP_SHORT_TIME; 700 else 701 dur += BPHY_PLCP_TIME; 702 } 703 return dur; 704} 705 706static void brcms_c_write_inits(struct brcms_hardware *wlc_hw, 707 const struct d11init *inits) 708{ 709 struct bcma_device *core = wlc_hw->d11core; 710 int i; 711 uint offset; 712 u16 size; 713 u32 value; 714 715 brcms_dbg_info(wlc_hw->d11core, "wl%d\n", wlc_hw->unit); 716 717 for (i = 0; inits[i].addr != cpu_to_le16(0xffff); i++) { 718 size = le16_to_cpu(inits[i].size); 719 offset = le16_to_cpu(inits[i].addr); 720 value = le32_to_cpu(inits[i].value); 721 if (size == 2) 722 bcma_write16(core, offset, value); 723 else if (size == 4) 724 bcma_write32(core, offset, value); 725 else 726 break; 727 } 728} 729 730static void brcms_c_write_mhf(struct brcms_hardware *wlc_hw, u16 *mhfs) 731{ 732 u8 idx; 733 u16 addr[] = { 734 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4, 735 M_HOST_FLAGS5 736 }; 737 738 for (idx = 0; idx < MHFMAX; idx++) 739 brcms_b_write_shm(wlc_hw, addr[idx], mhfs[idx]); 740} 741 742static void brcms_c_ucode_bsinit(struct brcms_hardware *wlc_hw) 743{ 744 struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode; 745 746 /* init microcode host flags */ 747 brcms_c_write_mhf(wlc_hw, wlc_hw->band->mhfs); 748 749 /* do band-specific ucode IHR, SHM, and SCR inits */ 750 if (D11REV_IS(wlc_hw->corerev, 23)) { 751 if (BRCMS_ISNPHY(wlc_hw->band)) 752 brcms_c_write_inits(wlc_hw, ucode->d11n0bsinitvals16); 753 else 754 brcms_err(wlc_hw->d11core, 755 "%s: wl%d: unsupported phy in corerev %d\n", 756 __func__, wlc_hw->unit, 757 wlc_hw->corerev); 758 } else { 759 if (D11REV_IS(wlc_hw->corerev, 24)) { 760 if (BRCMS_ISLCNPHY(wlc_hw->band)) 761 brcms_c_write_inits(wlc_hw, 762 ucode->d11lcn0bsinitvals24); 763 else 764 brcms_err(wlc_hw->d11core, 765 "%s: wl%d: unsupported phy in core rev %d\n", 766 __func__, wlc_hw->unit, 767 wlc_hw->corerev); 768 } else { 769 brcms_err(wlc_hw->d11core, 770 "%s: wl%d: unsupported corerev %d\n", 771 __func__, wlc_hw->unit, wlc_hw->corerev); 772 } 773 } 774} 775 776static void brcms_b_core_ioctl(struct brcms_hardware *wlc_hw, u32 m, u32 v) 777{ 778 struct bcma_device *core = wlc_hw->d11core; 779 u32 ioctl = bcma_aread32(core, BCMA_IOCTL) & ~m; 780 781 bcma_awrite32(core, BCMA_IOCTL, ioctl | v); 782} 783 784static void brcms_b_core_phy_clk(struct brcms_hardware *wlc_hw, bool clk) 785{ 786 brcms_dbg_info(wlc_hw->d11core, "wl%d: clk %d\n", wlc_hw->unit, clk); 787 788 wlc_hw->phyclk = clk; 789 790 if (OFF == clk) { /* clear gmode bit, put phy into reset */ 791 792 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC | SICF_GMODE), 793 (SICF_PRST | SICF_FGC)); 794 udelay(1); 795 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC), SICF_PRST); 796 udelay(1); 797 798 } else { /* take phy out of reset */ 799 800 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC), SICF_FGC); 801 udelay(1); 802 brcms_b_core_ioctl(wlc_hw, SICF_FGC, 0); 803 udelay(1); 804 805 } 806} 807 808/* low-level band switch utility routine */ 809static void brcms_c_setxband(struct brcms_hardware *wlc_hw, uint bandunit) 810{ 811 brcms_dbg_mac80211(wlc_hw->d11core, "wl%d: bandunit %d\n", wlc_hw->unit, 812 bandunit); 813 814 wlc_hw->band = wlc_hw->bandstate[bandunit]; 815 816 /* 817 * BMAC_NOTE: 818 * until we eliminate need for wlc->band refs in low level code 819 */ 820 wlc_hw->wlc->band = wlc_hw->wlc->bandstate[bandunit]; 821 822 /* set gmode core flag */ 823 if (wlc_hw->sbclk && !wlc_hw->noreset) { 824 u32 gmode = 0; 825 826 if (bandunit == 0) 827 gmode = SICF_GMODE; 828 829 brcms_b_core_ioctl(wlc_hw, SICF_GMODE, gmode); 830 } 831} 832 833/* switch to new band but leave it inactive */ 834static u32 brcms_c_setband_inact(struct brcms_c_info *wlc, uint bandunit) 835{ 836 struct brcms_hardware *wlc_hw = wlc->hw; 837 u32 macintmask; 838 u32 macctrl; 839 840 brcms_dbg_mac80211(wlc_hw->d11core, "wl%d\n", wlc_hw->unit); 841 macctrl = bcma_read32(wlc_hw->d11core, 842 D11REGOFFS(maccontrol)); 843 WARN_ON((macctrl & MCTL_EN_MAC) != 0); 844 845 /* disable interrupts */ 846 macintmask = brcms_intrsoff(wlc->wl); 847 848 /* radio off */ 849 wlc_phy_switch_radio(wlc_hw->band->pi, OFF); 850 851 brcms_b_core_phy_clk(wlc_hw, OFF); 852 853 brcms_c_setxband(wlc_hw, bandunit); 854 855 return macintmask; 856} 857 858/* process an individual struct tx_status */ 859static bool 860brcms_c_dotxstatus(struct brcms_c_info *wlc, struct tx_status *txs) 861{ 862 struct sk_buff *p = NULL; 863 uint queue = NFIFO; 864 struct dma_pub *dma = NULL; 865 struct d11txh *txh; 866 struct scb *scb = NULL; 867 bool free_pdu; 868 int tx_rts, tx_frame_count, tx_rts_count; 869 uint totlen, supr_status; 870 bool lastframe; 871 struct ieee80211_hdr *h; 872 u16 mcl; 873 struct ieee80211_tx_info *tx_info; 874 struct ieee80211_tx_rate *txrate; 875 int i; 876 bool fatal = true; 877 878 /* discard intermediate indications for ucode with one legitimate case: 879 * e.g. if "useRTS" is set. ucode did a successful rts/cts exchange, 880 * but the subsequent tx of DATA failed. so it will start rts/cts 881 * from the beginning (resetting the rts transmission count) 882 */ 883 if (!(txs->status & TX_STATUS_AMPDU) 884 && (txs->status & TX_STATUS_INTERMEDIATE)) { 885 BCMMSG(wlc->wiphy, "INTERMEDIATE but not AMPDU\n"); 886 fatal = false; 887 goto out; 888 } 889 890 queue = txs->frameid & TXFID_QUEUE_MASK; 891 if (queue >= NFIFO) 892 goto out; 893 894 dma = wlc->hw->di[queue]; 895 896 p = dma_getnexttxp(wlc->hw->di[queue], DMA_RANGE_TRANSMITTED); 897 if (p == NULL) 898 goto out; 899 900 txh = (struct d11txh *) (p->data); 901 mcl = le16_to_cpu(txh->MacTxControlLow); 902 903 if (txs->phyerr) { 904 if (brcm_msg_level & BRCM_DL_INFO) { 905 brcms_err(wlc->hw->d11core, "phyerr 0x%x, rate 0x%x\n", 906 txs->phyerr, txh->MainRates); 907 brcms_c_print_txdesc(txh); 908 } 909 brcms_c_print_txstatus(txs); 910 } 911 912 if (txs->frameid != le16_to_cpu(txh->TxFrameID)) 913 goto out; 914 tx_info = IEEE80211_SKB_CB(p); 915 h = (struct ieee80211_hdr *)((u8 *) (txh + 1) + D11_PHY_HDR_LEN); 916 917 if (tx_info->rate_driver_data[0]) 918 scb = &wlc->pri_scb; 919 920 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) { 921 brcms_c_ampdu_dotxstatus(wlc->ampdu, scb, p, txs); 922 fatal = false; 923 goto out; 924 } 925 926 supr_status = txs->status & TX_STATUS_SUPR_MASK; 927 if (supr_status == TX_STATUS_SUPR_BADCH) 928 BCMMSG(wlc->wiphy, 929 "%s: Pkt tx suppressed, possibly channel %d\n", 930 __func__, CHSPEC_CHANNEL(wlc->default_bss->chanspec)); 931 932 tx_rts = le16_to_cpu(txh->MacTxControlLow) & TXC_SENDRTS; 933 tx_frame_count = 934 (txs->status & TX_STATUS_FRM_RTX_MASK) >> TX_STATUS_FRM_RTX_SHIFT; 935 tx_rts_count = 936 (txs->status & TX_STATUS_RTS_RTX_MASK) >> TX_STATUS_RTS_RTX_SHIFT; 937 938 lastframe = !ieee80211_has_morefrags(h->frame_control); 939 940 if (!lastframe) { 941 brcms_err(wlc->hw->d11core, "Not last frame!\n"); 942 } else { 943 /* 944 * Set information to be consumed by Minstrel ht. 945 * 946 * The "fallback limit" is the number of tx attempts a given 947 * MPDU is sent at the "primary" rate. Tx attempts beyond that 948 * limit are sent at the "secondary" rate. 949 * A 'short frame' does not exceed RTS treshold. 950 */ 951 u16 sfbl, /* Short Frame Rate Fallback Limit */ 952 lfbl, /* Long Frame Rate Fallback Limit */ 953 fbl; 954 955 if (queue < IEEE80211_NUM_ACS) { 956 sfbl = GFIELD(wlc->wme_retries[wme_fifo2ac[queue]], 957 EDCF_SFB); 958 lfbl = GFIELD(wlc->wme_retries[wme_fifo2ac[queue]], 959 EDCF_LFB); 960 } else { 961 sfbl = wlc->SFBL; 962 lfbl = wlc->LFBL; 963 } 964 965 txrate = tx_info->status.rates; 966 if (txrate[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) 967 fbl = lfbl; 968 else 969 fbl = sfbl; 970 971 ieee80211_tx_info_clear_status(tx_info); 972 973 if ((tx_frame_count > fbl) && (txrate[1].idx >= 0)) { 974 /* 975 * rate selection requested a fallback rate 976 * and we used it 977 */ 978 txrate[0].count = fbl; 979 txrate[1].count = tx_frame_count - fbl; 980 } else { 981 /* 982 * rate selection did not request fallback rate, or 983 * we didn't need it 984 */ 985 txrate[0].count = tx_frame_count; 986 /* 987 * rc80211_minstrel.c:minstrel_tx_status() expects 988 * unused rates to be marked with idx = -1 989 */ 990 txrate[1].idx = -1; 991 txrate[1].count = 0; 992 } 993 994 /* clear the rest of the rates */ 995 for (i = 2; i < IEEE80211_TX_MAX_RATES; i++) { 996 txrate[i].idx = -1; 997 txrate[i].count = 0; 998 } 999 1000 if (txs->status & TX_STATUS_ACK_RCV) 1001 tx_info->flags |= IEEE80211_TX_STAT_ACK; 1002 } 1003 1004 totlen = p->len; 1005 free_pdu = true; 1006 1007 if (lastframe) { 1008 /* remove PLCP & Broadcom tx descriptor header */ 1009 skb_pull(p, D11_PHY_HDR_LEN); 1010 skb_pull(p, D11_TXH_LEN); 1011 ieee80211_tx_status_irqsafe(wlc->pub->ieee_hw, p); 1012 } else { 1013 brcms_err(wlc->hw->d11core, 1014 "%s: Not last frame => not calling tx_status\n", 1015 __func__); 1016 } 1017 1018 fatal = false; 1019 1020 out: 1021 if (fatal && p) 1022 brcmu_pkt_buf_free_skb(p); 1023 1024 if (dma && queue < NFIFO) { 1025 u16 ac_queue = brcms_fifo_to_ac(queue); 1026 if (dma->txavail > TX_HEADROOM && queue < TX_BCMC_FIFO && 1027 ieee80211_queue_stopped(wlc->pub->ieee_hw, ac_queue)) 1028 ieee80211_wake_queue(wlc->pub->ieee_hw, ac_queue); 1029 dma_kick_tx(dma); 1030 } 1031 1032 return fatal; 1033} 1034 1035/* process tx completion events in BMAC 1036 * Return true if more tx status need to be processed. false otherwise. 1037 */ 1038static bool 1039brcms_b_txstatus(struct brcms_hardware *wlc_hw, bool bound, bool *fatal) 1040{ 1041 bool morepending = false; 1042 struct brcms_c_info *wlc = wlc_hw->wlc; 1043 struct bcma_device *core; 1044 struct tx_status txstatus, *txs; 1045 u32 s1, s2; 1046 uint n = 0; 1047 /* 1048 * Param 'max_tx_num' indicates max. # tx status to process before 1049 * break out. 1050 */ 1051 uint max_tx_num = bound ? TXSBND : -1; 1052 1053 BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit); 1054 1055 txs = &txstatus; 1056 core = wlc_hw->d11core; 1057 *fatal = false; 1058 s1 = bcma_read32(core, D11REGOFFS(frmtxstatus)); 1059 while (!(*fatal) 1060 && (s1 & TXS_V)) { 1061 1062 if (s1 == 0xffffffff) { 1063 brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit, 1064 __func__); 1065 return morepending; 1066 } 1067 s2 = bcma_read32(core, D11REGOFFS(frmtxstatus2)); 1068 1069 txs->status = s1 & TXS_STATUS_MASK; 1070 txs->frameid = (s1 & TXS_FID_MASK) >> TXS_FID_SHIFT; 1071 txs->sequence = s2 & TXS_SEQ_MASK; 1072 txs->phyerr = (s2 & TXS_PTX_MASK) >> TXS_PTX_SHIFT; 1073 txs->lasttxtime = 0; 1074 1075 *fatal = brcms_c_dotxstatus(wlc_hw->wlc, txs); 1076 1077 /* !give others some time to run! */ 1078 if (++n >= max_tx_num) 1079 break; 1080 s1 = bcma_read32(core, D11REGOFFS(frmtxstatus)); 1081 } 1082 1083 if (*fatal) 1084 return 0; 1085 1086 if (n >= max_tx_num) 1087 morepending = true; 1088 1089 return morepending; 1090} 1091 1092static void brcms_c_tbtt(struct brcms_c_info *wlc) 1093{ 1094 if (!wlc->bsscfg->BSS) 1095 /* 1096 * DirFrmQ is now valid...defer setting until end 1097 * of ATIM window 1098 */ 1099 wlc->qvalid |= MCMD_DIRFRMQVAL; 1100} 1101 1102/* set initial host flags value */ 1103static void 1104brcms_c_mhfdef(struct brcms_c_info *wlc, u16 *mhfs, u16 mhf2_init) 1105{ 1106 struct brcms_hardware *wlc_hw = wlc->hw; 1107 1108 memset(mhfs, 0, MHFMAX * sizeof(u16)); 1109 1110 mhfs[MHF2] |= mhf2_init; 1111 1112 /* prohibit use of slowclock on multifunction boards */ 1113 if (wlc_hw->boardflags & BFL_NOPLLDOWN) 1114 mhfs[MHF1] |= MHF1_FORCEFASTCLK; 1115 1116 if (BRCMS_ISNPHY(wlc_hw->band) && NREV_LT(wlc_hw->band->phyrev, 2)) { 1117 mhfs[MHF2] |= MHF2_NPHY40MHZ_WAR; 1118 mhfs[MHF1] |= MHF1_IQSWAP_WAR; 1119 } 1120} 1121 1122static uint 1123dmareg(uint direction, uint fifonum) 1124{ 1125 if (direction == DMA_TX) 1126 return offsetof(struct d11regs, fifo64regs[fifonum].dmaxmt); 1127 return offsetof(struct d11regs, fifo64regs[fifonum].dmarcv); 1128} 1129 1130static bool brcms_b_attach_dmapio(struct brcms_c_info *wlc, uint j, bool wme) 1131{ 1132 uint i; 1133 char name[8]; 1134 /* 1135 * ucode host flag 2 needed for pio mode, independent of band and fifo 1136 */ 1137 u16 pio_mhf2 = 0; 1138 struct brcms_hardware *wlc_hw = wlc->hw; 1139 uint unit = wlc_hw->unit; 1140 1141 /* name and offsets for dma_attach */ 1142 snprintf(name, sizeof(name), "wl%d", unit); 1143 1144 if (wlc_hw->di[0] == NULL) { /* Init FIFOs */ 1145 int dma_attach_err = 0; 1146 1147 /* 1148 * FIFO 0 1149 * TX: TX_AC_BK_FIFO (TX AC Background data packets) 1150 * RX: RX_FIFO (RX data packets) 1151 */ 1152 wlc_hw->di[0] = dma_attach(name, wlc, 1153 (wme ? dmareg(DMA_TX, 0) : 0), 1154 dmareg(DMA_RX, 0), 1155 (wme ? NTXD : 0), NRXD, 1156 RXBUFSZ, -1, NRXBUFPOST, 1157 BRCMS_HWRXOFF, &brcm_msg_level); 1158 dma_attach_err |= (NULL == wlc_hw->di[0]); 1159 1160 /* 1161 * FIFO 1 1162 * TX: TX_AC_BE_FIFO (TX AC Best-Effort data packets) 1163 * (legacy) TX_DATA_FIFO (TX data packets) 1164 * RX: UNUSED 1165 */ 1166 wlc_hw->di[1] = dma_attach(name, wlc, 1167 dmareg(DMA_TX, 1), 0, 1168 NTXD, 0, 0, -1, 0, 0, 1169 &brcm_msg_level); 1170 dma_attach_err |= (NULL == wlc_hw->di[1]); 1171 1172 /* 1173 * FIFO 2 1174 * TX: TX_AC_VI_FIFO (TX AC Video data packets) 1175 * RX: UNUSED 1176 */ 1177 wlc_hw->di[2] = dma_attach(name, wlc, 1178 dmareg(DMA_TX, 2), 0, 1179 NTXD, 0, 0, -1, 0, 0, 1180 &brcm_msg_level); 1181 dma_attach_err |= (NULL == wlc_hw->di[2]); 1182 /* 1183 * FIFO 3 1184 * TX: TX_AC_VO_FIFO (TX AC Voice data packets) 1185 * (legacy) TX_CTL_FIFO (TX control & mgmt packets) 1186 */ 1187 wlc_hw->di[3] = dma_attach(name, wlc, 1188 dmareg(DMA_TX, 3), 1189 0, NTXD, 0, 0, -1, 1190 0, 0, &brcm_msg_level); 1191 dma_attach_err |= (NULL == wlc_hw->di[3]); 1192/* Cleaner to leave this as if with AP defined */ 1193 1194 if (dma_attach_err) { 1195 brcms_err(wlc_hw->d11core, 1196 "wl%d: wlc_attach: dma_attach failed\n", 1197 unit); 1198 return false; 1199 } 1200 1201 /* get pointer to dma engine tx flow control variable */ 1202 for (i = 0; i < NFIFO; i++) 1203 if (wlc_hw->di[i]) 1204 wlc_hw->txavail[i] = 1205 (uint *) dma_getvar(wlc_hw->di[i], 1206 "&txavail"); 1207 } 1208 1209 /* initial ucode host flags */ 1210 brcms_c_mhfdef(wlc, wlc_hw->band->mhfs, pio_mhf2); 1211 1212 return true; 1213} 1214 1215static void brcms_b_detach_dmapio(struct brcms_hardware *wlc_hw) 1216{ 1217 uint j; 1218 1219 for (j = 0; j < NFIFO; j++) { 1220 if (wlc_hw->di[j]) { 1221 dma_detach(wlc_hw->di[j]); 1222 wlc_hw->di[j] = NULL; 1223 } 1224 } 1225} 1226 1227/* 1228 * Initialize brcms_c_info default values ... 1229 * may get overrides later in this function 1230 * BMAC_NOTES, move low out and resolve the dangling ones 1231 */ 1232static void brcms_b_info_init(struct brcms_hardware *wlc_hw) 1233{ 1234 struct brcms_c_info *wlc = wlc_hw->wlc; 1235 1236 /* set default sw macintmask value */ 1237 wlc->defmacintmask = DEF_MACINTMASK; 1238 1239 /* various 802.11g modes */ 1240 wlc_hw->shortslot = false; 1241 1242 wlc_hw->SFBL = RETRY_SHORT_FB; 1243 wlc_hw->LFBL = RETRY_LONG_FB; 1244 1245 /* default mac retry limits */ 1246 wlc_hw->SRL = RETRY_SHORT_DEF; 1247 wlc_hw->LRL = RETRY_LONG_DEF; 1248 wlc_hw->chanspec = ch20mhz_chspec(1); 1249} 1250 1251static void brcms_b_wait_for_wake(struct brcms_hardware *wlc_hw) 1252{ 1253 /* delay before first read of ucode state */ 1254 udelay(40); 1255 1256 /* wait until ucode is no longer asleep */ 1257 SPINWAIT((brcms_b_read_shm(wlc_hw, M_UCODE_DBGST) == 1258 DBGST_ASLEEP), wlc_hw->wlc->fastpwrup_dly); 1259} 1260 1261/* control chip clock to save power, enable dynamic clock or force fast clock */ 1262static void brcms_b_clkctl_clk(struct brcms_hardware *wlc_hw, enum bcma_clkmode mode) 1263{ 1264 if (ai_get_cccaps(wlc_hw->sih) & CC_CAP_PMU) { 1265 /* new chips with PMU, CCS_FORCEHT will distribute the HT clock 1266 * on backplane, but mac core will still run on ALP(not HT) when 1267 * it enters powersave mode, which means the FCA bit may not be 1268 * set. Should wakeup mac if driver wants it to run on HT. 1269 */ 1270 1271 if (wlc_hw->clk) { 1272 if (mode == BCMA_CLKMODE_FAST) { 1273 bcma_set32(wlc_hw->d11core, 1274 D11REGOFFS(clk_ctl_st), 1275 CCS_FORCEHT); 1276 1277 udelay(64); 1278 1279 SPINWAIT( 1280 ((bcma_read32(wlc_hw->d11core, 1281 D11REGOFFS(clk_ctl_st)) & 1282 CCS_HTAVAIL) == 0), 1283 PMU_MAX_TRANSITION_DLY); 1284 WARN_ON(!(bcma_read32(wlc_hw->d11core, 1285 D11REGOFFS(clk_ctl_st)) & 1286 CCS_HTAVAIL)); 1287 } else { 1288 if ((ai_get_pmurev(wlc_hw->sih) == 0) && 1289 (bcma_read32(wlc_hw->d11core, 1290 D11REGOFFS(clk_ctl_st)) & 1291 (CCS_FORCEHT | CCS_HTAREQ))) 1292 SPINWAIT( 1293 ((bcma_read32(wlc_hw->d11core, 1294 offsetof(struct d11regs, 1295 clk_ctl_st)) & 1296 CCS_HTAVAIL) == 0), 1297 PMU_MAX_TRANSITION_DLY); 1298 bcma_mask32(wlc_hw->d11core, 1299 D11REGOFFS(clk_ctl_st), 1300 ~CCS_FORCEHT); 1301 } 1302 } 1303 wlc_hw->forcefastclk = (mode == BCMA_CLKMODE_FAST); 1304 } else { 1305 1306 /* old chips w/o PMU, force HT through cc, 1307 * then use FCA to verify mac is running fast clock 1308 */ 1309 1310 wlc_hw->forcefastclk = ai_clkctl_cc(wlc_hw->sih, mode); 1311 1312 /* check fast clock is available (if core is not in reset) */ 1313 if (wlc_hw->forcefastclk && wlc_hw->clk) 1314 WARN_ON(!(bcma_aread32(wlc_hw->d11core, BCMA_IOST) & 1315 SISF_FCLKA)); 1316 1317 /* 1318 * keep the ucode wake bit on if forcefastclk is on since we 1319 * do not want ucode to put us back to slow clock when it dozes 1320 * for PM mode. Code below matches the wake override bit with 1321 * current forcefastclk state. Only setting bit in wake_override 1322 * instead of waking ucode immediately since old code had this 1323 * behavior. Older code set wlc->forcefastclk but only had the 1324 * wake happen if the wakup_ucode work (protected by an up 1325 * check) was executed just below. 1326 */ 1327 if (wlc_hw->forcefastclk) 1328 mboolset(wlc_hw->wake_override, 1329 BRCMS_WAKE_OVERRIDE_FORCEFAST); 1330 else 1331 mboolclr(wlc_hw->wake_override, 1332 BRCMS_WAKE_OVERRIDE_FORCEFAST); 1333 } 1334} 1335 1336/* set or clear ucode host flag bits 1337 * it has an optimization for no-change write 1338 * it only writes through shared memory when the core has clock; 1339 * pre-CLK changes should use wlc_write_mhf to get around the optimization 1340 * 1341 * 1342 * bands values are: BRCM_BAND_AUTO <--- Current band only 1343 * BRCM_BAND_5G <--- 5G band only 1344 * BRCM_BAND_2G <--- 2G band only 1345 * BRCM_BAND_ALL <--- All bands 1346 */ 1347void 1348brcms_b_mhf(struct brcms_hardware *wlc_hw, u8 idx, u16 mask, u16 val, 1349 int bands) 1350{ 1351 u16 save; 1352 u16 addr[MHFMAX] = { 1353 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4, 1354 M_HOST_FLAGS5 1355 }; 1356 struct brcms_hw_band *band; 1357 1358 if ((val & ~mask) || idx >= MHFMAX) 1359 return; /* error condition */ 1360 1361 switch (bands) { 1362 /* Current band only or all bands, 1363 * then set the band to current band 1364 */ 1365 case BRCM_BAND_AUTO: 1366 case BRCM_BAND_ALL: 1367 band = wlc_hw->band; 1368 break; 1369 case BRCM_BAND_5G: 1370 band = wlc_hw->bandstate[BAND_5G_INDEX]; 1371 break; 1372 case BRCM_BAND_2G: 1373 band = wlc_hw->bandstate[BAND_2G_INDEX]; 1374 break; 1375 default: 1376 band = NULL; /* error condition */ 1377 } 1378 1379 if (band) { 1380 save = band->mhfs[idx]; 1381 band->mhfs[idx] = (band->mhfs[idx] & ~mask) | val; 1382 1383 /* optimization: only write through if changed, and 1384 * changed band is the current band 1385 */ 1386 if (wlc_hw->clk && (band->mhfs[idx] != save) 1387 && (band == wlc_hw->band)) 1388 brcms_b_write_shm(wlc_hw, addr[idx], 1389 (u16) band->mhfs[idx]); 1390 } 1391 1392 if (bands == BRCM_BAND_ALL) { 1393 wlc_hw->bandstate[0]->mhfs[idx] = 1394 (wlc_hw->bandstate[0]->mhfs[idx] & ~mask) | val; 1395 wlc_hw->bandstate[1]->mhfs[idx] = 1396 (wlc_hw->bandstate[1]->mhfs[idx] & ~mask) | val; 1397 } 1398} 1399 1400/* set the maccontrol register to desired reset state and 1401 * initialize the sw cache of the register 1402 */ 1403static void brcms_c_mctrl_reset(struct brcms_hardware *wlc_hw) 1404{ 1405 /* IHR accesses are always enabled, PSM disabled, HPS off and WAKE on */ 1406 wlc_hw->maccontrol = 0; 1407 wlc_hw->suspended_fifos = 0; 1408 wlc_hw->wake_override = 0; 1409 wlc_hw->mute_override = 0; 1410 brcms_b_mctrl(wlc_hw, ~0, MCTL_IHR_EN | MCTL_WAKE); 1411} 1412 1413/* 1414 * write the software state of maccontrol and 1415 * overrides to the maccontrol register 1416 */ 1417static void brcms_c_mctrl_write(struct brcms_hardware *wlc_hw) 1418{ 1419 u32 maccontrol = wlc_hw->maccontrol; 1420 1421 /* OR in the wake bit if overridden */ 1422 if (wlc_hw->wake_override) 1423 maccontrol |= MCTL_WAKE; 1424 1425 /* set AP and INFRA bits for mute if needed */ 1426 if (wlc_hw->mute_override) { 1427 maccontrol &= ~(MCTL_AP); 1428 maccontrol |= MCTL_INFRA; 1429 } 1430 1431 bcma_write32(wlc_hw->d11core, D11REGOFFS(maccontrol), 1432 maccontrol); 1433} 1434 1435/* set or clear maccontrol bits */ 1436void brcms_b_mctrl(struct brcms_hardware *wlc_hw, u32 mask, u32 val) 1437{ 1438 u32 maccontrol; 1439 u32 new_maccontrol; 1440 1441 if (val & ~mask) 1442 return; /* error condition */ 1443 maccontrol = wlc_hw->maccontrol; 1444 new_maccontrol = (maccontrol & ~mask) | val; 1445 1446 /* if the new maccontrol value is the same as the old, nothing to do */ 1447 if (new_maccontrol == maccontrol) 1448 return; 1449 1450 /* something changed, cache the new value */ 1451 wlc_hw->maccontrol = new_maccontrol; 1452 1453 /* write the new values with overrides applied */ 1454 brcms_c_mctrl_write(wlc_hw); 1455} 1456 1457void brcms_c_ucode_wake_override_set(struct brcms_hardware *wlc_hw, 1458 u32 override_bit) 1459{ 1460 if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE)) { 1461 mboolset(wlc_hw->wake_override, override_bit); 1462 return; 1463 } 1464 1465 mboolset(wlc_hw->wake_override, override_bit); 1466 1467 brcms_c_mctrl_write(wlc_hw); 1468 brcms_b_wait_for_wake(wlc_hw); 1469} 1470 1471void brcms_c_ucode_wake_override_clear(struct brcms_hardware *wlc_hw, 1472 u32 override_bit) 1473{ 1474 mboolclr(wlc_hw->wake_override, override_bit); 1475 1476 if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE)) 1477 return; 1478 1479 brcms_c_mctrl_write(wlc_hw); 1480} 1481 1482/* When driver needs ucode to stop beaconing, it has to make sure that 1483 * MCTL_AP is clear and MCTL_INFRA is set 1484 * Mode MCTL_AP MCTL_INFRA 1485 * AP 1 1 1486 * STA 0 1 <--- This will ensure no beacons 1487 * IBSS 0 0 1488 */ 1489static void brcms_c_ucode_mute_override_set(struct brcms_hardware *wlc_hw) 1490{ 1491 wlc_hw->mute_override = 1; 1492 1493 /* if maccontrol already has AP == 0 and INFRA == 1 without this 1494 * override, then there is no change to write 1495 */ 1496 if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA) 1497 return; 1498 1499 brcms_c_mctrl_write(wlc_hw); 1500} 1501 1502/* Clear the override on AP and INFRA bits */ 1503static void brcms_c_ucode_mute_override_clear(struct brcms_hardware *wlc_hw) 1504{ 1505 if (wlc_hw->mute_override == 0) 1506 return; 1507 1508 wlc_hw->mute_override = 0; 1509 1510 /* if maccontrol already has AP == 0 and INFRA == 1 without this 1511 * override, then there is no change to write 1512 */ 1513 if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA) 1514 return; 1515 1516 brcms_c_mctrl_write(wlc_hw); 1517} 1518 1519/* 1520 * Write a MAC address to the given match reg offset in the RXE match engine. 1521 */ 1522static void 1523brcms_b_set_addrmatch(struct brcms_hardware *wlc_hw, int match_reg_offset, 1524 const u8 *addr) 1525{ 1526 struct bcma_device *core = wlc_hw->d11core; 1527 u16 mac_l; 1528 u16 mac_m; 1529 u16 mac_h; 1530 1531 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: brcms_b_set_addrmatch\n", 1532 wlc_hw->unit); 1533 1534 mac_l = addr[0] | (addr[1] << 8); 1535 mac_m = addr[2] | (addr[3] << 8); 1536 mac_h = addr[4] | (addr[5] << 8); 1537 1538 /* enter the MAC addr into the RXE match registers */ 1539 bcma_write16(core, D11REGOFFS(rcm_ctl), 1540 RCM_INC_DATA | match_reg_offset); 1541 bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_l); 1542 bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_m); 1543 bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_h); 1544} 1545 1546void 1547brcms_b_write_template_ram(struct brcms_hardware *wlc_hw, int offset, int len, 1548 void *buf) 1549{ 1550 struct bcma_device *core = wlc_hw->d11core; 1551 u32 word; 1552 __le32 word_le; 1553 __be32 word_be; 1554 bool be_bit; 1555 brcms_dbg_info(core, "wl%d\n", wlc_hw->unit); 1556 1557 bcma_write32(core, D11REGOFFS(tplatewrptr), offset); 1558 1559 /* if MCTL_BIGEND bit set in mac control register, 1560 * the chip swaps data in fifo, as well as data in 1561 * template ram 1562 */ 1563 be_bit = (bcma_read32(core, D11REGOFFS(maccontrol)) & MCTL_BIGEND) != 0; 1564 1565 while (len > 0) { 1566 memcpy(&word, buf, sizeof(u32)); 1567 1568 if (be_bit) { 1569 word_be = cpu_to_be32(word); 1570 word = *(u32 *)&word_be; 1571 } else { 1572 word_le = cpu_to_le32(word); 1573 word = *(u32 *)&word_le; 1574 } 1575 1576 bcma_write32(core, D11REGOFFS(tplatewrdata), word); 1577 1578 buf = (u8 *) buf + sizeof(u32); 1579 len -= sizeof(u32); 1580 } 1581} 1582 1583static void brcms_b_set_cwmin(struct brcms_hardware *wlc_hw, u16 newmin) 1584{ 1585 wlc_hw->band->CWmin = newmin; 1586 1587 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr), 1588 OBJADDR_SCR_SEL | S_DOT11_CWMIN); 1589 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr)); 1590 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), newmin); 1591} 1592 1593static void brcms_b_set_cwmax(struct brcms_hardware *wlc_hw, u16 newmax) 1594{ 1595 wlc_hw->band->CWmax = newmax; 1596 1597 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr), 1598 OBJADDR_SCR_SEL | S_DOT11_CWMAX); 1599 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr)); 1600 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), newmax); 1601} 1602 1603void brcms_b_bw_set(struct brcms_hardware *wlc_hw, u16 bw) 1604{ 1605 bool fastclk; 1606 1607 /* request FAST clock if not on */ 1608 fastclk = wlc_hw->forcefastclk; 1609 if (!fastclk) 1610 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST); 1611 1612 wlc_phy_bw_state_set(wlc_hw->band->pi, bw); 1613 1614 brcms_b_phy_reset(wlc_hw); 1615 wlc_phy_init(wlc_hw->band->pi, wlc_phy_chanspec_get(wlc_hw->band->pi)); 1616 1617 /* restore the clk */ 1618 if (!fastclk) 1619 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC); 1620} 1621 1622static void brcms_b_upd_synthpu(struct brcms_hardware *wlc_hw) 1623{ 1624 u16 v; 1625 struct brcms_c_info *wlc = wlc_hw->wlc; 1626 /* update SYNTHPU_DLY */ 1627 1628 if (BRCMS_ISLCNPHY(wlc->band)) 1629 v = SYNTHPU_DLY_LPPHY_US; 1630 else if (BRCMS_ISNPHY(wlc->band) && (NREV_GE(wlc->band->phyrev, 3))) 1631 v = SYNTHPU_DLY_NPHY_US; 1632 else 1633 v = SYNTHPU_DLY_BPHY_US; 1634 1635 brcms_b_write_shm(wlc_hw, M_SYNTHPU_DLY, v); 1636} 1637 1638static void brcms_c_ucode_txant_set(struct brcms_hardware *wlc_hw) 1639{ 1640 u16 phyctl; 1641 u16 phytxant = wlc_hw->bmac_phytxant; 1642 u16 mask = PHY_TXC_ANT_MASK; 1643 1644 /* set the Probe Response frame phy control word */ 1645 phyctl = brcms_b_read_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS); 1646 phyctl = (phyctl & ~mask) | phytxant; 1647 brcms_b_write_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS, phyctl); 1648 1649 /* set the Response (ACK/CTS) frame phy control word */ 1650 phyctl = brcms_b_read_shm(wlc_hw, M_RSP_PCTLWD); 1651 phyctl = (phyctl & ~mask) | phytxant; 1652 brcms_b_write_shm(wlc_hw, M_RSP_PCTLWD, phyctl); 1653} 1654 1655static u16 brcms_b_ofdm_ratetable_offset(struct brcms_hardware *wlc_hw, 1656 u8 rate) 1657{ 1658 uint i; 1659 u8 plcp_rate = 0; 1660 struct plcp_signal_rate_lookup { 1661 u8 rate; 1662 u8 signal_rate; 1663 }; 1664 /* OFDM RATE sub-field of PLCP SIGNAL field, per 802.11 sec 17.3.4.1 */ 1665 const struct plcp_signal_rate_lookup rate_lookup[] = { 1666 {BRCM_RATE_6M, 0xB}, 1667 {BRCM_RATE_9M, 0xF}, 1668 {BRCM_RATE_12M, 0xA}, 1669 {BRCM_RATE_18M, 0xE}, 1670 {BRCM_RATE_24M, 0x9}, 1671 {BRCM_RATE_36M, 0xD}, 1672 {BRCM_RATE_48M, 0x8}, 1673 {BRCM_RATE_54M, 0xC} 1674 }; 1675 1676 for (i = 0; i < ARRAY_SIZE(rate_lookup); i++) { 1677 if (rate == rate_lookup[i].rate) { 1678 plcp_rate = rate_lookup[i].signal_rate; 1679 break; 1680 } 1681 } 1682 1683 /* Find the SHM pointer to the rate table entry by looking in the 1684 * Direct-map Table 1685 */ 1686 return 2 * brcms_b_read_shm(wlc_hw, M_RT_DIRMAP_A + (plcp_rate * 2)); 1687} 1688 1689static void brcms_upd_ofdm_pctl1_table(struct brcms_hardware *wlc_hw) 1690{ 1691 u8 rate; 1692 u8 rates[8] = { 1693 BRCM_RATE_6M, BRCM_RATE_9M, BRCM_RATE_12M, BRCM_RATE_18M, 1694 BRCM_RATE_24M, BRCM_RATE_36M, BRCM_RATE_48M, BRCM_RATE_54M 1695 }; 1696 u16 entry_ptr; 1697 u16 pctl1; 1698 uint i; 1699 1700 if (!BRCMS_PHY_11N_CAP(wlc_hw->band)) 1701 return; 1702 1703 /* walk the phy rate table and update the entries */ 1704 for (i = 0; i < ARRAY_SIZE(rates); i++) { 1705 rate = rates[i]; 1706 1707 entry_ptr = brcms_b_ofdm_ratetable_offset(wlc_hw, rate); 1708 1709 /* read the SHM Rate Table entry OFDM PCTL1 values */ 1710 pctl1 = 1711 brcms_b_read_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS); 1712 1713 /* modify the value */ 1714 pctl1 &= ~PHY_TXC1_MODE_MASK; 1715 pctl1 |= (wlc_hw->hw_stf_ss_opmode << PHY_TXC1_MODE_SHIFT); 1716 1717 /* Update the SHM Rate Table entry OFDM PCTL1 values */ 1718 brcms_b_write_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS, 1719 pctl1); 1720 } 1721} 1722 1723/* band-specific init */ 1724static void brcms_b_bsinit(struct brcms_c_info *wlc, u16 chanspec) 1725{ 1726 struct brcms_hardware *wlc_hw = wlc->hw; 1727 1728 brcms_dbg_mac80211(wlc_hw->d11core, "wl%d: bandunit %d\n", wlc_hw->unit, 1729 wlc_hw->band->bandunit); 1730 1731 brcms_c_ucode_bsinit(wlc_hw); 1732 1733 wlc_phy_init(wlc_hw->band->pi, chanspec); 1734 1735 brcms_c_ucode_txant_set(wlc_hw); 1736 1737 /* 1738 * cwmin is band-specific, update hardware 1739 * with value for current band 1740 */ 1741 brcms_b_set_cwmin(wlc_hw, wlc_hw->band->CWmin); 1742 brcms_b_set_cwmax(wlc_hw, wlc_hw->band->CWmax); 1743 1744 brcms_b_update_slot_timing(wlc_hw, 1745 wlc_hw->band->bandtype == BRCM_BAND_5G ? 1746 true : wlc_hw->shortslot); 1747 1748 /* write phytype and phyvers */ 1749 brcms_b_write_shm(wlc_hw, M_PHYTYPE, (u16) wlc_hw->band->phytype); 1750 brcms_b_write_shm(wlc_hw, M_PHYVER, (u16) wlc_hw->band->phyrev); 1751 1752 /* 1753 * initialize the txphyctl1 rate table since 1754 * shmem is shared between bands 1755 */ 1756 brcms_upd_ofdm_pctl1_table(wlc_hw); 1757 1758 brcms_b_upd_synthpu(wlc_hw); 1759} 1760 1761/* Perform a soft reset of the PHY PLL */ 1762void brcms_b_core_phypll_reset(struct brcms_hardware *wlc_hw) 1763{ 1764 ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_addr), 1765 ~0, 0); 1766 udelay(1); 1767 ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data), 1768 0x4, 0); 1769 udelay(1); 1770 ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data), 1771 0x4, 4); 1772 udelay(1); 1773 ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data), 1774 0x4, 0); 1775 udelay(1); 1776} 1777 1778/* light way to turn on phy clock without reset for NPHY only 1779 * refer to brcms_b_core_phy_clk for full version 1780 */ 1781void brcms_b_phyclk_fgc(struct brcms_hardware *wlc_hw, bool clk) 1782{ 1783 /* support(necessary for NPHY and HYPHY) only */ 1784 if (!BRCMS_ISNPHY(wlc_hw->band)) 1785 return; 1786 1787 if (ON == clk) 1788 brcms_b_core_ioctl(wlc_hw, SICF_FGC, SICF_FGC); 1789 else 1790 brcms_b_core_ioctl(wlc_hw, SICF_FGC, 0); 1791 1792} 1793 1794void brcms_b_macphyclk_set(struct brcms_hardware *wlc_hw, bool clk) 1795{ 1796 if (ON == clk) 1797 brcms_b_core_ioctl(wlc_hw, SICF_MPCLKE, SICF_MPCLKE); 1798 else 1799 brcms_b_core_ioctl(wlc_hw, SICF_MPCLKE, 0); 1800} 1801 1802void brcms_b_phy_reset(struct brcms_hardware *wlc_hw) 1803{ 1804 struct brcms_phy_pub *pih = wlc_hw->band->pi; 1805 u32 phy_bw_clkbits; 1806 bool phy_in_reset = false; 1807 1808 brcms_dbg_info(wlc_hw->d11core, "wl%d: reset phy\n", wlc_hw->unit); 1809 1810 if (pih == NULL) 1811 return; 1812 1813 phy_bw_clkbits = wlc_phy_clk_bwbits(wlc_hw->band->pi); 1814 1815 /* Specific reset sequence required for NPHY rev 3 and 4 */ 1816 if (BRCMS_ISNPHY(wlc_hw->band) && NREV_GE(wlc_hw->band->phyrev, 3) && 1817 NREV_LE(wlc_hw->band->phyrev, 4)) { 1818 /* Set the PHY bandwidth */ 1819 brcms_b_core_ioctl(wlc_hw, SICF_BWMASK, phy_bw_clkbits); 1820 1821 udelay(1); 1822 1823 /* Perform a soft reset of the PHY PLL */ 1824 brcms_b_core_phypll_reset(wlc_hw); 1825 1826 /* reset the PHY */ 1827 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_PCLKE), 1828 (SICF_PRST | SICF_PCLKE)); 1829 phy_in_reset = true; 1830 } else { 1831 brcms_b_core_ioctl(wlc_hw, 1832 (SICF_PRST | SICF_PCLKE | SICF_BWMASK), 1833 (SICF_PRST | SICF_PCLKE | phy_bw_clkbits)); 1834 } 1835 1836 udelay(2); 1837 brcms_b_core_phy_clk(wlc_hw, ON); 1838 1839 if (pih) 1840 wlc_phy_anacore(pih, ON); 1841} 1842 1843/* switch to and initialize new band */ 1844static void brcms_b_setband(struct brcms_hardware *wlc_hw, uint bandunit, 1845 u16 chanspec) { 1846 struct brcms_c_info *wlc = wlc_hw->wlc; 1847 u32 macintmask; 1848 1849 /* Enable the d11 core before accessing it */ 1850 if (!bcma_core_is_enabled(wlc_hw->d11core)) { 1851 bcma_core_enable(wlc_hw->d11core, 0); 1852 brcms_c_mctrl_reset(wlc_hw); 1853 } 1854 1855 macintmask = brcms_c_setband_inact(wlc, bandunit); 1856 1857 if (!wlc_hw->up) 1858 return; 1859 1860 brcms_b_core_phy_clk(wlc_hw, ON); 1861 1862 /* band-specific initializations */ 1863 brcms_b_bsinit(wlc, chanspec); 1864 1865 /* 1866 * If there are any pending software interrupt bits, 1867 * then replace these with a harmless nonzero value 1868 * so brcms_c_dpc() will re-enable interrupts when done. 1869 */ 1870 if (wlc->macintstatus) 1871 wlc->macintstatus = MI_DMAINT; 1872 1873 /* restore macintmask */ 1874 brcms_intrsrestore(wlc->wl, macintmask); 1875 1876 /* ucode should still be suspended.. */ 1877 WARN_ON((bcma_read32(wlc_hw->d11core, D11REGOFFS(maccontrol)) & 1878 MCTL_EN_MAC) != 0); 1879} 1880 1881static bool brcms_c_isgoodchip(struct brcms_hardware *wlc_hw) 1882{ 1883 1884 /* reject unsupported corerev */ 1885 if (!CONF_HAS(D11CONF, wlc_hw->corerev)) { 1886 wiphy_err(wlc_hw->wlc->wiphy, "unsupported core rev %d\n", 1887 wlc_hw->corerev); 1888 return false; 1889 } 1890 1891 return true; 1892} 1893 1894/* Validate some board info parameters */ 1895static bool brcms_c_validboardtype(struct brcms_hardware *wlc_hw) 1896{ 1897 uint boardrev = wlc_hw->boardrev; 1898 1899 /* 4 bits each for board type, major, minor, and tiny version */ 1900 uint brt = (boardrev & 0xf000) >> 12; 1901 uint b0 = (boardrev & 0xf00) >> 8; 1902 uint b1 = (boardrev & 0xf0) >> 4; 1903 uint b2 = boardrev & 0xf; 1904 1905 /* voards from other vendors are always considered valid */ 1906 if (ai_get_boardvendor(wlc_hw->sih) != PCI_VENDOR_ID_BROADCOM) 1907 return true; 1908 1909 /* do some boardrev sanity checks when boardvendor is Broadcom */ 1910 if (boardrev == 0) 1911 return false; 1912 1913 if (boardrev <= 0xff) 1914 return true; 1915 1916 if ((brt > 2) || (brt == 0) || (b0 > 9) || (b0 == 0) || (b1 > 9) 1917 || (b2 > 9)) 1918 return false; 1919 1920 return true; 1921} 1922 1923static void brcms_c_get_macaddr(struct brcms_hardware *wlc_hw, u8 etheraddr[ETH_ALEN]) 1924{ 1925 struct ssb_sprom *sprom = &wlc_hw->d11core->bus->sprom; 1926 1927 /* If macaddr exists, use it (Sromrev4, CIS, ...). */ 1928 if (!is_zero_ether_addr(sprom->il0mac)) { 1929 memcpy(etheraddr, sprom->il0mac, 6); 1930 return; 1931 } 1932 1933 if (wlc_hw->_nbands > 1) 1934 memcpy(etheraddr, sprom->et1mac, 6); 1935 else 1936 memcpy(etheraddr, sprom->il0mac, 6); 1937} 1938 1939/* power both the pll and external oscillator on/off */ 1940static void brcms_b_xtal(struct brcms_hardware *wlc_hw, bool want) 1941{ 1942 brcms_dbg_info(wlc_hw->d11core, "wl%d: want %d\n", wlc_hw->unit, want); 1943 1944 /* 1945 * dont power down if plldown is false or 1946 * we must poll hw radio disable 1947 */ 1948 if (!want && wlc_hw->pllreq) 1949 return; 1950 1951 wlc_hw->sbclk = want; 1952 if (!wlc_hw->sbclk) { 1953 wlc_hw->clk = false; 1954 if (wlc_hw->band && wlc_hw->band->pi) 1955 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false); 1956 } 1957} 1958 1959/* 1960 * Return true if radio is disabled, otherwise false. 1961 * hw radio disable signal is an external pin, users activate it asynchronously 1962 * this function could be called when driver is down and w/o clock 1963 * it operates on different registers depending on corerev and boardflag. 1964 */ 1965static bool brcms_b_radio_read_hwdisabled(struct brcms_hardware *wlc_hw) 1966{ 1967 bool v, clk, xtal; 1968 u32 flags = 0; 1969 1970 xtal = wlc_hw->sbclk; 1971 if (!xtal) 1972 brcms_b_xtal(wlc_hw, ON); 1973 1974 /* may need to take core out of reset first */ 1975 clk = wlc_hw->clk; 1976 if (!clk) { 1977 /* 1978 * mac no longer enables phyclk automatically when driver 1979 * accesses phyreg throughput mac. This can be skipped since 1980 * only mac reg is accessed below 1981 */ 1982 if (D11REV_GE(wlc_hw->corerev, 18)) 1983 flags |= SICF_PCLKE; 1984 1985 /* 1986 * TODO: test suspend/resume 1987 * 1988 * AI chip doesn't restore bar0win2 on 1989 * hibernation/resume, need sw fixup 1990 */ 1991 1992 bcma_core_enable(wlc_hw->d11core, flags); 1993 brcms_c_mctrl_reset(wlc_hw); 1994 } 1995 1996 v = ((bcma_read32(wlc_hw->d11core, 1997 D11REGOFFS(phydebug)) & PDBG_RFD) != 0); 1998 1999 /* put core back into reset */ 2000 if (!clk) 2001 bcma_core_disable(wlc_hw->d11core, 0); 2002 2003 if (!xtal) 2004 brcms_b_xtal(wlc_hw, OFF); 2005 2006 return v; 2007} 2008 2009static bool wlc_dma_rxreset(struct brcms_hardware *wlc_hw, uint fifo) 2010{ 2011 struct dma_pub *di = wlc_hw->di[fifo]; 2012 return dma_rxreset(di); 2013} 2014 2015/* d11 core reset 2016 * ensure fask clock during reset 2017 * reset dma 2018 * reset d11(out of reset) 2019 * reset phy(out of reset) 2020 * clear software macintstatus for fresh new start 2021 * one testing hack wlc_hw->noreset will bypass the d11/phy reset 2022 */ 2023void brcms_b_corereset(struct brcms_hardware *wlc_hw, u32 flags) 2024{ 2025 uint i; 2026 bool fastclk; 2027 2028 if (flags == BRCMS_USE_COREFLAGS) 2029 flags = (wlc_hw->band->pi ? wlc_hw->band->core_flags : 0); 2030 2031 brcms_dbg_info(wlc_hw->d11core, "wl%d: core reset\n", wlc_hw->unit); 2032 2033 /* request FAST clock if not on */ 2034 fastclk = wlc_hw->forcefastclk; 2035 if (!fastclk) 2036 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST); 2037 2038 /* reset the dma engines except first time thru */ 2039 if (bcma_core_is_enabled(wlc_hw->d11core)) { 2040 for (i = 0; i < NFIFO; i++) 2041 if ((wlc_hw->di[i]) && (!dma_txreset(wlc_hw->di[i]))) 2042 brcms_err(wlc_hw->d11core, "wl%d: %s: " 2043 "dma_txreset[%d]: cannot stop dma\n", 2044 wlc_hw->unit, __func__, i); 2045 2046 if ((wlc_hw->di[RX_FIFO]) 2047 && (!wlc_dma_rxreset(wlc_hw, RX_FIFO))) 2048 brcms_err(wlc_hw->d11core, "wl%d: %s: dma_rxreset" 2049 "[%d]: cannot stop dma\n", 2050 wlc_hw->unit, __func__, RX_FIFO); 2051 } 2052 /* if noreset, just stop the psm and return */ 2053 if (wlc_hw->noreset) { 2054 wlc_hw->wlc->macintstatus = 0; /* skip wl_dpc after down */ 2055 brcms_b_mctrl(wlc_hw, MCTL_PSM_RUN | MCTL_EN_MAC, 0); 2056 return; 2057 } 2058 2059 /* 2060 * mac no longer enables phyclk automatically when driver accesses 2061 * phyreg throughput mac, AND phy_reset is skipped at early stage when 2062 * band->pi is invalid. need to enable PHY CLK 2063 */ 2064 if (D11REV_GE(wlc_hw->corerev, 18)) 2065 flags |= SICF_PCLKE; 2066 2067 /* 2068 * reset the core 2069 * In chips with PMU, the fastclk request goes through d11 core 2070 * reg 0x1e0, which is cleared by the core_reset. have to re-request it. 2071 * 2072 * This adds some delay and we can optimize it by also requesting 2073 * fastclk through chipcommon during this period if necessary. But 2074 * that has to work coordinate with other driver like mips/arm since 2075 * they may touch chipcommon as well. 2076 */ 2077 wlc_hw->clk = false; 2078 bcma_core_enable(wlc_hw->d11core, flags); 2079 wlc_hw->clk = true; 2080 if (wlc_hw->band && wlc_hw->band->pi) 2081 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, true); 2082 2083 brcms_c_mctrl_reset(wlc_hw); 2084 2085 if (ai_get_cccaps(wlc_hw->sih) & CC_CAP_PMU) 2086 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST); 2087 2088 brcms_b_phy_reset(wlc_hw); 2089 2090 /* turn on PHY_PLL */ 2091 brcms_b_core_phypll_ctl(wlc_hw, true); 2092 2093 /* clear sw intstatus */ 2094 wlc_hw->wlc->macintstatus = 0; 2095 2096 /* restore the clk setting */ 2097 if (!fastclk) 2098 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC); 2099} 2100 2101/* txfifo sizes needs to be modified(increased) since the newer cores 2102 * have more memory. 2103 */ 2104static void brcms_b_corerev_fifofixup(struct brcms_hardware *wlc_hw) 2105{ 2106 struct bcma_device *core = wlc_hw->d11core; 2107 u16 fifo_nu; 2108 u16 txfifo_startblk = TXFIFO_START_BLK, txfifo_endblk; 2109 u16 txfifo_def, txfifo_def1; 2110 u16 txfifo_cmd; 2111 2112 /* tx fifos start at TXFIFO_START_BLK from the Base address */ 2113 txfifo_startblk = TXFIFO_START_BLK; 2114 2115 /* sequence of operations: reset fifo, set fifo size, reset fifo */ 2116 for (fifo_nu = 0; fifo_nu < NFIFO; fifo_nu++) { 2117 2118 txfifo_endblk = txfifo_startblk + wlc_hw->xmtfifo_sz[fifo_nu]; 2119 txfifo_def = (txfifo_startblk & 0xff) | 2120 (((txfifo_endblk - 1) & 0xff) << TXFIFO_FIFOTOP_SHIFT); 2121 txfifo_def1 = ((txfifo_startblk >> 8) & 0x1) | 2122 ((((txfifo_endblk - 2123 1) >> 8) & 0x1) << TXFIFO_FIFOTOP_SHIFT); 2124 txfifo_cmd = 2125 TXFIFOCMD_RESET_MASK | (fifo_nu << TXFIFOCMD_FIFOSEL_SHIFT); 2126 2127 bcma_write16(core, D11REGOFFS(xmtfifocmd), txfifo_cmd); 2128 bcma_write16(core, D11REGOFFS(xmtfifodef), txfifo_def); 2129 bcma_write16(core, D11REGOFFS(xmtfifodef1), txfifo_def1); 2130 2131 bcma_write16(core, D11REGOFFS(xmtfifocmd), txfifo_cmd); 2132 2133 txfifo_startblk += wlc_hw->xmtfifo_sz[fifo_nu]; 2134 } 2135 /* 2136 * need to propagate to shm location to be in sync since ucode/hw won't 2137 * do this 2138 */ 2139 brcms_b_write_shm(wlc_hw, M_FIFOSIZE0, 2140 wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]); 2141 brcms_b_write_shm(wlc_hw, M_FIFOSIZE1, 2142 wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]); 2143 brcms_b_write_shm(wlc_hw, M_FIFOSIZE2, 2144 ((wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO] << 8) | wlc_hw-> 2145 xmtfifo_sz[TX_AC_BK_FIFO])); 2146 brcms_b_write_shm(wlc_hw, M_FIFOSIZE3, 2147 ((wlc_hw->xmtfifo_sz[TX_ATIM_FIFO] << 8) | wlc_hw-> 2148 xmtfifo_sz[TX_BCMC_FIFO])); 2149} 2150 2151/* This function is used for changing the tsf frac register 2152 * If spur avoidance mode is off, the mac freq will be 80/120/160Mhz 2153 * If spur avoidance mode is on1, the mac freq will be 82/123/164Mhz 2154 * If spur avoidance mode is on2, the mac freq will be 84/126/168Mhz 2155 * HTPHY Formula is 2^26/freq(MHz) e.g. 2156 * For spuron2 - 126MHz -> 2^26/126 = 532610.0 2157 * - 532610 = 0x82082 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x2082 2158 * For spuron: 123MHz -> 2^26/123 = 545600.5 2159 * - 545601 = 0x85341 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x5341 2160 * For spur off: 120MHz -> 2^26/120 = 559240.5 2161 * - 559241 = 0x88889 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x8889 2162 */ 2163 2164void brcms_b_switch_macfreq(struct brcms_hardware *wlc_hw, u8 spurmode) 2165{ 2166 struct bcma_device *core = wlc_hw->d11core; 2167 2168 if ((ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM43224) || 2169 (ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM43225)) { 2170 if (spurmode == WL_SPURAVOID_ON2) { /* 126Mhz */ 2171 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x2082); 2172 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8); 2173 } else if (spurmode == WL_SPURAVOID_ON1) { /* 123Mhz */ 2174 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x5341); 2175 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8); 2176 } else { /* 120Mhz */ 2177 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x8889); 2178 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8); 2179 } 2180 } else if (BRCMS_ISLCNPHY(wlc_hw->band)) { 2181 if (spurmode == WL_SPURAVOID_ON1) { /* 82Mhz */ 2182 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x7CE0); 2183 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0xC); 2184 } else { /* 80Mhz */ 2185 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0xCCCD); 2186 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0xC); 2187 } 2188 } 2189} 2190 2191/* Initialize GPIOs that are controlled by D11 core */ 2192static void brcms_c_gpio_init(struct brcms_c_info *wlc) 2193{ 2194 struct brcms_hardware *wlc_hw = wlc->hw; 2195 u32 gc, gm; 2196 2197 /* use GPIO select 0 to get all gpio signals from the gpio out reg */ 2198 brcms_b_mctrl(wlc_hw, MCTL_GPOUT_SEL_MASK, 0); 2199 2200 /* 2201 * Common GPIO setup: 2202 * G0 = LED 0 = WLAN Activity 2203 * G1 = LED 1 = WLAN 2.4 GHz Radio State 2204 * G2 = LED 2 = WLAN 5 GHz Radio State 2205 * G4 = radio disable input (HI enabled, LO disabled) 2206 */ 2207 2208 gc = gm = 0; 2209 2210 /* Allocate GPIOs for mimo antenna diversity feature */ 2211 if (wlc_hw->antsel_type == ANTSEL_2x3) { 2212 /* Enable antenna diversity, use 2x3 mode */ 2213 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN, 2214 MHF3_ANTSEL_EN, BRCM_BAND_ALL); 2215 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE, 2216 MHF3_ANTSEL_MODE, BRCM_BAND_ALL); 2217 2218 /* init superswitch control */ 2219 wlc_phy_antsel_init(wlc_hw->band->pi, false); 2220 2221 } else if (wlc_hw->antsel_type == ANTSEL_2x4) { 2222 gm |= gc |= (BOARD_GPIO_12 | BOARD_GPIO_13); 2223 /* 2224 * The board itself is powered by these GPIOs 2225 * (when not sending pattern) so set them high 2226 */ 2227 bcma_set16(wlc_hw->d11core, D11REGOFFS(psm_gpio_oe), 2228 (BOARD_GPIO_12 | BOARD_GPIO_13)); 2229 bcma_set16(wlc_hw->d11core, D11REGOFFS(psm_gpio_out), 2230 (BOARD_GPIO_12 | BOARD_GPIO_13)); 2231 2232 /* Enable antenna diversity, use 2x4 mode */ 2233 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN, 2234 MHF3_ANTSEL_EN, BRCM_BAND_ALL); 2235 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE, 0, 2236 BRCM_BAND_ALL); 2237 2238 /* Configure the desired clock to be 4Mhz */ 2239 brcms_b_write_shm(wlc_hw, M_ANTSEL_CLKDIV, 2240 ANTSEL_CLKDIV_4MHZ); 2241 } 2242 2243 /* 2244 * gpio 9 controls the PA. ucode is responsible 2245 * for wiggling out and oe 2246 */ 2247 if (wlc_hw->boardflags & BFL_PACTRL) 2248 gm |= gc |= BOARD_GPIO_PACTRL; 2249 2250 /* apply to gpiocontrol register */ 2251 bcma_chipco_gpio_control(&wlc_hw->d11core->bus->drv_cc, gm, gc); 2252} 2253 2254static void brcms_ucode_write(struct brcms_hardware *wlc_hw, 2255 const __le32 ucode[], const size_t nbytes) 2256{ 2257 struct bcma_device *core = wlc_hw->d11core; 2258 uint i; 2259 uint count; 2260 2261 brcms_dbg_info(wlc_hw->d11core, "wl%d\n", wlc_hw->unit); 2262 2263 count = (nbytes / sizeof(u32)); 2264 2265 bcma_write32(core, D11REGOFFS(objaddr), 2266 OBJADDR_AUTO_INC | OBJADDR_UCM_SEL); 2267 (void)bcma_read32(core, D11REGOFFS(objaddr)); 2268 for (i = 0; i < count; i++) 2269 bcma_write32(core, D11REGOFFS(objdata), le32_to_cpu(ucode[i])); 2270 2271} 2272 2273static void brcms_ucode_download(struct brcms_hardware *wlc_hw) 2274{ 2275 struct brcms_c_info *wlc; 2276 struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode; 2277 2278 wlc = wlc_hw->wlc; 2279 2280 if (wlc_hw->ucode_loaded) 2281 return; 2282 2283 if (D11REV_IS(wlc_hw->corerev, 23)) { 2284 if (BRCMS_ISNPHY(wlc_hw->band)) { 2285 brcms_ucode_write(wlc_hw, ucode->bcm43xx_16_mimo, 2286 ucode->bcm43xx_16_mimosz); 2287 wlc_hw->ucode_loaded = true; 2288 } else 2289 brcms_err(wlc_hw->d11core, 2290 "%s: wl%d: unsupported phy in corerev %d\n", 2291 __func__, wlc_hw->unit, wlc_hw->corerev); 2292 } else if (D11REV_IS(wlc_hw->corerev, 24)) { 2293 if (BRCMS_ISLCNPHY(wlc_hw->band)) { 2294 brcms_ucode_write(wlc_hw, ucode->bcm43xx_24_lcn, 2295 ucode->bcm43xx_24_lcnsz); 2296 wlc_hw->ucode_loaded = true; 2297 } else { 2298 brcms_err(wlc_hw->d11core, 2299 "%s: wl%d: unsupported phy in corerev %d\n", 2300 __func__, wlc_hw->unit, wlc_hw->corerev); 2301 } 2302 } 2303} 2304 2305void brcms_b_txant_set(struct brcms_hardware *wlc_hw, u16 phytxant) 2306{ 2307 /* update sw state */ 2308 wlc_hw->bmac_phytxant = phytxant; 2309 2310 /* push to ucode if up */ 2311 if (!wlc_hw->up) 2312 return; 2313 brcms_c_ucode_txant_set(wlc_hw); 2314 2315} 2316 2317u16 brcms_b_get_txant(struct brcms_hardware *wlc_hw) 2318{ 2319 return (u16) wlc_hw->wlc->stf->txant; 2320} 2321 2322void brcms_b_antsel_type_set(struct brcms_hardware *wlc_hw, u8 antsel_type) 2323{ 2324 wlc_hw->antsel_type = antsel_type; 2325 2326 /* Update the antsel type for phy module to use */ 2327 wlc_phy_antsel_type_set(wlc_hw->band->pi, antsel_type); 2328} 2329 2330static void brcms_b_fifoerrors(struct brcms_hardware *wlc_hw) 2331{ 2332 bool fatal = false; 2333 uint unit; 2334 uint intstatus, idx; 2335 struct bcma_device *core = wlc_hw->d11core; 2336 2337 unit = wlc_hw->unit; 2338 2339 for (idx = 0; idx < NFIFO; idx++) { 2340 /* read intstatus register and ignore any non-error bits */ 2341 intstatus = 2342 bcma_read32(core, 2343 D11REGOFFS(intctrlregs[idx].intstatus)) & 2344 I_ERRORS; 2345 if (!intstatus) 2346 continue; 2347 2348 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: intstatus%d 0x%x\n", 2349 unit, idx, intstatus); 2350 2351 if (intstatus & I_RO) { 2352 brcms_err(core, "wl%d: fifo %d: receive fifo " 2353 "overflow\n", unit, idx); 2354 fatal = true; 2355 } 2356 2357 if (intstatus & I_PC) { 2358 brcms_err(core, "wl%d: fifo %d: descriptor error\n", 2359 unit, idx); 2360 fatal = true; 2361 } 2362 2363 if (intstatus & I_PD) { 2364 brcms_err(core, "wl%d: fifo %d: data error\n", unit, 2365 idx); 2366 fatal = true; 2367 } 2368 2369 if (intstatus & I_DE) { 2370 brcms_err(core, "wl%d: fifo %d: descriptor protocol " 2371 "error\n", unit, idx); 2372 fatal = true; 2373 } 2374 2375 if (intstatus & I_RU) 2376 brcms_err(core, "wl%d: fifo %d: receive descriptor " 2377 "underflow\n", idx, unit); 2378 2379 if (intstatus & I_XU) { 2380 brcms_err(core, "wl%d: fifo %d: transmit fifo " 2381 "underflow\n", idx, unit); 2382 fatal = true; 2383 } 2384 2385 if (fatal) { 2386 brcms_fatal_error(wlc_hw->wlc->wl); /* big hammer */ 2387 break; 2388 } else 2389 bcma_write32(core, 2390 D11REGOFFS(intctrlregs[idx].intstatus), 2391 intstatus); 2392 } 2393} 2394 2395void brcms_c_intrson(struct brcms_c_info *wlc) 2396{ 2397 struct brcms_hardware *wlc_hw = wlc->hw; 2398 wlc->macintmask = wlc->defmacintmask; 2399 bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), wlc->macintmask); 2400} 2401 2402u32 brcms_c_intrsoff(struct brcms_c_info *wlc) 2403{ 2404 struct brcms_hardware *wlc_hw = wlc->hw; 2405 u32 macintmask; 2406 2407 if (!wlc_hw->clk) 2408 return 0; 2409 2410 macintmask = wlc->macintmask; /* isr can still happen */ 2411 2412 bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), 0); 2413 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(macintmask)); 2414 udelay(1); /* ensure int line is no longer driven */ 2415 wlc->macintmask = 0; 2416 2417 /* return previous macintmask; resolve race between us and our isr */ 2418 return wlc->macintstatus ? 0 : macintmask; 2419} 2420 2421void brcms_c_intrsrestore(struct brcms_c_info *wlc, u32 macintmask) 2422{ 2423 struct brcms_hardware *wlc_hw = wlc->hw; 2424 if (!wlc_hw->clk) 2425 return; 2426 2427 wlc->macintmask = macintmask; 2428 bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), wlc->macintmask); 2429} 2430 2431/* assumes that the d11 MAC is enabled */ 2432static void brcms_b_tx_fifo_suspend(struct brcms_hardware *wlc_hw, 2433 uint tx_fifo) 2434{ 2435 u8 fifo = 1 << tx_fifo; 2436 2437 /* Two clients of this code, 11h Quiet period and scanning. */ 2438 2439 /* only suspend if not already suspended */ 2440 if ((wlc_hw->suspended_fifos & fifo) == fifo) 2441 return; 2442 2443 /* force the core awake only if not already */ 2444 if (wlc_hw->suspended_fifos == 0) 2445 brcms_c_ucode_wake_override_set(wlc_hw, 2446 BRCMS_WAKE_OVERRIDE_TXFIFO); 2447 2448 wlc_hw->suspended_fifos |= fifo; 2449 2450 if (wlc_hw->di[tx_fifo]) { 2451 /* 2452 * Suspending AMPDU transmissions in the middle can cause 2453 * underflow which may result in mismatch between ucode and 2454 * driver so suspend the mac before suspending the FIFO 2455 */ 2456 if (BRCMS_PHY_11N_CAP(wlc_hw->band)) 2457 brcms_c_suspend_mac_and_wait(wlc_hw->wlc); 2458 2459 dma_txsuspend(wlc_hw->di[tx_fifo]); 2460 2461 if (BRCMS_PHY_11N_CAP(wlc_hw->band)) 2462 brcms_c_enable_mac(wlc_hw->wlc); 2463 } 2464} 2465 2466static void brcms_b_tx_fifo_resume(struct brcms_hardware *wlc_hw, 2467 uint tx_fifo) 2468{ 2469 /* BMAC_NOTE: BRCMS_TX_FIFO_ENAB is done in brcms_c_dpc() for DMA case 2470 * but need to be done here for PIO otherwise the watchdog will catch 2471 * the inconsistency and fire 2472 */ 2473 /* Two clients of this code, 11h Quiet period and scanning. */ 2474 if (wlc_hw->di[tx_fifo]) 2475 dma_txresume(wlc_hw->di[tx_fifo]); 2476 2477 /* allow core to sleep again */ 2478 if (wlc_hw->suspended_fifos == 0) 2479 return; 2480 else { 2481 wlc_hw->suspended_fifos &= ~(1 << tx_fifo); 2482 if (wlc_hw->suspended_fifos == 0) 2483 brcms_c_ucode_wake_override_clear(wlc_hw, 2484 BRCMS_WAKE_OVERRIDE_TXFIFO); 2485 } 2486} 2487 2488/* precondition: requires the mac core to be enabled */ 2489static void brcms_b_mute(struct brcms_hardware *wlc_hw, bool mute_tx) 2490{ 2491 static const u8 null_ether_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0}; 2492 2493 if (mute_tx) { 2494 /* suspend tx fifos */ 2495 brcms_b_tx_fifo_suspend(wlc_hw, TX_DATA_FIFO); 2496 brcms_b_tx_fifo_suspend(wlc_hw, TX_CTL_FIFO); 2497 brcms_b_tx_fifo_suspend(wlc_hw, TX_AC_BK_FIFO); 2498 brcms_b_tx_fifo_suspend(wlc_hw, TX_AC_VI_FIFO); 2499 2500 /* zero the address match register so we do not send ACKs */ 2501 brcms_b_set_addrmatch(wlc_hw, RCM_MAC_OFFSET, 2502 null_ether_addr); 2503 } else { 2504 /* resume tx fifos */ 2505 brcms_b_tx_fifo_resume(wlc_hw, TX_DATA_FIFO); 2506 brcms_b_tx_fifo_resume(wlc_hw, TX_CTL_FIFO); 2507 brcms_b_tx_fifo_resume(wlc_hw, TX_AC_BK_FIFO); 2508 brcms_b_tx_fifo_resume(wlc_hw, TX_AC_VI_FIFO); 2509 2510 /* Restore address */ 2511 brcms_b_set_addrmatch(wlc_hw, RCM_MAC_OFFSET, 2512 wlc_hw->etheraddr); 2513 } 2514 2515 wlc_phy_mute_upd(wlc_hw->band->pi, mute_tx, 0); 2516 2517 if (mute_tx) 2518 brcms_c_ucode_mute_override_set(wlc_hw); 2519 else 2520 brcms_c_ucode_mute_override_clear(wlc_hw); 2521} 2522 2523void 2524brcms_c_mute(struct brcms_c_info *wlc, bool mute_tx) 2525{ 2526 brcms_b_mute(wlc->hw, mute_tx); 2527} 2528 2529/* 2530 * Read and clear macintmask and macintstatus and intstatus registers. 2531 * This routine should be called with interrupts off 2532 * Return: 2533 * -1 if brcms_deviceremoved(wlc) evaluates to true; 2534 * 0 if the interrupt is not for us, or we are in some special cases; 2535 * device interrupt status bits otherwise. 2536 */ 2537static inline u32 wlc_intstatus(struct brcms_c_info *wlc, bool in_isr) 2538{ 2539 struct brcms_hardware *wlc_hw = wlc->hw; 2540 struct bcma_device *core = wlc_hw->d11core; 2541 u32 macintstatus; 2542 2543 /* macintstatus includes a DMA interrupt summary bit */ 2544 macintstatus = bcma_read32(core, D11REGOFFS(macintstatus)); 2545 2546 BCMMSG(wlc->wiphy, "wl%d: macintstatus: 0x%x\n", wlc_hw->unit, 2547 macintstatus); 2548 2549 /* detect cardbus removed, in power down(suspend) and in reset */ 2550 if (brcms_deviceremoved(wlc)) 2551 return -1; 2552 2553 /* brcms_deviceremoved() succeeds even when the core is still resetting, 2554 * handle that case here. 2555 */ 2556 if (macintstatus == 0xffffffff) 2557 return 0; 2558 2559 /* defer unsolicited interrupts */ 2560 macintstatus &= (in_isr ? wlc->macintmask : wlc->defmacintmask); 2561 2562 /* if not for us */ 2563 if (macintstatus == 0) 2564 return 0; 2565 2566 /* interrupts are already turned off for CFE build 2567 * Caution: For CFE Turning off the interrupts again has some undesired 2568 * consequences 2569 */ 2570 /* turn off the interrupts */ 2571 bcma_write32(core, D11REGOFFS(macintmask), 0); 2572 (void)bcma_read32(core, D11REGOFFS(macintmask)); 2573 wlc->macintmask = 0; 2574 2575 /* clear device interrupts */ 2576 bcma_write32(core, D11REGOFFS(macintstatus), macintstatus); 2577 2578 /* MI_DMAINT is indication of non-zero intstatus */ 2579 if (macintstatus & MI_DMAINT) 2580 /* 2581 * only fifo interrupt enabled is I_RI in 2582 * RX_FIFO. If MI_DMAINT is set, assume it 2583 * is set and clear the interrupt. 2584 */ 2585 bcma_write32(core, D11REGOFFS(intctrlregs[RX_FIFO].intstatus), 2586 DEF_RXINTMASK); 2587 2588 return macintstatus; 2589} 2590 2591/* Update wlc->macintstatus and wlc->intstatus[]. */ 2592/* Return true if they are updated successfully. false otherwise */ 2593bool brcms_c_intrsupd(struct brcms_c_info *wlc) 2594{ 2595 u32 macintstatus; 2596 2597 /* read and clear macintstatus and intstatus registers */ 2598 macintstatus = wlc_intstatus(wlc, false); 2599 2600 /* device is removed */ 2601 if (macintstatus == 0xffffffff) 2602 return false; 2603 2604 /* update interrupt status in software */ 2605 wlc->macintstatus |= macintstatus; 2606 2607 return true; 2608} 2609 2610/* 2611 * First-level interrupt processing. 2612 * Return true if this was our interrupt, false otherwise. 2613 * *wantdpc will be set to true if further brcms_c_dpc() processing is required, 2614 * false otherwise. 2615 */ 2616bool brcms_c_isr(struct brcms_c_info *wlc, bool *wantdpc) 2617{ 2618 struct brcms_hardware *wlc_hw = wlc->hw; 2619 u32 macintstatus; 2620 2621 *wantdpc = false; 2622 2623 if (!wlc_hw->up || !wlc->macintmask) 2624 return false; 2625 2626 /* read and clear macintstatus and intstatus registers */ 2627 macintstatus = wlc_intstatus(wlc, true); 2628 2629 if (macintstatus == 0xffffffff) 2630 brcms_err(wlc_hw->d11core, 2631 "DEVICEREMOVED detected in the ISR code path\n"); 2632 2633 /* it is not for us */ 2634 if (macintstatus == 0) 2635 return false; 2636 2637 *wantdpc = true; 2638 2639 /* save interrupt status bits */ 2640 wlc->macintstatus = macintstatus; 2641 2642 return true; 2643 2644} 2645 2646void brcms_c_suspend_mac_and_wait(struct brcms_c_info *wlc) 2647{ 2648 struct brcms_hardware *wlc_hw = wlc->hw; 2649 struct bcma_device *core = wlc_hw->d11core; 2650 u32 mc, mi; 2651 2652 brcms_dbg_mac80211(core, "wl%d: bandunit %d\n", wlc_hw->unit, 2653 wlc_hw->band->bandunit); 2654 2655 /* 2656 * Track overlapping suspend requests 2657 */ 2658 wlc_hw->mac_suspend_depth++; 2659 if (wlc_hw->mac_suspend_depth > 1) 2660 return; 2661 2662 /* force the core awake */ 2663 brcms_c_ucode_wake_override_set(wlc_hw, BRCMS_WAKE_OVERRIDE_MACSUSPEND); 2664 2665 mc = bcma_read32(core, D11REGOFFS(maccontrol)); 2666 2667 if (mc == 0xffffffff) { 2668 brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit, 2669 __func__); 2670 brcms_down(wlc->wl); 2671 return; 2672 } 2673 WARN_ON(mc & MCTL_PSM_JMP_0); 2674 WARN_ON(!(mc & MCTL_PSM_RUN)); 2675 WARN_ON(!(mc & MCTL_EN_MAC)); 2676 2677 mi = bcma_read32(core, D11REGOFFS(macintstatus)); 2678 if (mi == 0xffffffff) { 2679 brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit, 2680 __func__); 2681 brcms_down(wlc->wl); 2682 return; 2683 } 2684 WARN_ON(mi & MI_MACSSPNDD); 2685 2686 brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, 0); 2687 2688 SPINWAIT(!(bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD), 2689 BRCMS_MAX_MAC_SUSPEND); 2690 2691 if (!(bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD)) { 2692 brcms_err(core, "wl%d: wlc_suspend_mac_and_wait: waited %d uS" 2693 " and MI_MACSSPNDD is still not on.\n", 2694 wlc_hw->unit, BRCMS_MAX_MAC_SUSPEND); 2695 brcms_err(core, "wl%d: psmdebug 0x%08x, phydebug 0x%08x, " 2696 "psm_brc 0x%04x\n", wlc_hw->unit, 2697 bcma_read32(core, D11REGOFFS(psmdebug)), 2698 bcma_read32(core, D11REGOFFS(phydebug)), 2699 bcma_read16(core, D11REGOFFS(psm_brc))); 2700 } 2701 2702 mc = bcma_read32(core, D11REGOFFS(maccontrol)); 2703 if (mc == 0xffffffff) { 2704 brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit, 2705 __func__); 2706 brcms_down(wlc->wl); 2707 return; 2708 } 2709 WARN_ON(mc & MCTL_PSM_JMP_0); 2710 WARN_ON(!(mc & MCTL_PSM_RUN)); 2711 WARN_ON(mc & MCTL_EN_MAC); 2712} 2713 2714void brcms_c_enable_mac(struct brcms_c_info *wlc) 2715{ 2716 struct brcms_hardware *wlc_hw = wlc->hw; 2717 struct bcma_device *core = wlc_hw->d11core; 2718 u32 mc, mi; 2719 2720 brcms_dbg_mac80211(core, "wl%d: bandunit %d\n", wlc_hw->unit, 2721 wlc->band->bandunit); 2722 2723 /* 2724 * Track overlapping suspend requests 2725 */ 2726 wlc_hw->mac_suspend_depth--; 2727 if (wlc_hw->mac_suspend_depth > 0) 2728 return; 2729 2730 mc = bcma_read32(core, D11REGOFFS(maccontrol)); 2731 WARN_ON(mc & MCTL_PSM_JMP_0); 2732 WARN_ON(mc & MCTL_EN_MAC); 2733 WARN_ON(!(mc & MCTL_PSM_RUN)); 2734 2735 brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, MCTL_EN_MAC); 2736 bcma_write32(core, D11REGOFFS(macintstatus), MI_MACSSPNDD); 2737 2738 mc = bcma_read32(core, D11REGOFFS(maccontrol)); 2739 WARN_ON(mc & MCTL_PSM_JMP_0); 2740 WARN_ON(!(mc & MCTL_EN_MAC)); 2741 WARN_ON(!(mc & MCTL_PSM_RUN)); 2742 2743 mi = bcma_read32(core, D11REGOFFS(macintstatus)); 2744 WARN_ON(mi & MI_MACSSPNDD); 2745 2746 brcms_c_ucode_wake_override_clear(wlc_hw, 2747 BRCMS_WAKE_OVERRIDE_MACSUSPEND); 2748} 2749 2750void brcms_b_band_stf_ss_set(struct brcms_hardware *wlc_hw, u8 stf_mode) 2751{ 2752 wlc_hw->hw_stf_ss_opmode = stf_mode; 2753 2754 if (wlc_hw->clk) 2755 brcms_upd_ofdm_pctl1_table(wlc_hw); 2756} 2757 2758static bool brcms_b_validate_chip_access(struct brcms_hardware *wlc_hw) 2759{ 2760 struct bcma_device *core = wlc_hw->d11core; 2761 u32 w, val; 2762 struct wiphy *wiphy = wlc_hw->wlc->wiphy; 2763 2764 /* Validate dchip register access */ 2765 2766 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0); 2767 (void)bcma_read32(core, D11REGOFFS(objaddr)); 2768 w = bcma_read32(core, D11REGOFFS(objdata)); 2769 2770 /* Can we write and read back a 32bit register? */ 2771 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0); 2772 (void)bcma_read32(core, D11REGOFFS(objaddr)); 2773 bcma_write32(core, D11REGOFFS(objdata), (u32) 0xaa5555aa); 2774 2775 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0); 2776 (void)bcma_read32(core, D11REGOFFS(objaddr)); 2777 val = bcma_read32(core, D11REGOFFS(objdata)); 2778 if (val != (u32) 0xaa5555aa) { 2779 wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, " 2780 "expected 0xaa5555aa\n", wlc_hw->unit, val); 2781 return false; 2782 } 2783 2784 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0); 2785 (void)bcma_read32(core, D11REGOFFS(objaddr)); 2786 bcma_write32(core, D11REGOFFS(objdata), (u32) 0x55aaaa55); 2787 2788 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0); 2789 (void)bcma_read32(core, D11REGOFFS(objaddr)); 2790 val = bcma_read32(core, D11REGOFFS(objdata)); 2791 if (val != (u32) 0x55aaaa55) { 2792 wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, " 2793 "expected 0x55aaaa55\n", wlc_hw->unit, val); 2794 return false; 2795 } 2796 2797 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0); 2798 (void)bcma_read32(core, D11REGOFFS(objaddr)); 2799 bcma_write32(core, D11REGOFFS(objdata), w); 2800 2801 /* clear CFPStart */ 2802 bcma_write32(core, D11REGOFFS(tsf_cfpstart), 0); 2803 2804 w = bcma_read32(core, D11REGOFFS(maccontrol)); 2805 if ((w != (MCTL_IHR_EN | MCTL_WAKE)) && 2806 (w != (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE))) { 2807 wiphy_err(wiphy, "wl%d: validate_chip_access: maccontrol = " 2808 "0x%x, expected 0x%x or 0x%x\n", wlc_hw->unit, w, 2809 (MCTL_IHR_EN | MCTL_WAKE), 2810 (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE)); 2811 return false; 2812 } 2813 2814 return true; 2815} 2816 2817#define PHYPLL_WAIT_US 100000 2818 2819void brcms_b_core_phypll_ctl(struct brcms_hardware *wlc_hw, bool on) 2820{ 2821 struct bcma_device *core = wlc_hw->d11core; 2822 u32 tmp; 2823 2824 brcms_dbg_info(core, "wl%d\n", wlc_hw->unit); 2825 2826 tmp = 0; 2827 2828 if (on) { 2829 if ((ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM4313)) { 2830 bcma_set32(core, D11REGOFFS(clk_ctl_st), 2831 CCS_ERSRC_REQ_HT | 2832 CCS_ERSRC_REQ_D11PLL | 2833 CCS_ERSRC_REQ_PHYPLL); 2834 SPINWAIT((bcma_read32(core, D11REGOFFS(clk_ctl_st)) & 2835 CCS_ERSRC_AVAIL_HT) != CCS_ERSRC_AVAIL_HT, 2836 PHYPLL_WAIT_US); 2837 2838 tmp = bcma_read32(core, D11REGOFFS(clk_ctl_st)); 2839 if ((tmp & CCS_ERSRC_AVAIL_HT) != CCS_ERSRC_AVAIL_HT) 2840 brcms_err(core, "%s: turn on PHY PLL failed\n", 2841 __func__); 2842 } else { 2843 bcma_set32(core, D11REGOFFS(clk_ctl_st), 2844 tmp | CCS_ERSRC_REQ_D11PLL | 2845 CCS_ERSRC_REQ_PHYPLL); 2846 SPINWAIT((bcma_read32(core, D11REGOFFS(clk_ctl_st)) & 2847 (CCS_ERSRC_AVAIL_D11PLL | 2848 CCS_ERSRC_AVAIL_PHYPLL)) != 2849 (CCS_ERSRC_AVAIL_D11PLL | 2850 CCS_ERSRC_AVAIL_PHYPLL), PHYPLL_WAIT_US); 2851 2852 tmp = bcma_read32(core, D11REGOFFS(clk_ctl_st)); 2853 if ((tmp & 2854 (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL)) 2855 != 2856 (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL)) 2857 brcms_err(core, "%s: turn on PHY PLL failed\n", 2858 __func__); 2859 } 2860 } else { 2861 /* 2862 * Since the PLL may be shared, other cores can still 2863 * be requesting it; so we'll deassert the request but 2864 * not wait for status to comply. 2865 */ 2866 bcma_mask32(core, D11REGOFFS(clk_ctl_st), 2867 ~CCS_ERSRC_REQ_PHYPLL); 2868 (void)bcma_read32(core, D11REGOFFS(clk_ctl_st)); 2869 } 2870} 2871 2872static void brcms_c_coredisable(struct brcms_hardware *wlc_hw) 2873{ 2874 bool dev_gone; 2875 2876 brcms_dbg_info(wlc_hw->d11core, "wl%d: disable core\n", wlc_hw->unit); 2877 2878 dev_gone = brcms_deviceremoved(wlc_hw->wlc); 2879 2880 if (dev_gone) 2881 return; 2882 2883 if (wlc_hw->noreset) 2884 return; 2885 2886 /* radio off */ 2887 wlc_phy_switch_radio(wlc_hw->band->pi, OFF); 2888 2889 /* turn off analog core */ 2890 wlc_phy_anacore(wlc_hw->band->pi, OFF); 2891 2892 /* turn off PHYPLL to save power */ 2893 brcms_b_core_phypll_ctl(wlc_hw, false); 2894 2895 wlc_hw->clk = false; 2896 bcma_core_disable(wlc_hw->d11core, 0); 2897 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false); 2898} 2899 2900static void brcms_c_flushqueues(struct brcms_c_info *wlc) 2901{ 2902 struct brcms_hardware *wlc_hw = wlc->hw; 2903 uint i; 2904 2905 /* free any posted tx packets */ 2906 for (i = 0; i < NFIFO; i++) { 2907 if (wlc_hw->di[i]) { 2908 dma_txreclaim(wlc_hw->di[i], DMA_RANGE_ALL); 2909 if (i < TX_BCMC_FIFO) 2910 ieee80211_wake_queue(wlc->pub->ieee_hw, 2911 brcms_fifo_to_ac(i)); 2912 } 2913 } 2914 2915 /* free any posted rx packets */ 2916 dma_rxreclaim(wlc_hw->di[RX_FIFO]); 2917} 2918 2919static u16 2920brcms_b_read_objmem(struct brcms_hardware *wlc_hw, uint offset, u32 sel) 2921{ 2922 struct bcma_device *core = wlc_hw->d11core; 2923 u16 objoff = D11REGOFFS(objdata); 2924 2925 bcma_write32(core, D11REGOFFS(objaddr), sel | (offset >> 2)); 2926 (void)bcma_read32(core, D11REGOFFS(objaddr)); 2927 if (offset & 2) 2928 objoff += 2; 2929 2930 return bcma_read16(core, objoff); 2931} 2932 2933static void 2934brcms_b_write_objmem(struct brcms_hardware *wlc_hw, uint offset, u16 v, 2935 u32 sel) 2936{ 2937 struct bcma_device *core = wlc_hw->d11core; 2938 u16 objoff = D11REGOFFS(objdata); 2939 2940 bcma_write32(core, D11REGOFFS(objaddr), sel | (offset >> 2)); 2941 (void)bcma_read32(core, D11REGOFFS(objaddr)); 2942 if (offset & 2) 2943 objoff += 2; 2944 2945 bcma_write16(core, objoff, v); 2946} 2947 2948/* 2949 * Read a single u16 from shared memory. 2950 * SHM 'offset' needs to be an even address 2951 */ 2952u16 brcms_b_read_shm(struct brcms_hardware *wlc_hw, uint offset) 2953{ 2954 return brcms_b_read_objmem(wlc_hw, offset, OBJADDR_SHM_SEL); 2955} 2956 2957/* 2958 * Write a single u16 to shared memory. 2959 * SHM 'offset' needs to be an even address 2960 */ 2961void brcms_b_write_shm(struct brcms_hardware *wlc_hw, uint offset, u16 v) 2962{ 2963 brcms_b_write_objmem(wlc_hw, offset, v, OBJADDR_SHM_SEL); 2964} 2965 2966/* 2967 * Copy a buffer to shared memory of specified type . 2968 * SHM 'offset' needs to be an even address and 2969 * Buffer length 'len' must be an even number of bytes 2970 * 'sel' selects the type of memory 2971 */ 2972void 2973brcms_b_copyto_objmem(struct brcms_hardware *wlc_hw, uint offset, 2974 const void *buf, int len, u32 sel) 2975{ 2976 u16 v; 2977 const u8 *p = (const u8 *)buf; 2978 int i; 2979 2980 if (len <= 0 || (offset & 1) || (len & 1)) 2981 return; 2982 2983 for (i = 0; i < len; i += 2) { 2984 v = p[i] | (p[i + 1] << 8); 2985 brcms_b_write_objmem(wlc_hw, offset + i, v, sel); 2986 } 2987} 2988 2989/* 2990 * Copy a piece of shared memory of specified type to a buffer . 2991 * SHM 'offset' needs to be an even address and 2992 * Buffer length 'len' must be an even number of bytes 2993 * 'sel' selects the type of memory 2994 */ 2995void 2996brcms_b_copyfrom_objmem(struct brcms_hardware *wlc_hw, uint offset, void *buf, 2997 int len, u32 sel) 2998{ 2999 u16 v; 3000 u8 *p = (u8 *) buf; 3001 int i; 3002 3003 if (len <= 0 || (offset & 1) || (len & 1)) 3004 return; 3005 3006 for (i = 0; i < len; i += 2) { 3007 v = brcms_b_read_objmem(wlc_hw, offset + i, sel); 3008 p[i] = v & 0xFF; 3009 p[i + 1] = (v >> 8) & 0xFF; 3010 } 3011} 3012 3013/* Copy a buffer to shared memory. 3014 * SHM 'offset' needs to be an even address and 3015 * Buffer length 'len' must be an even number of bytes 3016 */ 3017static void brcms_c_copyto_shm(struct brcms_c_info *wlc, uint offset, 3018 const void *buf, int len) 3019{ 3020 brcms_b_copyto_objmem(wlc->hw, offset, buf, len, OBJADDR_SHM_SEL); 3021} 3022 3023static void brcms_b_retrylimit_upd(struct brcms_hardware *wlc_hw, 3024 u16 SRL, u16 LRL) 3025{ 3026 wlc_hw->SRL = SRL; 3027 wlc_hw->LRL = LRL; 3028 3029 /* write retry limit to SCR, shouldn't need to suspend */ 3030 if (wlc_hw->up) { 3031 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr), 3032 OBJADDR_SCR_SEL | S_DOT11_SRC_LMT); 3033 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr)); 3034 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), wlc_hw->SRL); 3035 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr), 3036 OBJADDR_SCR_SEL | S_DOT11_LRC_LMT); 3037 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr)); 3038 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), wlc_hw->LRL); 3039 } 3040} 3041 3042static void brcms_b_pllreq(struct brcms_hardware *wlc_hw, bool set, u32 req_bit) 3043{ 3044 if (set) { 3045 if (mboolisset(wlc_hw->pllreq, req_bit)) 3046 return; 3047 3048 mboolset(wlc_hw->pllreq, req_bit); 3049 3050 if (mboolisset(wlc_hw->pllreq, BRCMS_PLLREQ_FLIP)) { 3051 if (!wlc_hw->sbclk) 3052 brcms_b_xtal(wlc_hw, ON); 3053 } 3054 } else { 3055 if (!mboolisset(wlc_hw->pllreq, req_bit)) 3056 return; 3057 3058 mboolclr(wlc_hw->pllreq, req_bit); 3059 3060 if (mboolisset(wlc_hw->pllreq, BRCMS_PLLREQ_FLIP)) { 3061 if (wlc_hw->sbclk) 3062 brcms_b_xtal(wlc_hw, OFF); 3063 } 3064 } 3065} 3066 3067static void brcms_b_antsel_set(struct brcms_hardware *wlc_hw, u32 antsel_avail) 3068{ 3069 wlc_hw->antsel_avail = antsel_avail; 3070} 3071 3072/* 3073 * conditions under which the PM bit should be set in outgoing frames 3074 * and STAY_AWAKE is meaningful 3075 */ 3076static bool brcms_c_ps_allowed(struct brcms_c_info *wlc) 3077{ 3078 struct brcms_bss_cfg *cfg = wlc->bsscfg; 3079 3080 /* disallow PS when one of the following global conditions meets */ 3081 if (!wlc->pub->associated) 3082 return false; 3083 3084 /* disallow PS when one of these meets when not scanning */ 3085 if (wlc->filter_flags & FIF_PROMISC_IN_BSS) 3086 return false; 3087 3088 if (cfg->associated) { 3089 /* 3090 * disallow PS when one of the following 3091 * bsscfg specific conditions meets 3092 */ 3093 if (!cfg->BSS) 3094 return false; 3095 3096 return false; 3097 } 3098 3099 return true; 3100} 3101 3102static void brcms_c_statsupd(struct brcms_c_info *wlc) 3103{ 3104 int i; 3105 struct macstat macstats; 3106#ifdef DEBUG 3107 u16 delta; 3108 u16 rxf0ovfl; 3109 u16 txfunfl[NFIFO]; 3110#endif /* DEBUG */ 3111 3112 /* if driver down, make no sense to update stats */ 3113 if (!wlc->pub->up) 3114 return; 3115 3116#ifdef DEBUG 3117 /* save last rx fifo 0 overflow count */ 3118 rxf0ovfl = wlc->core->macstat_snapshot->rxf0ovfl; 3119 3120 /* save last tx fifo underflow count */ 3121 for (i = 0; i < NFIFO; i++) 3122 txfunfl[i] = wlc->core->macstat_snapshot->txfunfl[i]; 3123#endif /* DEBUG */ 3124 3125 /* Read mac stats from contiguous shared memory */ 3126 brcms_b_copyfrom_objmem(wlc->hw, M_UCODE_MACSTAT, &macstats, 3127 sizeof(struct macstat), OBJADDR_SHM_SEL); 3128 3129#ifdef DEBUG 3130 /* check for rx fifo 0 overflow */ 3131 delta = (u16) (wlc->core->macstat_snapshot->rxf0ovfl - rxf0ovfl); 3132 if (delta) 3133 brcms_err(wlc->hw->d11core, "wl%d: %u rx fifo 0 overflows!\n", 3134 wlc->pub->unit, delta); 3135 3136 /* check for tx fifo underflows */ 3137 for (i = 0; i < NFIFO; i++) { 3138 delta = 3139 (u16) (wlc->core->macstat_snapshot->txfunfl[i] - 3140 txfunfl[i]); 3141 if (delta) 3142 brcms_err(wlc->hw->d11core, 3143 "wl%d: %u tx fifo %d underflows!\n", 3144 wlc->pub->unit, delta, i); 3145 } 3146#endif /* DEBUG */ 3147 3148 /* merge counters from dma module */ 3149 for (i = 0; i < NFIFO; i++) { 3150 if (wlc->hw->di[i]) 3151 dma_counterreset(wlc->hw->di[i]); 3152 } 3153} 3154 3155static void brcms_b_reset(struct brcms_hardware *wlc_hw) 3156{ 3157 /* reset the core */ 3158 if (!brcms_deviceremoved(wlc_hw->wlc)) 3159 brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS); 3160 3161 /* purge the dma rings */ 3162 brcms_c_flushqueues(wlc_hw->wlc); 3163} 3164 3165void brcms_c_reset(struct brcms_c_info *wlc) 3166{ 3167 brcms_dbg_info(wlc->hw->d11core, "wl%d\n", wlc->pub->unit); 3168 3169 /* slurp up hw mac counters before core reset */ 3170 brcms_c_statsupd(wlc); 3171 3172 /* reset our snapshot of macstat counters */ 3173 memset((char *)wlc->core->macstat_snapshot, 0, 3174 sizeof(struct macstat)); 3175 3176 brcms_b_reset(wlc->hw); 3177} 3178 3179void brcms_c_init_scb(struct scb *scb) 3180{ 3181 int i; 3182 3183 memset(scb, 0, sizeof(struct scb)); 3184 scb->flags = SCB_WMECAP | SCB_HTCAP; 3185 for (i = 0; i < NUMPRIO; i++) { 3186 scb->seqnum[i] = 0; 3187 scb->seqctl[i] = 0xFFFF; 3188 } 3189 3190 scb->seqctl_nonqos = 0xFFFF; 3191 scb->magic = SCB_MAGIC; 3192} 3193 3194/* d11 core init 3195 * reset PSM 3196 * download ucode/PCM 3197 * let ucode run to suspended 3198 * download ucode inits 3199 * config other core registers 3200 * init dma 3201 */ 3202static void brcms_b_coreinit(struct brcms_c_info *wlc) 3203{ 3204 struct brcms_hardware *wlc_hw = wlc->hw; 3205 struct bcma_device *core = wlc_hw->d11core; 3206 u32 sflags; 3207 u32 bcnint_us; 3208 uint i = 0; 3209 bool fifosz_fixup = false; 3210 int err = 0; 3211 u16 buf[NFIFO]; 3212 struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode; 3213 3214 brcms_dbg_info(core, "wl%d: core init\n", wlc_hw->unit); 3215 3216 /* reset PSM */ 3217 brcms_b_mctrl(wlc_hw, ~0, (MCTL_IHR_EN | MCTL_PSM_JMP_0 | MCTL_WAKE)); 3218 3219 brcms_ucode_download(wlc_hw); 3220 /* 3221 * FIFOSZ fixup. driver wants to controls the fifo allocation. 3222 */ 3223 fifosz_fixup = true; 3224 3225 /* let the PSM run to the suspended state, set mode to BSS STA */ 3226 bcma_write32(core, D11REGOFFS(macintstatus), -1); 3227 brcms_b_mctrl(wlc_hw, ~0, 3228 (MCTL_IHR_EN | MCTL_INFRA | MCTL_PSM_RUN | MCTL_WAKE)); 3229 3230 /* wait for ucode to self-suspend after auto-init */ 3231 SPINWAIT(((bcma_read32(core, D11REGOFFS(macintstatus)) & 3232 MI_MACSSPNDD) == 0), 1000 * 1000); 3233 if ((bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD) == 0) 3234 brcms_err(core, "wl%d: wlc_coreinit: ucode did not self-" 3235 "suspend!\n", wlc_hw->unit); 3236 3237 brcms_c_gpio_init(wlc); 3238 3239 sflags = bcma_aread32(core, BCMA_IOST); 3240 3241 if (D11REV_IS(wlc_hw->corerev, 23)) { 3242 if (BRCMS_ISNPHY(wlc_hw->band)) 3243 brcms_c_write_inits(wlc_hw, ucode->d11n0initvals16); 3244 else 3245 brcms_err(core, "%s: wl%d: unsupported phy in corerev" 3246 " %d\n", __func__, wlc_hw->unit, 3247 wlc_hw->corerev); 3248 } else if (D11REV_IS(wlc_hw->corerev, 24)) { 3249 if (BRCMS_ISLCNPHY(wlc_hw->band)) 3250 brcms_c_write_inits(wlc_hw, ucode->d11lcn0initvals24); 3251 else 3252 brcms_err(core, "%s: wl%d: unsupported phy in corerev" 3253 " %d\n", __func__, wlc_hw->unit, 3254 wlc_hw->corerev); 3255 } else { 3256 brcms_err(core, "%s: wl%d: unsupported corerev %d\n", 3257 __func__, wlc_hw->unit, wlc_hw->corerev); 3258 } 3259 3260 /* For old ucode, txfifo sizes needs to be modified(increased) */ 3261 if (fifosz_fixup) 3262 brcms_b_corerev_fifofixup(wlc_hw); 3263 3264 /* check txfifo allocations match between ucode and driver */ 3265 buf[TX_AC_BE_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE0); 3266 if (buf[TX_AC_BE_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]) { 3267 i = TX_AC_BE_FIFO; 3268 err = -1; 3269 } 3270 buf[TX_AC_VI_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE1); 3271 if (buf[TX_AC_VI_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]) { 3272 i = TX_AC_VI_FIFO; 3273 err = -1; 3274 } 3275 buf[TX_AC_BK_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE2); 3276 buf[TX_AC_VO_FIFO] = (buf[TX_AC_BK_FIFO] >> 8) & 0xff; 3277 buf[TX_AC_BK_FIFO] &= 0xff; 3278 if (buf[TX_AC_BK_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BK_FIFO]) { 3279 i = TX_AC_BK_FIFO; 3280 err = -1; 3281 } 3282 if (buf[TX_AC_VO_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO]) { 3283 i = TX_AC_VO_FIFO; 3284 err = -1; 3285 } 3286 buf[TX_BCMC_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE3); 3287 buf[TX_ATIM_FIFO] = (buf[TX_BCMC_FIFO] >> 8) & 0xff; 3288 buf[TX_BCMC_FIFO] &= 0xff; 3289 if (buf[TX_BCMC_FIFO] != wlc_hw->xmtfifo_sz[TX_BCMC_FIFO]) { 3290 i = TX_BCMC_FIFO; 3291 err = -1; 3292 } 3293 if (buf[TX_ATIM_FIFO] != wlc_hw->xmtfifo_sz[TX_ATIM_FIFO]) { 3294 i = TX_ATIM_FIFO; 3295 err = -1; 3296 } 3297 if (err != 0) 3298 brcms_err(core, "wlc_coreinit: txfifo mismatch: ucode size %d" 3299 " driver size %d index %d\n", buf[i], 3300 wlc_hw->xmtfifo_sz[i], i); 3301 3302 /* make sure we can still talk to the mac */ 3303 WARN_ON(bcma_read32(core, D11REGOFFS(maccontrol)) == 0xffffffff); 3304 3305 /* band-specific inits done by wlc_bsinit() */ 3306 3307 /* Set up frame burst size and antenna swap threshold init values */ 3308 brcms_b_write_shm(wlc_hw, M_MBURST_SIZE, MAXTXFRAMEBURST); 3309 brcms_b_write_shm(wlc_hw, M_MAX_ANTCNT, ANTCNT); 3310 3311 /* enable one rx interrupt per received frame */ 3312 bcma_write32(core, D11REGOFFS(intrcvlazy[0]), (1 << IRL_FC_SHIFT)); 3313 3314 /* set the station mode (BSS STA) */ 3315 brcms_b_mctrl(wlc_hw, 3316 (MCTL_INFRA | MCTL_DISCARD_PMQ | MCTL_AP), 3317 (MCTL_INFRA | MCTL_DISCARD_PMQ)); 3318 3319 /* set up Beacon interval */ 3320 bcnint_us = 0x8000 << 10; 3321 bcma_write32(core, D11REGOFFS(tsf_cfprep), 3322 (bcnint_us << CFPREP_CBI_SHIFT)); 3323 bcma_write32(core, D11REGOFFS(tsf_cfpstart), bcnint_us); 3324 bcma_write32(core, D11REGOFFS(macintstatus), MI_GP1); 3325 3326 /* write interrupt mask */ 3327 bcma_write32(core, D11REGOFFS(intctrlregs[RX_FIFO].intmask), 3328 DEF_RXINTMASK); 3329 3330 /* allow the MAC to control the PHY clock (dynamic on/off) */ 3331 brcms_b_macphyclk_set(wlc_hw, ON); 3332 3333 /* program dynamic clock control fast powerup delay register */ 3334 wlc->fastpwrup_dly = ai_clkctl_fast_pwrup_delay(wlc_hw->sih); 3335 bcma_write16(core, D11REGOFFS(scc_fastpwrup_dly), wlc->fastpwrup_dly); 3336 3337 /* tell the ucode the corerev */ 3338 brcms_b_write_shm(wlc_hw, M_MACHW_VER, (u16) wlc_hw->corerev); 3339 3340 /* tell the ucode MAC capabilities */ 3341 brcms_b_write_shm(wlc_hw, M_MACHW_CAP_L, 3342 (u16) (wlc_hw->machwcap & 0xffff)); 3343 brcms_b_write_shm(wlc_hw, M_MACHW_CAP_H, 3344 (u16) ((wlc_hw-> 3345 machwcap >> 16) & 0xffff)); 3346 3347 /* write retry limits to SCR, this done after PSM init */ 3348 bcma_write32(core, D11REGOFFS(objaddr), 3349 OBJADDR_SCR_SEL | S_DOT11_SRC_LMT); 3350 (void)bcma_read32(core, D11REGOFFS(objaddr)); 3351 bcma_write32(core, D11REGOFFS(objdata), wlc_hw->SRL); 3352 bcma_write32(core, D11REGOFFS(objaddr), 3353 OBJADDR_SCR_SEL | S_DOT11_LRC_LMT); 3354 (void)bcma_read32(core, D11REGOFFS(objaddr)); 3355 bcma_write32(core, D11REGOFFS(objdata), wlc_hw->LRL); 3356 3357 /* write rate fallback retry limits */ 3358 brcms_b_write_shm(wlc_hw, M_SFRMTXCNTFBRTHSD, wlc_hw->SFBL); 3359 brcms_b_write_shm(wlc_hw, M_LFRMTXCNTFBRTHSD, wlc_hw->LFBL); 3360 3361 bcma_mask16(core, D11REGOFFS(ifs_ctl), 0x0FFF); 3362 bcma_write16(core, D11REGOFFS(ifs_aifsn), EDCF_AIFSN_MIN); 3363 3364 /* init the tx dma engines */ 3365 for (i = 0; i < NFIFO; i++) { 3366 if (wlc_hw->di[i]) 3367 dma_txinit(wlc_hw->di[i]); 3368 } 3369 3370 /* init the rx dma engine(s) and post receive buffers */ 3371 dma_rxinit(wlc_hw->di[RX_FIFO]); 3372 dma_rxfill(wlc_hw->di[RX_FIFO]); 3373} 3374 3375void 3376static brcms_b_init(struct brcms_hardware *wlc_hw, u16 chanspec) { 3377 u32 macintmask; 3378 bool fastclk; 3379 struct brcms_c_info *wlc = wlc_hw->wlc; 3380 3381 /* request FAST clock if not on */ 3382 fastclk = wlc_hw->forcefastclk; 3383 if (!fastclk) 3384 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST); 3385 3386 /* disable interrupts */ 3387 macintmask = brcms_intrsoff(wlc->wl); 3388 3389 /* set up the specified band and chanspec */ 3390 brcms_c_setxband(wlc_hw, chspec_bandunit(chanspec)); 3391 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec); 3392 3393 /* do one-time phy inits and calibration */ 3394 wlc_phy_cal_init(wlc_hw->band->pi); 3395 3396 /* core-specific initialization */ 3397 brcms_b_coreinit(wlc); 3398 3399 /* band-specific inits */ 3400 brcms_b_bsinit(wlc, chanspec); 3401 3402 /* restore macintmask */ 3403 brcms_intrsrestore(wlc->wl, macintmask); 3404 3405 /* seed wake_override with BRCMS_WAKE_OVERRIDE_MACSUSPEND since the mac 3406 * is suspended and brcms_c_enable_mac() will clear this override bit. 3407 */ 3408 mboolset(wlc_hw->wake_override, BRCMS_WAKE_OVERRIDE_MACSUSPEND); 3409 3410 /* 3411 * initialize mac_suspend_depth to 1 to match ucode 3412 * initial suspended state 3413 */ 3414 wlc_hw->mac_suspend_depth = 1; 3415 3416 /* restore the clk */ 3417 if (!fastclk) 3418 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC); 3419} 3420 3421static void brcms_c_set_phy_chanspec(struct brcms_c_info *wlc, 3422 u16 chanspec) 3423{ 3424 /* Save our copy of the chanspec */ 3425 wlc->chanspec = chanspec; 3426 3427 /* Set the chanspec and power limits for this locale */ 3428 brcms_c_channel_set_chanspec(wlc->cmi, chanspec, BRCMS_TXPWR_MAX); 3429 3430 if (wlc->stf->ss_algosel_auto) 3431 brcms_c_stf_ss_algo_channel_get(wlc, &wlc->stf->ss_algo_channel, 3432 chanspec); 3433 3434 brcms_c_stf_ss_update(wlc, wlc->band); 3435} 3436 3437static void 3438brcms_default_rateset(struct brcms_c_info *wlc, struct brcms_c_rateset *rs) 3439{ 3440 brcms_c_rateset_default(rs, NULL, wlc->band->phytype, 3441 wlc->band->bandtype, false, BRCMS_RATE_MASK_FULL, 3442 (bool) (wlc->pub->_n_enab & SUPPORT_11N), 3443 brcms_chspec_bw(wlc->default_bss->chanspec), 3444 wlc->stf->txstreams); 3445} 3446 3447/* derive wlc->band->basic_rate[] table from 'rateset' */ 3448static void brcms_c_rate_lookup_init(struct brcms_c_info *wlc, 3449 struct brcms_c_rateset *rateset) 3450{ 3451 u8 rate; 3452 u8 mandatory; 3453 u8 cck_basic = 0; 3454 u8 ofdm_basic = 0; 3455 u8 *br = wlc->band->basic_rate; 3456 uint i; 3457 3458 /* incoming rates are in 500kbps units as in 802.11 Supported Rates */ 3459 memset(br, 0, BRCM_MAXRATE + 1); 3460 3461 /* For each basic rate in the rates list, make an entry in the 3462 * best basic lookup. 3463 */ 3464 for (i = 0; i < rateset->count; i++) { 3465 /* only make an entry for a basic rate */ 3466 if (!(rateset->rates[i] & BRCMS_RATE_FLAG)) 3467 continue; 3468 3469 /* mask off basic bit */ 3470 rate = (rateset->rates[i] & BRCMS_RATE_MASK); 3471 3472 if (rate > BRCM_MAXRATE) { 3473 brcms_err(wlc->hw->d11core, "brcms_c_rate_lookup_init: " 3474 "invalid rate 0x%X in rate set\n", 3475 rateset->rates[i]); 3476 continue; 3477 } 3478 3479 br[rate] = rate; 3480 } 3481 3482 /* The rate lookup table now has non-zero entries for each 3483 * basic rate, equal to the basic rate: br[basicN] = basicN 3484 * 3485 * To look up the best basic rate corresponding to any 3486 * particular rate, code can use the basic_rate table 3487 * like this 3488 * 3489 * basic_rate = wlc->band->basic_rate[tx_rate] 3490 * 3491 * Make sure there is a best basic rate entry for 3492 * every rate by walking up the table from low rates 3493 * to high, filling in holes in the lookup table 3494 */ 3495 3496 for (i = 0; i < wlc->band->hw_rateset.count; i++) { 3497 rate = wlc->band->hw_rateset.rates[i]; 3498 3499 if (br[rate] != 0) { 3500 /* This rate is a basic rate. 3501 * Keep track of the best basic rate so far by 3502 * modulation type. 3503 */ 3504 if (is_ofdm_rate(rate)) 3505 ofdm_basic = rate; 3506 else 3507 cck_basic = rate; 3508 3509 continue; 3510 } 3511 3512 /* This rate is not a basic rate so figure out the 3513 * best basic rate less than this rate and fill in 3514 * the hole in the table 3515 */ 3516 3517 br[rate] = is_ofdm_rate(rate) ? ofdm_basic : cck_basic; 3518 3519 if (br[rate] != 0) 3520 continue; 3521 3522 if (is_ofdm_rate(rate)) { 3523 /* 3524 * In 11g and 11a, the OFDM mandatory rates 3525 * are 6, 12, and 24 Mbps 3526 */ 3527 if (rate >= BRCM_RATE_24M) 3528 mandatory = BRCM_RATE_24M; 3529 else if (rate >= BRCM_RATE_12M) 3530 mandatory = BRCM_RATE_12M; 3531 else 3532 mandatory = BRCM_RATE_6M; 3533 } else { 3534 /* In 11b, all CCK rates are mandatory 1 - 11 Mbps */ 3535 mandatory = rate; 3536 } 3537 3538 br[rate] = mandatory; 3539 } 3540} 3541 3542static void brcms_c_bandinit_ordered(struct brcms_c_info *wlc, 3543 u16 chanspec) 3544{ 3545 struct brcms_c_rateset default_rateset; 3546 uint parkband; 3547 uint i, band_order[2]; 3548 3549 /* 3550 * We might have been bandlocked during down and the chip 3551 * power-cycled (hibernate). Figure out the right band to park on 3552 */ 3553 if (wlc->bandlocked || wlc->pub->_nbands == 1) { 3554 /* updated in brcms_c_bandlock() */ 3555 parkband = wlc->band->bandunit; 3556 band_order[0] = band_order[1] = parkband; 3557 } else { 3558 /* park on the band of the specified chanspec */ 3559 parkband = chspec_bandunit(chanspec); 3560 3561 /* order so that parkband initialize last */ 3562 band_order[0] = parkband ^ 1; 3563 band_order[1] = parkband; 3564 } 3565 3566 /* make each band operational, software state init */ 3567 for (i = 0; i < wlc->pub->_nbands; i++) { 3568 uint j = band_order[i]; 3569 3570 wlc->band = wlc->bandstate[j]; 3571 3572 brcms_default_rateset(wlc, &default_rateset); 3573 3574 /* fill in hw_rate */ 3575 brcms_c_rateset_filter(&default_rateset, &wlc->band->hw_rateset, 3576 false, BRCMS_RATES_CCK_OFDM, BRCMS_RATE_MASK, 3577 (bool) (wlc->pub->_n_enab & SUPPORT_11N)); 3578 3579 /* init basic rate lookup */ 3580 brcms_c_rate_lookup_init(wlc, &default_rateset); 3581 } 3582 3583 /* sync up phy/radio chanspec */ 3584 brcms_c_set_phy_chanspec(wlc, chanspec); 3585} 3586 3587/* 3588 * Set or clear filtering related maccontrol bits based on 3589 * specified filter flags 3590 */ 3591void brcms_c_mac_promisc(struct brcms_c_info *wlc, uint filter_flags) 3592{ 3593 u32 promisc_bits = 0; 3594 3595 wlc->filter_flags = filter_flags; 3596 3597 if (filter_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) 3598 promisc_bits |= MCTL_PROMISC; 3599 3600 if (filter_flags & FIF_BCN_PRBRESP_PROMISC) 3601 promisc_bits |= MCTL_BCNS_PROMISC; 3602 3603 if (filter_flags & FIF_FCSFAIL) 3604 promisc_bits |= MCTL_KEEPBADFCS; 3605 3606 if (filter_flags & (FIF_CONTROL | FIF_PSPOLL)) 3607 promisc_bits |= MCTL_KEEPCONTROL; 3608 3609 brcms_b_mctrl(wlc->hw, 3610 MCTL_PROMISC | MCTL_BCNS_PROMISC | 3611 MCTL_KEEPCONTROL | MCTL_KEEPBADFCS, 3612 promisc_bits); 3613} 3614 3615/* 3616 * ucode, hwmac update 3617 * Channel dependent updates for ucode and hw 3618 */ 3619static void brcms_c_ucode_mac_upd(struct brcms_c_info *wlc) 3620{ 3621 /* enable or disable any active IBSSs depending on whether or not 3622 * we are on the home channel 3623 */ 3624 if (wlc->home_chanspec == wlc_phy_chanspec_get(wlc->band->pi)) { 3625 if (wlc->pub->associated) { 3626 /* 3627 * BMAC_NOTE: This is something that should be fixed 3628 * in ucode inits. I think that the ucode inits set 3629 * up the bcn templates and shm values with a bogus 3630 * beacon. This should not be done in the inits. If 3631 * ucode needs to set up a beacon for testing, the 3632 * test routines should write it down, not expect the 3633 * inits to populate a bogus beacon. 3634 */ 3635 if (BRCMS_PHY_11N_CAP(wlc->band)) 3636 brcms_b_write_shm(wlc->hw, 3637 M_BCN_TXTSF_OFFSET, 0); 3638 } 3639 } else { 3640 /* disable an active IBSS if we are not on the home channel */ 3641 } 3642} 3643 3644static void brcms_c_write_rate_shm(struct brcms_c_info *wlc, u8 rate, 3645 u8 basic_rate) 3646{ 3647 u8 phy_rate, index; 3648 u8 basic_phy_rate, basic_index; 3649 u16 dir_table, basic_table; 3650 u16 basic_ptr; 3651 3652 /* Shared memory address for the table we are reading */ 3653 dir_table = is_ofdm_rate(basic_rate) ? M_RT_DIRMAP_A : M_RT_DIRMAP_B; 3654 3655 /* Shared memory address for the table we are writing */ 3656 basic_table = is_ofdm_rate(rate) ? M_RT_BBRSMAP_A : M_RT_BBRSMAP_B; 3657 3658 /* 3659 * for a given rate, the LS-nibble of the PLCP SIGNAL field is 3660 * the index into the rate table. 3661 */ 3662 phy_rate = rate_info[rate] & BRCMS_RATE_MASK; 3663 basic_phy_rate = rate_info[basic_rate] & BRCMS_RATE_MASK; 3664 index = phy_rate & 0xf; 3665 basic_index = basic_phy_rate & 0xf; 3666 3667 /* Find the SHM pointer to the ACK rate entry by looking in the 3668 * Direct-map Table 3669 */ 3670 basic_ptr = brcms_b_read_shm(wlc->hw, (dir_table + basic_index * 2)); 3671 3672 /* Update the SHM BSS-basic-rate-set mapping table with the pointer 3673 * to the correct basic rate for the given incoming rate 3674 */ 3675 brcms_b_write_shm(wlc->hw, (basic_table + index * 2), basic_ptr); 3676} 3677 3678static const struct brcms_c_rateset * 3679brcms_c_rateset_get_hwrs(struct brcms_c_info *wlc) 3680{ 3681 const struct brcms_c_rateset *rs_dflt; 3682 3683 if (BRCMS_PHY_11N_CAP(wlc->band)) { 3684 if (wlc->band->bandtype == BRCM_BAND_5G) 3685 rs_dflt = &ofdm_mimo_rates; 3686 else 3687 rs_dflt = &cck_ofdm_mimo_rates; 3688 } else if (wlc->band->gmode) 3689 rs_dflt = &cck_ofdm_rates; 3690 else 3691 rs_dflt = &cck_rates; 3692 3693 return rs_dflt; 3694} 3695 3696static void brcms_c_set_ratetable(struct brcms_c_info *wlc) 3697{ 3698 const struct brcms_c_rateset *rs_dflt; 3699 struct brcms_c_rateset rs; 3700 u8 rate, basic_rate; 3701 uint i; 3702 3703 rs_dflt = brcms_c_rateset_get_hwrs(wlc); 3704 3705 brcms_c_rateset_copy(rs_dflt, &rs); 3706 brcms_c_rateset_mcs_upd(&rs, wlc->stf->txstreams); 3707 3708 /* walk the phy rate table and update SHM basic rate lookup table */ 3709 for (i = 0; i < rs.count; i++) { 3710 rate = rs.rates[i] & BRCMS_RATE_MASK; 3711 3712 /* for a given rate brcms_basic_rate returns the rate at 3713 * which a response ACK/CTS should be sent. 3714 */ 3715 basic_rate = brcms_basic_rate(wlc, rate); 3716 if (basic_rate == 0) 3717 /* This should only happen if we are using a 3718 * restricted rateset. 3719 */ 3720 basic_rate = rs.rates[0] & BRCMS_RATE_MASK; 3721 3722 brcms_c_write_rate_shm(wlc, rate, basic_rate); 3723 } 3724} 3725 3726/* band-specific init */ 3727static void brcms_c_bsinit(struct brcms_c_info *wlc) 3728{ 3729 brcms_dbg_info(wlc->hw->d11core, "wl%d: bandunit %d\n", 3730 wlc->pub->unit, wlc->band->bandunit); 3731 3732 /* write ucode ACK/CTS rate table */ 3733 brcms_c_set_ratetable(wlc); 3734 3735 /* update some band specific mac configuration */ 3736 brcms_c_ucode_mac_upd(wlc); 3737 3738 /* init antenna selection */ 3739 brcms_c_antsel_init(wlc->asi); 3740 3741} 3742 3743/* formula: IDLE_BUSY_RATIO_X_16 = (100-duty_cycle)/duty_cycle*16 */ 3744static int 3745brcms_c_duty_cycle_set(struct brcms_c_info *wlc, int duty_cycle, bool isOFDM, 3746 bool writeToShm) 3747{ 3748 int idle_busy_ratio_x_16 = 0; 3749 uint offset = 3750 isOFDM ? M_TX_IDLE_BUSY_RATIO_X_16_OFDM : 3751 M_TX_IDLE_BUSY_RATIO_X_16_CCK; 3752 if (duty_cycle > 100 || duty_cycle < 0) { 3753 brcms_err(wlc->hw->d11core, 3754 "wl%d: duty cycle value off limit\n", 3755 wlc->pub->unit); 3756 return -EINVAL; 3757 } 3758 if (duty_cycle) 3759 idle_busy_ratio_x_16 = (100 - duty_cycle) * 16 / duty_cycle; 3760 /* Only write to shared memory when wl is up */ 3761 if (writeToShm) 3762 brcms_b_write_shm(wlc->hw, offset, (u16) idle_busy_ratio_x_16); 3763 3764 if (isOFDM) 3765 wlc->tx_duty_cycle_ofdm = (u16) duty_cycle; 3766 else 3767 wlc->tx_duty_cycle_cck = (u16) duty_cycle; 3768 3769 return 0; 3770} 3771 3772/* push sw hps and wake state through hardware */ 3773static void brcms_c_set_ps_ctrl(struct brcms_c_info *wlc) 3774{ 3775 u32 v1, v2; 3776 bool hps; 3777 bool awake_before; 3778 3779 hps = brcms_c_ps_allowed(wlc); 3780 3781 brcms_dbg_mac80211(wlc->hw->d11core, "wl%d: hps %d\n", wlc->pub->unit, 3782 hps); 3783 3784 v1 = bcma_read32(wlc->hw->d11core, D11REGOFFS(maccontrol)); 3785 v2 = MCTL_WAKE; 3786 if (hps) 3787 v2 |= MCTL_HPS; 3788 3789 brcms_b_mctrl(wlc->hw, MCTL_WAKE | MCTL_HPS, v2); 3790 3791 awake_before = ((v1 & MCTL_WAKE) || ((v1 & MCTL_HPS) == 0)); 3792 3793 if (!awake_before) 3794 brcms_b_wait_for_wake(wlc->hw); 3795} 3796 3797/* 3798 * Write this BSS config's MAC address to core. 3799 * Updates RXE match engine. 3800 */ 3801static int brcms_c_set_mac(struct brcms_bss_cfg *bsscfg) 3802{ 3803 int err = 0; 3804 struct brcms_c_info *wlc = bsscfg->wlc; 3805 3806 /* enter the MAC addr into the RXE match registers */ 3807 brcms_c_set_addrmatch(wlc, RCM_MAC_OFFSET, bsscfg->cur_etheraddr); 3808 3809 brcms_c_ampdu_macaddr_upd(wlc); 3810 3811 return err; 3812} 3813 3814/* Write the BSS config's BSSID address to core (set_bssid in d11procs.tcl). 3815 * Updates RXE match engine. 3816 */ 3817static void brcms_c_set_bssid(struct brcms_bss_cfg *bsscfg) 3818{ 3819 /* we need to update BSSID in RXE match registers */ 3820 brcms_c_set_addrmatch(bsscfg->wlc, RCM_BSSID_OFFSET, bsscfg->BSSID); 3821} 3822 3823static void brcms_b_set_shortslot(struct brcms_hardware *wlc_hw, bool shortslot) 3824{ 3825 wlc_hw->shortslot = shortslot; 3826 3827 if (wlc_hw->band->bandtype == BRCM_BAND_2G && wlc_hw->up) { 3828 brcms_c_suspend_mac_and_wait(wlc_hw->wlc); 3829 brcms_b_update_slot_timing(wlc_hw, shortslot); 3830 brcms_c_enable_mac(wlc_hw->wlc); 3831 } 3832} 3833 3834/* 3835 * Suspend the the MAC and update the slot timing 3836 * for standard 11b/g (20us slots) or shortslot 11g (9us slots). 3837 */ 3838static void brcms_c_switch_shortslot(struct brcms_c_info *wlc, bool shortslot) 3839{ 3840 /* use the override if it is set */ 3841 if (wlc->shortslot_override != BRCMS_SHORTSLOT_AUTO) 3842 shortslot = (wlc->shortslot_override == BRCMS_SHORTSLOT_ON); 3843 3844 if (wlc->shortslot == shortslot) 3845 return; 3846 3847 wlc->shortslot = shortslot; 3848 3849 brcms_b_set_shortslot(wlc->hw, shortslot); 3850} 3851 3852static void brcms_c_set_home_chanspec(struct brcms_c_info *wlc, u16 chanspec) 3853{ 3854 if (wlc->home_chanspec != chanspec) { 3855 wlc->home_chanspec = chanspec; 3856 3857 if (wlc->bsscfg->associated) 3858 wlc->bsscfg->current_bss->chanspec = chanspec; 3859 } 3860} 3861 3862void 3863brcms_b_set_chanspec(struct brcms_hardware *wlc_hw, u16 chanspec, 3864 bool mute_tx, struct txpwr_limits *txpwr) 3865{ 3866 uint bandunit; 3867 3868 brcms_dbg_mac80211(wlc_hw->d11core, "wl%d: 0x%x\n", wlc_hw->unit, 3869 chanspec); 3870 3871 wlc_hw->chanspec = chanspec; 3872 3873 /* Switch bands if necessary */ 3874 if (wlc_hw->_nbands > 1) { 3875 bandunit = chspec_bandunit(chanspec); 3876 if (wlc_hw->band->bandunit != bandunit) { 3877 /* brcms_b_setband disables other bandunit, 3878 * use light band switch if not up yet 3879 */ 3880 if (wlc_hw->up) { 3881 wlc_phy_chanspec_radio_set(wlc_hw-> 3882 bandstate[bandunit]-> 3883 pi, chanspec); 3884 brcms_b_setband(wlc_hw, bandunit, chanspec); 3885 } else { 3886 brcms_c_setxband(wlc_hw, bandunit); 3887 } 3888 } 3889 } 3890 3891 wlc_phy_initcal_enable(wlc_hw->band->pi, !mute_tx); 3892 3893 if (!wlc_hw->up) { 3894 if (wlc_hw->clk) 3895 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr, 3896 chanspec); 3897 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec); 3898 } else { 3899 wlc_phy_chanspec_set(wlc_hw->band->pi, chanspec); 3900 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr, chanspec); 3901 3902 /* Update muting of the channel */ 3903 brcms_b_mute(wlc_hw, mute_tx); 3904 } 3905} 3906 3907/* switch to and initialize new band */ 3908static void brcms_c_setband(struct brcms_c_info *wlc, 3909 uint bandunit) 3910{ 3911 wlc->band = wlc->bandstate[bandunit]; 3912 3913 if (!wlc->pub->up) 3914 return; 3915 3916 /* wait for at least one beacon before entering sleeping state */ 3917 brcms_c_set_ps_ctrl(wlc); 3918 3919 /* band-specific initializations */ 3920 brcms_c_bsinit(wlc); 3921} 3922 3923static void brcms_c_set_chanspec(struct brcms_c_info *wlc, u16 chanspec) 3924{ 3925 uint bandunit; 3926 bool switchband = false; 3927 u16 old_chanspec = wlc->chanspec; 3928 3929 if (!brcms_c_valid_chanspec_db(wlc->cmi, chanspec)) { 3930 brcms_err(wlc->hw->d11core, "wl%d: %s: Bad channel %d\n", 3931 wlc->pub->unit, __func__, CHSPEC_CHANNEL(chanspec)); 3932 return; 3933 } 3934 3935 /* Switch bands if necessary */ 3936 if (wlc->pub->_nbands > 1) { 3937 bandunit = chspec_bandunit(chanspec); 3938 if (wlc->band->bandunit != bandunit || wlc->bandinit_pending) { 3939 switchband = true; 3940 if (wlc->bandlocked) { 3941 brcms_err(wlc->hw->d11core, 3942 "wl%d: %s: chspec %d band is locked!\n", 3943 wlc->pub->unit, __func__, 3944 CHSPEC_CHANNEL(chanspec)); 3945 return; 3946 } 3947 /* 3948 * should the setband call come after the 3949 * brcms_b_chanspec() ? if the setband updates 3950 * (brcms_c_bsinit) use low level calls to inspect and 3951 * set state, the state inspected may be from the wrong 3952 * band, or the following brcms_b_set_chanspec() may 3953 * undo the work. 3954 */ 3955 brcms_c_setband(wlc, bandunit); 3956 } 3957 } 3958 3959 /* sync up phy/radio chanspec */ 3960 brcms_c_set_phy_chanspec(wlc, chanspec); 3961 3962 /* init antenna selection */ 3963 if (brcms_chspec_bw(old_chanspec) != brcms_chspec_bw(chanspec)) { 3964 brcms_c_antsel_init(wlc->asi); 3965 3966 /* Fix the hardware rateset based on bw. 3967 * Mainly add MCS32 for 40Mhz, remove MCS 32 for 20Mhz 3968 */ 3969 brcms_c_rateset_bw_mcs_filter(&wlc->band->hw_rateset, 3970 wlc->band->mimo_cap_40 ? brcms_chspec_bw(chanspec) : 0); 3971 } 3972 3973 /* update some mac configuration since chanspec changed */ 3974 brcms_c_ucode_mac_upd(wlc); 3975} 3976 3977/* 3978 * This function changes the phytxctl for beacon based on current 3979 * beacon ratespec AND txant setting as per this table: 3980 * ratespec CCK ant = wlc->stf->txant 3981 * OFDM ant = 3 3982 */ 3983void brcms_c_beacon_phytxctl_txant_upd(struct brcms_c_info *wlc, 3984 u32 bcn_rspec) 3985{ 3986 u16 phyctl; 3987 u16 phytxant = wlc->stf->phytxant; 3988 u16 mask = PHY_TXC_ANT_MASK; 3989 3990 /* for non-siso rates or default setting, use the available chains */ 3991 if (BRCMS_PHY_11N_CAP(wlc->band)) 3992 phytxant = brcms_c_stf_phytxchain_sel(wlc, bcn_rspec); 3993 3994 phyctl = brcms_b_read_shm(wlc->hw, M_BCN_PCTLWD); 3995 phyctl = (phyctl & ~mask) | phytxant; 3996 brcms_b_write_shm(wlc->hw, M_BCN_PCTLWD, phyctl); 3997} 3998 3999/* 4000 * centralized protection config change function to simplify debugging, no 4001 * consistency checking this should be called only on changes to avoid overhead 4002 * in periodic function 4003 */ 4004void brcms_c_protection_upd(struct brcms_c_info *wlc, uint idx, int val) 4005{ 4006 /* 4007 * Cannot use brcms_dbg_* here because this function is called 4008 * before wlc is sufficiently initialized. 4009 */ 4010 BCMMSG(wlc->wiphy, "idx %d, val %d\n", idx, val); 4011 4012 switch (idx) { 4013 case BRCMS_PROT_G_SPEC: 4014 wlc->protection->_g = (bool) val; 4015 break; 4016 case BRCMS_PROT_G_OVR: 4017 wlc->protection->g_override = (s8) val; 4018 break; 4019 case BRCMS_PROT_G_USER: 4020 wlc->protection->gmode_user = (u8) val; 4021 break; 4022 case BRCMS_PROT_OVERLAP: 4023 wlc->protection->overlap = (s8) val; 4024 break; 4025 case BRCMS_PROT_N_USER: 4026 wlc->protection->nmode_user = (s8) val; 4027 break; 4028 case BRCMS_PROT_N_CFG: 4029 wlc->protection->n_cfg = (s8) val; 4030 break; 4031 case BRCMS_PROT_N_CFG_OVR: 4032 wlc->protection->n_cfg_override = (s8) val; 4033 break; 4034 case BRCMS_PROT_N_NONGF: 4035 wlc->protection->nongf = (bool) val; 4036 break; 4037 case BRCMS_PROT_N_NONGF_OVR: 4038 wlc->protection->nongf_override = (s8) val; 4039 break; 4040 case BRCMS_PROT_N_PAM_OVR: 4041 wlc->protection->n_pam_override = (s8) val; 4042 break; 4043 case BRCMS_PROT_N_OBSS: 4044 wlc->protection->n_obss = (bool) val; 4045 break; 4046 4047 default: 4048 break; 4049 } 4050 4051} 4052 4053static void brcms_c_ht_update_sgi_rx(struct brcms_c_info *wlc, int val) 4054{ 4055 if (wlc->pub->up) { 4056 brcms_c_update_beacon(wlc); 4057 brcms_c_update_probe_resp(wlc, true); 4058 } 4059} 4060 4061static void brcms_c_ht_update_ldpc(struct brcms_c_info *wlc, s8 val) 4062{ 4063 wlc->stf->ldpc = val; 4064 4065 if (wlc->pub->up) { 4066 brcms_c_update_beacon(wlc); 4067 brcms_c_update_probe_resp(wlc, true); 4068 wlc_phy_ldpc_override_set(wlc->band->pi, (val ? true : false)); 4069 } 4070} 4071 4072void brcms_c_wme_setparams(struct brcms_c_info *wlc, u16 aci, 4073 const struct ieee80211_tx_queue_params *params, 4074 bool suspend) 4075{ 4076 int i; 4077 struct shm_acparams acp_shm; 4078 u16 *shm_entry; 4079 4080 /* Only apply params if the core is out of reset and has clocks */ 4081 if (!wlc->clk) { 4082 brcms_err(wlc->hw->d11core, "wl%d: %s : no-clock\n", 4083 wlc->pub->unit, __func__); 4084 return; 4085 } 4086 4087 memset((char *)&acp_shm, 0, sizeof(struct shm_acparams)); 4088 /* fill in shm ac params struct */ 4089 acp_shm.txop = params->txop; 4090 /* convert from units of 32us to us for ucode */ 4091 wlc->edcf_txop[aci & 0x3] = acp_shm.txop = 4092 EDCF_TXOP2USEC(acp_shm.txop); 4093 acp_shm.aifs = (params->aifs & EDCF_AIFSN_MASK); 4094 4095 if (aci == IEEE80211_AC_VI && acp_shm.txop == 0 4096 && acp_shm.aifs < EDCF_AIFSN_MAX) 4097 acp_shm.aifs++; 4098 4099 if (acp_shm.aifs < EDCF_AIFSN_MIN 4100 || acp_shm.aifs > EDCF_AIFSN_MAX) { 4101 brcms_err(wlc->hw->d11core, "wl%d: edcf_setparams: bad " 4102 "aifs %d\n", wlc->pub->unit, acp_shm.aifs); 4103 } else { 4104 acp_shm.cwmin = params->cw_min; 4105 acp_shm.cwmax = params->cw_max; 4106 acp_shm.cwcur = acp_shm.cwmin; 4107 acp_shm.bslots = 4108 bcma_read16(wlc->hw->d11core, D11REGOFFS(tsf_random)) & 4109 acp_shm.cwcur; 4110 acp_shm.reggap = acp_shm.bslots + acp_shm.aifs; 4111 /* Indicate the new params to the ucode */ 4112 acp_shm.status = brcms_b_read_shm(wlc->hw, (M_EDCF_QINFO + 4113 wme_ac2fifo[aci] * 4114 M_EDCF_QLEN + 4115 M_EDCF_STATUS_OFF)); 4116 acp_shm.status |= WME_STATUS_NEWAC; 4117 4118 /* Fill in shm acparam table */ 4119 shm_entry = (u16 *) &acp_shm; 4120 for (i = 0; i < (int)sizeof(struct shm_acparams); i += 2) 4121 brcms_b_write_shm(wlc->hw, 4122 M_EDCF_QINFO + 4123 wme_ac2fifo[aci] * M_EDCF_QLEN + i, 4124 *shm_entry++); 4125 } 4126 4127 if (suspend) { 4128 brcms_c_suspend_mac_and_wait(wlc); 4129 brcms_c_enable_mac(wlc); 4130 } 4131} 4132 4133static void brcms_c_edcf_setparams(struct brcms_c_info *wlc, bool suspend) 4134{ 4135 u16 aci; 4136 int i_ac; 4137 struct ieee80211_tx_queue_params txq_pars; 4138 static const struct edcf_acparam default_edcf_acparams[] = { 4139 {EDCF_AC_BE_ACI_STA, EDCF_AC_BE_ECW_STA, EDCF_AC_BE_TXOP_STA}, 4140 {EDCF_AC_BK_ACI_STA, EDCF_AC_BK_ECW_STA, EDCF_AC_BK_TXOP_STA}, 4141 {EDCF_AC_VI_ACI_STA, EDCF_AC_VI_ECW_STA, EDCF_AC_VI_TXOP_STA}, 4142 {EDCF_AC_VO_ACI_STA, EDCF_AC_VO_ECW_STA, EDCF_AC_VO_TXOP_STA} 4143 }; /* ucode needs these parameters during its initialization */ 4144 const struct edcf_acparam *edcf_acp = &default_edcf_acparams[0]; 4145 4146 for (i_ac = 0; i_ac < IEEE80211_NUM_ACS; i_ac++, edcf_acp++) { 4147 /* find out which ac this set of params applies to */ 4148 aci = (edcf_acp->ACI & EDCF_ACI_MASK) >> EDCF_ACI_SHIFT; 4149 4150 /* fill in shm ac params struct */ 4151 txq_pars.txop = edcf_acp->TXOP; 4152 txq_pars.aifs = edcf_acp->ACI; 4153 4154 /* CWmin = 2^(ECWmin) - 1 */ 4155 txq_pars.cw_min = EDCF_ECW2CW(edcf_acp->ECW & EDCF_ECWMIN_MASK); 4156 /* CWmax = 2^(ECWmax) - 1 */ 4157 txq_pars.cw_max = EDCF_ECW2CW((edcf_acp->ECW & EDCF_ECWMAX_MASK) 4158 >> EDCF_ECWMAX_SHIFT); 4159 brcms_c_wme_setparams(wlc, aci, &txq_pars, suspend); 4160 } 4161 4162 if (suspend) { 4163 brcms_c_suspend_mac_and_wait(wlc); 4164 brcms_c_enable_mac(wlc); 4165 } 4166} 4167 4168static void brcms_c_radio_monitor_start(struct brcms_c_info *wlc) 4169{ 4170 /* Don't start the timer if HWRADIO feature is disabled */ 4171 if (wlc->radio_monitor) 4172 return; 4173 4174 wlc->radio_monitor = true; 4175 brcms_b_pllreq(wlc->hw, true, BRCMS_PLLREQ_RADIO_MON); 4176 brcms_add_timer(wlc->radio_timer, TIMER_INTERVAL_RADIOCHK, true); 4177} 4178 4179static bool brcms_c_radio_monitor_stop(struct brcms_c_info *wlc) 4180{ 4181 if (!wlc->radio_monitor) 4182 return true; 4183 4184 wlc->radio_monitor = false; 4185 brcms_b_pllreq(wlc->hw, false, BRCMS_PLLREQ_RADIO_MON); 4186 return brcms_del_timer(wlc->radio_timer); 4187} 4188 4189/* read hwdisable state and propagate to wlc flag */ 4190static void brcms_c_radio_hwdisable_upd(struct brcms_c_info *wlc) 4191{ 4192 if (wlc->pub->hw_off) 4193 return; 4194 4195 if (brcms_b_radio_read_hwdisabled(wlc->hw)) 4196 mboolset(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE); 4197 else 4198 mboolclr(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE); 4199} 4200 4201/* update hwradio status and return it */ 4202bool brcms_c_check_radio_disabled(struct brcms_c_info *wlc) 4203{ 4204 brcms_c_radio_hwdisable_upd(wlc); 4205 4206 return mboolisset(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE) ? 4207 true : false; 4208} 4209 4210/* periodical query hw radio button while driver is "down" */ 4211static void brcms_c_radio_timer(void *arg) 4212{ 4213 struct brcms_c_info *wlc = (struct brcms_c_info *) arg; 4214 4215 if (brcms_deviceremoved(wlc)) { 4216 brcms_err(wlc->hw->d11core, "wl%d: %s: dead chip\n", 4217 wlc->pub->unit, __func__); 4218 brcms_down(wlc->wl); 4219 return; 4220 } 4221 4222 brcms_c_radio_hwdisable_upd(wlc); 4223} 4224 4225/* common low-level watchdog code */ 4226static void brcms_b_watchdog(struct brcms_c_info *wlc) 4227{ 4228 struct brcms_hardware *wlc_hw = wlc->hw; 4229 4230 if (!wlc_hw->up) 4231 return; 4232 4233 /* increment second count */ 4234 wlc_hw->now++; 4235 4236 /* Check for FIFO error interrupts */ 4237 brcms_b_fifoerrors(wlc_hw); 4238 4239 /* make sure RX dma has buffers */ 4240 dma_rxfill(wlc->hw->di[RX_FIFO]); 4241 4242 wlc_phy_watchdog(wlc_hw->band->pi); 4243} 4244 4245/* common watchdog code */ 4246static void brcms_c_watchdog(struct brcms_c_info *wlc) 4247{ 4248 brcms_dbg_info(wlc->hw->d11core, "wl%d\n", wlc->pub->unit); 4249 4250 if (!wlc->pub->up) 4251 return; 4252 4253 if (brcms_deviceremoved(wlc)) { 4254 brcms_err(wlc->hw->d11core, "wl%d: %s: dead chip\n", 4255 wlc->pub->unit, __func__); 4256 brcms_down(wlc->wl); 4257 return; 4258 } 4259 4260 /* increment second count */ 4261 wlc->pub->now++; 4262 4263 brcms_c_radio_hwdisable_upd(wlc); 4264 /* if radio is disable, driver may be down, quit here */ 4265 if (wlc->pub->radio_disabled) 4266 return; 4267 4268 brcms_b_watchdog(wlc); 4269 4270 /* 4271 * occasionally sample mac stat counters to 4272 * detect 16-bit counter wrap 4273 */ 4274 if ((wlc->pub->now % SW_TIMER_MAC_STAT_UPD) == 0) 4275 brcms_c_statsupd(wlc); 4276 4277 if (BRCMS_ISNPHY(wlc->band) && 4278 ((wlc->pub->now - wlc->tempsense_lasttime) >= 4279 BRCMS_TEMPSENSE_PERIOD)) { 4280 wlc->tempsense_lasttime = wlc->pub->now; 4281 brcms_c_tempsense_upd(wlc); 4282 } 4283} 4284 4285static void brcms_c_watchdog_by_timer(void *arg) 4286{ 4287 struct brcms_c_info *wlc = (struct brcms_c_info *) arg; 4288 4289 brcms_c_watchdog(wlc); 4290} 4291 4292static bool brcms_c_timers_init(struct brcms_c_info *wlc, int unit) 4293{ 4294 wlc->wdtimer = brcms_init_timer(wlc->wl, brcms_c_watchdog_by_timer, 4295 wlc, "watchdog"); 4296 if (!wlc->wdtimer) { 4297 wiphy_err(wlc->wiphy, "wl%d: wl_init_timer for wdtimer " 4298 "failed\n", unit); 4299 goto fail; 4300 } 4301 4302 wlc->radio_timer = brcms_init_timer(wlc->wl, brcms_c_radio_timer, 4303 wlc, "radio"); 4304 if (!wlc->radio_timer) { 4305 wiphy_err(wlc->wiphy, "wl%d: wl_init_timer for radio_timer " 4306 "failed\n", unit); 4307 goto fail; 4308 } 4309 4310 return true; 4311 4312 fail: 4313 return false; 4314} 4315 4316/* 4317 * Initialize brcms_c_info default values ... 4318 * may get overrides later in this function 4319 */ 4320static void brcms_c_info_init(struct brcms_c_info *wlc, int unit) 4321{ 4322 int i; 4323 4324 /* Save our copy of the chanspec */ 4325 wlc->chanspec = ch20mhz_chspec(1); 4326 4327 /* various 802.11g modes */ 4328 wlc->shortslot = false; 4329 wlc->shortslot_override = BRCMS_SHORTSLOT_AUTO; 4330 4331 brcms_c_protection_upd(wlc, BRCMS_PROT_G_OVR, BRCMS_PROTECTION_AUTO); 4332 brcms_c_protection_upd(wlc, BRCMS_PROT_G_SPEC, false); 4333 4334 brcms_c_protection_upd(wlc, BRCMS_PROT_N_CFG_OVR, 4335 BRCMS_PROTECTION_AUTO); 4336 brcms_c_protection_upd(wlc, BRCMS_PROT_N_CFG, BRCMS_N_PROTECTION_OFF); 4337 brcms_c_protection_upd(wlc, BRCMS_PROT_N_NONGF_OVR, 4338 BRCMS_PROTECTION_AUTO); 4339 brcms_c_protection_upd(wlc, BRCMS_PROT_N_NONGF, false); 4340 brcms_c_protection_upd(wlc, BRCMS_PROT_N_PAM_OVR, AUTO); 4341 4342 brcms_c_protection_upd(wlc, BRCMS_PROT_OVERLAP, 4343 BRCMS_PROTECTION_CTL_OVERLAP); 4344 4345 /* 802.11g draft 4.0 NonERP elt advertisement */ 4346 wlc->include_legacy_erp = true; 4347 4348 wlc->stf->ant_rx_ovr = ANT_RX_DIV_DEF; 4349 wlc->stf->txant = ANT_TX_DEF; 4350 4351 wlc->prb_resp_timeout = BRCMS_PRB_RESP_TIMEOUT; 4352 4353 wlc->usr_fragthresh = DOT11_DEFAULT_FRAG_LEN; 4354 for (i = 0; i < NFIFO; i++) 4355 wlc->fragthresh[i] = DOT11_DEFAULT_FRAG_LEN; 4356 wlc->RTSThresh = DOT11_DEFAULT_RTS_LEN; 4357 4358 /* default rate fallback retry limits */ 4359 wlc->SFBL = RETRY_SHORT_FB; 4360 wlc->LFBL = RETRY_LONG_FB; 4361 4362 /* default mac retry limits */ 4363 wlc->SRL = RETRY_SHORT_DEF; 4364 wlc->LRL = RETRY_LONG_DEF; 4365 4366 /* WME QoS mode is Auto by default */ 4367 wlc->pub->_ampdu = AMPDU_AGG_HOST; 4368 wlc->pub->bcmerror = 0; 4369} 4370 4371static uint brcms_c_attach_module(struct brcms_c_info *wlc) 4372{ 4373 uint err = 0; 4374 uint unit; 4375 unit = wlc->pub->unit; 4376 4377 wlc->asi = brcms_c_antsel_attach(wlc); 4378 if (wlc->asi == NULL) { 4379 wiphy_err(wlc->wiphy, "wl%d: attach: antsel_attach " 4380 "failed\n", unit); 4381 err = 44; 4382 goto fail; 4383 } 4384 4385 wlc->ampdu = brcms_c_ampdu_attach(wlc); 4386 if (wlc->ampdu == NULL) { 4387 wiphy_err(wlc->wiphy, "wl%d: attach: ampdu_attach " 4388 "failed\n", unit); 4389 err = 50; 4390 goto fail; 4391 } 4392 4393 if ((brcms_c_stf_attach(wlc) != 0)) { 4394 wiphy_err(wlc->wiphy, "wl%d: attach: stf_attach " 4395 "failed\n", unit); 4396 err = 68; 4397 goto fail; 4398 } 4399 fail: 4400 return err; 4401} 4402 4403struct brcms_pub *brcms_c_pub(struct brcms_c_info *wlc) 4404{ 4405 return wlc->pub; 4406} 4407 4408/* low level attach 4409 * run backplane attach, init nvram 4410 * run phy attach 4411 * initialize software state for each core and band 4412 * put the whole chip in reset(driver down state), no clock 4413 */ 4414static int brcms_b_attach(struct brcms_c_info *wlc, struct bcma_device *core, 4415 uint unit, bool piomode) 4416{ 4417 struct brcms_hardware *wlc_hw; 4418 uint err = 0; 4419 uint j; 4420 bool wme = false; 4421 struct shared_phy_params sha_params; 4422 struct wiphy *wiphy = wlc->wiphy; 4423 struct pci_dev *pcidev = core->bus->host_pci; 4424 struct ssb_sprom *sprom = &core->bus->sprom; 4425 4426 if (core->bus->hosttype == BCMA_HOSTTYPE_PCI) 4427 brcms_dbg_info(core, "wl%d: vendor 0x%x device 0x%x\n", unit, 4428 pcidev->vendor, 4429 pcidev->device); 4430 else 4431 brcms_dbg_info(core, "wl%d: vendor 0x%x device 0x%x\n", unit, 4432 core->bus->boardinfo.vendor, 4433 core->bus->boardinfo.type); 4434 4435 wme = true; 4436 4437 wlc_hw = wlc->hw; 4438 wlc_hw->wlc = wlc; 4439 wlc_hw->unit = unit; 4440 wlc_hw->band = wlc_hw->bandstate[0]; 4441 wlc_hw->_piomode = piomode; 4442 4443 /* populate struct brcms_hardware with default values */ 4444 brcms_b_info_init(wlc_hw); 4445 4446 /* 4447 * Do the hardware portion of the attach. Also initialize software 4448 * state that depends on the particular hardware we are running. 4449 */ 4450 wlc_hw->sih = ai_attach(core->bus); 4451 if (wlc_hw->sih == NULL) { 4452 wiphy_err(wiphy, "wl%d: brcms_b_attach: si_attach failed\n", 4453 unit); 4454 err = 11; 4455 goto fail; 4456 } 4457 4458 /* verify again the device is supported */ 4459 if (!brcms_c_chipmatch(core)) { 4460 wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported device\n", 4461 unit); 4462 err = 12; 4463 goto fail; 4464 } 4465 4466 if (core->bus->hosttype == BCMA_HOSTTYPE_PCI) { 4467 wlc_hw->vendorid = pcidev->vendor; 4468 wlc_hw->deviceid = pcidev->device; 4469 } else { 4470 wlc_hw->vendorid = core->bus->boardinfo.vendor; 4471 wlc_hw->deviceid = core->bus->boardinfo.type; 4472 } 4473 4474 wlc_hw->d11core = core; 4475 wlc_hw->corerev = core->id.rev; 4476 4477 /* validate chip, chiprev and corerev */ 4478 if (!brcms_c_isgoodchip(wlc_hw)) { 4479 err = 13; 4480 goto fail; 4481 } 4482 4483 /* initialize power control registers */ 4484 ai_clkctl_init(wlc_hw->sih); 4485 4486 /* request fastclock and force fastclock for the rest of attach 4487 * bring the d11 core out of reset. 4488 * For PMU chips, the first wlc_clkctl_clk is no-op since core-clk 4489 * is still false; But it will be called again inside wlc_corereset, 4490 * after d11 is out of reset. 4491 */ 4492 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST); 4493 brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS); 4494 4495 if (!brcms_b_validate_chip_access(wlc_hw)) { 4496 wiphy_err(wiphy, "wl%d: brcms_b_attach: validate_chip_access " 4497 "failed\n", unit); 4498 err = 14; 4499 goto fail; 4500 } 4501 4502 /* get the board rev, used just below */ 4503 j = sprom->board_rev; 4504 /* promote srom boardrev of 0xFF to 1 */ 4505 if (j == BOARDREV_PROMOTABLE) 4506 j = BOARDREV_PROMOTED; 4507 wlc_hw->boardrev = (u16) j; 4508 if (!brcms_c_validboardtype(wlc_hw)) { 4509 wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported Broadcom " 4510 "board type (0x%x)" " or revision level (0x%x)\n", 4511 unit, ai_get_boardtype(wlc_hw->sih), 4512 wlc_hw->boardrev); 4513 err = 15; 4514 goto fail; 4515 } 4516 wlc_hw->sromrev = sprom->revision; 4517 wlc_hw->boardflags = sprom->boardflags_lo + (sprom->boardflags_hi << 16); 4518 wlc_hw->boardflags2 = sprom->boardflags2_lo + (sprom->boardflags2_hi << 16); 4519 4520 if (wlc_hw->boardflags & BFL_NOPLLDOWN) 4521 brcms_b_pllreq(wlc_hw, true, BRCMS_PLLREQ_SHARED); 4522 4523 /* check device id(srom, nvram etc.) to set bands */ 4524 if (wlc_hw->deviceid == BCM43224_D11N_ID || 4525 wlc_hw->deviceid == BCM43224_D11N_ID_VEN1) 4526 /* Dualband boards */ 4527 wlc_hw->_nbands = 2; 4528 else 4529 wlc_hw->_nbands = 1; 4530 4531 if ((ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM43225)) 4532 wlc_hw->_nbands = 1; 4533 4534 /* BMAC_NOTE: remove init of pub values when brcms_c_attach() 4535 * unconditionally does the init of these values 4536 */ 4537 wlc->vendorid = wlc_hw->vendorid; 4538 wlc->deviceid = wlc_hw->deviceid; 4539 wlc->pub->sih = wlc_hw->sih; 4540 wlc->pub->corerev = wlc_hw->corerev; 4541 wlc->pub->sromrev = wlc_hw->sromrev; 4542 wlc->pub->boardrev = wlc_hw->boardrev; 4543 wlc->pub->boardflags = wlc_hw->boardflags; 4544 wlc->pub->boardflags2 = wlc_hw->boardflags2; 4545 wlc->pub->_nbands = wlc_hw->_nbands; 4546 4547 wlc_hw->physhim = wlc_phy_shim_attach(wlc_hw, wlc->wl, wlc); 4548 4549 if (wlc_hw->physhim == NULL) { 4550 wiphy_err(wiphy, "wl%d: brcms_b_attach: wlc_phy_shim_attach " 4551 "failed\n", unit); 4552 err = 25; 4553 goto fail; 4554 } 4555 4556 /* pass all the parameters to wlc_phy_shared_attach in one struct */ 4557 sha_params.sih = wlc_hw->sih; 4558 sha_params.physhim = wlc_hw->physhim; 4559 sha_params.unit = unit; 4560 sha_params.corerev = wlc_hw->corerev; 4561 sha_params.vid = wlc_hw->vendorid; 4562 sha_params.did = wlc_hw->deviceid; 4563 sha_params.chip = ai_get_chip_id(wlc_hw->sih); 4564 sha_params.chiprev = ai_get_chiprev(wlc_hw->sih); 4565 sha_params.chippkg = ai_get_chippkg(wlc_hw->sih); 4566 sha_params.sromrev = wlc_hw->sromrev; 4567 sha_params.boardtype = ai_get_boardtype(wlc_hw->sih); 4568 sha_params.boardrev = wlc_hw->boardrev; 4569 sha_params.boardflags = wlc_hw->boardflags; 4570 sha_params.boardflags2 = wlc_hw->boardflags2; 4571 4572 /* alloc and save pointer to shared phy state area */ 4573 wlc_hw->phy_sh = wlc_phy_shared_attach(&sha_params); 4574 if (!wlc_hw->phy_sh) { 4575 err = 16; 4576 goto fail; 4577 } 4578 4579 /* initialize software state for each core and band */ 4580 for (j = 0; j < wlc_hw->_nbands; j++) { 4581 /* 4582 * band0 is always 2.4Ghz 4583 * band1, if present, is 5Ghz 4584 */ 4585 4586 brcms_c_setxband(wlc_hw, j); 4587 4588 wlc_hw->band->bandunit = j; 4589 wlc_hw->band->bandtype = j ? BRCM_BAND_5G : BRCM_BAND_2G; 4590 wlc->band->bandunit = j; 4591 wlc->band->bandtype = j ? BRCM_BAND_5G : BRCM_BAND_2G; 4592 wlc->core->coreidx = core->core_index; 4593 4594 wlc_hw->machwcap = bcma_read32(core, D11REGOFFS(machwcap)); 4595 wlc_hw->machwcap_backup = wlc_hw->machwcap; 4596 4597 /* init tx fifo size */ 4598 WARN_ON((wlc_hw->corerev - XMTFIFOTBL_STARTREV) < 0 || 4599 (wlc_hw->corerev - XMTFIFOTBL_STARTREV) > 4600 ARRAY_SIZE(xmtfifo_sz)); 4601 wlc_hw->xmtfifo_sz = 4602 xmtfifo_sz[(wlc_hw->corerev - XMTFIFOTBL_STARTREV)]; 4603 WARN_ON(!wlc_hw->xmtfifo_sz[0]); 4604 4605 /* Get a phy for this band */ 4606 wlc_hw->band->pi = 4607 wlc_phy_attach(wlc_hw->phy_sh, core, 4608 wlc_hw->band->bandtype, 4609 wlc->wiphy); 4610 if (wlc_hw->band->pi == NULL) { 4611 wiphy_err(wiphy, "wl%d: brcms_b_attach: wlc_phy_" 4612 "attach failed\n", unit); 4613 err = 17; 4614 goto fail; 4615 } 4616 4617 wlc_phy_machwcap_set(wlc_hw->band->pi, wlc_hw->machwcap); 4618 4619 wlc_phy_get_phyversion(wlc_hw->band->pi, &wlc_hw->band->phytype, 4620 &wlc_hw->band->phyrev, 4621 &wlc_hw->band->radioid, 4622 &wlc_hw->band->radiorev); 4623 wlc_hw->band->abgphy_encore = 4624 wlc_phy_get_encore(wlc_hw->band->pi); 4625 wlc->band->abgphy_encore = wlc_phy_get_encore(wlc_hw->band->pi); 4626 wlc_hw->band->core_flags = 4627 wlc_phy_get_coreflags(wlc_hw->band->pi); 4628 4629 /* verify good phy_type & supported phy revision */ 4630 if (BRCMS_ISNPHY(wlc_hw->band)) { 4631 if (NCONF_HAS(wlc_hw->band->phyrev)) 4632 goto good_phy; 4633 else 4634 goto bad_phy; 4635 } else if (BRCMS_ISLCNPHY(wlc_hw->band)) { 4636 if (LCNCONF_HAS(wlc_hw->band->phyrev)) 4637 goto good_phy; 4638 else 4639 goto bad_phy; 4640 } else { 4641 bad_phy: 4642 wiphy_err(wiphy, "wl%d: brcms_b_attach: unsupported " 4643 "phy type/rev (%d/%d)\n", unit, 4644 wlc_hw->band->phytype, wlc_hw->band->phyrev); 4645 err = 18; 4646 goto fail; 4647 } 4648 4649 good_phy: 4650 /* 4651 * BMAC_NOTE: wlc->band->pi should not be set below and should 4652 * be done in the high level attach. However we can not make 4653 * that change until all low level access is changed to 4654 * wlc_hw->band->pi. Instead do the wlc->band->pi init below, 4655 * keeping wlc_hw->band->pi as well for incremental update of 4656 * low level fns, and cut over low only init when all fns 4657 * updated. 4658 */ 4659 wlc->band->pi = wlc_hw->band->pi; 4660 wlc->band->phytype = wlc_hw->band->phytype; 4661 wlc->band->phyrev = wlc_hw->band->phyrev; 4662 wlc->band->radioid = wlc_hw->band->radioid; 4663 wlc->band->radiorev = wlc_hw->band->radiorev; 4664 4665 /* default contention windows size limits */ 4666 wlc_hw->band->CWmin = APHY_CWMIN; 4667 wlc_hw->band->CWmax = PHY_CWMAX; 4668 4669 if (!brcms_b_attach_dmapio(wlc, j, wme)) { 4670 err = 19; 4671 goto fail; 4672 } 4673 } 4674 4675 /* disable core to match driver "down" state */ 4676 brcms_c_coredisable(wlc_hw); 4677 4678 /* Match driver "down" state */ 4679 ai_pci_down(wlc_hw->sih); 4680 4681 /* turn off pll and xtal to match driver "down" state */ 4682 brcms_b_xtal(wlc_hw, OFF); 4683 4684 /* ******************************************************************* 4685 * The hardware is in the DOWN state at this point. D11 core 4686 * or cores are in reset with clocks off, and the board PLLs 4687 * are off if possible. 4688 * 4689 * Beyond this point, wlc->sbclk == false and chip registers 4690 * should not be touched. 4691 ********************************************************************* 4692 */ 4693 4694 /* init etheraddr state variables */ 4695 brcms_c_get_macaddr(wlc_hw, wlc_hw->etheraddr); 4696 4697 if (is_broadcast_ether_addr(wlc_hw->etheraddr) || 4698 is_zero_ether_addr(wlc_hw->etheraddr)) { 4699 wiphy_err(wiphy, "wl%d: brcms_b_attach: bad macaddr\n", 4700 unit); 4701 err = 22; 4702 goto fail; 4703 } 4704 4705 brcms_dbg_info(wlc_hw->d11core, "deviceid 0x%x nbands %d board 0x%x\n", 4706 wlc_hw->deviceid, wlc_hw->_nbands, 4707 ai_get_boardtype(wlc_hw->sih)); 4708 4709 return err; 4710 4711 fail: 4712 wiphy_err(wiphy, "wl%d: brcms_b_attach: failed with err %d\n", unit, 4713 err); 4714 return err; 4715} 4716 4717static void brcms_c_attach_antgain_init(struct brcms_c_info *wlc) 4718{ 4719 uint unit; 4720 unit = wlc->pub->unit; 4721 4722 if ((wlc->band->antgain == -1) && (wlc->pub->sromrev == 1)) { 4723 /* default antenna gain for srom rev 1 is 2 dBm (8 qdbm) */ 4724 wlc->band->antgain = 8; 4725 } else if (wlc->band->antgain == -1) { 4726 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid antennas available in" 4727 " srom, using 2dB\n", unit, __func__); 4728 wlc->band->antgain = 8; 4729 } else { 4730 s8 gain, fract; 4731 /* Older sroms specified gain in whole dbm only. In order 4732 * be able to specify qdbm granularity and remain backward 4733 * compatible the whole dbms are now encoded in only 4734 * low 6 bits and remaining qdbms are encoded in the hi 2 bits. 4735 * 6 bit signed number ranges from -32 - 31. 4736 * 4737 * Examples: 4738 * 0x1 = 1 db, 4739 * 0xc1 = 1.75 db (1 + 3 quarters), 4740 * 0x3f = -1 (-1 + 0 quarters), 4741 * 0x7f = -.75 (-1 + 1 quarters) = -3 qdbm. 4742 * 0xbf = -.50 (-1 + 2 quarters) = -2 qdbm. 4743 */ 4744 gain = wlc->band->antgain & 0x3f; 4745 gain <<= 2; /* Sign extend */ 4746 gain >>= 2; 4747 fract = (wlc->band->antgain & 0xc0) >> 6; 4748 wlc->band->antgain = 4 * gain + fract; 4749 } 4750} 4751 4752static bool brcms_c_attach_stf_ant_init(struct brcms_c_info *wlc) 4753{ 4754 int aa; 4755 uint unit; 4756 int bandtype; 4757 struct ssb_sprom *sprom = &wlc->hw->d11core->bus->sprom; 4758 4759 unit = wlc->pub->unit; 4760 bandtype = wlc->band->bandtype; 4761 4762 /* get antennas available */ 4763 if (bandtype == BRCM_BAND_5G) 4764 aa = sprom->ant_available_a; 4765 else 4766 aa = sprom->ant_available_bg; 4767 4768 if ((aa < 1) || (aa > 15)) { 4769 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid antennas available in" 4770 " srom (0x%x), using 3\n", unit, __func__, aa); 4771 aa = 3; 4772 } 4773 4774 /* reset the defaults if we have a single antenna */ 4775 if (aa == 1) { 4776 wlc->stf->ant_rx_ovr = ANT_RX_DIV_FORCE_0; 4777 wlc->stf->txant = ANT_TX_FORCE_0; 4778 } else if (aa == 2) { 4779 wlc->stf->ant_rx_ovr = ANT_RX_DIV_FORCE_1; 4780 wlc->stf->txant = ANT_TX_FORCE_1; 4781 } else { 4782 } 4783 4784 /* Compute Antenna Gain */ 4785 if (bandtype == BRCM_BAND_5G) 4786 wlc->band->antgain = sprom->antenna_gain.a1; 4787 else 4788 wlc->band->antgain = sprom->antenna_gain.a0; 4789 4790 brcms_c_attach_antgain_init(wlc); 4791 4792 return true; 4793} 4794 4795static void brcms_c_bss_default_init(struct brcms_c_info *wlc) 4796{ 4797 u16 chanspec; 4798 struct brcms_band *band; 4799 struct brcms_bss_info *bi = wlc->default_bss; 4800 4801 /* init default and target BSS with some sane initial values */ 4802 memset((char *)(bi), 0, sizeof(struct brcms_bss_info)); 4803 bi->beacon_period = BEACON_INTERVAL_DEFAULT; 4804 4805 /* fill the default channel as the first valid channel 4806 * starting from the 2G channels 4807 */ 4808 chanspec = ch20mhz_chspec(1); 4809 wlc->home_chanspec = bi->chanspec = chanspec; 4810 4811 /* find the band of our default channel */ 4812 band = wlc->band; 4813 if (wlc->pub->_nbands > 1 && 4814 band->bandunit != chspec_bandunit(chanspec)) 4815 band = wlc->bandstate[OTHERBANDUNIT(wlc)]; 4816 4817 /* init bss rates to the band specific default rate set */ 4818 brcms_c_rateset_default(&bi->rateset, NULL, band->phytype, 4819 band->bandtype, false, BRCMS_RATE_MASK_FULL, 4820 (bool) (wlc->pub->_n_enab & SUPPORT_11N), 4821 brcms_chspec_bw(chanspec), wlc->stf->txstreams); 4822 4823 if (wlc->pub->_n_enab & SUPPORT_11N) 4824 bi->flags |= BRCMS_BSS_HT; 4825} 4826 4827static void brcms_c_update_mimo_band_bwcap(struct brcms_c_info *wlc, u8 bwcap) 4828{ 4829 uint i; 4830 struct brcms_band *band; 4831 4832 for (i = 0; i < wlc->pub->_nbands; i++) { 4833 band = wlc->bandstate[i]; 4834 if (band->bandtype == BRCM_BAND_5G) { 4835 if ((bwcap == BRCMS_N_BW_40ALL) 4836 || (bwcap == BRCMS_N_BW_20IN2G_40IN5G)) 4837 band->mimo_cap_40 = true; 4838 else 4839 band->mimo_cap_40 = false; 4840 } else { 4841 if (bwcap == BRCMS_N_BW_40ALL) 4842 band->mimo_cap_40 = true; 4843 else 4844 band->mimo_cap_40 = false; 4845 } 4846 } 4847} 4848 4849static void brcms_c_timers_deinit(struct brcms_c_info *wlc) 4850{ 4851 /* free timer state */ 4852 if (wlc->wdtimer) { 4853 brcms_free_timer(wlc->wdtimer); 4854 wlc->wdtimer = NULL; 4855 } 4856 if (wlc->radio_timer) { 4857 brcms_free_timer(wlc->radio_timer); 4858 wlc->radio_timer = NULL; 4859 } 4860} 4861 4862static void brcms_c_detach_module(struct brcms_c_info *wlc) 4863{ 4864 if (wlc->asi) { 4865 brcms_c_antsel_detach(wlc->asi); 4866 wlc->asi = NULL; 4867 } 4868 4869 if (wlc->ampdu) { 4870 brcms_c_ampdu_detach(wlc->ampdu); 4871 wlc->ampdu = NULL; 4872 } 4873 4874 brcms_c_stf_detach(wlc); 4875} 4876 4877/* 4878 * low level detach 4879 */ 4880static int brcms_b_detach(struct brcms_c_info *wlc) 4881{ 4882 uint i; 4883 struct brcms_hw_band *band; 4884 struct brcms_hardware *wlc_hw = wlc->hw; 4885 int callbacks; 4886 4887 callbacks = 0; 4888 4889 brcms_b_detach_dmapio(wlc_hw); 4890 4891 band = wlc_hw->band; 4892 for (i = 0; i < wlc_hw->_nbands; i++) { 4893 if (band->pi) { 4894 /* Detach this band's phy */ 4895 wlc_phy_detach(band->pi); 4896 band->pi = NULL; 4897 } 4898 band = wlc_hw->bandstate[OTHERBANDUNIT(wlc)]; 4899 } 4900 4901 /* Free shared phy state */ 4902 kfree(wlc_hw->phy_sh); 4903 4904 wlc_phy_shim_detach(wlc_hw->physhim); 4905 4906 if (wlc_hw->sih) { 4907 ai_detach(wlc_hw->sih); 4908 wlc_hw->sih = NULL; 4909 } 4910 4911 return callbacks; 4912 4913} 4914 4915/* 4916 * Return a count of the number of driver callbacks still pending. 4917 * 4918 * General policy is that brcms_c_detach can only dealloc/free software states. 4919 * It can NOT touch hardware registers since the d11core may be in reset and 4920 * clock may not be available. 4921 * One exception is sb register access, which is possible if crystal is turned 4922 * on after "down" state, driver should avoid software timer with the exception 4923 * of radio_monitor. 4924 */ 4925uint brcms_c_detach(struct brcms_c_info *wlc) 4926{ 4927 uint callbacks = 0; 4928 4929 if (wlc == NULL) 4930 return 0; 4931 4932 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit); 4933 4934 callbacks += brcms_b_detach(wlc); 4935 4936 /* delete software timers */ 4937 if (!brcms_c_radio_monitor_stop(wlc)) 4938 callbacks++; 4939 4940 brcms_c_channel_mgr_detach(wlc->cmi); 4941 4942 brcms_c_timers_deinit(wlc); 4943 4944 brcms_c_detach_module(wlc); 4945 4946 brcms_c_detach_mfree(wlc); 4947 return callbacks; 4948} 4949 4950/* update state that depends on the current value of "ap" */ 4951static void brcms_c_ap_upd(struct brcms_c_info *wlc) 4952{ 4953 /* STA-BSS; short capable */ 4954 wlc->PLCPHdr_override = BRCMS_PLCP_SHORT; 4955} 4956 4957/* Initialize just the hardware when coming out of POR or S3/S5 system states */ 4958static void brcms_b_hw_up(struct brcms_hardware *wlc_hw) 4959{ 4960 if (wlc_hw->wlc->pub->hw_up) 4961 return; 4962 4963 brcms_dbg_info(wlc_hw->d11core, "wl%d\n", wlc_hw->unit); 4964 4965 /* 4966 * Enable pll and xtal, initialize the power control registers, 4967 * and force fastclock for the remainder of brcms_c_up(). 4968 */ 4969 brcms_b_xtal(wlc_hw, ON); 4970 ai_clkctl_init(wlc_hw->sih); 4971 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST); 4972 4973 /* 4974 * TODO: test suspend/resume 4975 * 4976 * AI chip doesn't restore bar0win2 on 4977 * hibernation/resume, need sw fixup 4978 */ 4979 4980 /* 4981 * Inform phy that a POR reset has occurred so 4982 * it does a complete phy init 4983 */ 4984 wlc_phy_por_inform(wlc_hw->band->pi); 4985 4986 wlc_hw->ucode_loaded = false; 4987 wlc_hw->wlc->pub->hw_up = true; 4988 4989 if ((wlc_hw->boardflags & BFL_FEM) 4990 && (ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM4313)) { 4991 if (! 4992 (wlc_hw->boardrev >= 0x1250 4993 && (wlc_hw->boardflags & BFL_FEM_BT))) 4994 ai_epa_4313war(wlc_hw->sih); 4995 } 4996} 4997 4998static int brcms_b_up_prep(struct brcms_hardware *wlc_hw) 4999{ 5000 brcms_dbg_info(wlc_hw->d11core, "wl%d\n", wlc_hw->unit); 5001 5002 /* 5003 * Enable pll and xtal, initialize the power control registers, 5004 * and force fastclock for the remainder of brcms_c_up(). 5005 */ 5006 brcms_b_xtal(wlc_hw, ON); 5007 ai_clkctl_init(wlc_hw->sih); 5008 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST); 5009 5010 /* 5011 * Configure pci/pcmcia here instead of in brcms_c_attach() 5012 * to allow mfg hotswap: down, hotswap (chip power cycle), up. 5013 */ 5014 bcma_core_pci_irq_ctl(&wlc_hw->d11core->bus->drv_pci[0], wlc_hw->d11core, 5015 true); 5016 5017 /* 5018 * Need to read the hwradio status here to cover the case where the 5019 * system is loaded with the hw radio disabled. We do not want to 5020 * bring the driver up in this case. 5021 */ 5022 if (brcms_b_radio_read_hwdisabled(wlc_hw)) { 5023 /* put SB PCI in down state again */ 5024 ai_pci_down(wlc_hw->sih); 5025 brcms_b_xtal(wlc_hw, OFF); 5026 return -ENOMEDIUM; 5027 } 5028 5029 ai_pci_up(wlc_hw->sih); 5030 5031 /* reset the d11 core */ 5032 brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS); 5033 5034 return 0; 5035} 5036 5037static int brcms_b_up_finish(struct brcms_hardware *wlc_hw) 5038{ 5039 wlc_hw->up = true; 5040 wlc_phy_hw_state_upd(wlc_hw->band->pi, true); 5041 5042 /* FULLY enable dynamic power control and d11 core interrupt */ 5043 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC); 5044 brcms_intrson(wlc_hw->wlc->wl); 5045 return 0; 5046} 5047 5048/* 5049 * Write WME tunable parameters for retransmit/max rate 5050 * from wlc struct to ucode 5051 */ 5052static void brcms_c_wme_retries_write(struct brcms_c_info *wlc) 5053{ 5054 int ac; 5055 5056 /* Need clock to do this */ 5057 if (!wlc->clk) 5058 return; 5059 5060 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) 5061 brcms_b_write_shm(wlc->hw, M_AC_TXLMT_ADDR(ac), 5062 wlc->wme_retries[ac]); 5063} 5064 5065/* make interface operational */ 5066int brcms_c_up(struct brcms_c_info *wlc) 5067{ 5068 struct ieee80211_channel *ch; 5069 5070 brcms_dbg_info(wlc->hw->d11core, "wl%d\n", wlc->pub->unit); 5071 5072 /* HW is turned off so don't try to access it */ 5073 if (wlc->pub->hw_off || brcms_deviceremoved(wlc)) 5074 return -ENOMEDIUM; 5075 5076 if (!wlc->pub->hw_up) { 5077 brcms_b_hw_up(wlc->hw); 5078 wlc->pub->hw_up = true; 5079 } 5080 5081 if ((wlc->pub->boardflags & BFL_FEM) 5082 && (ai_get_chip_id(wlc->hw->sih) == BCMA_CHIP_ID_BCM4313)) { 5083 if (wlc->pub->boardrev >= 0x1250 5084 && (wlc->pub->boardflags & BFL_FEM_BT)) 5085 brcms_b_mhf(wlc->hw, MHF5, MHF5_4313_GPIOCTRL, 5086 MHF5_4313_GPIOCTRL, BRCM_BAND_ALL); 5087 else 5088 brcms_b_mhf(wlc->hw, MHF4, MHF4_EXTPA_ENABLE, 5089 MHF4_EXTPA_ENABLE, BRCM_BAND_ALL); 5090 } 5091 5092 /* 5093 * Need to read the hwradio status here to cover the case where the 5094 * system is loaded with the hw radio disabled. We do not want to bring 5095 * the driver up in this case. If radio is disabled, abort up, lower 5096 * power, start radio timer and return 0(for NDIS) don't call 5097 * radio_update to avoid looping brcms_c_up. 5098 * 5099 * brcms_b_up_prep() returns either 0 or -BCME_RADIOOFF only 5100 */ 5101 if (!wlc->pub->radio_disabled) { 5102 int status = brcms_b_up_prep(wlc->hw); 5103 if (status == -ENOMEDIUM) { 5104 if (!mboolisset 5105 (wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE)) { 5106 struct brcms_bss_cfg *bsscfg = wlc->bsscfg; 5107 mboolset(wlc->pub->radio_disabled, 5108 WL_RADIO_HW_DISABLE); 5109 5110 if (bsscfg->enable && bsscfg->BSS) 5111 brcms_err(wlc->hw->d11core, 5112 "wl%d: up: rfdisable -> " 5113 "bsscfg_disable()\n", 5114 wlc->pub->unit); 5115 } 5116 } 5117 } 5118 5119 if (wlc->pub->radio_disabled) { 5120 brcms_c_radio_monitor_start(wlc); 5121 return 0; 5122 } 5123 5124 /* brcms_b_up_prep has done brcms_c_corereset(). so clk is on, set it */ 5125 wlc->clk = true; 5126 5127 brcms_c_radio_monitor_stop(wlc); 5128 5129 /* Set EDCF hostflags */ 5130 brcms_b_mhf(wlc->hw, MHF1, MHF1_EDCF, MHF1_EDCF, BRCM_BAND_ALL); 5131 5132 brcms_init(wlc->wl); 5133 wlc->pub->up = true; 5134 5135 if (wlc->bandinit_pending) { 5136 ch = wlc->pub->ieee_hw->conf.channel; 5137 brcms_c_suspend_mac_and_wait(wlc); 5138 brcms_c_set_chanspec(wlc, ch20mhz_chspec(ch->hw_value)); 5139 wlc->bandinit_pending = false; 5140 brcms_c_enable_mac(wlc); 5141 } 5142 5143 brcms_b_up_finish(wlc->hw); 5144 5145 /* Program the TX wme params with the current settings */ 5146 brcms_c_wme_retries_write(wlc); 5147 5148 /* start one second watchdog timer */ 5149 brcms_add_timer(wlc->wdtimer, TIMER_INTERVAL_WATCHDOG, true); 5150 wlc->WDarmed = true; 5151 5152 /* ensure antenna config is up to date */ 5153 brcms_c_stf_phy_txant_upd(wlc); 5154 /* ensure LDPC config is in sync */ 5155 brcms_c_ht_update_ldpc(wlc, wlc->stf->ldpc); 5156 5157 return 0; 5158} 5159 5160static uint brcms_c_down_del_timer(struct brcms_c_info *wlc) 5161{ 5162 uint callbacks = 0; 5163 5164 return callbacks; 5165} 5166 5167static int brcms_b_bmac_down_prep(struct brcms_hardware *wlc_hw) 5168{ 5169 bool dev_gone; 5170 uint callbacks = 0; 5171 5172 if (!wlc_hw->up) 5173 return callbacks; 5174 5175 dev_gone = brcms_deviceremoved(wlc_hw->wlc); 5176 5177 /* disable interrupts */ 5178 if (dev_gone) 5179 wlc_hw->wlc->macintmask = 0; 5180 else { 5181 /* now disable interrupts */ 5182 brcms_intrsoff(wlc_hw->wlc->wl); 5183 5184 /* ensure we're running on the pll clock again */ 5185 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST); 5186 } 5187 /* down phy at the last of this stage */ 5188 callbacks += wlc_phy_down(wlc_hw->band->pi); 5189 5190 return callbacks; 5191} 5192 5193static int brcms_b_down_finish(struct brcms_hardware *wlc_hw) 5194{ 5195 uint callbacks = 0; 5196 bool dev_gone; 5197 5198 if (!wlc_hw->up) 5199 return callbacks; 5200 5201 wlc_hw->up = false; 5202 wlc_phy_hw_state_upd(wlc_hw->band->pi, false); 5203 5204 dev_gone = brcms_deviceremoved(wlc_hw->wlc); 5205 5206 if (dev_gone) { 5207 wlc_hw->sbclk = false; 5208 wlc_hw->clk = false; 5209 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false); 5210 5211 /* reclaim any posted packets */ 5212 brcms_c_flushqueues(wlc_hw->wlc); 5213 } else { 5214 5215 /* Reset and disable the core */ 5216 if (bcma_core_is_enabled(wlc_hw->d11core)) { 5217 if (bcma_read32(wlc_hw->d11core, 5218 D11REGOFFS(maccontrol)) & MCTL_EN_MAC) 5219 brcms_c_suspend_mac_and_wait(wlc_hw->wlc); 5220 callbacks += brcms_reset(wlc_hw->wlc->wl); 5221 brcms_c_coredisable(wlc_hw); 5222 } 5223 5224 /* turn off primary xtal and pll */ 5225 if (!wlc_hw->noreset) { 5226 ai_pci_down(wlc_hw->sih); 5227 brcms_b_xtal(wlc_hw, OFF); 5228 } 5229 } 5230 5231 return callbacks; 5232} 5233 5234/* 5235 * Mark the interface nonoperational, stop the software mechanisms, 5236 * disable the hardware, free any transient buffer state. 5237 * Return a count of the number of driver callbacks still pending. 5238 */ 5239uint brcms_c_down(struct brcms_c_info *wlc) 5240{ 5241 5242 uint callbacks = 0; 5243 int i; 5244 bool dev_gone = false; 5245 5246 brcms_dbg_info(wlc->hw->d11core, "wl%d\n", wlc->pub->unit); 5247 5248 /* check if we are already in the going down path */ 5249 if (wlc->going_down) { 5250 brcms_err(wlc->hw->d11core, 5251 "wl%d: %s: Driver going down so return\n", 5252 wlc->pub->unit, __func__); 5253 return 0; 5254 } 5255 if (!wlc->pub->up) 5256 return callbacks; 5257 5258 wlc->going_down = true; 5259 5260 callbacks += brcms_b_bmac_down_prep(wlc->hw); 5261 5262 dev_gone = brcms_deviceremoved(wlc); 5263 5264 /* Call any registered down handlers */ 5265 for (i = 0; i < BRCMS_MAXMODULES; i++) { 5266 if (wlc->modulecb[i].down_fn) 5267 callbacks += 5268 wlc->modulecb[i].down_fn(wlc->modulecb[i].hdl); 5269 } 5270 5271 /* cancel the watchdog timer */ 5272 if (wlc->WDarmed) { 5273 if (!brcms_del_timer(wlc->wdtimer)) 5274 callbacks++; 5275 wlc->WDarmed = false; 5276 } 5277 /* cancel all other timers */ 5278 callbacks += brcms_c_down_del_timer(wlc); 5279 5280 wlc->pub->up = false; 5281 5282 wlc_phy_mute_upd(wlc->band->pi, false, PHY_MUTE_ALL); 5283 5284 callbacks += brcms_b_down_finish(wlc->hw); 5285 5286 /* brcms_b_down_finish has done brcms_c_coredisable(). so clk is off */ 5287 wlc->clk = false; 5288 5289 wlc->going_down = false; 5290 return callbacks; 5291} 5292 5293/* Set the current gmode configuration */ 5294int brcms_c_set_gmode(struct brcms_c_info *wlc, u8 gmode, bool config) 5295{ 5296 int ret = 0; 5297 uint i; 5298 struct brcms_c_rateset rs; 5299 /* Default to 54g Auto */ 5300 /* Advertise and use shortslot (-1/0/1 Auto/Off/On) */ 5301 s8 shortslot = BRCMS_SHORTSLOT_AUTO; 5302 bool shortslot_restrict = false; /* Restrict association to stations 5303 * that support shortslot 5304 */ 5305 bool ofdm_basic = false; /* Make 6, 12, and 24 basic rates */ 5306 /* Advertise and use short preambles (-1/0/1 Auto/Off/On) */ 5307 int preamble = BRCMS_PLCP_LONG; 5308 bool preamble_restrict = false; /* Restrict association to stations 5309 * that support short preambles 5310 */ 5311 struct brcms_band *band; 5312 5313 /* if N-support is enabled, allow Gmode set as long as requested 5314 * Gmode is not GMODE_LEGACY_B 5315 */ 5316 if ((wlc->pub->_n_enab & SUPPORT_11N) && gmode == GMODE_LEGACY_B) 5317 return -ENOTSUPP; 5318 5319 /* verify that we are dealing with 2G band and grab the band pointer */ 5320 if (wlc->band->bandtype == BRCM_BAND_2G) 5321 band = wlc->band; 5322 else if ((wlc->pub->_nbands > 1) && 5323 (wlc->bandstate[OTHERBANDUNIT(wlc)]->bandtype == BRCM_BAND_2G)) 5324 band = wlc->bandstate[OTHERBANDUNIT(wlc)]; 5325 else 5326 return -EINVAL; 5327 5328 /* update configuration value */ 5329 if (config) 5330 brcms_c_protection_upd(wlc, BRCMS_PROT_G_USER, gmode); 5331 5332 /* Clear rateset override */ 5333 memset(&rs, 0, sizeof(struct brcms_c_rateset)); 5334 5335 switch (gmode) { 5336 case GMODE_LEGACY_B: 5337 shortslot = BRCMS_SHORTSLOT_OFF; 5338 brcms_c_rateset_copy(&gphy_legacy_rates, &rs); 5339 5340 break; 5341 5342 case GMODE_LRS: 5343 break; 5344 5345 case GMODE_AUTO: 5346 /* Accept defaults */ 5347 break; 5348 5349 case GMODE_ONLY: 5350 ofdm_basic = true; 5351 preamble = BRCMS_PLCP_SHORT; 5352 preamble_restrict = true; 5353 break; 5354 5355 case GMODE_PERFORMANCE: 5356 shortslot = BRCMS_SHORTSLOT_ON; 5357 shortslot_restrict = true; 5358 ofdm_basic = true; 5359 preamble = BRCMS_PLCP_SHORT; 5360 preamble_restrict = true; 5361 break; 5362 5363 default: 5364 /* Error */ 5365 brcms_err(wlc->hw->d11core, "wl%d: %s: invalid gmode %d\n", 5366 wlc->pub->unit, __func__, gmode); 5367 return -ENOTSUPP; 5368 } 5369 5370 band->gmode = gmode; 5371 5372 wlc->shortslot_override = shortslot; 5373 5374 /* Use the default 11g rateset */ 5375 if (!rs.count) 5376 brcms_c_rateset_copy(&cck_ofdm_rates, &rs); 5377 5378 if (ofdm_basic) { 5379 for (i = 0; i < rs.count; i++) { 5380 if (rs.rates[i] == BRCM_RATE_6M 5381 || rs.rates[i] == BRCM_RATE_12M 5382 || rs.rates[i] == BRCM_RATE_24M) 5383 rs.rates[i] |= BRCMS_RATE_FLAG; 5384 } 5385 } 5386 5387 /* Set default bss rateset */ 5388 wlc->default_bss->rateset.count = rs.count; 5389 memcpy(wlc->default_bss->rateset.rates, rs.rates, 5390 sizeof(wlc->default_bss->rateset.rates)); 5391 5392 return ret; 5393} 5394 5395int brcms_c_set_nmode(struct brcms_c_info *wlc) 5396{ 5397 uint i; 5398 s32 nmode = AUTO; 5399 5400 if (wlc->stf->txstreams == WL_11N_3x3) 5401 nmode = WL_11N_3x3; 5402 else 5403 nmode = WL_11N_2x2; 5404 5405 /* force GMODE_AUTO if NMODE is ON */ 5406 brcms_c_set_gmode(wlc, GMODE_AUTO, true); 5407 if (nmode == WL_11N_3x3) 5408 wlc->pub->_n_enab = SUPPORT_HT; 5409 else 5410 wlc->pub->_n_enab = SUPPORT_11N; 5411 wlc->default_bss->flags |= BRCMS_BSS_HT; 5412 /* add the mcs rates to the default and hw ratesets */ 5413 brcms_c_rateset_mcs_build(&wlc->default_bss->rateset, 5414 wlc->stf->txstreams); 5415 for (i = 0; i < wlc->pub->_nbands; i++) 5416 memcpy(wlc->bandstate[i]->hw_rateset.mcs, 5417 wlc->default_bss->rateset.mcs, MCSSET_LEN); 5418 5419 return 0; 5420} 5421 5422static int 5423brcms_c_set_internal_rateset(struct brcms_c_info *wlc, 5424 struct brcms_c_rateset *rs_arg) 5425{ 5426 struct brcms_c_rateset rs, new; 5427 uint bandunit; 5428 5429 memcpy(&rs, rs_arg, sizeof(struct brcms_c_rateset)); 5430 5431 /* check for bad count value */ 5432 if ((rs.count == 0) || (rs.count > BRCMS_NUMRATES)) 5433 return -EINVAL; 5434 5435 /* try the current band */ 5436 bandunit = wlc->band->bandunit; 5437 memcpy(&new, &rs, sizeof(struct brcms_c_rateset)); 5438 if (brcms_c_rate_hwrs_filter_sort_validate 5439 (&new, &wlc->bandstate[bandunit]->hw_rateset, true, 5440 wlc->stf->txstreams)) 5441 goto good; 5442 5443 /* try the other band */ 5444 if (brcms_is_mband_unlocked(wlc)) { 5445 bandunit = OTHERBANDUNIT(wlc); 5446 memcpy(&new, &rs, sizeof(struct brcms_c_rateset)); 5447 if (brcms_c_rate_hwrs_filter_sort_validate(&new, 5448 &wlc-> 5449 bandstate[bandunit]-> 5450 hw_rateset, true, 5451 wlc->stf->txstreams)) 5452 goto good; 5453 } 5454 5455 return -EBADE; 5456 5457 good: 5458 /* apply new rateset */ 5459 memcpy(&wlc->default_bss->rateset, &new, 5460 sizeof(struct brcms_c_rateset)); 5461 memcpy(&wlc->bandstate[bandunit]->defrateset, &new, 5462 sizeof(struct brcms_c_rateset)); 5463 return 0; 5464} 5465 5466static void brcms_c_ofdm_rateset_war(struct brcms_c_info *wlc) 5467{ 5468 u8 r; 5469 bool war = false; 5470 5471 if (wlc->bsscfg->associated) 5472 r = wlc->bsscfg->current_bss->rateset.rates[0]; 5473 else 5474 r = wlc->default_bss->rateset.rates[0]; 5475 5476 wlc_phy_ofdm_rateset_war(wlc->band->pi, war); 5477} 5478 5479int brcms_c_set_channel(struct brcms_c_info *wlc, u16 channel) 5480{ 5481 u16 chspec = ch20mhz_chspec(channel); 5482 5483 if (channel < 0 || channel > MAXCHANNEL) 5484 return -EINVAL; 5485 5486 if (!brcms_c_valid_chanspec_db(wlc->cmi, chspec)) 5487 return -EINVAL; 5488 5489 5490 if (!wlc->pub->up && brcms_is_mband_unlocked(wlc)) { 5491 if (wlc->band->bandunit != chspec_bandunit(chspec)) 5492 wlc->bandinit_pending = true; 5493 else 5494 wlc->bandinit_pending = false; 5495 } 5496 5497 wlc->default_bss->chanspec = chspec; 5498 /* brcms_c_BSSinit() will sanitize the rateset before 5499 * using it.. */ 5500 if (wlc->pub->up && (wlc_phy_chanspec_get(wlc->band->pi) != chspec)) { 5501 brcms_c_set_home_chanspec(wlc, chspec); 5502 brcms_c_suspend_mac_and_wait(wlc); 5503 brcms_c_set_chanspec(wlc, chspec); 5504 brcms_c_enable_mac(wlc); 5505 } 5506 return 0; 5507} 5508 5509int brcms_c_set_rate_limit(struct brcms_c_info *wlc, u16 srl, u16 lrl) 5510{ 5511 int ac; 5512 5513 if (srl < 1 || srl > RETRY_SHORT_MAX || 5514 lrl < 1 || lrl > RETRY_SHORT_MAX) 5515 return -EINVAL; 5516 5517 wlc->SRL = srl; 5518 wlc->LRL = lrl; 5519 5520 brcms_b_retrylimit_upd(wlc->hw, wlc->SRL, wlc->LRL); 5521 5522 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) { 5523 wlc->wme_retries[ac] = SFIELD(wlc->wme_retries[ac], 5524 EDCF_SHORT, wlc->SRL); 5525 wlc->wme_retries[ac] = SFIELD(wlc->wme_retries[ac], 5526 EDCF_LONG, wlc->LRL); 5527 } 5528 brcms_c_wme_retries_write(wlc); 5529 5530 return 0; 5531} 5532 5533void brcms_c_get_current_rateset(struct brcms_c_info *wlc, 5534 struct brcm_rateset *currs) 5535{ 5536 struct brcms_c_rateset *rs; 5537 5538 if (wlc->pub->associated) 5539 rs = &wlc->bsscfg->current_bss->rateset; 5540 else 5541 rs = &wlc->default_bss->rateset; 5542 5543 /* Copy only legacy rateset section */ 5544 currs->count = rs->count; 5545 memcpy(&currs->rates, &rs->rates, rs->count); 5546} 5547 5548int brcms_c_set_rateset(struct brcms_c_info *wlc, struct brcm_rateset *rs) 5549{ 5550 struct brcms_c_rateset internal_rs; 5551 int bcmerror; 5552 5553 if (rs->count > BRCMS_NUMRATES) 5554 return -ENOBUFS; 5555 5556 memset(&internal_rs, 0, sizeof(struct brcms_c_rateset)); 5557 5558 /* Copy only legacy rateset section */ 5559 internal_rs.count = rs->count; 5560 memcpy(&internal_rs.rates, &rs->rates, internal_rs.count); 5561 5562 /* merge rateset coming in with the current mcsset */ 5563 if (wlc->pub->_n_enab & SUPPORT_11N) { 5564 struct brcms_bss_info *mcsset_bss; 5565 if (wlc->bsscfg->associated) 5566 mcsset_bss = wlc->bsscfg->current_bss; 5567 else 5568 mcsset_bss = wlc->default_bss; 5569 memcpy(internal_rs.mcs, &mcsset_bss->rateset.mcs[0], 5570 MCSSET_LEN); 5571 } 5572 5573 bcmerror = brcms_c_set_internal_rateset(wlc, &internal_rs); 5574 if (!bcmerror) 5575 brcms_c_ofdm_rateset_war(wlc); 5576 5577 return bcmerror; 5578} 5579 5580int brcms_c_set_beacon_period(struct brcms_c_info *wlc, u16 period) 5581{ 5582 if (period < DOT11_MIN_BEACON_PERIOD || 5583 period > DOT11_MAX_BEACON_PERIOD) 5584 return -EINVAL; 5585 5586 wlc->default_bss->beacon_period = period; 5587 return 0; 5588} 5589 5590u16 brcms_c_get_phy_type(struct brcms_c_info *wlc, int phyidx) 5591{ 5592 return wlc->band->phytype; 5593} 5594 5595void brcms_c_set_shortslot_override(struct brcms_c_info *wlc, s8 sslot_override) 5596{ 5597 wlc->shortslot_override = sslot_override; 5598 5599 /* 5600 * shortslot is an 11g feature, so no more work if we are 5601 * currently on the 5G band 5602 */ 5603 if (wlc->band->bandtype == BRCM_BAND_5G) 5604 return; 5605 5606 if (wlc->pub->up && wlc->pub->associated) { 5607 /* let watchdog or beacon processing update shortslot */ 5608 } else if (wlc->pub->up) { 5609 /* unassociated shortslot is off */ 5610 brcms_c_switch_shortslot(wlc, false); 5611 } else { 5612 /* driver is down, so just update the brcms_c_info 5613 * value */ 5614 if (wlc->shortslot_override == BRCMS_SHORTSLOT_AUTO) 5615 wlc->shortslot = false; 5616 else 5617 wlc->shortslot = 5618 (wlc->shortslot_override == 5619 BRCMS_SHORTSLOT_ON); 5620 } 5621} 5622 5623/* 5624 * register watchdog and down handlers. 5625 */ 5626int brcms_c_module_register(struct brcms_pub *pub, 5627 const char *name, struct brcms_info *hdl, 5628 int (*d_fn)(void *handle)) 5629{ 5630 struct brcms_c_info *wlc = (struct brcms_c_info *) pub->wlc; 5631 int i; 5632 5633 /* find an empty entry and just add, no duplication check! */ 5634 for (i = 0; i < BRCMS_MAXMODULES; i++) { 5635 if (wlc->modulecb[i].name[0] == '\0') { 5636 strncpy(wlc->modulecb[i].name, name, 5637 sizeof(wlc->modulecb[i].name) - 1); 5638 wlc->modulecb[i].hdl = hdl; 5639 wlc->modulecb[i].down_fn = d_fn; 5640 return 0; 5641 } 5642 } 5643 5644 return -ENOSR; 5645} 5646 5647/* unregister module callbacks */ 5648int brcms_c_module_unregister(struct brcms_pub *pub, const char *name, 5649 struct brcms_info *hdl) 5650{ 5651 struct brcms_c_info *wlc = (struct brcms_c_info *) pub->wlc; 5652 int i; 5653 5654 if (wlc == NULL) 5655 return -ENODATA; 5656 5657 for (i = 0; i < BRCMS_MAXMODULES; i++) { 5658 if (!strcmp(wlc->modulecb[i].name, name) && 5659 (wlc->modulecb[i].hdl == hdl)) { 5660 memset(&wlc->modulecb[i], 0, sizeof(struct modulecb)); 5661 return 0; 5662 } 5663 } 5664 5665 /* table not found! */ 5666 return -ENODATA; 5667} 5668 5669void brcms_c_print_txstatus(struct tx_status *txs) 5670{ 5671 pr_debug("\ntxpkt (MPDU) Complete\n"); 5672 5673 pr_debug("FrameID: %04x TxStatus: %04x\n", txs->frameid, txs->status); 5674 5675 pr_debug("[15:12] %d frame attempts\n", 5676 (txs->status & TX_STATUS_FRM_RTX_MASK) >> 5677 TX_STATUS_FRM_RTX_SHIFT); 5678 pr_debug(" [11:8] %d rts attempts\n", 5679 (txs->status & TX_STATUS_RTS_RTX_MASK) >> 5680 TX_STATUS_RTS_RTX_SHIFT); 5681 pr_debug(" [7] %d PM mode indicated\n", 5682 txs->status & TX_STATUS_PMINDCTD ? 1 : 0); 5683 pr_debug(" [6] %d intermediate status\n", 5684 txs->status & TX_STATUS_INTERMEDIATE ? 1 : 0); 5685 pr_debug(" [5] %d AMPDU\n", 5686 txs->status & TX_STATUS_AMPDU ? 1 : 0); 5687 pr_debug(" [4:2] %d Frame Suppressed Reason (%s)\n", 5688 (txs->status & TX_STATUS_SUPR_MASK) >> TX_STATUS_SUPR_SHIFT, 5689 (const char *[]) { 5690 "None", 5691 "PMQ Entry", 5692 "Flush request", 5693 "Previous frag failure", 5694 "Channel mismatch", 5695 "Lifetime Expiry", 5696 "Underflow" 5697 } [(txs->status & TX_STATUS_SUPR_MASK) >> 5698 TX_STATUS_SUPR_SHIFT]); 5699 pr_debug(" [1] %d acked\n", 5700 txs->status & TX_STATUS_ACK_RCV ? 1 : 0); 5701 5702 pr_debug("LastTxTime: %04x Seq: %04x PHYTxStatus: %04x RxAckRSSI: %04x RxAckSQ: %04x\n", 5703 txs->lasttxtime, txs->sequence, txs->phyerr, 5704 (txs->ackphyrxsh & PRXS1_JSSI_MASK) >> PRXS1_JSSI_SHIFT, 5705 (txs->ackphyrxsh & PRXS1_SQ_MASK) >> PRXS1_SQ_SHIFT); 5706} 5707 5708static bool brcms_c_chipmatch_pci(struct bcma_device *core) 5709{ 5710 struct pci_dev *pcidev = core->bus->host_pci; 5711 u16 vendor = pcidev->vendor; 5712 u16 device = pcidev->device; 5713 5714 if (vendor != PCI_VENDOR_ID_BROADCOM) { 5715 pr_err("unknown vendor id %04x\n", vendor); 5716 return false; 5717 } 5718 5719 if (device == BCM43224_D11N_ID_VEN1) 5720 return true; 5721 if ((device == BCM43224_D11N_ID) || (device == BCM43225_D11N2G_ID)) 5722 return true; 5723 if (device == BCM4313_D11N2G_ID) 5724 return true; 5725 if ((device == BCM43236_D11N_ID) || (device == BCM43236_D11N2G_ID)) 5726 return true; 5727 5728 pr_err("unknown device id %04x\n", device); 5729 return false; 5730} 5731 5732static bool brcms_c_chipmatch_soc(struct bcma_device *core) 5733{ 5734 struct bcma_chipinfo *chipinfo = &core->bus->chipinfo; 5735 5736 if (chipinfo->id == BCMA_CHIP_ID_BCM4716) 5737 return true; 5738 5739 pr_err("unknown chip id %04x\n", chipinfo->id); 5740 return false; 5741} 5742 5743bool brcms_c_chipmatch(struct bcma_device *core) 5744{ 5745 switch (core->bus->hosttype) { 5746 case BCMA_HOSTTYPE_PCI: 5747 return brcms_c_chipmatch_pci(core); 5748 case BCMA_HOSTTYPE_SOC: 5749 return brcms_c_chipmatch_soc(core); 5750 default: 5751 pr_err("unknown host type: %i\n", core->bus->hosttype); 5752 return false; 5753 } 5754} 5755 5756#if defined(DEBUG) 5757void brcms_c_print_txdesc(struct d11txh *txh) 5758{ 5759 u16 mtcl = le16_to_cpu(txh->MacTxControlLow); 5760 u16 mtch = le16_to_cpu(txh->MacTxControlHigh); 5761 u16 mfc = le16_to_cpu(txh->MacFrameControl); 5762 u16 tfest = le16_to_cpu(txh->TxFesTimeNormal); 5763 u16 ptcw = le16_to_cpu(txh->PhyTxControlWord); 5764 u16 ptcw_1 = le16_to_cpu(txh->PhyTxControlWord_1); 5765 u16 ptcw_1_Fbr = le16_to_cpu(txh->PhyTxControlWord_1_Fbr); 5766 u16 ptcw_1_Rts = le16_to_cpu(txh->PhyTxControlWord_1_Rts); 5767 u16 ptcw_1_FbrRts = le16_to_cpu(txh->PhyTxControlWord_1_FbrRts); 5768 u16 mainrates = le16_to_cpu(txh->MainRates); 5769 u16 xtraft = le16_to_cpu(txh->XtraFrameTypes); 5770 u8 *iv = txh->IV; 5771 u8 *ra = txh->TxFrameRA; 5772 u16 tfestfb = le16_to_cpu(txh->TxFesTimeFallback); 5773 u8 *rtspfb = txh->RTSPLCPFallback; 5774 u16 rtsdfb = le16_to_cpu(txh->RTSDurFallback); 5775 u8 *fragpfb = txh->FragPLCPFallback; 5776 u16 fragdfb = le16_to_cpu(txh->FragDurFallback); 5777 u16 mmodelen = le16_to_cpu(txh->MModeLen); 5778 u16 mmodefbrlen = le16_to_cpu(txh->MModeFbrLen); 5779 u16 tfid = le16_to_cpu(txh->TxFrameID); 5780 u16 txs = le16_to_cpu(txh->TxStatus); 5781 u16 mnmpdu = le16_to_cpu(txh->MaxNMpdus); 5782 u16 mabyte = le16_to_cpu(txh->MaxABytes_MRT); 5783 u16 mabyte_f = le16_to_cpu(txh->MaxABytes_FBR); 5784 u16 mmbyte = le16_to_cpu(txh->MinMBytes); 5785 5786 u8 *rtsph = txh->RTSPhyHeader; 5787 struct ieee80211_rts rts = txh->rts_frame; 5788 5789 /* add plcp header along with txh descriptor */ 5790 brcmu_dbg_hex_dump(txh, sizeof(struct d11txh) + 48, 5791 "Raw TxDesc + plcp header:\n"); 5792 5793 pr_debug("TxCtlLow: %04x ", mtcl); 5794 pr_debug("TxCtlHigh: %04x ", mtch); 5795 pr_debug("FC: %04x ", mfc); 5796 pr_debug("FES Time: %04x\n", tfest); 5797 pr_debug("PhyCtl: %04x%s ", ptcw, 5798 (ptcw & PHY_TXC_SHORT_HDR) ? " short" : ""); 5799 pr_debug("PhyCtl_1: %04x ", ptcw_1); 5800 pr_debug("PhyCtl_1_Fbr: %04x\n", ptcw_1_Fbr); 5801 pr_debug("PhyCtl_1_Rts: %04x ", ptcw_1_Rts); 5802 pr_debug("PhyCtl_1_Fbr_Rts: %04x\n", ptcw_1_FbrRts); 5803 pr_debug("MainRates: %04x ", mainrates); 5804 pr_debug("XtraFrameTypes: %04x ", xtraft); 5805 pr_debug("\n"); 5806 5807 print_hex_dump_bytes("SecIV:", DUMP_PREFIX_OFFSET, iv, sizeof(txh->IV)); 5808 print_hex_dump_bytes("RA:", DUMP_PREFIX_OFFSET, 5809 ra, sizeof(txh->TxFrameRA)); 5810 5811 pr_debug("Fb FES Time: %04x ", tfestfb); 5812 print_hex_dump_bytes("Fb RTS PLCP:", DUMP_PREFIX_OFFSET, 5813 rtspfb, sizeof(txh->RTSPLCPFallback)); 5814 pr_debug("RTS DUR: %04x ", rtsdfb); 5815 print_hex_dump_bytes("PLCP:", DUMP_PREFIX_OFFSET, 5816 fragpfb, sizeof(txh->FragPLCPFallback)); 5817 pr_debug("DUR: %04x", fragdfb); 5818 pr_debug("\n"); 5819 5820 pr_debug("MModeLen: %04x ", mmodelen); 5821 pr_debug("MModeFbrLen: %04x\n", mmodefbrlen); 5822 5823 pr_debug("FrameID: %04x\n", tfid); 5824 pr_debug("TxStatus: %04x\n", txs); 5825 5826 pr_debug("MaxNumMpdu: %04x\n", mnmpdu); 5827 pr_debug("MaxAggbyte: %04x\n", mabyte); 5828 pr_debug("MaxAggbyte_fb: %04x\n", mabyte_f); 5829 pr_debug("MinByte: %04x\n", mmbyte); 5830 5831 print_hex_dump_bytes("RTS PLCP:", DUMP_PREFIX_OFFSET, 5832 rtsph, sizeof(txh->RTSPhyHeader)); 5833 print_hex_dump_bytes("RTS Frame:", DUMP_PREFIX_OFFSET, 5834 (u8 *)&rts, sizeof(txh->rts_frame)); 5835 pr_debug("\n"); 5836} 5837#endif /* defined(DEBUG) */ 5838 5839#if defined(DEBUG) 5840static int 5841brcms_c_format_flags(const struct brcms_c_bit_desc *bd, u32 flags, char *buf, 5842 int len) 5843{ 5844 int i; 5845 char *p = buf; 5846 char hexstr[16]; 5847 int slen = 0, nlen = 0; 5848 u32 bit; 5849 const char *name; 5850 5851 if (len < 2 || !buf) 5852 return 0; 5853 5854 buf[0] = '\0'; 5855 5856 for (i = 0; flags != 0; i++) { 5857 bit = bd[i].bit; 5858 name = bd[i].name; 5859 if (bit == 0 && flags != 0) { 5860 /* print any unnamed bits */ 5861 snprintf(hexstr, 16, "0x%X", flags); 5862 name = hexstr; 5863 flags = 0; /* exit loop */ 5864 } else if ((flags & bit) == 0) 5865 continue; 5866 flags &= ~bit; 5867 nlen = strlen(name); 5868 slen += nlen; 5869 /* count btwn flag space */ 5870 if (flags != 0) 5871 slen += 1; 5872 /* need NULL char as well */ 5873 if (len <= slen) 5874 break; 5875 /* copy NULL char but don't count it */ 5876 strncpy(p, name, nlen + 1); 5877 p += nlen; 5878 /* copy btwn flag space and NULL char */ 5879 if (flags != 0) 5880 p += snprintf(p, 2, " "); 5881 len -= slen; 5882 } 5883 5884 /* indicate the str was too short */ 5885 if (flags != 0) { 5886 if (len < 2) 5887 p -= 2 - len; /* overwrite last char */ 5888 p += snprintf(p, 2, ">"); 5889 } 5890 5891 return (int)(p - buf); 5892} 5893#endif /* defined(DEBUG) */ 5894 5895#if defined(DEBUG) 5896void brcms_c_print_rxh(struct d11rxhdr *rxh) 5897{ 5898 u16 len = rxh->RxFrameSize; 5899 u16 phystatus_0 = rxh->PhyRxStatus_0; 5900 u16 phystatus_1 = rxh->PhyRxStatus_1; 5901 u16 phystatus_2 = rxh->PhyRxStatus_2; 5902 u16 phystatus_3 = rxh->PhyRxStatus_3; 5903 u16 macstatus1 = rxh->RxStatus1; 5904 u16 macstatus2 = rxh->RxStatus2; 5905 char flagstr[64]; 5906 char lenbuf[20]; 5907 static const struct brcms_c_bit_desc macstat_flags[] = { 5908 {RXS_FCSERR, "FCSErr"}, 5909 {RXS_RESPFRAMETX, "Reply"}, 5910 {RXS_PBPRES, "PADDING"}, 5911 {RXS_DECATMPT, "DeCr"}, 5912 {RXS_DECERR, "DeCrErr"}, 5913 {RXS_BCNSENT, "Bcn"}, 5914 {0, NULL} 5915 }; 5916 5917 brcmu_dbg_hex_dump(rxh, sizeof(struct d11rxhdr), "Raw RxDesc:\n"); 5918 5919 brcms_c_format_flags(macstat_flags, macstatus1, flagstr, 64); 5920 5921 snprintf(lenbuf, sizeof(lenbuf), "0x%x", len); 5922 5923 pr_debug("RxFrameSize: %6s (%d)%s\n", lenbuf, len, 5924 (rxh->PhyRxStatus_0 & PRXS0_SHORTH) ? " short preamble" : ""); 5925 pr_debug("RxPHYStatus: %04x %04x %04x %04x\n", 5926 phystatus_0, phystatus_1, phystatus_2, phystatus_3); 5927 pr_debug("RxMACStatus: %x %s\n", macstatus1, flagstr); 5928 pr_debug("RXMACaggtype: %x\n", 5929 (macstatus2 & RXS_AGGTYPE_MASK)); 5930 pr_debug("RxTSFTime: %04x\n", rxh->RxTSFTime); 5931} 5932#endif /* defined(DEBUG) */ 5933 5934u16 brcms_b_rate_shm_offset(struct brcms_hardware *wlc_hw, u8 rate) 5935{ 5936 u16 table_ptr; 5937 u8 phy_rate, index; 5938 5939 /* get the phy specific rate encoding for the PLCP SIGNAL field */ 5940 if (is_ofdm_rate(rate)) 5941 table_ptr = M_RT_DIRMAP_A; 5942 else 5943 table_ptr = M_RT_DIRMAP_B; 5944 5945 /* for a given rate, the LS-nibble of the PLCP SIGNAL field is 5946 * the index into the rate table. 5947 */ 5948 phy_rate = rate_info[rate] & BRCMS_RATE_MASK; 5949 index = phy_rate & 0xf; 5950 5951 /* Find the SHM pointer to the rate table entry by looking in the 5952 * Direct-map Table 5953 */ 5954 return 2 * brcms_b_read_shm(wlc_hw, table_ptr + (index * 2)); 5955} 5956 5957/* 5958 * bcmc_fid_generate: 5959 * Generate frame ID for a BCMC packet. The frag field is not used 5960 * for MC frames so is used as part of the sequence number. 5961 */ 5962static inline u16 5963bcmc_fid_generate(struct brcms_c_info *wlc, struct brcms_bss_cfg *bsscfg, 5964 struct d11txh *txh) 5965{ 5966 u16 frameid; 5967 5968 frameid = le16_to_cpu(txh->TxFrameID) & ~(TXFID_SEQ_MASK | 5969 TXFID_QUEUE_MASK); 5970 frameid |= 5971 (((wlc-> 5972 mc_fid_counter++) << TXFID_SEQ_SHIFT) & TXFID_SEQ_MASK) | 5973 TX_BCMC_FIFO; 5974 5975 return frameid; 5976} 5977 5978static uint 5979brcms_c_calc_ack_time(struct brcms_c_info *wlc, u32 rspec, 5980 u8 preamble_type) 5981{ 5982 uint dur = 0; 5983 5984 brcms_dbg_mac80211(wlc->hw->d11core, 5985 "wl%d: rspec 0x%x, preamble_type %d\n", 5986 wlc->pub->unit, rspec, preamble_type); 5987 /* 5988 * Spec 9.6: ack rate is the highest rate in BSSBasicRateSet that 5989 * is less than or equal to the rate of the immediately previous 5990 * frame in the FES 5991 */ 5992 rspec = brcms_basic_rate(wlc, rspec); 5993 /* ACK frame len == 14 == 2(fc) + 2(dur) + 6(ra) + 4(fcs) */ 5994 dur = 5995 brcms_c_calc_frame_time(wlc, rspec, preamble_type, 5996 (DOT11_ACK_LEN + FCS_LEN)); 5997 return dur; 5998} 5999 6000static uint 6001brcms_c_calc_cts_time(struct brcms_c_info *wlc, u32 rspec, 6002 u8 preamble_type) 6003{ 6004 brcms_dbg_mac80211(wlc->hw->d11core, 6005 "wl%d: ratespec 0x%x, preamble_type %d\n", 6006 wlc->pub->unit, rspec, preamble_type); 6007 return brcms_c_calc_ack_time(wlc, rspec, preamble_type); 6008} 6009 6010static uint 6011brcms_c_calc_ba_time(struct brcms_c_info *wlc, u32 rspec, 6012 u8 preamble_type) 6013{ 6014 brcms_dbg_mac80211(wlc->hw->d11core, 6015 "wl%d: rspec 0x%x, preamble_type %d\n", 6016 wlc->pub->unit, rspec, preamble_type); 6017 /* 6018 * Spec 9.6: ack rate is the highest rate in BSSBasicRateSet that 6019 * is less than or equal to the rate of the immediately previous 6020 * frame in the FES 6021 */ 6022 rspec = brcms_basic_rate(wlc, rspec); 6023 /* BA len == 32 == 16(ctl hdr) + 4(ba len) + 8(bitmap) + 4(fcs) */ 6024 return brcms_c_calc_frame_time(wlc, rspec, preamble_type, 6025 (DOT11_BA_LEN + DOT11_BA_BITMAP_LEN + 6026 FCS_LEN)); 6027} 6028 6029/* brcms_c_compute_frame_dur() 6030 * 6031 * Calculate the 802.11 MAC header DUR field for MPDU 6032 * DUR for a single frame = 1 SIFS + 1 ACK 6033 * DUR for a frame with following frags = 3 SIFS + 2 ACK + next frag time 6034 * 6035 * rate MPDU rate in unit of 500kbps 6036 * next_frag_len next MPDU length in bytes 6037 * preamble_type use short/GF or long/MM PLCP header 6038 */ 6039static u16 6040brcms_c_compute_frame_dur(struct brcms_c_info *wlc, u32 rate, 6041 u8 preamble_type, uint next_frag_len) 6042{ 6043 u16 dur, sifs; 6044 6045 sifs = get_sifs(wlc->band); 6046 6047 dur = sifs; 6048 dur += (u16) brcms_c_calc_ack_time(wlc, rate, preamble_type); 6049 6050 if (next_frag_len) { 6051 /* Double the current DUR to get 2 SIFS + 2 ACKs */ 6052 dur *= 2; 6053 /* add another SIFS and the frag time */ 6054 dur += sifs; 6055 dur += 6056 (u16) brcms_c_calc_frame_time(wlc, rate, preamble_type, 6057 next_frag_len); 6058 } 6059 return dur; 6060} 6061 6062/* The opposite of brcms_c_calc_frame_time */ 6063static uint 6064brcms_c_calc_frame_len(struct brcms_c_info *wlc, u32 ratespec, 6065 u8 preamble_type, uint dur) 6066{ 6067 uint nsyms, mac_len, Ndps, kNdps; 6068 uint rate = rspec2rate(ratespec); 6069 6070 brcms_dbg_mac80211(wlc->hw->d11core, 6071 "wl%d: rspec 0x%x, preamble_type %d, dur %d\n", 6072 wlc->pub->unit, ratespec, preamble_type, dur); 6073 6074 if (is_mcs_rate(ratespec)) { 6075 uint mcs = ratespec & RSPEC_RATE_MASK; 6076 int tot_streams = mcs_2_txstreams(mcs) + rspec_stc(ratespec); 6077 dur -= PREN_PREAMBLE + (tot_streams * PREN_PREAMBLE_EXT); 6078 /* payload calculation matches that of regular ofdm */ 6079 if (wlc->band->bandtype == BRCM_BAND_2G) 6080 dur -= DOT11_OFDM_SIGNAL_EXTENSION; 6081 /* kNdbps = kbps * 4 */ 6082 kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec), 6083 rspec_issgi(ratespec)) * 4; 6084 nsyms = dur / APHY_SYMBOL_TIME; 6085 mac_len = 6086 ((nsyms * kNdps) - 6087 ((APHY_SERVICE_NBITS + APHY_TAIL_NBITS) * 1000)) / 8000; 6088 } else if (is_ofdm_rate(ratespec)) { 6089 dur -= APHY_PREAMBLE_TIME; 6090 dur -= APHY_SIGNAL_TIME; 6091 /* Ndbps = Mbps * 4 = rate(500Kbps) * 2 */ 6092 Ndps = rate * 2; 6093 nsyms = dur / APHY_SYMBOL_TIME; 6094 mac_len = 6095 ((nsyms * Ndps) - 6096 (APHY_SERVICE_NBITS + APHY_TAIL_NBITS)) / 8; 6097 } else { 6098 if (preamble_type & BRCMS_SHORT_PREAMBLE) 6099 dur -= BPHY_PLCP_SHORT_TIME; 6100 else 6101 dur -= BPHY_PLCP_TIME; 6102 mac_len = dur * rate; 6103 /* divide out factor of 2 in rate (1/2 mbps) */ 6104 mac_len = mac_len / 8 / 2; 6105 } 6106 return mac_len; 6107} 6108 6109/* 6110 * Return true if the specified rate is supported by the specified band. 6111 * BRCM_BAND_AUTO indicates the current band. 6112 */ 6113static bool brcms_c_valid_rate(struct brcms_c_info *wlc, u32 rspec, int band, 6114 bool verbose) 6115{ 6116 struct brcms_c_rateset *hw_rateset; 6117 uint i; 6118 6119 if ((band == BRCM_BAND_AUTO) || (band == wlc->band->bandtype)) 6120 hw_rateset = &wlc->band->hw_rateset; 6121 else if (wlc->pub->_nbands > 1) 6122 hw_rateset = &wlc->bandstate[OTHERBANDUNIT(wlc)]->hw_rateset; 6123 else 6124 /* other band specified and we are a single band device */ 6125 return false; 6126 6127 /* check if this is a mimo rate */ 6128 if (is_mcs_rate(rspec)) { 6129 if ((rspec & RSPEC_RATE_MASK) >= MCS_TABLE_SIZE) 6130 goto error; 6131 6132 return isset(hw_rateset->mcs, (rspec & RSPEC_RATE_MASK)); 6133 } 6134 6135 for (i = 0; i < hw_rateset->count; i++) 6136 if (hw_rateset->rates[i] == rspec2rate(rspec)) 6137 return true; 6138 error: 6139 if (verbose) 6140 brcms_err(wlc->hw->d11core, "wl%d: valid_rate: rate spec 0x%x " 6141 "not in hw_rateset\n", wlc->pub->unit, rspec); 6142 6143 return false; 6144} 6145 6146static u32 6147mac80211_wlc_set_nrate(struct brcms_c_info *wlc, struct brcms_band *cur_band, 6148 u32 int_val) 6149{ 6150 struct bcma_device *core = wlc->hw->d11core; 6151 u8 stf = (int_val & NRATE_STF_MASK) >> NRATE_STF_SHIFT; 6152 u8 rate = int_val & NRATE_RATE_MASK; 6153 u32 rspec; 6154 bool ismcs = ((int_val & NRATE_MCS_INUSE) == NRATE_MCS_INUSE); 6155 bool issgi = ((int_val & NRATE_SGI_MASK) >> NRATE_SGI_SHIFT); 6156 bool override_mcs_only = ((int_val & NRATE_OVERRIDE_MCS_ONLY) 6157 == NRATE_OVERRIDE_MCS_ONLY); 6158 int bcmerror = 0; 6159 6160 if (!ismcs) 6161 return (u32) rate; 6162 6163 /* validate the combination of rate/mcs/stf is allowed */ 6164 if ((wlc->pub->_n_enab & SUPPORT_11N) && ismcs) { 6165 /* mcs only allowed when nmode */ 6166 if (stf > PHY_TXC1_MODE_SDM) { 6167 brcms_err(core, "wl%d: %s: Invalid stf\n", 6168 wlc->pub->unit, __func__); 6169 bcmerror = -EINVAL; 6170 goto done; 6171 } 6172 6173 /* mcs 32 is a special case, DUP mode 40 only */ 6174 if (rate == 32) { 6175 if (!CHSPEC_IS40(wlc->home_chanspec) || 6176 ((stf != PHY_TXC1_MODE_SISO) 6177 && (stf != PHY_TXC1_MODE_CDD))) { 6178 brcms_err(core, "wl%d: %s: Invalid mcs 32\n", 6179 wlc->pub->unit, __func__); 6180 bcmerror = -EINVAL; 6181 goto done; 6182 } 6183 /* mcs > 7 must use stf SDM */ 6184 } else if (rate > HIGHEST_SINGLE_STREAM_MCS) { 6185 /* mcs > 7 must use stf SDM */ 6186 if (stf != PHY_TXC1_MODE_SDM) { 6187 brcms_dbg_mac80211(core, "wl%d: enabling " 6188 "SDM mode for mcs %d\n", 6189 wlc->pub->unit, rate); 6190 stf = PHY_TXC1_MODE_SDM; 6191 } 6192 } else { 6193 /* 6194 * MCS 0-7 may use SISO, CDD, and for 6195 * phy_rev >= 3 STBC 6196 */ 6197 if ((stf > PHY_TXC1_MODE_STBC) || 6198 (!BRCMS_STBC_CAP_PHY(wlc) 6199 && (stf == PHY_TXC1_MODE_STBC))) { 6200 brcms_err(core, "wl%d: %s: Invalid STBC\n", 6201 wlc->pub->unit, __func__); 6202 bcmerror = -EINVAL; 6203 goto done; 6204 } 6205 } 6206 } else if (is_ofdm_rate(rate)) { 6207 if ((stf != PHY_TXC1_MODE_CDD) && (stf != PHY_TXC1_MODE_SISO)) { 6208 brcms_err(core, "wl%d: %s: Invalid OFDM\n", 6209 wlc->pub->unit, __func__); 6210 bcmerror = -EINVAL; 6211 goto done; 6212 } 6213 } else if (is_cck_rate(rate)) { 6214 if ((cur_band->bandtype != BRCM_BAND_2G) 6215 || (stf != PHY_TXC1_MODE_SISO)) { 6216 brcms_err(core, "wl%d: %s: Invalid CCK\n", 6217 wlc->pub->unit, __func__); 6218 bcmerror = -EINVAL; 6219 goto done; 6220 } 6221 } else { 6222 brcms_err(core, "wl%d: %s: Unknown rate type\n", 6223 wlc->pub->unit, __func__); 6224 bcmerror = -EINVAL; 6225 goto done; 6226 } 6227 /* make sure multiple antennae are available for non-siso rates */ 6228 if ((stf != PHY_TXC1_MODE_SISO) && (wlc->stf->txstreams == 1)) { 6229 brcms_err(core, "wl%d: %s: SISO antenna but !SISO " 6230 "request\n", wlc->pub->unit, __func__); 6231 bcmerror = -EINVAL; 6232 goto done; 6233 } 6234 6235 rspec = rate; 6236 if (ismcs) { 6237 rspec |= RSPEC_MIMORATE; 6238 /* For STBC populate the STC field of the ratespec */ 6239 if (stf == PHY_TXC1_MODE_STBC) { 6240 u8 stc; 6241 stc = 1; /* Nss for single stream is always 1 */ 6242 rspec |= (stc << RSPEC_STC_SHIFT); 6243 } 6244 } 6245 6246 rspec |= (stf << RSPEC_STF_SHIFT); 6247 6248 if (override_mcs_only) 6249 rspec |= RSPEC_OVERRIDE_MCS_ONLY; 6250 6251 if (issgi) 6252 rspec |= RSPEC_SHORT_GI; 6253 6254 if ((rate != 0) 6255 && !brcms_c_valid_rate(wlc, rspec, cur_band->bandtype, true)) 6256 return rate; 6257 6258 return rspec; 6259done: 6260 return rate; 6261} 6262 6263/* 6264 * Compute PLCP, but only requires actual rate and length of pkt. 6265 * Rate is given in the driver standard multiple of 500 kbps. 6266 * le is set for 11 Mbps rate if necessary. 6267 * Broken out for PRQ. 6268 */ 6269 6270static void brcms_c_cck_plcp_set(struct brcms_c_info *wlc, int rate_500, 6271 uint length, u8 *plcp) 6272{ 6273 u16 usec = 0; 6274 u8 le = 0; 6275 6276 switch (rate_500) { 6277 case BRCM_RATE_1M: 6278 usec = length << 3; 6279 break; 6280 case BRCM_RATE_2M: 6281 usec = length << 2; 6282 break; 6283 case BRCM_RATE_5M5: 6284 usec = (length << 4) / 11; 6285 if ((length << 4) - (usec * 11) > 0) 6286 usec++; 6287 break; 6288 case BRCM_RATE_11M: 6289 usec = (length << 3) / 11; 6290 if ((length << 3) - (usec * 11) > 0) { 6291 usec++; 6292 if ((usec * 11) - (length << 3) >= 8) 6293 le = D11B_PLCP_SIGNAL_LE; 6294 } 6295 break; 6296 6297 default: 6298 brcms_err(wlc->hw->d11core, 6299 "brcms_c_cck_plcp_set: unsupported rate %d\n", 6300 rate_500); 6301 rate_500 = BRCM_RATE_1M; 6302 usec = length << 3; 6303 break; 6304 } 6305 /* PLCP signal byte */ 6306 plcp[0] = rate_500 * 5; /* r (500kbps) * 5 == r (100kbps) */ 6307 /* PLCP service byte */ 6308 plcp[1] = (u8) (le | D11B_PLCP_SIGNAL_LOCKED); 6309 /* PLCP length u16, little endian */ 6310 plcp[2] = usec & 0xff; 6311 plcp[3] = (usec >> 8) & 0xff; 6312 /* PLCP CRC16 */ 6313 plcp[4] = 0; 6314 plcp[5] = 0; 6315} 6316 6317/* Rate: 802.11 rate code, length: PSDU length in octets */ 6318static void brcms_c_compute_mimo_plcp(u32 rspec, uint length, u8 *plcp) 6319{ 6320 u8 mcs = (u8) (rspec & RSPEC_RATE_MASK); 6321 plcp[0] = mcs; 6322 if (rspec_is40mhz(rspec) || (mcs == 32)) 6323 plcp[0] |= MIMO_PLCP_40MHZ; 6324 BRCMS_SET_MIMO_PLCP_LEN(plcp, length); 6325 plcp[3] = rspec_mimoplcp3(rspec); /* rspec already holds this byte */ 6326 plcp[3] |= 0x7; /* set smoothing, not sounding ppdu & reserved */ 6327 plcp[4] = 0; /* number of extension spatial streams bit 0 & 1 */ 6328 plcp[5] = 0; 6329} 6330 6331/* Rate: 802.11 rate code, length: PSDU length in octets */ 6332static void 6333brcms_c_compute_ofdm_plcp(u32 rspec, u32 length, u8 *plcp) 6334{ 6335 u8 rate_signal; 6336 u32 tmp = 0; 6337 int rate = rspec2rate(rspec); 6338 6339 /* 6340 * encode rate per 802.11a-1999 sec 17.3.4.1, with lsb 6341 * transmitted first 6342 */ 6343 rate_signal = rate_info[rate] & BRCMS_RATE_MASK; 6344 memset(plcp, 0, D11_PHY_HDR_LEN); 6345 D11A_PHY_HDR_SRATE((struct ofdm_phy_hdr *) plcp, rate_signal); 6346 6347 tmp = (length & 0xfff) << 5; 6348 plcp[2] |= (tmp >> 16) & 0xff; 6349 plcp[1] |= (tmp >> 8) & 0xff; 6350 plcp[0] |= tmp & 0xff; 6351} 6352 6353/* Rate: 802.11 rate code, length: PSDU length in octets */ 6354static void brcms_c_compute_cck_plcp(struct brcms_c_info *wlc, u32 rspec, 6355 uint length, u8 *plcp) 6356{ 6357 int rate = rspec2rate(rspec); 6358 6359 brcms_c_cck_plcp_set(wlc, rate, length, plcp); 6360} 6361 6362static void 6363brcms_c_compute_plcp(struct brcms_c_info *wlc, u32 rspec, 6364 uint length, u8 *plcp) 6365{ 6366 if (is_mcs_rate(rspec)) 6367 brcms_c_compute_mimo_plcp(rspec, length, plcp); 6368 else if (is_ofdm_rate(rspec)) 6369 brcms_c_compute_ofdm_plcp(rspec, length, plcp); 6370 else 6371 brcms_c_compute_cck_plcp(wlc, rspec, length, plcp); 6372} 6373 6374/* brcms_c_compute_rtscts_dur() 6375 * 6376 * Calculate the 802.11 MAC header DUR field for an RTS or CTS frame 6377 * DUR for normal RTS/CTS w/ frame = 3 SIFS + 1 CTS + next frame time + 1 ACK 6378 * DUR for CTS-TO-SELF w/ frame = 2 SIFS + next frame time + 1 ACK 6379 * 6380 * cts cts-to-self or rts/cts 6381 * rts_rate rts or cts rate in unit of 500kbps 6382 * rate next MPDU rate in unit of 500kbps 6383 * frame_len next MPDU frame length in bytes 6384 */ 6385u16 6386brcms_c_compute_rtscts_dur(struct brcms_c_info *wlc, bool cts_only, 6387 u32 rts_rate, 6388 u32 frame_rate, u8 rts_preamble_type, 6389 u8 frame_preamble_type, uint frame_len, bool ba) 6390{ 6391 u16 dur, sifs; 6392 6393 sifs = get_sifs(wlc->band); 6394 6395 if (!cts_only) { 6396 /* RTS/CTS */ 6397 dur = 3 * sifs; 6398 dur += 6399 (u16) brcms_c_calc_cts_time(wlc, rts_rate, 6400 rts_preamble_type); 6401 } else { 6402 /* CTS-TO-SELF */ 6403 dur = 2 * sifs; 6404 } 6405 6406 dur += 6407 (u16) brcms_c_calc_frame_time(wlc, frame_rate, frame_preamble_type, 6408 frame_len); 6409 if (ba) 6410 dur += 6411 (u16) brcms_c_calc_ba_time(wlc, frame_rate, 6412 BRCMS_SHORT_PREAMBLE); 6413 else 6414 dur += 6415 (u16) brcms_c_calc_ack_time(wlc, frame_rate, 6416 frame_preamble_type); 6417 return dur; 6418} 6419 6420static u16 brcms_c_phytxctl1_calc(struct brcms_c_info *wlc, u32 rspec) 6421{ 6422 u16 phyctl1 = 0; 6423 u16 bw; 6424 6425 if (BRCMS_ISLCNPHY(wlc->band)) { 6426 bw = PHY_TXC1_BW_20MHZ; 6427 } else { 6428 bw = rspec_get_bw(rspec); 6429 /* 10Mhz is not supported yet */ 6430 if (bw < PHY_TXC1_BW_20MHZ) { 6431 brcms_err(wlc->hw->d11core, "phytxctl1_calc: bw %d is " 6432 "not supported yet, set to 20L\n", bw); 6433 bw = PHY_TXC1_BW_20MHZ; 6434 } 6435 } 6436 6437 if (is_mcs_rate(rspec)) { 6438 uint mcs = rspec & RSPEC_RATE_MASK; 6439 6440 /* bw, stf, coding-type is part of rspec_phytxbyte2 returns */ 6441 phyctl1 = rspec_phytxbyte2(rspec); 6442 /* set the upper byte of phyctl1 */ 6443 phyctl1 |= (mcs_table[mcs].tx_phy_ctl3 << 8); 6444 } else if (is_cck_rate(rspec) && !BRCMS_ISLCNPHY(wlc->band) 6445 && !BRCMS_ISSSLPNPHY(wlc->band)) { 6446 /* 6447 * In CCK mode LPPHY overloads OFDM Modulation bits with CCK 6448 * Data Rate. Eventually MIMOPHY would also be converted to 6449 * this format 6450 */ 6451 /* 0 = 1Mbps; 1 = 2Mbps; 2 = 5.5Mbps; 3 = 11Mbps */ 6452 phyctl1 = (bw | (rspec_stf(rspec) << PHY_TXC1_MODE_SHIFT)); 6453 } else { /* legacy OFDM/CCK */ 6454 s16 phycfg; 6455 /* get the phyctl byte from rate phycfg table */ 6456 phycfg = brcms_c_rate_legacy_phyctl(rspec2rate(rspec)); 6457 if (phycfg == -1) { 6458 brcms_err(wlc->hw->d11core, "phytxctl1_calc: wrong " 6459 "legacy OFDM/CCK rate\n"); 6460 phycfg = 0; 6461 } 6462 /* set the upper byte of phyctl1 */ 6463 phyctl1 = 6464 (bw | (phycfg << 8) | 6465 (rspec_stf(rspec) << PHY_TXC1_MODE_SHIFT)); 6466 } 6467 return phyctl1; 6468} 6469 6470/* 6471 * Add struct d11txh, struct cck_phy_hdr. 6472 * 6473 * 'p' data must start with 802.11 MAC header 6474 * 'p' must allow enough bytes of local headers to be "pushed" onto the packet 6475 * 6476 * headroom == D11_PHY_HDR_LEN + D11_TXH_LEN (D11_TXH_LEN is now 104 bytes) 6477 * 6478 */ 6479static u16 6480brcms_c_d11hdrs_mac80211(struct brcms_c_info *wlc, struct ieee80211_hw *hw, 6481 struct sk_buff *p, struct scb *scb, uint frag, 6482 uint nfrags, uint queue, uint next_frag_len) 6483{ 6484 struct ieee80211_hdr *h; 6485 struct d11txh *txh; 6486 u8 *plcp, plcp_fallback[D11_PHY_HDR_LEN]; 6487 int len, phylen, rts_phylen; 6488 u16 mch, phyctl, xfts, mainrates; 6489 u16 seq = 0, mcl = 0, status = 0, frameid = 0; 6490 u32 rspec[2] = { BRCM_RATE_1M, BRCM_RATE_1M }; 6491 u32 rts_rspec[2] = { BRCM_RATE_1M, BRCM_RATE_1M }; 6492 bool use_rts = false; 6493 bool use_cts = false; 6494 bool use_rifs = false; 6495 bool short_preamble[2] = { false, false }; 6496 u8 preamble_type[2] = { BRCMS_LONG_PREAMBLE, BRCMS_LONG_PREAMBLE }; 6497 u8 rts_preamble_type[2] = { BRCMS_LONG_PREAMBLE, BRCMS_LONG_PREAMBLE }; 6498 u8 *rts_plcp, rts_plcp_fallback[D11_PHY_HDR_LEN]; 6499 struct ieee80211_rts *rts = NULL; 6500 bool qos; 6501 uint ac; 6502 bool hwtkmic = false; 6503 u16 mimo_ctlchbw = PHY_TXC1_BW_20MHZ; 6504#define ANTCFG_NONE 0xFF 6505 u8 antcfg = ANTCFG_NONE; 6506 u8 fbantcfg = ANTCFG_NONE; 6507 uint phyctl1_stf = 0; 6508 u16 durid = 0; 6509 struct ieee80211_tx_rate *txrate[2]; 6510 int k; 6511 struct ieee80211_tx_info *tx_info; 6512 bool is_mcs; 6513 u16 mimo_txbw; 6514 u8 mimo_preamble_type; 6515 6516 /* locate 802.11 MAC header */ 6517 h = (struct ieee80211_hdr *)(p->data); 6518 qos = ieee80211_is_data_qos(h->frame_control); 6519 6520 /* compute length of frame in bytes for use in PLCP computations */ 6521 len = p->len; 6522 phylen = len + FCS_LEN; 6523 6524 /* Get tx_info */ 6525 tx_info = IEEE80211_SKB_CB(p); 6526 6527 /* add PLCP */ 6528 plcp = skb_push(p, D11_PHY_HDR_LEN); 6529 6530 /* add Broadcom tx descriptor header */ 6531 txh = (struct d11txh *) skb_push(p, D11_TXH_LEN); 6532 memset(txh, 0, D11_TXH_LEN); 6533 6534 /* setup frameid */ 6535 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { 6536 /* non-AP STA should never use BCMC queue */ 6537 if (queue == TX_BCMC_FIFO) { 6538 brcms_err(wlc->hw->d11core, 6539 "wl%d: %s: ASSERT queue == TX_BCMC!\n", 6540 wlc->pub->unit, __func__); 6541 frameid = bcmc_fid_generate(wlc, NULL, txh); 6542 } else { 6543 /* Increment the counter for first fragment */ 6544 if (tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) 6545 scb->seqnum[p->priority]++; 6546 6547 /* extract fragment number from frame first */ 6548 seq = le16_to_cpu(h->seq_ctrl) & FRAGNUM_MASK; 6549 seq |= (scb->seqnum[p->priority] << SEQNUM_SHIFT); 6550 h->seq_ctrl = cpu_to_le16(seq); 6551 6552 frameid = ((seq << TXFID_SEQ_SHIFT) & TXFID_SEQ_MASK) | 6553 (queue & TXFID_QUEUE_MASK); 6554 } 6555 } 6556 frameid |= queue & TXFID_QUEUE_MASK; 6557 6558 /* set the ignpmq bit for all pkts tx'd in PS mode and for beacons */ 6559 if (ieee80211_is_beacon(h->frame_control)) 6560 mcl |= TXC_IGNOREPMQ; 6561 6562 txrate[0] = tx_info->control.rates; 6563 txrate[1] = txrate[0] + 1; 6564 6565 /* 6566 * if rate control algorithm didn't give us a fallback 6567 * rate, use the primary rate 6568 */ 6569 if (txrate[1]->idx < 0) 6570 txrate[1] = txrate[0]; 6571 6572 for (k = 0; k < hw->max_rates; k++) { 6573 is_mcs = txrate[k]->flags & IEEE80211_TX_RC_MCS ? true : false; 6574 if (!is_mcs) { 6575 if ((txrate[k]->idx >= 0) 6576 && (txrate[k]->idx < 6577 hw->wiphy->bands[tx_info->band]->n_bitrates)) { 6578 rspec[k] = 6579 hw->wiphy->bands[tx_info->band]-> 6580 bitrates[txrate[k]->idx].hw_value; 6581 short_preamble[k] = 6582 txrate[k]-> 6583 flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE ? 6584 true : false; 6585 } else { 6586 rspec[k] = BRCM_RATE_1M; 6587 } 6588 } else { 6589 rspec[k] = mac80211_wlc_set_nrate(wlc, wlc->band, 6590 NRATE_MCS_INUSE | txrate[k]->idx); 6591 } 6592 6593 /* 6594 * Currently only support same setting for primay and 6595 * fallback rates. Unify flags for each rate into a 6596 * single value for the frame 6597 */ 6598 use_rts |= 6599 txrate[k]-> 6600 flags & IEEE80211_TX_RC_USE_RTS_CTS ? true : false; 6601 use_cts |= 6602 txrate[k]-> 6603 flags & IEEE80211_TX_RC_USE_CTS_PROTECT ? true : false; 6604 6605 6606 /* 6607 * (1) RATE: 6608 * determine and validate primary rate 6609 * and fallback rates 6610 */ 6611 if (!rspec_active(rspec[k])) { 6612 rspec[k] = BRCM_RATE_1M; 6613 } else { 6614 if (!is_multicast_ether_addr(h->addr1)) { 6615 /* set tx antenna config */ 6616 brcms_c_antsel_antcfg_get(wlc->asi, false, 6617 false, 0, 0, &antcfg, &fbantcfg); 6618 } 6619 } 6620 } 6621 6622 phyctl1_stf = wlc->stf->ss_opmode; 6623 6624 if (wlc->pub->_n_enab & SUPPORT_11N) { 6625 for (k = 0; k < hw->max_rates; k++) { 6626 /* 6627 * apply siso/cdd to single stream mcs's or ofdm 6628 * if rspec is auto selected 6629 */ 6630 if (((is_mcs_rate(rspec[k]) && 6631 is_single_stream(rspec[k] & RSPEC_RATE_MASK)) || 6632 is_ofdm_rate(rspec[k])) 6633 && ((rspec[k] & RSPEC_OVERRIDE_MCS_ONLY) 6634 || !(rspec[k] & RSPEC_OVERRIDE))) { 6635 rspec[k] &= ~(RSPEC_STF_MASK | RSPEC_STC_MASK); 6636 6637 /* For SISO MCS use STBC if possible */ 6638 if (is_mcs_rate(rspec[k]) 6639 && BRCMS_STF_SS_STBC_TX(wlc, scb)) { 6640 u8 stc; 6641 6642 /* Nss for single stream is always 1 */ 6643 stc = 1; 6644 rspec[k] |= (PHY_TXC1_MODE_STBC << 6645 RSPEC_STF_SHIFT) | 6646 (stc << RSPEC_STC_SHIFT); 6647 } else 6648 rspec[k] |= 6649 (phyctl1_stf << RSPEC_STF_SHIFT); 6650 } 6651 6652 /* 6653 * Is the phy configured to use 40MHZ frames? If 6654 * so then pick the desired txbw 6655 */ 6656 if (brcms_chspec_bw(wlc->chanspec) == BRCMS_40_MHZ) { 6657 /* default txbw is 20in40 SB */ 6658 mimo_ctlchbw = mimo_txbw = 6659 CHSPEC_SB_UPPER(wlc_phy_chanspec_get( 6660 wlc->band->pi)) 6661 ? PHY_TXC1_BW_20MHZ_UP : PHY_TXC1_BW_20MHZ; 6662 6663 if (is_mcs_rate(rspec[k])) { 6664 /* mcs 32 must be 40b/w DUP */ 6665 if ((rspec[k] & RSPEC_RATE_MASK) 6666 == 32) { 6667 mimo_txbw = 6668 PHY_TXC1_BW_40MHZ_DUP; 6669 /* use override */ 6670 } else if (wlc->mimo_40txbw != AUTO) 6671 mimo_txbw = wlc->mimo_40txbw; 6672 /* else check if dst is using 40 Mhz */ 6673 else if (scb->flags & SCB_IS40) 6674 mimo_txbw = PHY_TXC1_BW_40MHZ; 6675 } else if (is_ofdm_rate(rspec[k])) { 6676 if (wlc->ofdm_40txbw != AUTO) 6677 mimo_txbw = wlc->ofdm_40txbw; 6678 } else if (wlc->cck_40txbw != AUTO) { 6679 mimo_txbw = wlc->cck_40txbw; 6680 } 6681 } else { 6682 /* 6683 * mcs32 is 40 b/w only. 6684 * This is possible for probe packets on 6685 * a STA during SCAN 6686 */ 6687 if ((rspec[k] & RSPEC_RATE_MASK) == 32) 6688 /* mcs 0 */ 6689 rspec[k] = RSPEC_MIMORATE; 6690 6691 mimo_txbw = PHY_TXC1_BW_20MHZ; 6692 } 6693 6694 /* Set channel width */ 6695 rspec[k] &= ~RSPEC_BW_MASK; 6696 if ((k == 0) || ((k > 0) && is_mcs_rate(rspec[k]))) 6697 rspec[k] |= (mimo_txbw << RSPEC_BW_SHIFT); 6698 else 6699 rspec[k] |= (mimo_ctlchbw << RSPEC_BW_SHIFT); 6700 6701 /* Disable short GI, not supported yet */ 6702 rspec[k] &= ~RSPEC_SHORT_GI; 6703 6704 mimo_preamble_type = BRCMS_MM_PREAMBLE; 6705 if (txrate[k]->flags & IEEE80211_TX_RC_GREEN_FIELD) 6706 mimo_preamble_type = BRCMS_GF_PREAMBLE; 6707 6708 if ((txrate[k]->flags & IEEE80211_TX_RC_MCS) 6709 && (!is_mcs_rate(rspec[k]))) { 6710 brcms_err(wlc->hw->d11core, 6711 "wl%d: %s: IEEE80211_TX_" 6712 "RC_MCS != is_mcs_rate(rspec)\n", 6713 wlc->pub->unit, __func__); 6714 } 6715 6716 if (is_mcs_rate(rspec[k])) { 6717 preamble_type[k] = mimo_preamble_type; 6718 6719 /* 6720 * if SGI is selected, then forced mm 6721 * for single stream 6722 */ 6723 if ((rspec[k] & RSPEC_SHORT_GI) 6724 && is_single_stream(rspec[k] & 6725 RSPEC_RATE_MASK)) 6726 preamble_type[k] = BRCMS_MM_PREAMBLE; 6727 } 6728 6729 /* should be better conditionalized */ 6730 if (!is_mcs_rate(rspec[0]) 6731 && (tx_info->control.rates[0]. 6732 flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)) 6733 preamble_type[k] = BRCMS_SHORT_PREAMBLE; 6734 } 6735 } else { 6736 for (k = 0; k < hw->max_rates; k++) { 6737 /* Set ctrlchbw as 20Mhz */ 6738 rspec[k] &= ~RSPEC_BW_MASK; 6739 rspec[k] |= (PHY_TXC1_BW_20MHZ << RSPEC_BW_SHIFT); 6740 6741 /* for nphy, stf of ofdm frames must follow policies */ 6742 if (BRCMS_ISNPHY(wlc->band) && is_ofdm_rate(rspec[k])) { 6743 rspec[k] &= ~RSPEC_STF_MASK; 6744 rspec[k] |= phyctl1_stf << RSPEC_STF_SHIFT; 6745 } 6746 } 6747 } 6748 6749 /* Reset these for use with AMPDU's */ 6750 txrate[0]->count = 0; 6751 txrate[1]->count = 0; 6752 6753 /* (2) PROTECTION, may change rspec */ 6754 if ((ieee80211_is_data(h->frame_control) || 6755 ieee80211_is_mgmt(h->frame_control)) && 6756 (phylen > wlc->RTSThresh) && !is_multicast_ether_addr(h->addr1)) 6757 use_rts = true; 6758 6759 /* (3) PLCP: determine PLCP header and MAC duration, 6760 * fill struct d11txh */ 6761 brcms_c_compute_plcp(wlc, rspec[0], phylen, plcp); 6762 brcms_c_compute_plcp(wlc, rspec[1], phylen, plcp_fallback); 6763 memcpy(&txh->FragPLCPFallback, 6764 plcp_fallback, sizeof(txh->FragPLCPFallback)); 6765 6766 /* Length field now put in CCK FBR CRC field */ 6767 if (is_cck_rate(rspec[1])) { 6768 txh->FragPLCPFallback[4] = phylen & 0xff; 6769 txh->FragPLCPFallback[5] = (phylen & 0xff00) >> 8; 6770 } 6771 6772 /* MIMO-RATE: need validation ?? */ 6773 mainrates = is_ofdm_rate(rspec[0]) ? 6774 D11A_PHY_HDR_GRATE((struct ofdm_phy_hdr *) plcp) : 6775 plcp[0]; 6776 6777 /* DUR field for main rate */ 6778 if (!ieee80211_is_pspoll(h->frame_control) && 6779 !is_multicast_ether_addr(h->addr1) && !use_rifs) { 6780 durid = 6781 brcms_c_compute_frame_dur(wlc, rspec[0], preamble_type[0], 6782 next_frag_len); 6783 h->duration_id = cpu_to_le16(durid); 6784 } else if (use_rifs) { 6785 /* NAV protect to end of next max packet size */ 6786 durid = 6787 (u16) brcms_c_calc_frame_time(wlc, rspec[0], 6788 preamble_type[0], 6789 DOT11_MAX_FRAG_LEN); 6790 durid += RIFS_11N_TIME; 6791 h->duration_id = cpu_to_le16(durid); 6792 } 6793 6794 /* DUR field for fallback rate */ 6795 if (ieee80211_is_pspoll(h->frame_control)) 6796 txh->FragDurFallback = h->duration_id; 6797 else if (is_multicast_ether_addr(h->addr1) || use_rifs) 6798 txh->FragDurFallback = 0; 6799 else { 6800 durid = brcms_c_compute_frame_dur(wlc, rspec[1], 6801 preamble_type[1], next_frag_len); 6802 txh->FragDurFallback = cpu_to_le16(durid); 6803 } 6804 6805 /* (4) MAC-HDR: MacTxControlLow */ 6806 if (frag == 0) 6807 mcl |= TXC_STARTMSDU; 6808 6809 if (!is_multicast_ether_addr(h->addr1)) 6810 mcl |= TXC_IMMEDACK; 6811 6812 if (wlc->band->bandtype == BRCM_BAND_5G) 6813 mcl |= TXC_FREQBAND_5G; 6814 6815 if (CHSPEC_IS40(wlc_phy_chanspec_get(wlc->band->pi))) 6816 mcl |= TXC_BW_40; 6817 6818 /* set AMIC bit if using hardware TKIP MIC */ 6819 if (hwtkmic) 6820 mcl |= TXC_AMIC; 6821 6822 txh->MacTxControlLow = cpu_to_le16(mcl); 6823 6824 /* MacTxControlHigh */ 6825 mch = 0; 6826 6827 /* Set fallback rate preamble type */ 6828 if ((preamble_type[1] == BRCMS_SHORT_PREAMBLE) || 6829 (preamble_type[1] == BRCMS_GF_PREAMBLE)) { 6830 if (rspec2rate(rspec[1]) != BRCM_RATE_1M) 6831 mch |= TXC_PREAMBLE_DATA_FB_SHORT; 6832 } 6833 6834 /* MacFrameControl */ 6835 memcpy(&txh->MacFrameControl, &h->frame_control, sizeof(u16)); 6836 txh->TxFesTimeNormal = cpu_to_le16(0); 6837 6838 txh->TxFesTimeFallback = cpu_to_le16(0); 6839 6840 /* TxFrameRA */ 6841 memcpy(&txh->TxFrameRA, &h->addr1, ETH_ALEN); 6842 6843 /* TxFrameID */ 6844 txh->TxFrameID = cpu_to_le16(frameid); 6845 6846 /* 6847 * TxStatus, Note the case of recreating the first frag of a suppressed 6848 * frame then we may need to reset the retry cnt's via the status reg 6849 */ 6850 txh->TxStatus = cpu_to_le16(status); 6851 6852 /* 6853 * extra fields for ucode AMPDU aggregation, the new fields are added to 6854 * the END of previous structure so that it's compatible in driver. 6855 */ 6856 txh->MaxNMpdus = cpu_to_le16(0); 6857 txh->MaxABytes_MRT = cpu_to_le16(0); 6858 txh->MaxABytes_FBR = cpu_to_le16(0); 6859 txh->MinMBytes = cpu_to_le16(0); 6860 6861 /* (5) RTS/CTS: determine RTS/CTS PLCP header and MAC duration, 6862 * furnish struct d11txh */ 6863 /* RTS PLCP header and RTS frame */ 6864 if (use_rts || use_cts) { 6865 if (use_rts && use_cts) 6866 use_cts = false; 6867 6868 for (k = 0; k < 2; k++) { 6869 rts_rspec[k] = brcms_c_rspec_to_rts_rspec(wlc, rspec[k], 6870 false, 6871 mimo_ctlchbw); 6872 } 6873 6874 if (!is_ofdm_rate(rts_rspec[0]) && 6875 !((rspec2rate(rts_rspec[0]) == BRCM_RATE_1M) || 6876 (wlc->PLCPHdr_override == BRCMS_PLCP_LONG))) { 6877 rts_preamble_type[0] = BRCMS_SHORT_PREAMBLE; 6878 mch |= TXC_PREAMBLE_RTS_MAIN_SHORT; 6879 } 6880 6881 if (!is_ofdm_rate(rts_rspec[1]) && 6882 !((rspec2rate(rts_rspec[1]) == BRCM_RATE_1M) || 6883 (wlc->PLCPHdr_override == BRCMS_PLCP_LONG))) { 6884 rts_preamble_type[1] = BRCMS_SHORT_PREAMBLE; 6885 mch |= TXC_PREAMBLE_RTS_FB_SHORT; 6886 } 6887 6888 /* RTS/CTS additions to MacTxControlLow */ 6889 if (use_cts) { 6890 txh->MacTxControlLow |= cpu_to_le16(TXC_SENDCTS); 6891 } else { 6892 txh->MacTxControlLow |= cpu_to_le16(TXC_SENDRTS); 6893 txh->MacTxControlLow |= cpu_to_le16(TXC_LONGFRAME); 6894 } 6895 6896 /* RTS PLCP header */ 6897 rts_plcp = txh->RTSPhyHeader; 6898 if (use_cts) 6899 rts_phylen = DOT11_CTS_LEN + FCS_LEN; 6900 else 6901 rts_phylen = DOT11_RTS_LEN + FCS_LEN; 6902 6903 brcms_c_compute_plcp(wlc, rts_rspec[0], rts_phylen, rts_plcp); 6904 6905 /* fallback rate version of RTS PLCP header */ 6906 brcms_c_compute_plcp(wlc, rts_rspec[1], rts_phylen, 6907 rts_plcp_fallback); 6908 memcpy(&txh->RTSPLCPFallback, rts_plcp_fallback, 6909 sizeof(txh->RTSPLCPFallback)); 6910 6911 /* RTS frame fields... */ 6912 rts = (struct ieee80211_rts *)&txh->rts_frame; 6913 6914 durid = brcms_c_compute_rtscts_dur(wlc, use_cts, rts_rspec[0], 6915 rspec[0], rts_preamble_type[0], 6916 preamble_type[0], phylen, false); 6917 rts->duration = cpu_to_le16(durid); 6918 /* fallback rate version of RTS DUR field */ 6919 durid = brcms_c_compute_rtscts_dur(wlc, use_cts, 6920 rts_rspec[1], rspec[1], 6921 rts_preamble_type[1], 6922 preamble_type[1], phylen, false); 6923 txh->RTSDurFallback = cpu_to_le16(durid); 6924 6925 if (use_cts) { 6926 rts->frame_control = cpu_to_le16(IEEE80211_FTYPE_CTL | 6927 IEEE80211_STYPE_CTS); 6928 6929 memcpy(&rts->ra, &h->addr2, ETH_ALEN); 6930 } else { 6931 rts->frame_control = cpu_to_le16(IEEE80211_FTYPE_CTL | 6932 IEEE80211_STYPE_RTS); 6933 6934 memcpy(&rts->ra, &h->addr1, 2 * ETH_ALEN); 6935 } 6936 6937 /* mainrate 6938 * low 8 bits: main frag rate/mcs, 6939 * high 8 bits: rts/cts rate/mcs 6940 */ 6941 mainrates |= (is_ofdm_rate(rts_rspec[0]) ? 6942 D11A_PHY_HDR_GRATE( 6943 (struct ofdm_phy_hdr *) rts_plcp) : 6944 rts_plcp[0]) << 8; 6945 } else { 6946 memset((char *)txh->RTSPhyHeader, 0, D11_PHY_HDR_LEN); 6947 memset((char *)&txh->rts_frame, 0, 6948 sizeof(struct ieee80211_rts)); 6949 memset((char *)txh->RTSPLCPFallback, 0, 6950 sizeof(txh->RTSPLCPFallback)); 6951 txh->RTSDurFallback = 0; 6952 } 6953 6954#ifdef SUPPORT_40MHZ 6955 /* add null delimiter count */ 6956 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && is_mcs_rate(rspec)) 6957 txh->RTSPLCPFallback[AMPDU_FBR_NULL_DELIM] = 6958 brcm_c_ampdu_null_delim_cnt(wlc->ampdu, scb, rspec, phylen); 6959 6960#endif 6961 6962 /* 6963 * Now that RTS/RTS FB preamble types are updated, write 6964 * the final value 6965 */ 6966 txh->MacTxControlHigh = cpu_to_le16(mch); 6967 6968 /* 6969 * MainRates (both the rts and frag plcp rates have 6970 * been calculated now) 6971 */ 6972 txh->MainRates = cpu_to_le16(mainrates); 6973 6974 /* XtraFrameTypes */ 6975 xfts = frametype(rspec[1], wlc->mimoft); 6976 xfts |= (frametype(rts_rspec[0], wlc->mimoft) << XFTS_RTS_FT_SHIFT); 6977 xfts |= (frametype(rts_rspec[1], wlc->mimoft) << XFTS_FBRRTS_FT_SHIFT); 6978 xfts |= CHSPEC_CHANNEL(wlc_phy_chanspec_get(wlc->band->pi)) << 6979 XFTS_CHANNEL_SHIFT; 6980 txh->XtraFrameTypes = cpu_to_le16(xfts); 6981 6982 /* PhyTxControlWord */ 6983 phyctl = frametype(rspec[0], wlc->mimoft); 6984 if ((preamble_type[0] == BRCMS_SHORT_PREAMBLE) || 6985 (preamble_type[0] == BRCMS_GF_PREAMBLE)) { 6986 if (rspec2rate(rspec[0]) != BRCM_RATE_1M) 6987 phyctl |= PHY_TXC_SHORT_HDR; 6988 } 6989 6990 /* phytxant is properly bit shifted */ 6991 phyctl |= brcms_c_stf_d11hdrs_phyctl_txant(wlc, rspec[0]); 6992 txh->PhyTxControlWord = cpu_to_le16(phyctl); 6993 6994 /* PhyTxControlWord_1 */ 6995 if (BRCMS_PHY_11N_CAP(wlc->band)) { 6996 u16 phyctl1 = 0; 6997 6998 phyctl1 = brcms_c_phytxctl1_calc(wlc, rspec[0]); 6999 txh->PhyTxControlWord_1 = cpu_to_le16(phyctl1); 7000 phyctl1 = brcms_c_phytxctl1_calc(wlc, rspec[1]); 7001 txh->PhyTxControlWord_1_Fbr = cpu_to_le16(phyctl1); 7002 7003 if (use_rts || use_cts) { 7004 phyctl1 = brcms_c_phytxctl1_calc(wlc, rts_rspec[0]); 7005 txh->PhyTxControlWord_1_Rts = cpu_to_le16(phyctl1); 7006 phyctl1 = brcms_c_phytxctl1_calc(wlc, rts_rspec[1]); 7007 txh->PhyTxControlWord_1_FbrRts = cpu_to_le16(phyctl1); 7008 } 7009 7010 /* 7011 * For mcs frames, if mixedmode(overloaded with long preamble) 7012 * is going to be set, fill in non-zero MModeLen and/or 7013 * MModeFbrLen it will be unnecessary if they are separated 7014 */ 7015 if (is_mcs_rate(rspec[0]) && 7016 (preamble_type[0] == BRCMS_MM_PREAMBLE)) { 7017 u16 mmodelen = 7018 brcms_c_calc_lsig_len(wlc, rspec[0], phylen); 7019 txh->MModeLen = cpu_to_le16(mmodelen); 7020 } 7021 7022 if (is_mcs_rate(rspec[1]) && 7023 (preamble_type[1] == BRCMS_MM_PREAMBLE)) { 7024 u16 mmodefbrlen = 7025 brcms_c_calc_lsig_len(wlc, rspec[1], phylen); 7026 txh->MModeFbrLen = cpu_to_le16(mmodefbrlen); 7027 } 7028 } 7029 7030 ac = skb_get_queue_mapping(p); 7031 if ((scb->flags & SCB_WMECAP) && qos && wlc->edcf_txop[ac]) { 7032 uint frag_dur, dur, dur_fallback; 7033 7034 /* WME: Update TXOP threshold */ 7035 if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU) && frag == 0) { 7036 frag_dur = 7037 brcms_c_calc_frame_time(wlc, rspec[0], 7038 preamble_type[0], phylen); 7039 7040 if (rts) { 7041 /* 1 RTS or CTS-to-self frame */ 7042 dur = 7043 brcms_c_calc_cts_time(wlc, rts_rspec[0], 7044 rts_preamble_type[0]); 7045 dur_fallback = 7046 brcms_c_calc_cts_time(wlc, rts_rspec[1], 7047 rts_preamble_type[1]); 7048 /* (SIFS + CTS) + SIFS + frame + SIFS + ACK */ 7049 dur += le16_to_cpu(rts->duration); 7050 dur_fallback += 7051 le16_to_cpu(txh->RTSDurFallback); 7052 } else if (use_rifs) { 7053 dur = frag_dur; 7054 dur_fallback = 0; 7055 } else { 7056 /* frame + SIFS + ACK */ 7057 dur = frag_dur; 7058 dur += 7059 brcms_c_compute_frame_dur(wlc, rspec[0], 7060 preamble_type[0], 0); 7061 7062 dur_fallback = 7063 brcms_c_calc_frame_time(wlc, rspec[1], 7064 preamble_type[1], 7065 phylen); 7066 dur_fallback += 7067 brcms_c_compute_frame_dur(wlc, rspec[1], 7068 preamble_type[1], 0); 7069 } 7070 /* NEED to set TxFesTimeNormal (hard) */ 7071 txh->TxFesTimeNormal = cpu_to_le16((u16) dur); 7072 /* 7073 * NEED to set fallback rate version of 7074 * TxFesTimeNormal (hard) 7075 */ 7076 txh->TxFesTimeFallback = 7077 cpu_to_le16((u16) dur_fallback); 7078 7079 /* 7080 * update txop byte threshold (txop minus intraframe 7081 * overhead) 7082 */ 7083 if (wlc->edcf_txop[ac] >= (dur - frag_dur)) { 7084 uint newfragthresh; 7085 7086 newfragthresh = 7087 brcms_c_calc_frame_len(wlc, 7088 rspec[0], preamble_type[0], 7089 (wlc->edcf_txop[ac] - 7090 (dur - frag_dur))); 7091 /* range bound the fragthreshold */ 7092 if (newfragthresh < DOT11_MIN_FRAG_LEN) 7093 newfragthresh = 7094 DOT11_MIN_FRAG_LEN; 7095 else if (newfragthresh > 7096 wlc->usr_fragthresh) 7097 newfragthresh = 7098 wlc->usr_fragthresh; 7099 /* update the fragthresh and do txc update */ 7100 if (wlc->fragthresh[queue] != 7101 (u16) newfragthresh) 7102 wlc->fragthresh[queue] = 7103 (u16) newfragthresh; 7104 } else { 7105 brcms_err(wlc->hw->d11core, 7106 "wl%d: %s txop invalid " 7107 "for rate %d\n", 7108 wlc->pub->unit, fifo_names[queue], 7109 rspec2rate(rspec[0])); 7110 } 7111 7112 if (dur > wlc->edcf_txop[ac]) 7113 brcms_err(wlc->hw->d11core, 7114 "wl%d: %s: %s txop " 7115 "exceeded phylen %d/%d dur %d/%d\n", 7116 wlc->pub->unit, __func__, 7117 fifo_names[queue], 7118 phylen, wlc->fragthresh[queue], 7119 dur, wlc->edcf_txop[ac]); 7120 } 7121 } 7122 7123 return 0; 7124} 7125 7126static int brcms_c_tx(struct brcms_c_info *wlc, struct sk_buff *skb) 7127{ 7128 struct dma_pub *dma; 7129 int fifo, ret = -ENOSPC; 7130 struct d11txh *txh; 7131 u16 frameid = INVALIDFID; 7132 7133 fifo = brcms_ac_to_fifo(skb_get_queue_mapping(skb)); 7134 dma = wlc->hw->di[fifo]; 7135 txh = (struct d11txh *)(skb->data); 7136 7137 if (dma->txavail == 0) { 7138 /* 7139 * We sometimes get a frame from mac80211 after stopping 7140 * the queues. This only ever seems to be a single frame 7141 * and is seems likely to be a race. TX_HEADROOM should 7142 * ensure that we have enough space to handle these stray 7143 * packets, so warn if there isn't. If we're out of space 7144 * in the tx ring and the tx queue isn't stopped then 7145 * we've really got a bug; warn loudly if that happens. 7146 */ 7147 brcms_warn(wlc->hw->d11core, 7148 "Received frame for tx with no space in DMA ring\n"); 7149 WARN_ON(!ieee80211_queue_stopped(wlc->pub->ieee_hw, 7150 skb_get_queue_mapping(skb))); 7151 return -ENOSPC; 7152 } 7153 7154 /* When a BC/MC frame is being committed to the BCMC fifo 7155 * via DMA (NOT PIO), update ucode or BSS info as appropriate. 7156 */ 7157 if (fifo == TX_BCMC_FIFO) 7158 frameid = le16_to_cpu(txh->TxFrameID); 7159 7160 /* Commit BCMC sequence number in the SHM frame ID location */ 7161 if (frameid != INVALIDFID) { 7162 /* 7163 * To inform the ucode of the last mcast frame posted 7164 * so that it can clear moredata bit 7165 */ 7166 brcms_b_write_shm(wlc->hw, M_BCMC_FID, frameid); 7167 } 7168 7169 ret = brcms_c_txfifo(wlc, fifo, skb); 7170 /* 7171 * The only reason for brcms_c_txfifo to fail is because 7172 * there weren't any DMA descriptors, but we've already 7173 * checked for that. So if it does fail yell loudly. 7174 */ 7175 WARN_ON_ONCE(ret); 7176 7177 return ret; 7178} 7179 7180void brcms_c_sendpkt_mac80211(struct brcms_c_info *wlc, struct sk_buff *sdu, 7181 struct ieee80211_hw *hw) 7182{ 7183 uint fifo; 7184 struct scb *scb = &wlc->pri_scb; 7185 7186 fifo = brcms_ac_to_fifo(skb_get_queue_mapping(sdu)); 7187 if (brcms_c_d11hdrs_mac80211(wlc, hw, sdu, scb, 0, 1, fifo, 0)) 7188 return; 7189 if (brcms_c_tx(wlc, sdu)) 7190 dev_kfree_skb_any(sdu); 7191} 7192 7193int 7194brcms_c_txfifo(struct brcms_c_info *wlc, uint fifo, struct sk_buff *p) 7195{ 7196 struct dma_pub *dma = wlc->hw->di[fifo]; 7197 int ret; 7198 u16 queue; 7199 7200 ret = dma_txfast(wlc, dma, p); 7201 if (ret < 0) 7202 wiphy_err(wlc->wiphy, "txfifo: fatal, toss frames !!!\n"); 7203 7204 /* 7205 * Stop queue if DMA ring is full. Reserve some free descriptors, 7206 * as we sometimes receive a frame from mac80211 after the queues 7207 * are stopped. 7208 */ 7209 queue = skb_get_queue_mapping(p); 7210 if (dma->txavail <= TX_HEADROOM && fifo < TX_BCMC_FIFO && 7211 !ieee80211_queue_stopped(wlc->pub->ieee_hw, queue)) 7212 ieee80211_stop_queue(wlc->pub->ieee_hw, queue); 7213 7214 return ret; 7215} 7216 7217u32 7218brcms_c_rspec_to_rts_rspec(struct brcms_c_info *wlc, u32 rspec, 7219 bool use_rspec, u16 mimo_ctlchbw) 7220{ 7221 u32 rts_rspec = 0; 7222 7223 if (use_rspec) 7224 /* use frame rate as rts rate */ 7225 rts_rspec = rspec; 7226 else if (wlc->band->gmode && wlc->protection->_g && !is_cck_rate(rspec)) 7227 /* Use 11Mbps as the g protection RTS target rate and fallback. 7228 * Use the brcms_basic_rate() lookup to find the best basic rate 7229 * under the target in case 11 Mbps is not Basic. 7230 * 6 and 9 Mbps are not usually selected by rate selection, but 7231 * even if the OFDM rate we are protecting is 6 or 9 Mbps, 11 7232 * is more robust. 7233 */ 7234 rts_rspec = brcms_basic_rate(wlc, BRCM_RATE_11M); 7235 else 7236 /* calculate RTS rate and fallback rate based on the frame rate 7237 * RTS must be sent at a basic rate since it is a 7238 * control frame, sec 9.6 of 802.11 spec 7239 */ 7240 rts_rspec = brcms_basic_rate(wlc, rspec); 7241 7242 if (BRCMS_PHY_11N_CAP(wlc->band)) { 7243 /* set rts txbw to correct side band */ 7244 rts_rspec &= ~RSPEC_BW_MASK; 7245 7246 /* 7247 * if rspec/rspec_fallback is 40MHz, then send RTS on both 7248 * 20MHz channel (DUP), otherwise send RTS on control channel 7249 */ 7250 if (rspec_is40mhz(rspec) && !is_cck_rate(rts_rspec)) 7251 rts_rspec |= (PHY_TXC1_BW_40MHZ_DUP << RSPEC_BW_SHIFT); 7252 else 7253 rts_rspec |= (mimo_ctlchbw << RSPEC_BW_SHIFT); 7254 7255 /* pick siso/cdd as default for ofdm */ 7256 if (is_ofdm_rate(rts_rspec)) { 7257 rts_rspec &= ~RSPEC_STF_MASK; 7258 rts_rspec |= (wlc->stf->ss_opmode << RSPEC_STF_SHIFT); 7259 } 7260 } 7261 return rts_rspec; 7262} 7263 7264/* Update beacon listen interval in shared memory */ 7265static void brcms_c_bcn_li_upd(struct brcms_c_info *wlc) 7266{ 7267 /* wake up every DTIM is the default */ 7268 if (wlc->bcn_li_dtim == 1) 7269 brcms_b_write_shm(wlc->hw, M_BCN_LI, 0); 7270 else 7271 brcms_b_write_shm(wlc->hw, M_BCN_LI, 7272 (wlc->bcn_li_dtim << 8) | wlc->bcn_li_bcn); 7273} 7274 7275static void 7276brcms_b_read_tsf(struct brcms_hardware *wlc_hw, u32 *tsf_l_ptr, 7277 u32 *tsf_h_ptr) 7278{ 7279 struct bcma_device *core = wlc_hw->d11core; 7280 7281 /* read the tsf timer low, then high to get an atomic read */ 7282 *tsf_l_ptr = bcma_read32(core, D11REGOFFS(tsf_timerlow)); 7283 *tsf_h_ptr = bcma_read32(core, D11REGOFFS(tsf_timerhigh)); 7284} 7285 7286/* 7287 * recover 64bit TSF value from the 16bit TSF value in the rx header 7288 * given the assumption that the TSF passed in header is within 65ms 7289 * of the current tsf. 7290 * 7291 * 6 5 4 4 3 2 1 7292 * 3.......6.......8.......0.......2.......4.......6.......8......0 7293 * |<---------- tsf_h ----------->||<--- tsf_l -->||<-RxTSFTime ->| 7294 * 7295 * The RxTSFTime are the lowest 16 bits and provided by the ucode. The 7296 * tsf_l is filled in by brcms_b_recv, which is done earlier in the 7297 * receive call sequence after rx interrupt. Only the higher 16 bits 7298 * are used. Finally, the tsf_h is read from the tsf register. 7299 */ 7300static u64 brcms_c_recover_tsf64(struct brcms_c_info *wlc, 7301 struct d11rxhdr *rxh) 7302{ 7303 u32 tsf_h, tsf_l; 7304 u16 rx_tsf_0_15, rx_tsf_16_31; 7305 7306 brcms_b_read_tsf(wlc->hw, &tsf_l, &tsf_h); 7307 7308 rx_tsf_16_31 = (u16)(tsf_l >> 16); 7309 rx_tsf_0_15 = rxh->RxTSFTime; 7310 7311 /* 7312 * a greater tsf time indicates the low 16 bits of 7313 * tsf_l wrapped, so decrement the high 16 bits. 7314 */ 7315 if ((u16)tsf_l < rx_tsf_0_15) { 7316 rx_tsf_16_31 -= 1; 7317 if (rx_tsf_16_31 == 0xffff) 7318 tsf_h -= 1; 7319 } 7320 7321 return ((u64)tsf_h << 32) | (((u32)rx_tsf_16_31 << 16) + rx_tsf_0_15); 7322} 7323 7324static void 7325prep_mac80211_status(struct brcms_c_info *wlc, struct d11rxhdr *rxh, 7326 struct sk_buff *p, 7327 struct ieee80211_rx_status *rx_status) 7328{ 7329 int preamble; 7330 int channel; 7331 u32 rspec; 7332 unsigned char *plcp; 7333 7334 /* fill in TSF and flag its presence */ 7335 rx_status->mactime = brcms_c_recover_tsf64(wlc, rxh); 7336 rx_status->flag |= RX_FLAG_MACTIME_MPDU; 7337 7338 channel = BRCMS_CHAN_CHANNEL(rxh->RxChan); 7339 7340 rx_status->band = 7341 channel > 14 ? IEEE80211_BAND_5GHZ : IEEE80211_BAND_2GHZ; 7342 rx_status->freq = 7343 ieee80211_channel_to_frequency(channel, rx_status->band); 7344 7345 rx_status->signal = wlc_phy_rssi_compute(wlc->hw->band->pi, rxh); 7346 7347 /* noise */ 7348 /* qual */ 7349 rx_status->antenna = 7350 (rxh->PhyRxStatus_0 & PRXS0_RXANT_UPSUBBAND) ? 1 : 0; 7351 7352 plcp = p->data; 7353 7354 rspec = brcms_c_compute_rspec(rxh, plcp); 7355 if (is_mcs_rate(rspec)) { 7356 rx_status->rate_idx = rspec & RSPEC_RATE_MASK; 7357 rx_status->flag |= RX_FLAG_HT; 7358 if (rspec_is40mhz(rspec)) 7359 rx_status->flag |= RX_FLAG_40MHZ; 7360 } else { 7361 switch (rspec2rate(rspec)) { 7362 case BRCM_RATE_1M: 7363 rx_status->rate_idx = 0; 7364 break; 7365 case BRCM_RATE_2M: 7366 rx_status->rate_idx = 1; 7367 break; 7368 case BRCM_RATE_5M5: 7369 rx_status->rate_idx = 2; 7370 break; 7371 case BRCM_RATE_11M: 7372 rx_status->rate_idx = 3; 7373 break; 7374 case BRCM_RATE_6M: 7375 rx_status->rate_idx = 4; 7376 break; 7377 case BRCM_RATE_9M: 7378 rx_status->rate_idx = 5; 7379 break; 7380 case BRCM_RATE_12M: 7381 rx_status->rate_idx = 6; 7382 break; 7383 case BRCM_RATE_18M: 7384 rx_status->rate_idx = 7; 7385 break; 7386 case BRCM_RATE_24M: 7387 rx_status->rate_idx = 8; 7388 break; 7389 case BRCM_RATE_36M: 7390 rx_status->rate_idx = 9; 7391 break; 7392 case BRCM_RATE_48M: 7393 rx_status->rate_idx = 10; 7394 break; 7395 case BRCM_RATE_54M: 7396 rx_status->rate_idx = 11; 7397 break; 7398 default: 7399 brcms_err(wlc->hw->d11core, 7400 "%s: Unknown rate\n", __func__); 7401 } 7402 7403 /* 7404 * For 5GHz, we should decrease the index as it is 7405 * a subset of the 2.4G rates. See bitrates field 7406 * of brcms_band_5GHz_nphy (in mac80211_if.c). 7407 */ 7408 if (rx_status->band == IEEE80211_BAND_5GHZ) 7409 rx_status->rate_idx -= BRCMS_LEGACY_5G_RATE_OFFSET; 7410 7411 /* Determine short preamble and rate_idx */ 7412 preamble = 0; 7413 if (is_cck_rate(rspec)) { 7414 if (rxh->PhyRxStatus_0 & PRXS0_SHORTH) 7415 rx_status->flag |= RX_FLAG_SHORTPRE; 7416 } else if (is_ofdm_rate(rspec)) { 7417 rx_status->flag |= RX_FLAG_SHORTPRE; 7418 } else { 7419 brcms_err(wlc->hw->d11core, "%s: Unknown modulation\n", 7420 __func__); 7421 } 7422 } 7423 7424 if (plcp3_issgi(plcp[3])) 7425 rx_status->flag |= RX_FLAG_SHORT_GI; 7426 7427 if (rxh->RxStatus1 & RXS_DECERR) { 7428 rx_status->flag |= RX_FLAG_FAILED_PLCP_CRC; 7429 brcms_err(wlc->hw->d11core, "%s: RX_FLAG_FAILED_PLCP_CRC\n", 7430 __func__); 7431 } 7432 if (rxh->RxStatus1 & RXS_FCSERR) { 7433 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; 7434 brcms_err(wlc->hw->d11core, "%s: RX_FLAG_FAILED_FCS_CRC\n", 7435 __func__); 7436 } 7437} 7438 7439static void 7440brcms_c_recvctl(struct brcms_c_info *wlc, struct d11rxhdr *rxh, 7441 struct sk_buff *p) 7442{ 7443 int len_mpdu; 7444 struct ieee80211_rx_status rx_status; 7445 struct ieee80211_hdr *hdr; 7446 7447 memset(&rx_status, 0, sizeof(rx_status)); 7448 prep_mac80211_status(wlc, rxh, p, &rx_status); 7449 7450 /* mac header+body length, exclude CRC and plcp header */ 7451 len_mpdu = p->len - D11_PHY_HDR_LEN - FCS_LEN; 7452 skb_pull(p, D11_PHY_HDR_LEN); 7453 __skb_trim(p, len_mpdu); 7454 7455 /* unmute transmit */ 7456 if (wlc->hw->suspended_fifos) { 7457 hdr = (struct ieee80211_hdr *)p->data; 7458 if (ieee80211_is_beacon(hdr->frame_control)) 7459 brcms_b_mute(wlc->hw, false); 7460 } 7461 7462 memcpy(IEEE80211_SKB_RXCB(p), &rx_status, sizeof(rx_status)); 7463 ieee80211_rx_irqsafe(wlc->pub->ieee_hw, p); 7464} 7465 7466/* calculate frame duration for Mixed-mode L-SIG spoofing, return 7467 * number of bytes goes in the length field 7468 * 7469 * Formula given by HT PHY Spec v 1.13 7470 * len = 3(nsyms + nstream + 3) - 3 7471 */ 7472u16 7473brcms_c_calc_lsig_len(struct brcms_c_info *wlc, u32 ratespec, 7474 uint mac_len) 7475{ 7476 uint nsyms, len = 0, kNdps; 7477 7478 brcms_dbg_mac80211(wlc->hw->d11core, "wl%d: rate %d, len%d\n", 7479 wlc->pub->unit, rspec2rate(ratespec), mac_len); 7480 7481 if (is_mcs_rate(ratespec)) { 7482 uint mcs = ratespec & RSPEC_RATE_MASK; 7483 int tot_streams = (mcs_2_txstreams(mcs) + 1) + 7484 rspec_stc(ratespec); 7485 7486 /* 7487 * the payload duration calculation matches that 7488 * of regular ofdm 7489 */ 7490 /* 1000Ndbps = kbps * 4 */ 7491 kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec), 7492 rspec_issgi(ratespec)) * 4; 7493 7494 if (rspec_stc(ratespec) == 0) 7495 nsyms = 7496 CEIL((APHY_SERVICE_NBITS + 8 * mac_len + 7497 APHY_TAIL_NBITS) * 1000, kNdps); 7498 else 7499 /* STBC needs to have even number of symbols */ 7500 nsyms = 7501 2 * 7502 CEIL((APHY_SERVICE_NBITS + 8 * mac_len + 7503 APHY_TAIL_NBITS) * 1000, 2 * kNdps); 7504 7505 /* (+3) account for HT-SIG(2) and HT-STF(1) */ 7506 nsyms += (tot_streams + 3); 7507 /* 7508 * 3 bytes/symbol @ legacy 6Mbps rate 7509 * (-3) excluding service bits and tail bits 7510 */ 7511 len = (3 * nsyms) - 3; 7512 } 7513 7514 return (u16) len; 7515} 7516 7517static void 7518brcms_c_mod_prb_rsp_rate_table(struct brcms_c_info *wlc, uint frame_len) 7519{ 7520 const struct brcms_c_rateset *rs_dflt; 7521 struct brcms_c_rateset rs; 7522 u8 rate; 7523 u16 entry_ptr; 7524 u8 plcp[D11_PHY_HDR_LEN]; 7525 u16 dur, sifs; 7526 uint i; 7527 7528 sifs = get_sifs(wlc->band); 7529 7530 rs_dflt = brcms_c_rateset_get_hwrs(wlc); 7531 7532 brcms_c_rateset_copy(rs_dflt, &rs); 7533 brcms_c_rateset_mcs_upd(&rs, wlc->stf->txstreams); 7534 7535 /* 7536 * walk the phy rate table and update MAC core SHM 7537 * basic rate table entries 7538 */ 7539 for (i = 0; i < rs.count; i++) { 7540 rate = rs.rates[i] & BRCMS_RATE_MASK; 7541 7542 entry_ptr = brcms_b_rate_shm_offset(wlc->hw, rate); 7543 7544 /* Calculate the Probe Response PLCP for the given rate */ 7545 brcms_c_compute_plcp(wlc, rate, frame_len, plcp); 7546 7547 /* 7548 * Calculate the duration of the Probe Response 7549 * frame plus SIFS for the MAC 7550 */ 7551 dur = (u16) brcms_c_calc_frame_time(wlc, rate, 7552 BRCMS_LONG_PREAMBLE, frame_len); 7553 dur += sifs; 7554 7555 /* Update the SHM Rate Table entry Probe Response values */ 7556 brcms_b_write_shm(wlc->hw, entry_ptr + M_RT_PRS_PLCP_POS, 7557 (u16) (plcp[0] + (plcp[1] << 8))); 7558 brcms_b_write_shm(wlc->hw, entry_ptr + M_RT_PRS_PLCP_POS + 2, 7559 (u16) (plcp[2] + (plcp[3] << 8))); 7560 brcms_b_write_shm(wlc->hw, entry_ptr + M_RT_PRS_DUR_POS, dur); 7561 } 7562} 7563 7564/* Max buffering needed for beacon template/prb resp template is 142 bytes. 7565 * 7566 * PLCP header is 6 bytes. 7567 * 802.11 A3 header is 24 bytes. 7568 * Max beacon frame body template length is 112 bytes. 7569 * Max probe resp frame body template length is 110 bytes. 7570 * 7571 * *len on input contains the max length of the packet available. 7572 * 7573 * The *len value is set to the number of bytes in buf used, and starts 7574 * with the PLCP and included up to, but not including, the 4 byte FCS. 7575 */ 7576static void 7577brcms_c_bcn_prb_template(struct brcms_c_info *wlc, u16 type, 7578 u32 bcn_rspec, 7579 struct brcms_bss_cfg *cfg, u16 *buf, int *len) 7580{ 7581 static const u8 ether_bcast[ETH_ALEN] = {255, 255, 255, 255, 255, 255}; 7582 struct cck_phy_hdr *plcp; 7583 struct ieee80211_mgmt *h; 7584 int hdr_len, body_len; 7585 7586 hdr_len = D11_PHY_HDR_LEN + DOT11_MAC_HDR_LEN; 7587 7588 /* calc buffer size provided for frame body */ 7589 body_len = *len - hdr_len; 7590 /* return actual size */ 7591 *len = hdr_len + body_len; 7592 7593 /* format PHY and MAC headers */ 7594 memset((char *)buf, 0, hdr_len); 7595 7596 plcp = (struct cck_phy_hdr *) buf; 7597 7598 /* 7599 * PLCP for Probe Response frames are filled in from 7600 * core's rate table 7601 */ 7602 if (type == IEEE80211_STYPE_BEACON) 7603 /* fill in PLCP */ 7604 brcms_c_compute_plcp(wlc, bcn_rspec, 7605 (DOT11_MAC_HDR_LEN + body_len + FCS_LEN), 7606 (u8 *) plcp); 7607 7608 /* "Regular" and 16 MBSS but not for 4 MBSS */ 7609 /* Update the phytxctl for the beacon based on the rspec */ 7610 brcms_c_beacon_phytxctl_txant_upd(wlc, bcn_rspec); 7611 7612 h = (struct ieee80211_mgmt *)&plcp[1]; 7613 7614 /* fill in 802.11 header */ 7615 h->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT | type); 7616 7617 /* DUR is 0 for multicast bcn, or filled in by MAC for prb resp */ 7618 /* A1 filled in by MAC for prb resp, broadcast for bcn */ 7619 if (type == IEEE80211_STYPE_BEACON) 7620 memcpy(&h->da, ðer_bcast, ETH_ALEN); 7621 memcpy(&h->sa, &cfg->cur_etheraddr, ETH_ALEN); 7622 memcpy(&h->bssid, &cfg->BSSID, ETH_ALEN); 7623 7624 /* SEQ filled in by MAC */ 7625} 7626 7627int brcms_c_get_header_len(void) 7628{ 7629 return TXOFF; 7630} 7631 7632/* 7633 * Update all beacons for the system. 7634 */ 7635void brcms_c_update_beacon(struct brcms_c_info *wlc) 7636{ 7637 struct brcms_bss_cfg *bsscfg = wlc->bsscfg; 7638 7639 if (bsscfg->up && !bsscfg->BSS) 7640 /* Clear the soft intmask */ 7641 wlc->defmacintmask &= ~MI_BCNTPL; 7642} 7643 7644/* Write ssid into shared memory */ 7645static void 7646brcms_c_shm_ssid_upd(struct brcms_c_info *wlc, struct brcms_bss_cfg *cfg) 7647{ 7648 u8 *ssidptr = cfg->SSID; 7649 u16 base = M_SSID; 7650 u8 ssidbuf[IEEE80211_MAX_SSID_LEN]; 7651 7652 /* padding the ssid with zero and copy it into shm */ 7653 memset(ssidbuf, 0, IEEE80211_MAX_SSID_LEN); 7654 memcpy(ssidbuf, ssidptr, cfg->SSID_len); 7655 7656 brcms_c_copyto_shm(wlc, base, ssidbuf, IEEE80211_MAX_SSID_LEN); 7657 brcms_b_write_shm(wlc->hw, M_SSIDLEN, (u16) cfg->SSID_len); 7658} 7659 7660static void 7661brcms_c_bss_update_probe_resp(struct brcms_c_info *wlc, 7662 struct brcms_bss_cfg *cfg, 7663 bool suspend) 7664{ 7665 u16 prb_resp[BCN_TMPL_LEN / 2]; 7666 int len = BCN_TMPL_LEN; 7667 7668 /* 7669 * write the probe response to hardware, or save in 7670 * the config structure 7671 */ 7672 7673 /* create the probe response template */ 7674 brcms_c_bcn_prb_template(wlc, IEEE80211_STYPE_PROBE_RESP, 0, 7675 cfg, prb_resp, &len); 7676 7677 if (suspend) 7678 brcms_c_suspend_mac_and_wait(wlc); 7679 7680 /* write the probe response into the template region */ 7681 brcms_b_write_template_ram(wlc->hw, T_PRS_TPL_BASE, 7682 (len + 3) & ~3, prb_resp); 7683 7684 /* write the length of the probe response frame (+PLCP/-FCS) */ 7685 brcms_b_write_shm(wlc->hw, M_PRB_RESP_FRM_LEN, (u16) len); 7686 7687 /* write the SSID and SSID length */ 7688 brcms_c_shm_ssid_upd(wlc, cfg); 7689 7690 /* 7691 * Write PLCP headers and durations for probe response frames 7692 * at all rates. Use the actual frame length covered by the 7693 * PLCP header for the call to brcms_c_mod_prb_rsp_rate_table() 7694 * by subtracting the PLCP len and adding the FCS. 7695 */ 7696 len += (-D11_PHY_HDR_LEN + FCS_LEN); 7697 brcms_c_mod_prb_rsp_rate_table(wlc, (u16) len); 7698 7699 if (suspend) 7700 brcms_c_enable_mac(wlc); 7701} 7702 7703void brcms_c_update_probe_resp(struct brcms_c_info *wlc, bool suspend) 7704{ 7705 struct brcms_bss_cfg *bsscfg = wlc->bsscfg; 7706 7707 /* update AP or IBSS probe responses */ 7708 if (bsscfg->up && !bsscfg->BSS) 7709 brcms_c_bss_update_probe_resp(wlc, bsscfg, suspend); 7710} 7711 7712int brcms_b_xmtfifo_sz_get(struct brcms_hardware *wlc_hw, uint fifo, 7713 uint *blocks) 7714{ 7715 if (fifo >= NFIFO) 7716 return -EINVAL; 7717 7718 *blocks = wlc_hw->xmtfifo_sz[fifo]; 7719 7720 return 0; 7721} 7722 7723void 7724brcms_c_set_addrmatch(struct brcms_c_info *wlc, int match_reg_offset, 7725 const u8 *addr) 7726{ 7727 brcms_b_set_addrmatch(wlc->hw, match_reg_offset, addr); 7728 if (match_reg_offset == RCM_BSSID_OFFSET) 7729 memcpy(wlc->bsscfg->BSSID, addr, ETH_ALEN); 7730} 7731 7732/* 7733 * Flag 'scan in progress' to withhold dynamic phy calibration 7734 */ 7735void brcms_c_scan_start(struct brcms_c_info *wlc) 7736{ 7737 wlc_phy_hold_upd(wlc->band->pi, PHY_HOLD_FOR_SCAN, true); 7738} 7739 7740void brcms_c_scan_stop(struct brcms_c_info *wlc) 7741{ 7742 wlc_phy_hold_upd(wlc->band->pi, PHY_HOLD_FOR_SCAN, false); 7743} 7744 7745void brcms_c_associate_upd(struct brcms_c_info *wlc, bool state) 7746{ 7747 wlc->pub->associated = state; 7748 wlc->bsscfg->associated = state; 7749} 7750 7751/* 7752 * When a remote STA/AP is removed by Mac80211, or when it can no longer accept 7753 * AMPDU traffic, packets pending in hardware have to be invalidated so that 7754 * when later on hardware releases them, they can be handled appropriately. 7755 */ 7756void brcms_c_inval_dma_pkts(struct brcms_hardware *hw, 7757 struct ieee80211_sta *sta, 7758 void (*dma_callback_fn)) 7759{ 7760 struct dma_pub *dmah; 7761 int i; 7762 for (i = 0; i < NFIFO; i++) { 7763 dmah = hw->di[i]; 7764 if (dmah != NULL) 7765 dma_walk_packets(dmah, dma_callback_fn, sta); 7766 } 7767} 7768 7769int brcms_c_get_curband(struct brcms_c_info *wlc) 7770{ 7771 return wlc->band->bandunit; 7772} 7773 7774void brcms_c_wait_for_tx_completion(struct brcms_c_info *wlc, bool drop) 7775{ 7776 int timeout = 20; 7777 int i; 7778 7779 /* Kick DMA to send any pending AMPDU */ 7780 for (i = 0; i < ARRAY_SIZE(wlc->hw->di); i++) 7781 if (wlc->hw->di[i]) 7782 dma_txflush(wlc->hw->di[i]); 7783 7784 /* wait for queue and DMA fifos to run dry */ 7785 while (brcms_txpktpendtot(wlc) > 0) { 7786 brcms_msleep(wlc->wl, 1); 7787 7788 if (--timeout == 0) 7789 break; 7790 } 7791 7792 WARN_ON_ONCE(timeout == 0); 7793} 7794 7795void brcms_c_set_beacon_listen_interval(struct brcms_c_info *wlc, u8 interval) 7796{ 7797 wlc->bcn_li_bcn = interval; 7798 if (wlc->pub->up) 7799 brcms_c_bcn_li_upd(wlc); 7800} 7801 7802int brcms_c_set_tx_power(struct brcms_c_info *wlc, int txpwr) 7803{ 7804 uint qdbm; 7805 7806 /* Remove override bit and clip to max qdbm value */ 7807 qdbm = min_t(uint, txpwr * BRCMS_TXPWR_DB_FACTOR, 0xff); 7808 return wlc_phy_txpower_set(wlc->band->pi, qdbm, false); 7809} 7810 7811int brcms_c_get_tx_power(struct brcms_c_info *wlc) 7812{ 7813 uint qdbm; 7814 bool override; 7815 7816 wlc_phy_txpower_get(wlc->band->pi, &qdbm, &override); 7817 7818 /* Return qdbm units */ 7819 return (int)(qdbm / BRCMS_TXPWR_DB_FACTOR); 7820} 7821 7822/* Process received frames */ 7823/* 7824 * Return true if more frames need to be processed. false otherwise. 7825 * Param 'bound' indicates max. # frames to process before break out. 7826 */ 7827static void brcms_c_recv(struct brcms_c_info *wlc, struct sk_buff *p) 7828{ 7829 struct d11rxhdr *rxh; 7830 struct ieee80211_hdr *h; 7831 uint len; 7832 bool is_amsdu; 7833 7834 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit); 7835 7836 /* frame starts with rxhdr */ 7837 rxh = (struct d11rxhdr *) (p->data); 7838 7839 /* strip off rxhdr */ 7840 skb_pull(p, BRCMS_HWRXOFF); 7841 7842 /* MAC inserts 2 pad bytes for a4 headers or QoS or A-MSDU subframes */ 7843 if (rxh->RxStatus1 & RXS_PBPRES) { 7844 if (p->len < 2) { 7845 brcms_err(wlc->hw->d11core, 7846 "wl%d: recv: rcvd runt of len %d\n", 7847 wlc->pub->unit, p->len); 7848 goto toss; 7849 } 7850 skb_pull(p, 2); 7851 } 7852 7853 h = (struct ieee80211_hdr *)(p->data + D11_PHY_HDR_LEN); 7854 len = p->len; 7855 7856 if (rxh->RxStatus1 & RXS_FCSERR) { 7857 if (!(wlc->filter_flags & FIF_FCSFAIL)) 7858 goto toss; 7859 } 7860 7861 /* check received pkt has at least frame control field */ 7862 if (len < D11_PHY_HDR_LEN + sizeof(h->frame_control)) 7863 goto toss; 7864 7865 /* not supporting A-MSDU */ 7866 is_amsdu = rxh->RxStatus2 & RXS_AMSDU_MASK; 7867 if (is_amsdu) 7868 goto toss; 7869 7870 brcms_c_recvctl(wlc, rxh, p); 7871 return; 7872 7873 toss: 7874 brcmu_pkt_buf_free_skb(p); 7875} 7876 7877/* Process received frames */ 7878/* 7879 * Return true if more frames need to be processed. false otherwise. 7880 * Param 'bound' indicates max. # frames to process before break out. 7881 */ 7882static bool 7883brcms_b_recv(struct brcms_hardware *wlc_hw, uint fifo, bool bound) 7884{ 7885 struct sk_buff *p; 7886 struct sk_buff *next = NULL; 7887 struct sk_buff_head recv_frames; 7888 7889 uint n = 0; 7890 uint bound_limit = bound ? RXBND : -1; 7891 7892 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit); 7893 skb_queue_head_init(&recv_frames); 7894 7895 /* gather received frames */ 7896 while (dma_rx(wlc_hw->di[fifo], &recv_frames)) { 7897 7898 /* !give others some time to run! */ 7899 if (++n >= bound_limit) 7900 break; 7901 } 7902 7903 /* post more rbufs */ 7904 dma_rxfill(wlc_hw->di[fifo]); 7905 7906 /* process each frame */ 7907 skb_queue_walk_safe(&recv_frames, p, next) { 7908 struct d11rxhdr_le *rxh_le; 7909 struct d11rxhdr *rxh; 7910 7911 skb_unlink(p, &recv_frames); 7912 rxh_le = (struct d11rxhdr_le *)p->data; 7913 rxh = (struct d11rxhdr *)p->data; 7914 7915 /* fixup rx header endianness */ 7916 rxh->RxFrameSize = le16_to_cpu(rxh_le->RxFrameSize); 7917 rxh->PhyRxStatus_0 = le16_to_cpu(rxh_le->PhyRxStatus_0); 7918 rxh->PhyRxStatus_1 = le16_to_cpu(rxh_le->PhyRxStatus_1); 7919 rxh->PhyRxStatus_2 = le16_to_cpu(rxh_le->PhyRxStatus_2); 7920 rxh->PhyRxStatus_3 = le16_to_cpu(rxh_le->PhyRxStatus_3); 7921 rxh->PhyRxStatus_4 = le16_to_cpu(rxh_le->PhyRxStatus_4); 7922 rxh->PhyRxStatus_5 = le16_to_cpu(rxh_le->PhyRxStatus_5); 7923 rxh->RxStatus1 = le16_to_cpu(rxh_le->RxStatus1); 7924 rxh->RxStatus2 = le16_to_cpu(rxh_le->RxStatus2); 7925 rxh->RxTSFTime = le16_to_cpu(rxh_le->RxTSFTime); 7926 rxh->RxChan = le16_to_cpu(rxh_le->RxChan); 7927 7928 brcms_c_recv(wlc_hw->wlc, p); 7929 } 7930 7931 return n >= bound_limit; 7932} 7933 7934/* second-level interrupt processing 7935 * Return true if another dpc needs to be re-scheduled. false otherwise. 7936 * Param 'bounded' indicates if applicable loops should be bounded. 7937 */ 7938bool brcms_c_dpc(struct brcms_c_info *wlc, bool bounded) 7939{ 7940 u32 macintstatus; 7941 struct brcms_hardware *wlc_hw = wlc->hw; 7942 struct bcma_device *core = wlc_hw->d11core; 7943 7944 if (brcms_deviceremoved(wlc)) { 7945 brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit, 7946 __func__); 7947 brcms_down(wlc->wl); 7948 return false; 7949 } 7950 7951 /* grab and clear the saved software intstatus bits */ 7952 macintstatus = wlc->macintstatus; 7953 wlc->macintstatus = 0; 7954 7955 BCMMSG(wlc->wiphy, "wl%d: macintstatus 0x%x\n", 7956 wlc_hw->unit, macintstatus); 7957 7958 WARN_ON(macintstatus & MI_PRQ); /* PRQ Interrupt in non-MBSS */ 7959 7960 /* tx status */ 7961 if (macintstatus & MI_TFS) { 7962 bool fatal; 7963 if (brcms_b_txstatus(wlc->hw, bounded, &fatal)) 7964 wlc->macintstatus |= MI_TFS; 7965 if (fatal) { 7966 brcms_err(core, "MI_TFS: fatal\n"); 7967 goto fatal; 7968 } 7969 } 7970 7971 if (macintstatus & (MI_TBTT | MI_DTIM_TBTT)) 7972 brcms_c_tbtt(wlc); 7973 7974 /* ATIM window end */ 7975 if (macintstatus & MI_ATIMWINEND) { 7976 brcms_dbg_info(core, "end of ATIM window\n"); 7977 bcma_set32(core, D11REGOFFS(maccommand), wlc->qvalid); 7978 wlc->qvalid = 0; 7979 } 7980 7981 /* 7982 * received data or control frame, MI_DMAINT is 7983 * indication of RX_FIFO interrupt 7984 */ 7985 if (macintstatus & MI_DMAINT) 7986 if (brcms_b_recv(wlc_hw, RX_FIFO, bounded)) 7987 wlc->macintstatus |= MI_DMAINT; 7988 7989 /* noise sample collected */ 7990 if (macintstatus & MI_BG_NOISE) 7991 wlc_phy_noise_sample_intr(wlc_hw->band->pi); 7992 7993 if (macintstatus & MI_GP0) { 7994 brcms_err(core, "wl%d: PSM microcode watchdog fired at %d " 7995 "(seconds). Resetting.\n", wlc_hw->unit, wlc_hw->now); 7996 7997 printk_once("%s : PSM Watchdog, chipid 0x%x, chiprev 0x%x\n", 7998 __func__, ai_get_chip_id(wlc_hw->sih), 7999 ai_get_chiprev(wlc_hw->sih)); 8000 brcms_fatal_error(wlc_hw->wlc->wl); 8001 } 8002 8003 /* gptimer timeout */ 8004 if (macintstatus & MI_TO) 8005 bcma_write32(core, D11REGOFFS(gptimer), 0); 8006 8007 if (macintstatus & MI_RFDISABLE) { 8008 brcms_dbg_info(core, "wl%d: BMAC Detected a change on the" 8009 " RF Disable Input\n", wlc_hw->unit); 8010 brcms_rfkill_set_hw_state(wlc->wl); 8011 } 8012 8013 /* it isn't done and needs to be resched if macintstatus is non-zero */ 8014 return wlc->macintstatus != 0; 8015 8016 fatal: 8017 brcms_fatal_error(wlc_hw->wlc->wl); 8018 return wlc->macintstatus != 0; 8019} 8020 8021void brcms_c_init(struct brcms_c_info *wlc, bool mute_tx) 8022{ 8023 struct bcma_device *core = wlc->hw->d11core; 8024 struct ieee80211_channel *ch = wlc->pub->ieee_hw->conf.channel; 8025 u16 chanspec; 8026 8027 brcms_dbg_info(core, "wl%d\n", wlc->pub->unit); 8028 8029 chanspec = ch20mhz_chspec(ch->hw_value); 8030 8031 brcms_b_init(wlc->hw, chanspec); 8032 8033 /* update beacon listen interval */ 8034 brcms_c_bcn_li_upd(wlc); 8035 8036 /* write ethernet address to core */ 8037 brcms_c_set_mac(wlc->bsscfg); 8038 brcms_c_set_bssid(wlc->bsscfg); 8039 8040 /* Update tsf_cfprep if associated and up */ 8041 if (wlc->pub->associated && wlc->bsscfg->up) { 8042 u32 bi; 8043 8044 /* get beacon period and convert to uS */ 8045 bi = wlc->bsscfg->current_bss->beacon_period << 10; 8046 /* 8047 * update since init path would reset 8048 * to default value 8049 */ 8050 bcma_write32(core, D11REGOFFS(tsf_cfprep), 8051 bi << CFPREP_CBI_SHIFT); 8052 8053 /* Update maccontrol PM related bits */ 8054 brcms_c_set_ps_ctrl(wlc); 8055 } 8056 8057 brcms_c_bandinit_ordered(wlc, chanspec); 8058 8059 /* init probe response timeout */ 8060 brcms_b_write_shm(wlc->hw, M_PRS_MAXTIME, wlc->prb_resp_timeout); 8061 8062 /* init max burst txop (framebursting) */ 8063 brcms_b_write_shm(wlc->hw, M_MBURST_TXOP, 8064 (wlc-> 8065 _rifs ? (EDCF_AC_VO_TXOP_AP << 5) : MAXFRAMEBURST_TXOP)); 8066 8067 /* initialize maximum allowed duty cycle */ 8068 brcms_c_duty_cycle_set(wlc, wlc->tx_duty_cycle_ofdm, true, true); 8069 brcms_c_duty_cycle_set(wlc, wlc->tx_duty_cycle_cck, false, true); 8070 8071 /* 8072 * Update some shared memory locations related to 8073 * max AMPDU size allowed to received 8074 */ 8075 brcms_c_ampdu_shm_upd(wlc->ampdu); 8076 8077 /* band-specific inits */ 8078 brcms_c_bsinit(wlc); 8079 8080 /* Enable EDCF mode (while the MAC is suspended) */ 8081 bcma_set16(core, D11REGOFFS(ifs_ctl), IFS_USEEDCF); 8082 brcms_c_edcf_setparams(wlc, false); 8083 8084 /* read the ucode version if we have not yet done so */ 8085 if (wlc->ucode_rev == 0) { 8086 wlc->ucode_rev = 8087 brcms_b_read_shm(wlc->hw, M_BOM_REV_MAJOR) << NBITS(u16); 8088 wlc->ucode_rev |= brcms_b_read_shm(wlc->hw, M_BOM_REV_MINOR); 8089 } 8090 8091 /* ..now really unleash hell (allow the MAC out of suspend) */ 8092 brcms_c_enable_mac(wlc); 8093 8094 /* suspend the tx fifos and mute the phy for preism cac time */ 8095 if (mute_tx) 8096 brcms_b_mute(wlc->hw, true); 8097 8098 /* enable the RF Disable Delay timer */ 8099 bcma_write32(core, D11REGOFFS(rfdisabledly), RFDISABLE_DEFAULT); 8100 8101 /* 8102 * Initialize WME parameters; if they haven't been set by some other 8103 * mechanism (IOVar, etc) then read them from the hardware. 8104 */ 8105 if (GFIELD(wlc->wme_retries[0], EDCF_SHORT) == 0) { 8106 /* Uninitialized; read from HW */ 8107 int ac; 8108 8109 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) 8110 wlc->wme_retries[ac] = 8111 brcms_b_read_shm(wlc->hw, M_AC_TXLMT_ADDR(ac)); 8112 } 8113} 8114 8115/* 8116 * The common driver entry routine. Error codes should be unique 8117 */ 8118struct brcms_c_info * 8119brcms_c_attach(struct brcms_info *wl, struct bcma_device *core, uint unit, 8120 bool piomode, uint *perr) 8121{ 8122 struct brcms_c_info *wlc; 8123 uint err = 0; 8124 uint i, j; 8125 struct brcms_pub *pub; 8126 8127 /* allocate struct brcms_c_info state and its substructures */ 8128 wlc = brcms_c_attach_malloc(unit, &err, 0); 8129 if (wlc == NULL) 8130 goto fail; 8131 wlc->wiphy = wl->wiphy; 8132 pub = wlc->pub; 8133 8134#if defined(DEBUG) 8135 wlc_info_dbg = wlc; 8136#endif 8137 8138 wlc->band = wlc->bandstate[0]; 8139 wlc->core = wlc->corestate; 8140 wlc->wl = wl; 8141 pub->unit = unit; 8142 pub->_piomode = piomode; 8143 wlc->bandinit_pending = false; 8144 8145 /* populate struct brcms_c_info with default values */ 8146 brcms_c_info_init(wlc, unit); 8147 8148 /* update sta/ap related parameters */ 8149 brcms_c_ap_upd(wlc); 8150 8151 /* 8152 * low level attach steps(all hw accesses go 8153 * inside, no more in rest of the attach) 8154 */ 8155 err = brcms_b_attach(wlc, core, unit, piomode); 8156 if (err) 8157 goto fail; 8158 8159 brcms_c_protection_upd(wlc, BRCMS_PROT_N_PAM_OVR, OFF); 8160 8161 pub->phy_11ncapable = BRCMS_PHY_11N_CAP(wlc->band); 8162 8163 /* disable allowed duty cycle */ 8164 wlc->tx_duty_cycle_ofdm = 0; 8165 wlc->tx_duty_cycle_cck = 0; 8166 8167 brcms_c_stf_phy_chain_calc(wlc); 8168 8169 /* txchain 1: txant 0, txchain 2: txant 1 */ 8170 if (BRCMS_ISNPHY(wlc->band) && (wlc->stf->txstreams == 1)) 8171 wlc->stf->txant = wlc->stf->hw_txchain - 1; 8172 8173 /* push to BMAC driver */ 8174 wlc_phy_stf_chain_init(wlc->band->pi, wlc->stf->hw_txchain, 8175 wlc->stf->hw_rxchain); 8176 8177 /* pull up some info resulting from the low attach */ 8178 for (i = 0; i < NFIFO; i++) 8179 wlc->core->txavail[i] = wlc->hw->txavail[i]; 8180 8181 memcpy(&wlc->perm_etheraddr, &wlc->hw->etheraddr, ETH_ALEN); 8182 memcpy(&pub->cur_etheraddr, &wlc->hw->etheraddr, ETH_ALEN); 8183 8184 for (j = 0; j < wlc->pub->_nbands; j++) { 8185 wlc->band = wlc->bandstate[j]; 8186 8187 if (!brcms_c_attach_stf_ant_init(wlc)) { 8188 err = 24; 8189 goto fail; 8190 } 8191 8192 /* default contention windows size limits */ 8193 wlc->band->CWmin = APHY_CWMIN; 8194 wlc->band->CWmax = PHY_CWMAX; 8195 8196 /* init gmode value */ 8197 if (wlc->band->bandtype == BRCM_BAND_2G) { 8198 wlc->band->gmode = GMODE_AUTO; 8199 brcms_c_protection_upd(wlc, BRCMS_PROT_G_USER, 8200 wlc->band->gmode); 8201 } 8202 8203 /* init _n_enab supported mode */ 8204 if (BRCMS_PHY_11N_CAP(wlc->band)) { 8205 pub->_n_enab = SUPPORT_11N; 8206 brcms_c_protection_upd(wlc, BRCMS_PROT_N_USER, 8207 ((pub->_n_enab == 8208 SUPPORT_11N) ? WL_11N_2x2 : 8209 WL_11N_3x3)); 8210 } 8211 8212 /* init per-band default rateset, depend on band->gmode */ 8213 brcms_default_rateset(wlc, &wlc->band->defrateset); 8214 8215 /* fill in hw_rateset */ 8216 brcms_c_rateset_filter(&wlc->band->defrateset, 8217 &wlc->band->hw_rateset, false, 8218 BRCMS_RATES_CCK_OFDM, BRCMS_RATE_MASK, 8219 (bool) (wlc->pub->_n_enab & SUPPORT_11N)); 8220 } 8221 8222 /* 8223 * update antenna config due to 8224 * wlc->stf->txant/txchain/ant_rx_ovr change 8225 */ 8226 brcms_c_stf_phy_txant_upd(wlc); 8227 8228 /* attach each modules */ 8229 err = brcms_c_attach_module(wlc); 8230 if (err != 0) 8231 goto fail; 8232 8233 if (!brcms_c_timers_init(wlc, unit)) { 8234 wiphy_err(wl->wiphy, "wl%d: %s: init_timer failed\n", unit, 8235 __func__); 8236 err = 32; 8237 goto fail; 8238 } 8239 8240 /* depend on rateset, gmode */ 8241 wlc->cmi = brcms_c_channel_mgr_attach(wlc); 8242 if (!wlc->cmi) { 8243 wiphy_err(wl->wiphy, "wl%d: %s: channel_mgr_attach failed" 8244 "\n", unit, __func__); 8245 err = 33; 8246 goto fail; 8247 } 8248 8249 /* init default when all parameters are ready, i.e. ->rateset */ 8250 brcms_c_bss_default_init(wlc); 8251 8252 /* 8253 * Complete the wlc default state initializations.. 8254 */ 8255 8256 wlc->bsscfg->wlc = wlc; 8257 8258 wlc->mimoft = FT_HT; 8259 wlc->mimo_40txbw = AUTO; 8260 wlc->ofdm_40txbw = AUTO; 8261 wlc->cck_40txbw = AUTO; 8262 brcms_c_update_mimo_band_bwcap(wlc, BRCMS_N_BW_20IN2G_40IN5G); 8263 8264 /* Set default values of SGI */ 8265 if (BRCMS_SGI_CAP_PHY(wlc)) { 8266 brcms_c_ht_update_sgi_rx(wlc, (BRCMS_N_SGI_20 | 8267 BRCMS_N_SGI_40)); 8268 } else if (BRCMS_ISSSLPNPHY(wlc->band)) { 8269 brcms_c_ht_update_sgi_rx(wlc, (BRCMS_N_SGI_20 | 8270 BRCMS_N_SGI_40)); 8271 } else { 8272 brcms_c_ht_update_sgi_rx(wlc, 0); 8273 } 8274 8275 brcms_b_antsel_set(wlc->hw, wlc->asi->antsel_avail); 8276 8277 if (perr) 8278 *perr = 0; 8279 8280 return wlc; 8281 8282 fail: 8283 wiphy_err(wl->wiphy, "wl%d: %s: failed with err %d\n", 8284 unit, __func__, err); 8285 if (wlc) 8286 brcms_c_detach(wlc); 8287 8288 if (perr) 8289 *perr = err; 8290 return NULL; 8291} 8292