main.c revision 937642f55ef7f8b9dcb202754d53853c7b36e15f
1/* 2 * Copyright (c) 2010 Broadcom Corporation 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17#include <linux/pci_ids.h> 18#include <linux/if_ether.h> 19#include <net/mac80211.h> 20#include <brcm_hw_ids.h> 21#include <aiutils.h> 22#include <chipcommon.h> 23#include "rate.h" 24#include "scb.h" 25#include "phy/phy_hal.h" 26#include "channel.h" 27#include "antsel.h" 28#include "stf.h" 29#include "ampdu.h" 30#include "mac80211_if.h" 31#include "ucode_loader.h" 32#include "main.h" 33#include "soc.h" 34 35/* 36 * Indication for txflowcontrol that all priority bits in 37 * TXQ_STOP_FOR_PRIOFC_MASK are to be considered. 38 */ 39#define ALLPRIO -1 40 41/* watchdog timer, in unit of ms */ 42#define TIMER_INTERVAL_WATCHDOG 1000 43/* radio monitor timer, in unit of ms */ 44#define TIMER_INTERVAL_RADIOCHK 800 45 46/* beacon interval, in unit of 1024TU */ 47#define BEACON_INTERVAL_DEFAULT 100 48 49/* n-mode support capability */ 50/* 2x2 includes both 1x1 & 2x2 devices 51 * reserved #define 2 for future when we want to separate 1x1 & 2x2 and 52 * control it independently 53 */ 54#define WL_11N_2x2 1 55#define WL_11N_3x3 3 56#define WL_11N_4x4 4 57 58#define EDCF_ACI_MASK 0x60 59#define EDCF_ACI_SHIFT 5 60#define EDCF_ECWMIN_MASK 0x0f 61#define EDCF_ECWMAX_SHIFT 4 62#define EDCF_AIFSN_MASK 0x0f 63#define EDCF_AIFSN_MAX 15 64#define EDCF_ECWMAX_MASK 0xf0 65 66#define EDCF_AC_BE_TXOP_STA 0x0000 67#define EDCF_AC_BK_TXOP_STA 0x0000 68#define EDCF_AC_VO_ACI_STA 0x62 69#define EDCF_AC_VO_ECW_STA 0x32 70#define EDCF_AC_VI_ACI_STA 0x42 71#define EDCF_AC_VI_ECW_STA 0x43 72#define EDCF_AC_BK_ECW_STA 0xA4 73#define EDCF_AC_VI_TXOP_STA 0x005e 74#define EDCF_AC_VO_TXOP_STA 0x002f 75#define EDCF_AC_BE_ACI_STA 0x03 76#define EDCF_AC_BE_ECW_STA 0xA4 77#define EDCF_AC_BK_ACI_STA 0x27 78#define EDCF_AC_VO_TXOP_AP 0x002f 79 80#define EDCF_TXOP2USEC(txop) ((txop) << 5) 81#define EDCF_ECW2CW(exp) ((1 << (exp)) - 1) 82 83#define APHY_SYMBOL_TIME 4 84#define APHY_PREAMBLE_TIME 16 85#define APHY_SIGNAL_TIME 4 86#define APHY_SIFS_TIME 16 87#define APHY_SERVICE_NBITS 16 88#define APHY_TAIL_NBITS 6 89#define BPHY_SIFS_TIME 10 90#define BPHY_PLCP_SHORT_TIME 96 91 92#define PREN_PREAMBLE 24 93#define PREN_MM_EXT 12 94#define PREN_PREAMBLE_EXT 4 95 96#define DOT11_MAC_HDR_LEN 24 97#define DOT11_ACK_LEN 10 98#define DOT11_BA_LEN 4 99#define DOT11_OFDM_SIGNAL_EXTENSION 6 100#define DOT11_MIN_FRAG_LEN 256 101#define DOT11_RTS_LEN 16 102#define DOT11_CTS_LEN 10 103#define DOT11_BA_BITMAP_LEN 128 104#define DOT11_MIN_BEACON_PERIOD 1 105#define DOT11_MAX_BEACON_PERIOD 0xFFFF 106#define DOT11_MAXNUMFRAGS 16 107#define DOT11_MAX_FRAG_LEN 2346 108 109#define BPHY_PLCP_TIME 192 110#define RIFS_11N_TIME 2 111 112/* length of the BCN template area */ 113#define BCN_TMPL_LEN 512 114 115/* brcms_bss_info flag bit values */ 116#define BRCMS_BSS_HT 0x0020 /* BSS is HT (MIMO) capable */ 117 118/* chip rx buffer offset */ 119#define BRCMS_HWRXOFF 38 120 121/* rfdisable delay timer 500 ms, runs of ALP clock */ 122#define RFDISABLE_DEFAULT 10000000 123 124#define BRCMS_TEMPSENSE_PERIOD 10 /* 10 second timeout */ 125 126/* precedences numbers for wlc queues. These are twice as may levels as 127 * 802.1D priorities. 128 * Odd numbers are used for HI priority traffic at same precedence levels 129 * These constants are used ONLY by wlc_prio2prec_map. Do not use them 130 * elsewhere. 131 */ 132#define _BRCMS_PREC_NONE 0 /* None = - */ 133#define _BRCMS_PREC_BK 2 /* BK - Background */ 134#define _BRCMS_PREC_BE 4 /* BE - Best-effort */ 135#define _BRCMS_PREC_EE 6 /* EE - Excellent-effort */ 136#define _BRCMS_PREC_CL 8 /* CL - Controlled Load */ 137#define _BRCMS_PREC_VI 10 /* Vi - Video */ 138#define _BRCMS_PREC_VO 12 /* Vo - Voice */ 139#define _BRCMS_PREC_NC 14 /* NC - Network Control */ 140 141/* synthpu_dly times in us */ 142#define SYNTHPU_DLY_APHY_US 3700 143#define SYNTHPU_DLY_BPHY_US 1050 144#define SYNTHPU_DLY_NPHY_US 2048 145#define SYNTHPU_DLY_LPPHY_US 300 146 147#define ANTCNT 10 /* vanilla M_MAX_ANTCNT val */ 148 149/* Per-AC retry limit register definitions; uses defs.h bitfield macros */ 150#define EDCF_SHORT_S 0 151#define EDCF_SFB_S 4 152#define EDCF_LONG_S 8 153#define EDCF_LFB_S 12 154#define EDCF_SHORT_M BITFIELD_MASK(4) 155#define EDCF_SFB_M BITFIELD_MASK(4) 156#define EDCF_LONG_M BITFIELD_MASK(4) 157#define EDCF_LFB_M BITFIELD_MASK(4) 158 159#define RETRY_SHORT_DEF 7 /* Default Short retry Limit */ 160#define RETRY_SHORT_MAX 255 /* Maximum Short retry Limit */ 161#define RETRY_LONG_DEF 4 /* Default Long retry count */ 162#define RETRY_SHORT_FB 3 /* Short count for fb rate */ 163#define RETRY_LONG_FB 2 /* Long count for fb rate */ 164 165#define APHY_CWMIN 15 166#define PHY_CWMAX 1023 167 168#define EDCF_AIFSN_MIN 1 169 170#define FRAGNUM_MASK 0xF 171 172#define APHY_SLOT_TIME 9 173#define BPHY_SLOT_TIME 20 174 175#define WL_SPURAVOID_OFF 0 176#define WL_SPURAVOID_ON1 1 177#define WL_SPURAVOID_ON2 2 178 179/* invalid core flags, use the saved coreflags */ 180#define BRCMS_USE_COREFLAGS 0xffffffff 181 182/* values for PLCPHdr_override */ 183#define BRCMS_PLCP_AUTO -1 184#define BRCMS_PLCP_SHORT 0 185#define BRCMS_PLCP_LONG 1 186 187/* values for g_protection_override and n_protection_override */ 188#define BRCMS_PROTECTION_AUTO -1 189#define BRCMS_PROTECTION_OFF 0 190#define BRCMS_PROTECTION_ON 1 191#define BRCMS_PROTECTION_MMHDR_ONLY 2 192#define BRCMS_PROTECTION_CTS_ONLY 3 193 194/* values for g_protection_control and n_protection_control */ 195#define BRCMS_PROTECTION_CTL_OFF 0 196#define BRCMS_PROTECTION_CTL_LOCAL 1 197#define BRCMS_PROTECTION_CTL_OVERLAP 2 198 199/* values for n_protection */ 200#define BRCMS_N_PROTECTION_OFF 0 201#define BRCMS_N_PROTECTION_OPTIONAL 1 202#define BRCMS_N_PROTECTION_20IN40 2 203#define BRCMS_N_PROTECTION_MIXEDMODE 3 204 205/* values for band specific 40MHz capabilities */ 206#define BRCMS_N_BW_20ALL 0 207#define BRCMS_N_BW_40ALL 1 208#define BRCMS_N_BW_20IN2G_40IN5G 2 209 210/* bitflags for SGI support (sgi_rx iovar) */ 211#define BRCMS_N_SGI_20 0x01 212#define BRCMS_N_SGI_40 0x02 213 214/* defines used by the nrate iovar */ 215/* MSC in use,indicates b0-6 holds an mcs */ 216#define NRATE_MCS_INUSE 0x00000080 217/* rate/mcs value */ 218#define NRATE_RATE_MASK 0x0000007f 219/* stf mode mask: siso, cdd, stbc, sdm */ 220#define NRATE_STF_MASK 0x0000ff00 221/* stf mode shift */ 222#define NRATE_STF_SHIFT 8 223/* bit indicate to override mcs only */ 224#define NRATE_OVERRIDE_MCS_ONLY 0x40000000 225#define NRATE_SGI_MASK 0x00800000 /* sgi mode */ 226#define NRATE_SGI_SHIFT 23 /* sgi mode */ 227#define NRATE_LDPC_CODING 0x00400000 /* adv coding in use */ 228#define NRATE_LDPC_SHIFT 22 /* ldpc shift */ 229 230#define NRATE_STF_SISO 0 /* stf mode SISO */ 231#define NRATE_STF_CDD 1 /* stf mode CDD */ 232#define NRATE_STF_STBC 2 /* stf mode STBC */ 233#define NRATE_STF_SDM 3 /* stf mode SDM */ 234 235#define MAX_DMA_SEGS 4 236 237/* Max # of entries in Tx FIFO based on 4kb page size */ 238#define NTXD 256 239/* Max # of entries in Rx FIFO based on 4kb page size */ 240#define NRXD 256 241 242/* try to keep this # rbufs posted to the chip */ 243#define NRXBUFPOST 32 244 245/* data msg txq hiwat mark */ 246#define BRCMS_DATAHIWAT 50 247 248/* max # frames to process in brcms_c_recv() */ 249#define RXBND 8 250/* max # tx status to process in wlc_txstatus() */ 251#define TXSBND 8 252 253/* brcmu_format_flags() bit description structure */ 254struct brcms_c_bit_desc { 255 u32 bit; 256 const char *name; 257}; 258 259/* 260 * The following table lists the buffer memory allocated to xmt fifos in HW. 261 * the size is in units of 256bytes(one block), total size is HW dependent 262 * ucode has default fifo partition, sw can overwrite if necessary 263 * 264 * This is documented in twiki under the topic UcodeTxFifo. Please ensure 265 * the twiki is updated before making changes. 266 */ 267 268/* Starting corerev for the fifo size table */ 269#define XMTFIFOTBL_STARTREV 20 270 271struct d11init { 272 __le16 addr; 273 __le16 size; 274 __le32 value; 275}; 276 277struct edcf_acparam { 278 u8 ACI; 279 u8 ECW; 280 u16 TXOP; 281} __packed; 282 283const u8 prio2fifo[NUMPRIO] = { 284 TX_AC_BE_FIFO, /* 0 BE AC_BE Best Effort */ 285 TX_AC_BK_FIFO, /* 1 BK AC_BK Background */ 286 TX_AC_BK_FIFO, /* 2 -- AC_BK Background */ 287 TX_AC_BE_FIFO, /* 3 EE AC_BE Best Effort */ 288 TX_AC_VI_FIFO, /* 4 CL AC_VI Video */ 289 TX_AC_VI_FIFO, /* 5 VI AC_VI Video */ 290 TX_AC_VO_FIFO, /* 6 VO AC_VO Voice */ 291 TX_AC_VO_FIFO /* 7 NC AC_VO Voice */ 292}; 293 294/* debug/trace */ 295uint brcm_msg_level = 296#if defined(BCMDBG) 297 LOG_ERROR_VAL; 298#else 299 0; 300#endif /* BCMDBG */ 301 302/* TX FIFO number to WME/802.1E Access Category */ 303static const u8 wme_fifo2ac[] = { 304 IEEE80211_AC_BK, 305 IEEE80211_AC_BE, 306 IEEE80211_AC_VI, 307 IEEE80211_AC_VO, 308 IEEE80211_AC_BE, 309 IEEE80211_AC_BE 310}; 311 312/* ieee80211 Access Category to TX FIFO number */ 313static const u8 wme_ac2fifo[] = { 314 TX_AC_VO_FIFO, 315 TX_AC_VI_FIFO, 316 TX_AC_BE_FIFO, 317 TX_AC_BK_FIFO 318}; 319 320/* 802.1D Priority to precedence queue mapping */ 321const u8 wlc_prio2prec_map[] = { 322 _BRCMS_PREC_BE, /* 0 BE - Best-effort */ 323 _BRCMS_PREC_BK, /* 1 BK - Background */ 324 _BRCMS_PREC_NONE, /* 2 None = - */ 325 _BRCMS_PREC_EE, /* 3 EE - Excellent-effort */ 326 _BRCMS_PREC_CL, /* 4 CL - Controlled Load */ 327 _BRCMS_PREC_VI, /* 5 Vi - Video */ 328 _BRCMS_PREC_VO, /* 6 Vo - Voice */ 329 _BRCMS_PREC_NC, /* 7 NC - Network Control */ 330}; 331 332static const u16 xmtfifo_sz[][NFIFO] = { 333 /* corerev 20: 5120, 49152, 49152, 5376, 4352, 1280 */ 334 {20, 192, 192, 21, 17, 5}, 335 /* corerev 21: 2304, 14848, 5632, 3584, 3584, 1280 */ 336 {9, 58, 22, 14, 14, 5}, 337 /* corerev 22: 5120, 49152, 49152, 5376, 4352, 1280 */ 338 {20, 192, 192, 21, 17, 5}, 339 /* corerev 23: 5120, 49152, 49152, 5376, 4352, 1280 */ 340 {20, 192, 192, 21, 17, 5}, 341 /* corerev 24: 2304, 14848, 5632, 3584, 3584, 1280 */ 342 {9, 58, 22, 14, 14, 5}, 343}; 344 345#ifdef BCMDBG 346static const char * const fifo_names[] = { 347 "AC_BK", "AC_BE", "AC_VI", "AC_VO", "BCMC", "ATIM" }; 348#else 349static const char fifo_names[6][0]; 350#endif 351 352#ifdef BCMDBG 353/* pointer to most recently allocated wl/wlc */ 354static struct brcms_c_info *wlc_info_dbg = (struct brcms_c_info *) (NULL); 355#endif 356 357/* Find basic rate for a given rate */ 358static u8 brcms_basic_rate(struct brcms_c_info *wlc, u32 rspec) 359{ 360 if (is_mcs_rate(rspec)) 361 return wlc->band->basic_rate[mcs_table[rspec & RSPEC_RATE_MASK] 362 .leg_ofdm]; 363 return wlc->band->basic_rate[rspec & RSPEC_RATE_MASK]; 364} 365 366static u16 frametype(u32 rspec, u8 mimoframe) 367{ 368 if (is_mcs_rate(rspec)) 369 return mimoframe; 370 return is_cck_rate(rspec) ? FT_CCK : FT_OFDM; 371} 372 373/* currently the best mechanism for determining SIFS is the band in use */ 374static u16 get_sifs(struct brcms_band *band) 375{ 376 return band->bandtype == BRCM_BAND_5G ? APHY_SIFS_TIME : 377 BPHY_SIFS_TIME; 378} 379 380/* 381 * Detect Card removed. 382 * Even checking an sbconfig register read will not false trigger when the core 383 * is in reset it breaks CF address mechanism. Accessing gphy phyversion will 384 * cause SB error if aphy is in reset on 4306B0-DB. Need a simple accessible 385 * reg with fixed 0/1 pattern (some platforms return all 0). 386 * If clocks are present, call the sb routine which will figure out if the 387 * device is removed. 388 */ 389static bool brcms_deviceremoved(struct brcms_c_info *wlc) 390{ 391 u32 macctrl; 392 393 if (!wlc->hw->clk) 394 return ai_deviceremoved(wlc->hw->sih); 395 macctrl = bcma_read32(wlc->hw->d11core, 396 D11REGOFFS(maccontrol)); 397 return (macctrl & (MCTL_PSM_JMP_0 | MCTL_IHR_EN)) != MCTL_IHR_EN; 398} 399 400/* sum the individual fifo tx pending packet counts */ 401static s16 brcms_txpktpendtot(struct brcms_c_info *wlc) 402{ 403 return wlc->core->txpktpend[0] + wlc->core->txpktpend[1] + 404 wlc->core->txpktpend[2] + wlc->core->txpktpend[3]; 405} 406 407static bool brcms_is_mband_unlocked(struct brcms_c_info *wlc) 408{ 409 return wlc->pub->_nbands > 1 && !wlc->bandlocked; 410} 411 412static int brcms_chspec_bw(u16 chanspec) 413{ 414 if (CHSPEC_IS40(chanspec)) 415 return BRCMS_40_MHZ; 416 if (CHSPEC_IS20(chanspec)) 417 return BRCMS_20_MHZ; 418 419 return BRCMS_10_MHZ; 420} 421 422static void brcms_c_bsscfg_mfree(struct brcms_bss_cfg *cfg) 423{ 424 if (cfg == NULL) 425 return; 426 427 kfree(cfg->current_bss); 428 kfree(cfg); 429} 430 431static void brcms_c_detach_mfree(struct brcms_c_info *wlc) 432{ 433 if (wlc == NULL) 434 return; 435 436 brcms_c_bsscfg_mfree(wlc->bsscfg); 437 kfree(wlc->pub); 438 kfree(wlc->modulecb); 439 kfree(wlc->default_bss); 440 kfree(wlc->protection); 441 kfree(wlc->stf); 442 kfree(wlc->bandstate[0]); 443 kfree(wlc->corestate->macstat_snapshot); 444 kfree(wlc->corestate); 445 kfree(wlc->hw->bandstate[0]); 446 kfree(wlc->hw); 447 448 /* free the wlc */ 449 kfree(wlc); 450 wlc = NULL; 451} 452 453static struct brcms_bss_cfg *brcms_c_bsscfg_malloc(uint unit) 454{ 455 struct brcms_bss_cfg *cfg; 456 457 cfg = kzalloc(sizeof(struct brcms_bss_cfg), GFP_ATOMIC); 458 if (cfg == NULL) 459 goto fail; 460 461 cfg->current_bss = kzalloc(sizeof(struct brcms_bss_info), GFP_ATOMIC); 462 if (cfg->current_bss == NULL) 463 goto fail; 464 465 return cfg; 466 467 fail: 468 brcms_c_bsscfg_mfree(cfg); 469 return NULL; 470} 471 472static struct brcms_c_info * 473brcms_c_attach_malloc(uint unit, uint *err, uint devid) 474{ 475 struct brcms_c_info *wlc; 476 477 wlc = kzalloc(sizeof(struct brcms_c_info), GFP_ATOMIC); 478 if (wlc == NULL) { 479 *err = 1002; 480 goto fail; 481 } 482 483 /* allocate struct brcms_c_pub state structure */ 484 wlc->pub = kzalloc(sizeof(struct brcms_pub), GFP_ATOMIC); 485 if (wlc->pub == NULL) { 486 *err = 1003; 487 goto fail; 488 } 489 wlc->pub->wlc = wlc; 490 491 /* allocate struct brcms_hardware state structure */ 492 493 wlc->hw = kzalloc(sizeof(struct brcms_hardware), GFP_ATOMIC); 494 if (wlc->hw == NULL) { 495 *err = 1005; 496 goto fail; 497 } 498 wlc->hw->wlc = wlc; 499 500 wlc->hw->bandstate[0] = 501 kzalloc(sizeof(struct brcms_hw_band) * MAXBANDS, GFP_ATOMIC); 502 if (wlc->hw->bandstate[0] == NULL) { 503 *err = 1006; 504 goto fail; 505 } else { 506 int i; 507 508 for (i = 1; i < MAXBANDS; i++) 509 wlc->hw->bandstate[i] = (struct brcms_hw_band *) 510 ((unsigned long)wlc->hw->bandstate[0] + 511 (sizeof(struct brcms_hw_band) * i)); 512 } 513 514 wlc->modulecb = 515 kzalloc(sizeof(struct modulecb) * BRCMS_MAXMODULES, GFP_ATOMIC); 516 if (wlc->modulecb == NULL) { 517 *err = 1009; 518 goto fail; 519 } 520 521 wlc->default_bss = kzalloc(sizeof(struct brcms_bss_info), GFP_ATOMIC); 522 if (wlc->default_bss == NULL) { 523 *err = 1010; 524 goto fail; 525 } 526 527 wlc->bsscfg = brcms_c_bsscfg_malloc(unit); 528 if (wlc->bsscfg == NULL) { 529 *err = 1011; 530 goto fail; 531 } 532 533 wlc->protection = kzalloc(sizeof(struct brcms_protection), 534 GFP_ATOMIC); 535 if (wlc->protection == NULL) { 536 *err = 1016; 537 goto fail; 538 } 539 540 wlc->stf = kzalloc(sizeof(struct brcms_stf), GFP_ATOMIC); 541 if (wlc->stf == NULL) { 542 *err = 1017; 543 goto fail; 544 } 545 546 wlc->bandstate[0] = 547 kzalloc(sizeof(struct brcms_band)*MAXBANDS, GFP_ATOMIC); 548 if (wlc->bandstate[0] == NULL) { 549 *err = 1025; 550 goto fail; 551 } else { 552 int i; 553 554 for (i = 1; i < MAXBANDS; i++) 555 wlc->bandstate[i] = (struct brcms_band *) 556 ((unsigned long)wlc->bandstate[0] 557 + (sizeof(struct brcms_band)*i)); 558 } 559 560 wlc->corestate = kzalloc(sizeof(struct brcms_core), GFP_ATOMIC); 561 if (wlc->corestate == NULL) { 562 *err = 1026; 563 goto fail; 564 } 565 566 wlc->corestate->macstat_snapshot = 567 kzalloc(sizeof(struct macstat), GFP_ATOMIC); 568 if (wlc->corestate->macstat_snapshot == NULL) { 569 *err = 1027; 570 goto fail; 571 } 572 573 return wlc; 574 575 fail: 576 brcms_c_detach_mfree(wlc); 577 return NULL; 578} 579 580/* 581 * Update the slot timing for standard 11b/g (20us slots) 582 * or shortslot 11g (9us slots) 583 * The PSM needs to be suspended for this call. 584 */ 585static void brcms_b_update_slot_timing(struct brcms_hardware *wlc_hw, 586 bool shortslot) 587{ 588 struct bcma_device *core = wlc_hw->d11core; 589 590 if (shortslot) { 591 /* 11g short slot: 11a timing */ 592 bcma_write16(core, D11REGOFFS(ifs_slot), 0x0207); 593 brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, APHY_SLOT_TIME); 594 } else { 595 /* 11g long slot: 11b timing */ 596 bcma_write16(core, D11REGOFFS(ifs_slot), 0x0212); 597 brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, BPHY_SLOT_TIME); 598 } 599} 600 601/* 602 * calculate frame duration of a given rate and length, return 603 * time in usec unit 604 */ 605static uint brcms_c_calc_frame_time(struct brcms_c_info *wlc, u32 ratespec, 606 u8 preamble_type, uint mac_len) 607{ 608 uint nsyms, dur = 0, Ndps, kNdps; 609 uint rate = rspec2rate(ratespec); 610 611 if (rate == 0) { 612 wiphy_err(wlc->wiphy, "wl%d: WAR: using rate of 1 mbps\n", 613 wlc->pub->unit); 614 rate = BRCM_RATE_1M; 615 } 616 617 BCMMSG(wlc->wiphy, "wl%d: rspec 0x%x, preamble_type %d, len%d\n", 618 wlc->pub->unit, ratespec, preamble_type, mac_len); 619 620 if (is_mcs_rate(ratespec)) { 621 uint mcs = ratespec & RSPEC_RATE_MASK; 622 int tot_streams = mcs_2_txstreams(mcs) + rspec_stc(ratespec); 623 624 dur = PREN_PREAMBLE + (tot_streams * PREN_PREAMBLE_EXT); 625 if (preamble_type == BRCMS_MM_PREAMBLE) 626 dur += PREN_MM_EXT; 627 /* 1000Ndbps = kbps * 4 */ 628 kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec), 629 rspec_issgi(ratespec)) * 4; 630 631 if (rspec_stc(ratespec) == 0) 632 nsyms = 633 CEIL((APHY_SERVICE_NBITS + 8 * mac_len + 634 APHY_TAIL_NBITS) * 1000, kNdps); 635 else 636 /* STBC needs to have even number of symbols */ 637 nsyms = 638 2 * 639 CEIL((APHY_SERVICE_NBITS + 8 * mac_len + 640 APHY_TAIL_NBITS) * 1000, 2 * kNdps); 641 642 dur += APHY_SYMBOL_TIME * nsyms; 643 if (wlc->band->bandtype == BRCM_BAND_2G) 644 dur += DOT11_OFDM_SIGNAL_EXTENSION; 645 } else if (is_ofdm_rate(rate)) { 646 dur = APHY_PREAMBLE_TIME; 647 dur += APHY_SIGNAL_TIME; 648 /* Ndbps = Mbps * 4 = rate(500Kbps) * 2 */ 649 Ndps = rate * 2; 650 /* NSyms = CEILING((SERVICE + 8*NBytes + TAIL) / Ndbps) */ 651 nsyms = 652 CEIL((APHY_SERVICE_NBITS + 8 * mac_len + APHY_TAIL_NBITS), 653 Ndps); 654 dur += APHY_SYMBOL_TIME * nsyms; 655 if (wlc->band->bandtype == BRCM_BAND_2G) 656 dur += DOT11_OFDM_SIGNAL_EXTENSION; 657 } else { 658 /* 659 * calc # bits * 2 so factor of 2 in rate (1/2 mbps) 660 * will divide out 661 */ 662 mac_len = mac_len * 8 * 2; 663 /* calc ceiling of bits/rate = microseconds of air time */ 664 dur = (mac_len + rate - 1) / rate; 665 if (preamble_type & BRCMS_SHORT_PREAMBLE) 666 dur += BPHY_PLCP_SHORT_TIME; 667 else 668 dur += BPHY_PLCP_TIME; 669 } 670 return dur; 671} 672 673static void brcms_c_write_inits(struct brcms_hardware *wlc_hw, 674 const struct d11init *inits) 675{ 676 struct bcma_device *core = wlc_hw->d11core; 677 int i; 678 uint offset; 679 u16 size; 680 u32 value; 681 682 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit); 683 684 for (i = 0; inits[i].addr != cpu_to_le16(0xffff); i++) { 685 size = le16_to_cpu(inits[i].size); 686 offset = le16_to_cpu(inits[i].addr); 687 value = le32_to_cpu(inits[i].value); 688 if (size == 2) 689 bcma_write16(core, offset, value); 690 else if (size == 4) 691 bcma_write32(core, offset, value); 692 else 693 break; 694 } 695} 696 697static void brcms_c_write_mhf(struct brcms_hardware *wlc_hw, u16 *mhfs) 698{ 699 u8 idx; 700 u16 addr[] = { 701 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4, 702 M_HOST_FLAGS5 703 }; 704 705 for (idx = 0; idx < MHFMAX; idx++) 706 brcms_b_write_shm(wlc_hw, addr[idx], mhfs[idx]); 707} 708 709static void brcms_c_ucode_bsinit(struct brcms_hardware *wlc_hw) 710{ 711 struct wiphy *wiphy = wlc_hw->wlc->wiphy; 712 struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode; 713 714 /* init microcode host flags */ 715 brcms_c_write_mhf(wlc_hw, wlc_hw->band->mhfs); 716 717 /* do band-specific ucode IHR, SHM, and SCR inits */ 718 if (D11REV_IS(wlc_hw->corerev, 23)) { 719 if (BRCMS_ISNPHY(wlc_hw->band)) 720 brcms_c_write_inits(wlc_hw, ucode->d11n0bsinitvals16); 721 else 722 wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev" 723 " %d\n", __func__, wlc_hw->unit, 724 wlc_hw->corerev); 725 } else { 726 if (D11REV_IS(wlc_hw->corerev, 24)) { 727 if (BRCMS_ISLCNPHY(wlc_hw->band)) 728 brcms_c_write_inits(wlc_hw, 729 ucode->d11lcn0bsinitvals24); 730 else 731 wiphy_err(wiphy, "%s: wl%d: unsupported phy in" 732 " core rev %d\n", __func__, 733 wlc_hw->unit, wlc_hw->corerev); 734 } else { 735 wiphy_err(wiphy, "%s: wl%d: unsupported corerev %d\n", 736 __func__, wlc_hw->unit, wlc_hw->corerev); 737 } 738 } 739} 740 741static void brcms_b_core_ioctl(struct brcms_hardware *wlc_hw, u32 m, u32 v) 742{ 743 struct bcma_device *core = wlc_hw->d11core; 744 u32 ioctl = bcma_aread32(core, BCMA_IOCTL) & ~m; 745 746 bcma_awrite32(core, BCMA_IOCTL, ioctl | v); 747} 748 749static void brcms_b_core_phy_clk(struct brcms_hardware *wlc_hw, bool clk) 750{ 751 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: clk %d\n", wlc_hw->unit, clk); 752 753 wlc_hw->phyclk = clk; 754 755 if (OFF == clk) { /* clear gmode bit, put phy into reset */ 756 757 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC | SICF_GMODE), 758 (SICF_PRST | SICF_FGC)); 759 udelay(1); 760 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC), SICF_PRST); 761 udelay(1); 762 763 } else { /* take phy out of reset */ 764 765 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC), SICF_FGC); 766 udelay(1); 767 brcms_b_core_ioctl(wlc_hw, SICF_FGC, 0); 768 udelay(1); 769 770 } 771} 772 773/* low-level band switch utility routine */ 774static void brcms_c_setxband(struct brcms_hardware *wlc_hw, uint bandunit) 775{ 776 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit, 777 bandunit); 778 779 wlc_hw->band = wlc_hw->bandstate[bandunit]; 780 781 /* 782 * BMAC_NOTE: 783 * until we eliminate need for wlc->band refs in low level code 784 */ 785 wlc_hw->wlc->band = wlc_hw->wlc->bandstate[bandunit]; 786 787 /* set gmode core flag */ 788 if (wlc_hw->sbclk && !wlc_hw->noreset) { 789 u32 gmode = 0; 790 791 if (bandunit == 0) 792 gmode = SICF_GMODE; 793 794 brcms_b_core_ioctl(wlc_hw, SICF_GMODE, gmode); 795 } 796} 797 798/* switch to new band but leave it inactive */ 799static u32 brcms_c_setband_inact(struct brcms_c_info *wlc, uint bandunit) 800{ 801 struct brcms_hardware *wlc_hw = wlc->hw; 802 u32 macintmask; 803 u32 macctrl; 804 805 BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit); 806 macctrl = bcma_read32(wlc_hw->d11core, 807 D11REGOFFS(maccontrol)); 808 WARN_ON((macctrl & MCTL_EN_MAC) != 0); 809 810 /* disable interrupts */ 811 macintmask = brcms_intrsoff(wlc->wl); 812 813 /* radio off */ 814 wlc_phy_switch_radio(wlc_hw->band->pi, OFF); 815 816 brcms_b_core_phy_clk(wlc_hw, OFF); 817 818 brcms_c_setxband(wlc_hw, bandunit); 819 820 return macintmask; 821} 822 823/* process an individual struct tx_status */ 824static bool 825brcms_c_dotxstatus(struct brcms_c_info *wlc, struct tx_status *txs) 826{ 827 struct sk_buff *p; 828 uint queue; 829 struct d11txh *txh; 830 struct scb *scb = NULL; 831 bool free_pdu; 832 int tx_rts, tx_frame_count, tx_rts_count; 833 uint totlen, supr_status; 834 bool lastframe; 835 struct ieee80211_hdr *h; 836 u16 mcl; 837 struct ieee80211_tx_info *tx_info; 838 struct ieee80211_tx_rate *txrate; 839 int i; 840 841 /* discard intermediate indications for ucode with one legitimate case: 842 * e.g. if "useRTS" is set. ucode did a successful rts/cts exchange, 843 * but the subsequent tx of DATA failed. so it will start rts/cts 844 * from the beginning (resetting the rts transmission count) 845 */ 846 if (!(txs->status & TX_STATUS_AMPDU) 847 && (txs->status & TX_STATUS_INTERMEDIATE)) { 848 wiphy_err(wlc->wiphy, "%s: INTERMEDIATE but not AMPDU\n", 849 __func__); 850 return false; 851 } 852 853 queue = txs->frameid & TXFID_QUEUE_MASK; 854 if (queue >= NFIFO) { 855 p = NULL; 856 goto fatal; 857 } 858 859 p = dma_getnexttxp(wlc->hw->di[queue], DMA_RANGE_TRANSMITTED); 860 if (p == NULL) 861 goto fatal; 862 863 txh = (struct d11txh *) (p->data); 864 mcl = le16_to_cpu(txh->MacTxControlLow); 865 866 if (txs->phyerr) { 867 if (brcm_msg_level & LOG_ERROR_VAL) { 868 wiphy_err(wlc->wiphy, "phyerr 0x%x, rate 0x%x\n", 869 txs->phyerr, txh->MainRates); 870 brcms_c_print_txdesc(txh); 871 } 872 brcms_c_print_txstatus(txs); 873 } 874 875 if (txs->frameid != le16_to_cpu(txh->TxFrameID)) 876 goto fatal; 877 tx_info = IEEE80211_SKB_CB(p); 878 h = (struct ieee80211_hdr *)((u8 *) (txh + 1) + D11_PHY_HDR_LEN); 879 880 if (tx_info->control.sta) 881 scb = &wlc->pri_scb; 882 883 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) { 884 brcms_c_ampdu_dotxstatus(wlc->ampdu, scb, p, txs); 885 return false; 886 } 887 888 supr_status = txs->status & TX_STATUS_SUPR_MASK; 889 if (supr_status == TX_STATUS_SUPR_BADCH) 890 BCMMSG(wlc->wiphy, 891 "%s: Pkt tx suppressed, possibly channel %d\n", 892 __func__, CHSPEC_CHANNEL(wlc->default_bss->chanspec)); 893 894 tx_rts = le16_to_cpu(txh->MacTxControlLow) & TXC_SENDRTS; 895 tx_frame_count = 896 (txs->status & TX_STATUS_FRM_RTX_MASK) >> TX_STATUS_FRM_RTX_SHIFT; 897 tx_rts_count = 898 (txs->status & TX_STATUS_RTS_RTX_MASK) >> TX_STATUS_RTS_RTX_SHIFT; 899 900 lastframe = !ieee80211_has_morefrags(h->frame_control); 901 902 if (!lastframe) { 903 wiphy_err(wlc->wiphy, "Not last frame!\n"); 904 } else { 905 /* 906 * Set information to be consumed by Minstrel ht. 907 * 908 * The "fallback limit" is the number of tx attempts a given 909 * MPDU is sent at the "primary" rate. Tx attempts beyond that 910 * limit are sent at the "secondary" rate. 911 * A 'short frame' does not exceed RTS treshold. 912 */ 913 u16 sfbl, /* Short Frame Rate Fallback Limit */ 914 lfbl, /* Long Frame Rate Fallback Limit */ 915 fbl; 916 917 if (queue < IEEE80211_NUM_ACS) { 918 sfbl = GFIELD(wlc->wme_retries[wme_fifo2ac[queue]], 919 EDCF_SFB); 920 lfbl = GFIELD(wlc->wme_retries[wme_fifo2ac[queue]], 921 EDCF_LFB); 922 } else { 923 sfbl = wlc->SFBL; 924 lfbl = wlc->LFBL; 925 } 926 927 txrate = tx_info->status.rates; 928 if (txrate[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) 929 fbl = lfbl; 930 else 931 fbl = sfbl; 932 933 ieee80211_tx_info_clear_status(tx_info); 934 935 if ((tx_frame_count > fbl) && (txrate[1].idx >= 0)) { 936 /* 937 * rate selection requested a fallback rate 938 * and we used it 939 */ 940 txrate[0].count = fbl; 941 txrate[1].count = tx_frame_count - fbl; 942 } else { 943 /* 944 * rate selection did not request fallback rate, or 945 * we didn't need it 946 */ 947 txrate[0].count = tx_frame_count; 948 /* 949 * rc80211_minstrel.c:minstrel_tx_status() expects 950 * unused rates to be marked with idx = -1 951 */ 952 txrate[1].idx = -1; 953 txrate[1].count = 0; 954 } 955 956 /* clear the rest of the rates */ 957 for (i = 2; i < IEEE80211_TX_MAX_RATES; i++) { 958 txrate[i].idx = -1; 959 txrate[i].count = 0; 960 } 961 962 if (txs->status & TX_STATUS_ACK_RCV) 963 tx_info->flags |= IEEE80211_TX_STAT_ACK; 964 } 965 966 totlen = p->len; 967 free_pdu = true; 968 969 brcms_c_txfifo_complete(wlc, queue, 1); 970 971 if (lastframe) { 972 /* remove PLCP & Broadcom tx descriptor header */ 973 skb_pull(p, D11_PHY_HDR_LEN); 974 skb_pull(p, D11_TXH_LEN); 975 ieee80211_tx_status_irqsafe(wlc->pub->ieee_hw, p); 976 } else { 977 wiphy_err(wlc->wiphy, "%s: Not last frame => not calling " 978 "tx_status\n", __func__); 979 } 980 981 return false; 982 983 fatal: 984 if (p) 985 brcmu_pkt_buf_free_skb(p); 986 987 return true; 988 989} 990 991/* process tx completion events in BMAC 992 * Return true if more tx status need to be processed. false otherwise. 993 */ 994static bool 995brcms_b_txstatus(struct brcms_hardware *wlc_hw, bool bound, bool *fatal) 996{ 997 bool morepending = false; 998 struct brcms_c_info *wlc = wlc_hw->wlc; 999 struct bcma_device *core; 1000 struct tx_status txstatus, *txs; 1001 u32 s1, s2; 1002 uint n = 0; 1003 /* 1004 * Param 'max_tx_num' indicates max. # tx status to process before 1005 * break out. 1006 */ 1007 uint max_tx_num = bound ? TXSBND : -1; 1008 1009 BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit); 1010 1011 txs = &txstatus; 1012 core = wlc_hw->d11core; 1013 *fatal = false; 1014 s1 = bcma_read32(core, D11REGOFFS(frmtxstatus)); 1015 while (!(*fatal) 1016 && (s1 & TXS_V)) { 1017 1018 if (s1 == 0xffffffff) { 1019 wiphy_err(wlc->wiphy, "wl%d: %s: dead chip\n", 1020 wlc_hw->unit, __func__); 1021 return morepending; 1022 } 1023 s2 = bcma_read32(core, D11REGOFFS(frmtxstatus2)); 1024 1025 txs->status = s1 & TXS_STATUS_MASK; 1026 txs->frameid = (s1 & TXS_FID_MASK) >> TXS_FID_SHIFT; 1027 txs->sequence = s2 & TXS_SEQ_MASK; 1028 txs->phyerr = (s2 & TXS_PTX_MASK) >> TXS_PTX_SHIFT; 1029 txs->lasttxtime = 0; 1030 1031 *fatal = brcms_c_dotxstatus(wlc_hw->wlc, txs); 1032 1033 /* !give others some time to run! */ 1034 if (++n >= max_tx_num) 1035 break; 1036 s1 = bcma_read32(core, D11REGOFFS(frmtxstatus)); 1037 } 1038 1039 if (*fatal) 1040 return 0; 1041 1042 if (n >= max_tx_num) 1043 morepending = true; 1044 1045 if (!pktq_empty(&wlc->pkt_queue->q)) 1046 brcms_c_send_q(wlc); 1047 1048 return morepending; 1049} 1050 1051static void brcms_c_tbtt(struct brcms_c_info *wlc) 1052{ 1053 if (!wlc->bsscfg->BSS) 1054 /* 1055 * DirFrmQ is now valid...defer setting until end 1056 * of ATIM window 1057 */ 1058 wlc->qvalid |= MCMD_DIRFRMQVAL; 1059} 1060 1061/* set initial host flags value */ 1062static void 1063brcms_c_mhfdef(struct brcms_c_info *wlc, u16 *mhfs, u16 mhf2_init) 1064{ 1065 struct brcms_hardware *wlc_hw = wlc->hw; 1066 1067 memset(mhfs, 0, MHFMAX * sizeof(u16)); 1068 1069 mhfs[MHF2] |= mhf2_init; 1070 1071 /* prohibit use of slowclock on multifunction boards */ 1072 if (wlc_hw->boardflags & BFL_NOPLLDOWN) 1073 mhfs[MHF1] |= MHF1_FORCEFASTCLK; 1074 1075 if (BRCMS_ISNPHY(wlc_hw->band) && NREV_LT(wlc_hw->band->phyrev, 2)) { 1076 mhfs[MHF2] |= MHF2_NPHY40MHZ_WAR; 1077 mhfs[MHF1] |= MHF1_IQSWAP_WAR; 1078 } 1079} 1080 1081static uint 1082dmareg(uint direction, uint fifonum) 1083{ 1084 if (direction == DMA_TX) 1085 return offsetof(struct d11regs, fifo64regs[fifonum].dmaxmt); 1086 return offsetof(struct d11regs, fifo64regs[fifonum].dmarcv); 1087} 1088 1089static bool brcms_b_attach_dmapio(struct brcms_c_info *wlc, uint j, bool wme) 1090{ 1091 uint i; 1092 char name[8]; 1093 /* 1094 * ucode host flag 2 needed for pio mode, independent of band and fifo 1095 */ 1096 u16 pio_mhf2 = 0; 1097 struct brcms_hardware *wlc_hw = wlc->hw; 1098 uint unit = wlc_hw->unit; 1099 struct wiphy *wiphy = wlc->wiphy; 1100 1101 /* name and offsets for dma_attach */ 1102 snprintf(name, sizeof(name), "wl%d", unit); 1103 1104 if (wlc_hw->di[0] == NULL) { /* Init FIFOs */ 1105 int dma_attach_err = 0; 1106 1107 /* 1108 * FIFO 0 1109 * TX: TX_AC_BK_FIFO (TX AC Background data packets) 1110 * RX: RX_FIFO (RX data packets) 1111 */ 1112 wlc_hw->di[0] = dma_attach(name, wlc_hw->sih, wlc_hw->d11core, 1113 (wme ? dmareg(DMA_TX, 0) : 0), 1114 dmareg(DMA_RX, 0), 1115 (wme ? NTXD : 0), NRXD, 1116 RXBUFSZ, -1, NRXBUFPOST, 1117 BRCMS_HWRXOFF, &brcm_msg_level); 1118 dma_attach_err |= (NULL == wlc_hw->di[0]); 1119 1120 /* 1121 * FIFO 1 1122 * TX: TX_AC_BE_FIFO (TX AC Best-Effort data packets) 1123 * (legacy) TX_DATA_FIFO (TX data packets) 1124 * RX: UNUSED 1125 */ 1126 wlc_hw->di[1] = dma_attach(name, wlc_hw->sih, wlc_hw->d11core, 1127 dmareg(DMA_TX, 1), 0, 1128 NTXD, 0, 0, -1, 0, 0, 1129 &brcm_msg_level); 1130 dma_attach_err |= (NULL == wlc_hw->di[1]); 1131 1132 /* 1133 * FIFO 2 1134 * TX: TX_AC_VI_FIFO (TX AC Video data packets) 1135 * RX: UNUSED 1136 */ 1137 wlc_hw->di[2] = dma_attach(name, wlc_hw->sih, wlc_hw->d11core, 1138 dmareg(DMA_TX, 2), 0, 1139 NTXD, 0, 0, -1, 0, 0, 1140 &brcm_msg_level); 1141 dma_attach_err |= (NULL == wlc_hw->di[2]); 1142 /* 1143 * FIFO 3 1144 * TX: TX_AC_VO_FIFO (TX AC Voice data packets) 1145 * (legacy) TX_CTL_FIFO (TX control & mgmt packets) 1146 */ 1147 wlc_hw->di[3] = dma_attach(name, wlc_hw->sih, wlc_hw->d11core, 1148 dmareg(DMA_TX, 3), 1149 0, NTXD, 0, 0, -1, 1150 0, 0, &brcm_msg_level); 1151 dma_attach_err |= (NULL == wlc_hw->di[3]); 1152/* Cleaner to leave this as if with AP defined */ 1153 1154 if (dma_attach_err) { 1155 wiphy_err(wiphy, "wl%d: wlc_attach: dma_attach failed" 1156 "\n", unit); 1157 return false; 1158 } 1159 1160 /* get pointer to dma engine tx flow control variable */ 1161 for (i = 0; i < NFIFO; i++) 1162 if (wlc_hw->di[i]) 1163 wlc_hw->txavail[i] = 1164 (uint *) dma_getvar(wlc_hw->di[i], 1165 "&txavail"); 1166 } 1167 1168 /* initial ucode host flags */ 1169 brcms_c_mhfdef(wlc, wlc_hw->band->mhfs, pio_mhf2); 1170 1171 return true; 1172} 1173 1174static void brcms_b_detach_dmapio(struct brcms_hardware *wlc_hw) 1175{ 1176 uint j; 1177 1178 for (j = 0; j < NFIFO; j++) { 1179 if (wlc_hw->di[j]) { 1180 dma_detach(wlc_hw->di[j]); 1181 wlc_hw->di[j] = NULL; 1182 } 1183 } 1184} 1185 1186/* 1187 * Initialize brcms_c_info default values ... 1188 * may get overrides later in this function 1189 * BMAC_NOTES, move low out and resolve the dangling ones 1190 */ 1191static void brcms_b_info_init(struct brcms_hardware *wlc_hw) 1192{ 1193 struct brcms_c_info *wlc = wlc_hw->wlc; 1194 1195 /* set default sw macintmask value */ 1196 wlc->defmacintmask = DEF_MACINTMASK; 1197 1198 /* various 802.11g modes */ 1199 wlc_hw->shortslot = false; 1200 1201 wlc_hw->SFBL = RETRY_SHORT_FB; 1202 wlc_hw->LFBL = RETRY_LONG_FB; 1203 1204 /* default mac retry limits */ 1205 wlc_hw->SRL = RETRY_SHORT_DEF; 1206 wlc_hw->LRL = RETRY_LONG_DEF; 1207 wlc_hw->chanspec = ch20mhz_chspec(1); 1208} 1209 1210static void brcms_b_wait_for_wake(struct brcms_hardware *wlc_hw) 1211{ 1212 /* delay before first read of ucode state */ 1213 udelay(40); 1214 1215 /* wait until ucode is no longer asleep */ 1216 SPINWAIT((brcms_b_read_shm(wlc_hw, M_UCODE_DBGST) == 1217 DBGST_ASLEEP), wlc_hw->wlc->fastpwrup_dly); 1218} 1219 1220/* control chip clock to save power, enable dynamic clock or force fast clock */ 1221static void brcms_b_clkctl_clk(struct brcms_hardware *wlc_hw, uint mode) 1222{ 1223 if (ai_get_cccaps(wlc_hw->sih) & CC_CAP_PMU) { 1224 /* new chips with PMU, CCS_FORCEHT will distribute the HT clock 1225 * on backplane, but mac core will still run on ALP(not HT) when 1226 * it enters powersave mode, which means the FCA bit may not be 1227 * set. Should wakeup mac if driver wants it to run on HT. 1228 */ 1229 1230 if (wlc_hw->clk) { 1231 if (mode == CLK_FAST) { 1232 bcma_set32(wlc_hw->d11core, 1233 D11REGOFFS(clk_ctl_st), 1234 CCS_FORCEHT); 1235 1236 udelay(64); 1237 1238 SPINWAIT( 1239 ((bcma_read32(wlc_hw->d11core, 1240 D11REGOFFS(clk_ctl_st)) & 1241 CCS_HTAVAIL) == 0), 1242 PMU_MAX_TRANSITION_DLY); 1243 WARN_ON(!(bcma_read32(wlc_hw->d11core, 1244 D11REGOFFS(clk_ctl_st)) & 1245 CCS_HTAVAIL)); 1246 } else { 1247 if ((ai_get_pmurev(wlc_hw->sih) == 0) && 1248 (bcma_read32(wlc_hw->d11core, 1249 D11REGOFFS(clk_ctl_st)) & 1250 (CCS_FORCEHT | CCS_HTAREQ))) 1251 SPINWAIT( 1252 ((bcma_read32(wlc_hw->d11core, 1253 offsetof(struct d11regs, 1254 clk_ctl_st)) & 1255 CCS_HTAVAIL) == 0), 1256 PMU_MAX_TRANSITION_DLY); 1257 bcma_mask32(wlc_hw->d11core, 1258 D11REGOFFS(clk_ctl_st), 1259 ~CCS_FORCEHT); 1260 } 1261 } 1262 wlc_hw->forcefastclk = (mode == CLK_FAST); 1263 } else { 1264 1265 /* old chips w/o PMU, force HT through cc, 1266 * then use FCA to verify mac is running fast clock 1267 */ 1268 1269 wlc_hw->forcefastclk = ai_clkctl_cc(wlc_hw->sih, mode); 1270 1271 /* check fast clock is available (if core is not in reset) */ 1272 if (wlc_hw->forcefastclk && wlc_hw->clk) 1273 WARN_ON(!(bcma_aread32(wlc_hw->d11core, BCMA_IOST) & 1274 SISF_FCLKA)); 1275 1276 /* 1277 * keep the ucode wake bit on if forcefastclk is on since we 1278 * do not want ucode to put us back to slow clock when it dozes 1279 * for PM mode. Code below matches the wake override bit with 1280 * current forcefastclk state. Only setting bit in wake_override 1281 * instead of waking ucode immediately since old code had this 1282 * behavior. Older code set wlc->forcefastclk but only had the 1283 * wake happen if the wakup_ucode work (protected by an up 1284 * check) was executed just below. 1285 */ 1286 if (wlc_hw->forcefastclk) 1287 mboolset(wlc_hw->wake_override, 1288 BRCMS_WAKE_OVERRIDE_FORCEFAST); 1289 else 1290 mboolclr(wlc_hw->wake_override, 1291 BRCMS_WAKE_OVERRIDE_FORCEFAST); 1292 } 1293} 1294 1295/* set or clear ucode host flag bits 1296 * it has an optimization for no-change write 1297 * it only writes through shared memory when the core has clock; 1298 * pre-CLK changes should use wlc_write_mhf to get around the optimization 1299 * 1300 * 1301 * bands values are: BRCM_BAND_AUTO <--- Current band only 1302 * BRCM_BAND_5G <--- 5G band only 1303 * BRCM_BAND_2G <--- 2G band only 1304 * BRCM_BAND_ALL <--- All bands 1305 */ 1306void 1307brcms_b_mhf(struct brcms_hardware *wlc_hw, u8 idx, u16 mask, u16 val, 1308 int bands) 1309{ 1310 u16 save; 1311 u16 addr[MHFMAX] = { 1312 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4, 1313 M_HOST_FLAGS5 1314 }; 1315 struct brcms_hw_band *band; 1316 1317 if ((val & ~mask) || idx >= MHFMAX) 1318 return; /* error condition */ 1319 1320 switch (bands) { 1321 /* Current band only or all bands, 1322 * then set the band to current band 1323 */ 1324 case BRCM_BAND_AUTO: 1325 case BRCM_BAND_ALL: 1326 band = wlc_hw->band; 1327 break; 1328 case BRCM_BAND_5G: 1329 band = wlc_hw->bandstate[BAND_5G_INDEX]; 1330 break; 1331 case BRCM_BAND_2G: 1332 band = wlc_hw->bandstate[BAND_2G_INDEX]; 1333 break; 1334 default: 1335 band = NULL; /* error condition */ 1336 } 1337 1338 if (band) { 1339 save = band->mhfs[idx]; 1340 band->mhfs[idx] = (band->mhfs[idx] & ~mask) | val; 1341 1342 /* optimization: only write through if changed, and 1343 * changed band is the current band 1344 */ 1345 if (wlc_hw->clk && (band->mhfs[idx] != save) 1346 && (band == wlc_hw->band)) 1347 brcms_b_write_shm(wlc_hw, addr[idx], 1348 (u16) band->mhfs[idx]); 1349 } 1350 1351 if (bands == BRCM_BAND_ALL) { 1352 wlc_hw->bandstate[0]->mhfs[idx] = 1353 (wlc_hw->bandstate[0]->mhfs[idx] & ~mask) | val; 1354 wlc_hw->bandstate[1]->mhfs[idx] = 1355 (wlc_hw->bandstate[1]->mhfs[idx] & ~mask) | val; 1356 } 1357} 1358 1359/* set the maccontrol register to desired reset state and 1360 * initialize the sw cache of the register 1361 */ 1362static void brcms_c_mctrl_reset(struct brcms_hardware *wlc_hw) 1363{ 1364 /* IHR accesses are always enabled, PSM disabled, HPS off and WAKE on */ 1365 wlc_hw->maccontrol = 0; 1366 wlc_hw->suspended_fifos = 0; 1367 wlc_hw->wake_override = 0; 1368 wlc_hw->mute_override = 0; 1369 brcms_b_mctrl(wlc_hw, ~0, MCTL_IHR_EN | MCTL_WAKE); 1370} 1371 1372/* 1373 * write the software state of maccontrol and 1374 * overrides to the maccontrol register 1375 */ 1376static void brcms_c_mctrl_write(struct brcms_hardware *wlc_hw) 1377{ 1378 u32 maccontrol = wlc_hw->maccontrol; 1379 1380 /* OR in the wake bit if overridden */ 1381 if (wlc_hw->wake_override) 1382 maccontrol |= MCTL_WAKE; 1383 1384 /* set AP and INFRA bits for mute if needed */ 1385 if (wlc_hw->mute_override) { 1386 maccontrol &= ~(MCTL_AP); 1387 maccontrol |= MCTL_INFRA; 1388 } 1389 1390 bcma_write32(wlc_hw->d11core, D11REGOFFS(maccontrol), 1391 maccontrol); 1392} 1393 1394/* set or clear maccontrol bits */ 1395void brcms_b_mctrl(struct brcms_hardware *wlc_hw, u32 mask, u32 val) 1396{ 1397 u32 maccontrol; 1398 u32 new_maccontrol; 1399 1400 if (val & ~mask) 1401 return; /* error condition */ 1402 maccontrol = wlc_hw->maccontrol; 1403 new_maccontrol = (maccontrol & ~mask) | val; 1404 1405 /* if the new maccontrol value is the same as the old, nothing to do */ 1406 if (new_maccontrol == maccontrol) 1407 return; 1408 1409 /* something changed, cache the new value */ 1410 wlc_hw->maccontrol = new_maccontrol; 1411 1412 /* write the new values with overrides applied */ 1413 brcms_c_mctrl_write(wlc_hw); 1414} 1415 1416void brcms_c_ucode_wake_override_set(struct brcms_hardware *wlc_hw, 1417 u32 override_bit) 1418{ 1419 if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE)) { 1420 mboolset(wlc_hw->wake_override, override_bit); 1421 return; 1422 } 1423 1424 mboolset(wlc_hw->wake_override, override_bit); 1425 1426 brcms_c_mctrl_write(wlc_hw); 1427 brcms_b_wait_for_wake(wlc_hw); 1428} 1429 1430void brcms_c_ucode_wake_override_clear(struct brcms_hardware *wlc_hw, 1431 u32 override_bit) 1432{ 1433 mboolclr(wlc_hw->wake_override, override_bit); 1434 1435 if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE)) 1436 return; 1437 1438 brcms_c_mctrl_write(wlc_hw); 1439} 1440 1441/* When driver needs ucode to stop beaconing, it has to make sure that 1442 * MCTL_AP is clear and MCTL_INFRA is set 1443 * Mode MCTL_AP MCTL_INFRA 1444 * AP 1 1 1445 * STA 0 1 <--- This will ensure no beacons 1446 * IBSS 0 0 1447 */ 1448static void brcms_c_ucode_mute_override_set(struct brcms_hardware *wlc_hw) 1449{ 1450 wlc_hw->mute_override = 1; 1451 1452 /* if maccontrol already has AP == 0 and INFRA == 1 without this 1453 * override, then there is no change to write 1454 */ 1455 if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA) 1456 return; 1457 1458 brcms_c_mctrl_write(wlc_hw); 1459} 1460 1461/* Clear the override on AP and INFRA bits */ 1462static void brcms_c_ucode_mute_override_clear(struct brcms_hardware *wlc_hw) 1463{ 1464 if (wlc_hw->mute_override == 0) 1465 return; 1466 1467 wlc_hw->mute_override = 0; 1468 1469 /* if maccontrol already has AP == 0 and INFRA == 1 without this 1470 * override, then there is no change to write 1471 */ 1472 if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA) 1473 return; 1474 1475 brcms_c_mctrl_write(wlc_hw); 1476} 1477 1478/* 1479 * Write a MAC address to the given match reg offset in the RXE match engine. 1480 */ 1481static void 1482brcms_b_set_addrmatch(struct brcms_hardware *wlc_hw, int match_reg_offset, 1483 const u8 *addr) 1484{ 1485 struct bcma_device *core = wlc_hw->d11core; 1486 u16 mac_l; 1487 u16 mac_m; 1488 u16 mac_h; 1489 1490 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: brcms_b_set_addrmatch\n", 1491 wlc_hw->unit); 1492 1493 mac_l = addr[0] | (addr[1] << 8); 1494 mac_m = addr[2] | (addr[3] << 8); 1495 mac_h = addr[4] | (addr[5] << 8); 1496 1497 /* enter the MAC addr into the RXE match registers */ 1498 bcma_write16(core, D11REGOFFS(rcm_ctl), 1499 RCM_INC_DATA | match_reg_offset); 1500 bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_l); 1501 bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_m); 1502 bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_h); 1503} 1504 1505void 1506brcms_b_write_template_ram(struct brcms_hardware *wlc_hw, int offset, int len, 1507 void *buf) 1508{ 1509 struct bcma_device *core = wlc_hw->d11core; 1510 u32 word; 1511 __le32 word_le; 1512 __be32 word_be; 1513 bool be_bit; 1514 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit); 1515 1516 bcma_write32(core, D11REGOFFS(tplatewrptr), offset); 1517 1518 /* if MCTL_BIGEND bit set in mac control register, 1519 * the chip swaps data in fifo, as well as data in 1520 * template ram 1521 */ 1522 be_bit = (bcma_read32(core, D11REGOFFS(maccontrol)) & MCTL_BIGEND) != 0; 1523 1524 while (len > 0) { 1525 memcpy(&word, buf, sizeof(u32)); 1526 1527 if (be_bit) { 1528 word_be = cpu_to_be32(word); 1529 word = *(u32 *)&word_be; 1530 } else { 1531 word_le = cpu_to_le32(word); 1532 word = *(u32 *)&word_le; 1533 } 1534 1535 bcma_write32(core, D11REGOFFS(tplatewrdata), word); 1536 1537 buf = (u8 *) buf + sizeof(u32); 1538 len -= sizeof(u32); 1539 } 1540} 1541 1542static void brcms_b_set_cwmin(struct brcms_hardware *wlc_hw, u16 newmin) 1543{ 1544 wlc_hw->band->CWmin = newmin; 1545 1546 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr), 1547 OBJADDR_SCR_SEL | S_DOT11_CWMIN); 1548 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr)); 1549 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), newmin); 1550} 1551 1552static void brcms_b_set_cwmax(struct brcms_hardware *wlc_hw, u16 newmax) 1553{ 1554 wlc_hw->band->CWmax = newmax; 1555 1556 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr), 1557 OBJADDR_SCR_SEL | S_DOT11_CWMAX); 1558 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr)); 1559 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), newmax); 1560} 1561 1562void brcms_b_bw_set(struct brcms_hardware *wlc_hw, u16 bw) 1563{ 1564 bool fastclk; 1565 1566 /* request FAST clock if not on */ 1567 fastclk = wlc_hw->forcefastclk; 1568 if (!fastclk) 1569 brcms_b_clkctl_clk(wlc_hw, CLK_FAST); 1570 1571 wlc_phy_bw_state_set(wlc_hw->band->pi, bw); 1572 1573 brcms_b_phy_reset(wlc_hw); 1574 wlc_phy_init(wlc_hw->band->pi, wlc_phy_chanspec_get(wlc_hw->band->pi)); 1575 1576 /* restore the clk */ 1577 if (!fastclk) 1578 brcms_b_clkctl_clk(wlc_hw, CLK_DYNAMIC); 1579} 1580 1581static void brcms_b_upd_synthpu(struct brcms_hardware *wlc_hw) 1582{ 1583 u16 v; 1584 struct brcms_c_info *wlc = wlc_hw->wlc; 1585 /* update SYNTHPU_DLY */ 1586 1587 if (BRCMS_ISLCNPHY(wlc->band)) 1588 v = SYNTHPU_DLY_LPPHY_US; 1589 else if (BRCMS_ISNPHY(wlc->band) && (NREV_GE(wlc->band->phyrev, 3))) 1590 v = SYNTHPU_DLY_NPHY_US; 1591 else 1592 v = SYNTHPU_DLY_BPHY_US; 1593 1594 brcms_b_write_shm(wlc_hw, M_SYNTHPU_DLY, v); 1595} 1596 1597static void brcms_c_ucode_txant_set(struct brcms_hardware *wlc_hw) 1598{ 1599 u16 phyctl; 1600 u16 phytxant = wlc_hw->bmac_phytxant; 1601 u16 mask = PHY_TXC_ANT_MASK; 1602 1603 /* set the Probe Response frame phy control word */ 1604 phyctl = brcms_b_read_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS); 1605 phyctl = (phyctl & ~mask) | phytxant; 1606 brcms_b_write_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS, phyctl); 1607 1608 /* set the Response (ACK/CTS) frame phy control word */ 1609 phyctl = brcms_b_read_shm(wlc_hw, M_RSP_PCTLWD); 1610 phyctl = (phyctl & ~mask) | phytxant; 1611 brcms_b_write_shm(wlc_hw, M_RSP_PCTLWD, phyctl); 1612} 1613 1614static u16 brcms_b_ofdm_ratetable_offset(struct brcms_hardware *wlc_hw, 1615 u8 rate) 1616{ 1617 uint i; 1618 u8 plcp_rate = 0; 1619 struct plcp_signal_rate_lookup { 1620 u8 rate; 1621 u8 signal_rate; 1622 }; 1623 /* OFDM RATE sub-field of PLCP SIGNAL field, per 802.11 sec 17.3.4.1 */ 1624 const struct plcp_signal_rate_lookup rate_lookup[] = { 1625 {BRCM_RATE_6M, 0xB}, 1626 {BRCM_RATE_9M, 0xF}, 1627 {BRCM_RATE_12M, 0xA}, 1628 {BRCM_RATE_18M, 0xE}, 1629 {BRCM_RATE_24M, 0x9}, 1630 {BRCM_RATE_36M, 0xD}, 1631 {BRCM_RATE_48M, 0x8}, 1632 {BRCM_RATE_54M, 0xC} 1633 }; 1634 1635 for (i = 0; i < ARRAY_SIZE(rate_lookup); i++) { 1636 if (rate == rate_lookup[i].rate) { 1637 plcp_rate = rate_lookup[i].signal_rate; 1638 break; 1639 } 1640 } 1641 1642 /* Find the SHM pointer to the rate table entry by looking in the 1643 * Direct-map Table 1644 */ 1645 return 2 * brcms_b_read_shm(wlc_hw, M_RT_DIRMAP_A + (plcp_rate * 2)); 1646} 1647 1648static void brcms_upd_ofdm_pctl1_table(struct brcms_hardware *wlc_hw) 1649{ 1650 u8 rate; 1651 u8 rates[8] = { 1652 BRCM_RATE_6M, BRCM_RATE_9M, BRCM_RATE_12M, BRCM_RATE_18M, 1653 BRCM_RATE_24M, BRCM_RATE_36M, BRCM_RATE_48M, BRCM_RATE_54M 1654 }; 1655 u16 entry_ptr; 1656 u16 pctl1; 1657 uint i; 1658 1659 if (!BRCMS_PHY_11N_CAP(wlc_hw->band)) 1660 return; 1661 1662 /* walk the phy rate table and update the entries */ 1663 for (i = 0; i < ARRAY_SIZE(rates); i++) { 1664 rate = rates[i]; 1665 1666 entry_ptr = brcms_b_ofdm_ratetable_offset(wlc_hw, rate); 1667 1668 /* read the SHM Rate Table entry OFDM PCTL1 values */ 1669 pctl1 = 1670 brcms_b_read_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS); 1671 1672 /* modify the value */ 1673 pctl1 &= ~PHY_TXC1_MODE_MASK; 1674 pctl1 |= (wlc_hw->hw_stf_ss_opmode << PHY_TXC1_MODE_SHIFT); 1675 1676 /* Update the SHM Rate Table entry OFDM PCTL1 values */ 1677 brcms_b_write_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS, 1678 pctl1); 1679 } 1680} 1681 1682/* band-specific init */ 1683static void brcms_b_bsinit(struct brcms_c_info *wlc, u16 chanspec) 1684{ 1685 struct brcms_hardware *wlc_hw = wlc->hw; 1686 1687 BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit, 1688 wlc_hw->band->bandunit); 1689 1690 brcms_c_ucode_bsinit(wlc_hw); 1691 1692 wlc_phy_init(wlc_hw->band->pi, chanspec); 1693 1694 brcms_c_ucode_txant_set(wlc_hw); 1695 1696 /* 1697 * cwmin is band-specific, update hardware 1698 * with value for current band 1699 */ 1700 brcms_b_set_cwmin(wlc_hw, wlc_hw->band->CWmin); 1701 brcms_b_set_cwmax(wlc_hw, wlc_hw->band->CWmax); 1702 1703 brcms_b_update_slot_timing(wlc_hw, 1704 wlc_hw->band->bandtype == BRCM_BAND_5G ? 1705 true : wlc_hw->shortslot); 1706 1707 /* write phytype and phyvers */ 1708 brcms_b_write_shm(wlc_hw, M_PHYTYPE, (u16) wlc_hw->band->phytype); 1709 brcms_b_write_shm(wlc_hw, M_PHYVER, (u16) wlc_hw->band->phyrev); 1710 1711 /* 1712 * initialize the txphyctl1 rate table since 1713 * shmem is shared between bands 1714 */ 1715 brcms_upd_ofdm_pctl1_table(wlc_hw); 1716 1717 brcms_b_upd_synthpu(wlc_hw); 1718} 1719 1720/* Perform a soft reset of the PHY PLL */ 1721void brcms_b_core_phypll_reset(struct brcms_hardware *wlc_hw) 1722{ 1723 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit); 1724 1725 ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_addr), 1726 ~0, 0); 1727 udelay(1); 1728 ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data), 1729 0x4, 0); 1730 udelay(1); 1731 ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data), 1732 0x4, 4); 1733 udelay(1); 1734 ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data), 1735 0x4, 0); 1736 udelay(1); 1737} 1738 1739/* light way to turn on phy clock without reset for NPHY only 1740 * refer to brcms_b_core_phy_clk for full version 1741 */ 1742void brcms_b_phyclk_fgc(struct brcms_hardware *wlc_hw, bool clk) 1743{ 1744 /* support(necessary for NPHY and HYPHY) only */ 1745 if (!BRCMS_ISNPHY(wlc_hw->band)) 1746 return; 1747 1748 if (ON == clk) 1749 brcms_b_core_ioctl(wlc_hw, SICF_FGC, SICF_FGC); 1750 else 1751 brcms_b_core_ioctl(wlc_hw, SICF_FGC, 0); 1752 1753} 1754 1755void brcms_b_macphyclk_set(struct brcms_hardware *wlc_hw, bool clk) 1756{ 1757 if (ON == clk) 1758 brcms_b_core_ioctl(wlc_hw, SICF_MPCLKE, SICF_MPCLKE); 1759 else 1760 brcms_b_core_ioctl(wlc_hw, SICF_MPCLKE, 0); 1761} 1762 1763void brcms_b_phy_reset(struct brcms_hardware *wlc_hw) 1764{ 1765 struct brcms_phy_pub *pih = wlc_hw->band->pi; 1766 u32 phy_bw_clkbits; 1767 bool phy_in_reset = false; 1768 1769 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit); 1770 1771 if (pih == NULL) 1772 return; 1773 1774 phy_bw_clkbits = wlc_phy_clk_bwbits(wlc_hw->band->pi); 1775 1776 /* Specific reset sequence required for NPHY rev 3 and 4 */ 1777 if (BRCMS_ISNPHY(wlc_hw->band) && NREV_GE(wlc_hw->band->phyrev, 3) && 1778 NREV_LE(wlc_hw->band->phyrev, 4)) { 1779 /* Set the PHY bandwidth */ 1780 brcms_b_core_ioctl(wlc_hw, SICF_BWMASK, phy_bw_clkbits); 1781 1782 udelay(1); 1783 1784 /* Perform a soft reset of the PHY PLL */ 1785 brcms_b_core_phypll_reset(wlc_hw); 1786 1787 /* reset the PHY */ 1788 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_PCLKE), 1789 (SICF_PRST | SICF_PCLKE)); 1790 phy_in_reset = true; 1791 } else { 1792 brcms_b_core_ioctl(wlc_hw, 1793 (SICF_PRST | SICF_PCLKE | SICF_BWMASK), 1794 (SICF_PRST | SICF_PCLKE | phy_bw_clkbits)); 1795 } 1796 1797 udelay(2); 1798 brcms_b_core_phy_clk(wlc_hw, ON); 1799 1800 if (pih) 1801 wlc_phy_anacore(pih, ON); 1802} 1803 1804/* switch to and initialize new band */ 1805static void brcms_b_setband(struct brcms_hardware *wlc_hw, uint bandunit, 1806 u16 chanspec) { 1807 struct brcms_c_info *wlc = wlc_hw->wlc; 1808 u32 macintmask; 1809 1810 /* Enable the d11 core before accessing it */ 1811 if (!bcma_core_is_enabled(wlc_hw->d11core)) { 1812 bcma_core_enable(wlc_hw->d11core, 0); 1813 brcms_c_mctrl_reset(wlc_hw); 1814 } 1815 1816 macintmask = brcms_c_setband_inact(wlc, bandunit); 1817 1818 if (!wlc_hw->up) 1819 return; 1820 1821 brcms_b_core_phy_clk(wlc_hw, ON); 1822 1823 /* band-specific initializations */ 1824 brcms_b_bsinit(wlc, chanspec); 1825 1826 /* 1827 * If there are any pending software interrupt bits, 1828 * then replace these with a harmless nonzero value 1829 * so brcms_c_dpc() will re-enable interrupts when done. 1830 */ 1831 if (wlc->macintstatus) 1832 wlc->macintstatus = MI_DMAINT; 1833 1834 /* restore macintmask */ 1835 brcms_intrsrestore(wlc->wl, macintmask); 1836 1837 /* ucode should still be suspended.. */ 1838 WARN_ON((bcma_read32(wlc_hw->d11core, D11REGOFFS(maccontrol)) & 1839 MCTL_EN_MAC) != 0); 1840} 1841 1842static bool brcms_c_isgoodchip(struct brcms_hardware *wlc_hw) 1843{ 1844 1845 /* reject unsupported corerev */ 1846 if (!CONF_HAS(D11CONF, wlc_hw->corerev)) { 1847 wiphy_err(wlc_hw->wlc->wiphy, "unsupported core rev %d\n", 1848 wlc_hw->corerev); 1849 return false; 1850 } 1851 1852 return true; 1853} 1854 1855/* Validate some board info parameters */ 1856static bool brcms_c_validboardtype(struct brcms_hardware *wlc_hw) 1857{ 1858 uint boardrev = wlc_hw->boardrev; 1859 1860 /* 4 bits each for board type, major, minor, and tiny version */ 1861 uint brt = (boardrev & 0xf000) >> 12; 1862 uint b0 = (boardrev & 0xf00) >> 8; 1863 uint b1 = (boardrev & 0xf0) >> 4; 1864 uint b2 = boardrev & 0xf; 1865 1866 /* voards from other vendors are always considered valid */ 1867 if (ai_get_boardvendor(wlc_hw->sih) != PCI_VENDOR_ID_BROADCOM) 1868 return true; 1869 1870 /* do some boardrev sanity checks when boardvendor is Broadcom */ 1871 if (boardrev == 0) 1872 return false; 1873 1874 if (boardrev <= 0xff) 1875 return true; 1876 1877 if ((brt > 2) || (brt == 0) || (b0 > 9) || (b0 == 0) || (b1 > 9) 1878 || (b2 > 9)) 1879 return false; 1880 1881 return true; 1882} 1883 1884static char *brcms_c_get_macaddr(struct brcms_hardware *wlc_hw) 1885{ 1886 enum brcms_srom_id var_id = BRCMS_SROM_MACADDR; 1887 char *macaddr; 1888 1889 /* If macaddr exists, use it (Sromrev4, CIS, ...). */ 1890 macaddr = getvar(wlc_hw->sih, var_id); 1891 if (macaddr != NULL) 1892 return macaddr; 1893 1894 if (wlc_hw->_nbands > 1) 1895 var_id = BRCMS_SROM_ET1MACADDR; 1896 else 1897 var_id = BRCMS_SROM_IL0MACADDR; 1898 1899 macaddr = getvar(wlc_hw->sih, var_id); 1900 if (macaddr == NULL) 1901 wiphy_err(wlc_hw->wlc->wiphy, "wl%d: wlc_get_macaddr: macaddr " 1902 "getvar(%d) not found\n", wlc_hw->unit, var_id); 1903 1904 return macaddr; 1905} 1906 1907/* power both the pll and external oscillator on/off */ 1908static void brcms_b_xtal(struct brcms_hardware *wlc_hw, bool want) 1909{ 1910 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: want %d\n", wlc_hw->unit, want); 1911 1912 /* 1913 * dont power down if plldown is false or 1914 * we must poll hw radio disable 1915 */ 1916 if (!want && wlc_hw->pllreq) 1917 return; 1918 1919 if (wlc_hw->sih) 1920 ai_clkctl_xtal(wlc_hw->sih, XTAL | PLL, want); 1921 1922 wlc_hw->sbclk = want; 1923 if (!wlc_hw->sbclk) { 1924 wlc_hw->clk = false; 1925 if (wlc_hw->band && wlc_hw->band->pi) 1926 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false); 1927 } 1928} 1929 1930/* 1931 * Return true if radio is disabled, otherwise false. 1932 * hw radio disable signal is an external pin, users activate it asynchronously 1933 * this function could be called when driver is down and w/o clock 1934 * it operates on different registers depending on corerev and boardflag. 1935 */ 1936static bool brcms_b_radio_read_hwdisabled(struct brcms_hardware *wlc_hw) 1937{ 1938 bool v, clk, xtal; 1939 u32 flags = 0; 1940 1941 xtal = wlc_hw->sbclk; 1942 if (!xtal) 1943 brcms_b_xtal(wlc_hw, ON); 1944 1945 /* may need to take core out of reset first */ 1946 clk = wlc_hw->clk; 1947 if (!clk) { 1948 /* 1949 * mac no longer enables phyclk automatically when driver 1950 * accesses phyreg throughput mac. This can be skipped since 1951 * only mac reg is accessed below 1952 */ 1953 flags |= SICF_PCLKE; 1954 1955 /* 1956 * AI chip doesn't restore bar0win2 on 1957 * hibernation/resume, need sw fixup 1958 */ 1959 if ((ai_get_chip_id(wlc_hw->sih) == BCM43224_CHIP_ID) || 1960 (ai_get_chip_id(wlc_hw->sih) == BCM43225_CHIP_ID)) 1961 (void)ai_setcore(wlc_hw->sih, D11_CORE_ID, 0); 1962 1963 bcma_core_enable(wlc_hw->d11core, flags); 1964 brcms_c_mctrl_reset(wlc_hw); 1965 } 1966 1967 v = ((bcma_read32(wlc_hw->d11core, 1968 D11REGOFFS(phydebug)) & PDBG_RFD) != 0); 1969 1970 /* put core back into reset */ 1971 if (!clk) 1972 bcma_core_disable(wlc_hw->d11core, 0); 1973 1974 if (!xtal) 1975 brcms_b_xtal(wlc_hw, OFF); 1976 1977 return v; 1978} 1979 1980static bool wlc_dma_rxreset(struct brcms_hardware *wlc_hw, uint fifo) 1981{ 1982 struct dma_pub *di = wlc_hw->di[fifo]; 1983 return dma_rxreset(di); 1984} 1985 1986/* d11 core reset 1987 * ensure fask clock during reset 1988 * reset dma 1989 * reset d11(out of reset) 1990 * reset phy(out of reset) 1991 * clear software macintstatus for fresh new start 1992 * one testing hack wlc_hw->noreset will bypass the d11/phy reset 1993 */ 1994void brcms_b_corereset(struct brcms_hardware *wlc_hw, u32 flags) 1995{ 1996 uint i; 1997 bool fastclk; 1998 1999 if (flags == BRCMS_USE_COREFLAGS) 2000 flags = (wlc_hw->band->pi ? wlc_hw->band->core_flags : 0); 2001 2002 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit); 2003 2004 /* request FAST clock if not on */ 2005 fastclk = wlc_hw->forcefastclk; 2006 if (!fastclk) 2007 brcms_b_clkctl_clk(wlc_hw, CLK_FAST); 2008 2009 /* reset the dma engines except first time thru */ 2010 if (bcma_core_is_enabled(wlc_hw->d11core)) { 2011 for (i = 0; i < NFIFO; i++) 2012 if ((wlc_hw->di[i]) && (!dma_txreset(wlc_hw->di[i]))) 2013 wiphy_err(wlc_hw->wlc->wiphy, "wl%d: %s: " 2014 "dma_txreset[%d]: cannot stop dma\n", 2015 wlc_hw->unit, __func__, i); 2016 2017 if ((wlc_hw->di[RX_FIFO]) 2018 && (!wlc_dma_rxreset(wlc_hw, RX_FIFO))) 2019 wiphy_err(wlc_hw->wlc->wiphy, "wl%d: %s: dma_rxreset" 2020 "[%d]: cannot stop dma\n", 2021 wlc_hw->unit, __func__, RX_FIFO); 2022 } 2023 /* if noreset, just stop the psm and return */ 2024 if (wlc_hw->noreset) { 2025 wlc_hw->wlc->macintstatus = 0; /* skip wl_dpc after down */ 2026 brcms_b_mctrl(wlc_hw, MCTL_PSM_RUN | MCTL_EN_MAC, 0); 2027 return; 2028 } 2029 2030 /* 2031 * mac no longer enables phyclk automatically when driver accesses 2032 * phyreg throughput mac, AND phy_reset is skipped at early stage when 2033 * band->pi is invalid. need to enable PHY CLK 2034 */ 2035 flags |= SICF_PCLKE; 2036 2037 /* 2038 * reset the core 2039 * In chips with PMU, the fastclk request goes through d11 core 2040 * reg 0x1e0, which is cleared by the core_reset. have to re-request it. 2041 * 2042 * This adds some delay and we can optimize it by also requesting 2043 * fastclk through chipcommon during this period if necessary. But 2044 * that has to work coordinate with other driver like mips/arm since 2045 * they may touch chipcommon as well. 2046 */ 2047 wlc_hw->clk = false; 2048 bcma_core_enable(wlc_hw->d11core, flags); 2049 wlc_hw->clk = true; 2050 if (wlc_hw->band && wlc_hw->band->pi) 2051 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, true); 2052 2053 brcms_c_mctrl_reset(wlc_hw); 2054 2055 if (ai_get_cccaps(wlc_hw->sih) & CC_CAP_PMU) 2056 brcms_b_clkctl_clk(wlc_hw, CLK_FAST); 2057 2058 brcms_b_phy_reset(wlc_hw); 2059 2060 /* turn on PHY_PLL */ 2061 brcms_b_core_phypll_ctl(wlc_hw, true); 2062 2063 /* clear sw intstatus */ 2064 wlc_hw->wlc->macintstatus = 0; 2065 2066 /* restore the clk setting */ 2067 if (!fastclk) 2068 brcms_b_clkctl_clk(wlc_hw, CLK_DYNAMIC); 2069} 2070 2071/* txfifo sizes needs to be modified(increased) since the newer cores 2072 * have more memory. 2073 */ 2074static void brcms_b_corerev_fifofixup(struct brcms_hardware *wlc_hw) 2075{ 2076 struct bcma_device *core = wlc_hw->d11core; 2077 u16 fifo_nu; 2078 u16 txfifo_startblk = TXFIFO_START_BLK, txfifo_endblk; 2079 u16 txfifo_def, txfifo_def1; 2080 u16 txfifo_cmd; 2081 2082 /* tx fifos start at TXFIFO_START_BLK from the Base address */ 2083 txfifo_startblk = TXFIFO_START_BLK; 2084 2085 /* sequence of operations: reset fifo, set fifo size, reset fifo */ 2086 for (fifo_nu = 0; fifo_nu < NFIFO; fifo_nu++) { 2087 2088 txfifo_endblk = txfifo_startblk + wlc_hw->xmtfifo_sz[fifo_nu]; 2089 txfifo_def = (txfifo_startblk & 0xff) | 2090 (((txfifo_endblk - 1) & 0xff) << TXFIFO_FIFOTOP_SHIFT); 2091 txfifo_def1 = ((txfifo_startblk >> 8) & 0x1) | 2092 ((((txfifo_endblk - 2093 1) >> 8) & 0x1) << TXFIFO_FIFOTOP_SHIFT); 2094 txfifo_cmd = 2095 TXFIFOCMD_RESET_MASK | (fifo_nu << TXFIFOCMD_FIFOSEL_SHIFT); 2096 2097 bcma_write16(core, D11REGOFFS(xmtfifocmd), txfifo_cmd); 2098 bcma_write16(core, D11REGOFFS(xmtfifodef), txfifo_def); 2099 bcma_write16(core, D11REGOFFS(xmtfifodef1), txfifo_def1); 2100 2101 bcma_write16(core, D11REGOFFS(xmtfifocmd), txfifo_cmd); 2102 2103 txfifo_startblk += wlc_hw->xmtfifo_sz[fifo_nu]; 2104 } 2105 /* 2106 * need to propagate to shm location to be in sync since ucode/hw won't 2107 * do this 2108 */ 2109 brcms_b_write_shm(wlc_hw, M_FIFOSIZE0, 2110 wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]); 2111 brcms_b_write_shm(wlc_hw, M_FIFOSIZE1, 2112 wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]); 2113 brcms_b_write_shm(wlc_hw, M_FIFOSIZE2, 2114 ((wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO] << 8) | wlc_hw-> 2115 xmtfifo_sz[TX_AC_BK_FIFO])); 2116 brcms_b_write_shm(wlc_hw, M_FIFOSIZE3, 2117 ((wlc_hw->xmtfifo_sz[TX_ATIM_FIFO] << 8) | wlc_hw-> 2118 xmtfifo_sz[TX_BCMC_FIFO])); 2119} 2120 2121/* This function is used for changing the tsf frac register 2122 * If spur avoidance mode is off, the mac freq will be 80/120/160Mhz 2123 * If spur avoidance mode is on1, the mac freq will be 82/123/164Mhz 2124 * If spur avoidance mode is on2, the mac freq will be 84/126/168Mhz 2125 * HTPHY Formula is 2^26/freq(MHz) e.g. 2126 * For spuron2 - 126MHz -> 2^26/126 = 532610.0 2127 * - 532610 = 0x82082 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x2082 2128 * For spuron: 123MHz -> 2^26/123 = 545600.5 2129 * - 545601 = 0x85341 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x5341 2130 * For spur off: 120MHz -> 2^26/120 = 559240.5 2131 * - 559241 = 0x88889 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x8889 2132 */ 2133 2134void brcms_b_switch_macfreq(struct brcms_hardware *wlc_hw, u8 spurmode) 2135{ 2136 struct bcma_device *core = wlc_hw->d11core; 2137 2138 if ((ai_get_chip_id(wlc_hw->sih) == BCM43224_CHIP_ID) || 2139 (ai_get_chip_id(wlc_hw->sih) == BCM43225_CHIP_ID)) { 2140 if (spurmode == WL_SPURAVOID_ON2) { /* 126Mhz */ 2141 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x2082); 2142 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8); 2143 } else if (spurmode == WL_SPURAVOID_ON1) { /* 123Mhz */ 2144 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x5341); 2145 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8); 2146 } else { /* 120Mhz */ 2147 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x8889); 2148 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8); 2149 } 2150 } else if (BRCMS_ISLCNPHY(wlc_hw->band)) { 2151 if (spurmode == WL_SPURAVOID_ON1) { /* 82Mhz */ 2152 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x7CE0); 2153 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0xC); 2154 } else { /* 80Mhz */ 2155 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0xCCCD); 2156 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0xC); 2157 } 2158 } 2159} 2160 2161/* Initialize GPIOs that are controlled by D11 core */ 2162static void brcms_c_gpio_init(struct brcms_c_info *wlc) 2163{ 2164 struct brcms_hardware *wlc_hw = wlc->hw; 2165 u32 gc, gm; 2166 2167 /* use GPIO select 0 to get all gpio signals from the gpio out reg */ 2168 brcms_b_mctrl(wlc_hw, MCTL_GPOUT_SEL_MASK, 0); 2169 2170 /* 2171 * Common GPIO setup: 2172 * G0 = LED 0 = WLAN Activity 2173 * G1 = LED 1 = WLAN 2.4 GHz Radio State 2174 * G2 = LED 2 = WLAN 5 GHz Radio State 2175 * G4 = radio disable input (HI enabled, LO disabled) 2176 */ 2177 2178 gc = gm = 0; 2179 2180 /* Allocate GPIOs for mimo antenna diversity feature */ 2181 if (wlc_hw->antsel_type == ANTSEL_2x3) { 2182 /* Enable antenna diversity, use 2x3 mode */ 2183 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN, 2184 MHF3_ANTSEL_EN, BRCM_BAND_ALL); 2185 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE, 2186 MHF3_ANTSEL_MODE, BRCM_BAND_ALL); 2187 2188 /* init superswitch control */ 2189 wlc_phy_antsel_init(wlc_hw->band->pi, false); 2190 2191 } else if (wlc_hw->antsel_type == ANTSEL_2x4) { 2192 gm |= gc |= (BOARD_GPIO_12 | BOARD_GPIO_13); 2193 /* 2194 * The board itself is powered by these GPIOs 2195 * (when not sending pattern) so set them high 2196 */ 2197 bcma_set16(wlc_hw->d11core, D11REGOFFS(psm_gpio_oe), 2198 (BOARD_GPIO_12 | BOARD_GPIO_13)); 2199 bcma_set16(wlc_hw->d11core, D11REGOFFS(psm_gpio_out), 2200 (BOARD_GPIO_12 | BOARD_GPIO_13)); 2201 2202 /* Enable antenna diversity, use 2x4 mode */ 2203 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN, 2204 MHF3_ANTSEL_EN, BRCM_BAND_ALL); 2205 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE, 0, 2206 BRCM_BAND_ALL); 2207 2208 /* Configure the desired clock to be 4Mhz */ 2209 brcms_b_write_shm(wlc_hw, M_ANTSEL_CLKDIV, 2210 ANTSEL_CLKDIV_4MHZ); 2211 } 2212 2213 /* 2214 * gpio 9 controls the PA. ucode is responsible 2215 * for wiggling out and oe 2216 */ 2217 if (wlc_hw->boardflags & BFL_PACTRL) 2218 gm |= gc |= BOARD_GPIO_PACTRL; 2219 2220 /* apply to gpiocontrol register */ 2221 ai_gpiocontrol(wlc_hw->sih, gm, gc, GPIO_DRV_PRIORITY); 2222} 2223 2224static void brcms_ucode_write(struct brcms_hardware *wlc_hw, 2225 const __le32 ucode[], const size_t nbytes) 2226{ 2227 struct bcma_device *core = wlc_hw->d11core; 2228 uint i; 2229 uint count; 2230 2231 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit); 2232 2233 count = (nbytes / sizeof(u32)); 2234 2235 bcma_write32(core, D11REGOFFS(objaddr), 2236 OBJADDR_AUTO_INC | OBJADDR_UCM_SEL); 2237 (void)bcma_read32(core, D11REGOFFS(objaddr)); 2238 for (i = 0; i < count; i++) 2239 bcma_write32(core, D11REGOFFS(objdata), le32_to_cpu(ucode[i])); 2240 2241} 2242 2243static void brcms_ucode_download(struct brcms_hardware *wlc_hw) 2244{ 2245 struct brcms_c_info *wlc; 2246 struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode; 2247 2248 wlc = wlc_hw->wlc; 2249 2250 if (wlc_hw->ucode_loaded) 2251 return; 2252 2253 if (D11REV_IS(wlc_hw->corerev, 23)) { 2254 if (BRCMS_ISNPHY(wlc_hw->band)) { 2255 brcms_ucode_write(wlc_hw, ucode->bcm43xx_16_mimo, 2256 ucode->bcm43xx_16_mimosz); 2257 wlc_hw->ucode_loaded = true; 2258 } else 2259 wiphy_err(wlc->wiphy, "%s: wl%d: unsupported phy in " 2260 "corerev %d\n", 2261 __func__, wlc_hw->unit, wlc_hw->corerev); 2262 } else if (D11REV_IS(wlc_hw->corerev, 24)) { 2263 if (BRCMS_ISLCNPHY(wlc_hw->band)) { 2264 brcms_ucode_write(wlc_hw, ucode->bcm43xx_24_lcn, 2265 ucode->bcm43xx_24_lcnsz); 2266 wlc_hw->ucode_loaded = true; 2267 } else { 2268 wiphy_err(wlc->wiphy, "%s: wl%d: unsupported phy in " 2269 "corerev %d\n", 2270 __func__, wlc_hw->unit, wlc_hw->corerev); 2271 } 2272 } 2273} 2274 2275void brcms_b_txant_set(struct brcms_hardware *wlc_hw, u16 phytxant) 2276{ 2277 /* update sw state */ 2278 wlc_hw->bmac_phytxant = phytxant; 2279 2280 /* push to ucode if up */ 2281 if (!wlc_hw->up) 2282 return; 2283 brcms_c_ucode_txant_set(wlc_hw); 2284 2285} 2286 2287u16 brcms_b_get_txant(struct brcms_hardware *wlc_hw) 2288{ 2289 return (u16) wlc_hw->wlc->stf->txant; 2290} 2291 2292void brcms_b_antsel_type_set(struct brcms_hardware *wlc_hw, u8 antsel_type) 2293{ 2294 wlc_hw->antsel_type = antsel_type; 2295 2296 /* Update the antsel type for phy module to use */ 2297 wlc_phy_antsel_type_set(wlc_hw->band->pi, antsel_type); 2298} 2299 2300static void brcms_b_fifoerrors(struct brcms_hardware *wlc_hw) 2301{ 2302 bool fatal = false; 2303 uint unit; 2304 uint intstatus, idx; 2305 struct bcma_device *core = wlc_hw->d11core; 2306 struct wiphy *wiphy = wlc_hw->wlc->wiphy; 2307 2308 unit = wlc_hw->unit; 2309 2310 for (idx = 0; idx < NFIFO; idx++) { 2311 /* read intstatus register and ignore any non-error bits */ 2312 intstatus = 2313 bcma_read32(core, 2314 D11REGOFFS(intctrlregs[idx].intstatus)) & 2315 I_ERRORS; 2316 if (!intstatus) 2317 continue; 2318 2319 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: intstatus%d 0x%x\n", 2320 unit, idx, intstatus); 2321 2322 if (intstatus & I_RO) { 2323 wiphy_err(wiphy, "wl%d: fifo %d: receive fifo " 2324 "overflow\n", unit, idx); 2325 fatal = true; 2326 } 2327 2328 if (intstatus & I_PC) { 2329 wiphy_err(wiphy, "wl%d: fifo %d: descriptor error\n", 2330 unit, idx); 2331 fatal = true; 2332 } 2333 2334 if (intstatus & I_PD) { 2335 wiphy_err(wiphy, "wl%d: fifo %d: data error\n", unit, 2336 idx); 2337 fatal = true; 2338 } 2339 2340 if (intstatus & I_DE) { 2341 wiphy_err(wiphy, "wl%d: fifo %d: descriptor protocol " 2342 "error\n", unit, idx); 2343 fatal = true; 2344 } 2345 2346 if (intstatus & I_RU) 2347 wiphy_err(wiphy, "wl%d: fifo %d: receive descriptor " 2348 "underflow\n", idx, unit); 2349 2350 if (intstatus & I_XU) { 2351 wiphy_err(wiphy, "wl%d: fifo %d: transmit fifo " 2352 "underflow\n", idx, unit); 2353 fatal = true; 2354 } 2355 2356 if (fatal) { 2357 brcms_fatal_error(wlc_hw->wlc->wl); /* big hammer */ 2358 break; 2359 } else 2360 bcma_write32(core, 2361 D11REGOFFS(intctrlregs[idx].intstatus), 2362 intstatus); 2363 } 2364} 2365 2366void brcms_c_intrson(struct brcms_c_info *wlc) 2367{ 2368 struct brcms_hardware *wlc_hw = wlc->hw; 2369 wlc->macintmask = wlc->defmacintmask; 2370 bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), wlc->macintmask); 2371} 2372 2373u32 brcms_c_intrsoff(struct brcms_c_info *wlc) 2374{ 2375 struct brcms_hardware *wlc_hw = wlc->hw; 2376 u32 macintmask; 2377 2378 if (!wlc_hw->clk) 2379 return 0; 2380 2381 macintmask = wlc->macintmask; /* isr can still happen */ 2382 2383 bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), 0); 2384 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(macintmask)); 2385 udelay(1); /* ensure int line is no longer driven */ 2386 wlc->macintmask = 0; 2387 2388 /* return previous macintmask; resolve race between us and our isr */ 2389 return wlc->macintstatus ? 0 : macintmask; 2390} 2391 2392void brcms_c_intrsrestore(struct brcms_c_info *wlc, u32 macintmask) 2393{ 2394 struct brcms_hardware *wlc_hw = wlc->hw; 2395 if (!wlc_hw->clk) 2396 return; 2397 2398 wlc->macintmask = macintmask; 2399 bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), wlc->macintmask); 2400} 2401 2402/* assumes that the d11 MAC is enabled */ 2403static void brcms_b_tx_fifo_suspend(struct brcms_hardware *wlc_hw, 2404 uint tx_fifo) 2405{ 2406 u8 fifo = 1 << tx_fifo; 2407 2408 /* Two clients of this code, 11h Quiet period and scanning. */ 2409 2410 /* only suspend if not already suspended */ 2411 if ((wlc_hw->suspended_fifos & fifo) == fifo) 2412 return; 2413 2414 /* force the core awake only if not already */ 2415 if (wlc_hw->suspended_fifos == 0) 2416 brcms_c_ucode_wake_override_set(wlc_hw, 2417 BRCMS_WAKE_OVERRIDE_TXFIFO); 2418 2419 wlc_hw->suspended_fifos |= fifo; 2420 2421 if (wlc_hw->di[tx_fifo]) { 2422 /* 2423 * Suspending AMPDU transmissions in the middle can cause 2424 * underflow which may result in mismatch between ucode and 2425 * driver so suspend the mac before suspending the FIFO 2426 */ 2427 if (BRCMS_PHY_11N_CAP(wlc_hw->band)) 2428 brcms_c_suspend_mac_and_wait(wlc_hw->wlc); 2429 2430 dma_txsuspend(wlc_hw->di[tx_fifo]); 2431 2432 if (BRCMS_PHY_11N_CAP(wlc_hw->band)) 2433 brcms_c_enable_mac(wlc_hw->wlc); 2434 } 2435} 2436 2437static void brcms_b_tx_fifo_resume(struct brcms_hardware *wlc_hw, 2438 uint tx_fifo) 2439{ 2440 /* BMAC_NOTE: BRCMS_TX_FIFO_ENAB is done in brcms_c_dpc() for DMA case 2441 * but need to be done here for PIO otherwise the watchdog will catch 2442 * the inconsistency and fire 2443 */ 2444 /* Two clients of this code, 11h Quiet period and scanning. */ 2445 if (wlc_hw->di[tx_fifo]) 2446 dma_txresume(wlc_hw->di[tx_fifo]); 2447 2448 /* allow core to sleep again */ 2449 if (wlc_hw->suspended_fifos == 0) 2450 return; 2451 else { 2452 wlc_hw->suspended_fifos &= ~(1 << tx_fifo); 2453 if (wlc_hw->suspended_fifos == 0) 2454 brcms_c_ucode_wake_override_clear(wlc_hw, 2455 BRCMS_WAKE_OVERRIDE_TXFIFO); 2456 } 2457} 2458 2459/* precondition: requires the mac core to be enabled */ 2460static void brcms_b_mute(struct brcms_hardware *wlc_hw, bool mute_tx) 2461{ 2462 static const u8 null_ether_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0}; 2463 2464 if (mute_tx) { 2465 /* suspend tx fifos */ 2466 brcms_b_tx_fifo_suspend(wlc_hw, TX_DATA_FIFO); 2467 brcms_b_tx_fifo_suspend(wlc_hw, TX_CTL_FIFO); 2468 brcms_b_tx_fifo_suspend(wlc_hw, TX_AC_BK_FIFO); 2469 brcms_b_tx_fifo_suspend(wlc_hw, TX_AC_VI_FIFO); 2470 2471 /* zero the address match register so we do not send ACKs */ 2472 brcms_b_set_addrmatch(wlc_hw, RCM_MAC_OFFSET, 2473 null_ether_addr); 2474 } else { 2475 /* resume tx fifos */ 2476 brcms_b_tx_fifo_resume(wlc_hw, TX_DATA_FIFO); 2477 brcms_b_tx_fifo_resume(wlc_hw, TX_CTL_FIFO); 2478 brcms_b_tx_fifo_resume(wlc_hw, TX_AC_BK_FIFO); 2479 brcms_b_tx_fifo_resume(wlc_hw, TX_AC_VI_FIFO); 2480 2481 /* Restore address */ 2482 brcms_b_set_addrmatch(wlc_hw, RCM_MAC_OFFSET, 2483 wlc_hw->etheraddr); 2484 } 2485 2486 wlc_phy_mute_upd(wlc_hw->band->pi, mute_tx, 0); 2487 2488 if (mute_tx) 2489 brcms_c_ucode_mute_override_set(wlc_hw); 2490 else 2491 brcms_c_ucode_mute_override_clear(wlc_hw); 2492} 2493 2494void 2495brcms_c_mute(struct brcms_c_info *wlc, bool mute_tx) 2496{ 2497 brcms_b_mute(wlc->hw, mute_tx); 2498} 2499 2500/* 2501 * Read and clear macintmask and macintstatus and intstatus registers. 2502 * This routine should be called with interrupts off 2503 * Return: 2504 * -1 if brcms_deviceremoved(wlc) evaluates to true; 2505 * 0 if the interrupt is not for us, or we are in some special cases; 2506 * device interrupt status bits otherwise. 2507 */ 2508static inline u32 wlc_intstatus(struct brcms_c_info *wlc, bool in_isr) 2509{ 2510 struct brcms_hardware *wlc_hw = wlc->hw; 2511 struct bcma_device *core = wlc_hw->d11core; 2512 u32 macintstatus; 2513 2514 /* macintstatus includes a DMA interrupt summary bit */ 2515 macintstatus = bcma_read32(core, D11REGOFFS(macintstatus)); 2516 2517 BCMMSG(wlc->wiphy, "wl%d: macintstatus: 0x%x\n", wlc_hw->unit, 2518 macintstatus); 2519 2520 /* detect cardbus removed, in power down(suspend) and in reset */ 2521 if (brcms_deviceremoved(wlc)) 2522 return -1; 2523 2524 /* brcms_deviceremoved() succeeds even when the core is still resetting, 2525 * handle that case here. 2526 */ 2527 if (macintstatus == 0xffffffff) 2528 return 0; 2529 2530 /* defer unsolicited interrupts */ 2531 macintstatus &= (in_isr ? wlc->macintmask : wlc->defmacintmask); 2532 2533 /* if not for us */ 2534 if (macintstatus == 0) 2535 return 0; 2536 2537 /* interrupts are already turned off for CFE build 2538 * Caution: For CFE Turning off the interrupts again has some undesired 2539 * consequences 2540 */ 2541 /* turn off the interrupts */ 2542 bcma_write32(core, D11REGOFFS(macintmask), 0); 2543 (void)bcma_read32(core, D11REGOFFS(macintmask)); 2544 wlc->macintmask = 0; 2545 2546 /* clear device interrupts */ 2547 bcma_write32(core, D11REGOFFS(macintstatus), macintstatus); 2548 2549 /* MI_DMAINT is indication of non-zero intstatus */ 2550 if (macintstatus & MI_DMAINT) 2551 /* 2552 * only fifo interrupt enabled is I_RI in 2553 * RX_FIFO. If MI_DMAINT is set, assume it 2554 * is set and clear the interrupt. 2555 */ 2556 bcma_write32(core, D11REGOFFS(intctrlregs[RX_FIFO].intstatus), 2557 DEF_RXINTMASK); 2558 2559 return macintstatus; 2560} 2561 2562/* Update wlc->macintstatus and wlc->intstatus[]. */ 2563/* Return true if they are updated successfully. false otherwise */ 2564bool brcms_c_intrsupd(struct brcms_c_info *wlc) 2565{ 2566 u32 macintstatus; 2567 2568 /* read and clear macintstatus and intstatus registers */ 2569 macintstatus = wlc_intstatus(wlc, false); 2570 2571 /* device is removed */ 2572 if (macintstatus == 0xffffffff) 2573 return false; 2574 2575 /* update interrupt status in software */ 2576 wlc->macintstatus |= macintstatus; 2577 2578 return true; 2579} 2580 2581/* 2582 * First-level interrupt processing. 2583 * Return true if this was our interrupt, false otherwise. 2584 * *wantdpc will be set to true if further brcms_c_dpc() processing is required, 2585 * false otherwise. 2586 */ 2587bool brcms_c_isr(struct brcms_c_info *wlc, bool *wantdpc) 2588{ 2589 struct brcms_hardware *wlc_hw = wlc->hw; 2590 u32 macintstatus; 2591 2592 *wantdpc = false; 2593 2594 if (!wlc_hw->up || !wlc->macintmask) 2595 return false; 2596 2597 /* read and clear macintstatus and intstatus registers */ 2598 macintstatus = wlc_intstatus(wlc, true); 2599 2600 if (macintstatus == 0xffffffff) 2601 wiphy_err(wlc->wiphy, "DEVICEREMOVED detected in the ISR code" 2602 " path\n"); 2603 2604 /* it is not for us */ 2605 if (macintstatus == 0) 2606 return false; 2607 2608 *wantdpc = true; 2609 2610 /* save interrupt status bits */ 2611 wlc->macintstatus = macintstatus; 2612 2613 return true; 2614 2615} 2616 2617void brcms_c_suspend_mac_and_wait(struct brcms_c_info *wlc) 2618{ 2619 struct brcms_hardware *wlc_hw = wlc->hw; 2620 struct bcma_device *core = wlc_hw->d11core; 2621 u32 mc, mi; 2622 struct wiphy *wiphy = wlc->wiphy; 2623 2624 BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit, 2625 wlc_hw->band->bandunit); 2626 2627 /* 2628 * Track overlapping suspend requests 2629 */ 2630 wlc_hw->mac_suspend_depth++; 2631 if (wlc_hw->mac_suspend_depth > 1) 2632 return; 2633 2634 /* force the core awake */ 2635 brcms_c_ucode_wake_override_set(wlc_hw, BRCMS_WAKE_OVERRIDE_MACSUSPEND); 2636 2637 mc = bcma_read32(core, D11REGOFFS(maccontrol)); 2638 2639 if (mc == 0xffffffff) { 2640 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit, 2641 __func__); 2642 brcms_down(wlc->wl); 2643 return; 2644 } 2645 WARN_ON(mc & MCTL_PSM_JMP_0); 2646 WARN_ON(!(mc & MCTL_PSM_RUN)); 2647 WARN_ON(!(mc & MCTL_EN_MAC)); 2648 2649 mi = bcma_read32(core, D11REGOFFS(macintstatus)); 2650 if (mi == 0xffffffff) { 2651 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit, 2652 __func__); 2653 brcms_down(wlc->wl); 2654 return; 2655 } 2656 WARN_ON(mi & MI_MACSSPNDD); 2657 2658 brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, 0); 2659 2660 SPINWAIT(!(bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD), 2661 BRCMS_MAX_MAC_SUSPEND); 2662 2663 if (!(bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD)) { 2664 wiphy_err(wiphy, "wl%d: wlc_suspend_mac_and_wait: waited %d uS" 2665 " and MI_MACSSPNDD is still not on.\n", 2666 wlc_hw->unit, BRCMS_MAX_MAC_SUSPEND); 2667 wiphy_err(wiphy, "wl%d: psmdebug 0x%08x, phydebug 0x%08x, " 2668 "psm_brc 0x%04x\n", wlc_hw->unit, 2669 bcma_read32(core, D11REGOFFS(psmdebug)), 2670 bcma_read32(core, D11REGOFFS(phydebug)), 2671 bcma_read16(core, D11REGOFFS(psm_brc))); 2672 } 2673 2674 mc = bcma_read32(core, D11REGOFFS(maccontrol)); 2675 if (mc == 0xffffffff) { 2676 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit, 2677 __func__); 2678 brcms_down(wlc->wl); 2679 return; 2680 } 2681 WARN_ON(mc & MCTL_PSM_JMP_0); 2682 WARN_ON(!(mc & MCTL_PSM_RUN)); 2683 WARN_ON(mc & MCTL_EN_MAC); 2684} 2685 2686void brcms_c_enable_mac(struct brcms_c_info *wlc) 2687{ 2688 struct brcms_hardware *wlc_hw = wlc->hw; 2689 struct bcma_device *core = wlc_hw->d11core; 2690 u32 mc, mi; 2691 2692 BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit, 2693 wlc->band->bandunit); 2694 2695 /* 2696 * Track overlapping suspend requests 2697 */ 2698 wlc_hw->mac_suspend_depth--; 2699 if (wlc_hw->mac_suspend_depth > 0) 2700 return; 2701 2702 mc = bcma_read32(core, D11REGOFFS(maccontrol)); 2703 WARN_ON(mc & MCTL_PSM_JMP_0); 2704 WARN_ON(mc & MCTL_EN_MAC); 2705 WARN_ON(!(mc & MCTL_PSM_RUN)); 2706 2707 brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, MCTL_EN_MAC); 2708 bcma_write32(core, D11REGOFFS(macintstatus), MI_MACSSPNDD); 2709 2710 mc = bcma_read32(core, D11REGOFFS(maccontrol)); 2711 WARN_ON(mc & MCTL_PSM_JMP_0); 2712 WARN_ON(!(mc & MCTL_EN_MAC)); 2713 WARN_ON(!(mc & MCTL_PSM_RUN)); 2714 2715 mi = bcma_read32(core, D11REGOFFS(macintstatus)); 2716 WARN_ON(mi & MI_MACSSPNDD); 2717 2718 brcms_c_ucode_wake_override_clear(wlc_hw, 2719 BRCMS_WAKE_OVERRIDE_MACSUSPEND); 2720} 2721 2722void brcms_b_band_stf_ss_set(struct brcms_hardware *wlc_hw, u8 stf_mode) 2723{ 2724 wlc_hw->hw_stf_ss_opmode = stf_mode; 2725 2726 if (wlc_hw->clk) 2727 brcms_upd_ofdm_pctl1_table(wlc_hw); 2728} 2729 2730static bool brcms_b_validate_chip_access(struct brcms_hardware *wlc_hw) 2731{ 2732 struct bcma_device *core = wlc_hw->d11core; 2733 u32 w, val; 2734 struct wiphy *wiphy = wlc_hw->wlc->wiphy; 2735 2736 BCMMSG(wiphy, "wl%d\n", wlc_hw->unit); 2737 2738 /* Validate dchip register access */ 2739 2740 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0); 2741 (void)bcma_read32(core, D11REGOFFS(objaddr)); 2742 w = bcma_read32(core, D11REGOFFS(objdata)); 2743 2744 /* Can we write and read back a 32bit register? */ 2745 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0); 2746 (void)bcma_read32(core, D11REGOFFS(objaddr)); 2747 bcma_write32(core, D11REGOFFS(objdata), (u32) 0xaa5555aa); 2748 2749 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0); 2750 (void)bcma_read32(core, D11REGOFFS(objaddr)); 2751 val = bcma_read32(core, D11REGOFFS(objdata)); 2752 if (val != (u32) 0xaa5555aa) { 2753 wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, " 2754 "expected 0xaa5555aa\n", wlc_hw->unit, val); 2755 return false; 2756 } 2757 2758 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0); 2759 (void)bcma_read32(core, D11REGOFFS(objaddr)); 2760 bcma_write32(core, D11REGOFFS(objdata), (u32) 0x55aaaa55); 2761 2762 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0); 2763 (void)bcma_read32(core, D11REGOFFS(objaddr)); 2764 val = bcma_read32(core, D11REGOFFS(objdata)); 2765 if (val != (u32) 0x55aaaa55) { 2766 wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, " 2767 "expected 0x55aaaa55\n", wlc_hw->unit, val); 2768 return false; 2769 } 2770 2771 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0); 2772 (void)bcma_read32(core, D11REGOFFS(objaddr)); 2773 bcma_write32(core, D11REGOFFS(objdata), w); 2774 2775 /* clear CFPStart */ 2776 bcma_write32(core, D11REGOFFS(tsf_cfpstart), 0); 2777 2778 w = bcma_read32(core, D11REGOFFS(maccontrol)); 2779 if ((w != (MCTL_IHR_EN | MCTL_WAKE)) && 2780 (w != (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE))) { 2781 wiphy_err(wiphy, "wl%d: validate_chip_access: maccontrol = " 2782 "0x%x, expected 0x%x or 0x%x\n", wlc_hw->unit, w, 2783 (MCTL_IHR_EN | MCTL_WAKE), 2784 (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE)); 2785 return false; 2786 } 2787 2788 return true; 2789} 2790 2791#define PHYPLL_WAIT_US 100000 2792 2793void brcms_b_core_phypll_ctl(struct brcms_hardware *wlc_hw, bool on) 2794{ 2795 struct bcma_device *core = wlc_hw->d11core; 2796 u32 tmp; 2797 2798 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit); 2799 2800 tmp = 0; 2801 2802 if (on) { 2803 if ((ai_get_chip_id(wlc_hw->sih) == BCM4313_CHIP_ID)) { 2804 bcma_set32(core, D11REGOFFS(clk_ctl_st), 2805 CCS_ERSRC_REQ_HT | 2806 CCS_ERSRC_REQ_D11PLL | 2807 CCS_ERSRC_REQ_PHYPLL); 2808 SPINWAIT((bcma_read32(core, D11REGOFFS(clk_ctl_st)) & 2809 CCS_ERSRC_AVAIL_HT) != CCS_ERSRC_AVAIL_HT, 2810 PHYPLL_WAIT_US); 2811 2812 tmp = bcma_read32(core, D11REGOFFS(clk_ctl_st)); 2813 if ((tmp & CCS_ERSRC_AVAIL_HT) != CCS_ERSRC_AVAIL_HT) 2814 wiphy_err(wlc_hw->wlc->wiphy, "%s: turn on PHY" 2815 " PLL failed\n", __func__); 2816 } else { 2817 bcma_set32(core, D11REGOFFS(clk_ctl_st), 2818 tmp | CCS_ERSRC_REQ_D11PLL | 2819 CCS_ERSRC_REQ_PHYPLL); 2820 SPINWAIT((bcma_read32(core, D11REGOFFS(clk_ctl_st)) & 2821 (CCS_ERSRC_AVAIL_D11PLL | 2822 CCS_ERSRC_AVAIL_PHYPLL)) != 2823 (CCS_ERSRC_AVAIL_D11PLL | 2824 CCS_ERSRC_AVAIL_PHYPLL), PHYPLL_WAIT_US); 2825 2826 tmp = bcma_read32(core, D11REGOFFS(clk_ctl_st)); 2827 if ((tmp & 2828 (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL)) 2829 != 2830 (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL)) 2831 wiphy_err(wlc_hw->wlc->wiphy, "%s: turn on " 2832 "PHY PLL failed\n", __func__); 2833 } 2834 } else { 2835 /* 2836 * Since the PLL may be shared, other cores can still 2837 * be requesting it; so we'll deassert the request but 2838 * not wait for status to comply. 2839 */ 2840 bcma_mask32(core, D11REGOFFS(clk_ctl_st), 2841 ~CCS_ERSRC_REQ_PHYPLL); 2842 (void)bcma_read32(core, D11REGOFFS(clk_ctl_st)); 2843 } 2844} 2845 2846static void brcms_c_coredisable(struct brcms_hardware *wlc_hw) 2847{ 2848 bool dev_gone; 2849 2850 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit); 2851 2852 dev_gone = brcms_deviceremoved(wlc_hw->wlc); 2853 2854 if (dev_gone) 2855 return; 2856 2857 if (wlc_hw->noreset) 2858 return; 2859 2860 /* radio off */ 2861 wlc_phy_switch_radio(wlc_hw->band->pi, OFF); 2862 2863 /* turn off analog core */ 2864 wlc_phy_anacore(wlc_hw->band->pi, OFF); 2865 2866 /* turn off PHYPLL to save power */ 2867 brcms_b_core_phypll_ctl(wlc_hw, false); 2868 2869 wlc_hw->clk = false; 2870 bcma_core_disable(wlc_hw->d11core, 0); 2871 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false); 2872} 2873 2874static void brcms_c_flushqueues(struct brcms_c_info *wlc) 2875{ 2876 struct brcms_hardware *wlc_hw = wlc->hw; 2877 uint i; 2878 2879 /* free any posted tx packets */ 2880 for (i = 0; i < NFIFO; i++) 2881 if (wlc_hw->di[i]) { 2882 dma_txreclaim(wlc_hw->di[i], DMA_RANGE_ALL); 2883 wlc->core->txpktpend[i] = 0; 2884 BCMMSG(wlc->wiphy, "pktpend fifo %d clrd\n", i); 2885 } 2886 2887 /* free any posted rx packets */ 2888 dma_rxreclaim(wlc_hw->di[RX_FIFO]); 2889} 2890 2891static u16 2892brcms_b_read_objmem(struct brcms_hardware *wlc_hw, uint offset, u32 sel) 2893{ 2894 struct bcma_device *core = wlc_hw->d11core; 2895 u16 objoff = D11REGOFFS(objdata); 2896 2897 bcma_write32(core, D11REGOFFS(objaddr), sel | (offset >> 2)); 2898 (void)bcma_read32(core, D11REGOFFS(objaddr)); 2899 if (offset & 2) 2900 objoff += 2; 2901 2902 return bcma_read16(core, objoff); 2903; 2904} 2905 2906static void 2907brcms_b_write_objmem(struct brcms_hardware *wlc_hw, uint offset, u16 v, 2908 u32 sel) 2909{ 2910 struct bcma_device *core = wlc_hw->d11core; 2911 u16 objoff = D11REGOFFS(objdata); 2912 2913 bcma_write32(core, D11REGOFFS(objaddr), sel | (offset >> 2)); 2914 (void)bcma_read32(core, D11REGOFFS(objaddr)); 2915 if (offset & 2) 2916 objoff += 2; 2917 2918 bcma_write16(core, objoff, v); 2919} 2920 2921/* 2922 * Read a single u16 from shared memory. 2923 * SHM 'offset' needs to be an even address 2924 */ 2925u16 brcms_b_read_shm(struct brcms_hardware *wlc_hw, uint offset) 2926{ 2927 return brcms_b_read_objmem(wlc_hw, offset, OBJADDR_SHM_SEL); 2928} 2929 2930/* 2931 * Write a single u16 to shared memory. 2932 * SHM 'offset' needs to be an even address 2933 */ 2934void brcms_b_write_shm(struct brcms_hardware *wlc_hw, uint offset, u16 v) 2935{ 2936 brcms_b_write_objmem(wlc_hw, offset, v, OBJADDR_SHM_SEL); 2937} 2938 2939/* 2940 * Copy a buffer to shared memory of specified type . 2941 * SHM 'offset' needs to be an even address and 2942 * Buffer length 'len' must be an even number of bytes 2943 * 'sel' selects the type of memory 2944 */ 2945void 2946brcms_b_copyto_objmem(struct brcms_hardware *wlc_hw, uint offset, 2947 const void *buf, int len, u32 sel) 2948{ 2949 u16 v; 2950 const u8 *p = (const u8 *)buf; 2951 int i; 2952 2953 if (len <= 0 || (offset & 1) || (len & 1)) 2954 return; 2955 2956 for (i = 0; i < len; i += 2) { 2957 v = p[i] | (p[i + 1] << 8); 2958 brcms_b_write_objmem(wlc_hw, offset + i, v, sel); 2959 } 2960} 2961 2962/* 2963 * Copy a piece of shared memory of specified type to a buffer . 2964 * SHM 'offset' needs to be an even address and 2965 * Buffer length 'len' must be an even number of bytes 2966 * 'sel' selects the type of memory 2967 */ 2968void 2969brcms_b_copyfrom_objmem(struct brcms_hardware *wlc_hw, uint offset, void *buf, 2970 int len, u32 sel) 2971{ 2972 u16 v; 2973 u8 *p = (u8 *) buf; 2974 int i; 2975 2976 if (len <= 0 || (offset & 1) || (len & 1)) 2977 return; 2978 2979 for (i = 0; i < len; i += 2) { 2980 v = brcms_b_read_objmem(wlc_hw, offset + i, sel); 2981 p[i] = v & 0xFF; 2982 p[i + 1] = (v >> 8) & 0xFF; 2983 } 2984} 2985 2986/* Copy a buffer to shared memory. 2987 * SHM 'offset' needs to be an even address and 2988 * Buffer length 'len' must be an even number of bytes 2989 */ 2990static void brcms_c_copyto_shm(struct brcms_c_info *wlc, uint offset, 2991 const void *buf, int len) 2992{ 2993 brcms_b_copyto_objmem(wlc->hw, offset, buf, len, OBJADDR_SHM_SEL); 2994} 2995 2996static void brcms_b_retrylimit_upd(struct brcms_hardware *wlc_hw, 2997 u16 SRL, u16 LRL) 2998{ 2999 wlc_hw->SRL = SRL; 3000 wlc_hw->LRL = LRL; 3001 3002 /* write retry limit to SCR, shouldn't need to suspend */ 3003 if (wlc_hw->up) { 3004 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr), 3005 OBJADDR_SCR_SEL | S_DOT11_SRC_LMT); 3006 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr)); 3007 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), wlc_hw->SRL); 3008 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr), 3009 OBJADDR_SCR_SEL | S_DOT11_LRC_LMT); 3010 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr)); 3011 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), wlc_hw->LRL); 3012 } 3013} 3014 3015static void brcms_b_pllreq(struct brcms_hardware *wlc_hw, bool set, u32 req_bit) 3016{ 3017 if (set) { 3018 if (mboolisset(wlc_hw->pllreq, req_bit)) 3019 return; 3020 3021 mboolset(wlc_hw->pllreq, req_bit); 3022 3023 if (mboolisset(wlc_hw->pllreq, BRCMS_PLLREQ_FLIP)) { 3024 if (!wlc_hw->sbclk) 3025 brcms_b_xtal(wlc_hw, ON); 3026 } 3027 } else { 3028 if (!mboolisset(wlc_hw->pllreq, req_bit)) 3029 return; 3030 3031 mboolclr(wlc_hw->pllreq, req_bit); 3032 3033 if (mboolisset(wlc_hw->pllreq, BRCMS_PLLREQ_FLIP)) { 3034 if (wlc_hw->sbclk) 3035 brcms_b_xtal(wlc_hw, OFF); 3036 } 3037 } 3038} 3039 3040static void brcms_b_antsel_set(struct brcms_hardware *wlc_hw, u32 antsel_avail) 3041{ 3042 wlc_hw->antsel_avail = antsel_avail; 3043} 3044 3045/* 3046 * conditions under which the PM bit should be set in outgoing frames 3047 * and STAY_AWAKE is meaningful 3048 */ 3049static bool brcms_c_ps_allowed(struct brcms_c_info *wlc) 3050{ 3051 struct brcms_bss_cfg *cfg = wlc->bsscfg; 3052 3053 /* disallow PS when one of the following global conditions meets */ 3054 if (!wlc->pub->associated) 3055 return false; 3056 3057 /* disallow PS when one of these meets when not scanning */ 3058 if (wlc->filter_flags & FIF_PROMISC_IN_BSS) 3059 return false; 3060 3061 if (cfg->associated) { 3062 /* 3063 * disallow PS when one of the following 3064 * bsscfg specific conditions meets 3065 */ 3066 if (!cfg->BSS) 3067 return false; 3068 3069 return false; 3070 } 3071 3072 return true; 3073} 3074 3075static void brcms_c_statsupd(struct brcms_c_info *wlc) 3076{ 3077 int i; 3078 struct macstat macstats; 3079#ifdef BCMDBG 3080 u16 delta; 3081 u16 rxf0ovfl; 3082 u16 txfunfl[NFIFO]; 3083#endif /* BCMDBG */ 3084 3085 /* if driver down, make no sense to update stats */ 3086 if (!wlc->pub->up) 3087 return; 3088 3089#ifdef BCMDBG 3090 /* save last rx fifo 0 overflow count */ 3091 rxf0ovfl = wlc->core->macstat_snapshot->rxf0ovfl; 3092 3093 /* save last tx fifo underflow count */ 3094 for (i = 0; i < NFIFO; i++) 3095 txfunfl[i] = wlc->core->macstat_snapshot->txfunfl[i]; 3096#endif /* BCMDBG */ 3097 3098 /* Read mac stats from contiguous shared memory */ 3099 brcms_b_copyfrom_objmem(wlc->hw, M_UCODE_MACSTAT, &macstats, 3100 sizeof(struct macstat), OBJADDR_SHM_SEL); 3101 3102#ifdef BCMDBG 3103 /* check for rx fifo 0 overflow */ 3104 delta = (u16) (wlc->core->macstat_snapshot->rxf0ovfl - rxf0ovfl); 3105 if (delta) 3106 wiphy_err(wlc->wiphy, "wl%d: %u rx fifo 0 overflows!\n", 3107 wlc->pub->unit, delta); 3108 3109 /* check for tx fifo underflows */ 3110 for (i = 0; i < NFIFO; i++) { 3111 delta = 3112 (u16) (wlc->core->macstat_snapshot->txfunfl[i] - 3113 txfunfl[i]); 3114 if (delta) 3115 wiphy_err(wlc->wiphy, "wl%d: %u tx fifo %d underflows!" 3116 "\n", wlc->pub->unit, delta, i); 3117 } 3118#endif /* BCMDBG */ 3119 3120 /* merge counters from dma module */ 3121 for (i = 0; i < NFIFO; i++) { 3122 if (wlc->hw->di[i]) 3123 dma_counterreset(wlc->hw->di[i]); 3124 } 3125} 3126 3127static void brcms_b_reset(struct brcms_hardware *wlc_hw) 3128{ 3129 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit); 3130 3131 /* reset the core */ 3132 if (!brcms_deviceremoved(wlc_hw->wlc)) 3133 brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS); 3134 3135 /* purge the dma rings */ 3136 brcms_c_flushqueues(wlc_hw->wlc); 3137} 3138 3139void brcms_c_reset(struct brcms_c_info *wlc) 3140{ 3141 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit); 3142 3143 /* slurp up hw mac counters before core reset */ 3144 brcms_c_statsupd(wlc); 3145 3146 /* reset our snapshot of macstat counters */ 3147 memset((char *)wlc->core->macstat_snapshot, 0, 3148 sizeof(struct macstat)); 3149 3150 brcms_b_reset(wlc->hw); 3151} 3152 3153/* Return the channel the driver should initialize during brcms_c_init. 3154 * the channel may have to be changed from the currently configured channel 3155 * if other configurations are in conflict (bandlocked, 11n mode disabled, 3156 * invalid channel for current country, etc.) 3157 */ 3158static u16 brcms_c_init_chanspec(struct brcms_c_info *wlc) 3159{ 3160 u16 chanspec = 3161 1 | WL_CHANSPEC_BW_20 | WL_CHANSPEC_CTL_SB_NONE | 3162 WL_CHANSPEC_BAND_2G; 3163 3164 return chanspec; 3165} 3166 3167void brcms_c_init_scb(struct scb *scb) 3168{ 3169 int i; 3170 3171 memset(scb, 0, sizeof(struct scb)); 3172 scb->flags = SCB_WMECAP | SCB_HTCAP; 3173 for (i = 0; i < NUMPRIO; i++) { 3174 scb->seqnum[i] = 0; 3175 scb->seqctl[i] = 0xFFFF; 3176 } 3177 3178 scb->seqctl_nonqos = 0xFFFF; 3179 scb->magic = SCB_MAGIC; 3180} 3181 3182/* d11 core init 3183 * reset PSM 3184 * download ucode/PCM 3185 * let ucode run to suspended 3186 * download ucode inits 3187 * config other core registers 3188 * init dma 3189 */ 3190static void brcms_b_coreinit(struct brcms_c_info *wlc) 3191{ 3192 struct brcms_hardware *wlc_hw = wlc->hw; 3193 struct bcma_device *core = wlc_hw->d11core; 3194 u32 sflags; 3195 u32 bcnint_us; 3196 uint i = 0; 3197 bool fifosz_fixup = false; 3198 int err = 0; 3199 u16 buf[NFIFO]; 3200 struct wiphy *wiphy = wlc->wiphy; 3201 struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode; 3202 3203 BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit); 3204 3205 /* reset PSM */ 3206 brcms_b_mctrl(wlc_hw, ~0, (MCTL_IHR_EN | MCTL_PSM_JMP_0 | MCTL_WAKE)); 3207 3208 brcms_ucode_download(wlc_hw); 3209 /* 3210 * FIFOSZ fixup. driver wants to controls the fifo allocation. 3211 */ 3212 fifosz_fixup = true; 3213 3214 /* let the PSM run to the suspended state, set mode to BSS STA */ 3215 bcma_write32(core, D11REGOFFS(macintstatus), -1); 3216 brcms_b_mctrl(wlc_hw, ~0, 3217 (MCTL_IHR_EN | MCTL_INFRA | MCTL_PSM_RUN | MCTL_WAKE)); 3218 3219 /* wait for ucode to self-suspend after auto-init */ 3220 SPINWAIT(((bcma_read32(core, D11REGOFFS(macintstatus)) & 3221 MI_MACSSPNDD) == 0), 1000 * 1000); 3222 if ((bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD) == 0) 3223 wiphy_err(wiphy, "wl%d: wlc_coreinit: ucode did not self-" 3224 "suspend!\n", wlc_hw->unit); 3225 3226 brcms_c_gpio_init(wlc); 3227 3228 sflags = bcma_aread32(core, BCMA_IOST); 3229 3230 if (D11REV_IS(wlc_hw->corerev, 23)) { 3231 if (BRCMS_ISNPHY(wlc_hw->band)) 3232 brcms_c_write_inits(wlc_hw, ucode->d11n0initvals16); 3233 else 3234 wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev" 3235 " %d\n", __func__, wlc_hw->unit, 3236 wlc_hw->corerev); 3237 } else if (D11REV_IS(wlc_hw->corerev, 24)) { 3238 if (BRCMS_ISLCNPHY(wlc_hw->band)) 3239 brcms_c_write_inits(wlc_hw, ucode->d11lcn0initvals24); 3240 else 3241 wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev" 3242 " %d\n", __func__, wlc_hw->unit, 3243 wlc_hw->corerev); 3244 } else { 3245 wiphy_err(wiphy, "%s: wl%d: unsupported corerev %d\n", 3246 __func__, wlc_hw->unit, wlc_hw->corerev); 3247 } 3248 3249 /* For old ucode, txfifo sizes needs to be modified(increased) */ 3250 if (fifosz_fixup == true) 3251 brcms_b_corerev_fifofixup(wlc_hw); 3252 3253 /* check txfifo allocations match between ucode and driver */ 3254 buf[TX_AC_BE_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE0); 3255 if (buf[TX_AC_BE_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]) { 3256 i = TX_AC_BE_FIFO; 3257 err = -1; 3258 } 3259 buf[TX_AC_VI_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE1); 3260 if (buf[TX_AC_VI_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]) { 3261 i = TX_AC_VI_FIFO; 3262 err = -1; 3263 } 3264 buf[TX_AC_BK_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE2); 3265 buf[TX_AC_VO_FIFO] = (buf[TX_AC_BK_FIFO] >> 8) & 0xff; 3266 buf[TX_AC_BK_FIFO] &= 0xff; 3267 if (buf[TX_AC_BK_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BK_FIFO]) { 3268 i = TX_AC_BK_FIFO; 3269 err = -1; 3270 } 3271 if (buf[TX_AC_VO_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO]) { 3272 i = TX_AC_VO_FIFO; 3273 err = -1; 3274 } 3275 buf[TX_BCMC_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE3); 3276 buf[TX_ATIM_FIFO] = (buf[TX_BCMC_FIFO] >> 8) & 0xff; 3277 buf[TX_BCMC_FIFO] &= 0xff; 3278 if (buf[TX_BCMC_FIFO] != wlc_hw->xmtfifo_sz[TX_BCMC_FIFO]) { 3279 i = TX_BCMC_FIFO; 3280 err = -1; 3281 } 3282 if (buf[TX_ATIM_FIFO] != wlc_hw->xmtfifo_sz[TX_ATIM_FIFO]) { 3283 i = TX_ATIM_FIFO; 3284 err = -1; 3285 } 3286 if (err != 0) 3287 wiphy_err(wiphy, "wlc_coreinit: txfifo mismatch: ucode size %d" 3288 " driver size %d index %d\n", buf[i], 3289 wlc_hw->xmtfifo_sz[i], i); 3290 3291 /* make sure we can still talk to the mac */ 3292 WARN_ON(bcma_read32(core, D11REGOFFS(maccontrol)) == 0xffffffff); 3293 3294 /* band-specific inits done by wlc_bsinit() */ 3295 3296 /* Set up frame burst size and antenna swap threshold init values */ 3297 brcms_b_write_shm(wlc_hw, M_MBURST_SIZE, MAXTXFRAMEBURST); 3298 brcms_b_write_shm(wlc_hw, M_MAX_ANTCNT, ANTCNT); 3299 3300 /* enable one rx interrupt per received frame */ 3301 bcma_write32(core, D11REGOFFS(intrcvlazy[0]), (1 << IRL_FC_SHIFT)); 3302 3303 /* set the station mode (BSS STA) */ 3304 brcms_b_mctrl(wlc_hw, 3305 (MCTL_INFRA | MCTL_DISCARD_PMQ | MCTL_AP), 3306 (MCTL_INFRA | MCTL_DISCARD_PMQ)); 3307 3308 /* set up Beacon interval */ 3309 bcnint_us = 0x8000 << 10; 3310 bcma_write32(core, D11REGOFFS(tsf_cfprep), 3311 (bcnint_us << CFPREP_CBI_SHIFT)); 3312 bcma_write32(core, D11REGOFFS(tsf_cfpstart), bcnint_us); 3313 bcma_write32(core, D11REGOFFS(macintstatus), MI_GP1); 3314 3315 /* write interrupt mask */ 3316 bcma_write32(core, D11REGOFFS(intctrlregs[RX_FIFO].intmask), 3317 DEF_RXINTMASK); 3318 3319 /* allow the MAC to control the PHY clock (dynamic on/off) */ 3320 brcms_b_macphyclk_set(wlc_hw, ON); 3321 3322 /* program dynamic clock control fast powerup delay register */ 3323 wlc->fastpwrup_dly = ai_clkctl_fast_pwrup_delay(wlc_hw->sih); 3324 bcma_write16(core, D11REGOFFS(scc_fastpwrup_dly), wlc->fastpwrup_dly); 3325 3326 /* tell the ucode the corerev */ 3327 brcms_b_write_shm(wlc_hw, M_MACHW_VER, (u16) wlc_hw->corerev); 3328 3329 /* tell the ucode MAC capabilities */ 3330 brcms_b_write_shm(wlc_hw, M_MACHW_CAP_L, 3331 (u16) (wlc_hw->machwcap & 0xffff)); 3332 brcms_b_write_shm(wlc_hw, M_MACHW_CAP_H, 3333 (u16) ((wlc_hw-> 3334 machwcap >> 16) & 0xffff)); 3335 3336 /* write retry limits to SCR, this done after PSM init */ 3337 bcma_write32(core, D11REGOFFS(objaddr), 3338 OBJADDR_SCR_SEL | S_DOT11_SRC_LMT); 3339 (void)bcma_read32(core, D11REGOFFS(objaddr)); 3340 bcma_write32(core, D11REGOFFS(objdata), wlc_hw->SRL); 3341 bcma_write32(core, D11REGOFFS(objaddr), 3342 OBJADDR_SCR_SEL | S_DOT11_LRC_LMT); 3343 (void)bcma_read32(core, D11REGOFFS(objaddr)); 3344 bcma_write32(core, D11REGOFFS(objdata), wlc_hw->LRL); 3345 3346 /* write rate fallback retry limits */ 3347 brcms_b_write_shm(wlc_hw, M_SFRMTXCNTFBRTHSD, wlc_hw->SFBL); 3348 brcms_b_write_shm(wlc_hw, M_LFRMTXCNTFBRTHSD, wlc_hw->LFBL); 3349 3350 bcma_mask16(core, D11REGOFFS(ifs_ctl), 0x0FFF); 3351 bcma_write16(core, D11REGOFFS(ifs_aifsn), EDCF_AIFSN_MIN); 3352 3353 /* init the tx dma engines */ 3354 for (i = 0; i < NFIFO; i++) { 3355 if (wlc_hw->di[i]) 3356 dma_txinit(wlc_hw->di[i]); 3357 } 3358 3359 /* init the rx dma engine(s) and post receive buffers */ 3360 dma_rxinit(wlc_hw->di[RX_FIFO]); 3361 dma_rxfill(wlc_hw->di[RX_FIFO]); 3362} 3363 3364void 3365static brcms_b_init(struct brcms_hardware *wlc_hw, u16 chanspec) { 3366 u32 macintmask; 3367 bool fastclk; 3368 struct brcms_c_info *wlc = wlc_hw->wlc; 3369 3370 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit); 3371 3372 /* request FAST clock if not on */ 3373 fastclk = wlc_hw->forcefastclk; 3374 if (!fastclk) 3375 brcms_b_clkctl_clk(wlc_hw, CLK_FAST); 3376 3377 /* disable interrupts */ 3378 macintmask = brcms_intrsoff(wlc->wl); 3379 3380 /* set up the specified band and chanspec */ 3381 brcms_c_setxband(wlc_hw, chspec_bandunit(chanspec)); 3382 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec); 3383 3384 /* do one-time phy inits and calibration */ 3385 wlc_phy_cal_init(wlc_hw->band->pi); 3386 3387 /* core-specific initialization */ 3388 brcms_b_coreinit(wlc); 3389 3390 /* band-specific inits */ 3391 brcms_b_bsinit(wlc, chanspec); 3392 3393 /* restore macintmask */ 3394 brcms_intrsrestore(wlc->wl, macintmask); 3395 3396 /* seed wake_override with BRCMS_WAKE_OVERRIDE_MACSUSPEND since the mac 3397 * is suspended and brcms_c_enable_mac() will clear this override bit. 3398 */ 3399 mboolset(wlc_hw->wake_override, BRCMS_WAKE_OVERRIDE_MACSUSPEND); 3400 3401 /* 3402 * initialize mac_suspend_depth to 1 to match ucode 3403 * initial suspended state 3404 */ 3405 wlc_hw->mac_suspend_depth = 1; 3406 3407 /* restore the clk */ 3408 if (!fastclk) 3409 brcms_b_clkctl_clk(wlc_hw, CLK_DYNAMIC); 3410} 3411 3412static void brcms_c_set_phy_chanspec(struct brcms_c_info *wlc, 3413 u16 chanspec) 3414{ 3415 /* Save our copy of the chanspec */ 3416 wlc->chanspec = chanspec; 3417 3418 /* Set the chanspec and power limits for this locale */ 3419 brcms_c_channel_set_chanspec(wlc->cmi, chanspec, BRCMS_TXPWR_MAX); 3420 3421 if (wlc->stf->ss_algosel_auto) 3422 brcms_c_stf_ss_algo_channel_get(wlc, &wlc->stf->ss_algo_channel, 3423 chanspec); 3424 3425 brcms_c_stf_ss_update(wlc, wlc->band); 3426} 3427 3428static void 3429brcms_default_rateset(struct brcms_c_info *wlc, struct brcms_c_rateset *rs) 3430{ 3431 brcms_c_rateset_default(rs, NULL, wlc->band->phytype, 3432 wlc->band->bandtype, false, BRCMS_RATE_MASK_FULL, 3433 (bool) (wlc->pub->_n_enab & SUPPORT_11N), 3434 brcms_chspec_bw(wlc->default_bss->chanspec), 3435 wlc->stf->txstreams); 3436} 3437 3438/* derive wlc->band->basic_rate[] table from 'rateset' */ 3439static void brcms_c_rate_lookup_init(struct brcms_c_info *wlc, 3440 struct brcms_c_rateset *rateset) 3441{ 3442 u8 rate; 3443 u8 mandatory; 3444 u8 cck_basic = 0; 3445 u8 ofdm_basic = 0; 3446 u8 *br = wlc->band->basic_rate; 3447 uint i; 3448 3449 /* incoming rates are in 500kbps units as in 802.11 Supported Rates */ 3450 memset(br, 0, BRCM_MAXRATE + 1); 3451 3452 /* For each basic rate in the rates list, make an entry in the 3453 * best basic lookup. 3454 */ 3455 for (i = 0; i < rateset->count; i++) { 3456 /* only make an entry for a basic rate */ 3457 if (!(rateset->rates[i] & BRCMS_RATE_FLAG)) 3458 continue; 3459 3460 /* mask off basic bit */ 3461 rate = (rateset->rates[i] & BRCMS_RATE_MASK); 3462 3463 if (rate > BRCM_MAXRATE) { 3464 wiphy_err(wlc->wiphy, "brcms_c_rate_lookup_init: " 3465 "invalid rate 0x%X in rate set\n", 3466 rateset->rates[i]); 3467 continue; 3468 } 3469 3470 br[rate] = rate; 3471 } 3472 3473 /* The rate lookup table now has non-zero entries for each 3474 * basic rate, equal to the basic rate: br[basicN] = basicN 3475 * 3476 * To look up the best basic rate corresponding to any 3477 * particular rate, code can use the basic_rate table 3478 * like this 3479 * 3480 * basic_rate = wlc->band->basic_rate[tx_rate] 3481 * 3482 * Make sure there is a best basic rate entry for 3483 * every rate by walking up the table from low rates 3484 * to high, filling in holes in the lookup table 3485 */ 3486 3487 for (i = 0; i < wlc->band->hw_rateset.count; i++) { 3488 rate = wlc->band->hw_rateset.rates[i]; 3489 3490 if (br[rate] != 0) { 3491 /* This rate is a basic rate. 3492 * Keep track of the best basic rate so far by 3493 * modulation type. 3494 */ 3495 if (is_ofdm_rate(rate)) 3496 ofdm_basic = rate; 3497 else 3498 cck_basic = rate; 3499 3500 continue; 3501 } 3502 3503 /* This rate is not a basic rate so figure out the 3504 * best basic rate less than this rate and fill in 3505 * the hole in the table 3506 */ 3507 3508 br[rate] = is_ofdm_rate(rate) ? ofdm_basic : cck_basic; 3509 3510 if (br[rate] != 0) 3511 continue; 3512 3513 if (is_ofdm_rate(rate)) { 3514 /* 3515 * In 11g and 11a, the OFDM mandatory rates 3516 * are 6, 12, and 24 Mbps 3517 */ 3518 if (rate >= BRCM_RATE_24M) 3519 mandatory = BRCM_RATE_24M; 3520 else if (rate >= BRCM_RATE_12M) 3521 mandatory = BRCM_RATE_12M; 3522 else 3523 mandatory = BRCM_RATE_6M; 3524 } else { 3525 /* In 11b, all CCK rates are mandatory 1 - 11 Mbps */ 3526 mandatory = rate; 3527 } 3528 3529 br[rate] = mandatory; 3530 } 3531} 3532 3533static void brcms_c_bandinit_ordered(struct brcms_c_info *wlc, 3534 u16 chanspec) 3535{ 3536 struct brcms_c_rateset default_rateset; 3537 uint parkband; 3538 uint i, band_order[2]; 3539 3540 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit); 3541 /* 3542 * We might have been bandlocked during down and the chip 3543 * power-cycled (hibernate). Figure out the right band to park on 3544 */ 3545 if (wlc->bandlocked || wlc->pub->_nbands == 1) { 3546 /* updated in brcms_c_bandlock() */ 3547 parkband = wlc->band->bandunit; 3548 band_order[0] = band_order[1] = parkband; 3549 } else { 3550 /* park on the band of the specified chanspec */ 3551 parkband = chspec_bandunit(chanspec); 3552 3553 /* order so that parkband initialize last */ 3554 band_order[0] = parkband ^ 1; 3555 band_order[1] = parkband; 3556 } 3557 3558 /* make each band operational, software state init */ 3559 for (i = 0; i < wlc->pub->_nbands; i++) { 3560 uint j = band_order[i]; 3561 3562 wlc->band = wlc->bandstate[j]; 3563 3564 brcms_default_rateset(wlc, &default_rateset); 3565 3566 /* fill in hw_rate */ 3567 brcms_c_rateset_filter(&default_rateset, &wlc->band->hw_rateset, 3568 false, BRCMS_RATES_CCK_OFDM, BRCMS_RATE_MASK, 3569 (bool) (wlc->pub->_n_enab & SUPPORT_11N)); 3570 3571 /* init basic rate lookup */ 3572 brcms_c_rate_lookup_init(wlc, &default_rateset); 3573 } 3574 3575 /* sync up phy/radio chanspec */ 3576 brcms_c_set_phy_chanspec(wlc, chanspec); 3577} 3578 3579/* 3580 * Set or clear filtering related maccontrol bits based on 3581 * specified filter flags 3582 */ 3583void brcms_c_mac_promisc(struct brcms_c_info *wlc, uint filter_flags) 3584{ 3585 u32 promisc_bits = 0; 3586 3587 wlc->filter_flags = filter_flags; 3588 3589 if (filter_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) 3590 promisc_bits |= MCTL_PROMISC; 3591 3592 if (filter_flags & FIF_BCN_PRBRESP_PROMISC) 3593 promisc_bits |= MCTL_BCNS_PROMISC; 3594 3595 if (filter_flags & FIF_FCSFAIL) 3596 promisc_bits |= MCTL_KEEPBADFCS; 3597 3598 if (filter_flags & (FIF_CONTROL | FIF_PSPOLL)) 3599 promisc_bits |= MCTL_KEEPCONTROL; 3600 3601 brcms_b_mctrl(wlc->hw, 3602 MCTL_PROMISC | MCTL_BCNS_PROMISC | 3603 MCTL_KEEPCONTROL | MCTL_KEEPBADFCS, 3604 promisc_bits); 3605} 3606 3607/* 3608 * ucode, hwmac update 3609 * Channel dependent updates for ucode and hw 3610 */ 3611static void brcms_c_ucode_mac_upd(struct brcms_c_info *wlc) 3612{ 3613 /* enable or disable any active IBSSs depending on whether or not 3614 * we are on the home channel 3615 */ 3616 if (wlc->home_chanspec == wlc_phy_chanspec_get(wlc->band->pi)) { 3617 if (wlc->pub->associated) { 3618 /* 3619 * BMAC_NOTE: This is something that should be fixed 3620 * in ucode inits. I think that the ucode inits set 3621 * up the bcn templates and shm values with a bogus 3622 * beacon. This should not be done in the inits. If 3623 * ucode needs to set up a beacon for testing, the 3624 * test routines should write it down, not expect the 3625 * inits to populate a bogus beacon. 3626 */ 3627 if (BRCMS_PHY_11N_CAP(wlc->band)) 3628 brcms_b_write_shm(wlc->hw, 3629 M_BCN_TXTSF_OFFSET, 0); 3630 } 3631 } else { 3632 /* disable an active IBSS if we are not on the home channel */ 3633 } 3634} 3635 3636static void brcms_c_write_rate_shm(struct brcms_c_info *wlc, u8 rate, 3637 u8 basic_rate) 3638{ 3639 u8 phy_rate, index; 3640 u8 basic_phy_rate, basic_index; 3641 u16 dir_table, basic_table; 3642 u16 basic_ptr; 3643 3644 /* Shared memory address for the table we are reading */ 3645 dir_table = is_ofdm_rate(basic_rate) ? M_RT_DIRMAP_A : M_RT_DIRMAP_B; 3646 3647 /* Shared memory address for the table we are writing */ 3648 basic_table = is_ofdm_rate(rate) ? M_RT_BBRSMAP_A : M_RT_BBRSMAP_B; 3649 3650 /* 3651 * for a given rate, the LS-nibble of the PLCP SIGNAL field is 3652 * the index into the rate table. 3653 */ 3654 phy_rate = rate_info[rate] & BRCMS_RATE_MASK; 3655 basic_phy_rate = rate_info[basic_rate] & BRCMS_RATE_MASK; 3656 index = phy_rate & 0xf; 3657 basic_index = basic_phy_rate & 0xf; 3658 3659 /* Find the SHM pointer to the ACK rate entry by looking in the 3660 * Direct-map Table 3661 */ 3662 basic_ptr = brcms_b_read_shm(wlc->hw, (dir_table + basic_index * 2)); 3663 3664 /* Update the SHM BSS-basic-rate-set mapping table with the pointer 3665 * to the correct basic rate for the given incoming rate 3666 */ 3667 brcms_b_write_shm(wlc->hw, (basic_table + index * 2), basic_ptr); 3668} 3669 3670static const struct brcms_c_rateset * 3671brcms_c_rateset_get_hwrs(struct brcms_c_info *wlc) 3672{ 3673 const struct brcms_c_rateset *rs_dflt; 3674 3675 if (BRCMS_PHY_11N_CAP(wlc->band)) { 3676 if (wlc->band->bandtype == BRCM_BAND_5G) 3677 rs_dflt = &ofdm_mimo_rates; 3678 else 3679 rs_dflt = &cck_ofdm_mimo_rates; 3680 } else if (wlc->band->gmode) 3681 rs_dflt = &cck_ofdm_rates; 3682 else 3683 rs_dflt = &cck_rates; 3684 3685 return rs_dflt; 3686} 3687 3688static void brcms_c_set_ratetable(struct brcms_c_info *wlc) 3689{ 3690 const struct brcms_c_rateset *rs_dflt; 3691 struct brcms_c_rateset rs; 3692 u8 rate, basic_rate; 3693 uint i; 3694 3695 rs_dflt = brcms_c_rateset_get_hwrs(wlc); 3696 3697 brcms_c_rateset_copy(rs_dflt, &rs); 3698 brcms_c_rateset_mcs_upd(&rs, wlc->stf->txstreams); 3699 3700 /* walk the phy rate table and update SHM basic rate lookup table */ 3701 for (i = 0; i < rs.count; i++) { 3702 rate = rs.rates[i] & BRCMS_RATE_MASK; 3703 3704 /* for a given rate brcms_basic_rate returns the rate at 3705 * which a response ACK/CTS should be sent. 3706 */ 3707 basic_rate = brcms_basic_rate(wlc, rate); 3708 if (basic_rate == 0) 3709 /* This should only happen if we are using a 3710 * restricted rateset. 3711 */ 3712 basic_rate = rs.rates[0] & BRCMS_RATE_MASK; 3713 3714 brcms_c_write_rate_shm(wlc, rate, basic_rate); 3715 } 3716} 3717 3718/* band-specific init */ 3719static void brcms_c_bsinit(struct brcms_c_info *wlc) 3720{ 3721 BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", 3722 wlc->pub->unit, wlc->band->bandunit); 3723 3724 /* write ucode ACK/CTS rate table */ 3725 brcms_c_set_ratetable(wlc); 3726 3727 /* update some band specific mac configuration */ 3728 brcms_c_ucode_mac_upd(wlc); 3729 3730 /* init antenna selection */ 3731 brcms_c_antsel_init(wlc->asi); 3732 3733} 3734 3735/* formula: IDLE_BUSY_RATIO_X_16 = (100-duty_cycle)/duty_cycle*16 */ 3736static int 3737brcms_c_duty_cycle_set(struct brcms_c_info *wlc, int duty_cycle, bool isOFDM, 3738 bool writeToShm) 3739{ 3740 int idle_busy_ratio_x_16 = 0; 3741 uint offset = 3742 isOFDM ? M_TX_IDLE_BUSY_RATIO_X_16_OFDM : 3743 M_TX_IDLE_BUSY_RATIO_X_16_CCK; 3744 if (duty_cycle > 100 || duty_cycle < 0) { 3745 wiphy_err(wlc->wiphy, "wl%d: duty cycle value off limit\n", 3746 wlc->pub->unit); 3747 return -EINVAL; 3748 } 3749 if (duty_cycle) 3750 idle_busy_ratio_x_16 = (100 - duty_cycle) * 16 / duty_cycle; 3751 /* Only write to shared memory when wl is up */ 3752 if (writeToShm) 3753 brcms_b_write_shm(wlc->hw, offset, (u16) idle_busy_ratio_x_16); 3754 3755 if (isOFDM) 3756 wlc->tx_duty_cycle_ofdm = (u16) duty_cycle; 3757 else 3758 wlc->tx_duty_cycle_cck = (u16) duty_cycle; 3759 3760 return 0; 3761} 3762 3763/* 3764 * Initialize the base precedence map for dequeueing 3765 * from txq based on WME settings 3766 */ 3767static void brcms_c_tx_prec_map_init(struct brcms_c_info *wlc) 3768{ 3769 wlc->tx_prec_map = BRCMS_PREC_BMP_ALL; 3770 memset(wlc->fifo2prec_map, 0, NFIFO * sizeof(u16)); 3771 3772 wlc->fifo2prec_map[TX_AC_BK_FIFO] = BRCMS_PREC_BMP_AC_BK; 3773 wlc->fifo2prec_map[TX_AC_BE_FIFO] = BRCMS_PREC_BMP_AC_BE; 3774 wlc->fifo2prec_map[TX_AC_VI_FIFO] = BRCMS_PREC_BMP_AC_VI; 3775 wlc->fifo2prec_map[TX_AC_VO_FIFO] = BRCMS_PREC_BMP_AC_VO; 3776} 3777 3778static void 3779brcms_c_txflowcontrol_signal(struct brcms_c_info *wlc, 3780 struct brcms_txq_info *qi, bool on, int prio) 3781{ 3782 /* transmit flowcontrol is not yet implemented */ 3783} 3784 3785static void brcms_c_txflowcontrol_reset(struct brcms_c_info *wlc) 3786{ 3787 struct brcms_txq_info *qi; 3788 3789 for (qi = wlc->tx_queues; qi != NULL; qi = qi->next) { 3790 if (qi->stopped) { 3791 brcms_c_txflowcontrol_signal(wlc, qi, OFF, ALLPRIO); 3792 qi->stopped = 0; 3793 } 3794 } 3795} 3796 3797/* push sw hps and wake state through hardware */ 3798static void brcms_c_set_ps_ctrl(struct brcms_c_info *wlc) 3799{ 3800 u32 v1, v2; 3801 bool hps; 3802 bool awake_before; 3803 3804 hps = brcms_c_ps_allowed(wlc); 3805 3806 BCMMSG(wlc->wiphy, "wl%d: hps %d\n", wlc->pub->unit, hps); 3807 3808 v1 = bcma_read32(wlc->hw->d11core, D11REGOFFS(maccontrol)); 3809 v2 = MCTL_WAKE; 3810 if (hps) 3811 v2 |= MCTL_HPS; 3812 3813 brcms_b_mctrl(wlc->hw, MCTL_WAKE | MCTL_HPS, v2); 3814 3815 awake_before = ((v1 & MCTL_WAKE) || ((v1 & MCTL_HPS) == 0)); 3816 3817 if (!awake_before) 3818 brcms_b_wait_for_wake(wlc->hw); 3819} 3820 3821/* 3822 * Write this BSS config's MAC address to core. 3823 * Updates RXE match engine. 3824 */ 3825static int brcms_c_set_mac(struct brcms_bss_cfg *bsscfg) 3826{ 3827 int err = 0; 3828 struct brcms_c_info *wlc = bsscfg->wlc; 3829 3830 /* enter the MAC addr into the RXE match registers */ 3831 brcms_c_set_addrmatch(wlc, RCM_MAC_OFFSET, bsscfg->cur_etheraddr); 3832 3833 brcms_c_ampdu_macaddr_upd(wlc); 3834 3835 return err; 3836} 3837 3838/* Write the BSS config's BSSID address to core (set_bssid in d11procs.tcl). 3839 * Updates RXE match engine. 3840 */ 3841static void brcms_c_set_bssid(struct brcms_bss_cfg *bsscfg) 3842{ 3843 /* we need to update BSSID in RXE match registers */ 3844 brcms_c_set_addrmatch(bsscfg->wlc, RCM_BSSID_OFFSET, bsscfg->BSSID); 3845} 3846 3847static void brcms_b_set_shortslot(struct brcms_hardware *wlc_hw, bool shortslot) 3848{ 3849 wlc_hw->shortslot = shortslot; 3850 3851 if (wlc_hw->band->bandtype == BRCM_BAND_2G && wlc_hw->up) { 3852 brcms_c_suspend_mac_and_wait(wlc_hw->wlc); 3853 brcms_b_update_slot_timing(wlc_hw, shortslot); 3854 brcms_c_enable_mac(wlc_hw->wlc); 3855 } 3856} 3857 3858/* 3859 * Suspend the the MAC and update the slot timing 3860 * for standard 11b/g (20us slots) or shortslot 11g (9us slots). 3861 */ 3862static void brcms_c_switch_shortslot(struct brcms_c_info *wlc, bool shortslot) 3863{ 3864 /* use the override if it is set */ 3865 if (wlc->shortslot_override != BRCMS_SHORTSLOT_AUTO) 3866 shortslot = (wlc->shortslot_override == BRCMS_SHORTSLOT_ON); 3867 3868 if (wlc->shortslot == shortslot) 3869 return; 3870 3871 wlc->shortslot = shortslot; 3872 3873 brcms_b_set_shortslot(wlc->hw, shortslot); 3874} 3875 3876static void brcms_c_set_home_chanspec(struct brcms_c_info *wlc, u16 chanspec) 3877{ 3878 if (wlc->home_chanspec != chanspec) { 3879 wlc->home_chanspec = chanspec; 3880 3881 if (wlc->bsscfg->associated) 3882 wlc->bsscfg->current_bss->chanspec = chanspec; 3883 } 3884} 3885 3886void 3887brcms_b_set_chanspec(struct brcms_hardware *wlc_hw, u16 chanspec, 3888 bool mute_tx, struct txpwr_limits *txpwr) 3889{ 3890 uint bandunit; 3891 3892 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: 0x%x\n", wlc_hw->unit, chanspec); 3893 3894 wlc_hw->chanspec = chanspec; 3895 3896 /* Switch bands if necessary */ 3897 if (wlc_hw->_nbands > 1) { 3898 bandunit = chspec_bandunit(chanspec); 3899 if (wlc_hw->band->bandunit != bandunit) { 3900 /* brcms_b_setband disables other bandunit, 3901 * use light band switch if not up yet 3902 */ 3903 if (wlc_hw->up) { 3904 wlc_phy_chanspec_radio_set(wlc_hw-> 3905 bandstate[bandunit]-> 3906 pi, chanspec); 3907 brcms_b_setband(wlc_hw, bandunit, chanspec); 3908 } else { 3909 brcms_c_setxband(wlc_hw, bandunit); 3910 } 3911 } 3912 } 3913 3914 wlc_phy_initcal_enable(wlc_hw->band->pi, !mute_tx); 3915 3916 if (!wlc_hw->up) { 3917 if (wlc_hw->clk) 3918 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr, 3919 chanspec); 3920 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec); 3921 } else { 3922 wlc_phy_chanspec_set(wlc_hw->band->pi, chanspec); 3923 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr, chanspec); 3924 3925 /* Update muting of the channel */ 3926 brcms_b_mute(wlc_hw, mute_tx); 3927 } 3928} 3929 3930/* switch to and initialize new band */ 3931static void brcms_c_setband(struct brcms_c_info *wlc, 3932 uint bandunit) 3933{ 3934 wlc->band = wlc->bandstate[bandunit]; 3935 3936 if (!wlc->pub->up) 3937 return; 3938 3939 /* wait for at least one beacon before entering sleeping state */ 3940 brcms_c_set_ps_ctrl(wlc); 3941 3942 /* band-specific initializations */ 3943 brcms_c_bsinit(wlc); 3944} 3945 3946static void brcms_c_set_chanspec(struct brcms_c_info *wlc, u16 chanspec) 3947{ 3948 uint bandunit; 3949 bool switchband = false; 3950 u16 old_chanspec = wlc->chanspec; 3951 3952 if (!brcms_c_valid_chanspec_db(wlc->cmi, chanspec)) { 3953 wiphy_err(wlc->wiphy, "wl%d: %s: Bad channel %d\n", 3954 wlc->pub->unit, __func__, CHSPEC_CHANNEL(chanspec)); 3955 return; 3956 } 3957 3958 /* Switch bands if necessary */ 3959 if (wlc->pub->_nbands > 1) { 3960 bandunit = chspec_bandunit(chanspec); 3961 if (wlc->band->bandunit != bandunit || wlc->bandinit_pending) { 3962 switchband = true; 3963 if (wlc->bandlocked) { 3964 wiphy_err(wlc->wiphy, "wl%d: %s: chspec %d " 3965 "band is locked!\n", 3966 wlc->pub->unit, __func__, 3967 CHSPEC_CHANNEL(chanspec)); 3968 return; 3969 } 3970 /* 3971 * should the setband call come after the 3972 * brcms_b_chanspec() ? if the setband updates 3973 * (brcms_c_bsinit) use low level calls to inspect and 3974 * set state, the state inspected may be from the wrong 3975 * band, or the following brcms_b_set_chanspec() may 3976 * undo the work. 3977 */ 3978 brcms_c_setband(wlc, bandunit); 3979 } 3980 } 3981 3982 /* sync up phy/radio chanspec */ 3983 brcms_c_set_phy_chanspec(wlc, chanspec); 3984 3985 /* init antenna selection */ 3986 if (brcms_chspec_bw(old_chanspec) != brcms_chspec_bw(chanspec)) { 3987 brcms_c_antsel_init(wlc->asi); 3988 3989 /* Fix the hardware rateset based on bw. 3990 * Mainly add MCS32 for 40Mhz, remove MCS 32 for 20Mhz 3991 */ 3992 brcms_c_rateset_bw_mcs_filter(&wlc->band->hw_rateset, 3993 wlc->band->mimo_cap_40 ? brcms_chspec_bw(chanspec) : 0); 3994 } 3995 3996 /* update some mac configuration since chanspec changed */ 3997 brcms_c_ucode_mac_upd(wlc); 3998} 3999 4000/* 4001 * This function changes the phytxctl for beacon based on current 4002 * beacon ratespec AND txant setting as per this table: 4003 * ratespec CCK ant = wlc->stf->txant 4004 * OFDM ant = 3 4005 */ 4006void brcms_c_beacon_phytxctl_txant_upd(struct brcms_c_info *wlc, 4007 u32 bcn_rspec) 4008{ 4009 u16 phyctl; 4010 u16 phytxant = wlc->stf->phytxant; 4011 u16 mask = PHY_TXC_ANT_MASK; 4012 4013 /* for non-siso rates or default setting, use the available chains */ 4014 if (BRCMS_PHY_11N_CAP(wlc->band)) 4015 phytxant = brcms_c_stf_phytxchain_sel(wlc, bcn_rspec); 4016 4017 phyctl = brcms_b_read_shm(wlc->hw, M_BCN_PCTLWD); 4018 phyctl = (phyctl & ~mask) | phytxant; 4019 brcms_b_write_shm(wlc->hw, M_BCN_PCTLWD, phyctl); 4020} 4021 4022/* 4023 * centralized protection config change function to simplify debugging, no 4024 * consistency checking this should be called only on changes to avoid overhead 4025 * in periodic function 4026 */ 4027void brcms_c_protection_upd(struct brcms_c_info *wlc, uint idx, int val) 4028{ 4029 BCMMSG(wlc->wiphy, "idx %d, val %d\n", idx, val); 4030 4031 switch (idx) { 4032 case BRCMS_PROT_G_SPEC: 4033 wlc->protection->_g = (bool) val; 4034 break; 4035 case BRCMS_PROT_G_OVR: 4036 wlc->protection->g_override = (s8) val; 4037 break; 4038 case BRCMS_PROT_G_USER: 4039 wlc->protection->gmode_user = (u8) val; 4040 break; 4041 case BRCMS_PROT_OVERLAP: 4042 wlc->protection->overlap = (s8) val; 4043 break; 4044 case BRCMS_PROT_N_USER: 4045 wlc->protection->nmode_user = (s8) val; 4046 break; 4047 case BRCMS_PROT_N_CFG: 4048 wlc->protection->n_cfg = (s8) val; 4049 break; 4050 case BRCMS_PROT_N_CFG_OVR: 4051 wlc->protection->n_cfg_override = (s8) val; 4052 break; 4053 case BRCMS_PROT_N_NONGF: 4054 wlc->protection->nongf = (bool) val; 4055 break; 4056 case BRCMS_PROT_N_NONGF_OVR: 4057 wlc->protection->nongf_override = (s8) val; 4058 break; 4059 case BRCMS_PROT_N_PAM_OVR: 4060 wlc->protection->n_pam_override = (s8) val; 4061 break; 4062 case BRCMS_PROT_N_OBSS: 4063 wlc->protection->n_obss = (bool) val; 4064 break; 4065 4066 default: 4067 break; 4068 } 4069 4070} 4071 4072static void brcms_c_ht_update_sgi_rx(struct brcms_c_info *wlc, int val) 4073{ 4074 if (wlc->pub->up) { 4075 brcms_c_update_beacon(wlc); 4076 brcms_c_update_probe_resp(wlc, true); 4077 } 4078} 4079 4080static void brcms_c_ht_update_ldpc(struct brcms_c_info *wlc, s8 val) 4081{ 4082 wlc->stf->ldpc = val; 4083 4084 if (wlc->pub->up) { 4085 brcms_c_update_beacon(wlc); 4086 brcms_c_update_probe_resp(wlc, true); 4087 wlc_phy_ldpc_override_set(wlc->band->pi, (val ? true : false)); 4088 } 4089} 4090 4091void brcms_c_wme_setparams(struct brcms_c_info *wlc, u16 aci, 4092 const struct ieee80211_tx_queue_params *params, 4093 bool suspend) 4094{ 4095 int i; 4096 struct shm_acparams acp_shm; 4097 u16 *shm_entry; 4098 4099 /* Only apply params if the core is out of reset and has clocks */ 4100 if (!wlc->clk) { 4101 wiphy_err(wlc->wiphy, "wl%d: %s : no-clock\n", wlc->pub->unit, 4102 __func__); 4103 return; 4104 } 4105 4106 memset((char *)&acp_shm, 0, sizeof(struct shm_acparams)); 4107 /* fill in shm ac params struct */ 4108 acp_shm.txop = params->txop; 4109 /* convert from units of 32us to us for ucode */ 4110 wlc->edcf_txop[aci & 0x3] = acp_shm.txop = 4111 EDCF_TXOP2USEC(acp_shm.txop); 4112 acp_shm.aifs = (params->aifs & EDCF_AIFSN_MASK); 4113 4114 if (aci == IEEE80211_AC_VI && acp_shm.txop == 0 4115 && acp_shm.aifs < EDCF_AIFSN_MAX) 4116 acp_shm.aifs++; 4117 4118 if (acp_shm.aifs < EDCF_AIFSN_MIN 4119 || acp_shm.aifs > EDCF_AIFSN_MAX) { 4120 wiphy_err(wlc->wiphy, "wl%d: edcf_setparams: bad " 4121 "aifs %d\n", wlc->pub->unit, acp_shm.aifs); 4122 } else { 4123 acp_shm.cwmin = params->cw_min; 4124 acp_shm.cwmax = params->cw_max; 4125 acp_shm.cwcur = acp_shm.cwmin; 4126 acp_shm.bslots = 4127 bcma_read16(wlc->hw->d11core, D11REGOFFS(tsf_random)) & 4128 acp_shm.cwcur; 4129 acp_shm.reggap = acp_shm.bslots + acp_shm.aifs; 4130 /* Indicate the new params to the ucode */ 4131 acp_shm.status = brcms_b_read_shm(wlc->hw, (M_EDCF_QINFO + 4132 wme_ac2fifo[aci] * 4133 M_EDCF_QLEN + 4134 M_EDCF_STATUS_OFF)); 4135 acp_shm.status |= WME_STATUS_NEWAC; 4136 4137 /* Fill in shm acparam table */ 4138 shm_entry = (u16 *) &acp_shm; 4139 for (i = 0; i < (int)sizeof(struct shm_acparams); i += 2) 4140 brcms_b_write_shm(wlc->hw, 4141 M_EDCF_QINFO + 4142 wme_ac2fifo[aci] * M_EDCF_QLEN + i, 4143 *shm_entry++); 4144 } 4145 4146 if (suspend) { 4147 brcms_c_suspend_mac_and_wait(wlc); 4148 brcms_c_enable_mac(wlc); 4149 } 4150} 4151 4152static void brcms_c_edcf_setparams(struct brcms_c_info *wlc, bool suspend) 4153{ 4154 u16 aci; 4155 int i_ac; 4156 struct ieee80211_tx_queue_params txq_pars; 4157 static const struct edcf_acparam default_edcf_acparams[] = { 4158 {EDCF_AC_BE_ACI_STA, EDCF_AC_BE_ECW_STA, EDCF_AC_BE_TXOP_STA}, 4159 {EDCF_AC_BK_ACI_STA, EDCF_AC_BK_ECW_STA, EDCF_AC_BK_TXOP_STA}, 4160 {EDCF_AC_VI_ACI_STA, EDCF_AC_VI_ECW_STA, EDCF_AC_VI_TXOP_STA}, 4161 {EDCF_AC_VO_ACI_STA, EDCF_AC_VO_ECW_STA, EDCF_AC_VO_TXOP_STA} 4162 }; /* ucode needs these parameters during its initialization */ 4163 const struct edcf_acparam *edcf_acp = &default_edcf_acparams[0]; 4164 4165 for (i_ac = 0; i_ac < IEEE80211_NUM_ACS; i_ac++, edcf_acp++) { 4166 /* find out which ac this set of params applies to */ 4167 aci = (edcf_acp->ACI & EDCF_ACI_MASK) >> EDCF_ACI_SHIFT; 4168 4169 /* fill in shm ac params struct */ 4170 txq_pars.txop = edcf_acp->TXOP; 4171 txq_pars.aifs = edcf_acp->ACI; 4172 4173 /* CWmin = 2^(ECWmin) - 1 */ 4174 txq_pars.cw_min = EDCF_ECW2CW(edcf_acp->ECW & EDCF_ECWMIN_MASK); 4175 /* CWmax = 2^(ECWmax) - 1 */ 4176 txq_pars.cw_max = EDCF_ECW2CW((edcf_acp->ECW & EDCF_ECWMAX_MASK) 4177 >> EDCF_ECWMAX_SHIFT); 4178 brcms_c_wme_setparams(wlc, aci, &txq_pars, suspend); 4179 } 4180 4181 if (suspend) { 4182 brcms_c_suspend_mac_and_wait(wlc); 4183 brcms_c_enable_mac(wlc); 4184 } 4185} 4186 4187static void brcms_c_radio_monitor_start(struct brcms_c_info *wlc) 4188{ 4189 /* Don't start the timer if HWRADIO feature is disabled */ 4190 if (wlc->radio_monitor) 4191 return; 4192 4193 wlc->radio_monitor = true; 4194 brcms_b_pllreq(wlc->hw, true, BRCMS_PLLREQ_RADIO_MON); 4195 brcms_add_timer(wlc->radio_timer, TIMER_INTERVAL_RADIOCHK, true); 4196} 4197 4198static bool brcms_c_radio_monitor_stop(struct brcms_c_info *wlc) 4199{ 4200 if (!wlc->radio_monitor) 4201 return true; 4202 4203 wlc->radio_monitor = false; 4204 brcms_b_pllreq(wlc->hw, false, BRCMS_PLLREQ_RADIO_MON); 4205 return brcms_del_timer(wlc->radio_timer); 4206} 4207 4208/* read hwdisable state and propagate to wlc flag */ 4209static void brcms_c_radio_hwdisable_upd(struct brcms_c_info *wlc) 4210{ 4211 if (wlc->pub->hw_off) 4212 return; 4213 4214 if (brcms_b_radio_read_hwdisabled(wlc->hw)) 4215 mboolset(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE); 4216 else 4217 mboolclr(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE); 4218} 4219 4220/* update hwradio status and return it */ 4221bool brcms_c_check_radio_disabled(struct brcms_c_info *wlc) 4222{ 4223 brcms_c_radio_hwdisable_upd(wlc); 4224 4225 return mboolisset(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE) ? 4226 true : false; 4227} 4228 4229/* periodical query hw radio button while driver is "down" */ 4230static void brcms_c_radio_timer(void *arg) 4231{ 4232 struct brcms_c_info *wlc = (struct brcms_c_info *) arg; 4233 4234 if (brcms_deviceremoved(wlc)) { 4235 wiphy_err(wlc->wiphy, "wl%d: %s: dead chip\n", wlc->pub->unit, 4236 __func__); 4237 brcms_down(wlc->wl); 4238 return; 4239 } 4240 4241 brcms_c_radio_hwdisable_upd(wlc); 4242} 4243 4244/* common low-level watchdog code */ 4245static void brcms_b_watchdog(void *arg) 4246{ 4247 struct brcms_c_info *wlc = (struct brcms_c_info *) arg; 4248 struct brcms_hardware *wlc_hw = wlc->hw; 4249 4250 BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit); 4251 4252 if (!wlc_hw->up) 4253 return; 4254 4255 /* increment second count */ 4256 wlc_hw->now++; 4257 4258 /* Check for FIFO error interrupts */ 4259 brcms_b_fifoerrors(wlc_hw); 4260 4261 /* make sure RX dma has buffers */ 4262 dma_rxfill(wlc->hw->di[RX_FIFO]); 4263 4264 wlc_phy_watchdog(wlc_hw->band->pi); 4265} 4266 4267/* common watchdog code */ 4268static void brcms_c_watchdog(void *arg) 4269{ 4270 struct brcms_c_info *wlc = (struct brcms_c_info *) arg; 4271 4272 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit); 4273 4274 if (!wlc->pub->up) 4275 return; 4276 4277 if (brcms_deviceremoved(wlc)) { 4278 wiphy_err(wlc->wiphy, "wl%d: %s: dead chip\n", wlc->pub->unit, 4279 __func__); 4280 brcms_down(wlc->wl); 4281 return; 4282 } 4283 4284 /* increment second count */ 4285 wlc->pub->now++; 4286 4287 brcms_c_radio_hwdisable_upd(wlc); 4288 /* if radio is disable, driver may be down, quit here */ 4289 if (wlc->pub->radio_disabled) 4290 return; 4291 4292 brcms_b_watchdog(wlc); 4293 4294 /* 4295 * occasionally sample mac stat counters to 4296 * detect 16-bit counter wrap 4297 */ 4298 if ((wlc->pub->now % SW_TIMER_MAC_STAT_UPD) == 0) 4299 brcms_c_statsupd(wlc); 4300 4301 if (BRCMS_ISNPHY(wlc->band) && 4302 ((wlc->pub->now - wlc->tempsense_lasttime) >= 4303 BRCMS_TEMPSENSE_PERIOD)) { 4304 wlc->tempsense_lasttime = wlc->pub->now; 4305 brcms_c_tempsense_upd(wlc); 4306 } 4307} 4308 4309static void brcms_c_watchdog_by_timer(void *arg) 4310{ 4311 brcms_c_watchdog(arg); 4312} 4313 4314static bool brcms_c_timers_init(struct brcms_c_info *wlc, int unit) 4315{ 4316 wlc->wdtimer = brcms_init_timer(wlc->wl, brcms_c_watchdog_by_timer, 4317 wlc, "watchdog"); 4318 if (!wlc->wdtimer) { 4319 wiphy_err(wlc->wiphy, "wl%d: wl_init_timer for wdtimer " 4320 "failed\n", unit); 4321 goto fail; 4322 } 4323 4324 wlc->radio_timer = brcms_init_timer(wlc->wl, brcms_c_radio_timer, 4325 wlc, "radio"); 4326 if (!wlc->radio_timer) { 4327 wiphy_err(wlc->wiphy, "wl%d: wl_init_timer for radio_timer " 4328 "failed\n", unit); 4329 goto fail; 4330 } 4331 4332 return true; 4333 4334 fail: 4335 return false; 4336} 4337 4338/* 4339 * Initialize brcms_c_info default values ... 4340 * may get overrides later in this function 4341 */ 4342static void brcms_c_info_init(struct brcms_c_info *wlc, int unit) 4343{ 4344 int i; 4345 4346 /* Save our copy of the chanspec */ 4347 wlc->chanspec = ch20mhz_chspec(1); 4348 4349 /* various 802.11g modes */ 4350 wlc->shortslot = false; 4351 wlc->shortslot_override = BRCMS_SHORTSLOT_AUTO; 4352 4353 brcms_c_protection_upd(wlc, BRCMS_PROT_G_OVR, BRCMS_PROTECTION_AUTO); 4354 brcms_c_protection_upd(wlc, BRCMS_PROT_G_SPEC, false); 4355 4356 brcms_c_protection_upd(wlc, BRCMS_PROT_N_CFG_OVR, 4357 BRCMS_PROTECTION_AUTO); 4358 brcms_c_protection_upd(wlc, BRCMS_PROT_N_CFG, BRCMS_N_PROTECTION_OFF); 4359 brcms_c_protection_upd(wlc, BRCMS_PROT_N_NONGF_OVR, 4360 BRCMS_PROTECTION_AUTO); 4361 brcms_c_protection_upd(wlc, BRCMS_PROT_N_NONGF, false); 4362 brcms_c_protection_upd(wlc, BRCMS_PROT_N_PAM_OVR, AUTO); 4363 4364 brcms_c_protection_upd(wlc, BRCMS_PROT_OVERLAP, 4365 BRCMS_PROTECTION_CTL_OVERLAP); 4366 4367 /* 802.11g draft 4.0 NonERP elt advertisement */ 4368 wlc->include_legacy_erp = true; 4369 4370 wlc->stf->ant_rx_ovr = ANT_RX_DIV_DEF; 4371 wlc->stf->txant = ANT_TX_DEF; 4372 4373 wlc->prb_resp_timeout = BRCMS_PRB_RESP_TIMEOUT; 4374 4375 wlc->usr_fragthresh = DOT11_DEFAULT_FRAG_LEN; 4376 for (i = 0; i < NFIFO; i++) 4377 wlc->fragthresh[i] = DOT11_DEFAULT_FRAG_LEN; 4378 wlc->RTSThresh = DOT11_DEFAULT_RTS_LEN; 4379 4380 /* default rate fallback retry limits */ 4381 wlc->SFBL = RETRY_SHORT_FB; 4382 wlc->LFBL = RETRY_LONG_FB; 4383 4384 /* default mac retry limits */ 4385 wlc->SRL = RETRY_SHORT_DEF; 4386 wlc->LRL = RETRY_LONG_DEF; 4387 4388 /* WME QoS mode is Auto by default */ 4389 wlc->pub->_ampdu = AMPDU_AGG_HOST; 4390 wlc->pub->bcmerror = 0; 4391} 4392 4393static uint brcms_c_attach_module(struct brcms_c_info *wlc) 4394{ 4395 uint err = 0; 4396 uint unit; 4397 unit = wlc->pub->unit; 4398 4399 wlc->asi = brcms_c_antsel_attach(wlc); 4400 if (wlc->asi == NULL) { 4401 wiphy_err(wlc->wiphy, "wl%d: attach: antsel_attach " 4402 "failed\n", unit); 4403 err = 44; 4404 goto fail; 4405 } 4406 4407 wlc->ampdu = brcms_c_ampdu_attach(wlc); 4408 if (wlc->ampdu == NULL) { 4409 wiphy_err(wlc->wiphy, "wl%d: attach: ampdu_attach " 4410 "failed\n", unit); 4411 err = 50; 4412 goto fail; 4413 } 4414 4415 if ((brcms_c_stf_attach(wlc) != 0)) { 4416 wiphy_err(wlc->wiphy, "wl%d: attach: stf_attach " 4417 "failed\n", unit); 4418 err = 68; 4419 goto fail; 4420 } 4421 fail: 4422 return err; 4423} 4424 4425struct brcms_pub *brcms_c_pub(struct brcms_c_info *wlc) 4426{ 4427 return wlc->pub; 4428} 4429 4430/* low level attach 4431 * run backplane attach, init nvram 4432 * run phy attach 4433 * initialize software state for each core and band 4434 * put the whole chip in reset(driver down state), no clock 4435 */ 4436static int brcms_b_attach(struct brcms_c_info *wlc, struct bcma_device *core, 4437 uint unit, bool piomode) 4438{ 4439 struct brcms_hardware *wlc_hw; 4440 char *macaddr = NULL; 4441 uint err = 0; 4442 uint j; 4443 bool wme = false; 4444 struct shared_phy_params sha_params; 4445 struct wiphy *wiphy = wlc->wiphy; 4446 struct pci_dev *pcidev = core->bus->host_pci; 4447 4448 BCMMSG(wlc->wiphy, "wl%d: vendor 0x%x device 0x%x\n", unit, 4449 pcidev->vendor, 4450 pcidev->device); 4451 4452 wme = true; 4453 4454 wlc_hw = wlc->hw; 4455 wlc_hw->wlc = wlc; 4456 wlc_hw->unit = unit; 4457 wlc_hw->band = wlc_hw->bandstate[0]; 4458 wlc_hw->_piomode = piomode; 4459 4460 /* populate struct brcms_hardware with default values */ 4461 brcms_b_info_init(wlc_hw); 4462 4463 /* 4464 * Do the hardware portion of the attach. Also initialize software 4465 * state that depends on the particular hardware we are running. 4466 */ 4467 wlc_hw->sih = ai_attach(core->bus); 4468 if (wlc_hw->sih == NULL) { 4469 wiphy_err(wiphy, "wl%d: brcms_b_attach: si_attach failed\n", 4470 unit); 4471 err = 11; 4472 goto fail; 4473 } 4474 4475 /* verify again the device is supported */ 4476 if (!brcms_c_chipmatch(pcidev->vendor, pcidev->device)) { 4477 wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported " 4478 "vendor/device (0x%x/0x%x)\n", 4479 unit, pcidev->vendor, pcidev->device); 4480 err = 12; 4481 goto fail; 4482 } 4483 4484 wlc_hw->vendorid = pcidev->vendor; 4485 wlc_hw->deviceid = pcidev->device; 4486 4487 /* set bar0 window to point at D11 core */ 4488 (void)ai_setcore(wlc_hw->sih, D11_CORE_ID, 0); 4489 wlc_hw->d11core = core; 4490 wlc_hw->corerev = core->id.rev; 4491 4492 /* validate chip, chiprev and corerev */ 4493 if (!brcms_c_isgoodchip(wlc_hw)) { 4494 err = 13; 4495 goto fail; 4496 } 4497 4498 /* initialize power control registers */ 4499 ai_clkctl_init(wlc_hw->sih); 4500 4501 /* request fastclock and force fastclock for the rest of attach 4502 * bring the d11 core out of reset. 4503 * For PMU chips, the first wlc_clkctl_clk is no-op since core-clk 4504 * is still false; But it will be called again inside wlc_corereset, 4505 * after d11 is out of reset. 4506 */ 4507 brcms_b_clkctl_clk(wlc_hw, CLK_FAST); 4508 brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS); 4509 4510 if (!brcms_b_validate_chip_access(wlc_hw)) { 4511 wiphy_err(wiphy, "wl%d: brcms_b_attach: validate_chip_access " 4512 "failed\n", unit); 4513 err = 14; 4514 goto fail; 4515 } 4516 4517 /* get the board rev, used just below */ 4518 j = getintvar(wlc_hw->sih, BRCMS_SROM_BOARDREV); 4519 /* promote srom boardrev of 0xFF to 1 */ 4520 if (j == BOARDREV_PROMOTABLE) 4521 j = BOARDREV_PROMOTED; 4522 wlc_hw->boardrev = (u16) j; 4523 if (!brcms_c_validboardtype(wlc_hw)) { 4524 wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported Broadcom " 4525 "board type (0x%x)" " or revision level (0x%x)\n", 4526 unit, ai_get_boardtype(wlc_hw->sih), 4527 wlc_hw->boardrev); 4528 err = 15; 4529 goto fail; 4530 } 4531 wlc_hw->sromrev = (u8) getintvar(wlc_hw->sih, BRCMS_SROM_REV); 4532 wlc_hw->boardflags = (u32) getintvar(wlc_hw->sih, 4533 BRCMS_SROM_BOARDFLAGS); 4534 wlc_hw->boardflags2 = (u32) getintvar(wlc_hw->sih, 4535 BRCMS_SROM_BOARDFLAGS2); 4536 4537 if (wlc_hw->boardflags & BFL_NOPLLDOWN) 4538 brcms_b_pllreq(wlc_hw, true, BRCMS_PLLREQ_SHARED); 4539 4540 /* check device id(srom, nvram etc.) to set bands */ 4541 if (wlc_hw->deviceid == BCM43224_D11N_ID || 4542 wlc_hw->deviceid == BCM43224_D11N_ID_VEN1) 4543 /* Dualband boards */ 4544 wlc_hw->_nbands = 2; 4545 else 4546 wlc_hw->_nbands = 1; 4547 4548 if ((ai_get_chip_id(wlc_hw->sih) == BCM43225_CHIP_ID)) 4549 wlc_hw->_nbands = 1; 4550 4551 /* BMAC_NOTE: remove init of pub values when brcms_c_attach() 4552 * unconditionally does the init of these values 4553 */ 4554 wlc->vendorid = wlc_hw->vendorid; 4555 wlc->deviceid = wlc_hw->deviceid; 4556 wlc->pub->sih = wlc_hw->sih; 4557 wlc->pub->corerev = wlc_hw->corerev; 4558 wlc->pub->sromrev = wlc_hw->sromrev; 4559 wlc->pub->boardrev = wlc_hw->boardrev; 4560 wlc->pub->boardflags = wlc_hw->boardflags; 4561 wlc->pub->boardflags2 = wlc_hw->boardflags2; 4562 wlc->pub->_nbands = wlc_hw->_nbands; 4563 4564 wlc_hw->physhim = wlc_phy_shim_attach(wlc_hw, wlc->wl, wlc); 4565 4566 if (wlc_hw->physhim == NULL) { 4567 wiphy_err(wiphy, "wl%d: brcms_b_attach: wlc_phy_shim_attach " 4568 "failed\n", unit); 4569 err = 25; 4570 goto fail; 4571 } 4572 4573 /* pass all the parameters to wlc_phy_shared_attach in one struct */ 4574 sha_params.sih = wlc_hw->sih; 4575 sha_params.physhim = wlc_hw->physhim; 4576 sha_params.unit = unit; 4577 sha_params.corerev = wlc_hw->corerev; 4578 sha_params.vid = wlc_hw->vendorid; 4579 sha_params.did = wlc_hw->deviceid; 4580 sha_params.chip = ai_get_chip_id(wlc_hw->sih); 4581 sha_params.chiprev = ai_get_chiprev(wlc_hw->sih); 4582 sha_params.chippkg = ai_get_chippkg(wlc_hw->sih); 4583 sha_params.sromrev = wlc_hw->sromrev; 4584 sha_params.boardtype = ai_get_boardtype(wlc_hw->sih); 4585 sha_params.boardrev = wlc_hw->boardrev; 4586 sha_params.boardflags = wlc_hw->boardflags; 4587 sha_params.boardflags2 = wlc_hw->boardflags2; 4588 4589 /* alloc and save pointer to shared phy state area */ 4590 wlc_hw->phy_sh = wlc_phy_shared_attach(&sha_params); 4591 if (!wlc_hw->phy_sh) { 4592 err = 16; 4593 goto fail; 4594 } 4595 4596 /* initialize software state for each core and band */ 4597 for (j = 0; j < wlc_hw->_nbands; j++) { 4598 /* 4599 * band0 is always 2.4Ghz 4600 * band1, if present, is 5Ghz 4601 */ 4602 4603 brcms_c_setxband(wlc_hw, j); 4604 4605 wlc_hw->band->bandunit = j; 4606 wlc_hw->band->bandtype = j ? BRCM_BAND_5G : BRCM_BAND_2G; 4607 wlc->band->bandunit = j; 4608 wlc->band->bandtype = j ? BRCM_BAND_5G : BRCM_BAND_2G; 4609 wlc->core->coreidx = ai_coreidx(wlc_hw->sih); 4610 4611 wlc_hw->machwcap = bcma_read32(core, D11REGOFFS(machwcap)); 4612 wlc_hw->machwcap_backup = wlc_hw->machwcap; 4613 4614 /* init tx fifo size */ 4615 wlc_hw->xmtfifo_sz = 4616 xmtfifo_sz[(wlc_hw->corerev - XMTFIFOTBL_STARTREV)]; 4617 4618 /* Get a phy for this band */ 4619 wlc_hw->band->pi = 4620 wlc_phy_attach(wlc_hw->phy_sh, core, 4621 wlc_hw->band->bandtype, 4622 wlc->wiphy); 4623 if (wlc_hw->band->pi == NULL) { 4624 wiphy_err(wiphy, "wl%d: brcms_b_attach: wlc_phy_" 4625 "attach failed\n", unit); 4626 err = 17; 4627 goto fail; 4628 } 4629 4630 wlc_phy_machwcap_set(wlc_hw->band->pi, wlc_hw->machwcap); 4631 4632 wlc_phy_get_phyversion(wlc_hw->band->pi, &wlc_hw->band->phytype, 4633 &wlc_hw->band->phyrev, 4634 &wlc_hw->band->radioid, 4635 &wlc_hw->band->radiorev); 4636 wlc_hw->band->abgphy_encore = 4637 wlc_phy_get_encore(wlc_hw->band->pi); 4638 wlc->band->abgphy_encore = wlc_phy_get_encore(wlc_hw->band->pi); 4639 wlc_hw->band->core_flags = 4640 wlc_phy_get_coreflags(wlc_hw->band->pi); 4641 4642 /* verify good phy_type & supported phy revision */ 4643 if (BRCMS_ISNPHY(wlc_hw->band)) { 4644 if (NCONF_HAS(wlc_hw->band->phyrev)) 4645 goto good_phy; 4646 else 4647 goto bad_phy; 4648 } else if (BRCMS_ISLCNPHY(wlc_hw->band)) { 4649 if (LCNCONF_HAS(wlc_hw->band->phyrev)) 4650 goto good_phy; 4651 else 4652 goto bad_phy; 4653 } else { 4654 bad_phy: 4655 wiphy_err(wiphy, "wl%d: brcms_b_attach: unsupported " 4656 "phy type/rev (%d/%d)\n", unit, 4657 wlc_hw->band->phytype, wlc_hw->band->phyrev); 4658 err = 18; 4659 goto fail; 4660 } 4661 4662 good_phy: 4663 /* 4664 * BMAC_NOTE: wlc->band->pi should not be set below and should 4665 * be done in the high level attach. However we can not make 4666 * that change until all low level access is changed to 4667 * wlc_hw->band->pi. Instead do the wlc->band->pi init below, 4668 * keeping wlc_hw->band->pi as well for incremental update of 4669 * low level fns, and cut over low only init when all fns 4670 * updated. 4671 */ 4672 wlc->band->pi = wlc_hw->band->pi; 4673 wlc->band->phytype = wlc_hw->band->phytype; 4674 wlc->band->phyrev = wlc_hw->band->phyrev; 4675 wlc->band->radioid = wlc_hw->band->radioid; 4676 wlc->band->radiorev = wlc_hw->band->radiorev; 4677 4678 /* default contention windows size limits */ 4679 wlc_hw->band->CWmin = APHY_CWMIN; 4680 wlc_hw->band->CWmax = PHY_CWMAX; 4681 4682 if (!brcms_b_attach_dmapio(wlc, j, wme)) { 4683 err = 19; 4684 goto fail; 4685 } 4686 } 4687 4688 /* disable core to match driver "down" state */ 4689 brcms_c_coredisable(wlc_hw); 4690 4691 /* Match driver "down" state */ 4692 ai_pci_down(wlc_hw->sih); 4693 4694 /* turn off pll and xtal to match driver "down" state */ 4695 brcms_b_xtal(wlc_hw, OFF); 4696 4697 /* ******************************************************************* 4698 * The hardware is in the DOWN state at this point. D11 core 4699 * or cores are in reset with clocks off, and the board PLLs 4700 * are off if possible. 4701 * 4702 * Beyond this point, wlc->sbclk == false and chip registers 4703 * should not be touched. 4704 ********************************************************************* 4705 */ 4706 4707 /* init etheraddr state variables */ 4708 macaddr = brcms_c_get_macaddr(wlc_hw); 4709 if (macaddr == NULL) { 4710 wiphy_err(wiphy, "wl%d: brcms_b_attach: macaddr not found\n", 4711 unit); 4712 err = 21; 4713 goto fail; 4714 } 4715 if (!mac_pton(macaddr, wlc_hw->etheraddr) || 4716 is_broadcast_ether_addr(wlc_hw->etheraddr) || 4717 is_zero_ether_addr(wlc_hw->etheraddr)) { 4718 wiphy_err(wiphy, "wl%d: brcms_b_attach: bad macaddr %s\n", 4719 unit, macaddr); 4720 err = 22; 4721 goto fail; 4722 } 4723 4724 BCMMSG(wlc->wiphy, "deviceid 0x%x nbands %d board 0x%x macaddr: %s\n", 4725 wlc_hw->deviceid, wlc_hw->_nbands, ai_get_boardtype(wlc_hw->sih), 4726 macaddr); 4727 4728 return err; 4729 4730 fail: 4731 wiphy_err(wiphy, "wl%d: brcms_b_attach: failed with err %d\n", unit, 4732 err); 4733 return err; 4734} 4735 4736static void brcms_c_attach_antgain_init(struct brcms_c_info *wlc) 4737{ 4738 uint unit; 4739 unit = wlc->pub->unit; 4740 4741 if ((wlc->band->antgain == -1) && (wlc->pub->sromrev == 1)) { 4742 /* default antenna gain for srom rev 1 is 2 dBm (8 qdbm) */ 4743 wlc->band->antgain = 8; 4744 } else if (wlc->band->antgain == -1) { 4745 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid antennas available in" 4746 " srom, using 2dB\n", unit, __func__); 4747 wlc->band->antgain = 8; 4748 } else { 4749 s8 gain, fract; 4750 /* Older sroms specified gain in whole dbm only. In order 4751 * be able to specify qdbm granularity and remain backward 4752 * compatible the whole dbms are now encoded in only 4753 * low 6 bits and remaining qdbms are encoded in the hi 2 bits. 4754 * 6 bit signed number ranges from -32 - 31. 4755 * 4756 * Examples: 4757 * 0x1 = 1 db, 4758 * 0xc1 = 1.75 db (1 + 3 quarters), 4759 * 0x3f = -1 (-1 + 0 quarters), 4760 * 0x7f = -.75 (-1 + 1 quarters) = -3 qdbm. 4761 * 0xbf = -.50 (-1 + 2 quarters) = -2 qdbm. 4762 */ 4763 gain = wlc->band->antgain & 0x3f; 4764 gain <<= 2; /* Sign extend */ 4765 gain >>= 2; 4766 fract = (wlc->band->antgain & 0xc0) >> 6; 4767 wlc->band->antgain = 4 * gain + fract; 4768 } 4769} 4770 4771static bool brcms_c_attach_stf_ant_init(struct brcms_c_info *wlc) 4772{ 4773 int aa; 4774 uint unit; 4775 int bandtype; 4776 struct si_pub *sih = wlc->hw->sih; 4777 4778 unit = wlc->pub->unit; 4779 bandtype = wlc->band->bandtype; 4780 4781 /* get antennas available */ 4782 if (bandtype == BRCM_BAND_5G) 4783 aa = (s8) getintvar(sih, BRCMS_SROM_AA5G); 4784 else 4785 aa = (s8) getintvar(sih, BRCMS_SROM_AA2G); 4786 4787 if ((aa < 1) || (aa > 15)) { 4788 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid antennas available in" 4789 " srom (0x%x), using 3\n", unit, __func__, aa); 4790 aa = 3; 4791 } 4792 4793 /* reset the defaults if we have a single antenna */ 4794 if (aa == 1) { 4795 wlc->stf->ant_rx_ovr = ANT_RX_DIV_FORCE_0; 4796 wlc->stf->txant = ANT_TX_FORCE_0; 4797 } else if (aa == 2) { 4798 wlc->stf->ant_rx_ovr = ANT_RX_DIV_FORCE_1; 4799 wlc->stf->txant = ANT_TX_FORCE_1; 4800 } else { 4801 } 4802 4803 /* Compute Antenna Gain */ 4804 if (bandtype == BRCM_BAND_5G) 4805 wlc->band->antgain = (s8) getintvar(sih, BRCMS_SROM_AG1); 4806 else 4807 wlc->band->antgain = (s8) getintvar(sih, BRCMS_SROM_AG0); 4808 4809 brcms_c_attach_antgain_init(wlc); 4810 4811 return true; 4812} 4813 4814static void brcms_c_bss_default_init(struct brcms_c_info *wlc) 4815{ 4816 u16 chanspec; 4817 struct brcms_band *band; 4818 struct brcms_bss_info *bi = wlc->default_bss; 4819 4820 /* init default and target BSS with some sane initial values */ 4821 memset((char *)(bi), 0, sizeof(struct brcms_bss_info)); 4822 bi->beacon_period = BEACON_INTERVAL_DEFAULT; 4823 4824 /* fill the default channel as the first valid channel 4825 * starting from the 2G channels 4826 */ 4827 chanspec = ch20mhz_chspec(1); 4828 wlc->home_chanspec = bi->chanspec = chanspec; 4829 4830 /* find the band of our default channel */ 4831 band = wlc->band; 4832 if (wlc->pub->_nbands > 1 && 4833 band->bandunit != chspec_bandunit(chanspec)) 4834 band = wlc->bandstate[OTHERBANDUNIT(wlc)]; 4835 4836 /* init bss rates to the band specific default rate set */ 4837 brcms_c_rateset_default(&bi->rateset, NULL, band->phytype, 4838 band->bandtype, false, BRCMS_RATE_MASK_FULL, 4839 (bool) (wlc->pub->_n_enab & SUPPORT_11N), 4840 brcms_chspec_bw(chanspec), wlc->stf->txstreams); 4841 4842 if (wlc->pub->_n_enab & SUPPORT_11N) 4843 bi->flags |= BRCMS_BSS_HT; 4844} 4845 4846static struct brcms_txq_info *brcms_c_txq_alloc(struct brcms_c_info *wlc) 4847{ 4848 struct brcms_txq_info *qi, *p; 4849 4850 qi = kzalloc(sizeof(struct brcms_txq_info), GFP_ATOMIC); 4851 if (qi != NULL) { 4852 /* 4853 * Have enough room for control packets along with HI watermark 4854 * Also, add room to txq for total psq packets if all the SCBs 4855 * leave PS mode. The watermark for flowcontrol to OS packets 4856 * will remain the same 4857 */ 4858 brcmu_pktq_init(&qi->q, BRCMS_PREC_COUNT, 4859 2 * BRCMS_DATAHIWAT + PKTQ_LEN_DEFAULT); 4860 4861 /* add this queue to the the global list */ 4862 p = wlc->tx_queues; 4863 if (p == NULL) { 4864 wlc->tx_queues = qi; 4865 } else { 4866 while (p->next != NULL) 4867 p = p->next; 4868 p->next = qi; 4869 } 4870 } 4871 return qi; 4872} 4873 4874static void brcms_c_txq_free(struct brcms_c_info *wlc, 4875 struct brcms_txq_info *qi) 4876{ 4877 struct brcms_txq_info *p; 4878 4879 if (qi == NULL) 4880 return; 4881 4882 /* remove the queue from the linked list */ 4883 p = wlc->tx_queues; 4884 if (p == qi) 4885 wlc->tx_queues = p->next; 4886 else { 4887 while (p != NULL && p->next != qi) 4888 p = p->next; 4889 if (p != NULL) 4890 p->next = p->next->next; 4891 } 4892 4893 kfree(qi); 4894} 4895 4896static void brcms_c_update_mimo_band_bwcap(struct brcms_c_info *wlc, u8 bwcap) 4897{ 4898 uint i; 4899 struct brcms_band *band; 4900 4901 for (i = 0; i < wlc->pub->_nbands; i++) { 4902 band = wlc->bandstate[i]; 4903 if (band->bandtype == BRCM_BAND_5G) { 4904 if ((bwcap == BRCMS_N_BW_40ALL) 4905 || (bwcap == BRCMS_N_BW_20IN2G_40IN5G)) 4906 band->mimo_cap_40 = true; 4907 else 4908 band->mimo_cap_40 = false; 4909 } else { 4910 if (bwcap == BRCMS_N_BW_40ALL) 4911 band->mimo_cap_40 = true; 4912 else 4913 band->mimo_cap_40 = false; 4914 } 4915 } 4916} 4917 4918static void brcms_c_timers_deinit(struct brcms_c_info *wlc) 4919{ 4920 /* free timer state */ 4921 if (wlc->wdtimer) { 4922 brcms_free_timer(wlc->wdtimer); 4923 wlc->wdtimer = NULL; 4924 } 4925 if (wlc->radio_timer) { 4926 brcms_free_timer(wlc->radio_timer); 4927 wlc->radio_timer = NULL; 4928 } 4929} 4930 4931static void brcms_c_detach_module(struct brcms_c_info *wlc) 4932{ 4933 if (wlc->asi) { 4934 brcms_c_antsel_detach(wlc->asi); 4935 wlc->asi = NULL; 4936 } 4937 4938 if (wlc->ampdu) { 4939 brcms_c_ampdu_detach(wlc->ampdu); 4940 wlc->ampdu = NULL; 4941 } 4942 4943 brcms_c_stf_detach(wlc); 4944} 4945 4946/* 4947 * low level detach 4948 */ 4949static int brcms_b_detach(struct brcms_c_info *wlc) 4950{ 4951 uint i; 4952 struct brcms_hw_band *band; 4953 struct brcms_hardware *wlc_hw = wlc->hw; 4954 int callbacks; 4955 4956 callbacks = 0; 4957 4958 if (wlc_hw->sih) { 4959 /* 4960 * detach interrupt sync mechanism since interrupt is disabled 4961 * and per-port interrupt object may has been freed. this must 4962 * be done before sb core switch 4963 */ 4964 ai_pci_sleep(wlc_hw->sih); 4965 } 4966 4967 brcms_b_detach_dmapio(wlc_hw); 4968 4969 band = wlc_hw->band; 4970 for (i = 0; i < wlc_hw->_nbands; i++) { 4971 if (band->pi) { 4972 /* Detach this band's phy */ 4973 wlc_phy_detach(band->pi); 4974 band->pi = NULL; 4975 } 4976 band = wlc_hw->bandstate[OTHERBANDUNIT(wlc)]; 4977 } 4978 4979 /* Free shared phy state */ 4980 kfree(wlc_hw->phy_sh); 4981 4982 wlc_phy_shim_detach(wlc_hw->physhim); 4983 4984 if (wlc_hw->sih) { 4985 ai_detach(wlc_hw->sih); 4986 wlc_hw->sih = NULL; 4987 } 4988 4989 return callbacks; 4990 4991} 4992 4993/* 4994 * Return a count of the number of driver callbacks still pending. 4995 * 4996 * General policy is that brcms_c_detach can only dealloc/free software states. 4997 * It can NOT touch hardware registers since the d11core may be in reset and 4998 * clock may not be available. 4999 * One exception is sb register access, which is possible if crystal is turned 5000 * on after "down" state, driver should avoid software timer with the exception 5001 * of radio_monitor. 5002 */ 5003uint brcms_c_detach(struct brcms_c_info *wlc) 5004{ 5005 uint callbacks = 0; 5006 5007 if (wlc == NULL) 5008 return 0; 5009 5010 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit); 5011 5012 callbacks += brcms_b_detach(wlc); 5013 5014 /* delete software timers */ 5015 if (!brcms_c_radio_monitor_stop(wlc)) 5016 callbacks++; 5017 5018 brcms_c_channel_mgr_detach(wlc->cmi); 5019 5020 brcms_c_timers_deinit(wlc); 5021 5022 brcms_c_detach_module(wlc); 5023 5024 5025 while (wlc->tx_queues != NULL) 5026 brcms_c_txq_free(wlc, wlc->tx_queues); 5027 5028 brcms_c_detach_mfree(wlc); 5029 return callbacks; 5030} 5031 5032/* update state that depends on the current value of "ap" */ 5033static void brcms_c_ap_upd(struct brcms_c_info *wlc) 5034{ 5035 /* STA-BSS; short capable */ 5036 wlc->PLCPHdr_override = BRCMS_PLCP_SHORT; 5037} 5038 5039/* Initialize just the hardware when coming out of POR or S3/S5 system states */ 5040static void brcms_b_hw_up(struct brcms_hardware *wlc_hw) 5041{ 5042 if (wlc_hw->wlc->pub->hw_up) 5043 return; 5044 5045 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit); 5046 5047 /* 5048 * Enable pll and xtal, initialize the power control registers, 5049 * and force fastclock for the remainder of brcms_c_up(). 5050 */ 5051 brcms_b_xtal(wlc_hw, ON); 5052 ai_clkctl_init(wlc_hw->sih); 5053 brcms_b_clkctl_clk(wlc_hw, CLK_FAST); 5054 5055 ai_pci_fixcfg(wlc_hw->sih); 5056 5057 /* 5058 * AI chip doesn't restore bar0win2 on 5059 * hibernation/resume, need sw fixup 5060 */ 5061 if ((ai_get_chip_id(wlc_hw->sih) == BCM43224_CHIP_ID) || 5062 (ai_get_chip_id(wlc_hw->sih) == BCM43225_CHIP_ID)) 5063 (void)ai_setcore(wlc_hw->sih, D11_CORE_ID, 0); 5064 5065 /* 5066 * Inform phy that a POR reset has occurred so 5067 * it does a complete phy init 5068 */ 5069 wlc_phy_por_inform(wlc_hw->band->pi); 5070 5071 wlc_hw->ucode_loaded = false; 5072 wlc_hw->wlc->pub->hw_up = true; 5073 5074 if ((wlc_hw->boardflags & BFL_FEM) 5075 && (ai_get_chip_id(wlc_hw->sih) == BCM4313_CHIP_ID)) { 5076 if (! 5077 (wlc_hw->boardrev >= 0x1250 5078 && (wlc_hw->boardflags & BFL_FEM_BT))) 5079 ai_epa_4313war(wlc_hw->sih); 5080 } 5081} 5082 5083static int brcms_b_up_prep(struct brcms_hardware *wlc_hw) 5084{ 5085 uint coremask; 5086 5087 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit); 5088 5089 /* 5090 * Enable pll and xtal, initialize the power control registers, 5091 * and force fastclock for the remainder of brcms_c_up(). 5092 */ 5093 brcms_b_xtal(wlc_hw, ON); 5094 ai_clkctl_init(wlc_hw->sih); 5095 brcms_b_clkctl_clk(wlc_hw, CLK_FAST); 5096 5097 /* 5098 * Configure pci/pcmcia here instead of in brcms_c_attach() 5099 * to allow mfg hotswap: down, hotswap (chip power cycle), up. 5100 */ 5101 coremask = (1 << wlc_hw->wlc->core->coreidx); 5102 5103 ai_pci_setup(wlc_hw->sih, coremask); 5104 5105 /* 5106 * Need to read the hwradio status here to cover the case where the 5107 * system is loaded with the hw radio disabled. We do not want to 5108 * bring the driver up in this case. 5109 */ 5110 if (brcms_b_radio_read_hwdisabled(wlc_hw)) { 5111 /* put SB PCI in down state again */ 5112 ai_pci_down(wlc_hw->sih); 5113 brcms_b_xtal(wlc_hw, OFF); 5114 return -ENOMEDIUM; 5115 } 5116 5117 ai_pci_up(wlc_hw->sih); 5118 5119 /* reset the d11 core */ 5120 brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS); 5121 5122 return 0; 5123} 5124 5125static int brcms_b_up_finish(struct brcms_hardware *wlc_hw) 5126{ 5127 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit); 5128 5129 wlc_hw->up = true; 5130 wlc_phy_hw_state_upd(wlc_hw->band->pi, true); 5131 5132 /* FULLY enable dynamic power control and d11 core interrupt */ 5133 brcms_b_clkctl_clk(wlc_hw, CLK_DYNAMIC); 5134 brcms_intrson(wlc_hw->wlc->wl); 5135 return 0; 5136} 5137 5138/* 5139 * Write WME tunable parameters for retransmit/max rate 5140 * from wlc struct to ucode 5141 */ 5142static void brcms_c_wme_retries_write(struct brcms_c_info *wlc) 5143{ 5144 int ac; 5145 5146 /* Need clock to do this */ 5147 if (!wlc->clk) 5148 return; 5149 5150 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) 5151 brcms_b_write_shm(wlc->hw, M_AC_TXLMT_ADDR(ac), 5152 wlc->wme_retries[ac]); 5153} 5154 5155/* make interface operational */ 5156int brcms_c_up(struct brcms_c_info *wlc) 5157{ 5158 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit); 5159 5160 /* HW is turned off so don't try to access it */ 5161 if (wlc->pub->hw_off || brcms_deviceremoved(wlc)) 5162 return -ENOMEDIUM; 5163 5164 if (!wlc->pub->hw_up) { 5165 brcms_b_hw_up(wlc->hw); 5166 wlc->pub->hw_up = true; 5167 } 5168 5169 if ((wlc->pub->boardflags & BFL_FEM) 5170 && (ai_get_chip_id(wlc->hw->sih) == BCM4313_CHIP_ID)) { 5171 if (wlc->pub->boardrev >= 0x1250 5172 && (wlc->pub->boardflags & BFL_FEM_BT)) 5173 brcms_b_mhf(wlc->hw, MHF5, MHF5_4313_GPIOCTRL, 5174 MHF5_4313_GPIOCTRL, BRCM_BAND_ALL); 5175 else 5176 brcms_b_mhf(wlc->hw, MHF4, MHF4_EXTPA_ENABLE, 5177 MHF4_EXTPA_ENABLE, BRCM_BAND_ALL); 5178 } 5179 5180 /* 5181 * Need to read the hwradio status here to cover the case where the 5182 * system is loaded with the hw radio disabled. We do not want to bring 5183 * the driver up in this case. If radio is disabled, abort up, lower 5184 * power, start radio timer and return 0(for NDIS) don't call 5185 * radio_update to avoid looping brcms_c_up. 5186 * 5187 * brcms_b_up_prep() returns either 0 or -BCME_RADIOOFF only 5188 */ 5189 if (!wlc->pub->radio_disabled) { 5190 int status = brcms_b_up_prep(wlc->hw); 5191 if (status == -ENOMEDIUM) { 5192 if (!mboolisset 5193 (wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE)) { 5194 struct brcms_bss_cfg *bsscfg = wlc->bsscfg; 5195 mboolset(wlc->pub->radio_disabled, 5196 WL_RADIO_HW_DISABLE); 5197 5198 if (bsscfg->enable && bsscfg->BSS) 5199 wiphy_err(wlc->wiphy, "wl%d: up" 5200 ": rfdisable -> " 5201 "bsscfg_disable()\n", 5202 wlc->pub->unit); 5203 } 5204 } 5205 } 5206 5207 if (wlc->pub->radio_disabled) { 5208 brcms_c_radio_monitor_start(wlc); 5209 return 0; 5210 } 5211 5212 /* brcms_b_up_prep has done brcms_c_corereset(). so clk is on, set it */ 5213 wlc->clk = true; 5214 5215 brcms_c_radio_monitor_stop(wlc); 5216 5217 /* Set EDCF hostflags */ 5218 brcms_b_mhf(wlc->hw, MHF1, MHF1_EDCF, MHF1_EDCF, BRCM_BAND_ALL); 5219 5220 brcms_init(wlc->wl); 5221 wlc->pub->up = true; 5222 5223 if (wlc->bandinit_pending) { 5224 brcms_c_suspend_mac_and_wait(wlc); 5225 brcms_c_set_chanspec(wlc, wlc->default_bss->chanspec); 5226 wlc->bandinit_pending = false; 5227 brcms_c_enable_mac(wlc); 5228 } 5229 5230 brcms_b_up_finish(wlc->hw); 5231 5232 /* Program the TX wme params with the current settings */ 5233 brcms_c_wme_retries_write(wlc); 5234 5235 /* start one second watchdog timer */ 5236 brcms_add_timer(wlc->wdtimer, TIMER_INTERVAL_WATCHDOG, true); 5237 wlc->WDarmed = true; 5238 5239 /* ensure antenna config is up to date */ 5240 brcms_c_stf_phy_txant_upd(wlc); 5241 /* ensure LDPC config is in sync */ 5242 brcms_c_ht_update_ldpc(wlc, wlc->stf->ldpc); 5243 5244 return 0; 5245} 5246 5247static uint brcms_c_down_del_timer(struct brcms_c_info *wlc) 5248{ 5249 uint callbacks = 0; 5250 5251 return callbacks; 5252} 5253 5254static int brcms_b_bmac_down_prep(struct brcms_hardware *wlc_hw) 5255{ 5256 bool dev_gone; 5257 uint callbacks = 0; 5258 5259 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit); 5260 5261 if (!wlc_hw->up) 5262 return callbacks; 5263 5264 dev_gone = brcms_deviceremoved(wlc_hw->wlc); 5265 5266 /* disable interrupts */ 5267 if (dev_gone) 5268 wlc_hw->wlc->macintmask = 0; 5269 else { 5270 /* now disable interrupts */ 5271 brcms_intrsoff(wlc_hw->wlc->wl); 5272 5273 /* ensure we're running on the pll clock again */ 5274 brcms_b_clkctl_clk(wlc_hw, CLK_FAST); 5275 } 5276 /* down phy at the last of this stage */ 5277 callbacks += wlc_phy_down(wlc_hw->band->pi); 5278 5279 return callbacks; 5280} 5281 5282static int brcms_b_down_finish(struct brcms_hardware *wlc_hw) 5283{ 5284 uint callbacks = 0; 5285 bool dev_gone; 5286 5287 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit); 5288 5289 if (!wlc_hw->up) 5290 return callbacks; 5291 5292 wlc_hw->up = false; 5293 wlc_phy_hw_state_upd(wlc_hw->band->pi, false); 5294 5295 dev_gone = brcms_deviceremoved(wlc_hw->wlc); 5296 5297 if (dev_gone) { 5298 wlc_hw->sbclk = false; 5299 wlc_hw->clk = false; 5300 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false); 5301 5302 /* reclaim any posted packets */ 5303 brcms_c_flushqueues(wlc_hw->wlc); 5304 } else { 5305 5306 /* Reset and disable the core */ 5307 if (bcma_core_is_enabled(wlc_hw->d11core)) { 5308 if (bcma_read32(wlc_hw->d11core, 5309 D11REGOFFS(maccontrol)) & MCTL_EN_MAC) 5310 brcms_c_suspend_mac_and_wait(wlc_hw->wlc); 5311 callbacks += brcms_reset(wlc_hw->wlc->wl); 5312 brcms_c_coredisable(wlc_hw); 5313 } 5314 5315 /* turn off primary xtal and pll */ 5316 if (!wlc_hw->noreset) { 5317 ai_pci_down(wlc_hw->sih); 5318 brcms_b_xtal(wlc_hw, OFF); 5319 } 5320 } 5321 5322 return callbacks; 5323} 5324 5325/* 5326 * Mark the interface nonoperational, stop the software mechanisms, 5327 * disable the hardware, free any transient buffer state. 5328 * Return a count of the number of driver callbacks still pending. 5329 */ 5330uint brcms_c_down(struct brcms_c_info *wlc) 5331{ 5332 5333 uint callbacks = 0; 5334 int i; 5335 bool dev_gone = false; 5336 struct brcms_txq_info *qi; 5337 5338 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit); 5339 5340 /* check if we are already in the going down path */ 5341 if (wlc->going_down) { 5342 wiphy_err(wlc->wiphy, "wl%d: %s: Driver going down so return" 5343 "\n", wlc->pub->unit, __func__); 5344 return 0; 5345 } 5346 if (!wlc->pub->up) 5347 return callbacks; 5348 5349 wlc->going_down = true; 5350 5351 callbacks += brcms_b_bmac_down_prep(wlc->hw); 5352 5353 dev_gone = brcms_deviceremoved(wlc); 5354 5355 /* Call any registered down handlers */ 5356 for (i = 0; i < BRCMS_MAXMODULES; i++) { 5357 if (wlc->modulecb[i].down_fn) 5358 callbacks += 5359 wlc->modulecb[i].down_fn(wlc->modulecb[i].hdl); 5360 } 5361 5362 /* cancel the watchdog timer */ 5363 if (wlc->WDarmed) { 5364 if (!brcms_del_timer(wlc->wdtimer)) 5365 callbacks++; 5366 wlc->WDarmed = false; 5367 } 5368 /* cancel all other timers */ 5369 callbacks += brcms_c_down_del_timer(wlc); 5370 5371 wlc->pub->up = false; 5372 5373 wlc_phy_mute_upd(wlc->band->pi, false, PHY_MUTE_ALL); 5374 5375 /* clear txq flow control */ 5376 brcms_c_txflowcontrol_reset(wlc); 5377 5378 /* flush tx queues */ 5379 for (qi = wlc->tx_queues; qi != NULL; qi = qi->next) 5380 brcmu_pktq_flush(&qi->q, true, NULL, NULL); 5381 5382 callbacks += brcms_b_down_finish(wlc->hw); 5383 5384 /* brcms_b_down_finish has done brcms_c_coredisable(). so clk is off */ 5385 wlc->clk = false; 5386 5387 wlc->going_down = false; 5388 return callbacks; 5389} 5390 5391/* Set the current gmode configuration */ 5392int brcms_c_set_gmode(struct brcms_c_info *wlc, u8 gmode, bool config) 5393{ 5394 int ret = 0; 5395 uint i; 5396 struct brcms_c_rateset rs; 5397 /* Default to 54g Auto */ 5398 /* Advertise and use shortslot (-1/0/1 Auto/Off/On) */ 5399 s8 shortslot = BRCMS_SHORTSLOT_AUTO; 5400 bool shortslot_restrict = false; /* Restrict association to stations 5401 * that support shortslot 5402 */ 5403 bool ofdm_basic = false; /* Make 6, 12, and 24 basic rates */ 5404 /* Advertise and use short preambles (-1/0/1 Auto/Off/On) */ 5405 int preamble = BRCMS_PLCP_LONG; 5406 bool preamble_restrict = false; /* Restrict association to stations 5407 * that support short preambles 5408 */ 5409 struct brcms_band *band; 5410 5411 /* if N-support is enabled, allow Gmode set as long as requested 5412 * Gmode is not GMODE_LEGACY_B 5413 */ 5414 if ((wlc->pub->_n_enab & SUPPORT_11N) && gmode == GMODE_LEGACY_B) 5415 return -ENOTSUPP; 5416 5417 /* verify that we are dealing with 2G band and grab the band pointer */ 5418 if (wlc->band->bandtype == BRCM_BAND_2G) 5419 band = wlc->band; 5420 else if ((wlc->pub->_nbands > 1) && 5421 (wlc->bandstate[OTHERBANDUNIT(wlc)]->bandtype == BRCM_BAND_2G)) 5422 band = wlc->bandstate[OTHERBANDUNIT(wlc)]; 5423 else 5424 return -EINVAL; 5425 5426 /* Legacy or bust when no OFDM is supported by regulatory */ 5427 if ((brcms_c_channel_locale_flags_in_band(wlc->cmi, band->bandunit) & 5428 BRCMS_NO_OFDM) && (gmode != GMODE_LEGACY_B)) 5429 return -EINVAL; 5430 5431 /* update configuration value */ 5432 if (config == true) 5433 brcms_c_protection_upd(wlc, BRCMS_PROT_G_USER, gmode); 5434 5435 /* Clear rateset override */ 5436 memset(&rs, 0, sizeof(struct brcms_c_rateset)); 5437 5438 switch (gmode) { 5439 case GMODE_LEGACY_B: 5440 shortslot = BRCMS_SHORTSLOT_OFF; 5441 brcms_c_rateset_copy(&gphy_legacy_rates, &rs); 5442 5443 break; 5444 5445 case GMODE_LRS: 5446 break; 5447 5448 case GMODE_AUTO: 5449 /* Accept defaults */ 5450 break; 5451 5452 case GMODE_ONLY: 5453 ofdm_basic = true; 5454 preamble = BRCMS_PLCP_SHORT; 5455 preamble_restrict = true; 5456 break; 5457 5458 case GMODE_PERFORMANCE: 5459 shortslot = BRCMS_SHORTSLOT_ON; 5460 shortslot_restrict = true; 5461 ofdm_basic = true; 5462 preamble = BRCMS_PLCP_SHORT; 5463 preamble_restrict = true; 5464 break; 5465 5466 default: 5467 /* Error */ 5468 wiphy_err(wlc->wiphy, "wl%d: %s: invalid gmode %d\n", 5469 wlc->pub->unit, __func__, gmode); 5470 return -ENOTSUPP; 5471 } 5472 5473 band->gmode = gmode; 5474 5475 wlc->shortslot_override = shortslot; 5476 5477 /* Use the default 11g rateset */ 5478 if (!rs.count) 5479 brcms_c_rateset_copy(&cck_ofdm_rates, &rs); 5480 5481 if (ofdm_basic) { 5482 for (i = 0; i < rs.count; i++) { 5483 if (rs.rates[i] == BRCM_RATE_6M 5484 || rs.rates[i] == BRCM_RATE_12M 5485 || rs.rates[i] == BRCM_RATE_24M) 5486 rs.rates[i] |= BRCMS_RATE_FLAG; 5487 } 5488 } 5489 5490 /* Set default bss rateset */ 5491 wlc->default_bss->rateset.count = rs.count; 5492 memcpy(wlc->default_bss->rateset.rates, rs.rates, 5493 sizeof(wlc->default_bss->rateset.rates)); 5494 5495 return ret; 5496} 5497 5498int brcms_c_set_nmode(struct brcms_c_info *wlc) 5499{ 5500 uint i; 5501 s32 nmode = AUTO; 5502 5503 if (wlc->stf->txstreams == WL_11N_3x3) 5504 nmode = WL_11N_3x3; 5505 else 5506 nmode = WL_11N_2x2; 5507 5508 /* force GMODE_AUTO if NMODE is ON */ 5509 brcms_c_set_gmode(wlc, GMODE_AUTO, true); 5510 if (nmode == WL_11N_3x3) 5511 wlc->pub->_n_enab = SUPPORT_HT; 5512 else 5513 wlc->pub->_n_enab = SUPPORT_11N; 5514 wlc->default_bss->flags |= BRCMS_BSS_HT; 5515 /* add the mcs rates to the default and hw ratesets */ 5516 brcms_c_rateset_mcs_build(&wlc->default_bss->rateset, 5517 wlc->stf->txstreams); 5518 for (i = 0; i < wlc->pub->_nbands; i++) 5519 memcpy(wlc->bandstate[i]->hw_rateset.mcs, 5520 wlc->default_bss->rateset.mcs, MCSSET_LEN); 5521 5522 return 0; 5523} 5524 5525static int 5526brcms_c_set_internal_rateset(struct brcms_c_info *wlc, 5527 struct brcms_c_rateset *rs_arg) 5528{ 5529 struct brcms_c_rateset rs, new; 5530 uint bandunit; 5531 5532 memcpy(&rs, rs_arg, sizeof(struct brcms_c_rateset)); 5533 5534 /* check for bad count value */ 5535 if ((rs.count == 0) || (rs.count > BRCMS_NUMRATES)) 5536 return -EINVAL; 5537 5538 /* try the current band */ 5539 bandunit = wlc->band->bandunit; 5540 memcpy(&new, &rs, sizeof(struct brcms_c_rateset)); 5541 if (brcms_c_rate_hwrs_filter_sort_validate 5542 (&new, &wlc->bandstate[bandunit]->hw_rateset, true, 5543 wlc->stf->txstreams)) 5544 goto good; 5545 5546 /* try the other band */ 5547 if (brcms_is_mband_unlocked(wlc)) { 5548 bandunit = OTHERBANDUNIT(wlc); 5549 memcpy(&new, &rs, sizeof(struct brcms_c_rateset)); 5550 if (brcms_c_rate_hwrs_filter_sort_validate(&new, 5551 &wlc-> 5552 bandstate[bandunit]-> 5553 hw_rateset, true, 5554 wlc->stf->txstreams)) 5555 goto good; 5556 } 5557 5558 return -EBADE; 5559 5560 good: 5561 /* apply new rateset */ 5562 memcpy(&wlc->default_bss->rateset, &new, 5563 sizeof(struct brcms_c_rateset)); 5564 memcpy(&wlc->bandstate[bandunit]->defrateset, &new, 5565 sizeof(struct brcms_c_rateset)); 5566 return 0; 5567} 5568 5569static void brcms_c_ofdm_rateset_war(struct brcms_c_info *wlc) 5570{ 5571 u8 r; 5572 bool war = false; 5573 5574 if (wlc->bsscfg->associated) 5575 r = wlc->bsscfg->current_bss->rateset.rates[0]; 5576 else 5577 r = wlc->default_bss->rateset.rates[0]; 5578 5579 wlc_phy_ofdm_rateset_war(wlc->band->pi, war); 5580} 5581 5582int brcms_c_set_channel(struct brcms_c_info *wlc, u16 channel) 5583{ 5584 u16 chspec = ch20mhz_chspec(channel); 5585 5586 if (channel < 0 || channel > MAXCHANNEL) 5587 return -EINVAL; 5588 5589 if (!brcms_c_valid_chanspec_db(wlc->cmi, chspec)) 5590 return -EINVAL; 5591 5592 5593 if (!wlc->pub->up && brcms_is_mband_unlocked(wlc)) { 5594 if (wlc->band->bandunit != chspec_bandunit(chspec)) 5595 wlc->bandinit_pending = true; 5596 else 5597 wlc->bandinit_pending = false; 5598 } 5599 5600 wlc->default_bss->chanspec = chspec; 5601 /* brcms_c_BSSinit() will sanitize the rateset before 5602 * using it.. */ 5603 if (wlc->pub->up && (wlc_phy_chanspec_get(wlc->band->pi) != chspec)) { 5604 brcms_c_set_home_chanspec(wlc, chspec); 5605 brcms_c_suspend_mac_and_wait(wlc); 5606 brcms_c_set_chanspec(wlc, chspec); 5607 brcms_c_enable_mac(wlc); 5608 } 5609 return 0; 5610} 5611 5612int brcms_c_set_rate_limit(struct brcms_c_info *wlc, u16 srl, u16 lrl) 5613{ 5614 int ac; 5615 5616 if (srl < 1 || srl > RETRY_SHORT_MAX || 5617 lrl < 1 || lrl > RETRY_SHORT_MAX) 5618 return -EINVAL; 5619 5620 wlc->SRL = srl; 5621 wlc->LRL = lrl; 5622 5623 brcms_b_retrylimit_upd(wlc->hw, wlc->SRL, wlc->LRL); 5624 5625 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) { 5626 wlc->wme_retries[ac] = SFIELD(wlc->wme_retries[ac], 5627 EDCF_SHORT, wlc->SRL); 5628 wlc->wme_retries[ac] = SFIELD(wlc->wme_retries[ac], 5629 EDCF_LONG, wlc->LRL); 5630 } 5631 brcms_c_wme_retries_write(wlc); 5632 5633 return 0; 5634} 5635 5636void brcms_c_get_current_rateset(struct brcms_c_info *wlc, 5637 struct brcm_rateset *currs) 5638{ 5639 struct brcms_c_rateset *rs; 5640 5641 if (wlc->pub->associated) 5642 rs = &wlc->bsscfg->current_bss->rateset; 5643 else 5644 rs = &wlc->default_bss->rateset; 5645 5646 /* Copy only legacy rateset section */ 5647 currs->count = rs->count; 5648 memcpy(&currs->rates, &rs->rates, rs->count); 5649} 5650 5651int brcms_c_set_rateset(struct brcms_c_info *wlc, struct brcm_rateset *rs) 5652{ 5653 struct brcms_c_rateset internal_rs; 5654 int bcmerror; 5655 5656 if (rs->count > BRCMS_NUMRATES) 5657 return -ENOBUFS; 5658 5659 memset(&internal_rs, 0, sizeof(struct brcms_c_rateset)); 5660 5661 /* Copy only legacy rateset section */ 5662 internal_rs.count = rs->count; 5663 memcpy(&internal_rs.rates, &rs->rates, internal_rs.count); 5664 5665 /* merge rateset coming in with the current mcsset */ 5666 if (wlc->pub->_n_enab & SUPPORT_11N) { 5667 struct brcms_bss_info *mcsset_bss; 5668 if (wlc->bsscfg->associated) 5669 mcsset_bss = wlc->bsscfg->current_bss; 5670 else 5671 mcsset_bss = wlc->default_bss; 5672 memcpy(internal_rs.mcs, &mcsset_bss->rateset.mcs[0], 5673 MCSSET_LEN); 5674 } 5675 5676 bcmerror = brcms_c_set_internal_rateset(wlc, &internal_rs); 5677 if (!bcmerror) 5678 brcms_c_ofdm_rateset_war(wlc); 5679 5680 return bcmerror; 5681} 5682 5683int brcms_c_set_beacon_period(struct brcms_c_info *wlc, u16 period) 5684{ 5685 if (period < DOT11_MIN_BEACON_PERIOD || 5686 period > DOT11_MAX_BEACON_PERIOD) 5687 return -EINVAL; 5688 5689 wlc->default_bss->beacon_period = period; 5690 return 0; 5691} 5692 5693u16 brcms_c_get_phy_type(struct brcms_c_info *wlc, int phyidx) 5694{ 5695 return wlc->band->phytype; 5696} 5697 5698void brcms_c_set_shortslot_override(struct brcms_c_info *wlc, s8 sslot_override) 5699{ 5700 wlc->shortslot_override = sslot_override; 5701 5702 /* 5703 * shortslot is an 11g feature, so no more work if we are 5704 * currently on the 5G band 5705 */ 5706 if (wlc->band->bandtype == BRCM_BAND_5G) 5707 return; 5708 5709 if (wlc->pub->up && wlc->pub->associated) { 5710 /* let watchdog or beacon processing update shortslot */ 5711 } else if (wlc->pub->up) { 5712 /* unassociated shortslot is off */ 5713 brcms_c_switch_shortslot(wlc, false); 5714 } else { 5715 /* driver is down, so just update the brcms_c_info 5716 * value */ 5717 if (wlc->shortslot_override == BRCMS_SHORTSLOT_AUTO) 5718 wlc->shortslot = false; 5719 else 5720 wlc->shortslot = 5721 (wlc->shortslot_override == 5722 BRCMS_SHORTSLOT_ON); 5723 } 5724} 5725 5726/* 5727 * register watchdog and down handlers. 5728 */ 5729int brcms_c_module_register(struct brcms_pub *pub, 5730 const char *name, struct brcms_info *hdl, 5731 int (*d_fn)(void *handle)) 5732{ 5733 struct brcms_c_info *wlc = (struct brcms_c_info *) pub->wlc; 5734 int i; 5735 5736 /* find an empty entry and just add, no duplication check! */ 5737 for (i = 0; i < BRCMS_MAXMODULES; i++) { 5738 if (wlc->modulecb[i].name[0] == '\0') { 5739 strncpy(wlc->modulecb[i].name, name, 5740 sizeof(wlc->modulecb[i].name) - 1); 5741 wlc->modulecb[i].hdl = hdl; 5742 wlc->modulecb[i].down_fn = d_fn; 5743 return 0; 5744 } 5745 } 5746 5747 return -ENOSR; 5748} 5749 5750/* unregister module callbacks */ 5751int brcms_c_module_unregister(struct brcms_pub *pub, const char *name, 5752 struct brcms_info *hdl) 5753{ 5754 struct brcms_c_info *wlc = (struct brcms_c_info *) pub->wlc; 5755 int i; 5756 5757 if (wlc == NULL) 5758 return -ENODATA; 5759 5760 for (i = 0; i < BRCMS_MAXMODULES; i++) { 5761 if (!strcmp(wlc->modulecb[i].name, name) && 5762 (wlc->modulecb[i].hdl == hdl)) { 5763 memset(&wlc->modulecb[i], 0, sizeof(struct modulecb)); 5764 return 0; 5765 } 5766 } 5767 5768 /* table not found! */ 5769 return -ENODATA; 5770} 5771 5772#ifdef BCMDBG 5773static const char * const supr_reason[] = { 5774 "None", "PMQ Entry", "Flush request", 5775 "Previous frag failure", "Channel mismatch", 5776 "Lifetime Expiry", "Underflow" 5777}; 5778 5779static void brcms_c_print_txs_status(u16 s) 5780{ 5781 printk(KERN_DEBUG "[15:12] %d frame attempts\n", 5782 (s & TX_STATUS_FRM_RTX_MASK) >> TX_STATUS_FRM_RTX_SHIFT); 5783 printk(KERN_DEBUG " [11:8] %d rts attempts\n", 5784 (s & TX_STATUS_RTS_RTX_MASK) >> TX_STATUS_RTS_RTX_SHIFT); 5785 printk(KERN_DEBUG " [7] %d PM mode indicated\n", 5786 ((s & TX_STATUS_PMINDCTD) ? 1 : 0)); 5787 printk(KERN_DEBUG " [6] %d intermediate status\n", 5788 ((s & TX_STATUS_INTERMEDIATE) ? 1 : 0)); 5789 printk(KERN_DEBUG " [5] %d AMPDU\n", 5790 (s & TX_STATUS_AMPDU) ? 1 : 0); 5791 printk(KERN_DEBUG " [4:2] %d Frame Suppressed Reason (%s)\n", 5792 ((s & TX_STATUS_SUPR_MASK) >> TX_STATUS_SUPR_SHIFT), 5793 supr_reason[(s & TX_STATUS_SUPR_MASK) >> TX_STATUS_SUPR_SHIFT]); 5794 printk(KERN_DEBUG " [1] %d acked\n", 5795 ((s & TX_STATUS_ACK_RCV) ? 1 : 0)); 5796} 5797#endif /* BCMDBG */ 5798 5799void brcms_c_print_txstatus(struct tx_status *txs) 5800{ 5801#if defined(BCMDBG) 5802 u16 s = txs->status; 5803 u16 ackphyrxsh = txs->ackphyrxsh; 5804 5805 printk(KERN_DEBUG "\ntxpkt (MPDU) Complete\n"); 5806 5807 printk(KERN_DEBUG "FrameID: %04x ", txs->frameid); 5808 printk(KERN_DEBUG "TxStatus: %04x", s); 5809 printk(KERN_DEBUG "\n"); 5810 5811 brcms_c_print_txs_status(s); 5812 5813 printk(KERN_DEBUG "LastTxTime: %04x ", txs->lasttxtime); 5814 printk(KERN_DEBUG "Seq: %04x ", txs->sequence); 5815 printk(KERN_DEBUG "PHYTxStatus: %04x ", txs->phyerr); 5816 printk(KERN_DEBUG "RxAckRSSI: %04x ", 5817 (ackphyrxsh & PRXS1_JSSI_MASK) >> PRXS1_JSSI_SHIFT); 5818 printk(KERN_DEBUG "RxAckSQ: %04x", 5819 (ackphyrxsh & PRXS1_SQ_MASK) >> PRXS1_SQ_SHIFT); 5820 printk(KERN_DEBUG "\n"); 5821#endif /* defined(BCMDBG) */ 5822} 5823 5824bool brcms_c_chipmatch(u16 vendor, u16 device) 5825{ 5826 if (vendor != PCI_VENDOR_ID_BROADCOM) { 5827 pr_err("chipmatch: unknown vendor id %04x\n", vendor); 5828 return false; 5829 } 5830 5831 if (device == BCM43224_D11N_ID_VEN1) 5832 return true; 5833 if ((device == BCM43224_D11N_ID) || (device == BCM43225_D11N2G_ID)) 5834 return true; 5835 if (device == BCM4313_D11N2G_ID) 5836 return true; 5837 if ((device == BCM43236_D11N_ID) || (device == BCM43236_D11N2G_ID)) 5838 return true; 5839 5840 pr_err("chipmatch: unknown device id %04x\n", device); 5841 return false; 5842} 5843 5844#if defined(BCMDBG) 5845void brcms_c_print_txdesc(struct d11txh *txh) 5846{ 5847 u16 mtcl = le16_to_cpu(txh->MacTxControlLow); 5848 u16 mtch = le16_to_cpu(txh->MacTxControlHigh); 5849 u16 mfc = le16_to_cpu(txh->MacFrameControl); 5850 u16 tfest = le16_to_cpu(txh->TxFesTimeNormal); 5851 u16 ptcw = le16_to_cpu(txh->PhyTxControlWord); 5852 u16 ptcw_1 = le16_to_cpu(txh->PhyTxControlWord_1); 5853 u16 ptcw_1_Fbr = le16_to_cpu(txh->PhyTxControlWord_1_Fbr); 5854 u16 ptcw_1_Rts = le16_to_cpu(txh->PhyTxControlWord_1_Rts); 5855 u16 ptcw_1_FbrRts = le16_to_cpu(txh->PhyTxControlWord_1_FbrRts); 5856 u16 mainrates = le16_to_cpu(txh->MainRates); 5857 u16 xtraft = le16_to_cpu(txh->XtraFrameTypes); 5858 u8 *iv = txh->IV; 5859 u8 *ra = txh->TxFrameRA; 5860 u16 tfestfb = le16_to_cpu(txh->TxFesTimeFallback); 5861 u8 *rtspfb = txh->RTSPLCPFallback; 5862 u16 rtsdfb = le16_to_cpu(txh->RTSDurFallback); 5863 u8 *fragpfb = txh->FragPLCPFallback; 5864 u16 fragdfb = le16_to_cpu(txh->FragDurFallback); 5865 u16 mmodelen = le16_to_cpu(txh->MModeLen); 5866 u16 mmodefbrlen = le16_to_cpu(txh->MModeFbrLen); 5867 u16 tfid = le16_to_cpu(txh->TxFrameID); 5868 u16 txs = le16_to_cpu(txh->TxStatus); 5869 u16 mnmpdu = le16_to_cpu(txh->MaxNMpdus); 5870 u16 mabyte = le16_to_cpu(txh->MaxABytes_MRT); 5871 u16 mabyte_f = le16_to_cpu(txh->MaxABytes_FBR); 5872 u16 mmbyte = le16_to_cpu(txh->MinMBytes); 5873 5874 u8 *rtsph = txh->RTSPhyHeader; 5875 struct ieee80211_rts rts = txh->rts_frame; 5876 5877 /* add plcp header along with txh descriptor */ 5878 printk(KERN_DEBUG "Raw TxDesc + plcp header:\n"); 5879 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, 5880 txh, sizeof(struct d11txh) + 48); 5881 5882 printk(KERN_DEBUG "TxCtlLow: %04x ", mtcl); 5883 printk(KERN_DEBUG "TxCtlHigh: %04x ", mtch); 5884 printk(KERN_DEBUG "FC: %04x ", mfc); 5885 printk(KERN_DEBUG "FES Time: %04x\n", tfest); 5886 printk(KERN_DEBUG "PhyCtl: %04x%s ", ptcw, 5887 (ptcw & PHY_TXC_SHORT_HDR) ? " short" : ""); 5888 printk(KERN_DEBUG "PhyCtl_1: %04x ", ptcw_1); 5889 printk(KERN_DEBUG "PhyCtl_1_Fbr: %04x\n", ptcw_1_Fbr); 5890 printk(KERN_DEBUG "PhyCtl_1_Rts: %04x ", ptcw_1_Rts); 5891 printk(KERN_DEBUG "PhyCtl_1_Fbr_Rts: %04x\n", ptcw_1_FbrRts); 5892 printk(KERN_DEBUG "MainRates: %04x ", mainrates); 5893 printk(KERN_DEBUG "XtraFrameTypes: %04x ", xtraft); 5894 printk(KERN_DEBUG "\n"); 5895 5896 print_hex_dump_bytes("SecIV:", DUMP_PREFIX_OFFSET, iv, sizeof(txh->IV)); 5897 print_hex_dump_bytes("RA:", DUMP_PREFIX_OFFSET, 5898 ra, sizeof(txh->TxFrameRA)); 5899 5900 printk(KERN_DEBUG "Fb FES Time: %04x ", tfestfb); 5901 print_hex_dump_bytes("Fb RTS PLCP:", DUMP_PREFIX_OFFSET, 5902 rtspfb, sizeof(txh->RTSPLCPFallback)); 5903 printk(KERN_DEBUG "RTS DUR: %04x ", rtsdfb); 5904 print_hex_dump_bytes("PLCP:", DUMP_PREFIX_OFFSET, 5905 fragpfb, sizeof(txh->FragPLCPFallback)); 5906 printk(KERN_DEBUG "DUR: %04x", fragdfb); 5907 printk(KERN_DEBUG "\n"); 5908 5909 printk(KERN_DEBUG "MModeLen: %04x ", mmodelen); 5910 printk(KERN_DEBUG "MModeFbrLen: %04x\n", mmodefbrlen); 5911 5912 printk(KERN_DEBUG "FrameID: %04x\n", tfid); 5913 printk(KERN_DEBUG "TxStatus: %04x\n", txs); 5914 5915 printk(KERN_DEBUG "MaxNumMpdu: %04x\n", mnmpdu); 5916 printk(KERN_DEBUG "MaxAggbyte: %04x\n", mabyte); 5917 printk(KERN_DEBUG "MaxAggbyte_fb: %04x\n", mabyte_f); 5918 printk(KERN_DEBUG "MinByte: %04x\n", mmbyte); 5919 5920 print_hex_dump_bytes("RTS PLCP:", DUMP_PREFIX_OFFSET, 5921 rtsph, sizeof(txh->RTSPhyHeader)); 5922 print_hex_dump_bytes("RTS Frame:", DUMP_PREFIX_OFFSET, 5923 (u8 *)&rts, sizeof(txh->rts_frame)); 5924 printk(KERN_DEBUG "\n"); 5925} 5926#endif /* defined(BCMDBG) */ 5927 5928#if defined(BCMDBG) 5929static int 5930brcms_c_format_flags(const struct brcms_c_bit_desc *bd, u32 flags, char *buf, 5931 int len) 5932{ 5933 int i; 5934 char *p = buf; 5935 char hexstr[16]; 5936 int slen = 0, nlen = 0; 5937 u32 bit; 5938 const char *name; 5939 5940 if (len < 2 || !buf) 5941 return 0; 5942 5943 buf[0] = '\0'; 5944 5945 for (i = 0; flags != 0; i++) { 5946 bit = bd[i].bit; 5947 name = bd[i].name; 5948 if (bit == 0 && flags != 0) { 5949 /* print any unnamed bits */ 5950 snprintf(hexstr, 16, "0x%X", flags); 5951 name = hexstr; 5952 flags = 0; /* exit loop */ 5953 } else if ((flags & bit) == 0) 5954 continue; 5955 flags &= ~bit; 5956 nlen = strlen(name); 5957 slen += nlen; 5958 /* count btwn flag space */ 5959 if (flags != 0) 5960 slen += 1; 5961 /* need NULL char as well */ 5962 if (len <= slen) 5963 break; 5964 /* copy NULL char but don't count it */ 5965 strncpy(p, name, nlen + 1); 5966 p += nlen; 5967 /* copy btwn flag space and NULL char */ 5968 if (flags != 0) 5969 p += snprintf(p, 2, " "); 5970 len -= slen; 5971 } 5972 5973 /* indicate the str was too short */ 5974 if (flags != 0) { 5975 if (len < 2) 5976 p -= 2 - len; /* overwrite last char */ 5977 p += snprintf(p, 2, ">"); 5978 } 5979 5980 return (int)(p - buf); 5981} 5982#endif /* defined(BCMDBG) */ 5983 5984#if defined(BCMDBG) 5985void brcms_c_print_rxh(struct d11rxhdr *rxh) 5986{ 5987 u16 len = rxh->RxFrameSize; 5988 u16 phystatus_0 = rxh->PhyRxStatus_0; 5989 u16 phystatus_1 = rxh->PhyRxStatus_1; 5990 u16 phystatus_2 = rxh->PhyRxStatus_2; 5991 u16 phystatus_3 = rxh->PhyRxStatus_3; 5992 u16 macstatus1 = rxh->RxStatus1; 5993 u16 macstatus2 = rxh->RxStatus2; 5994 char flagstr[64]; 5995 char lenbuf[20]; 5996 static const struct brcms_c_bit_desc macstat_flags[] = { 5997 {RXS_FCSERR, "FCSErr"}, 5998 {RXS_RESPFRAMETX, "Reply"}, 5999 {RXS_PBPRES, "PADDING"}, 6000 {RXS_DECATMPT, "DeCr"}, 6001 {RXS_DECERR, "DeCrErr"}, 6002 {RXS_BCNSENT, "Bcn"}, 6003 {0, NULL} 6004 }; 6005 6006 printk(KERN_DEBUG "Raw RxDesc:\n"); 6007 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, rxh, 6008 sizeof(struct d11rxhdr)); 6009 6010 brcms_c_format_flags(macstat_flags, macstatus1, flagstr, 64); 6011 6012 snprintf(lenbuf, sizeof(lenbuf), "0x%x", len); 6013 6014 printk(KERN_DEBUG "RxFrameSize: %6s (%d)%s\n", lenbuf, len, 6015 (rxh->PhyRxStatus_0 & PRXS0_SHORTH) ? " short preamble" : ""); 6016 printk(KERN_DEBUG "RxPHYStatus: %04x %04x %04x %04x\n", 6017 phystatus_0, phystatus_1, phystatus_2, phystatus_3); 6018 printk(KERN_DEBUG "RxMACStatus: %x %s\n", macstatus1, flagstr); 6019 printk(KERN_DEBUG "RXMACaggtype: %x\n", 6020 (macstatus2 & RXS_AGGTYPE_MASK)); 6021 printk(KERN_DEBUG "RxTSFTime: %04x\n", rxh->RxTSFTime); 6022} 6023#endif /* defined(BCMDBG) */ 6024 6025u16 brcms_b_rate_shm_offset(struct brcms_hardware *wlc_hw, u8 rate) 6026{ 6027 u16 table_ptr; 6028 u8 phy_rate, index; 6029 6030 /* get the phy specific rate encoding for the PLCP SIGNAL field */ 6031 if (is_ofdm_rate(rate)) 6032 table_ptr = M_RT_DIRMAP_A; 6033 else 6034 table_ptr = M_RT_DIRMAP_B; 6035 6036 /* for a given rate, the LS-nibble of the PLCP SIGNAL field is 6037 * the index into the rate table. 6038 */ 6039 phy_rate = rate_info[rate] & BRCMS_RATE_MASK; 6040 index = phy_rate & 0xf; 6041 6042 /* Find the SHM pointer to the rate table entry by looking in the 6043 * Direct-map Table 6044 */ 6045 return 2 * brcms_b_read_shm(wlc_hw, table_ptr + (index * 2)); 6046} 6047 6048static bool 6049brcms_c_prec_enq_head(struct brcms_c_info *wlc, struct pktq *q, 6050 struct sk_buff *pkt, int prec, bool head) 6051{ 6052 struct sk_buff *p; 6053 int eprec = -1; /* precedence to evict from */ 6054 6055 /* Determine precedence from which to evict packet, if any */ 6056 if (pktq_pfull(q, prec)) 6057 eprec = prec; 6058 else if (pktq_full(q)) { 6059 p = brcmu_pktq_peek_tail(q, &eprec); 6060 if (eprec > prec) { 6061 wiphy_err(wlc->wiphy, "%s: Failing: eprec %d > prec %d" 6062 "\n", __func__, eprec, prec); 6063 return false; 6064 } 6065 } 6066 6067 /* Evict if needed */ 6068 if (eprec >= 0) { 6069 bool discard_oldest; 6070 6071 discard_oldest = ac_bitmap_tst(0, eprec); 6072 6073 /* Refuse newer packet unless configured to discard oldest */ 6074 if (eprec == prec && !discard_oldest) { 6075 wiphy_err(wlc->wiphy, "%s: No where to go, prec == %d" 6076 "\n", __func__, prec); 6077 return false; 6078 } 6079 6080 /* Evict packet according to discard policy */ 6081 p = discard_oldest ? brcmu_pktq_pdeq(q, eprec) : 6082 brcmu_pktq_pdeq_tail(q, eprec); 6083 brcmu_pkt_buf_free_skb(p); 6084 } 6085 6086 /* Enqueue */ 6087 if (head) 6088 p = brcmu_pktq_penq_head(q, prec, pkt); 6089 else 6090 p = brcmu_pktq_penq(q, prec, pkt); 6091 6092 return true; 6093} 6094 6095/* 6096 * Attempts to queue a packet onto a multiple-precedence queue, 6097 * if necessary evicting a lower precedence packet from the queue. 6098 * 6099 * 'prec' is the precedence number that has already been mapped 6100 * from the packet priority. 6101 * 6102 * Returns true if packet consumed (queued), false if not. 6103 */ 6104static bool brcms_c_prec_enq(struct brcms_c_info *wlc, struct pktq *q, 6105 struct sk_buff *pkt, int prec) 6106{ 6107 return brcms_c_prec_enq_head(wlc, q, pkt, prec, false); 6108} 6109 6110void brcms_c_txq_enq(struct brcms_c_info *wlc, struct scb *scb, 6111 struct sk_buff *sdu, uint prec) 6112{ 6113 struct brcms_txq_info *qi = wlc->pkt_queue; /* Check me */ 6114 struct pktq *q = &qi->q; 6115 int prio; 6116 6117 prio = sdu->priority; 6118 6119 if (!brcms_c_prec_enq(wlc, q, sdu, prec)) { 6120 /* 6121 * we might hit this condtion in case 6122 * packet flooding from mac80211 stack 6123 */ 6124 brcmu_pkt_buf_free_skb(sdu); 6125 } 6126} 6127 6128/* 6129 * bcmc_fid_generate: 6130 * Generate frame ID for a BCMC packet. The frag field is not used 6131 * for MC frames so is used as part of the sequence number. 6132 */ 6133static inline u16 6134bcmc_fid_generate(struct brcms_c_info *wlc, struct brcms_bss_cfg *bsscfg, 6135 struct d11txh *txh) 6136{ 6137 u16 frameid; 6138 6139 frameid = le16_to_cpu(txh->TxFrameID) & ~(TXFID_SEQ_MASK | 6140 TXFID_QUEUE_MASK); 6141 frameid |= 6142 (((wlc-> 6143 mc_fid_counter++) << TXFID_SEQ_SHIFT) & TXFID_SEQ_MASK) | 6144 TX_BCMC_FIFO; 6145 6146 return frameid; 6147} 6148 6149static uint 6150brcms_c_calc_ack_time(struct brcms_c_info *wlc, u32 rspec, 6151 u8 preamble_type) 6152{ 6153 uint dur = 0; 6154 6155 BCMMSG(wlc->wiphy, "wl%d: rspec 0x%x, preamble_type %d\n", 6156 wlc->pub->unit, rspec, preamble_type); 6157 /* 6158 * Spec 9.6: ack rate is the highest rate in BSSBasicRateSet that 6159 * is less than or equal to the rate of the immediately previous 6160 * frame in the FES 6161 */ 6162 rspec = brcms_basic_rate(wlc, rspec); 6163 /* ACK frame len == 14 == 2(fc) + 2(dur) + 6(ra) + 4(fcs) */ 6164 dur = 6165 brcms_c_calc_frame_time(wlc, rspec, preamble_type, 6166 (DOT11_ACK_LEN + FCS_LEN)); 6167 return dur; 6168} 6169 6170static uint 6171brcms_c_calc_cts_time(struct brcms_c_info *wlc, u32 rspec, 6172 u8 preamble_type) 6173{ 6174 BCMMSG(wlc->wiphy, "wl%d: ratespec 0x%x, preamble_type %d\n", 6175 wlc->pub->unit, rspec, preamble_type); 6176 return brcms_c_calc_ack_time(wlc, rspec, preamble_type); 6177} 6178 6179static uint 6180brcms_c_calc_ba_time(struct brcms_c_info *wlc, u32 rspec, 6181 u8 preamble_type) 6182{ 6183 BCMMSG(wlc->wiphy, "wl%d: rspec 0x%x, " 6184 "preamble_type %d\n", wlc->pub->unit, rspec, preamble_type); 6185 /* 6186 * Spec 9.6: ack rate is the highest rate in BSSBasicRateSet that 6187 * is less than or equal to the rate of the immediately previous 6188 * frame in the FES 6189 */ 6190 rspec = brcms_basic_rate(wlc, rspec); 6191 /* BA len == 32 == 16(ctl hdr) + 4(ba len) + 8(bitmap) + 4(fcs) */ 6192 return brcms_c_calc_frame_time(wlc, rspec, preamble_type, 6193 (DOT11_BA_LEN + DOT11_BA_BITMAP_LEN + 6194 FCS_LEN)); 6195} 6196 6197/* brcms_c_compute_frame_dur() 6198 * 6199 * Calculate the 802.11 MAC header DUR field for MPDU 6200 * DUR for a single frame = 1 SIFS + 1 ACK 6201 * DUR for a frame with following frags = 3 SIFS + 2 ACK + next frag time 6202 * 6203 * rate MPDU rate in unit of 500kbps 6204 * next_frag_len next MPDU length in bytes 6205 * preamble_type use short/GF or long/MM PLCP header 6206 */ 6207static u16 6208brcms_c_compute_frame_dur(struct brcms_c_info *wlc, u32 rate, 6209 u8 preamble_type, uint next_frag_len) 6210{ 6211 u16 dur, sifs; 6212 6213 sifs = get_sifs(wlc->band); 6214 6215 dur = sifs; 6216 dur += (u16) brcms_c_calc_ack_time(wlc, rate, preamble_type); 6217 6218 if (next_frag_len) { 6219 /* Double the current DUR to get 2 SIFS + 2 ACKs */ 6220 dur *= 2; 6221 /* add another SIFS and the frag time */ 6222 dur += sifs; 6223 dur += 6224 (u16) brcms_c_calc_frame_time(wlc, rate, preamble_type, 6225 next_frag_len); 6226 } 6227 return dur; 6228} 6229 6230/* The opposite of brcms_c_calc_frame_time */ 6231static uint 6232brcms_c_calc_frame_len(struct brcms_c_info *wlc, u32 ratespec, 6233 u8 preamble_type, uint dur) 6234{ 6235 uint nsyms, mac_len, Ndps, kNdps; 6236 uint rate = rspec2rate(ratespec); 6237 6238 BCMMSG(wlc->wiphy, "wl%d: rspec 0x%x, preamble_type %d, dur %d\n", 6239 wlc->pub->unit, ratespec, preamble_type, dur); 6240 6241 if (is_mcs_rate(ratespec)) { 6242 uint mcs = ratespec & RSPEC_RATE_MASK; 6243 int tot_streams = mcs_2_txstreams(mcs) + rspec_stc(ratespec); 6244 dur -= PREN_PREAMBLE + (tot_streams * PREN_PREAMBLE_EXT); 6245 /* payload calculation matches that of regular ofdm */ 6246 if (wlc->band->bandtype == BRCM_BAND_2G) 6247 dur -= DOT11_OFDM_SIGNAL_EXTENSION; 6248 /* kNdbps = kbps * 4 */ 6249 kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec), 6250 rspec_issgi(ratespec)) * 4; 6251 nsyms = dur / APHY_SYMBOL_TIME; 6252 mac_len = 6253 ((nsyms * kNdps) - 6254 ((APHY_SERVICE_NBITS + APHY_TAIL_NBITS) * 1000)) / 8000; 6255 } else if (is_ofdm_rate(ratespec)) { 6256 dur -= APHY_PREAMBLE_TIME; 6257 dur -= APHY_SIGNAL_TIME; 6258 /* Ndbps = Mbps * 4 = rate(500Kbps) * 2 */ 6259 Ndps = rate * 2; 6260 nsyms = dur / APHY_SYMBOL_TIME; 6261 mac_len = 6262 ((nsyms * Ndps) - 6263 (APHY_SERVICE_NBITS + APHY_TAIL_NBITS)) / 8; 6264 } else { 6265 if (preamble_type & BRCMS_SHORT_PREAMBLE) 6266 dur -= BPHY_PLCP_SHORT_TIME; 6267 else 6268 dur -= BPHY_PLCP_TIME; 6269 mac_len = dur * rate; 6270 /* divide out factor of 2 in rate (1/2 mbps) */ 6271 mac_len = mac_len / 8 / 2; 6272 } 6273 return mac_len; 6274} 6275 6276/* 6277 * Return true if the specified rate is supported by the specified band. 6278 * BRCM_BAND_AUTO indicates the current band. 6279 */ 6280static bool brcms_c_valid_rate(struct brcms_c_info *wlc, u32 rspec, int band, 6281 bool verbose) 6282{ 6283 struct brcms_c_rateset *hw_rateset; 6284 uint i; 6285 6286 if ((band == BRCM_BAND_AUTO) || (band == wlc->band->bandtype)) 6287 hw_rateset = &wlc->band->hw_rateset; 6288 else if (wlc->pub->_nbands > 1) 6289 hw_rateset = &wlc->bandstate[OTHERBANDUNIT(wlc)]->hw_rateset; 6290 else 6291 /* other band specified and we are a single band device */ 6292 return false; 6293 6294 /* check if this is a mimo rate */ 6295 if (is_mcs_rate(rspec)) { 6296 if ((rspec & RSPEC_RATE_MASK) >= MCS_TABLE_SIZE) 6297 goto error; 6298 6299 return isset(hw_rateset->mcs, (rspec & RSPEC_RATE_MASK)); 6300 } 6301 6302 for (i = 0; i < hw_rateset->count; i++) 6303 if (hw_rateset->rates[i] == rspec2rate(rspec)) 6304 return true; 6305 error: 6306 if (verbose) 6307 wiphy_err(wlc->wiphy, "wl%d: valid_rate: rate spec 0x%x " 6308 "not in hw_rateset\n", wlc->pub->unit, rspec); 6309 6310 return false; 6311} 6312 6313static u32 6314mac80211_wlc_set_nrate(struct brcms_c_info *wlc, struct brcms_band *cur_band, 6315 u32 int_val) 6316{ 6317 u8 stf = (int_val & NRATE_STF_MASK) >> NRATE_STF_SHIFT; 6318 u8 rate = int_val & NRATE_RATE_MASK; 6319 u32 rspec; 6320 bool ismcs = ((int_val & NRATE_MCS_INUSE) == NRATE_MCS_INUSE); 6321 bool issgi = ((int_val & NRATE_SGI_MASK) >> NRATE_SGI_SHIFT); 6322 bool override_mcs_only = ((int_val & NRATE_OVERRIDE_MCS_ONLY) 6323 == NRATE_OVERRIDE_MCS_ONLY); 6324 int bcmerror = 0; 6325 6326 if (!ismcs) 6327 return (u32) rate; 6328 6329 /* validate the combination of rate/mcs/stf is allowed */ 6330 if ((wlc->pub->_n_enab & SUPPORT_11N) && ismcs) { 6331 /* mcs only allowed when nmode */ 6332 if (stf > PHY_TXC1_MODE_SDM) { 6333 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid stf\n", 6334 wlc->pub->unit, __func__); 6335 bcmerror = -EINVAL; 6336 goto done; 6337 } 6338 6339 /* mcs 32 is a special case, DUP mode 40 only */ 6340 if (rate == 32) { 6341 if (!CHSPEC_IS40(wlc->home_chanspec) || 6342 ((stf != PHY_TXC1_MODE_SISO) 6343 && (stf != PHY_TXC1_MODE_CDD))) { 6344 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid mcs " 6345 "32\n", wlc->pub->unit, __func__); 6346 bcmerror = -EINVAL; 6347 goto done; 6348 } 6349 /* mcs > 7 must use stf SDM */ 6350 } else if (rate > HIGHEST_SINGLE_STREAM_MCS) { 6351 /* mcs > 7 must use stf SDM */ 6352 if (stf != PHY_TXC1_MODE_SDM) { 6353 BCMMSG(wlc->wiphy, "wl%d: enabling " 6354 "SDM mode for mcs %d\n", 6355 wlc->pub->unit, rate); 6356 stf = PHY_TXC1_MODE_SDM; 6357 } 6358 } else { 6359 /* 6360 * MCS 0-7 may use SISO, CDD, and for 6361 * phy_rev >= 3 STBC 6362 */ 6363 if ((stf > PHY_TXC1_MODE_STBC) || 6364 (!BRCMS_STBC_CAP_PHY(wlc) 6365 && (stf == PHY_TXC1_MODE_STBC))) { 6366 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid STBC" 6367 "\n", wlc->pub->unit, __func__); 6368 bcmerror = -EINVAL; 6369 goto done; 6370 } 6371 } 6372 } else if (is_ofdm_rate(rate)) { 6373 if ((stf != PHY_TXC1_MODE_CDD) && (stf != PHY_TXC1_MODE_SISO)) { 6374 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid OFDM\n", 6375 wlc->pub->unit, __func__); 6376 bcmerror = -EINVAL; 6377 goto done; 6378 } 6379 } else if (is_cck_rate(rate)) { 6380 if ((cur_band->bandtype != BRCM_BAND_2G) 6381 || (stf != PHY_TXC1_MODE_SISO)) { 6382 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid CCK\n", 6383 wlc->pub->unit, __func__); 6384 bcmerror = -EINVAL; 6385 goto done; 6386 } 6387 } else { 6388 wiphy_err(wlc->wiphy, "wl%d: %s: Unknown rate type\n", 6389 wlc->pub->unit, __func__); 6390 bcmerror = -EINVAL; 6391 goto done; 6392 } 6393 /* make sure multiple antennae are available for non-siso rates */ 6394 if ((stf != PHY_TXC1_MODE_SISO) && (wlc->stf->txstreams == 1)) { 6395 wiphy_err(wlc->wiphy, "wl%d: %s: SISO antenna but !SISO " 6396 "request\n", wlc->pub->unit, __func__); 6397 bcmerror = -EINVAL; 6398 goto done; 6399 } 6400 6401 rspec = rate; 6402 if (ismcs) { 6403 rspec |= RSPEC_MIMORATE; 6404 /* For STBC populate the STC field of the ratespec */ 6405 if (stf == PHY_TXC1_MODE_STBC) { 6406 u8 stc; 6407 stc = 1; /* Nss for single stream is always 1 */ 6408 rspec |= (stc << RSPEC_STC_SHIFT); 6409 } 6410 } 6411 6412 rspec |= (stf << RSPEC_STF_SHIFT); 6413 6414 if (override_mcs_only) 6415 rspec |= RSPEC_OVERRIDE_MCS_ONLY; 6416 6417 if (issgi) 6418 rspec |= RSPEC_SHORT_GI; 6419 6420 if ((rate != 0) 6421 && !brcms_c_valid_rate(wlc, rspec, cur_band->bandtype, true)) 6422 return rate; 6423 6424 return rspec; 6425done: 6426 return rate; 6427} 6428 6429/* 6430 * Compute PLCP, but only requires actual rate and length of pkt. 6431 * Rate is given in the driver standard multiple of 500 kbps. 6432 * le is set for 11 Mbps rate if necessary. 6433 * Broken out for PRQ. 6434 */ 6435 6436static void brcms_c_cck_plcp_set(struct brcms_c_info *wlc, int rate_500, 6437 uint length, u8 *plcp) 6438{ 6439 u16 usec = 0; 6440 u8 le = 0; 6441 6442 switch (rate_500) { 6443 case BRCM_RATE_1M: 6444 usec = length << 3; 6445 break; 6446 case BRCM_RATE_2M: 6447 usec = length << 2; 6448 break; 6449 case BRCM_RATE_5M5: 6450 usec = (length << 4) / 11; 6451 if ((length << 4) - (usec * 11) > 0) 6452 usec++; 6453 break; 6454 case BRCM_RATE_11M: 6455 usec = (length << 3) / 11; 6456 if ((length << 3) - (usec * 11) > 0) { 6457 usec++; 6458 if ((usec * 11) - (length << 3) >= 8) 6459 le = D11B_PLCP_SIGNAL_LE; 6460 } 6461 break; 6462 6463 default: 6464 wiphy_err(wlc->wiphy, 6465 "brcms_c_cck_plcp_set: unsupported rate %d\n", 6466 rate_500); 6467 rate_500 = BRCM_RATE_1M; 6468 usec = length << 3; 6469 break; 6470 } 6471 /* PLCP signal byte */ 6472 plcp[0] = rate_500 * 5; /* r (500kbps) * 5 == r (100kbps) */ 6473 /* PLCP service byte */ 6474 plcp[1] = (u8) (le | D11B_PLCP_SIGNAL_LOCKED); 6475 /* PLCP length u16, little endian */ 6476 plcp[2] = usec & 0xff; 6477 plcp[3] = (usec >> 8) & 0xff; 6478 /* PLCP CRC16 */ 6479 plcp[4] = 0; 6480 plcp[5] = 0; 6481} 6482 6483/* Rate: 802.11 rate code, length: PSDU length in octets */ 6484static void brcms_c_compute_mimo_plcp(u32 rspec, uint length, u8 *plcp) 6485{ 6486 u8 mcs = (u8) (rspec & RSPEC_RATE_MASK); 6487 plcp[0] = mcs; 6488 if (rspec_is40mhz(rspec) || (mcs == 32)) 6489 plcp[0] |= MIMO_PLCP_40MHZ; 6490 BRCMS_SET_MIMO_PLCP_LEN(plcp, length); 6491 plcp[3] = rspec_mimoplcp3(rspec); /* rspec already holds this byte */ 6492 plcp[3] |= 0x7; /* set smoothing, not sounding ppdu & reserved */ 6493 plcp[4] = 0; /* number of extension spatial streams bit 0 & 1 */ 6494 plcp[5] = 0; 6495} 6496 6497/* Rate: 802.11 rate code, length: PSDU length in octets */ 6498static void 6499brcms_c_compute_ofdm_plcp(u32 rspec, u32 length, u8 *plcp) 6500{ 6501 u8 rate_signal; 6502 u32 tmp = 0; 6503 int rate = rspec2rate(rspec); 6504 6505 /* 6506 * encode rate per 802.11a-1999 sec 17.3.4.1, with lsb 6507 * transmitted first 6508 */ 6509 rate_signal = rate_info[rate] & BRCMS_RATE_MASK; 6510 memset(plcp, 0, D11_PHY_HDR_LEN); 6511 D11A_PHY_HDR_SRATE((struct ofdm_phy_hdr *) plcp, rate_signal); 6512 6513 tmp = (length & 0xfff) << 5; 6514 plcp[2] |= (tmp >> 16) & 0xff; 6515 plcp[1] |= (tmp >> 8) & 0xff; 6516 plcp[0] |= tmp & 0xff; 6517} 6518 6519/* Rate: 802.11 rate code, length: PSDU length in octets */ 6520static void brcms_c_compute_cck_plcp(struct brcms_c_info *wlc, u32 rspec, 6521 uint length, u8 *plcp) 6522{ 6523 int rate = rspec2rate(rspec); 6524 6525 brcms_c_cck_plcp_set(wlc, rate, length, plcp); 6526} 6527 6528static void 6529brcms_c_compute_plcp(struct brcms_c_info *wlc, u32 rspec, 6530 uint length, u8 *plcp) 6531{ 6532 if (is_mcs_rate(rspec)) 6533 brcms_c_compute_mimo_plcp(rspec, length, plcp); 6534 else if (is_ofdm_rate(rspec)) 6535 brcms_c_compute_ofdm_plcp(rspec, length, plcp); 6536 else 6537 brcms_c_compute_cck_plcp(wlc, rspec, length, plcp); 6538} 6539 6540/* brcms_c_compute_rtscts_dur() 6541 * 6542 * Calculate the 802.11 MAC header DUR field for an RTS or CTS frame 6543 * DUR for normal RTS/CTS w/ frame = 3 SIFS + 1 CTS + next frame time + 1 ACK 6544 * DUR for CTS-TO-SELF w/ frame = 2 SIFS + next frame time + 1 ACK 6545 * 6546 * cts cts-to-self or rts/cts 6547 * rts_rate rts or cts rate in unit of 500kbps 6548 * rate next MPDU rate in unit of 500kbps 6549 * frame_len next MPDU frame length in bytes 6550 */ 6551u16 6552brcms_c_compute_rtscts_dur(struct brcms_c_info *wlc, bool cts_only, 6553 u32 rts_rate, 6554 u32 frame_rate, u8 rts_preamble_type, 6555 u8 frame_preamble_type, uint frame_len, bool ba) 6556{ 6557 u16 dur, sifs; 6558 6559 sifs = get_sifs(wlc->band); 6560 6561 if (!cts_only) { 6562 /* RTS/CTS */ 6563 dur = 3 * sifs; 6564 dur += 6565 (u16) brcms_c_calc_cts_time(wlc, rts_rate, 6566 rts_preamble_type); 6567 } else { 6568 /* CTS-TO-SELF */ 6569 dur = 2 * sifs; 6570 } 6571 6572 dur += 6573 (u16) brcms_c_calc_frame_time(wlc, frame_rate, frame_preamble_type, 6574 frame_len); 6575 if (ba) 6576 dur += 6577 (u16) brcms_c_calc_ba_time(wlc, frame_rate, 6578 BRCMS_SHORT_PREAMBLE); 6579 else 6580 dur += 6581 (u16) brcms_c_calc_ack_time(wlc, frame_rate, 6582 frame_preamble_type); 6583 return dur; 6584} 6585 6586static u16 brcms_c_phytxctl1_calc(struct brcms_c_info *wlc, u32 rspec) 6587{ 6588 u16 phyctl1 = 0; 6589 u16 bw; 6590 6591 if (BRCMS_ISLCNPHY(wlc->band)) { 6592 bw = PHY_TXC1_BW_20MHZ; 6593 } else { 6594 bw = rspec_get_bw(rspec); 6595 /* 10Mhz is not supported yet */ 6596 if (bw < PHY_TXC1_BW_20MHZ) { 6597 wiphy_err(wlc->wiphy, "phytxctl1_calc: bw %d is " 6598 "not supported yet, set to 20L\n", bw); 6599 bw = PHY_TXC1_BW_20MHZ; 6600 } 6601 } 6602 6603 if (is_mcs_rate(rspec)) { 6604 uint mcs = rspec & RSPEC_RATE_MASK; 6605 6606 /* bw, stf, coding-type is part of rspec_phytxbyte2 returns */ 6607 phyctl1 = rspec_phytxbyte2(rspec); 6608 /* set the upper byte of phyctl1 */ 6609 phyctl1 |= (mcs_table[mcs].tx_phy_ctl3 << 8); 6610 } else if (is_cck_rate(rspec) && !BRCMS_ISLCNPHY(wlc->band) 6611 && !BRCMS_ISSSLPNPHY(wlc->band)) { 6612 /* 6613 * In CCK mode LPPHY overloads OFDM Modulation bits with CCK 6614 * Data Rate. Eventually MIMOPHY would also be converted to 6615 * this format 6616 */ 6617 /* 0 = 1Mbps; 1 = 2Mbps; 2 = 5.5Mbps; 3 = 11Mbps */ 6618 phyctl1 = (bw | (rspec_stf(rspec) << PHY_TXC1_MODE_SHIFT)); 6619 } else { /* legacy OFDM/CCK */ 6620 s16 phycfg; 6621 /* get the phyctl byte from rate phycfg table */ 6622 phycfg = brcms_c_rate_legacy_phyctl(rspec2rate(rspec)); 6623 if (phycfg == -1) { 6624 wiphy_err(wlc->wiphy, "phytxctl1_calc: wrong " 6625 "legacy OFDM/CCK rate\n"); 6626 phycfg = 0; 6627 } 6628 /* set the upper byte of phyctl1 */ 6629 phyctl1 = 6630 (bw | (phycfg << 8) | 6631 (rspec_stf(rspec) << PHY_TXC1_MODE_SHIFT)); 6632 } 6633 return phyctl1; 6634} 6635 6636/* 6637 * Add struct d11txh, struct cck_phy_hdr. 6638 * 6639 * 'p' data must start with 802.11 MAC header 6640 * 'p' must allow enough bytes of local headers to be "pushed" onto the packet 6641 * 6642 * headroom == D11_PHY_HDR_LEN + D11_TXH_LEN (D11_TXH_LEN is now 104 bytes) 6643 * 6644 */ 6645static u16 6646brcms_c_d11hdrs_mac80211(struct brcms_c_info *wlc, struct ieee80211_hw *hw, 6647 struct sk_buff *p, struct scb *scb, uint frag, 6648 uint nfrags, uint queue, uint next_frag_len) 6649{ 6650 struct ieee80211_hdr *h; 6651 struct d11txh *txh; 6652 u8 *plcp, plcp_fallback[D11_PHY_HDR_LEN]; 6653 int len, phylen, rts_phylen; 6654 u16 mch, phyctl, xfts, mainrates; 6655 u16 seq = 0, mcl = 0, status = 0, frameid = 0; 6656 u32 rspec[2] = { BRCM_RATE_1M, BRCM_RATE_1M }; 6657 u32 rts_rspec[2] = { BRCM_RATE_1M, BRCM_RATE_1M }; 6658 bool use_rts = false; 6659 bool use_cts = false; 6660 bool use_rifs = false; 6661 bool short_preamble[2] = { false, false }; 6662 u8 preamble_type[2] = { BRCMS_LONG_PREAMBLE, BRCMS_LONG_PREAMBLE }; 6663 u8 rts_preamble_type[2] = { BRCMS_LONG_PREAMBLE, BRCMS_LONG_PREAMBLE }; 6664 u8 *rts_plcp, rts_plcp_fallback[D11_PHY_HDR_LEN]; 6665 struct ieee80211_rts *rts = NULL; 6666 bool qos; 6667 uint ac; 6668 bool hwtkmic = false; 6669 u16 mimo_ctlchbw = PHY_TXC1_BW_20MHZ; 6670#define ANTCFG_NONE 0xFF 6671 u8 antcfg = ANTCFG_NONE; 6672 u8 fbantcfg = ANTCFG_NONE; 6673 uint phyctl1_stf = 0; 6674 u16 durid = 0; 6675 struct ieee80211_tx_rate *txrate[2]; 6676 int k; 6677 struct ieee80211_tx_info *tx_info; 6678 bool is_mcs; 6679 u16 mimo_txbw; 6680 u8 mimo_preamble_type; 6681 6682 /* locate 802.11 MAC header */ 6683 h = (struct ieee80211_hdr *)(p->data); 6684 qos = ieee80211_is_data_qos(h->frame_control); 6685 6686 /* compute length of frame in bytes for use in PLCP computations */ 6687 len = p->len; 6688 phylen = len + FCS_LEN; 6689 6690 /* Get tx_info */ 6691 tx_info = IEEE80211_SKB_CB(p); 6692 6693 /* add PLCP */ 6694 plcp = skb_push(p, D11_PHY_HDR_LEN); 6695 6696 /* add Broadcom tx descriptor header */ 6697 txh = (struct d11txh *) skb_push(p, D11_TXH_LEN); 6698 memset(txh, 0, D11_TXH_LEN); 6699 6700 /* setup frameid */ 6701 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { 6702 /* non-AP STA should never use BCMC queue */ 6703 if (queue == TX_BCMC_FIFO) { 6704 wiphy_err(wlc->wiphy, "wl%d: %s: ASSERT queue == " 6705 "TX_BCMC!\n", wlc->pub->unit, __func__); 6706 frameid = bcmc_fid_generate(wlc, NULL, txh); 6707 } else { 6708 /* Increment the counter for first fragment */ 6709 if (tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) 6710 scb->seqnum[p->priority]++; 6711 6712 /* extract fragment number from frame first */ 6713 seq = le16_to_cpu(h->seq_ctrl) & FRAGNUM_MASK; 6714 seq |= (scb->seqnum[p->priority] << SEQNUM_SHIFT); 6715 h->seq_ctrl = cpu_to_le16(seq); 6716 6717 frameid = ((seq << TXFID_SEQ_SHIFT) & TXFID_SEQ_MASK) | 6718 (queue & TXFID_QUEUE_MASK); 6719 } 6720 } 6721 frameid |= queue & TXFID_QUEUE_MASK; 6722 6723 /* set the ignpmq bit for all pkts tx'd in PS mode and for beacons */ 6724 if (ieee80211_is_beacon(h->frame_control)) 6725 mcl |= TXC_IGNOREPMQ; 6726 6727 txrate[0] = tx_info->control.rates; 6728 txrate[1] = txrate[0] + 1; 6729 6730 /* 6731 * if rate control algorithm didn't give us a fallback 6732 * rate, use the primary rate 6733 */ 6734 if (txrate[1]->idx < 0) 6735 txrate[1] = txrate[0]; 6736 6737 for (k = 0; k < hw->max_rates; k++) { 6738 is_mcs = txrate[k]->flags & IEEE80211_TX_RC_MCS ? true : false; 6739 if (!is_mcs) { 6740 if ((txrate[k]->idx >= 0) 6741 && (txrate[k]->idx < 6742 hw->wiphy->bands[tx_info->band]->n_bitrates)) { 6743 rspec[k] = 6744 hw->wiphy->bands[tx_info->band]-> 6745 bitrates[txrate[k]->idx].hw_value; 6746 short_preamble[k] = 6747 txrate[k]-> 6748 flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE ? 6749 true : false; 6750 } else { 6751 rspec[k] = BRCM_RATE_1M; 6752 } 6753 } else { 6754 rspec[k] = mac80211_wlc_set_nrate(wlc, wlc->band, 6755 NRATE_MCS_INUSE | txrate[k]->idx); 6756 } 6757 6758 /* 6759 * Currently only support same setting for primay and 6760 * fallback rates. Unify flags for each rate into a 6761 * single value for the frame 6762 */ 6763 use_rts |= 6764 txrate[k]-> 6765 flags & IEEE80211_TX_RC_USE_RTS_CTS ? true : false; 6766 use_cts |= 6767 txrate[k]-> 6768 flags & IEEE80211_TX_RC_USE_CTS_PROTECT ? true : false; 6769 6770 6771 /* 6772 * (1) RATE: 6773 * determine and validate primary rate 6774 * and fallback rates 6775 */ 6776 if (!rspec_active(rspec[k])) { 6777 rspec[k] = BRCM_RATE_1M; 6778 } else { 6779 if (!is_multicast_ether_addr(h->addr1)) { 6780 /* set tx antenna config */ 6781 brcms_c_antsel_antcfg_get(wlc->asi, false, 6782 false, 0, 0, &antcfg, &fbantcfg); 6783 } 6784 } 6785 } 6786 6787 phyctl1_stf = wlc->stf->ss_opmode; 6788 6789 if (wlc->pub->_n_enab & SUPPORT_11N) { 6790 for (k = 0; k < hw->max_rates; k++) { 6791 /* 6792 * apply siso/cdd to single stream mcs's or ofdm 6793 * if rspec is auto selected 6794 */ 6795 if (((is_mcs_rate(rspec[k]) && 6796 is_single_stream(rspec[k] & RSPEC_RATE_MASK)) || 6797 is_ofdm_rate(rspec[k])) 6798 && ((rspec[k] & RSPEC_OVERRIDE_MCS_ONLY) 6799 || !(rspec[k] & RSPEC_OVERRIDE))) { 6800 rspec[k] &= ~(RSPEC_STF_MASK | RSPEC_STC_MASK); 6801 6802 /* For SISO MCS use STBC if possible */ 6803 if (is_mcs_rate(rspec[k]) 6804 && BRCMS_STF_SS_STBC_TX(wlc, scb)) { 6805 u8 stc; 6806 6807 /* Nss for single stream is always 1 */ 6808 stc = 1; 6809 rspec[k] |= (PHY_TXC1_MODE_STBC << 6810 RSPEC_STF_SHIFT) | 6811 (stc << RSPEC_STC_SHIFT); 6812 } else 6813 rspec[k] |= 6814 (phyctl1_stf << RSPEC_STF_SHIFT); 6815 } 6816 6817 /* 6818 * Is the phy configured to use 40MHZ frames? If 6819 * so then pick the desired txbw 6820 */ 6821 if (brcms_chspec_bw(wlc->chanspec) == BRCMS_40_MHZ) { 6822 /* default txbw is 20in40 SB */ 6823 mimo_ctlchbw = mimo_txbw = 6824 CHSPEC_SB_UPPER(wlc_phy_chanspec_get( 6825 wlc->band->pi)) 6826 ? PHY_TXC1_BW_20MHZ_UP : PHY_TXC1_BW_20MHZ; 6827 6828 if (is_mcs_rate(rspec[k])) { 6829 /* mcs 32 must be 40b/w DUP */ 6830 if ((rspec[k] & RSPEC_RATE_MASK) 6831 == 32) { 6832 mimo_txbw = 6833 PHY_TXC1_BW_40MHZ_DUP; 6834 /* use override */ 6835 } else if (wlc->mimo_40txbw != AUTO) 6836 mimo_txbw = wlc->mimo_40txbw; 6837 /* else check if dst is using 40 Mhz */ 6838 else if (scb->flags & SCB_IS40) 6839 mimo_txbw = PHY_TXC1_BW_40MHZ; 6840 } else if (is_ofdm_rate(rspec[k])) { 6841 if (wlc->ofdm_40txbw != AUTO) 6842 mimo_txbw = wlc->ofdm_40txbw; 6843 } else if (wlc->cck_40txbw != AUTO) { 6844 mimo_txbw = wlc->cck_40txbw; 6845 } 6846 } else { 6847 /* 6848 * mcs32 is 40 b/w only. 6849 * This is possible for probe packets on 6850 * a STA during SCAN 6851 */ 6852 if ((rspec[k] & RSPEC_RATE_MASK) == 32) 6853 /* mcs 0 */ 6854 rspec[k] = RSPEC_MIMORATE; 6855 6856 mimo_txbw = PHY_TXC1_BW_20MHZ; 6857 } 6858 6859 /* Set channel width */ 6860 rspec[k] &= ~RSPEC_BW_MASK; 6861 if ((k == 0) || ((k > 0) && is_mcs_rate(rspec[k]))) 6862 rspec[k] |= (mimo_txbw << RSPEC_BW_SHIFT); 6863 else 6864 rspec[k] |= (mimo_ctlchbw << RSPEC_BW_SHIFT); 6865 6866 /* Disable short GI, not supported yet */ 6867 rspec[k] &= ~RSPEC_SHORT_GI; 6868 6869 mimo_preamble_type = BRCMS_MM_PREAMBLE; 6870 if (txrate[k]->flags & IEEE80211_TX_RC_GREEN_FIELD) 6871 mimo_preamble_type = BRCMS_GF_PREAMBLE; 6872 6873 if ((txrate[k]->flags & IEEE80211_TX_RC_MCS) 6874 && (!is_mcs_rate(rspec[k]))) { 6875 wiphy_err(wlc->wiphy, "wl%d: %s: IEEE80211_TX_" 6876 "RC_MCS != is_mcs_rate(rspec)\n", 6877 wlc->pub->unit, __func__); 6878 } 6879 6880 if (is_mcs_rate(rspec[k])) { 6881 preamble_type[k] = mimo_preamble_type; 6882 6883 /* 6884 * if SGI is selected, then forced mm 6885 * for single stream 6886 */ 6887 if ((rspec[k] & RSPEC_SHORT_GI) 6888 && is_single_stream(rspec[k] & 6889 RSPEC_RATE_MASK)) 6890 preamble_type[k] = BRCMS_MM_PREAMBLE; 6891 } 6892 6893 /* should be better conditionalized */ 6894 if (!is_mcs_rate(rspec[0]) 6895 && (tx_info->control.rates[0]. 6896 flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)) 6897 preamble_type[k] = BRCMS_SHORT_PREAMBLE; 6898 } 6899 } else { 6900 for (k = 0; k < hw->max_rates; k++) { 6901 /* Set ctrlchbw as 20Mhz */ 6902 rspec[k] &= ~RSPEC_BW_MASK; 6903 rspec[k] |= (PHY_TXC1_BW_20MHZ << RSPEC_BW_SHIFT); 6904 6905 /* for nphy, stf of ofdm frames must follow policies */ 6906 if (BRCMS_ISNPHY(wlc->band) && is_ofdm_rate(rspec[k])) { 6907 rspec[k] &= ~RSPEC_STF_MASK; 6908 rspec[k] |= phyctl1_stf << RSPEC_STF_SHIFT; 6909 } 6910 } 6911 } 6912 6913 /* Reset these for use with AMPDU's */ 6914 txrate[0]->count = 0; 6915 txrate[1]->count = 0; 6916 6917 /* (2) PROTECTION, may change rspec */ 6918 if ((ieee80211_is_data(h->frame_control) || 6919 ieee80211_is_mgmt(h->frame_control)) && 6920 (phylen > wlc->RTSThresh) && !is_multicast_ether_addr(h->addr1)) 6921 use_rts = true; 6922 6923 /* (3) PLCP: determine PLCP header and MAC duration, 6924 * fill struct d11txh */ 6925 brcms_c_compute_plcp(wlc, rspec[0], phylen, plcp); 6926 brcms_c_compute_plcp(wlc, rspec[1], phylen, plcp_fallback); 6927 memcpy(&txh->FragPLCPFallback, 6928 plcp_fallback, sizeof(txh->FragPLCPFallback)); 6929 6930 /* Length field now put in CCK FBR CRC field */ 6931 if (is_cck_rate(rspec[1])) { 6932 txh->FragPLCPFallback[4] = phylen & 0xff; 6933 txh->FragPLCPFallback[5] = (phylen & 0xff00) >> 8; 6934 } 6935 6936 /* MIMO-RATE: need validation ?? */ 6937 mainrates = is_ofdm_rate(rspec[0]) ? 6938 D11A_PHY_HDR_GRATE((struct ofdm_phy_hdr *) plcp) : 6939 plcp[0]; 6940 6941 /* DUR field for main rate */ 6942 if (!ieee80211_is_pspoll(h->frame_control) && 6943 !is_multicast_ether_addr(h->addr1) && !use_rifs) { 6944 durid = 6945 brcms_c_compute_frame_dur(wlc, rspec[0], preamble_type[0], 6946 next_frag_len); 6947 h->duration_id = cpu_to_le16(durid); 6948 } else if (use_rifs) { 6949 /* NAV protect to end of next max packet size */ 6950 durid = 6951 (u16) brcms_c_calc_frame_time(wlc, rspec[0], 6952 preamble_type[0], 6953 DOT11_MAX_FRAG_LEN); 6954 durid += RIFS_11N_TIME; 6955 h->duration_id = cpu_to_le16(durid); 6956 } 6957 6958 /* DUR field for fallback rate */ 6959 if (ieee80211_is_pspoll(h->frame_control)) 6960 txh->FragDurFallback = h->duration_id; 6961 else if (is_multicast_ether_addr(h->addr1) || use_rifs) 6962 txh->FragDurFallback = 0; 6963 else { 6964 durid = brcms_c_compute_frame_dur(wlc, rspec[1], 6965 preamble_type[1], next_frag_len); 6966 txh->FragDurFallback = cpu_to_le16(durid); 6967 } 6968 6969 /* (4) MAC-HDR: MacTxControlLow */ 6970 if (frag == 0) 6971 mcl |= TXC_STARTMSDU; 6972 6973 if (!is_multicast_ether_addr(h->addr1)) 6974 mcl |= TXC_IMMEDACK; 6975 6976 if (wlc->band->bandtype == BRCM_BAND_5G) 6977 mcl |= TXC_FREQBAND_5G; 6978 6979 if (CHSPEC_IS40(wlc_phy_chanspec_get(wlc->band->pi))) 6980 mcl |= TXC_BW_40; 6981 6982 /* set AMIC bit if using hardware TKIP MIC */ 6983 if (hwtkmic) 6984 mcl |= TXC_AMIC; 6985 6986 txh->MacTxControlLow = cpu_to_le16(mcl); 6987 6988 /* MacTxControlHigh */ 6989 mch = 0; 6990 6991 /* Set fallback rate preamble type */ 6992 if ((preamble_type[1] == BRCMS_SHORT_PREAMBLE) || 6993 (preamble_type[1] == BRCMS_GF_PREAMBLE)) { 6994 if (rspec2rate(rspec[1]) != BRCM_RATE_1M) 6995 mch |= TXC_PREAMBLE_DATA_FB_SHORT; 6996 } 6997 6998 /* MacFrameControl */ 6999 memcpy(&txh->MacFrameControl, &h->frame_control, sizeof(u16)); 7000 txh->TxFesTimeNormal = cpu_to_le16(0); 7001 7002 txh->TxFesTimeFallback = cpu_to_le16(0); 7003 7004 /* TxFrameRA */ 7005 memcpy(&txh->TxFrameRA, &h->addr1, ETH_ALEN); 7006 7007 /* TxFrameID */ 7008 txh->TxFrameID = cpu_to_le16(frameid); 7009 7010 /* 7011 * TxStatus, Note the case of recreating the first frag of a suppressed 7012 * frame then we may need to reset the retry cnt's via the status reg 7013 */ 7014 txh->TxStatus = cpu_to_le16(status); 7015 7016 /* 7017 * extra fields for ucode AMPDU aggregation, the new fields are added to 7018 * the END of previous structure so that it's compatible in driver. 7019 */ 7020 txh->MaxNMpdus = cpu_to_le16(0); 7021 txh->MaxABytes_MRT = cpu_to_le16(0); 7022 txh->MaxABytes_FBR = cpu_to_le16(0); 7023 txh->MinMBytes = cpu_to_le16(0); 7024 7025 /* (5) RTS/CTS: determine RTS/CTS PLCP header and MAC duration, 7026 * furnish struct d11txh */ 7027 /* RTS PLCP header and RTS frame */ 7028 if (use_rts || use_cts) { 7029 if (use_rts && use_cts) 7030 use_cts = false; 7031 7032 for (k = 0; k < 2; k++) { 7033 rts_rspec[k] = brcms_c_rspec_to_rts_rspec(wlc, rspec[k], 7034 false, 7035 mimo_ctlchbw); 7036 } 7037 7038 if (!is_ofdm_rate(rts_rspec[0]) && 7039 !((rspec2rate(rts_rspec[0]) == BRCM_RATE_1M) || 7040 (wlc->PLCPHdr_override == BRCMS_PLCP_LONG))) { 7041 rts_preamble_type[0] = BRCMS_SHORT_PREAMBLE; 7042 mch |= TXC_PREAMBLE_RTS_MAIN_SHORT; 7043 } 7044 7045 if (!is_ofdm_rate(rts_rspec[1]) && 7046 !((rspec2rate(rts_rspec[1]) == BRCM_RATE_1M) || 7047 (wlc->PLCPHdr_override == BRCMS_PLCP_LONG))) { 7048 rts_preamble_type[1] = BRCMS_SHORT_PREAMBLE; 7049 mch |= TXC_PREAMBLE_RTS_FB_SHORT; 7050 } 7051 7052 /* RTS/CTS additions to MacTxControlLow */ 7053 if (use_cts) { 7054 txh->MacTxControlLow |= cpu_to_le16(TXC_SENDCTS); 7055 } else { 7056 txh->MacTxControlLow |= cpu_to_le16(TXC_SENDRTS); 7057 txh->MacTxControlLow |= cpu_to_le16(TXC_LONGFRAME); 7058 } 7059 7060 /* RTS PLCP header */ 7061 rts_plcp = txh->RTSPhyHeader; 7062 if (use_cts) 7063 rts_phylen = DOT11_CTS_LEN + FCS_LEN; 7064 else 7065 rts_phylen = DOT11_RTS_LEN + FCS_LEN; 7066 7067 brcms_c_compute_plcp(wlc, rts_rspec[0], rts_phylen, rts_plcp); 7068 7069 /* fallback rate version of RTS PLCP header */ 7070 brcms_c_compute_plcp(wlc, rts_rspec[1], rts_phylen, 7071 rts_plcp_fallback); 7072 memcpy(&txh->RTSPLCPFallback, rts_plcp_fallback, 7073 sizeof(txh->RTSPLCPFallback)); 7074 7075 /* RTS frame fields... */ 7076 rts = (struct ieee80211_rts *)&txh->rts_frame; 7077 7078 durid = brcms_c_compute_rtscts_dur(wlc, use_cts, rts_rspec[0], 7079 rspec[0], rts_preamble_type[0], 7080 preamble_type[0], phylen, false); 7081 rts->duration = cpu_to_le16(durid); 7082 /* fallback rate version of RTS DUR field */ 7083 durid = brcms_c_compute_rtscts_dur(wlc, use_cts, 7084 rts_rspec[1], rspec[1], 7085 rts_preamble_type[1], 7086 preamble_type[1], phylen, false); 7087 txh->RTSDurFallback = cpu_to_le16(durid); 7088 7089 if (use_cts) { 7090 rts->frame_control = cpu_to_le16(IEEE80211_FTYPE_CTL | 7091 IEEE80211_STYPE_CTS); 7092 7093 memcpy(&rts->ra, &h->addr2, ETH_ALEN); 7094 } else { 7095 rts->frame_control = cpu_to_le16(IEEE80211_FTYPE_CTL | 7096 IEEE80211_STYPE_RTS); 7097 7098 memcpy(&rts->ra, &h->addr1, 2 * ETH_ALEN); 7099 } 7100 7101 /* mainrate 7102 * low 8 bits: main frag rate/mcs, 7103 * high 8 bits: rts/cts rate/mcs 7104 */ 7105 mainrates |= (is_ofdm_rate(rts_rspec[0]) ? 7106 D11A_PHY_HDR_GRATE( 7107 (struct ofdm_phy_hdr *) rts_plcp) : 7108 rts_plcp[0]) << 8; 7109 } else { 7110 memset((char *)txh->RTSPhyHeader, 0, D11_PHY_HDR_LEN); 7111 memset((char *)&txh->rts_frame, 0, 7112 sizeof(struct ieee80211_rts)); 7113 memset((char *)txh->RTSPLCPFallback, 0, 7114 sizeof(txh->RTSPLCPFallback)); 7115 txh->RTSDurFallback = 0; 7116 } 7117 7118#ifdef SUPPORT_40MHZ 7119 /* add null delimiter count */ 7120 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && is_mcs_rate(rspec)) 7121 txh->RTSPLCPFallback[AMPDU_FBR_NULL_DELIM] = 7122 brcm_c_ampdu_null_delim_cnt(wlc->ampdu, scb, rspec, phylen); 7123 7124#endif 7125 7126 /* 7127 * Now that RTS/RTS FB preamble types are updated, write 7128 * the final value 7129 */ 7130 txh->MacTxControlHigh = cpu_to_le16(mch); 7131 7132 /* 7133 * MainRates (both the rts and frag plcp rates have 7134 * been calculated now) 7135 */ 7136 txh->MainRates = cpu_to_le16(mainrates); 7137 7138 /* XtraFrameTypes */ 7139 xfts = frametype(rspec[1], wlc->mimoft); 7140 xfts |= (frametype(rts_rspec[0], wlc->mimoft) << XFTS_RTS_FT_SHIFT); 7141 xfts |= (frametype(rts_rspec[1], wlc->mimoft) << XFTS_FBRRTS_FT_SHIFT); 7142 xfts |= CHSPEC_CHANNEL(wlc_phy_chanspec_get(wlc->band->pi)) << 7143 XFTS_CHANNEL_SHIFT; 7144 txh->XtraFrameTypes = cpu_to_le16(xfts); 7145 7146 /* PhyTxControlWord */ 7147 phyctl = frametype(rspec[0], wlc->mimoft); 7148 if ((preamble_type[0] == BRCMS_SHORT_PREAMBLE) || 7149 (preamble_type[0] == BRCMS_GF_PREAMBLE)) { 7150 if (rspec2rate(rspec[0]) != BRCM_RATE_1M) 7151 phyctl |= PHY_TXC_SHORT_HDR; 7152 } 7153 7154 /* phytxant is properly bit shifted */ 7155 phyctl |= brcms_c_stf_d11hdrs_phyctl_txant(wlc, rspec[0]); 7156 txh->PhyTxControlWord = cpu_to_le16(phyctl); 7157 7158 /* PhyTxControlWord_1 */ 7159 if (BRCMS_PHY_11N_CAP(wlc->band)) { 7160 u16 phyctl1 = 0; 7161 7162 phyctl1 = brcms_c_phytxctl1_calc(wlc, rspec[0]); 7163 txh->PhyTxControlWord_1 = cpu_to_le16(phyctl1); 7164 phyctl1 = brcms_c_phytxctl1_calc(wlc, rspec[1]); 7165 txh->PhyTxControlWord_1_Fbr = cpu_to_le16(phyctl1); 7166 7167 if (use_rts || use_cts) { 7168 phyctl1 = brcms_c_phytxctl1_calc(wlc, rts_rspec[0]); 7169 txh->PhyTxControlWord_1_Rts = cpu_to_le16(phyctl1); 7170 phyctl1 = brcms_c_phytxctl1_calc(wlc, rts_rspec[1]); 7171 txh->PhyTxControlWord_1_FbrRts = cpu_to_le16(phyctl1); 7172 } 7173 7174 /* 7175 * For mcs frames, if mixedmode(overloaded with long preamble) 7176 * is going to be set, fill in non-zero MModeLen and/or 7177 * MModeFbrLen it will be unnecessary if they are separated 7178 */ 7179 if (is_mcs_rate(rspec[0]) && 7180 (preamble_type[0] == BRCMS_MM_PREAMBLE)) { 7181 u16 mmodelen = 7182 brcms_c_calc_lsig_len(wlc, rspec[0], phylen); 7183 txh->MModeLen = cpu_to_le16(mmodelen); 7184 } 7185 7186 if (is_mcs_rate(rspec[1]) && 7187 (preamble_type[1] == BRCMS_MM_PREAMBLE)) { 7188 u16 mmodefbrlen = 7189 brcms_c_calc_lsig_len(wlc, rspec[1], phylen); 7190 txh->MModeFbrLen = cpu_to_le16(mmodefbrlen); 7191 } 7192 } 7193 7194 ac = skb_get_queue_mapping(p); 7195 if ((scb->flags & SCB_WMECAP) && qos && wlc->edcf_txop[ac]) { 7196 uint frag_dur, dur, dur_fallback; 7197 7198 /* WME: Update TXOP threshold */ 7199 if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU) && frag == 0) { 7200 frag_dur = 7201 brcms_c_calc_frame_time(wlc, rspec[0], 7202 preamble_type[0], phylen); 7203 7204 if (rts) { 7205 /* 1 RTS or CTS-to-self frame */ 7206 dur = 7207 brcms_c_calc_cts_time(wlc, rts_rspec[0], 7208 rts_preamble_type[0]); 7209 dur_fallback = 7210 brcms_c_calc_cts_time(wlc, rts_rspec[1], 7211 rts_preamble_type[1]); 7212 /* (SIFS + CTS) + SIFS + frame + SIFS + ACK */ 7213 dur += le16_to_cpu(rts->duration); 7214 dur_fallback += 7215 le16_to_cpu(txh->RTSDurFallback); 7216 } else if (use_rifs) { 7217 dur = frag_dur; 7218 dur_fallback = 0; 7219 } else { 7220 /* frame + SIFS + ACK */ 7221 dur = frag_dur; 7222 dur += 7223 brcms_c_compute_frame_dur(wlc, rspec[0], 7224 preamble_type[0], 0); 7225 7226 dur_fallback = 7227 brcms_c_calc_frame_time(wlc, rspec[1], 7228 preamble_type[1], 7229 phylen); 7230 dur_fallback += 7231 brcms_c_compute_frame_dur(wlc, rspec[1], 7232 preamble_type[1], 0); 7233 } 7234 /* NEED to set TxFesTimeNormal (hard) */ 7235 txh->TxFesTimeNormal = cpu_to_le16((u16) dur); 7236 /* 7237 * NEED to set fallback rate version of 7238 * TxFesTimeNormal (hard) 7239 */ 7240 txh->TxFesTimeFallback = 7241 cpu_to_le16((u16) dur_fallback); 7242 7243 /* 7244 * update txop byte threshold (txop minus intraframe 7245 * overhead) 7246 */ 7247 if (wlc->edcf_txop[ac] >= (dur - frag_dur)) { 7248 uint newfragthresh; 7249 7250 newfragthresh = 7251 brcms_c_calc_frame_len(wlc, 7252 rspec[0], preamble_type[0], 7253 (wlc->edcf_txop[ac] - 7254 (dur - frag_dur))); 7255 /* range bound the fragthreshold */ 7256 if (newfragthresh < DOT11_MIN_FRAG_LEN) 7257 newfragthresh = 7258 DOT11_MIN_FRAG_LEN; 7259 else if (newfragthresh > 7260 wlc->usr_fragthresh) 7261 newfragthresh = 7262 wlc->usr_fragthresh; 7263 /* update the fragthresh and do txc update */ 7264 if (wlc->fragthresh[queue] != 7265 (u16) newfragthresh) 7266 wlc->fragthresh[queue] = 7267 (u16) newfragthresh; 7268 } else { 7269 wiphy_err(wlc->wiphy, "wl%d: %s txop invalid " 7270 "for rate %d\n", 7271 wlc->pub->unit, fifo_names[queue], 7272 rspec2rate(rspec[0])); 7273 } 7274 7275 if (dur > wlc->edcf_txop[ac]) 7276 wiphy_err(wlc->wiphy, "wl%d: %s: %s txop " 7277 "exceeded phylen %d/%d dur %d/%d\n", 7278 wlc->pub->unit, __func__, 7279 fifo_names[queue], 7280 phylen, wlc->fragthresh[queue], 7281 dur, wlc->edcf_txop[ac]); 7282 } 7283 } 7284 7285 return 0; 7286} 7287 7288void brcms_c_sendpkt_mac80211(struct brcms_c_info *wlc, struct sk_buff *sdu, 7289 struct ieee80211_hw *hw) 7290{ 7291 u8 prio; 7292 uint fifo; 7293 struct scb *scb = &wlc->pri_scb; 7294 struct ieee80211_hdr *d11_header = (struct ieee80211_hdr *)(sdu->data); 7295 7296 /* 7297 * 802.11 standard requires management traffic 7298 * to go at highest priority 7299 */ 7300 prio = ieee80211_is_data(d11_header->frame_control) ? sdu->priority : 7301 MAXPRIO; 7302 fifo = prio2fifo[prio]; 7303 if (brcms_c_d11hdrs_mac80211(wlc, hw, sdu, scb, 0, 1, fifo, 0)) 7304 return; 7305 brcms_c_txq_enq(wlc, scb, sdu, BRCMS_PRIO_TO_PREC(prio)); 7306 brcms_c_send_q(wlc); 7307} 7308 7309void brcms_c_send_q(struct brcms_c_info *wlc) 7310{ 7311 struct sk_buff *pkt[DOT11_MAXNUMFRAGS]; 7312 int prec; 7313 u16 prec_map; 7314 int err = 0, i, count; 7315 uint fifo; 7316 struct brcms_txq_info *qi = wlc->pkt_queue; 7317 struct pktq *q = &qi->q; 7318 struct ieee80211_tx_info *tx_info; 7319 7320 prec_map = wlc->tx_prec_map; 7321 7322 /* Send all the enq'd pkts that we can. 7323 * Dequeue packets with precedence with empty HW fifo only 7324 */ 7325 while (prec_map && (pkt[0] = brcmu_pktq_mdeq(q, prec_map, &prec))) { 7326 tx_info = IEEE80211_SKB_CB(pkt[0]); 7327 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) { 7328 err = brcms_c_sendampdu(wlc->ampdu, qi, pkt, prec); 7329 } else { 7330 count = 1; 7331 err = brcms_c_prep_pdu(wlc, pkt[0], &fifo); 7332 if (!err) { 7333 for (i = 0; i < count; i++) 7334 brcms_c_txfifo(wlc, fifo, pkt[i], true, 7335 1); 7336 } 7337 } 7338 7339 if (err == -EBUSY) { 7340 brcmu_pktq_penq_head(q, prec, pkt[0]); 7341 /* 7342 * If send failed due to any other reason than a 7343 * change in HW FIFO condition, quit. Otherwise, 7344 * read the new prec_map! 7345 */ 7346 if (prec_map == wlc->tx_prec_map) 7347 break; 7348 prec_map = wlc->tx_prec_map; 7349 } 7350 } 7351} 7352 7353void 7354brcms_c_txfifo(struct brcms_c_info *wlc, uint fifo, struct sk_buff *p, 7355 bool commit, s8 txpktpend) 7356{ 7357 u16 frameid = INVALIDFID; 7358 struct d11txh *txh; 7359 7360 txh = (struct d11txh *) (p->data); 7361 7362 /* When a BC/MC frame is being committed to the BCMC fifo 7363 * via DMA (NOT PIO), update ucode or BSS info as appropriate. 7364 */ 7365 if (fifo == TX_BCMC_FIFO) 7366 frameid = le16_to_cpu(txh->TxFrameID); 7367 7368 /* 7369 * Bump up pending count for if not using rpc. If rpc is 7370 * used, this will be handled in brcms_b_txfifo() 7371 */ 7372 if (commit) { 7373 wlc->core->txpktpend[fifo] += txpktpend; 7374 BCMMSG(wlc->wiphy, "pktpend inc %d to %d\n", 7375 txpktpend, wlc->core->txpktpend[fifo]); 7376 } 7377 7378 /* Commit BCMC sequence number in the SHM frame ID location */ 7379 if (frameid != INVALIDFID) { 7380 /* 7381 * To inform the ucode of the last mcast frame posted 7382 * so that it can clear moredata bit 7383 */ 7384 brcms_b_write_shm(wlc->hw, M_BCMC_FID, frameid); 7385 } 7386 7387 if (dma_txfast(wlc->hw->di[fifo], p, commit) < 0) 7388 wiphy_err(wlc->wiphy, "txfifo: fatal, toss frames !!!\n"); 7389} 7390 7391u32 7392brcms_c_rspec_to_rts_rspec(struct brcms_c_info *wlc, u32 rspec, 7393 bool use_rspec, u16 mimo_ctlchbw) 7394{ 7395 u32 rts_rspec = 0; 7396 7397 if (use_rspec) 7398 /* use frame rate as rts rate */ 7399 rts_rspec = rspec; 7400 else if (wlc->band->gmode && wlc->protection->_g && !is_cck_rate(rspec)) 7401 /* Use 11Mbps as the g protection RTS target rate and fallback. 7402 * Use the brcms_basic_rate() lookup to find the best basic rate 7403 * under the target in case 11 Mbps is not Basic. 7404 * 6 and 9 Mbps are not usually selected by rate selection, but 7405 * even if the OFDM rate we are protecting is 6 or 9 Mbps, 11 7406 * is more robust. 7407 */ 7408 rts_rspec = brcms_basic_rate(wlc, BRCM_RATE_11M); 7409 else 7410 /* calculate RTS rate and fallback rate based on the frame rate 7411 * RTS must be sent at a basic rate since it is a 7412 * control frame, sec 9.6 of 802.11 spec 7413 */ 7414 rts_rspec = brcms_basic_rate(wlc, rspec); 7415 7416 if (BRCMS_PHY_11N_CAP(wlc->band)) { 7417 /* set rts txbw to correct side band */ 7418 rts_rspec &= ~RSPEC_BW_MASK; 7419 7420 /* 7421 * if rspec/rspec_fallback is 40MHz, then send RTS on both 7422 * 20MHz channel (DUP), otherwise send RTS on control channel 7423 */ 7424 if (rspec_is40mhz(rspec) && !is_cck_rate(rts_rspec)) 7425 rts_rspec |= (PHY_TXC1_BW_40MHZ_DUP << RSPEC_BW_SHIFT); 7426 else 7427 rts_rspec |= (mimo_ctlchbw << RSPEC_BW_SHIFT); 7428 7429 /* pick siso/cdd as default for ofdm */ 7430 if (is_ofdm_rate(rts_rspec)) { 7431 rts_rspec &= ~RSPEC_STF_MASK; 7432 rts_rspec |= (wlc->stf->ss_opmode << RSPEC_STF_SHIFT); 7433 } 7434 } 7435 return rts_rspec; 7436} 7437 7438void 7439brcms_c_txfifo_complete(struct brcms_c_info *wlc, uint fifo, s8 txpktpend) 7440{ 7441 wlc->core->txpktpend[fifo] -= txpktpend; 7442 BCMMSG(wlc->wiphy, "pktpend dec %d to %d\n", txpktpend, 7443 wlc->core->txpktpend[fifo]); 7444 7445 /* There is more room; mark precedences related to this FIFO sendable */ 7446 wlc->tx_prec_map |= wlc->fifo2prec_map[fifo]; 7447 7448 /* figure out which bsscfg is being worked on... */ 7449} 7450 7451/* Update beacon listen interval in shared memory */ 7452static void brcms_c_bcn_li_upd(struct brcms_c_info *wlc) 7453{ 7454 /* wake up every DTIM is the default */ 7455 if (wlc->bcn_li_dtim == 1) 7456 brcms_b_write_shm(wlc->hw, M_BCN_LI, 0); 7457 else 7458 brcms_b_write_shm(wlc->hw, M_BCN_LI, 7459 (wlc->bcn_li_dtim << 8) | wlc->bcn_li_bcn); 7460} 7461 7462static void 7463brcms_b_read_tsf(struct brcms_hardware *wlc_hw, u32 *tsf_l_ptr, 7464 u32 *tsf_h_ptr) 7465{ 7466 struct bcma_device *core = wlc_hw->d11core; 7467 7468 /* read the tsf timer low, then high to get an atomic read */ 7469 *tsf_l_ptr = bcma_read32(core, D11REGOFFS(tsf_timerlow)); 7470 *tsf_h_ptr = bcma_read32(core, D11REGOFFS(tsf_timerhigh)); 7471} 7472 7473/* 7474 * recover 64bit TSF value from the 16bit TSF value in the rx header 7475 * given the assumption that the TSF passed in header is within 65ms 7476 * of the current tsf. 7477 * 7478 * 6 5 4 4 3 2 1 7479 * 3.......6.......8.......0.......2.......4.......6.......8......0 7480 * |<---------- tsf_h ----------->||<--- tsf_l -->||<-RxTSFTime ->| 7481 * 7482 * The RxTSFTime are the lowest 16 bits and provided by the ucode. The 7483 * tsf_l is filled in by brcms_b_recv, which is done earlier in the 7484 * receive call sequence after rx interrupt. Only the higher 16 bits 7485 * are used. Finally, the tsf_h is read from the tsf register. 7486 */ 7487static u64 brcms_c_recover_tsf64(struct brcms_c_info *wlc, 7488 struct d11rxhdr *rxh) 7489{ 7490 u32 tsf_h, tsf_l; 7491 u16 rx_tsf_0_15, rx_tsf_16_31; 7492 7493 brcms_b_read_tsf(wlc->hw, &tsf_l, &tsf_h); 7494 7495 rx_tsf_16_31 = (u16)(tsf_l >> 16); 7496 rx_tsf_0_15 = rxh->RxTSFTime; 7497 7498 /* 7499 * a greater tsf time indicates the low 16 bits of 7500 * tsf_l wrapped, so decrement the high 16 bits. 7501 */ 7502 if ((u16)tsf_l < rx_tsf_0_15) { 7503 rx_tsf_16_31 -= 1; 7504 if (rx_tsf_16_31 == 0xffff) 7505 tsf_h -= 1; 7506 } 7507 7508 return ((u64)tsf_h << 32) | (((u32)rx_tsf_16_31 << 16) + rx_tsf_0_15); 7509} 7510 7511static void 7512prep_mac80211_status(struct brcms_c_info *wlc, struct d11rxhdr *rxh, 7513 struct sk_buff *p, 7514 struct ieee80211_rx_status *rx_status) 7515{ 7516 int preamble; 7517 int channel; 7518 u32 rspec; 7519 unsigned char *plcp; 7520 7521 /* fill in TSF and flag its presence */ 7522 rx_status->mactime = brcms_c_recover_tsf64(wlc, rxh); 7523 rx_status->flag |= RX_FLAG_MACTIME_MPDU; 7524 7525 channel = BRCMS_CHAN_CHANNEL(rxh->RxChan); 7526 7527 if (channel > 14) { 7528 rx_status->band = IEEE80211_BAND_5GHZ; 7529 rx_status->freq = ieee80211_ofdm_chan_to_freq( 7530 WF_CHAN_FACTOR_5_G/2, channel); 7531 7532 } else { 7533 rx_status->band = IEEE80211_BAND_2GHZ; 7534 rx_status->freq = ieee80211_dsss_chan_to_freq(channel); 7535 } 7536 7537 rx_status->signal = wlc_phy_rssi_compute(wlc->hw->band->pi, rxh); 7538 7539 /* noise */ 7540 /* qual */ 7541 rx_status->antenna = 7542 (rxh->PhyRxStatus_0 & PRXS0_RXANT_UPSUBBAND) ? 1 : 0; 7543 7544 plcp = p->data; 7545 7546 rspec = brcms_c_compute_rspec(rxh, plcp); 7547 if (is_mcs_rate(rspec)) { 7548 rx_status->rate_idx = rspec & RSPEC_RATE_MASK; 7549 rx_status->flag |= RX_FLAG_HT; 7550 if (rspec_is40mhz(rspec)) 7551 rx_status->flag |= RX_FLAG_40MHZ; 7552 } else { 7553 switch (rspec2rate(rspec)) { 7554 case BRCM_RATE_1M: 7555 rx_status->rate_idx = 0; 7556 break; 7557 case BRCM_RATE_2M: 7558 rx_status->rate_idx = 1; 7559 break; 7560 case BRCM_RATE_5M5: 7561 rx_status->rate_idx = 2; 7562 break; 7563 case BRCM_RATE_11M: 7564 rx_status->rate_idx = 3; 7565 break; 7566 case BRCM_RATE_6M: 7567 rx_status->rate_idx = 4; 7568 break; 7569 case BRCM_RATE_9M: 7570 rx_status->rate_idx = 5; 7571 break; 7572 case BRCM_RATE_12M: 7573 rx_status->rate_idx = 6; 7574 break; 7575 case BRCM_RATE_18M: 7576 rx_status->rate_idx = 7; 7577 break; 7578 case BRCM_RATE_24M: 7579 rx_status->rate_idx = 8; 7580 break; 7581 case BRCM_RATE_36M: 7582 rx_status->rate_idx = 9; 7583 break; 7584 case BRCM_RATE_48M: 7585 rx_status->rate_idx = 10; 7586 break; 7587 case BRCM_RATE_54M: 7588 rx_status->rate_idx = 11; 7589 break; 7590 default: 7591 wiphy_err(wlc->wiphy, "%s: Unknown rate\n", __func__); 7592 } 7593 7594 /* 7595 * For 5GHz, we should decrease the index as it is 7596 * a subset of the 2.4G rates. See bitrates field 7597 * of brcms_band_5GHz_nphy (in mac80211_if.c). 7598 */ 7599 if (rx_status->band == IEEE80211_BAND_5GHZ) 7600 rx_status->rate_idx -= BRCMS_LEGACY_5G_RATE_OFFSET; 7601 7602 /* Determine short preamble and rate_idx */ 7603 preamble = 0; 7604 if (is_cck_rate(rspec)) { 7605 if (rxh->PhyRxStatus_0 & PRXS0_SHORTH) 7606 rx_status->flag |= RX_FLAG_SHORTPRE; 7607 } else if (is_ofdm_rate(rspec)) { 7608 rx_status->flag |= RX_FLAG_SHORTPRE; 7609 } else { 7610 wiphy_err(wlc->wiphy, "%s: Unknown modulation\n", 7611 __func__); 7612 } 7613 } 7614 7615 if (plcp3_issgi(plcp[3])) 7616 rx_status->flag |= RX_FLAG_SHORT_GI; 7617 7618 if (rxh->RxStatus1 & RXS_DECERR) { 7619 rx_status->flag |= RX_FLAG_FAILED_PLCP_CRC; 7620 wiphy_err(wlc->wiphy, "%s: RX_FLAG_FAILED_PLCP_CRC\n", 7621 __func__); 7622 } 7623 if (rxh->RxStatus1 & RXS_FCSERR) { 7624 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; 7625 wiphy_err(wlc->wiphy, "%s: RX_FLAG_FAILED_FCS_CRC\n", 7626 __func__); 7627 } 7628} 7629 7630static void 7631brcms_c_recvctl(struct brcms_c_info *wlc, struct d11rxhdr *rxh, 7632 struct sk_buff *p) 7633{ 7634 int len_mpdu; 7635 struct ieee80211_rx_status rx_status; 7636 7637 memset(&rx_status, 0, sizeof(rx_status)); 7638 prep_mac80211_status(wlc, rxh, p, &rx_status); 7639 7640 /* mac header+body length, exclude CRC and plcp header */ 7641 len_mpdu = p->len - D11_PHY_HDR_LEN - FCS_LEN; 7642 skb_pull(p, D11_PHY_HDR_LEN); 7643 __skb_trim(p, len_mpdu); 7644 7645 memcpy(IEEE80211_SKB_RXCB(p), &rx_status, sizeof(rx_status)); 7646 ieee80211_rx_irqsafe(wlc->pub->ieee_hw, p); 7647} 7648 7649/* calculate frame duration for Mixed-mode L-SIG spoofing, return 7650 * number of bytes goes in the length field 7651 * 7652 * Formula given by HT PHY Spec v 1.13 7653 * len = 3(nsyms + nstream + 3) - 3 7654 */ 7655u16 7656brcms_c_calc_lsig_len(struct brcms_c_info *wlc, u32 ratespec, 7657 uint mac_len) 7658{ 7659 uint nsyms, len = 0, kNdps; 7660 7661 BCMMSG(wlc->wiphy, "wl%d: rate %d, len%d\n", 7662 wlc->pub->unit, rspec2rate(ratespec), mac_len); 7663 7664 if (is_mcs_rate(ratespec)) { 7665 uint mcs = ratespec & RSPEC_RATE_MASK; 7666 int tot_streams = (mcs_2_txstreams(mcs) + 1) + 7667 rspec_stc(ratespec); 7668 7669 /* 7670 * the payload duration calculation matches that 7671 * of regular ofdm 7672 */ 7673 /* 1000Ndbps = kbps * 4 */ 7674 kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec), 7675 rspec_issgi(ratespec)) * 4; 7676 7677 if (rspec_stc(ratespec) == 0) 7678 nsyms = 7679 CEIL((APHY_SERVICE_NBITS + 8 * mac_len + 7680 APHY_TAIL_NBITS) * 1000, kNdps); 7681 else 7682 /* STBC needs to have even number of symbols */ 7683 nsyms = 7684 2 * 7685 CEIL((APHY_SERVICE_NBITS + 8 * mac_len + 7686 APHY_TAIL_NBITS) * 1000, 2 * kNdps); 7687 7688 /* (+3) account for HT-SIG(2) and HT-STF(1) */ 7689 nsyms += (tot_streams + 3); 7690 /* 7691 * 3 bytes/symbol @ legacy 6Mbps rate 7692 * (-3) excluding service bits and tail bits 7693 */ 7694 len = (3 * nsyms) - 3; 7695 } 7696 7697 return (u16) len; 7698} 7699 7700static void 7701brcms_c_mod_prb_rsp_rate_table(struct brcms_c_info *wlc, uint frame_len) 7702{ 7703 const struct brcms_c_rateset *rs_dflt; 7704 struct brcms_c_rateset rs; 7705 u8 rate; 7706 u16 entry_ptr; 7707 u8 plcp[D11_PHY_HDR_LEN]; 7708 u16 dur, sifs; 7709 uint i; 7710 7711 sifs = get_sifs(wlc->band); 7712 7713 rs_dflt = brcms_c_rateset_get_hwrs(wlc); 7714 7715 brcms_c_rateset_copy(rs_dflt, &rs); 7716 brcms_c_rateset_mcs_upd(&rs, wlc->stf->txstreams); 7717 7718 /* 7719 * walk the phy rate table and update MAC core SHM 7720 * basic rate table entries 7721 */ 7722 for (i = 0; i < rs.count; i++) { 7723 rate = rs.rates[i] & BRCMS_RATE_MASK; 7724 7725 entry_ptr = brcms_b_rate_shm_offset(wlc->hw, rate); 7726 7727 /* Calculate the Probe Response PLCP for the given rate */ 7728 brcms_c_compute_plcp(wlc, rate, frame_len, plcp); 7729 7730 /* 7731 * Calculate the duration of the Probe Response 7732 * frame plus SIFS for the MAC 7733 */ 7734 dur = (u16) brcms_c_calc_frame_time(wlc, rate, 7735 BRCMS_LONG_PREAMBLE, frame_len); 7736 dur += sifs; 7737 7738 /* Update the SHM Rate Table entry Probe Response values */ 7739 brcms_b_write_shm(wlc->hw, entry_ptr + M_RT_PRS_PLCP_POS, 7740 (u16) (plcp[0] + (plcp[1] << 8))); 7741 brcms_b_write_shm(wlc->hw, entry_ptr + M_RT_PRS_PLCP_POS + 2, 7742 (u16) (plcp[2] + (plcp[3] << 8))); 7743 brcms_b_write_shm(wlc->hw, entry_ptr + M_RT_PRS_DUR_POS, dur); 7744 } 7745} 7746 7747/* Max buffering needed for beacon template/prb resp template is 142 bytes. 7748 * 7749 * PLCP header is 6 bytes. 7750 * 802.11 A3 header is 24 bytes. 7751 * Max beacon frame body template length is 112 bytes. 7752 * Max probe resp frame body template length is 110 bytes. 7753 * 7754 * *len on input contains the max length of the packet available. 7755 * 7756 * The *len value is set to the number of bytes in buf used, and starts 7757 * with the PLCP and included up to, but not including, the 4 byte FCS. 7758 */ 7759static void 7760brcms_c_bcn_prb_template(struct brcms_c_info *wlc, u16 type, 7761 u32 bcn_rspec, 7762 struct brcms_bss_cfg *cfg, u16 *buf, int *len) 7763{ 7764 static const u8 ether_bcast[ETH_ALEN] = {255, 255, 255, 255, 255, 255}; 7765 struct cck_phy_hdr *plcp; 7766 struct ieee80211_mgmt *h; 7767 int hdr_len, body_len; 7768 7769 hdr_len = D11_PHY_HDR_LEN + DOT11_MAC_HDR_LEN; 7770 7771 /* calc buffer size provided for frame body */ 7772 body_len = *len - hdr_len; 7773 /* return actual size */ 7774 *len = hdr_len + body_len; 7775 7776 /* format PHY and MAC headers */ 7777 memset((char *)buf, 0, hdr_len); 7778 7779 plcp = (struct cck_phy_hdr *) buf; 7780 7781 /* 7782 * PLCP for Probe Response frames are filled in from 7783 * core's rate table 7784 */ 7785 if (type == IEEE80211_STYPE_BEACON) 7786 /* fill in PLCP */ 7787 brcms_c_compute_plcp(wlc, bcn_rspec, 7788 (DOT11_MAC_HDR_LEN + body_len + FCS_LEN), 7789 (u8 *) plcp); 7790 7791 /* "Regular" and 16 MBSS but not for 4 MBSS */ 7792 /* Update the phytxctl for the beacon based on the rspec */ 7793 brcms_c_beacon_phytxctl_txant_upd(wlc, bcn_rspec); 7794 7795 h = (struct ieee80211_mgmt *)&plcp[1]; 7796 7797 /* fill in 802.11 header */ 7798 h->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT | type); 7799 7800 /* DUR is 0 for multicast bcn, or filled in by MAC for prb resp */ 7801 /* A1 filled in by MAC for prb resp, broadcast for bcn */ 7802 if (type == IEEE80211_STYPE_BEACON) 7803 memcpy(&h->da, ðer_bcast, ETH_ALEN); 7804 memcpy(&h->sa, &cfg->cur_etheraddr, ETH_ALEN); 7805 memcpy(&h->bssid, &cfg->BSSID, ETH_ALEN); 7806 7807 /* SEQ filled in by MAC */ 7808} 7809 7810int brcms_c_get_header_len(void) 7811{ 7812 return TXOFF; 7813} 7814 7815/* 7816 * Update all beacons for the system. 7817 */ 7818void brcms_c_update_beacon(struct brcms_c_info *wlc) 7819{ 7820 struct brcms_bss_cfg *bsscfg = wlc->bsscfg; 7821 7822 if (bsscfg->up && !bsscfg->BSS) 7823 /* Clear the soft intmask */ 7824 wlc->defmacintmask &= ~MI_BCNTPL; 7825} 7826 7827/* Write ssid into shared memory */ 7828static void 7829brcms_c_shm_ssid_upd(struct brcms_c_info *wlc, struct brcms_bss_cfg *cfg) 7830{ 7831 u8 *ssidptr = cfg->SSID; 7832 u16 base = M_SSID; 7833 u8 ssidbuf[IEEE80211_MAX_SSID_LEN]; 7834 7835 /* padding the ssid with zero and copy it into shm */ 7836 memset(ssidbuf, 0, IEEE80211_MAX_SSID_LEN); 7837 memcpy(ssidbuf, ssidptr, cfg->SSID_len); 7838 7839 brcms_c_copyto_shm(wlc, base, ssidbuf, IEEE80211_MAX_SSID_LEN); 7840 brcms_b_write_shm(wlc->hw, M_SSIDLEN, (u16) cfg->SSID_len); 7841} 7842 7843static void 7844brcms_c_bss_update_probe_resp(struct brcms_c_info *wlc, 7845 struct brcms_bss_cfg *cfg, 7846 bool suspend) 7847{ 7848 u16 prb_resp[BCN_TMPL_LEN / 2]; 7849 int len = BCN_TMPL_LEN; 7850 7851 /* 7852 * write the probe response to hardware, or save in 7853 * the config structure 7854 */ 7855 7856 /* create the probe response template */ 7857 brcms_c_bcn_prb_template(wlc, IEEE80211_STYPE_PROBE_RESP, 0, 7858 cfg, prb_resp, &len); 7859 7860 if (suspend) 7861 brcms_c_suspend_mac_and_wait(wlc); 7862 7863 /* write the probe response into the template region */ 7864 brcms_b_write_template_ram(wlc->hw, T_PRS_TPL_BASE, 7865 (len + 3) & ~3, prb_resp); 7866 7867 /* write the length of the probe response frame (+PLCP/-FCS) */ 7868 brcms_b_write_shm(wlc->hw, M_PRB_RESP_FRM_LEN, (u16) len); 7869 7870 /* write the SSID and SSID length */ 7871 brcms_c_shm_ssid_upd(wlc, cfg); 7872 7873 /* 7874 * Write PLCP headers and durations for probe response frames 7875 * at all rates. Use the actual frame length covered by the 7876 * PLCP header for the call to brcms_c_mod_prb_rsp_rate_table() 7877 * by subtracting the PLCP len and adding the FCS. 7878 */ 7879 len += (-D11_PHY_HDR_LEN + FCS_LEN); 7880 brcms_c_mod_prb_rsp_rate_table(wlc, (u16) len); 7881 7882 if (suspend) 7883 brcms_c_enable_mac(wlc); 7884} 7885 7886void brcms_c_update_probe_resp(struct brcms_c_info *wlc, bool suspend) 7887{ 7888 struct brcms_bss_cfg *bsscfg = wlc->bsscfg; 7889 7890 /* update AP or IBSS probe responses */ 7891 if (bsscfg->up && !bsscfg->BSS) 7892 brcms_c_bss_update_probe_resp(wlc, bsscfg, suspend); 7893} 7894 7895/* prepares pdu for transmission. returns BCM error codes */ 7896int brcms_c_prep_pdu(struct brcms_c_info *wlc, struct sk_buff *pdu, uint *fifop) 7897{ 7898 uint fifo; 7899 struct d11txh *txh; 7900 struct ieee80211_hdr *h; 7901 struct scb *scb; 7902 7903 txh = (struct d11txh *) (pdu->data); 7904 h = (struct ieee80211_hdr *)((u8 *) (txh + 1) + D11_PHY_HDR_LEN); 7905 7906 /* get the pkt queue info. This was put at brcms_c_sendctl or 7907 * brcms_c_send for PDU */ 7908 fifo = le16_to_cpu(txh->TxFrameID) & TXFID_QUEUE_MASK; 7909 7910 scb = NULL; 7911 7912 *fifop = fifo; 7913 7914 /* return if insufficient dma resources */ 7915 if (*wlc->core->txavail[fifo] < MAX_DMA_SEGS) { 7916 /* Mark precedences related to this FIFO, unsendable */ 7917 /* A fifo is full. Clear precedences related to that FIFO */ 7918 wlc->tx_prec_map &= ~(wlc->fifo2prec_map[fifo]); 7919 return -EBUSY; 7920 } 7921 return 0; 7922} 7923 7924int brcms_b_xmtfifo_sz_get(struct brcms_hardware *wlc_hw, uint fifo, 7925 uint *blocks) 7926{ 7927 if (fifo >= NFIFO) 7928 return -EINVAL; 7929 7930 *blocks = wlc_hw->xmtfifo_sz[fifo]; 7931 7932 return 0; 7933} 7934 7935void 7936brcms_c_set_addrmatch(struct brcms_c_info *wlc, int match_reg_offset, 7937 const u8 *addr) 7938{ 7939 brcms_b_set_addrmatch(wlc->hw, match_reg_offset, addr); 7940 if (match_reg_offset == RCM_BSSID_OFFSET) 7941 memcpy(wlc->bsscfg->BSSID, addr, ETH_ALEN); 7942} 7943 7944/* 7945 * Flag 'scan in progress' to withhold dynamic phy calibration 7946 */ 7947void brcms_c_scan_start(struct brcms_c_info *wlc) 7948{ 7949 wlc_phy_hold_upd(wlc->band->pi, PHY_HOLD_FOR_SCAN, true); 7950} 7951 7952void brcms_c_scan_stop(struct brcms_c_info *wlc) 7953{ 7954 wlc_phy_hold_upd(wlc->band->pi, PHY_HOLD_FOR_SCAN, false); 7955} 7956 7957void brcms_c_associate_upd(struct brcms_c_info *wlc, bool state) 7958{ 7959 wlc->pub->associated = state; 7960 wlc->bsscfg->associated = state; 7961} 7962 7963/* 7964 * When a remote STA/AP is removed by Mac80211, or when it can no longer accept 7965 * AMPDU traffic, packets pending in hardware have to be invalidated so that 7966 * when later on hardware releases them, they can be handled appropriately. 7967 */ 7968void brcms_c_inval_dma_pkts(struct brcms_hardware *hw, 7969 struct ieee80211_sta *sta, 7970 void (*dma_callback_fn)) 7971{ 7972 struct dma_pub *dmah; 7973 int i; 7974 for (i = 0; i < NFIFO; i++) { 7975 dmah = hw->di[i]; 7976 if (dmah != NULL) 7977 dma_walk_packets(dmah, dma_callback_fn, sta); 7978 } 7979} 7980 7981int brcms_c_get_curband(struct brcms_c_info *wlc) 7982{ 7983 return wlc->band->bandunit; 7984} 7985 7986void brcms_c_wait_for_tx_completion(struct brcms_c_info *wlc, bool drop) 7987{ 7988 /* flush packet queue when requested */ 7989 if (drop) 7990 brcmu_pktq_flush(&wlc->pkt_queue->q, false, NULL, NULL); 7991 7992 /* wait for queue and DMA fifos to run dry */ 7993 while (!pktq_empty(&wlc->pkt_queue->q) || brcms_txpktpendtot(wlc) > 0) 7994 brcms_msleep(wlc->wl, 1); 7995} 7996 7997void brcms_c_set_beacon_listen_interval(struct brcms_c_info *wlc, u8 interval) 7998{ 7999 wlc->bcn_li_bcn = interval; 8000 if (wlc->pub->up) 8001 brcms_c_bcn_li_upd(wlc); 8002} 8003 8004int brcms_c_set_tx_power(struct brcms_c_info *wlc, int txpwr) 8005{ 8006 uint qdbm; 8007 8008 /* Remove override bit and clip to max qdbm value */ 8009 qdbm = min_t(uint, txpwr * BRCMS_TXPWR_DB_FACTOR, 0xff); 8010 return wlc_phy_txpower_set(wlc->band->pi, qdbm, false); 8011} 8012 8013int brcms_c_get_tx_power(struct brcms_c_info *wlc) 8014{ 8015 uint qdbm; 8016 bool override; 8017 8018 wlc_phy_txpower_get(wlc->band->pi, &qdbm, &override); 8019 8020 /* Return qdbm units */ 8021 return (int)(qdbm / BRCMS_TXPWR_DB_FACTOR); 8022} 8023 8024/* Process received frames */ 8025/* 8026 * Return true if more frames need to be processed. false otherwise. 8027 * Param 'bound' indicates max. # frames to process before break out. 8028 */ 8029static void brcms_c_recv(struct brcms_c_info *wlc, struct sk_buff *p) 8030{ 8031 struct d11rxhdr *rxh; 8032 struct ieee80211_hdr *h; 8033 uint len; 8034 bool is_amsdu; 8035 8036 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit); 8037 8038 /* frame starts with rxhdr */ 8039 rxh = (struct d11rxhdr *) (p->data); 8040 8041 /* strip off rxhdr */ 8042 skb_pull(p, BRCMS_HWRXOFF); 8043 8044 /* MAC inserts 2 pad bytes for a4 headers or QoS or A-MSDU subframes */ 8045 if (rxh->RxStatus1 & RXS_PBPRES) { 8046 if (p->len < 2) { 8047 wiphy_err(wlc->wiphy, "wl%d: recv: rcvd runt of " 8048 "len %d\n", wlc->pub->unit, p->len); 8049 goto toss; 8050 } 8051 skb_pull(p, 2); 8052 } 8053 8054 h = (struct ieee80211_hdr *)(p->data + D11_PHY_HDR_LEN); 8055 len = p->len; 8056 8057 if (rxh->RxStatus1 & RXS_FCSERR) { 8058 if (!(wlc->filter_flags & FIF_FCSFAIL)) 8059 goto toss; 8060 } 8061 8062 /* check received pkt has at least frame control field */ 8063 if (len < D11_PHY_HDR_LEN + sizeof(h->frame_control)) 8064 goto toss; 8065 8066 /* not supporting A-MSDU */ 8067 is_amsdu = rxh->RxStatus2 & RXS_AMSDU_MASK; 8068 if (is_amsdu) 8069 goto toss; 8070 8071 brcms_c_recvctl(wlc, rxh, p); 8072 return; 8073 8074 toss: 8075 brcmu_pkt_buf_free_skb(p); 8076} 8077 8078/* Process received frames */ 8079/* 8080 * Return true if more frames need to be processed. false otherwise. 8081 * Param 'bound' indicates max. # frames to process before break out. 8082 */ 8083static bool 8084brcms_b_recv(struct brcms_hardware *wlc_hw, uint fifo, bool bound) 8085{ 8086 struct sk_buff *p; 8087 struct sk_buff *next = NULL; 8088 struct sk_buff_head recv_frames; 8089 8090 uint n = 0; 8091 uint bound_limit = bound ? RXBND : -1; 8092 8093 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit); 8094 skb_queue_head_init(&recv_frames); 8095 8096 /* gather received frames */ 8097 while (dma_rx(wlc_hw->di[fifo], &recv_frames)) { 8098 8099 /* !give others some time to run! */ 8100 if (++n >= bound_limit) 8101 break; 8102 } 8103 8104 /* post more rbufs */ 8105 dma_rxfill(wlc_hw->di[fifo]); 8106 8107 /* process each frame */ 8108 skb_queue_walk_safe(&recv_frames, p, next) { 8109 struct d11rxhdr_le *rxh_le; 8110 struct d11rxhdr *rxh; 8111 8112 skb_unlink(p, &recv_frames); 8113 rxh_le = (struct d11rxhdr_le *)p->data; 8114 rxh = (struct d11rxhdr *)p->data; 8115 8116 /* fixup rx header endianness */ 8117 rxh->RxFrameSize = le16_to_cpu(rxh_le->RxFrameSize); 8118 rxh->PhyRxStatus_0 = le16_to_cpu(rxh_le->PhyRxStatus_0); 8119 rxh->PhyRxStatus_1 = le16_to_cpu(rxh_le->PhyRxStatus_1); 8120 rxh->PhyRxStatus_2 = le16_to_cpu(rxh_le->PhyRxStatus_2); 8121 rxh->PhyRxStatus_3 = le16_to_cpu(rxh_le->PhyRxStatus_3); 8122 rxh->PhyRxStatus_4 = le16_to_cpu(rxh_le->PhyRxStatus_4); 8123 rxh->PhyRxStatus_5 = le16_to_cpu(rxh_le->PhyRxStatus_5); 8124 rxh->RxStatus1 = le16_to_cpu(rxh_le->RxStatus1); 8125 rxh->RxStatus2 = le16_to_cpu(rxh_le->RxStatus2); 8126 rxh->RxTSFTime = le16_to_cpu(rxh_le->RxTSFTime); 8127 rxh->RxChan = le16_to_cpu(rxh_le->RxChan); 8128 8129 brcms_c_recv(wlc_hw->wlc, p); 8130 } 8131 8132 return n >= bound_limit; 8133} 8134 8135/* second-level interrupt processing 8136 * Return true if another dpc needs to be re-scheduled. false otherwise. 8137 * Param 'bounded' indicates if applicable loops should be bounded. 8138 */ 8139bool brcms_c_dpc(struct brcms_c_info *wlc, bool bounded) 8140{ 8141 u32 macintstatus; 8142 struct brcms_hardware *wlc_hw = wlc->hw; 8143 struct bcma_device *core = wlc_hw->d11core; 8144 struct wiphy *wiphy = wlc->wiphy; 8145 8146 if (brcms_deviceremoved(wlc)) { 8147 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit, 8148 __func__); 8149 brcms_down(wlc->wl); 8150 return false; 8151 } 8152 8153 /* grab and clear the saved software intstatus bits */ 8154 macintstatus = wlc->macintstatus; 8155 wlc->macintstatus = 0; 8156 8157 BCMMSG(wlc->wiphy, "wl%d: macintstatus 0x%x\n", 8158 wlc_hw->unit, macintstatus); 8159 8160 WARN_ON(macintstatus & MI_PRQ); /* PRQ Interrupt in non-MBSS */ 8161 8162 /* tx status */ 8163 if (macintstatus & MI_TFS) { 8164 bool fatal; 8165 if (brcms_b_txstatus(wlc->hw, bounded, &fatal)) 8166 wlc->macintstatus |= MI_TFS; 8167 if (fatal) { 8168 wiphy_err(wiphy, "MI_TFS: fatal\n"); 8169 goto fatal; 8170 } 8171 } 8172 8173 if (macintstatus & (MI_TBTT | MI_DTIM_TBTT)) 8174 brcms_c_tbtt(wlc); 8175 8176 /* ATIM window end */ 8177 if (macintstatus & MI_ATIMWINEND) { 8178 BCMMSG(wlc->wiphy, "end of ATIM window\n"); 8179 bcma_set32(core, D11REGOFFS(maccommand), wlc->qvalid); 8180 wlc->qvalid = 0; 8181 } 8182 8183 /* 8184 * received data or control frame, MI_DMAINT is 8185 * indication of RX_FIFO interrupt 8186 */ 8187 if (macintstatus & MI_DMAINT) 8188 if (brcms_b_recv(wlc_hw, RX_FIFO, bounded)) 8189 wlc->macintstatus |= MI_DMAINT; 8190 8191 /* noise sample collected */ 8192 if (macintstatus & MI_BG_NOISE) 8193 wlc_phy_noise_sample_intr(wlc_hw->band->pi); 8194 8195 if (macintstatus & MI_GP0) { 8196 wiphy_err(wiphy, "wl%d: PSM microcode watchdog fired at %d " 8197 "(seconds). Resetting.\n", wlc_hw->unit, wlc_hw->now); 8198 8199 printk_once("%s : PSM Watchdog, chipid 0x%x, chiprev 0x%x\n", 8200 __func__, ai_get_chip_id(wlc_hw->sih), 8201 ai_get_chiprev(wlc_hw->sih)); 8202 brcms_fatal_error(wlc_hw->wlc->wl); 8203 } 8204 8205 /* gptimer timeout */ 8206 if (macintstatus & MI_TO) 8207 bcma_write32(core, D11REGOFFS(gptimer), 0); 8208 8209 if (macintstatus & MI_RFDISABLE) { 8210 BCMMSG(wlc->wiphy, "wl%d: BMAC Detected a change on the" 8211 " RF Disable Input\n", wlc_hw->unit); 8212 brcms_rfkill_set_hw_state(wlc->wl); 8213 } 8214 8215 /* send any enq'd tx packets. Just makes sure to jump start tx */ 8216 if (!pktq_empty(&wlc->pkt_queue->q)) 8217 brcms_c_send_q(wlc); 8218 8219 /* it isn't done and needs to be resched if macintstatus is non-zero */ 8220 return wlc->macintstatus != 0; 8221 8222 fatal: 8223 brcms_fatal_error(wlc_hw->wlc->wl); 8224 return wlc->macintstatus != 0; 8225} 8226 8227void brcms_c_init(struct brcms_c_info *wlc, bool mute_tx) 8228{ 8229 struct bcma_device *core = wlc->hw->d11core; 8230 u16 chanspec; 8231 8232 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit); 8233 8234 /* 8235 * This will happen if a big-hammer was executed. In 8236 * that case, we want to go back to the channel that 8237 * we were on and not new channel 8238 */ 8239 if (wlc->pub->associated) 8240 chanspec = wlc->home_chanspec; 8241 else 8242 chanspec = brcms_c_init_chanspec(wlc); 8243 8244 brcms_b_init(wlc->hw, chanspec); 8245 8246 /* update beacon listen interval */ 8247 brcms_c_bcn_li_upd(wlc); 8248 8249 /* write ethernet address to core */ 8250 brcms_c_set_mac(wlc->bsscfg); 8251 brcms_c_set_bssid(wlc->bsscfg); 8252 8253 /* Update tsf_cfprep if associated and up */ 8254 if (wlc->pub->associated && wlc->bsscfg->up) { 8255 u32 bi; 8256 8257 /* get beacon period and convert to uS */ 8258 bi = wlc->bsscfg->current_bss->beacon_period << 10; 8259 /* 8260 * update since init path would reset 8261 * to default value 8262 */ 8263 bcma_write32(core, D11REGOFFS(tsf_cfprep), 8264 bi << CFPREP_CBI_SHIFT); 8265 8266 /* Update maccontrol PM related bits */ 8267 brcms_c_set_ps_ctrl(wlc); 8268 } 8269 8270 brcms_c_bandinit_ordered(wlc, chanspec); 8271 8272 /* init probe response timeout */ 8273 brcms_b_write_shm(wlc->hw, M_PRS_MAXTIME, wlc->prb_resp_timeout); 8274 8275 /* init max burst txop (framebursting) */ 8276 brcms_b_write_shm(wlc->hw, M_MBURST_TXOP, 8277 (wlc-> 8278 _rifs ? (EDCF_AC_VO_TXOP_AP << 5) : MAXFRAMEBURST_TXOP)); 8279 8280 /* initialize maximum allowed duty cycle */ 8281 brcms_c_duty_cycle_set(wlc, wlc->tx_duty_cycle_ofdm, true, true); 8282 brcms_c_duty_cycle_set(wlc, wlc->tx_duty_cycle_cck, false, true); 8283 8284 /* 8285 * Update some shared memory locations related to 8286 * max AMPDU size allowed to received 8287 */ 8288 brcms_c_ampdu_shm_upd(wlc->ampdu); 8289 8290 /* band-specific inits */ 8291 brcms_c_bsinit(wlc); 8292 8293 /* Enable EDCF mode (while the MAC is suspended) */ 8294 bcma_set16(core, D11REGOFFS(ifs_ctl), IFS_USEEDCF); 8295 brcms_c_edcf_setparams(wlc, false); 8296 8297 /* Init precedence maps for empty FIFOs */ 8298 brcms_c_tx_prec_map_init(wlc); 8299 8300 /* read the ucode version if we have not yet done so */ 8301 if (wlc->ucode_rev == 0) { 8302 wlc->ucode_rev = 8303 brcms_b_read_shm(wlc->hw, M_BOM_REV_MAJOR) << NBITS(u16); 8304 wlc->ucode_rev |= brcms_b_read_shm(wlc->hw, M_BOM_REV_MINOR); 8305 } 8306 8307 /* ..now really unleash hell (allow the MAC out of suspend) */ 8308 brcms_c_enable_mac(wlc); 8309 8310 /* suspend the tx fifos and mute the phy for preism cac time */ 8311 if (mute_tx) 8312 brcms_b_mute(wlc->hw, true); 8313 8314 /* clear tx flow control */ 8315 brcms_c_txflowcontrol_reset(wlc); 8316 8317 /* enable the RF Disable Delay timer */ 8318 bcma_write32(core, D11REGOFFS(rfdisabledly), RFDISABLE_DEFAULT); 8319 8320 /* 8321 * Initialize WME parameters; if they haven't been set by some other 8322 * mechanism (IOVar, etc) then read them from the hardware. 8323 */ 8324 if (GFIELD(wlc->wme_retries[0], EDCF_SHORT) == 0) { 8325 /* Uninitialized; read from HW */ 8326 int ac; 8327 8328 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) 8329 wlc->wme_retries[ac] = 8330 brcms_b_read_shm(wlc->hw, M_AC_TXLMT_ADDR(ac)); 8331 } 8332} 8333 8334/* 8335 * The common driver entry routine. Error codes should be unique 8336 */ 8337struct brcms_c_info * 8338brcms_c_attach(struct brcms_info *wl, struct bcma_device *core, uint unit, 8339 bool piomode, uint *perr) 8340{ 8341 struct brcms_c_info *wlc; 8342 uint err = 0; 8343 uint i, j; 8344 struct brcms_pub *pub; 8345 8346 /* allocate struct brcms_c_info state and its substructures */ 8347 wlc = (struct brcms_c_info *) brcms_c_attach_malloc(unit, &err, 0); 8348 if (wlc == NULL) 8349 goto fail; 8350 wlc->wiphy = wl->wiphy; 8351 pub = wlc->pub; 8352 8353#if defined(BCMDBG) 8354 wlc_info_dbg = wlc; 8355#endif 8356 8357 wlc->band = wlc->bandstate[0]; 8358 wlc->core = wlc->corestate; 8359 wlc->wl = wl; 8360 pub->unit = unit; 8361 pub->_piomode = piomode; 8362 wlc->bandinit_pending = false; 8363 8364 /* populate struct brcms_c_info with default values */ 8365 brcms_c_info_init(wlc, unit); 8366 8367 /* update sta/ap related parameters */ 8368 brcms_c_ap_upd(wlc); 8369 8370 /* 8371 * low level attach steps(all hw accesses go 8372 * inside, no more in rest of the attach) 8373 */ 8374 err = brcms_b_attach(wlc, core, unit, piomode); 8375 if (err) 8376 goto fail; 8377 8378 brcms_c_protection_upd(wlc, BRCMS_PROT_N_PAM_OVR, OFF); 8379 8380 pub->phy_11ncapable = BRCMS_PHY_11N_CAP(wlc->band); 8381 8382 /* disable allowed duty cycle */ 8383 wlc->tx_duty_cycle_ofdm = 0; 8384 wlc->tx_duty_cycle_cck = 0; 8385 8386 brcms_c_stf_phy_chain_calc(wlc); 8387 8388 /* txchain 1: txant 0, txchain 2: txant 1 */ 8389 if (BRCMS_ISNPHY(wlc->band) && (wlc->stf->txstreams == 1)) 8390 wlc->stf->txant = wlc->stf->hw_txchain - 1; 8391 8392 /* push to BMAC driver */ 8393 wlc_phy_stf_chain_init(wlc->band->pi, wlc->stf->hw_txchain, 8394 wlc->stf->hw_rxchain); 8395 8396 /* pull up some info resulting from the low attach */ 8397 for (i = 0; i < NFIFO; i++) 8398 wlc->core->txavail[i] = wlc->hw->txavail[i]; 8399 8400 memcpy(&wlc->perm_etheraddr, &wlc->hw->etheraddr, ETH_ALEN); 8401 memcpy(&pub->cur_etheraddr, &wlc->hw->etheraddr, ETH_ALEN); 8402 8403 for (j = 0; j < wlc->pub->_nbands; j++) { 8404 wlc->band = wlc->bandstate[j]; 8405 8406 if (!brcms_c_attach_stf_ant_init(wlc)) { 8407 err = 24; 8408 goto fail; 8409 } 8410 8411 /* default contention windows size limits */ 8412 wlc->band->CWmin = APHY_CWMIN; 8413 wlc->band->CWmax = PHY_CWMAX; 8414 8415 /* init gmode value */ 8416 if (wlc->band->bandtype == BRCM_BAND_2G) { 8417 wlc->band->gmode = GMODE_AUTO; 8418 brcms_c_protection_upd(wlc, BRCMS_PROT_G_USER, 8419 wlc->band->gmode); 8420 } 8421 8422 /* init _n_enab supported mode */ 8423 if (BRCMS_PHY_11N_CAP(wlc->band)) { 8424 pub->_n_enab = SUPPORT_11N; 8425 brcms_c_protection_upd(wlc, BRCMS_PROT_N_USER, 8426 ((pub->_n_enab == 8427 SUPPORT_11N) ? WL_11N_2x2 : 8428 WL_11N_3x3)); 8429 } 8430 8431 /* init per-band default rateset, depend on band->gmode */ 8432 brcms_default_rateset(wlc, &wlc->band->defrateset); 8433 8434 /* fill in hw_rateset */ 8435 brcms_c_rateset_filter(&wlc->band->defrateset, 8436 &wlc->band->hw_rateset, false, 8437 BRCMS_RATES_CCK_OFDM, BRCMS_RATE_MASK, 8438 (bool) (wlc->pub->_n_enab & SUPPORT_11N)); 8439 } 8440 8441 /* 8442 * update antenna config due to 8443 * wlc->stf->txant/txchain/ant_rx_ovr change 8444 */ 8445 brcms_c_stf_phy_txant_upd(wlc); 8446 8447 /* attach each modules */ 8448 err = brcms_c_attach_module(wlc); 8449 if (err != 0) 8450 goto fail; 8451 8452 if (!brcms_c_timers_init(wlc, unit)) { 8453 wiphy_err(wl->wiphy, "wl%d: %s: init_timer failed\n", unit, 8454 __func__); 8455 err = 32; 8456 goto fail; 8457 } 8458 8459 /* depend on rateset, gmode */ 8460 wlc->cmi = brcms_c_channel_mgr_attach(wlc); 8461 if (!wlc->cmi) { 8462 wiphy_err(wl->wiphy, "wl%d: %s: channel_mgr_attach failed" 8463 "\n", unit, __func__); 8464 err = 33; 8465 goto fail; 8466 } 8467 8468 /* init default when all parameters are ready, i.e. ->rateset */ 8469 brcms_c_bss_default_init(wlc); 8470 8471 /* 8472 * Complete the wlc default state initializations.. 8473 */ 8474 8475 /* allocate our initial queue */ 8476 wlc->pkt_queue = brcms_c_txq_alloc(wlc); 8477 if (wlc->pkt_queue == NULL) { 8478 wiphy_err(wl->wiphy, "wl%d: %s: failed to malloc tx queue\n", 8479 unit, __func__); 8480 err = 100; 8481 goto fail; 8482 } 8483 8484 wlc->bsscfg->wlc = wlc; 8485 8486 wlc->mimoft = FT_HT; 8487 wlc->mimo_40txbw = AUTO; 8488 wlc->ofdm_40txbw = AUTO; 8489 wlc->cck_40txbw = AUTO; 8490 brcms_c_update_mimo_band_bwcap(wlc, BRCMS_N_BW_20IN2G_40IN5G); 8491 8492 /* Set default values of SGI */ 8493 if (BRCMS_SGI_CAP_PHY(wlc)) { 8494 brcms_c_ht_update_sgi_rx(wlc, (BRCMS_N_SGI_20 | 8495 BRCMS_N_SGI_40)); 8496 } else if (BRCMS_ISSSLPNPHY(wlc->band)) { 8497 brcms_c_ht_update_sgi_rx(wlc, (BRCMS_N_SGI_20 | 8498 BRCMS_N_SGI_40)); 8499 } else { 8500 brcms_c_ht_update_sgi_rx(wlc, 0); 8501 } 8502 8503 brcms_b_antsel_set(wlc->hw, wlc->asi->antsel_avail); 8504 8505 if (perr) 8506 *perr = 0; 8507 8508 return wlc; 8509 8510 fail: 8511 wiphy_err(wl->wiphy, "wl%d: %s: failed with err %d\n", 8512 unit, __func__, err); 8513 if (wlc) 8514 brcms_c_detach(wlc); 8515 8516 if (perr) 8517 *perr = err; 8518 return NULL; 8519} 8520