iwl-5000.c revision 0ef2ca67b19e2286eed8eeb7ef7a35ce57d6d629
1/****************************************************************************** 2 * 3 * Copyright(c) 2007-2008 Intel Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * The full GNU General Public License is included in this distribution in the 19 * file called LICENSE. 20 * 21 * Contact Information: 22 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 23 * 24 *****************************************************************************/ 25 26#include <linux/kernel.h> 27#include <linux/module.h> 28#include <linux/init.h> 29#include <linux/pci.h> 30#include <linux/dma-mapping.h> 31#include <linux/delay.h> 32#include <linux/skbuff.h> 33#include <linux/netdevice.h> 34#include <linux/wireless.h> 35#include <net/mac80211.h> 36#include <linux/etherdevice.h> 37#include <asm/unaligned.h> 38 39#include "iwl-eeprom.h" 40#include "iwl-dev.h" 41#include "iwl-core.h" 42#include "iwl-io.h" 43#include "iwl-sta.h" 44#include "iwl-helpers.h" 45#include "iwl-5000-hw.h" 46 47#define IWL5000_UCODE_API "-1" 48 49#define IWL5000_MODULE_FIRMWARE "iwlwifi-5000" IWL5000_UCODE_API ".ucode" 50 51static const u16 iwl5000_default_queue_to_tx_fifo[] = { 52 IWL_TX_FIFO_AC3, 53 IWL_TX_FIFO_AC2, 54 IWL_TX_FIFO_AC1, 55 IWL_TX_FIFO_AC0, 56 IWL50_CMD_FIFO_NUM, 57 IWL_TX_FIFO_HCCA_1, 58 IWL_TX_FIFO_HCCA_2 59}; 60 61/* FIXME: same implementation as 4965 */ 62static int iwl5000_apm_stop_master(struct iwl_priv *priv) 63{ 64 int ret = 0; 65 unsigned long flags; 66 67 spin_lock_irqsave(&priv->lock, flags); 68 69 /* set stop master bit */ 70 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); 71 72 ret = iwl_poll_bit(priv, CSR_RESET, 73 CSR_RESET_REG_FLAG_MASTER_DISABLED, 74 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); 75 if (ret < 0) 76 goto out; 77 78out: 79 spin_unlock_irqrestore(&priv->lock, flags); 80 IWL_DEBUG_INFO("stop master\n"); 81 82 return ret; 83} 84 85 86static int iwl5000_apm_init(struct iwl_priv *priv) 87{ 88 int ret = 0; 89 90 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS, 91 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 92 93 /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */ 94 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS, 95 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 96 97 /* Set FH wait treshold to maximum (HW error during stress W/A) */ 98 iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); 99 100 /* enable HAP INTA to move device L1a -> L0s */ 101 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, 102 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); 103 104 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); 105 106 /* set "initialization complete" bit to move adapter 107 * D0U* --> D0A* state */ 108 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 109 110 /* wait for clock stabilization */ 111 ret = iwl_poll_bit(priv, CSR_GP_CNTRL, 112 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 113 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); 114 if (ret < 0) { 115 IWL_DEBUG_INFO("Failed to init the card\n"); 116 return ret; 117 } 118 119 ret = iwl_grab_nic_access(priv); 120 if (ret) 121 return ret; 122 123 /* enable DMA */ 124 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT); 125 126 udelay(20); 127 128 /* disable L1-Active */ 129 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG, 130 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 131 132 iwl_release_nic_access(priv); 133 134 return ret; 135} 136 137/* FIXME: this is indentical to 4965 */ 138static void iwl5000_apm_stop(struct iwl_priv *priv) 139{ 140 unsigned long flags; 141 142 iwl5000_apm_stop_master(priv); 143 144 spin_lock_irqsave(&priv->lock, flags); 145 146 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 147 148 udelay(10); 149 150 /* clear "init complete" move adapter D0A* --> D0U state */ 151 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 152 153 spin_unlock_irqrestore(&priv->lock, flags); 154} 155 156 157static int iwl5000_apm_reset(struct iwl_priv *priv) 158{ 159 int ret = 0; 160 unsigned long flags; 161 162 iwl5000_apm_stop_master(priv); 163 164 spin_lock_irqsave(&priv->lock, flags); 165 166 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 167 168 udelay(10); 169 170 171 /* FIXME: put here L1A -L0S w/a */ 172 173 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); 174 175 /* set "initialization complete" bit to move adapter 176 * D0U* --> D0A* state */ 177 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 178 179 /* wait for clock stabilization */ 180 ret = iwl_poll_bit(priv, CSR_GP_CNTRL, 181 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 182 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); 183 if (ret < 0) { 184 IWL_DEBUG_INFO("Failed to init the card\n"); 185 goto out; 186 } 187 188 ret = iwl_grab_nic_access(priv); 189 if (ret) 190 goto out; 191 192 /* enable DMA */ 193 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT); 194 195 udelay(20); 196 197 /* disable L1-Active */ 198 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG, 199 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 200 201 iwl_release_nic_access(priv); 202 203out: 204 spin_unlock_irqrestore(&priv->lock, flags); 205 206 return ret; 207} 208 209 210static void iwl5000_nic_config(struct iwl_priv *priv) 211{ 212 unsigned long flags; 213 u16 radio_cfg; 214 u16 link; 215 216 spin_lock_irqsave(&priv->lock, flags); 217 218 pci_read_config_word(priv->pci_dev, PCI_CFG_LINK_CTRL, &link); 219 220 /* L1 is enabled by BIOS */ 221 if ((link & PCI_CFG_LINK_CTRL_VAL_L1_EN) == PCI_CFG_LINK_CTRL_VAL_L1_EN) 222 /* diable L0S disabled L1A enabled */ 223 iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); 224 else 225 /* L0S enabled L1A disabled */ 226 iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); 227 228 radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG); 229 230 /* write radio config values to register */ 231 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_5000_RF_CFG_TYPE_MAX) 232 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, 233 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) | 234 EEPROM_RF_CFG_STEP_MSK(radio_cfg) | 235 EEPROM_RF_CFG_DASH_MSK(radio_cfg)); 236 237 /* set CSR_HW_CONFIG_REG for uCode use */ 238 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, 239 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI | 240 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI); 241 242 /* W/A : NIC is stuck in a reset state after Early PCIe power off 243 * (PCIe power is lost before PERST# is asserted), 244 * causing ME FW to lose ownership and not being able to obtain it back. 245 */ 246 iwl_grab_nic_access(priv); 247 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, 248 APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS, 249 ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS); 250 iwl_release_nic_access(priv); 251 252 spin_unlock_irqrestore(&priv->lock, flags); 253} 254 255 256 257/* 258 * EEPROM 259 */ 260static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address) 261{ 262 u16 offset = 0; 263 264 if ((address & INDIRECT_ADDRESS) == 0) 265 return address; 266 267 switch (address & INDIRECT_TYPE_MSK) { 268 case INDIRECT_HOST: 269 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST); 270 break; 271 case INDIRECT_GENERAL: 272 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL); 273 break; 274 case INDIRECT_REGULATORY: 275 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY); 276 break; 277 case INDIRECT_CALIBRATION: 278 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION); 279 break; 280 case INDIRECT_PROCESS_ADJST: 281 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST); 282 break; 283 case INDIRECT_OTHERS: 284 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS); 285 break; 286 default: 287 IWL_ERROR("illegal indirect type: 0x%X\n", 288 address & INDIRECT_TYPE_MSK); 289 break; 290 } 291 292 /* translate the offset from words to byte */ 293 return (address & ADDRESS_MSK) + (offset << 1); 294} 295 296static u16 iwl5000_eeprom_calib_version(struct iwl_priv *priv) 297{ 298 struct iwl_eeprom_calib_hdr { 299 u8 version; 300 u8 pa_type; 301 u16 voltage; 302 } *hdr; 303 304 hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv, 305 EEPROM_5000_CALIB_ALL); 306 return hdr->version; 307 308} 309 310static void iwl5000_gain_computation(struct iwl_priv *priv, 311 u32 average_noise[NUM_RX_CHAINS], 312 u16 min_average_noise_antenna_i, 313 u32 min_average_noise) 314{ 315 int i; 316 s32 delta_g; 317 struct iwl_chain_noise_data *data = &priv->chain_noise_data; 318 319 /* Find Gain Code for the antennas B and C */ 320 for (i = 1; i < NUM_RX_CHAINS; i++) { 321 if ((data->disconn_array[i])) { 322 data->delta_gain_code[i] = 0; 323 continue; 324 } 325 delta_g = (1000 * ((s32)average_noise[0] - 326 (s32)average_noise[i])) / 1500; 327 /* bound gain by 2 bits value max, 3rd bit is sign */ 328 data->delta_gain_code[i] = 329 min(abs(delta_g), CHAIN_NOISE_MAX_DELTA_GAIN_CODE); 330 331 if (delta_g < 0) 332 /* set negative sign */ 333 data->delta_gain_code[i] |= (1 << 2); 334 } 335 336 IWL_DEBUG_CALIB("Delta gains: ANT_B = %d ANT_C = %d\n", 337 data->delta_gain_code[1], data->delta_gain_code[2]); 338 339 if (!data->radio_write) { 340 struct iwl5000_calibration_chain_noise_gain_cmd cmd; 341 memset(&cmd, 0, sizeof(cmd)); 342 343 cmd.op_code = IWL5000_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD; 344 cmd.delta_gain_1 = data->delta_gain_code[1]; 345 cmd.delta_gain_2 = data->delta_gain_code[2]; 346 iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD, 347 sizeof(cmd), &cmd, NULL); 348 349 data->radio_write = 1; 350 data->state = IWL_CHAIN_NOISE_CALIBRATED; 351 } 352 353 data->chain_noise_a = 0; 354 data->chain_noise_b = 0; 355 data->chain_noise_c = 0; 356 data->chain_signal_a = 0; 357 data->chain_signal_b = 0; 358 data->chain_signal_c = 0; 359 data->beacon_count = 0; 360} 361 362static void iwl5000_chain_noise_reset(struct iwl_priv *priv) 363{ 364 struct iwl_chain_noise_data *data = &priv->chain_noise_data; 365 366 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) { 367 struct iwl5000_calibration_chain_noise_reset_cmd cmd; 368 369 memset(&cmd, 0, sizeof(cmd)); 370 cmd.op_code = IWL5000_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD; 371 if (iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD, 372 sizeof(cmd), &cmd)) 373 IWL_ERROR("Could not send REPLY_PHY_CALIBRATION_CMD\n"); 374 data->state = IWL_CHAIN_NOISE_ACCUMULATE; 375 IWL_DEBUG_CALIB("Run chain_noise_calibrate\n"); 376 } 377} 378 379static void iwl5000_rts_tx_cmd_flag(struct ieee80211_tx_info *info, 380 __le32 *tx_flags) 381{ 382 if ((info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) || 383 (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT)) 384 *tx_flags |= TX_CMD_FLG_RTS_CTS_MSK; 385 else 386 *tx_flags &= ~TX_CMD_FLG_RTS_CTS_MSK; 387} 388 389static struct iwl_sensitivity_ranges iwl5000_sensitivity = { 390 .min_nrg_cck = 95, 391 .max_nrg_cck = 0, 392 .auto_corr_min_ofdm = 90, 393 .auto_corr_min_ofdm_mrc = 170, 394 .auto_corr_min_ofdm_x1 = 120, 395 .auto_corr_min_ofdm_mrc_x1 = 240, 396 397 .auto_corr_max_ofdm = 120, 398 .auto_corr_max_ofdm_mrc = 210, 399 .auto_corr_max_ofdm_x1 = 155, 400 .auto_corr_max_ofdm_mrc_x1 = 290, 401 402 .auto_corr_min_cck = 125, 403 .auto_corr_max_cck = 200, 404 .auto_corr_min_cck_mrc = 170, 405 .auto_corr_max_cck_mrc = 400, 406 .nrg_th_cck = 95, 407 .nrg_th_ofdm = 95, 408}; 409 410static const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv, 411 size_t offset) 412{ 413 u32 address = eeprom_indirect_address(priv, offset); 414 BUG_ON(address >= priv->cfg->eeprom_size); 415 return &priv->eeprom[address]; 416} 417 418/* 419 * Calibration 420 */ 421static int iwl5000_set_Xtal_calib(struct iwl_priv *priv) 422{ 423 u8 data[sizeof(struct iwl5000_calib_hdr) + 424 sizeof(struct iwl_cal_xtal_freq)]; 425 struct iwl5000_calib_cmd *cmd = (struct iwl5000_calib_cmd *)data; 426 struct iwl_cal_xtal_freq *xtal = (struct iwl_cal_xtal_freq *)cmd->data; 427 u16 *xtal_calib = (u16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_XTAL); 428 429 cmd->hdr.op_code = IWL5000_PHY_CALIBRATE_CRYSTAL_FRQ_CMD; 430 xtal->cap_pin1 = (u8)xtal_calib[0]; 431 xtal->cap_pin2 = (u8)xtal_calib[1]; 432 return iwl_calib_set(&priv->calib_results[IWL5000_CALIB_XTAL], 433 data, sizeof(data)); 434} 435 436static int iwl5000_send_calib_cfg(struct iwl_priv *priv) 437{ 438 struct iwl5000_calib_cfg_cmd calib_cfg_cmd; 439 struct iwl_host_cmd cmd = { 440 .id = CALIBRATION_CFG_CMD, 441 .len = sizeof(struct iwl5000_calib_cfg_cmd), 442 .data = &calib_cfg_cmd, 443 }; 444 445 memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd)); 446 calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL; 447 calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL; 448 calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL; 449 calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL; 450 451 return iwl_send_cmd(priv, &cmd); 452} 453 454static void iwl5000_rx_calib_result(struct iwl_priv *priv, 455 struct iwl_rx_mem_buffer *rxb) 456{ 457 struct iwl_rx_packet *pkt = (void *)rxb->skb->data; 458 struct iwl5000_calib_hdr *hdr = (struct iwl5000_calib_hdr *)pkt->u.raw; 459 int len = le32_to_cpu(pkt->len) & FH_RSCSR_FRAME_SIZE_MSK; 460 int index; 461 462 /* reduce the size of the length field itself */ 463 len -= 4; 464 465 /* Define the order in which the results will be sent to the runtime 466 * uCode. iwl_send_calib_results sends them in a row according to their 467 * index. We sort them here */ 468 switch (hdr->op_code) { 469 case IWL5000_PHY_CALIBRATE_LO_CMD: 470 index = IWL5000_CALIB_LO; 471 break; 472 case IWL5000_PHY_CALIBRATE_TX_IQ_CMD: 473 index = IWL5000_CALIB_TX_IQ; 474 break; 475 case IWL5000_PHY_CALIBRATE_TX_IQ_PERD_CMD: 476 index = IWL5000_CALIB_TX_IQ_PERD; 477 break; 478 default: 479 IWL_ERROR("Unknown calibration notification %d\n", 480 hdr->op_code); 481 return; 482 } 483 iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len); 484} 485 486static void iwl5000_rx_calib_complete(struct iwl_priv *priv, 487 struct iwl_rx_mem_buffer *rxb) 488{ 489 IWL_DEBUG_INFO("Init. calibration is completed, restarting fw.\n"); 490 queue_work(priv->workqueue, &priv->restart); 491} 492 493/* 494 * ucode 495 */ 496static int iwl5000_load_section(struct iwl_priv *priv, 497 struct fw_desc *image, 498 u32 dst_addr) 499{ 500 int ret = 0; 501 unsigned long flags; 502 503 dma_addr_t phy_addr = image->p_addr; 504 u32 byte_cnt = image->len; 505 506 spin_lock_irqsave(&priv->lock, flags); 507 ret = iwl_grab_nic_access(priv); 508 if (ret) { 509 spin_unlock_irqrestore(&priv->lock, flags); 510 return ret; 511 } 512 513 iwl_write_direct32(priv, 514 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 515 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); 516 517 iwl_write_direct32(priv, 518 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr); 519 520 iwl_write_direct32(priv, 521 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), 522 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); 523 524 iwl_write_direct32(priv, 525 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), 526 (iwl_get_dma_hi_addr(phy_addr) 527 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); 528 529 iwl_write_direct32(priv, 530 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), 531 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM | 532 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX | 533 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); 534 535 iwl_write_direct32(priv, 536 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 537 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 538 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL | 539 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); 540 541 iwl_release_nic_access(priv); 542 spin_unlock_irqrestore(&priv->lock, flags); 543 return 0; 544} 545 546static int iwl5000_load_given_ucode(struct iwl_priv *priv, 547 struct fw_desc *inst_image, 548 struct fw_desc *data_image) 549{ 550 int ret = 0; 551 552 ret = iwl5000_load_section( 553 priv, inst_image, RTC_INST_LOWER_BOUND); 554 if (ret) 555 return ret; 556 557 IWL_DEBUG_INFO("INST uCode section being loaded...\n"); 558 ret = wait_event_interruptible_timeout(priv->wait_command_queue, 559 priv->ucode_write_complete, 5 * HZ); 560 if (ret == -ERESTARTSYS) { 561 IWL_ERROR("Could not load the INST uCode section due " 562 "to interrupt\n"); 563 return ret; 564 } 565 if (!ret) { 566 IWL_ERROR("Could not load the INST uCode section\n"); 567 return -ETIMEDOUT; 568 } 569 570 priv->ucode_write_complete = 0; 571 572 ret = iwl5000_load_section( 573 priv, data_image, RTC_DATA_LOWER_BOUND); 574 if (ret) 575 return ret; 576 577 IWL_DEBUG_INFO("DATA uCode section being loaded...\n"); 578 579 ret = wait_event_interruptible_timeout(priv->wait_command_queue, 580 priv->ucode_write_complete, 5 * HZ); 581 if (ret == -ERESTARTSYS) { 582 IWL_ERROR("Could not load the INST uCode section due " 583 "to interrupt\n"); 584 return ret; 585 } else if (!ret) { 586 IWL_ERROR("Could not load the DATA uCode section\n"); 587 return -ETIMEDOUT; 588 } else 589 ret = 0; 590 591 priv->ucode_write_complete = 0; 592 593 return ret; 594} 595 596static int iwl5000_load_ucode(struct iwl_priv *priv) 597{ 598 int ret = 0; 599 600 /* check whether init ucode should be loaded, or rather runtime ucode */ 601 if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) { 602 IWL_DEBUG_INFO("Init ucode found. Loading init ucode...\n"); 603 ret = iwl5000_load_given_ucode(priv, 604 &priv->ucode_init, &priv->ucode_init_data); 605 if (!ret) { 606 IWL_DEBUG_INFO("Init ucode load complete.\n"); 607 priv->ucode_type = UCODE_INIT; 608 } 609 } else { 610 IWL_DEBUG_INFO("Init ucode not found, or already loaded. " 611 "Loading runtime ucode...\n"); 612 ret = iwl5000_load_given_ucode(priv, 613 &priv->ucode_code, &priv->ucode_data); 614 if (!ret) { 615 IWL_DEBUG_INFO("Runtime ucode load complete.\n"); 616 priv->ucode_type = UCODE_RT; 617 } 618 } 619 620 return ret; 621} 622 623static void iwl5000_init_alive_start(struct iwl_priv *priv) 624{ 625 int ret = 0; 626 627 /* Check alive response for "valid" sign from uCode */ 628 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) { 629 /* We had an error bringing up the hardware, so take it 630 * all the way back down so we can try again */ 631 IWL_DEBUG_INFO("Initialize Alive failed.\n"); 632 goto restart; 633 } 634 635 /* initialize uCode was loaded... verify inst image. 636 * This is a paranoid check, because we would not have gotten the 637 * "initialize" alive if code weren't properly loaded. */ 638 if (iwl_verify_ucode(priv)) { 639 /* Runtime instruction load was bad; 640 * take it all the way back down so we can try again */ 641 IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n"); 642 goto restart; 643 } 644 645 iwl_clear_stations_table(priv); 646 ret = priv->cfg->ops->lib->alive_notify(priv); 647 if (ret) { 648 IWL_WARNING("Could not complete ALIVE transition: %d\n", ret); 649 goto restart; 650 } 651 652 iwl5000_send_calib_cfg(priv); 653 return; 654 655restart: 656 /* real restart (first load init_ucode) */ 657 queue_work(priv->workqueue, &priv->restart); 658} 659 660static void iwl5000_set_wr_ptrs(struct iwl_priv *priv, 661 int txq_id, u32 index) 662{ 663 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 664 (index & 0xff) | (txq_id << 8)); 665 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index); 666} 667 668static void iwl5000_tx_queue_set_status(struct iwl_priv *priv, 669 struct iwl_tx_queue *txq, 670 int tx_fifo_id, int scd_retry) 671{ 672 int txq_id = txq->q.id; 673 int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0; 674 675 iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id), 676 (active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) | 677 (tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) | 678 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) | 679 IWL50_SCD_QUEUE_STTS_REG_MSK); 680 681 txq->sched_retry = scd_retry; 682 683 IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n", 684 active ? "Activate" : "Deactivate", 685 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id); 686} 687 688static int iwl5000_send_wimax_coex(struct iwl_priv *priv) 689{ 690 struct iwl_wimax_coex_cmd coex_cmd; 691 692 memset(&coex_cmd, 0, sizeof(coex_cmd)); 693 694 return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD, 695 sizeof(coex_cmd), &coex_cmd); 696} 697 698static int iwl5000_alive_notify(struct iwl_priv *priv) 699{ 700 u32 a; 701 int i = 0; 702 unsigned long flags; 703 int ret; 704 705 spin_lock_irqsave(&priv->lock, flags); 706 707 ret = iwl_grab_nic_access(priv); 708 if (ret) { 709 spin_unlock_irqrestore(&priv->lock, flags); 710 return ret; 711 } 712 713 priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR); 714 a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET; 715 for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET; 716 a += 4) 717 iwl_write_targ_mem(priv, a, 0); 718 for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET; 719 a += 4) 720 iwl_write_targ_mem(priv, a, 0); 721 for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4) 722 iwl_write_targ_mem(priv, a, 0); 723 724 iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR, 725 (priv->shared_phys + 726 offsetof(struct iwl5000_shared, queues_byte_cnt_tbls)) >> 10); 727 iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, 728 IWL50_SCD_QUEUECHAIN_SEL_ALL( 729 priv->hw_params.max_txq_num)); 730 iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0); 731 732 /* initiate the queues */ 733 for (i = 0; i < priv->hw_params.max_txq_num; i++) { 734 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0); 735 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8)); 736 iwl_write_targ_mem(priv, priv->scd_base_addr + 737 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0); 738 iwl_write_targ_mem(priv, priv->scd_base_addr + 739 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) + 740 sizeof(u32), 741 ((SCD_WIN_SIZE << 742 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & 743 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | 744 ((SCD_FRAME_LIMIT << 745 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & 746 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); 747 } 748 749 iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK, 750 IWL_MASK(0, priv->hw_params.max_txq_num)); 751 752 /* Activate all Tx DMA/FIFO channels */ 753 priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7)); 754 755 iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0); 756 /* map qos queues to fifos one-to-one */ 757 for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) { 758 int ac = iwl5000_default_queue_to_tx_fifo[i]; 759 iwl_txq_ctx_activate(priv, i); 760 iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0); 761 } 762 /* TODO - need to initialize those FIFOs inside the loop above, 763 * not only mark them as active */ 764 iwl_txq_ctx_activate(priv, 4); 765 iwl_txq_ctx_activate(priv, 7); 766 iwl_txq_ctx_activate(priv, 8); 767 iwl_txq_ctx_activate(priv, 9); 768 769 iwl_release_nic_access(priv); 770 spin_unlock_irqrestore(&priv->lock, flags); 771 772 773 iwl5000_send_wimax_coex(priv); 774 775 iwl5000_set_Xtal_calib(priv); 776 iwl_send_calib_results(priv); 777 778 return 0; 779} 780 781static int iwl5000_hw_set_hw_params(struct iwl_priv *priv) 782{ 783 if ((priv->cfg->mod_params->num_of_queues > IWL50_NUM_QUEUES) || 784 (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) { 785 IWL_ERROR("invalid queues_num, should be between %d and %d\n", 786 IWL_MIN_NUM_QUEUES, IWL50_NUM_QUEUES); 787 return -EINVAL; 788 } 789 790 priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues; 791 priv->hw_params.max_stations = IWL5000_STATION_COUNT; 792 priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID; 793 priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE; 794 priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE; 795 priv->hw_params.max_bsm_size = 0; 796 priv->hw_params.fat_channel = BIT(IEEE80211_BAND_2GHZ) | 797 BIT(IEEE80211_BAND_5GHZ); 798 priv->hw_params.sens = &iwl5000_sensitivity; 799 800 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) { 801 case CSR_HW_REV_TYPE_5100: 802 priv->hw_params.tx_chains_num = 1; 803 priv->hw_params.rx_chains_num = 2; 804 priv->hw_params.valid_tx_ant = ANT_B; 805 priv->hw_params.valid_rx_ant = ANT_AB; 806 break; 807 case CSR_HW_REV_TYPE_5150: 808 priv->hw_params.tx_chains_num = 1; 809 priv->hw_params.rx_chains_num = 2; 810 priv->hw_params.valid_tx_ant = ANT_A; 811 priv->hw_params.valid_rx_ant = ANT_AB; 812 break; 813 case CSR_HW_REV_TYPE_5300: 814 case CSR_HW_REV_TYPE_5350: 815 priv->hw_params.tx_chains_num = 3; 816 priv->hw_params.rx_chains_num = 3; 817 priv->hw_params.valid_tx_ant = ANT_ABC; 818 priv->hw_params.valid_rx_ant = ANT_ABC; 819 break; 820 } 821 822 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) { 823 case CSR_HW_REV_TYPE_5100: 824 case CSR_HW_REV_TYPE_5300: 825 case CSR_HW_REV_TYPE_5350: 826 /* 5X00 and 5350 wants in Celsius */ 827 priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD; 828 break; 829 case CSR_HW_REV_TYPE_5150: 830 /* 5150 wants in Kelvin */ 831 priv->hw_params.ct_kill_threshold = 832 CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD); 833 break; 834 } 835 836 /* Set initial calibration set */ 837 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) { 838 case CSR_HW_REV_TYPE_5100: 839 case CSR_HW_REV_TYPE_5300: 840 case CSR_HW_REV_TYPE_5350: 841 priv->hw_params.calib_init_cfg = 842 BIT(IWL5000_CALIB_XTAL) | 843 BIT(IWL5000_CALIB_LO) | 844 BIT(IWL5000_CALIB_TX_IQ) | 845 BIT(IWL5000_CALIB_TX_IQ_PERD); 846 break; 847 case CSR_HW_REV_TYPE_5150: 848 priv->hw_params.calib_init_cfg = 0; 849 break; 850 } 851 852 853 return 0; 854} 855 856static int iwl5000_alloc_shared_mem(struct iwl_priv *priv) 857{ 858 priv->shared_virt = pci_alloc_consistent(priv->pci_dev, 859 sizeof(struct iwl5000_shared), 860 &priv->shared_phys); 861 if (!priv->shared_virt) 862 return -ENOMEM; 863 864 memset(priv->shared_virt, 0, sizeof(struct iwl5000_shared)); 865 866 priv->rb_closed_offset = offsetof(struct iwl5000_shared, rb_closed); 867 868 return 0; 869} 870 871static void iwl5000_free_shared_mem(struct iwl_priv *priv) 872{ 873 if (priv->shared_virt) 874 pci_free_consistent(priv->pci_dev, 875 sizeof(struct iwl5000_shared), 876 priv->shared_virt, 877 priv->shared_phys); 878} 879 880static int iwl5000_shared_mem_rx_idx(struct iwl_priv *priv) 881{ 882 struct iwl5000_shared *s = priv->shared_virt; 883 return le32_to_cpu(s->rb_closed) & 0xFFF; 884} 885 886/** 887 * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array 888 */ 889static void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv, 890 struct iwl_tx_queue *txq, 891 u16 byte_cnt) 892{ 893 struct iwl5000_shared *shared_data = priv->shared_virt; 894 int txq_id = txq->q.id; 895 u8 sec_ctl = 0; 896 u8 sta = 0; 897 int len; 898 899 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE; 900 901 if (txq_id != IWL_CMD_QUEUE_NUM) { 902 sta = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id; 903 sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl; 904 905 switch (sec_ctl & TX_CMD_SEC_MSK) { 906 case TX_CMD_SEC_CCM: 907 len += CCMP_MIC_LEN; 908 break; 909 case TX_CMD_SEC_TKIP: 910 len += TKIP_ICV_LEN; 911 break; 912 case TX_CMD_SEC_WEP: 913 len += WEP_IV_LEN + WEP_ICV_LEN; 914 break; 915 } 916 } 917 918 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id]. 919 tfd_offset[txq->q.write_ptr], byte_cnt, len); 920 921 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id]. 922 tfd_offset[txq->q.write_ptr], sta_id, sta); 923 924 if (txq->q.write_ptr < IWL50_MAX_WIN_SIZE) { 925 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id]. 926 tfd_offset[IWL50_QUEUE_SIZE + txq->q.write_ptr], 927 byte_cnt, len); 928 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id]. 929 tfd_offset[IWL50_QUEUE_SIZE + txq->q.write_ptr], 930 sta_id, sta); 931 } 932} 933 934static void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv, 935 struct iwl_tx_queue *txq) 936{ 937 int txq_id = txq->q.id; 938 struct iwl5000_shared *shared_data = priv->shared_virt; 939 u8 sta = 0; 940 941 if (txq_id != IWL_CMD_QUEUE_NUM) 942 sta = txq->cmd[txq->q.read_ptr]->cmd.tx.sta_id; 943 944 shared_data->queues_byte_cnt_tbls[txq_id].tfd_offset[txq->q.read_ptr]. 945 val = cpu_to_le16(1 | (sta << 12)); 946 947 if (txq->q.write_ptr < IWL50_MAX_WIN_SIZE) { 948 shared_data->queues_byte_cnt_tbls[txq_id]. 949 tfd_offset[IWL50_QUEUE_SIZE + txq->q.read_ptr]. 950 val = cpu_to_le16(1 | (sta << 12)); 951 } 952} 953 954static int iwl5000_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid, 955 u16 txq_id) 956{ 957 u32 tbl_dw_addr; 958 u32 tbl_dw; 959 u16 scd_q2ratid; 960 961 scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK; 962 963 tbl_dw_addr = priv->scd_base_addr + 964 IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id); 965 966 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr); 967 968 if (txq_id & 0x1) 969 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF); 970 else 971 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000); 972 973 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw); 974 975 return 0; 976} 977static void iwl5000_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id) 978{ 979 /* Simply stop the queue, but don't change any configuration; 980 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */ 981 iwl_write_prph(priv, 982 IWL50_SCD_QUEUE_STATUS_BITS(txq_id), 983 (0 << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE)| 984 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN)); 985} 986 987static int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id, 988 int tx_fifo, int sta_id, int tid, u16 ssn_idx) 989{ 990 unsigned long flags; 991 int ret; 992 u16 ra_tid; 993 994 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) || 995 (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) { 996 IWL_WARNING("queue number out of range: %d, must be %d to %d\n", 997 txq_id, IWL50_FIRST_AMPDU_QUEUE, 998 IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1); 999 return -EINVAL; 1000 } 1001 1002 ra_tid = BUILD_RAxTID(sta_id, tid); 1003 1004 /* Modify device's station table to Tx this TID */ 1005 iwl_sta_modify_enable_tid_tx(priv, sta_id, tid); 1006 1007 spin_lock_irqsave(&priv->lock, flags); 1008 ret = iwl_grab_nic_access(priv); 1009 if (ret) { 1010 spin_unlock_irqrestore(&priv->lock, flags); 1011 return ret; 1012 } 1013 1014 /* Stop this Tx queue before configuring it */ 1015 iwl5000_tx_queue_stop_scheduler(priv, txq_id); 1016 1017 /* Map receiver-address / traffic-ID to this queue */ 1018 iwl5000_tx_queue_set_q2ratid(priv, ra_tid, txq_id); 1019 1020 /* Set this queue as a chain-building queue */ 1021 iwl_set_bits_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, (1<<txq_id)); 1022 1023 /* enable aggregations for the queue */ 1024 iwl_set_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1<<txq_id)); 1025 1026 /* Place first TFD at index corresponding to start sequence number. 1027 * Assumes that ssn_idx is valid (!= 0xFFF) */ 1028 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff); 1029 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff); 1030 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx); 1031 1032 /* Set up Tx window size and frame limit for this queue */ 1033 iwl_write_targ_mem(priv, priv->scd_base_addr + 1034 IWL50_SCD_CONTEXT_QUEUE_OFFSET(txq_id) + 1035 sizeof(u32), 1036 ((SCD_WIN_SIZE << 1037 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & 1038 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | 1039 ((SCD_FRAME_LIMIT << 1040 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & 1041 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); 1042 1043 iwl_set_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id)); 1044 1045 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */ 1046 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1); 1047 1048 iwl_release_nic_access(priv); 1049 spin_unlock_irqrestore(&priv->lock, flags); 1050 1051 return 0; 1052} 1053 1054static int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id, 1055 u16 ssn_idx, u8 tx_fifo) 1056{ 1057 int ret; 1058 1059 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) || 1060 (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) { 1061 IWL_WARNING("queue number out of range: %d, must be %d to %d\n", 1062 txq_id, IWL50_FIRST_AMPDU_QUEUE, 1063 IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1); 1064 return -EINVAL; 1065 } 1066 1067 ret = iwl_grab_nic_access(priv); 1068 if (ret) 1069 return ret; 1070 1071 iwl5000_tx_queue_stop_scheduler(priv, txq_id); 1072 1073 iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id)); 1074 1075 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff); 1076 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff); 1077 /* supposes that ssn_idx is valid (!= 0xFFF) */ 1078 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx); 1079 1080 iwl_clear_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id)); 1081 iwl_txq_ctx_deactivate(priv, txq_id); 1082 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0); 1083 1084 iwl_release_nic_access(priv); 1085 1086 return 0; 1087} 1088 1089static u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data) 1090{ 1091 u16 size = (u16)sizeof(struct iwl_addsta_cmd); 1092 memcpy(data, cmd, size); 1093 return size; 1094} 1095 1096 1097/* 1098 * Activate/Deactivat Tx DMA/FIFO channels according tx fifos mask 1099 * must be called under priv->lock and mac access 1100 */ 1101static void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask) 1102{ 1103 iwl_write_prph(priv, IWL50_SCD_TXFACT, mask); 1104} 1105 1106 1107static inline u32 iwl5000_get_scd_ssn(struct iwl5000_tx_resp *tx_resp) 1108{ 1109 return le32_to_cpup((__le32 *)&tx_resp->status + 1110 tx_resp->frame_count) & MAX_SN; 1111} 1112 1113static int iwl5000_tx_status_reply_tx(struct iwl_priv *priv, 1114 struct iwl_ht_agg *agg, 1115 struct iwl5000_tx_resp *tx_resp, 1116 int txq_id, u16 start_idx) 1117{ 1118 u16 status; 1119 struct agg_tx_status *frame_status = &tx_resp->status; 1120 struct ieee80211_tx_info *info = NULL; 1121 struct ieee80211_hdr *hdr = NULL; 1122 u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags); 1123 int i, sh, idx; 1124 u16 seq; 1125 1126 if (agg->wait_for_ba) 1127 IWL_DEBUG_TX_REPLY("got tx response w/o block-ack\n"); 1128 1129 agg->frame_count = tx_resp->frame_count; 1130 agg->start_idx = start_idx; 1131 agg->rate_n_flags = rate_n_flags; 1132 agg->bitmap = 0; 1133 1134 /* # frames attempted by Tx command */ 1135 if (agg->frame_count == 1) { 1136 /* Only one frame was attempted; no block-ack will arrive */ 1137 status = le16_to_cpu(frame_status[0].status); 1138 idx = start_idx; 1139 1140 /* FIXME: code repetition */ 1141 IWL_DEBUG_TX_REPLY("FrameCnt = %d, StartIdx=%d idx=%d\n", 1142 agg->frame_count, agg->start_idx, idx); 1143 1144 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]); 1145 info->status.rates[0].count = tx_resp->failure_frame + 1; 1146 info->flags &= ~IEEE80211_TX_CTL_AMPDU; 1147 info->flags |= iwl_is_tx_success(status)? 1148 IEEE80211_TX_STAT_ACK : 0; 1149 iwl_hwrate_to_tx_control(priv, rate_n_flags, info); 1150 1151 /* FIXME: code repetition end */ 1152 1153 IWL_DEBUG_TX_REPLY("1 Frame 0x%x failure :%d\n", 1154 status & 0xff, tx_resp->failure_frame); 1155 IWL_DEBUG_TX_REPLY("Rate Info rate_n_flags=%x\n", rate_n_flags); 1156 1157 agg->wait_for_ba = 0; 1158 } else { 1159 /* Two or more frames were attempted; expect block-ack */ 1160 u64 bitmap = 0; 1161 int start = agg->start_idx; 1162 1163 /* Construct bit-map of pending frames within Tx window */ 1164 for (i = 0; i < agg->frame_count; i++) { 1165 u16 sc; 1166 status = le16_to_cpu(frame_status[i].status); 1167 seq = le16_to_cpu(frame_status[i].sequence); 1168 idx = SEQ_TO_INDEX(seq); 1169 txq_id = SEQ_TO_QUEUE(seq); 1170 1171 if (status & (AGG_TX_STATE_FEW_BYTES_MSK | 1172 AGG_TX_STATE_ABORT_MSK)) 1173 continue; 1174 1175 IWL_DEBUG_TX_REPLY("FrameCnt = %d, txq_id=%d idx=%d\n", 1176 agg->frame_count, txq_id, idx); 1177 1178 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx); 1179 1180 sc = le16_to_cpu(hdr->seq_ctrl); 1181 if (idx != (SEQ_TO_SN(sc) & 0xff)) { 1182 IWL_ERROR("BUG_ON idx doesn't match seq control" 1183 " idx=%d, seq_idx=%d, seq=%d\n", 1184 idx, SEQ_TO_SN(sc), 1185 hdr->seq_ctrl); 1186 return -1; 1187 } 1188 1189 IWL_DEBUG_TX_REPLY("AGG Frame i=%d idx %d seq=%d\n", 1190 i, idx, SEQ_TO_SN(sc)); 1191 1192 sh = idx - start; 1193 if (sh > 64) { 1194 sh = (start - idx) + 0xff; 1195 bitmap = bitmap << sh; 1196 sh = 0; 1197 start = idx; 1198 } else if (sh < -64) 1199 sh = 0xff - (start - idx); 1200 else if (sh < 0) { 1201 sh = start - idx; 1202 start = idx; 1203 bitmap = bitmap << sh; 1204 sh = 0; 1205 } 1206 bitmap |= 1ULL << sh; 1207 IWL_DEBUG_TX_REPLY("start=%d bitmap=0x%llx\n", 1208 start, (unsigned long long)bitmap); 1209 } 1210 1211 agg->bitmap = bitmap; 1212 agg->start_idx = start; 1213 IWL_DEBUG_TX_REPLY("Frames %d start_idx=%d bitmap=0x%llx\n", 1214 agg->frame_count, agg->start_idx, 1215 (unsigned long long)agg->bitmap); 1216 1217 if (bitmap) 1218 agg->wait_for_ba = 1; 1219 } 1220 return 0; 1221} 1222 1223static void iwl5000_rx_reply_tx(struct iwl_priv *priv, 1224 struct iwl_rx_mem_buffer *rxb) 1225{ 1226 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; 1227 u16 sequence = le16_to_cpu(pkt->hdr.sequence); 1228 int txq_id = SEQ_TO_QUEUE(sequence); 1229 int index = SEQ_TO_INDEX(sequence); 1230 struct iwl_tx_queue *txq = &priv->txq[txq_id]; 1231 struct ieee80211_tx_info *info; 1232 struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0]; 1233 u32 status = le16_to_cpu(tx_resp->status.status); 1234 int tid; 1235 int sta_id; 1236 int freed; 1237 1238 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) { 1239 IWL_ERROR("Read index for DMA queue txq_id (%d) index %d " 1240 "is out of range [0-%d] %d %d\n", txq_id, 1241 index, txq->q.n_bd, txq->q.write_ptr, 1242 txq->q.read_ptr); 1243 return; 1244 } 1245 1246 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]); 1247 memset(&info->status, 0, sizeof(info->status)); 1248 1249 tid = (tx_resp->ra_tid & IWL50_TX_RES_TID_MSK) >> IWL50_TX_RES_TID_POS; 1250 sta_id = (tx_resp->ra_tid & IWL50_TX_RES_RA_MSK) >> IWL50_TX_RES_RA_POS; 1251 1252 if (txq->sched_retry) { 1253 const u32 scd_ssn = iwl5000_get_scd_ssn(tx_resp); 1254 struct iwl_ht_agg *agg = NULL; 1255 1256 agg = &priv->stations[sta_id].tid[tid].agg; 1257 1258 iwl5000_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index); 1259 1260 /* check if BAR is needed */ 1261 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status)) 1262 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK; 1263 1264 if (txq->q.read_ptr != (scd_ssn & 0xff)) { 1265 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd); 1266 IWL_DEBUG_TX_REPLY("Retry scheduler reclaim " 1267 "scd_ssn=%d idx=%d txq=%d swq=%d\n", 1268 scd_ssn , index, txq_id, txq->swq_id); 1269 1270 freed = iwl_tx_queue_reclaim(priv, txq_id, index); 1271 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed; 1272 1273 if (priv->mac80211_registered && 1274 (iwl_queue_space(&txq->q) > txq->q.low_mark) && 1275 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) { 1276 if (agg->state == IWL_AGG_OFF) 1277 ieee80211_wake_queue(priv->hw, txq_id); 1278 else 1279 ieee80211_wake_queue(priv->hw, 1280 txq->swq_id); 1281 } 1282 } 1283 } else { 1284 BUG_ON(txq_id != txq->swq_id); 1285 1286 info->status.rates[0].count = tx_resp->failure_frame + 1; 1287 info->flags |= iwl_is_tx_success(status) ? 1288 IEEE80211_TX_STAT_ACK : 0; 1289 iwl_hwrate_to_tx_control(priv, 1290 le32_to_cpu(tx_resp->rate_n_flags), 1291 info); 1292 1293 IWL_DEBUG_TX_REPLY("TXQ %d status %s (0x%08x) rate_n_flags " 1294 "0x%x retries %d\n", 1295 txq_id, 1296 iwl_get_tx_fail_reason(status), status, 1297 le32_to_cpu(tx_resp->rate_n_flags), 1298 tx_resp->failure_frame); 1299 1300 freed = iwl_tx_queue_reclaim(priv, txq_id, index); 1301 if (ieee80211_is_data_qos(tx_resp->frame_ctrl)) 1302 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed; 1303 1304 if (priv->mac80211_registered && 1305 (iwl_queue_space(&txq->q) > txq->q.low_mark)) 1306 ieee80211_wake_queue(priv->hw, txq_id); 1307 } 1308 1309 if (ieee80211_is_data_qos(tx_resp->frame_ctrl)) 1310 iwl_txq_check_empty(priv, sta_id, tid, txq_id); 1311 1312 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK)) 1313 IWL_ERROR("TODO: Implement Tx ABORT REQUIRED!!!\n"); 1314} 1315 1316/* Currently 5000 is the supperset of everything */ 1317static u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len) 1318{ 1319 return len; 1320} 1321 1322static void iwl5000_setup_deferred_work(struct iwl_priv *priv) 1323{ 1324 /* in 5000 the tx power calibration is done in uCode */ 1325 priv->disable_tx_power_cal = 1; 1326} 1327 1328static void iwl5000_rx_handler_setup(struct iwl_priv *priv) 1329{ 1330 /* init calibration handlers */ 1331 priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] = 1332 iwl5000_rx_calib_result; 1333 priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] = 1334 iwl5000_rx_calib_complete; 1335 priv->rx_handlers[REPLY_TX] = iwl5000_rx_reply_tx; 1336} 1337 1338 1339static int iwl5000_hw_valid_rtc_data_addr(u32 addr) 1340{ 1341 return (addr >= RTC_DATA_LOWER_BOUND) && 1342 (addr < IWL50_RTC_DATA_UPPER_BOUND); 1343} 1344 1345static int iwl5000_send_rxon_assoc(struct iwl_priv *priv) 1346{ 1347 int ret = 0; 1348 struct iwl5000_rxon_assoc_cmd rxon_assoc; 1349 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon; 1350 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon; 1351 1352 if ((rxon1->flags == rxon2->flags) && 1353 (rxon1->filter_flags == rxon2->filter_flags) && 1354 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) && 1355 (rxon1->ofdm_ht_single_stream_basic_rates == 1356 rxon2->ofdm_ht_single_stream_basic_rates) && 1357 (rxon1->ofdm_ht_dual_stream_basic_rates == 1358 rxon2->ofdm_ht_dual_stream_basic_rates) && 1359 (rxon1->ofdm_ht_triple_stream_basic_rates == 1360 rxon2->ofdm_ht_triple_stream_basic_rates) && 1361 (rxon1->acquisition_data == rxon2->acquisition_data) && 1362 (rxon1->rx_chain == rxon2->rx_chain) && 1363 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) { 1364 IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n"); 1365 return 0; 1366 } 1367 1368 rxon_assoc.flags = priv->staging_rxon.flags; 1369 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags; 1370 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates; 1371 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates; 1372 rxon_assoc.reserved1 = 0; 1373 rxon_assoc.reserved2 = 0; 1374 rxon_assoc.reserved3 = 0; 1375 rxon_assoc.ofdm_ht_single_stream_basic_rates = 1376 priv->staging_rxon.ofdm_ht_single_stream_basic_rates; 1377 rxon_assoc.ofdm_ht_dual_stream_basic_rates = 1378 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates; 1379 rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain; 1380 rxon_assoc.ofdm_ht_triple_stream_basic_rates = 1381 priv->staging_rxon.ofdm_ht_triple_stream_basic_rates; 1382 rxon_assoc.acquisition_data = priv->staging_rxon.acquisition_data; 1383 1384 ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC, 1385 sizeof(rxon_assoc), &rxon_assoc, NULL); 1386 if (ret) 1387 return ret; 1388 1389 return ret; 1390} 1391static int iwl5000_send_tx_power(struct iwl_priv *priv) 1392{ 1393 struct iwl5000_tx_power_dbm_cmd tx_power_cmd; 1394 1395 /* half dBm need to multiply */ 1396 tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt); 1397 tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED; 1398 tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO; 1399 return iwl_send_cmd_pdu_async(priv, REPLY_TX_POWER_DBM_CMD, 1400 sizeof(tx_power_cmd), &tx_power_cmd, 1401 NULL); 1402} 1403 1404static void iwl5000_temperature(struct iwl_priv *priv) 1405{ 1406 /* store temperature from statistics (in Celsius) */ 1407 priv->temperature = le32_to_cpu(priv->statistics.general.temperature); 1408} 1409 1410/* Calc max signal level (dBm) among 3 possible receivers */ 1411static int iwl5000_calc_rssi(struct iwl_priv *priv, 1412 struct iwl_rx_phy_res *rx_resp) 1413{ 1414 /* data from PHY/DSP regarding signal strength, etc., 1415 * contents are always there, not configurable by host 1416 */ 1417 struct iwl5000_non_cfg_phy *ncphy = 1418 (struct iwl5000_non_cfg_phy *)rx_resp->non_cfg_phy_buf; 1419 u32 val, rssi_a, rssi_b, rssi_c, max_rssi; 1420 u8 agc; 1421 1422 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_AGC_IDX]); 1423 agc = (val & IWL50_OFDM_AGC_MSK) >> IWL50_OFDM_AGC_BIT_POS; 1424 1425 /* Find max rssi among 3 possible receivers. 1426 * These values are measured by the digital signal processor (DSP). 1427 * They should stay fairly constant even as the signal strength varies, 1428 * if the radio's automatic gain control (AGC) is working right. 1429 * AGC value (see below) will provide the "interesting" info. 1430 */ 1431 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_AB_IDX]); 1432 rssi_a = (val & IWL50_OFDM_RSSI_A_MSK) >> IWL50_OFDM_RSSI_A_BIT_POS; 1433 rssi_b = (val & IWL50_OFDM_RSSI_B_MSK) >> IWL50_OFDM_RSSI_B_BIT_POS; 1434 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_C_IDX]); 1435 rssi_c = (val & IWL50_OFDM_RSSI_C_MSK) >> IWL50_OFDM_RSSI_C_BIT_POS; 1436 1437 max_rssi = max_t(u32, rssi_a, rssi_b); 1438 max_rssi = max_t(u32, max_rssi, rssi_c); 1439 1440 IWL_DEBUG_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n", 1441 rssi_a, rssi_b, rssi_c, max_rssi, agc); 1442 1443 /* dBm = max_rssi dB - agc dB - constant. 1444 * Higher AGC (higher radio gain) means lower signal. */ 1445 return max_rssi - agc - IWL_RSSI_OFFSET; 1446} 1447 1448static struct iwl_hcmd_ops iwl5000_hcmd = { 1449 .rxon_assoc = iwl5000_send_rxon_assoc, 1450}; 1451 1452static struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = { 1453 .get_hcmd_size = iwl5000_get_hcmd_size, 1454 .build_addsta_hcmd = iwl5000_build_addsta_hcmd, 1455 .gain_computation = iwl5000_gain_computation, 1456 .chain_noise_reset = iwl5000_chain_noise_reset, 1457 .rts_tx_cmd_flag = iwl5000_rts_tx_cmd_flag, 1458 .calc_rssi = iwl5000_calc_rssi, 1459}; 1460 1461static struct iwl_lib_ops iwl5000_lib = { 1462 .set_hw_params = iwl5000_hw_set_hw_params, 1463 .alloc_shared_mem = iwl5000_alloc_shared_mem, 1464 .free_shared_mem = iwl5000_free_shared_mem, 1465 .shared_mem_rx_idx = iwl5000_shared_mem_rx_idx, 1466 .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl, 1467 .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl, 1468 .txq_set_sched = iwl5000_txq_set_sched, 1469 .txq_agg_enable = iwl5000_txq_agg_enable, 1470 .txq_agg_disable = iwl5000_txq_agg_disable, 1471 .rx_handler_setup = iwl5000_rx_handler_setup, 1472 .setup_deferred_work = iwl5000_setup_deferred_work, 1473 .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr, 1474 .load_ucode = iwl5000_load_ucode, 1475 .init_alive_start = iwl5000_init_alive_start, 1476 .alive_notify = iwl5000_alive_notify, 1477 .send_tx_power = iwl5000_send_tx_power, 1478 .temperature = iwl5000_temperature, 1479 .update_chain_flags = iwl4965_update_chain_flags, 1480 .apm_ops = { 1481 .init = iwl5000_apm_init, 1482 .reset = iwl5000_apm_reset, 1483 .stop = iwl5000_apm_stop, 1484 .config = iwl5000_nic_config, 1485 .set_pwr_src = iwl4965_set_pwr_src, 1486 }, 1487 .eeprom_ops = { 1488 .regulatory_bands = { 1489 EEPROM_5000_REG_BAND_1_CHANNELS, 1490 EEPROM_5000_REG_BAND_2_CHANNELS, 1491 EEPROM_5000_REG_BAND_3_CHANNELS, 1492 EEPROM_5000_REG_BAND_4_CHANNELS, 1493 EEPROM_5000_REG_BAND_5_CHANNELS, 1494 EEPROM_5000_REG_BAND_24_FAT_CHANNELS, 1495 EEPROM_5000_REG_BAND_52_FAT_CHANNELS 1496 }, 1497 .verify_signature = iwlcore_eeprom_verify_signature, 1498 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore, 1499 .release_semaphore = iwlcore_eeprom_release_semaphore, 1500 .calib_version = iwl5000_eeprom_calib_version, 1501 .query_addr = iwl5000_eeprom_query_addr, 1502 }, 1503}; 1504 1505static struct iwl_ops iwl5000_ops = { 1506 .lib = &iwl5000_lib, 1507 .hcmd = &iwl5000_hcmd, 1508 .utils = &iwl5000_hcmd_utils, 1509}; 1510 1511static struct iwl_mod_params iwl50_mod_params = { 1512 .num_of_queues = IWL50_NUM_QUEUES, 1513 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES, 1514 .enable_qos = 1, 1515 .amsdu_size_8K = 1, 1516 .restart_fw = 1, 1517 /* the rest are 0 by default */ 1518}; 1519 1520 1521struct iwl_cfg iwl5300_agn_cfg = { 1522 .name = "5300AGN", 1523 .fw_name = IWL5000_MODULE_FIRMWARE, 1524 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N, 1525 .ops = &iwl5000_ops, 1526 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, 1527 .eeprom_ver = EEPROM_5000_EEPROM_VERSION, 1528 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION, 1529 .mod_params = &iwl50_mod_params, 1530}; 1531 1532struct iwl_cfg iwl5100_bg_cfg = { 1533 .name = "5100BG", 1534 .fw_name = IWL5000_MODULE_FIRMWARE, 1535 .sku = IWL_SKU_G, 1536 .ops = &iwl5000_ops, 1537 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, 1538 .eeprom_ver = EEPROM_5000_EEPROM_VERSION, 1539 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION, 1540 .mod_params = &iwl50_mod_params, 1541}; 1542 1543struct iwl_cfg iwl5100_abg_cfg = { 1544 .name = "5100ABG", 1545 .fw_name = IWL5000_MODULE_FIRMWARE, 1546 .sku = IWL_SKU_A|IWL_SKU_G, 1547 .ops = &iwl5000_ops, 1548 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, 1549 .eeprom_ver = EEPROM_5000_EEPROM_VERSION, 1550 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION, 1551 .mod_params = &iwl50_mod_params, 1552}; 1553 1554struct iwl_cfg iwl5100_agn_cfg = { 1555 .name = "5100AGN", 1556 .fw_name = IWL5000_MODULE_FIRMWARE, 1557 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N, 1558 .ops = &iwl5000_ops, 1559 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, 1560 .eeprom_ver = EEPROM_5000_EEPROM_VERSION, 1561 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION, 1562 .mod_params = &iwl50_mod_params, 1563}; 1564 1565struct iwl_cfg iwl5350_agn_cfg = { 1566 .name = "5350AGN", 1567 .fw_name = IWL5000_MODULE_FIRMWARE, 1568 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N, 1569 .ops = &iwl5000_ops, 1570 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, 1571 .eeprom_ver = EEPROM_5050_EEPROM_VERSION, 1572 .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION, 1573 .mod_params = &iwl50_mod_params, 1574}; 1575 1576MODULE_FIRMWARE(IWL5000_MODULE_FIRMWARE); 1577 1578module_param_named(disable50, iwl50_mod_params.disable, int, 0444); 1579MODULE_PARM_DESC(disable50, 1580 "manually disable the 50XX radio (default 0 [radio on])"); 1581module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, 0444); 1582MODULE_PARM_DESC(swcrypto50, 1583 "using software crypto engine (default 0 [hardware])\n"); 1584module_param_named(debug50, iwl50_mod_params.debug, int, 0444); 1585MODULE_PARM_DESC(debug50, "50XX debug output mask"); 1586module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, 0444); 1587MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series"); 1588module_param_named(qos_enable50, iwl50_mod_params.enable_qos, int, 0444); 1589MODULE_PARM_DESC(qos_enable50, "enable all 50XX QoS functionality"); 1590module_param_named(11n_disable50, iwl50_mod_params.disable_11n, int, 0444); 1591MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality"); 1592module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K, int, 0444); 1593MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series"); 1594module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, 0444); 1595MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error"); 1596