iwl-5000.c revision 2d3db679511be102741cb2d5f8c2b8a1ededdee7
1/****************************************************************************** 2 * 3 * Copyright(c) 2007-2008 Intel Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * The full GNU General Public License is included in this distribution in the 19 * file called LICENSE. 20 * 21 * Contact Information: 22 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 23 * 24 *****************************************************************************/ 25 26#include <linux/kernel.h> 27#include <linux/module.h> 28#include <linux/version.h> 29#include <linux/init.h> 30#include <linux/pci.h> 31#include <linux/dma-mapping.h> 32#include <linux/delay.h> 33#include <linux/skbuff.h> 34#include <linux/netdevice.h> 35#include <linux/wireless.h> 36#include <net/mac80211.h> 37#include <linux/etherdevice.h> 38#include <asm/unaligned.h> 39 40#include "iwl-eeprom.h" 41#include "iwl-dev.h" 42#include "iwl-core.h" 43#include "iwl-io.h" 44#include "iwl-sta.h" 45#include "iwl-helpers.h" 46#include "iwl-5000-hw.h" 47 48#define IWL5000_UCODE_API "-1" 49 50static const u16 iwl5000_default_queue_to_tx_fifo[] = { 51 IWL_TX_FIFO_AC3, 52 IWL_TX_FIFO_AC2, 53 IWL_TX_FIFO_AC1, 54 IWL_TX_FIFO_AC0, 55 IWL50_CMD_FIFO_NUM, 56 IWL_TX_FIFO_HCCA_1, 57 IWL_TX_FIFO_HCCA_2 58}; 59 60/* FIXME: same implementation as 4965 */ 61static int iwl5000_apm_stop_master(struct iwl_priv *priv) 62{ 63 int ret = 0; 64 unsigned long flags; 65 66 spin_lock_irqsave(&priv->lock, flags); 67 68 /* set stop master bit */ 69 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); 70 71 ret = iwl_poll_bit(priv, CSR_RESET, 72 CSR_RESET_REG_FLAG_MASTER_DISABLED, 73 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); 74 if (ret < 0) 75 goto out; 76 77out: 78 spin_unlock_irqrestore(&priv->lock, flags); 79 IWL_DEBUG_INFO("stop master\n"); 80 81 return ret; 82} 83 84 85static int iwl5000_apm_init(struct iwl_priv *priv) 86{ 87 int ret = 0; 88 89 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS, 90 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 91 92 /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */ 93 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS, 94 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 95 96 /* Set FH wait treshold to maximum (HW error during stress W/A) */ 97 iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); 98 99 /* enable HAP INTA to move device L1a -> L0s */ 100 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, 101 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); 102 103 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); 104 105 /* set "initialization complete" bit to move adapter 106 * D0U* --> D0A* state */ 107 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 108 109 /* wait for clock stabilization */ 110 ret = iwl_poll_bit(priv, CSR_GP_CNTRL, 111 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 112 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); 113 if (ret < 0) { 114 IWL_DEBUG_INFO("Failed to init the card\n"); 115 return ret; 116 } 117 118 ret = iwl_grab_nic_access(priv); 119 if (ret) 120 return ret; 121 122 /* enable DMA */ 123 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT); 124 125 udelay(20); 126 127 /* disable L1-Active */ 128 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG, 129 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 130 131 iwl_release_nic_access(priv); 132 133 return ret; 134} 135 136/* FIXME: this is indentical to 4965 */ 137static void iwl5000_apm_stop(struct iwl_priv *priv) 138{ 139 unsigned long flags; 140 141 iwl5000_apm_stop_master(priv); 142 143 spin_lock_irqsave(&priv->lock, flags); 144 145 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 146 147 udelay(10); 148 149 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 150 151 spin_unlock_irqrestore(&priv->lock, flags); 152} 153 154 155static int iwl5000_apm_reset(struct iwl_priv *priv) 156{ 157 int ret = 0; 158 unsigned long flags; 159 160 iwl5000_apm_stop_master(priv); 161 162 spin_lock_irqsave(&priv->lock, flags); 163 164 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 165 166 udelay(10); 167 168 169 /* FIXME: put here L1A -L0S w/a */ 170 171 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); 172 173 /* set "initialization complete" bit to move adapter 174 * D0U* --> D0A* state */ 175 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 176 177 /* wait for clock stabilization */ 178 ret = iwl_poll_bit(priv, CSR_GP_CNTRL, 179 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 180 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); 181 if (ret < 0) { 182 IWL_DEBUG_INFO("Failed to init the card\n"); 183 goto out; 184 } 185 186 ret = iwl_grab_nic_access(priv); 187 if (ret) 188 goto out; 189 190 /* enable DMA */ 191 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT); 192 193 udelay(20); 194 195 /* disable L1-Active */ 196 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG, 197 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 198 199 iwl_release_nic_access(priv); 200 201out: 202 spin_unlock_irqrestore(&priv->lock, flags); 203 204 return ret; 205} 206 207 208static void iwl5000_nic_config(struct iwl_priv *priv) 209{ 210 unsigned long flags; 211 u16 radio_cfg; 212 u8 val_link; 213 214 spin_lock_irqsave(&priv->lock, flags); 215 216 pci_read_config_byte(priv->pci_dev, PCI_LINK_CTRL, &val_link); 217 218 /* L1 is enabled by BIOS */ 219 if ((val_link & PCI_LINK_VAL_L1_EN) == PCI_LINK_VAL_L1_EN) 220 /* diable L0S disabled L1A enabled */ 221 iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); 222 else 223 /* L0S enabled L1A disabled */ 224 iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); 225 226 radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG); 227 228 /* write radio config values to register */ 229 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_5000_RF_CFG_TYPE_MAX) 230 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, 231 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) | 232 EEPROM_RF_CFG_STEP_MSK(radio_cfg) | 233 EEPROM_RF_CFG_DASH_MSK(radio_cfg)); 234 235 /* set CSR_HW_CONFIG_REG for uCode use */ 236 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, 237 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI | 238 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI); 239 240 /* W/A : NIC is stuck in a reset state after Early PCIe power off 241 * (PCIe power is lost before PERST# is asserted), 242 * causing ME FW to lose ownership and not being able to obtain it back. 243 */ 244 iwl_grab_nic_access(priv); 245 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, 246 APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS, 247 ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS); 248 iwl_release_nic_access(priv); 249 250 spin_unlock_irqrestore(&priv->lock, flags); 251} 252 253 254 255/* 256 * EEPROM 257 */ 258static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address) 259{ 260 u16 offset = 0; 261 262 if ((address & INDIRECT_ADDRESS) == 0) 263 return address; 264 265 switch (address & INDIRECT_TYPE_MSK) { 266 case INDIRECT_HOST: 267 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST); 268 break; 269 case INDIRECT_GENERAL: 270 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL); 271 break; 272 case INDIRECT_REGULATORY: 273 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY); 274 break; 275 case INDIRECT_CALIBRATION: 276 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION); 277 break; 278 case INDIRECT_PROCESS_ADJST: 279 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST); 280 break; 281 case INDIRECT_OTHERS: 282 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS); 283 break; 284 default: 285 IWL_ERROR("illegal indirect type: 0x%X\n", 286 address & INDIRECT_TYPE_MSK); 287 break; 288 } 289 290 /* translate the offset from words to byte */ 291 return (address & ADDRESS_MSK) + (offset << 1); 292} 293 294static int iwl5000_eeprom_check_version(struct iwl_priv *priv) 295{ 296 u16 eeprom_ver; 297 struct iwl_eeprom_calib_hdr { 298 u8 version; 299 u8 pa_type; 300 u16 voltage; 301 } *hdr; 302 303 eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION); 304 305 hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv, 306 EEPROM_5000_CALIB_ALL); 307 308 if (eeprom_ver < EEPROM_5000_EEPROM_VERSION || 309 hdr->version < EEPROM_5000_TX_POWER_VERSION) 310 goto err; 311 312 return 0; 313err: 314 IWL_ERROR("Unsuported EEPROM VER=0x%x < 0x%x CALIB=0x%x < 0x%x\n", 315 eeprom_ver, EEPROM_5000_EEPROM_VERSION, 316 hdr->version, EEPROM_5000_TX_POWER_VERSION); 317 return -EINVAL; 318 319} 320 321static void iwl5000_gain_computation(struct iwl_priv *priv, 322 u32 average_noise[NUM_RX_CHAINS], 323 u16 min_average_noise_antenna_i, 324 u32 min_average_noise) 325{ 326 int i; 327 s32 delta_g; 328 struct iwl_chain_noise_data *data = &priv->chain_noise_data; 329 330 /* Find Gain Code for the antennas B and C */ 331 for (i = 1; i < NUM_RX_CHAINS; i++) { 332 if ((data->disconn_array[i])) { 333 data->delta_gain_code[i] = 0; 334 continue; 335 } 336 delta_g = (1000 * ((s32)average_noise[0] - 337 (s32)average_noise[i])) / 1500; 338 /* bound gain by 2 bits value max, 3rd bit is sign */ 339 data->delta_gain_code[i] = 340 min(abs(delta_g), CHAIN_NOISE_MAX_DELTA_GAIN_CODE); 341 342 if (delta_g < 0) 343 /* set negative sign */ 344 data->delta_gain_code[i] |= (1 << 2); 345 } 346 347 IWL_DEBUG_CALIB("Delta gains: ANT_B = %d ANT_C = %d\n", 348 data->delta_gain_code[1], data->delta_gain_code[2]); 349 350 if (!data->radio_write) { 351 struct iwl5000_calibration_chain_noise_gain_cmd cmd; 352 memset(&cmd, 0, sizeof(cmd)); 353 354 cmd.op_code = IWL5000_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD; 355 cmd.delta_gain_1 = data->delta_gain_code[1]; 356 cmd.delta_gain_2 = data->delta_gain_code[2]; 357 iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD, 358 sizeof(cmd), &cmd, NULL); 359 360 data->radio_write = 1; 361 data->state = IWL_CHAIN_NOISE_CALIBRATED; 362 } 363 364 data->chain_noise_a = 0; 365 data->chain_noise_b = 0; 366 data->chain_noise_c = 0; 367 data->chain_signal_a = 0; 368 data->chain_signal_b = 0; 369 data->chain_signal_c = 0; 370 data->beacon_count = 0; 371} 372 373static void iwl5000_chain_noise_reset(struct iwl_priv *priv) 374{ 375 struct iwl_chain_noise_data *data = &priv->chain_noise_data; 376 377 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) { 378 struct iwl5000_calibration_chain_noise_reset_cmd cmd; 379 380 memset(&cmd, 0, sizeof(cmd)); 381 cmd.op_code = IWL5000_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD; 382 if (iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD, 383 sizeof(cmd), &cmd)) 384 IWL_ERROR("Could not send REPLY_PHY_CALIBRATION_CMD\n"); 385 data->state = IWL_CHAIN_NOISE_ACCUMULATE; 386 IWL_DEBUG_CALIB("Run chain_noise_calibrate\n"); 387 } 388} 389 390static void iwl5000_rts_tx_cmd_flag(struct ieee80211_tx_info *info, 391 __le32 *tx_flags) 392{ 393 if ((info->flags & IEEE80211_TX_CTL_USE_RTS_CTS) || 394 (info->flags & IEEE80211_TX_CTL_USE_CTS_PROTECT)) 395 *tx_flags |= TX_CMD_FLG_RTS_CTS_MSK; 396 else 397 *tx_flags &= ~TX_CMD_FLG_RTS_CTS_MSK; 398} 399 400static struct iwl_sensitivity_ranges iwl5000_sensitivity = { 401 .min_nrg_cck = 95, 402 .max_nrg_cck = 0, 403 .auto_corr_min_ofdm = 90, 404 .auto_corr_min_ofdm_mrc = 170, 405 .auto_corr_min_ofdm_x1 = 120, 406 .auto_corr_min_ofdm_mrc_x1 = 240, 407 408 .auto_corr_max_ofdm = 120, 409 .auto_corr_max_ofdm_mrc = 210, 410 .auto_corr_max_ofdm_x1 = 155, 411 .auto_corr_max_ofdm_mrc_x1 = 290, 412 413 .auto_corr_min_cck = 125, 414 .auto_corr_max_cck = 200, 415 .auto_corr_min_cck_mrc = 170, 416 .auto_corr_max_cck_mrc = 400, 417 .nrg_th_cck = 95, 418 .nrg_th_ofdm = 95, 419}; 420 421static const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv, 422 size_t offset) 423{ 424 u32 address = eeprom_indirect_address(priv, offset); 425 BUG_ON(address >= priv->cfg->eeprom_size); 426 return &priv->eeprom[address]; 427} 428 429/* 430 * Calibration 431 */ 432static int iwl5000_send_Xtal_calib(struct iwl_priv *priv) 433{ 434 u16 *xtal_calib = (u16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_XTAL); 435 436 struct iwl5000_calibration cal_cmd = { 437 .op_code = IWL5000_PHY_CALIBRATE_CRYSTAL_FRQ_CMD, 438 .data = { 439 (u8)xtal_calib[0], 440 (u8)xtal_calib[1], 441 } 442 }; 443 444 return iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD, 445 sizeof(cal_cmd), &cal_cmd); 446} 447 448static int iwl5000_send_calib_results(struct iwl_priv *priv) 449{ 450 int ret = 0; 451 452 struct iwl_host_cmd hcmd = { 453 .id = REPLY_PHY_CALIBRATION_CMD, 454 .meta.flags = CMD_SIZE_HUGE, 455 }; 456 457 if (priv->calib_results.lo_res) { 458 hcmd.len = priv->calib_results.lo_res_len; 459 hcmd.data = priv->calib_results.lo_res; 460 ret = iwl_send_cmd_sync(priv, &hcmd); 461 462 if (ret) 463 goto err; 464 } 465 466 if (priv->calib_results.tx_iq_res) { 467 hcmd.len = priv->calib_results.tx_iq_res_len; 468 hcmd.data = priv->calib_results.tx_iq_res; 469 ret = iwl_send_cmd_sync(priv, &hcmd); 470 471 if (ret) 472 goto err; 473 } 474 475 if (priv->calib_results.tx_iq_perd_res) { 476 hcmd.len = priv->calib_results.tx_iq_perd_res_len; 477 hcmd.data = priv->calib_results.tx_iq_perd_res; 478 ret = iwl_send_cmd_sync(priv, &hcmd); 479 480 if (ret) 481 goto err; 482 } 483 484 return 0; 485err: 486 IWL_ERROR("Error %d\n", ret); 487 return ret; 488} 489 490static int iwl5000_send_calib_cfg(struct iwl_priv *priv) 491{ 492 struct iwl5000_calib_cfg_cmd calib_cfg_cmd; 493 struct iwl_host_cmd cmd = { 494 .id = CALIBRATION_CFG_CMD, 495 .len = sizeof(struct iwl5000_calib_cfg_cmd), 496 .data = &calib_cfg_cmd, 497 }; 498 499 memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd)); 500 calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL; 501 calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL; 502 calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL; 503 calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL; 504 505 return iwl_send_cmd(priv, &cmd); 506} 507 508static void iwl5000_rx_calib_result(struct iwl_priv *priv, 509 struct iwl_rx_mem_buffer *rxb) 510{ 511 struct iwl_rx_packet *pkt = (void *)rxb->skb->data; 512 struct iwl5000_calib_hdr *hdr = (struct iwl5000_calib_hdr *)pkt->u.raw; 513 int len = le32_to_cpu(pkt->len) & FH_RSCSR_FRAME_SIZE_MSK; 514 515 iwl_free_calib_results(priv); 516 517 /* reduce the size of the length field itself */ 518 len -= 4; 519 520 switch (hdr->op_code) { 521 case IWL5000_PHY_CALIBRATE_LO_CMD: 522 priv->calib_results.lo_res = kzalloc(len, GFP_ATOMIC); 523 priv->calib_results.lo_res_len = len; 524 memcpy(priv->calib_results.lo_res, pkt->u.raw, len); 525 break; 526 case IWL5000_PHY_CALIBRATE_TX_IQ_CMD: 527 priv->calib_results.tx_iq_res = kzalloc(len, GFP_ATOMIC); 528 priv->calib_results.tx_iq_res_len = len; 529 memcpy(priv->calib_results.tx_iq_res, pkt->u.raw, len); 530 break; 531 case IWL5000_PHY_CALIBRATE_TX_IQ_PERD_CMD: 532 priv->calib_results.tx_iq_perd_res = kzalloc(len, GFP_ATOMIC); 533 priv->calib_results.tx_iq_perd_res_len = len; 534 memcpy(priv->calib_results.tx_iq_perd_res, pkt->u.raw, len); 535 break; 536 default: 537 IWL_ERROR("Unknown calibration notification %d\n", 538 hdr->op_code); 539 return; 540 } 541} 542 543static void iwl5000_rx_calib_complete(struct iwl_priv *priv, 544 struct iwl_rx_mem_buffer *rxb) 545{ 546 IWL_DEBUG_INFO("Init. calibration is completed, restarting fw.\n"); 547 queue_work(priv->workqueue, &priv->restart); 548} 549 550/* 551 * ucode 552 */ 553static int iwl5000_load_section(struct iwl_priv *priv, 554 struct fw_desc *image, 555 u32 dst_addr) 556{ 557 int ret = 0; 558 unsigned long flags; 559 560 dma_addr_t phy_addr = image->p_addr; 561 u32 byte_cnt = image->len; 562 563 spin_lock_irqsave(&priv->lock, flags); 564 ret = iwl_grab_nic_access(priv); 565 if (ret) { 566 spin_unlock_irqrestore(&priv->lock, flags); 567 return ret; 568 } 569 570 iwl_write_direct32(priv, 571 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 572 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); 573 574 iwl_write_direct32(priv, 575 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr); 576 577 iwl_write_direct32(priv, 578 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), 579 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); 580 581 /* FIME: write the MSB of the phy_addr in CTRL1 582 * iwl_write_direct32(priv, 583 IWL_FH_TFDIB_CTRL1_REG(IWL_FH_SRVC_CHNL), 584 ((phy_addr & MSB_MSK) 585 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_count); 586 */ 587 iwl_write_direct32(priv, 588 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), byte_cnt); 589 iwl_write_direct32(priv, 590 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), 591 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM | 592 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX | 593 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); 594 595 iwl_write_direct32(priv, 596 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 597 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 598 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL | 599 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); 600 601 iwl_release_nic_access(priv); 602 spin_unlock_irqrestore(&priv->lock, flags); 603 return 0; 604} 605 606static int iwl5000_load_given_ucode(struct iwl_priv *priv, 607 struct fw_desc *inst_image, 608 struct fw_desc *data_image) 609{ 610 int ret = 0; 611 612 ret = iwl5000_load_section( 613 priv, inst_image, RTC_INST_LOWER_BOUND); 614 if (ret) 615 return ret; 616 617 IWL_DEBUG_INFO("INST uCode section being loaded...\n"); 618 ret = wait_event_interruptible_timeout(priv->wait_command_queue, 619 priv->ucode_write_complete, 5 * HZ); 620 if (ret == -ERESTARTSYS) { 621 IWL_ERROR("Could not load the INST uCode section due " 622 "to interrupt\n"); 623 return ret; 624 } 625 if (!ret) { 626 IWL_ERROR("Could not load the INST uCode section\n"); 627 return -ETIMEDOUT; 628 } 629 630 priv->ucode_write_complete = 0; 631 632 ret = iwl5000_load_section( 633 priv, data_image, RTC_DATA_LOWER_BOUND); 634 if (ret) 635 return ret; 636 637 IWL_DEBUG_INFO("DATA uCode section being loaded...\n"); 638 639 ret = wait_event_interruptible_timeout(priv->wait_command_queue, 640 priv->ucode_write_complete, 5 * HZ); 641 if (ret == -ERESTARTSYS) { 642 IWL_ERROR("Could not load the INST uCode section due " 643 "to interrupt\n"); 644 return ret; 645 } else if (!ret) { 646 IWL_ERROR("Could not load the DATA uCode section\n"); 647 return -ETIMEDOUT; 648 } else 649 ret = 0; 650 651 priv->ucode_write_complete = 0; 652 653 return ret; 654} 655 656static int iwl5000_load_ucode(struct iwl_priv *priv) 657{ 658 int ret = 0; 659 660 /* check whether init ucode should be loaded, or rather runtime ucode */ 661 if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) { 662 IWL_DEBUG_INFO("Init ucode found. Loading init ucode...\n"); 663 ret = iwl5000_load_given_ucode(priv, 664 &priv->ucode_init, &priv->ucode_init_data); 665 if (!ret) { 666 IWL_DEBUG_INFO("Init ucode load complete.\n"); 667 priv->ucode_type = UCODE_INIT; 668 } 669 } else { 670 IWL_DEBUG_INFO("Init ucode not found, or already loaded. " 671 "Loading runtime ucode...\n"); 672 ret = iwl5000_load_given_ucode(priv, 673 &priv->ucode_code, &priv->ucode_data); 674 if (!ret) { 675 IWL_DEBUG_INFO("Runtime ucode load complete.\n"); 676 priv->ucode_type = UCODE_RT; 677 } 678 } 679 680 return ret; 681} 682 683static void iwl5000_init_alive_start(struct iwl_priv *priv) 684{ 685 int ret = 0; 686 687 /* Check alive response for "valid" sign from uCode */ 688 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) { 689 /* We had an error bringing up the hardware, so take it 690 * all the way back down so we can try again */ 691 IWL_DEBUG_INFO("Initialize Alive failed.\n"); 692 goto restart; 693 } 694 695 /* initialize uCode was loaded... verify inst image. 696 * This is a paranoid check, because we would not have gotten the 697 * "initialize" alive if code weren't properly loaded. */ 698 if (iwl_verify_ucode(priv)) { 699 /* Runtime instruction load was bad; 700 * take it all the way back down so we can try again */ 701 IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n"); 702 goto restart; 703 } 704 705 iwl_clear_stations_table(priv); 706 ret = priv->cfg->ops->lib->alive_notify(priv); 707 if (ret) { 708 IWL_WARNING("Could not complete ALIVE transition: %d\n", ret); 709 goto restart; 710 } 711 712 iwl5000_send_calib_cfg(priv); 713 return; 714 715restart: 716 /* real restart (first load init_ucode) */ 717 queue_work(priv->workqueue, &priv->restart); 718} 719 720static void iwl5000_set_wr_ptrs(struct iwl_priv *priv, 721 int txq_id, u32 index) 722{ 723 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 724 (index & 0xff) | (txq_id << 8)); 725 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index); 726} 727 728static void iwl5000_tx_queue_set_status(struct iwl_priv *priv, 729 struct iwl_tx_queue *txq, 730 int tx_fifo_id, int scd_retry) 731{ 732 int txq_id = txq->q.id; 733 int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0; 734 735 iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id), 736 (active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) | 737 (tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) | 738 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) | 739 IWL50_SCD_QUEUE_STTS_REG_MSK); 740 741 txq->sched_retry = scd_retry; 742 743 IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n", 744 active ? "Activate" : "Deactivate", 745 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id); 746} 747 748static int iwl5000_send_wimax_coex(struct iwl_priv *priv) 749{ 750 struct iwl_wimax_coex_cmd coex_cmd; 751 752 memset(&coex_cmd, 0, sizeof(coex_cmd)); 753 754 return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD, 755 sizeof(coex_cmd), &coex_cmd); 756} 757 758static int iwl5000_alive_notify(struct iwl_priv *priv) 759{ 760 u32 a; 761 int i = 0; 762 unsigned long flags; 763 int ret; 764 765 spin_lock_irqsave(&priv->lock, flags); 766 767 ret = iwl_grab_nic_access(priv); 768 if (ret) { 769 spin_unlock_irqrestore(&priv->lock, flags); 770 return ret; 771 } 772 773 priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR); 774 a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET; 775 for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET; 776 a += 4) 777 iwl_write_targ_mem(priv, a, 0); 778 for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET; 779 a += 4) 780 iwl_write_targ_mem(priv, a, 0); 781 for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4) 782 iwl_write_targ_mem(priv, a, 0); 783 784 iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR, 785 (priv->shared_phys + 786 offsetof(struct iwl5000_shared, queues_byte_cnt_tbls)) >> 10); 787 iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, 788 IWL50_SCD_QUEUECHAIN_SEL_ALL( 789 priv->hw_params.max_txq_num)); 790 iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0); 791 792 /* initiate the queues */ 793 for (i = 0; i < priv->hw_params.max_txq_num; i++) { 794 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0); 795 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8)); 796 iwl_write_targ_mem(priv, priv->scd_base_addr + 797 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0); 798 iwl_write_targ_mem(priv, priv->scd_base_addr + 799 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) + 800 sizeof(u32), 801 ((SCD_WIN_SIZE << 802 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & 803 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | 804 ((SCD_FRAME_LIMIT << 805 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & 806 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); 807 } 808 809 iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK, 810 IWL_MASK(0, priv->hw_params.max_txq_num)); 811 812 /* Activate all Tx DMA/FIFO channels */ 813 priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7)); 814 815 iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0); 816 /* map qos queues to fifos one-to-one */ 817 for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) { 818 int ac = iwl5000_default_queue_to_tx_fifo[i]; 819 iwl_txq_ctx_activate(priv, i); 820 iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0); 821 } 822 /* TODO - need to initialize those FIFOs inside the loop above, 823 * not only mark them as active */ 824 iwl_txq_ctx_activate(priv, 4); 825 iwl_txq_ctx_activate(priv, 7); 826 iwl_txq_ctx_activate(priv, 8); 827 iwl_txq_ctx_activate(priv, 9); 828 829 iwl_release_nic_access(priv); 830 spin_unlock_irqrestore(&priv->lock, flags); 831 832 833 iwl5000_send_wimax_coex(priv); 834 835 iwl5000_send_Xtal_calib(priv); 836 837 if (priv->ucode_type == UCODE_RT) 838 iwl5000_send_calib_results(priv); 839 840 return 0; 841} 842 843static int iwl5000_hw_set_hw_params(struct iwl_priv *priv) 844{ 845 if ((priv->cfg->mod_params->num_of_queues > IWL50_NUM_QUEUES) || 846 (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) { 847 IWL_ERROR("invalid queues_num, should be between %d and %d\n", 848 IWL_MIN_NUM_QUEUES, IWL50_NUM_QUEUES); 849 return -EINVAL; 850 } 851 852 priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues; 853 priv->hw_params.first_ampdu_q = IWL50_FIRST_AMPDU_QUEUE; 854 priv->hw_params.max_stations = IWL5000_STATION_COUNT; 855 priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID; 856 priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE; 857 priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE; 858 priv->hw_params.max_bsm_size = 0; 859 priv->hw_params.fat_channel = BIT(IEEE80211_BAND_2GHZ) | 860 BIT(IEEE80211_BAND_5GHZ); 861 priv->hw_params.sens = &iwl5000_sensitivity; 862 863 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) { 864 case CSR_HW_REV_TYPE_5100: 865 case CSR_HW_REV_TYPE_5150: 866 priv->hw_params.tx_chains_num = 1; 867 priv->hw_params.rx_chains_num = 2; 868 /* FIXME: move to ANT_A, ANT_B, ANT_C enum */ 869 priv->hw_params.valid_tx_ant = ANT_A; 870 priv->hw_params.valid_rx_ant = ANT_AB; 871 break; 872 case CSR_HW_REV_TYPE_5300: 873 case CSR_HW_REV_TYPE_5350: 874 priv->hw_params.tx_chains_num = 3; 875 priv->hw_params.rx_chains_num = 3; 876 priv->hw_params.valid_tx_ant = ANT_ABC; 877 priv->hw_params.valid_rx_ant = ANT_ABC; 878 break; 879 } 880 881 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) { 882 case CSR_HW_REV_TYPE_5100: 883 case CSR_HW_REV_TYPE_5300: 884 /* 5X00 wants in Celsius */ 885 priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD; 886 break; 887 case CSR_HW_REV_TYPE_5150: 888 case CSR_HW_REV_TYPE_5350: 889 /* 5X50 wants in Kelvin */ 890 priv->hw_params.ct_kill_threshold = 891 CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD); 892 break; 893 } 894 895 return 0; 896} 897 898static int iwl5000_alloc_shared_mem(struct iwl_priv *priv) 899{ 900 priv->shared_virt = pci_alloc_consistent(priv->pci_dev, 901 sizeof(struct iwl5000_shared), 902 &priv->shared_phys); 903 if (!priv->shared_virt) 904 return -ENOMEM; 905 906 memset(priv->shared_virt, 0, sizeof(struct iwl5000_shared)); 907 908 priv->rb_closed_offset = offsetof(struct iwl5000_shared, rb_closed); 909 910 return 0; 911} 912 913static void iwl5000_free_shared_mem(struct iwl_priv *priv) 914{ 915 if (priv->shared_virt) 916 pci_free_consistent(priv->pci_dev, 917 sizeof(struct iwl5000_shared), 918 priv->shared_virt, 919 priv->shared_phys); 920} 921 922static int iwl5000_shared_mem_rx_idx(struct iwl_priv *priv) 923{ 924 struct iwl5000_shared *s = priv->shared_virt; 925 return le32_to_cpu(s->rb_closed) & 0xFFF; 926} 927 928/** 929 * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array 930 */ 931static void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv, 932 struct iwl_tx_queue *txq, 933 u16 byte_cnt) 934{ 935 struct iwl5000_shared *shared_data = priv->shared_virt; 936 int txq_id = txq->q.id; 937 u8 sec_ctl = 0; 938 u8 sta = 0; 939 int len; 940 941 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE; 942 943 if (txq_id != IWL_CMD_QUEUE_NUM) { 944 sta = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id; 945 sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl; 946 947 switch (sec_ctl & TX_CMD_SEC_MSK) { 948 case TX_CMD_SEC_CCM: 949 len += CCMP_MIC_LEN; 950 break; 951 case TX_CMD_SEC_TKIP: 952 len += TKIP_ICV_LEN; 953 break; 954 case TX_CMD_SEC_WEP: 955 len += WEP_IV_LEN + WEP_ICV_LEN; 956 break; 957 } 958 } 959 960 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id]. 961 tfd_offset[txq->q.write_ptr], byte_cnt, len); 962 963 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id]. 964 tfd_offset[txq->q.write_ptr], sta_id, sta); 965 966 if (txq->q.write_ptr < IWL50_MAX_WIN_SIZE) { 967 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id]. 968 tfd_offset[IWL50_QUEUE_SIZE + txq->q.write_ptr], 969 byte_cnt, len); 970 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id]. 971 tfd_offset[IWL50_QUEUE_SIZE + txq->q.write_ptr], 972 sta_id, sta); 973 } 974} 975 976static void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv, 977 struct iwl_tx_queue *txq) 978{ 979 int txq_id = txq->q.id; 980 struct iwl5000_shared *shared_data = priv->shared_virt; 981 u8 sta = 0; 982 983 if (txq_id != IWL_CMD_QUEUE_NUM) 984 sta = txq->cmd[txq->q.read_ptr]->cmd.tx.sta_id; 985 986 shared_data->queues_byte_cnt_tbls[txq_id].tfd_offset[txq->q.read_ptr]. 987 val = cpu_to_le16(1 | (sta << 12)); 988 989 if (txq->q.write_ptr < IWL50_MAX_WIN_SIZE) { 990 shared_data->queues_byte_cnt_tbls[txq_id]. 991 tfd_offset[IWL50_QUEUE_SIZE + txq->q.read_ptr]. 992 val = cpu_to_le16(1 | (sta << 12)); 993 } 994} 995 996static int iwl5000_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid, 997 u16 txq_id) 998{ 999 u32 tbl_dw_addr; 1000 u32 tbl_dw; 1001 u16 scd_q2ratid; 1002 1003 scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK; 1004 1005 tbl_dw_addr = priv->scd_base_addr + 1006 IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id); 1007 1008 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr); 1009 1010 if (txq_id & 0x1) 1011 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF); 1012 else 1013 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000); 1014 1015 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw); 1016 1017 return 0; 1018} 1019static void iwl5000_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id) 1020{ 1021 /* Simply stop the queue, but don't change any configuration; 1022 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */ 1023 iwl_write_prph(priv, 1024 IWL50_SCD_QUEUE_STATUS_BITS(txq_id), 1025 (0 << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE)| 1026 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN)); 1027} 1028 1029static int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id, 1030 int tx_fifo, int sta_id, int tid, u16 ssn_idx) 1031{ 1032 unsigned long flags; 1033 int ret; 1034 u16 ra_tid; 1035 1036 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) || 1037 (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) { 1038 IWL_WARNING("queue number out of range: %d, must be %d to %d\n", 1039 txq_id, IWL50_FIRST_AMPDU_QUEUE, 1040 IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1); 1041 return -EINVAL; 1042 } 1043 1044 ra_tid = BUILD_RAxTID(sta_id, tid); 1045 1046 /* Modify device's station table to Tx this TID */ 1047 iwl_sta_modify_enable_tid_tx(priv, sta_id, tid); 1048 1049 spin_lock_irqsave(&priv->lock, flags); 1050 ret = iwl_grab_nic_access(priv); 1051 if (ret) { 1052 spin_unlock_irqrestore(&priv->lock, flags); 1053 return ret; 1054 } 1055 1056 /* Stop this Tx queue before configuring it */ 1057 iwl5000_tx_queue_stop_scheduler(priv, txq_id); 1058 1059 /* Map receiver-address / traffic-ID to this queue */ 1060 iwl5000_tx_queue_set_q2ratid(priv, ra_tid, txq_id); 1061 1062 /* Set this queue as a chain-building queue */ 1063 iwl_set_bits_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, (1<<txq_id)); 1064 1065 /* enable aggregations for the queue */ 1066 iwl_set_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1<<txq_id)); 1067 1068 /* Place first TFD at index corresponding to start sequence number. 1069 * Assumes that ssn_idx is valid (!= 0xFFF) */ 1070 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff); 1071 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff); 1072 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx); 1073 1074 /* Set up Tx window size and frame limit for this queue */ 1075 iwl_write_targ_mem(priv, priv->scd_base_addr + 1076 IWL50_SCD_CONTEXT_QUEUE_OFFSET(txq_id) + 1077 sizeof(u32), 1078 ((SCD_WIN_SIZE << 1079 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & 1080 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | 1081 ((SCD_FRAME_LIMIT << 1082 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & 1083 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); 1084 1085 iwl_set_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id)); 1086 1087 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */ 1088 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1); 1089 1090 iwl_release_nic_access(priv); 1091 spin_unlock_irqrestore(&priv->lock, flags); 1092 1093 return 0; 1094} 1095 1096static int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id, 1097 u16 ssn_idx, u8 tx_fifo) 1098{ 1099 int ret; 1100 1101 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) || 1102 (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) { 1103 IWL_WARNING("queue number out of range: %d, must be %d to %d\n", 1104 txq_id, IWL50_FIRST_AMPDU_QUEUE, 1105 IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1); 1106 return -EINVAL; 1107 } 1108 1109 ret = iwl_grab_nic_access(priv); 1110 if (ret) 1111 return ret; 1112 1113 iwl5000_tx_queue_stop_scheduler(priv, txq_id); 1114 1115 iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id)); 1116 1117 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff); 1118 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff); 1119 /* supposes that ssn_idx is valid (!= 0xFFF) */ 1120 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx); 1121 1122 iwl_clear_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id)); 1123 iwl_txq_ctx_deactivate(priv, txq_id); 1124 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0); 1125 1126 iwl_release_nic_access(priv); 1127 1128 return 0; 1129} 1130 1131static u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data) 1132{ 1133 u16 size = (u16)sizeof(struct iwl_addsta_cmd); 1134 memcpy(data, cmd, size); 1135 return size; 1136} 1137 1138 1139/* 1140 * Activate/Deactivat Tx DMA/FIFO channels according tx fifos mask 1141 * must be called under priv->lock and mac access 1142 */ 1143static void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask) 1144{ 1145 iwl_write_prph(priv, IWL50_SCD_TXFACT, mask); 1146} 1147 1148 1149static inline u32 iwl5000_get_scd_ssn(struct iwl5000_tx_resp *tx_resp) 1150{ 1151 return le32_to_cpup((__le32 *)&tx_resp->status + 1152 tx_resp->frame_count) & MAX_SN; 1153} 1154 1155static int iwl5000_tx_status_reply_tx(struct iwl_priv *priv, 1156 struct iwl_ht_agg *agg, 1157 struct iwl5000_tx_resp *tx_resp, 1158 int txq_id, u16 start_idx) 1159{ 1160 u16 status; 1161 struct agg_tx_status *frame_status = &tx_resp->status; 1162 struct ieee80211_tx_info *info = NULL; 1163 struct ieee80211_hdr *hdr = NULL; 1164 u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags); 1165 int i, sh, idx; 1166 u16 seq; 1167 1168 if (agg->wait_for_ba) 1169 IWL_DEBUG_TX_REPLY("got tx response w/o block-ack\n"); 1170 1171 agg->frame_count = tx_resp->frame_count; 1172 agg->start_idx = start_idx; 1173 agg->rate_n_flags = rate_n_flags; 1174 agg->bitmap = 0; 1175 1176 /* # frames attempted by Tx command */ 1177 if (agg->frame_count == 1) { 1178 /* Only one frame was attempted; no block-ack will arrive */ 1179 status = le16_to_cpu(frame_status[0].status); 1180 idx = start_idx; 1181 1182 /* FIXME: code repetition */ 1183 IWL_DEBUG_TX_REPLY("FrameCnt = %d, StartIdx=%d idx=%d\n", 1184 agg->frame_count, agg->start_idx, idx); 1185 1186 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]); 1187 info->status.retry_count = tx_resp->failure_frame; 1188 info->flags &= ~IEEE80211_TX_CTL_AMPDU; 1189 info->flags |= iwl_is_tx_success(status)? 1190 IEEE80211_TX_STAT_ACK : 0; 1191 iwl_hwrate_to_tx_control(priv, rate_n_flags, info); 1192 1193 /* FIXME: code repetition end */ 1194 1195 IWL_DEBUG_TX_REPLY("1 Frame 0x%x failure :%d\n", 1196 status & 0xff, tx_resp->failure_frame); 1197 IWL_DEBUG_TX_REPLY("Rate Info rate_n_flags=%x\n", rate_n_flags); 1198 1199 agg->wait_for_ba = 0; 1200 } else { 1201 /* Two or more frames were attempted; expect block-ack */ 1202 u64 bitmap = 0; 1203 int start = agg->start_idx; 1204 1205 /* Construct bit-map of pending frames within Tx window */ 1206 for (i = 0; i < agg->frame_count; i++) { 1207 u16 sc; 1208 status = le16_to_cpu(frame_status[i].status); 1209 seq = le16_to_cpu(frame_status[i].sequence); 1210 idx = SEQ_TO_INDEX(seq); 1211 txq_id = SEQ_TO_QUEUE(seq); 1212 1213 if (status & (AGG_TX_STATE_FEW_BYTES_MSK | 1214 AGG_TX_STATE_ABORT_MSK)) 1215 continue; 1216 1217 IWL_DEBUG_TX_REPLY("FrameCnt = %d, txq_id=%d idx=%d\n", 1218 agg->frame_count, txq_id, idx); 1219 1220 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx); 1221 1222 sc = le16_to_cpu(hdr->seq_ctrl); 1223 if (idx != (SEQ_TO_SN(sc) & 0xff)) { 1224 IWL_ERROR("BUG_ON idx doesn't match seq control" 1225 " idx=%d, seq_idx=%d, seq=%d\n", 1226 idx, SEQ_TO_SN(sc), 1227 hdr->seq_ctrl); 1228 return -1; 1229 } 1230 1231 IWL_DEBUG_TX_REPLY("AGG Frame i=%d idx %d seq=%d\n", 1232 i, idx, SEQ_TO_SN(sc)); 1233 1234 sh = idx - start; 1235 if (sh > 64) { 1236 sh = (start - idx) + 0xff; 1237 bitmap = bitmap << sh; 1238 sh = 0; 1239 start = idx; 1240 } else if (sh < -64) 1241 sh = 0xff - (start - idx); 1242 else if (sh < 0) { 1243 sh = start - idx; 1244 start = idx; 1245 bitmap = bitmap << sh; 1246 sh = 0; 1247 } 1248 bitmap |= 1ULL << sh; 1249 IWL_DEBUG_TX_REPLY("start=%d bitmap=0x%llx\n", 1250 start, (unsigned long long)bitmap); 1251 } 1252 1253 agg->bitmap = bitmap; 1254 agg->start_idx = start; 1255 IWL_DEBUG_TX_REPLY("Frames %d start_idx=%d bitmap=0x%llx\n", 1256 agg->frame_count, agg->start_idx, 1257 (unsigned long long)agg->bitmap); 1258 1259 if (bitmap) 1260 agg->wait_for_ba = 1; 1261 } 1262 return 0; 1263} 1264 1265static void iwl5000_rx_reply_tx(struct iwl_priv *priv, 1266 struct iwl_rx_mem_buffer *rxb) 1267{ 1268 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; 1269 u16 sequence = le16_to_cpu(pkt->hdr.sequence); 1270 int txq_id = SEQ_TO_QUEUE(sequence); 1271 int index = SEQ_TO_INDEX(sequence); 1272 struct iwl_tx_queue *txq = &priv->txq[txq_id]; 1273 struct ieee80211_tx_info *info; 1274 struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0]; 1275 u32 status = le16_to_cpu(tx_resp->status.status); 1276 int tid = MAX_TID_COUNT, sta_id = IWL_INVALID_STATION; 1277 struct ieee80211_hdr *hdr; 1278 u8 *qc = NULL; 1279 1280 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) { 1281 IWL_ERROR("Read index for DMA queue txq_id (%d) index %d " 1282 "is out of range [0-%d] %d %d\n", txq_id, 1283 index, txq->q.n_bd, txq->q.write_ptr, 1284 txq->q.read_ptr); 1285 return; 1286 } 1287 1288 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]); 1289 memset(&info->status, 0, sizeof(info->status)); 1290 1291 hdr = iwl_tx_queue_get_hdr(priv, txq_id, index); 1292 if (ieee80211_is_data_qos(hdr->frame_control)) { 1293 qc = ieee80211_get_qos_ctl(hdr); 1294 tid = qc[0] & 0xf; 1295 } 1296 1297 sta_id = iwl_get_ra_sta_id(priv, hdr); 1298 if (txq->sched_retry && unlikely(sta_id == IWL_INVALID_STATION)) { 1299 IWL_ERROR("Station not known\n"); 1300 return; 1301 } 1302 1303 if (txq->sched_retry) { 1304 const u32 scd_ssn = iwl5000_get_scd_ssn(tx_resp); 1305 struct iwl_ht_agg *agg = NULL; 1306 1307 if (!qc) 1308 return; 1309 1310 agg = &priv->stations[sta_id].tid[tid].agg; 1311 1312 iwl5000_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index); 1313 1314 /* check if BAR is needed */ 1315 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status)) 1316 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK; 1317 1318 if (txq->q.read_ptr != (scd_ssn & 0xff)) { 1319 int freed, ampdu_q; 1320 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd); 1321 IWL_DEBUG_TX_REPLY("Retry scheduler reclaim scd_ssn " 1322 "%d index %d\n", scd_ssn , index); 1323 freed = iwl_tx_queue_reclaim(priv, txq_id, index); 1324 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed; 1325 1326 if (iwl_queue_space(&txq->q) > txq->q.low_mark && 1327 txq_id >= 0 && priv->mac80211_registered && 1328 agg->state != IWL_EMPTYING_HW_QUEUE_DELBA) { 1329 /* calculate mac80211 ampdu sw queue to wake */ 1330 ampdu_q = txq_id - IWL50_FIRST_AMPDU_QUEUE + 1331 priv->hw->queues; 1332 if (agg->state == IWL_AGG_OFF) 1333 ieee80211_wake_queue(priv->hw, txq_id); 1334 else 1335 ieee80211_wake_queue(priv->hw, ampdu_q); 1336 } 1337 iwl_txq_check_empty(priv, sta_id, tid, txq_id); 1338 } 1339 } else { 1340 info->status.retry_count = tx_resp->failure_frame; 1341 info->flags = 1342 iwl_is_tx_success(status) ? IEEE80211_TX_STAT_ACK : 0; 1343 iwl_hwrate_to_tx_control(priv, 1344 le32_to_cpu(tx_resp->rate_n_flags), 1345 info); 1346 1347 IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) rate_n_flags " 1348 "0x%x retries %d\n", txq_id, 1349 iwl_get_tx_fail_reason(status), 1350 status, le32_to_cpu(tx_resp->rate_n_flags), 1351 tx_resp->failure_frame); 1352 1353 IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index); 1354 if (index != -1) { 1355 int freed = iwl_tx_queue_reclaim(priv, txq_id, index); 1356 if (tid != MAX_TID_COUNT) 1357 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed; 1358 if (iwl_queue_space(&txq->q) > txq->q.low_mark && 1359 (txq_id >= 0) && priv->mac80211_registered) 1360 ieee80211_wake_queue(priv->hw, txq_id); 1361 if (tid != MAX_TID_COUNT) 1362 iwl_txq_check_empty(priv, sta_id, tid, txq_id); 1363 } 1364 } 1365 1366 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK)) 1367 IWL_ERROR("TODO: Implement Tx ABORT REQUIRED!!!\n"); 1368} 1369 1370/* Currently 5000 is the supperset of everything */ 1371static u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len) 1372{ 1373 return len; 1374} 1375 1376static void iwl5000_setup_deferred_work(struct iwl_priv *priv) 1377{ 1378 /* in 5000 the tx power calibration is done in uCode */ 1379 priv->disable_tx_power_cal = 1; 1380} 1381 1382static void iwl5000_rx_handler_setup(struct iwl_priv *priv) 1383{ 1384 /* init calibration handlers */ 1385 priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] = 1386 iwl5000_rx_calib_result; 1387 priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] = 1388 iwl5000_rx_calib_complete; 1389 priv->rx_handlers[REPLY_TX] = iwl5000_rx_reply_tx; 1390} 1391 1392 1393static int iwl5000_hw_valid_rtc_data_addr(u32 addr) 1394{ 1395 return (addr >= RTC_DATA_LOWER_BOUND) && 1396 (addr < IWL50_RTC_DATA_UPPER_BOUND); 1397} 1398 1399static int iwl5000_send_rxon_assoc(struct iwl_priv *priv) 1400{ 1401 int ret = 0; 1402 struct iwl5000_rxon_assoc_cmd rxon_assoc; 1403 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon; 1404 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon; 1405 1406 if ((rxon1->flags == rxon2->flags) && 1407 (rxon1->filter_flags == rxon2->filter_flags) && 1408 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) && 1409 (rxon1->ofdm_ht_single_stream_basic_rates == 1410 rxon2->ofdm_ht_single_stream_basic_rates) && 1411 (rxon1->ofdm_ht_dual_stream_basic_rates == 1412 rxon2->ofdm_ht_dual_stream_basic_rates) && 1413 (rxon1->ofdm_ht_triple_stream_basic_rates == 1414 rxon2->ofdm_ht_triple_stream_basic_rates) && 1415 (rxon1->acquisition_data == rxon2->acquisition_data) && 1416 (rxon1->rx_chain == rxon2->rx_chain) && 1417 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) { 1418 IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n"); 1419 return 0; 1420 } 1421 1422 rxon_assoc.flags = priv->staging_rxon.flags; 1423 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags; 1424 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates; 1425 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates; 1426 rxon_assoc.reserved1 = 0; 1427 rxon_assoc.reserved2 = 0; 1428 rxon_assoc.reserved3 = 0; 1429 rxon_assoc.ofdm_ht_single_stream_basic_rates = 1430 priv->staging_rxon.ofdm_ht_single_stream_basic_rates; 1431 rxon_assoc.ofdm_ht_dual_stream_basic_rates = 1432 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates; 1433 rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain; 1434 rxon_assoc.ofdm_ht_triple_stream_basic_rates = 1435 priv->staging_rxon.ofdm_ht_triple_stream_basic_rates; 1436 rxon_assoc.acquisition_data = priv->staging_rxon.acquisition_data; 1437 1438 ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC, 1439 sizeof(rxon_assoc), &rxon_assoc, NULL); 1440 if (ret) 1441 return ret; 1442 1443 return ret; 1444} 1445static int iwl5000_send_tx_power(struct iwl_priv *priv) 1446{ 1447 struct iwl5000_tx_power_dbm_cmd tx_power_cmd; 1448 1449 /* half dBm need to multiply */ 1450 tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt); 1451 tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED; 1452 tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO; 1453 return iwl_send_cmd_pdu_async(priv, REPLY_TX_POWER_DBM_CMD, 1454 sizeof(tx_power_cmd), &tx_power_cmd, 1455 NULL); 1456} 1457 1458static void iwl5000_temperature(struct iwl_priv *priv) 1459{ 1460 /* store temperature from statistics (in Celsius) */ 1461 priv->temperature = le32_to_cpu(priv->statistics.general.temperature); 1462} 1463 1464/* Calc max signal level (dBm) among 3 possible receivers */ 1465static int iwl5000_calc_rssi(struct iwl_priv *priv, 1466 struct iwl_rx_phy_res *rx_resp) 1467{ 1468 /* data from PHY/DSP regarding signal strength, etc., 1469 * contents are always there, not configurable by host 1470 */ 1471 struct iwl5000_non_cfg_phy *ncphy = 1472 (struct iwl5000_non_cfg_phy *)rx_resp->non_cfg_phy_buf; 1473 u32 val, rssi_a, rssi_b, rssi_c, max_rssi; 1474 u8 agc; 1475 1476 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_AGC_IDX]); 1477 agc = (val & IWL50_OFDM_AGC_MSK) >> IWL50_OFDM_AGC_BIT_POS; 1478 1479 /* Find max rssi among 3 possible receivers. 1480 * These values are measured by the digital signal processor (DSP). 1481 * They should stay fairly constant even as the signal strength varies, 1482 * if the radio's automatic gain control (AGC) is working right. 1483 * AGC value (see below) will provide the "interesting" info. 1484 */ 1485 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_AB_IDX]); 1486 rssi_a = (val & IWL50_OFDM_RSSI_A_MSK) >> IWL50_OFDM_RSSI_A_BIT_POS; 1487 rssi_b = (val & IWL50_OFDM_RSSI_B_MSK) >> IWL50_OFDM_RSSI_B_BIT_POS; 1488 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_C_IDX]); 1489 rssi_c = (val & IWL50_OFDM_RSSI_C_MSK) >> IWL50_OFDM_RSSI_C_BIT_POS; 1490 1491 max_rssi = max_t(u32, rssi_a, rssi_b); 1492 max_rssi = max_t(u32, max_rssi, rssi_c); 1493 1494 IWL_DEBUG_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n", 1495 rssi_a, rssi_b, rssi_c, max_rssi, agc); 1496 1497 /* dBm = max_rssi dB - agc dB - constant. 1498 * Higher AGC (higher radio gain) means lower signal. */ 1499 return max_rssi - agc - IWL_RSSI_OFFSET; 1500} 1501 1502static struct iwl_hcmd_ops iwl5000_hcmd = { 1503 .rxon_assoc = iwl5000_send_rxon_assoc, 1504}; 1505 1506static struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = { 1507 .get_hcmd_size = iwl5000_get_hcmd_size, 1508 .build_addsta_hcmd = iwl5000_build_addsta_hcmd, 1509 .gain_computation = iwl5000_gain_computation, 1510 .chain_noise_reset = iwl5000_chain_noise_reset, 1511 .rts_tx_cmd_flag = iwl5000_rts_tx_cmd_flag, 1512 .calc_rssi = iwl5000_calc_rssi, 1513}; 1514 1515static struct iwl_lib_ops iwl5000_lib = { 1516 .set_hw_params = iwl5000_hw_set_hw_params, 1517 .alloc_shared_mem = iwl5000_alloc_shared_mem, 1518 .free_shared_mem = iwl5000_free_shared_mem, 1519 .shared_mem_rx_idx = iwl5000_shared_mem_rx_idx, 1520 .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl, 1521 .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl, 1522 .txq_set_sched = iwl5000_txq_set_sched, 1523 .txq_agg_enable = iwl5000_txq_agg_enable, 1524 .txq_agg_disable = iwl5000_txq_agg_disable, 1525 .rx_handler_setup = iwl5000_rx_handler_setup, 1526 .setup_deferred_work = iwl5000_setup_deferred_work, 1527 .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr, 1528 .load_ucode = iwl5000_load_ucode, 1529 .init_alive_start = iwl5000_init_alive_start, 1530 .alive_notify = iwl5000_alive_notify, 1531 .send_tx_power = iwl5000_send_tx_power, 1532 .temperature = iwl5000_temperature, 1533 .update_chain_flags = iwl4965_update_chain_flags, 1534 .apm_ops = { 1535 .init = iwl5000_apm_init, 1536 .reset = iwl5000_apm_reset, 1537 .stop = iwl5000_apm_stop, 1538 .config = iwl5000_nic_config, 1539 .set_pwr_src = iwl4965_set_pwr_src, 1540 }, 1541 .eeprom_ops = { 1542 .regulatory_bands = { 1543 EEPROM_5000_REG_BAND_1_CHANNELS, 1544 EEPROM_5000_REG_BAND_2_CHANNELS, 1545 EEPROM_5000_REG_BAND_3_CHANNELS, 1546 EEPROM_5000_REG_BAND_4_CHANNELS, 1547 EEPROM_5000_REG_BAND_5_CHANNELS, 1548 EEPROM_5000_REG_BAND_24_FAT_CHANNELS, 1549 EEPROM_5000_REG_BAND_52_FAT_CHANNELS 1550 }, 1551 .verify_signature = iwlcore_eeprom_verify_signature, 1552 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore, 1553 .release_semaphore = iwlcore_eeprom_release_semaphore, 1554 .check_version = iwl5000_eeprom_check_version, 1555 .query_addr = iwl5000_eeprom_query_addr, 1556 }, 1557}; 1558 1559static struct iwl_ops iwl5000_ops = { 1560 .lib = &iwl5000_lib, 1561 .hcmd = &iwl5000_hcmd, 1562 .utils = &iwl5000_hcmd_utils, 1563}; 1564 1565static struct iwl_mod_params iwl50_mod_params = { 1566 .num_of_queues = IWL50_NUM_QUEUES, 1567 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES, 1568 .enable_qos = 1, 1569 .amsdu_size_8K = 1, 1570 .restart_fw = 1, 1571 /* the rest are 0 by default */ 1572}; 1573 1574 1575struct iwl_cfg iwl5300_agn_cfg = { 1576 .name = "5300AGN", 1577 .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode", 1578 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N, 1579 .ops = &iwl5000_ops, 1580 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, 1581 .mod_params = &iwl50_mod_params, 1582}; 1583 1584struct iwl_cfg iwl5100_bg_cfg = { 1585 .name = "5100BG", 1586 .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode", 1587 .sku = IWL_SKU_G, 1588 .ops = &iwl5000_ops, 1589 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, 1590 .mod_params = &iwl50_mod_params, 1591}; 1592 1593struct iwl_cfg iwl5100_abg_cfg = { 1594 .name = "5100ABG", 1595 .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode", 1596 .sku = IWL_SKU_A|IWL_SKU_G, 1597 .ops = &iwl5000_ops, 1598 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, 1599 .mod_params = &iwl50_mod_params, 1600}; 1601 1602struct iwl_cfg iwl5100_agn_cfg = { 1603 .name = "5100AGN", 1604 .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode", 1605 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N, 1606 .ops = &iwl5000_ops, 1607 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, 1608 .mod_params = &iwl50_mod_params, 1609}; 1610 1611struct iwl_cfg iwl5350_agn_cfg = { 1612 .name = "5350AGN", 1613 .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode", 1614 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N, 1615 .ops = &iwl5000_ops, 1616 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, 1617 .mod_params = &iwl50_mod_params, 1618}; 1619 1620module_param_named(disable50, iwl50_mod_params.disable, int, 0444); 1621MODULE_PARM_DESC(disable50, 1622 "manually disable the 50XX radio (default 0 [radio on])"); 1623module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, 0444); 1624MODULE_PARM_DESC(swcrypto50, 1625 "using software crypto engine (default 0 [hardware])\n"); 1626module_param_named(debug50, iwl50_mod_params.debug, int, 0444); 1627MODULE_PARM_DESC(debug50, "50XX debug output mask"); 1628module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, 0444); 1629MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series"); 1630module_param_named(qos_enable50, iwl50_mod_params.enable_qos, int, 0444); 1631MODULE_PARM_DESC(qos_enable50, "enable all 50XX QoS functionality"); 1632module_param_named(11n_disable50, iwl50_mod_params.disable_11n, int, 0444); 1633MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality"); 1634module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K, int, 0444); 1635MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series"); 1636module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, 0444); 1637MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error"); 1638