iwl-5000.c revision 499b1883038a7db2dcf8b64229f8533ce2c8f0fc
1/****************************************************************************** 2 * 3 * Copyright(c) 2007-2008 Intel Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * The full GNU General Public License is included in this distribution in the 19 * file called LICENSE. 20 * 21 * Contact Information: 22 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 23 * 24 *****************************************************************************/ 25 26#include <linux/kernel.h> 27#include <linux/module.h> 28#include <linux/init.h> 29#include <linux/pci.h> 30#include <linux/dma-mapping.h> 31#include <linux/delay.h> 32#include <linux/skbuff.h> 33#include <linux/netdevice.h> 34#include <linux/wireless.h> 35#include <net/mac80211.h> 36#include <linux/etherdevice.h> 37#include <asm/unaligned.h> 38 39#include "iwl-eeprom.h" 40#include "iwl-dev.h" 41#include "iwl-core.h" 42#include "iwl-io.h" 43#include "iwl-sta.h" 44#include "iwl-helpers.h" 45#include "iwl-5000-hw.h" 46 47#define IWL5000_UCODE_API "-1" 48 49#define IWL5000_MODULE_FIRMWARE "iwlwifi-5000" IWL5000_UCODE_API ".ucode" 50 51static const u16 iwl5000_default_queue_to_tx_fifo[] = { 52 IWL_TX_FIFO_AC3, 53 IWL_TX_FIFO_AC2, 54 IWL_TX_FIFO_AC1, 55 IWL_TX_FIFO_AC0, 56 IWL50_CMD_FIFO_NUM, 57 IWL_TX_FIFO_HCCA_1, 58 IWL_TX_FIFO_HCCA_2 59}; 60 61/* FIXME: same implementation as 4965 */ 62static int iwl5000_apm_stop_master(struct iwl_priv *priv) 63{ 64 int ret = 0; 65 unsigned long flags; 66 67 spin_lock_irqsave(&priv->lock, flags); 68 69 /* set stop master bit */ 70 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); 71 72 ret = iwl_poll_bit(priv, CSR_RESET, 73 CSR_RESET_REG_FLAG_MASTER_DISABLED, 74 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); 75 if (ret < 0) 76 goto out; 77 78out: 79 spin_unlock_irqrestore(&priv->lock, flags); 80 IWL_DEBUG_INFO("stop master\n"); 81 82 return ret; 83} 84 85 86static int iwl5000_apm_init(struct iwl_priv *priv) 87{ 88 int ret = 0; 89 90 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS, 91 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 92 93 /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */ 94 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS, 95 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 96 97 /* Set FH wait treshold to maximum (HW error during stress W/A) */ 98 iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); 99 100 /* enable HAP INTA to move device L1a -> L0s */ 101 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, 102 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); 103 104 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); 105 106 /* set "initialization complete" bit to move adapter 107 * D0U* --> D0A* state */ 108 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 109 110 /* wait for clock stabilization */ 111 ret = iwl_poll_bit(priv, CSR_GP_CNTRL, 112 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 113 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); 114 if (ret < 0) { 115 IWL_DEBUG_INFO("Failed to init the card\n"); 116 return ret; 117 } 118 119 ret = iwl_grab_nic_access(priv); 120 if (ret) 121 return ret; 122 123 /* enable DMA */ 124 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT); 125 126 udelay(20); 127 128 /* disable L1-Active */ 129 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG, 130 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 131 132 iwl_release_nic_access(priv); 133 134 return ret; 135} 136 137/* FIXME: this is indentical to 4965 */ 138static void iwl5000_apm_stop(struct iwl_priv *priv) 139{ 140 unsigned long flags; 141 142 iwl5000_apm_stop_master(priv); 143 144 spin_lock_irqsave(&priv->lock, flags); 145 146 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 147 148 udelay(10); 149 150 /* clear "init complete" move adapter D0A* --> D0U state */ 151 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 152 153 spin_unlock_irqrestore(&priv->lock, flags); 154} 155 156 157static int iwl5000_apm_reset(struct iwl_priv *priv) 158{ 159 int ret = 0; 160 unsigned long flags; 161 162 iwl5000_apm_stop_master(priv); 163 164 spin_lock_irqsave(&priv->lock, flags); 165 166 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 167 168 udelay(10); 169 170 171 /* FIXME: put here L1A -L0S w/a */ 172 173 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); 174 175 /* set "initialization complete" bit to move adapter 176 * D0U* --> D0A* state */ 177 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 178 179 /* wait for clock stabilization */ 180 ret = iwl_poll_bit(priv, CSR_GP_CNTRL, 181 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 182 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); 183 if (ret < 0) { 184 IWL_DEBUG_INFO("Failed to init the card\n"); 185 goto out; 186 } 187 188 ret = iwl_grab_nic_access(priv); 189 if (ret) 190 goto out; 191 192 /* enable DMA */ 193 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT); 194 195 udelay(20); 196 197 /* disable L1-Active */ 198 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG, 199 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 200 201 iwl_release_nic_access(priv); 202 203out: 204 spin_unlock_irqrestore(&priv->lock, flags); 205 206 return ret; 207} 208 209 210static void iwl5000_nic_config(struct iwl_priv *priv) 211{ 212 unsigned long flags; 213 u16 radio_cfg; 214 u16 link; 215 216 spin_lock_irqsave(&priv->lock, flags); 217 218 pci_read_config_word(priv->pci_dev, PCI_CFG_LINK_CTRL, &link); 219 220 /* L1 is enabled by BIOS */ 221 if ((link & PCI_CFG_LINK_CTRL_VAL_L1_EN) == PCI_CFG_LINK_CTRL_VAL_L1_EN) 222 /* diable L0S disabled L1A enabled */ 223 iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); 224 else 225 /* L0S enabled L1A disabled */ 226 iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); 227 228 radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG); 229 230 /* write radio config values to register */ 231 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_5000_RF_CFG_TYPE_MAX) 232 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, 233 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) | 234 EEPROM_RF_CFG_STEP_MSK(radio_cfg) | 235 EEPROM_RF_CFG_DASH_MSK(radio_cfg)); 236 237 /* set CSR_HW_CONFIG_REG for uCode use */ 238 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, 239 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI | 240 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI); 241 242 /* W/A : NIC is stuck in a reset state after Early PCIe power off 243 * (PCIe power is lost before PERST# is asserted), 244 * causing ME FW to lose ownership and not being able to obtain it back. 245 */ 246 iwl_grab_nic_access(priv); 247 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, 248 APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS, 249 ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS); 250 iwl_release_nic_access(priv); 251 252 spin_unlock_irqrestore(&priv->lock, flags); 253} 254 255 256 257/* 258 * EEPROM 259 */ 260static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address) 261{ 262 u16 offset = 0; 263 264 if ((address & INDIRECT_ADDRESS) == 0) 265 return address; 266 267 switch (address & INDIRECT_TYPE_MSK) { 268 case INDIRECT_HOST: 269 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST); 270 break; 271 case INDIRECT_GENERAL: 272 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL); 273 break; 274 case INDIRECT_REGULATORY: 275 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY); 276 break; 277 case INDIRECT_CALIBRATION: 278 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION); 279 break; 280 case INDIRECT_PROCESS_ADJST: 281 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST); 282 break; 283 case INDIRECT_OTHERS: 284 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS); 285 break; 286 default: 287 IWL_ERROR("illegal indirect type: 0x%X\n", 288 address & INDIRECT_TYPE_MSK); 289 break; 290 } 291 292 /* translate the offset from words to byte */ 293 return (address & ADDRESS_MSK) + (offset << 1); 294} 295 296static int iwl5000_eeprom_check_version(struct iwl_priv *priv) 297{ 298 u16 eeprom_ver; 299 struct iwl_eeprom_calib_hdr { 300 u8 version; 301 u8 pa_type; 302 u16 voltage; 303 } *hdr; 304 305 eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION); 306 307 hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv, 308 EEPROM_5000_CALIB_ALL); 309 310 if (eeprom_ver < EEPROM_5000_EEPROM_VERSION || 311 hdr->version < EEPROM_5000_TX_POWER_VERSION) 312 goto err; 313 314 return 0; 315err: 316 IWL_ERROR("Unsuported EEPROM VER=0x%x < 0x%x CALIB=0x%x < 0x%x\n", 317 eeprom_ver, EEPROM_5000_EEPROM_VERSION, 318 hdr->version, EEPROM_5000_TX_POWER_VERSION); 319 return -EINVAL; 320 321} 322 323static void iwl5000_gain_computation(struct iwl_priv *priv, 324 u32 average_noise[NUM_RX_CHAINS], 325 u16 min_average_noise_antenna_i, 326 u32 min_average_noise) 327{ 328 int i; 329 s32 delta_g; 330 struct iwl_chain_noise_data *data = &priv->chain_noise_data; 331 332 /* Find Gain Code for the antennas B and C */ 333 for (i = 1; i < NUM_RX_CHAINS; i++) { 334 if ((data->disconn_array[i])) { 335 data->delta_gain_code[i] = 0; 336 continue; 337 } 338 delta_g = (1000 * ((s32)average_noise[0] - 339 (s32)average_noise[i])) / 1500; 340 /* bound gain by 2 bits value max, 3rd bit is sign */ 341 data->delta_gain_code[i] = 342 min(abs(delta_g), CHAIN_NOISE_MAX_DELTA_GAIN_CODE); 343 344 if (delta_g < 0) 345 /* set negative sign */ 346 data->delta_gain_code[i] |= (1 << 2); 347 } 348 349 IWL_DEBUG_CALIB("Delta gains: ANT_B = %d ANT_C = %d\n", 350 data->delta_gain_code[1], data->delta_gain_code[2]); 351 352 if (!data->radio_write) { 353 struct iwl5000_calibration_chain_noise_gain_cmd cmd; 354 memset(&cmd, 0, sizeof(cmd)); 355 356 cmd.op_code = IWL5000_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD; 357 cmd.delta_gain_1 = data->delta_gain_code[1]; 358 cmd.delta_gain_2 = data->delta_gain_code[2]; 359 iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD, 360 sizeof(cmd), &cmd, NULL); 361 362 data->radio_write = 1; 363 data->state = IWL_CHAIN_NOISE_CALIBRATED; 364 } 365 366 data->chain_noise_a = 0; 367 data->chain_noise_b = 0; 368 data->chain_noise_c = 0; 369 data->chain_signal_a = 0; 370 data->chain_signal_b = 0; 371 data->chain_signal_c = 0; 372 data->beacon_count = 0; 373} 374 375static void iwl5000_chain_noise_reset(struct iwl_priv *priv) 376{ 377 struct iwl_chain_noise_data *data = &priv->chain_noise_data; 378 379 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) { 380 struct iwl5000_calibration_chain_noise_reset_cmd cmd; 381 382 memset(&cmd, 0, sizeof(cmd)); 383 cmd.op_code = IWL5000_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD; 384 if (iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD, 385 sizeof(cmd), &cmd)) 386 IWL_ERROR("Could not send REPLY_PHY_CALIBRATION_CMD\n"); 387 data->state = IWL_CHAIN_NOISE_ACCUMULATE; 388 IWL_DEBUG_CALIB("Run chain_noise_calibrate\n"); 389 } 390} 391 392static void iwl5000_rts_tx_cmd_flag(struct ieee80211_tx_info *info, 393 __le32 *tx_flags) 394{ 395 if ((info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) || 396 (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT)) 397 *tx_flags |= TX_CMD_FLG_RTS_CTS_MSK; 398 else 399 *tx_flags &= ~TX_CMD_FLG_RTS_CTS_MSK; 400} 401 402static struct iwl_sensitivity_ranges iwl5000_sensitivity = { 403 .min_nrg_cck = 95, 404 .max_nrg_cck = 0, 405 .auto_corr_min_ofdm = 90, 406 .auto_corr_min_ofdm_mrc = 170, 407 .auto_corr_min_ofdm_x1 = 120, 408 .auto_corr_min_ofdm_mrc_x1 = 240, 409 410 .auto_corr_max_ofdm = 120, 411 .auto_corr_max_ofdm_mrc = 210, 412 .auto_corr_max_ofdm_x1 = 155, 413 .auto_corr_max_ofdm_mrc_x1 = 290, 414 415 .auto_corr_min_cck = 125, 416 .auto_corr_max_cck = 200, 417 .auto_corr_min_cck_mrc = 170, 418 .auto_corr_max_cck_mrc = 400, 419 .nrg_th_cck = 95, 420 .nrg_th_ofdm = 95, 421}; 422 423static const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv, 424 size_t offset) 425{ 426 u32 address = eeprom_indirect_address(priv, offset); 427 BUG_ON(address >= priv->cfg->eeprom_size); 428 return &priv->eeprom[address]; 429} 430 431/* 432 * Calibration 433 */ 434static int iwl5000_set_Xtal_calib(struct iwl_priv *priv) 435{ 436 u8 data[sizeof(struct iwl5000_calib_hdr) + 437 sizeof(struct iwl_cal_xtal_freq)]; 438 struct iwl5000_calib_cmd *cmd = (struct iwl5000_calib_cmd *)data; 439 struct iwl_cal_xtal_freq *xtal = (struct iwl_cal_xtal_freq *)cmd->data; 440 u16 *xtal_calib = (u16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_XTAL); 441 442 cmd->hdr.op_code = IWL5000_PHY_CALIBRATE_CRYSTAL_FRQ_CMD; 443 xtal->cap_pin1 = (u8)xtal_calib[0]; 444 xtal->cap_pin2 = (u8)xtal_calib[1]; 445 return iwl_calib_set(&priv->calib_results[IWL5000_CALIB_XTAL], 446 data, sizeof(data)); 447} 448 449static int iwl5000_send_calib_cfg(struct iwl_priv *priv) 450{ 451 struct iwl5000_calib_cfg_cmd calib_cfg_cmd; 452 struct iwl_host_cmd cmd = { 453 .id = CALIBRATION_CFG_CMD, 454 .len = sizeof(struct iwl5000_calib_cfg_cmd), 455 .data = &calib_cfg_cmd, 456 }; 457 458 memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd)); 459 calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL; 460 calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL; 461 calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL; 462 calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL; 463 464 return iwl_send_cmd(priv, &cmd); 465} 466 467static void iwl5000_rx_calib_result(struct iwl_priv *priv, 468 struct iwl_rx_mem_buffer *rxb) 469{ 470 struct iwl_rx_packet *pkt = (void *)rxb->skb->data; 471 struct iwl5000_calib_hdr *hdr = (struct iwl5000_calib_hdr *)pkt->u.raw; 472 int len = le32_to_cpu(pkt->len) & FH_RSCSR_FRAME_SIZE_MSK; 473 int index; 474 475 /* reduce the size of the length field itself */ 476 len -= 4; 477 478 /* Define the order in which the results will be sent to the runtime 479 * uCode. iwl_send_calib_results sends them in a row according to their 480 * index. We sort them here */ 481 switch (hdr->op_code) { 482 case IWL5000_PHY_CALIBRATE_LO_CMD: 483 index = IWL5000_CALIB_LO; 484 break; 485 case IWL5000_PHY_CALIBRATE_TX_IQ_CMD: 486 index = IWL5000_CALIB_TX_IQ; 487 break; 488 case IWL5000_PHY_CALIBRATE_TX_IQ_PERD_CMD: 489 index = IWL5000_CALIB_TX_IQ_PERD; 490 break; 491 default: 492 IWL_ERROR("Unknown calibration notification %d\n", 493 hdr->op_code); 494 return; 495 } 496 iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len); 497} 498 499static void iwl5000_rx_calib_complete(struct iwl_priv *priv, 500 struct iwl_rx_mem_buffer *rxb) 501{ 502 IWL_DEBUG_INFO("Init. calibration is completed, restarting fw.\n"); 503 queue_work(priv->workqueue, &priv->restart); 504} 505 506/* 507 * ucode 508 */ 509static int iwl5000_load_section(struct iwl_priv *priv, 510 struct fw_desc *image, 511 u32 dst_addr) 512{ 513 int ret = 0; 514 unsigned long flags; 515 516 dma_addr_t phy_addr = image->p_addr; 517 u32 byte_cnt = image->len; 518 519 spin_lock_irqsave(&priv->lock, flags); 520 ret = iwl_grab_nic_access(priv); 521 if (ret) { 522 spin_unlock_irqrestore(&priv->lock, flags); 523 return ret; 524 } 525 526 iwl_write_direct32(priv, 527 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 528 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); 529 530 iwl_write_direct32(priv, 531 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr); 532 533 iwl_write_direct32(priv, 534 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), 535 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); 536 537 iwl_write_direct32(priv, 538 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), 539 (iwl_get_dma_hi_addr(phy_addr) 540 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); 541 542 iwl_write_direct32(priv, 543 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), 544 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM | 545 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX | 546 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); 547 548 iwl_write_direct32(priv, 549 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 550 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 551 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL | 552 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); 553 554 iwl_release_nic_access(priv); 555 spin_unlock_irqrestore(&priv->lock, flags); 556 return 0; 557} 558 559static int iwl5000_load_given_ucode(struct iwl_priv *priv, 560 struct fw_desc *inst_image, 561 struct fw_desc *data_image) 562{ 563 int ret = 0; 564 565 ret = iwl5000_load_section( 566 priv, inst_image, RTC_INST_LOWER_BOUND); 567 if (ret) 568 return ret; 569 570 IWL_DEBUG_INFO("INST uCode section being loaded...\n"); 571 ret = wait_event_interruptible_timeout(priv->wait_command_queue, 572 priv->ucode_write_complete, 5 * HZ); 573 if (ret == -ERESTARTSYS) { 574 IWL_ERROR("Could not load the INST uCode section due " 575 "to interrupt\n"); 576 return ret; 577 } 578 if (!ret) { 579 IWL_ERROR("Could not load the INST uCode section\n"); 580 return -ETIMEDOUT; 581 } 582 583 priv->ucode_write_complete = 0; 584 585 ret = iwl5000_load_section( 586 priv, data_image, RTC_DATA_LOWER_BOUND); 587 if (ret) 588 return ret; 589 590 IWL_DEBUG_INFO("DATA uCode section being loaded...\n"); 591 592 ret = wait_event_interruptible_timeout(priv->wait_command_queue, 593 priv->ucode_write_complete, 5 * HZ); 594 if (ret == -ERESTARTSYS) { 595 IWL_ERROR("Could not load the INST uCode section due " 596 "to interrupt\n"); 597 return ret; 598 } else if (!ret) { 599 IWL_ERROR("Could not load the DATA uCode section\n"); 600 return -ETIMEDOUT; 601 } else 602 ret = 0; 603 604 priv->ucode_write_complete = 0; 605 606 return ret; 607} 608 609static int iwl5000_load_ucode(struct iwl_priv *priv) 610{ 611 int ret = 0; 612 613 /* check whether init ucode should be loaded, or rather runtime ucode */ 614 if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) { 615 IWL_DEBUG_INFO("Init ucode found. Loading init ucode...\n"); 616 ret = iwl5000_load_given_ucode(priv, 617 &priv->ucode_init, &priv->ucode_init_data); 618 if (!ret) { 619 IWL_DEBUG_INFO("Init ucode load complete.\n"); 620 priv->ucode_type = UCODE_INIT; 621 } 622 } else { 623 IWL_DEBUG_INFO("Init ucode not found, or already loaded. " 624 "Loading runtime ucode...\n"); 625 ret = iwl5000_load_given_ucode(priv, 626 &priv->ucode_code, &priv->ucode_data); 627 if (!ret) { 628 IWL_DEBUG_INFO("Runtime ucode load complete.\n"); 629 priv->ucode_type = UCODE_RT; 630 } 631 } 632 633 return ret; 634} 635 636static void iwl5000_init_alive_start(struct iwl_priv *priv) 637{ 638 int ret = 0; 639 640 /* Check alive response for "valid" sign from uCode */ 641 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) { 642 /* We had an error bringing up the hardware, so take it 643 * all the way back down so we can try again */ 644 IWL_DEBUG_INFO("Initialize Alive failed.\n"); 645 goto restart; 646 } 647 648 /* initialize uCode was loaded... verify inst image. 649 * This is a paranoid check, because we would not have gotten the 650 * "initialize" alive if code weren't properly loaded. */ 651 if (iwl_verify_ucode(priv)) { 652 /* Runtime instruction load was bad; 653 * take it all the way back down so we can try again */ 654 IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n"); 655 goto restart; 656 } 657 658 iwl_clear_stations_table(priv); 659 ret = priv->cfg->ops->lib->alive_notify(priv); 660 if (ret) { 661 IWL_WARNING("Could not complete ALIVE transition: %d\n", ret); 662 goto restart; 663 } 664 665 iwl5000_send_calib_cfg(priv); 666 return; 667 668restart: 669 /* real restart (first load init_ucode) */ 670 queue_work(priv->workqueue, &priv->restart); 671} 672 673static void iwl5000_set_wr_ptrs(struct iwl_priv *priv, 674 int txq_id, u32 index) 675{ 676 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 677 (index & 0xff) | (txq_id << 8)); 678 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index); 679} 680 681static void iwl5000_tx_queue_set_status(struct iwl_priv *priv, 682 struct iwl_tx_queue *txq, 683 int tx_fifo_id, int scd_retry) 684{ 685 int txq_id = txq->q.id; 686 int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0; 687 688 iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id), 689 (active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) | 690 (tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) | 691 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) | 692 IWL50_SCD_QUEUE_STTS_REG_MSK); 693 694 txq->sched_retry = scd_retry; 695 696 IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n", 697 active ? "Activate" : "Deactivate", 698 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id); 699} 700 701static int iwl5000_send_wimax_coex(struct iwl_priv *priv) 702{ 703 struct iwl_wimax_coex_cmd coex_cmd; 704 705 memset(&coex_cmd, 0, sizeof(coex_cmd)); 706 707 return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD, 708 sizeof(coex_cmd), &coex_cmd); 709} 710 711static int iwl5000_alive_notify(struct iwl_priv *priv) 712{ 713 u32 a; 714 int i = 0; 715 unsigned long flags; 716 int ret; 717 718 spin_lock_irqsave(&priv->lock, flags); 719 720 ret = iwl_grab_nic_access(priv); 721 if (ret) { 722 spin_unlock_irqrestore(&priv->lock, flags); 723 return ret; 724 } 725 726 priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR); 727 a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET; 728 for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET; 729 a += 4) 730 iwl_write_targ_mem(priv, a, 0); 731 for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET; 732 a += 4) 733 iwl_write_targ_mem(priv, a, 0); 734 for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4) 735 iwl_write_targ_mem(priv, a, 0); 736 737 iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR, 738 (priv->shared_phys + 739 offsetof(struct iwl5000_shared, queues_byte_cnt_tbls)) >> 10); 740 iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, 741 IWL50_SCD_QUEUECHAIN_SEL_ALL( 742 priv->hw_params.max_txq_num)); 743 iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0); 744 745 /* initiate the queues */ 746 for (i = 0; i < priv->hw_params.max_txq_num; i++) { 747 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0); 748 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8)); 749 iwl_write_targ_mem(priv, priv->scd_base_addr + 750 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0); 751 iwl_write_targ_mem(priv, priv->scd_base_addr + 752 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) + 753 sizeof(u32), 754 ((SCD_WIN_SIZE << 755 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & 756 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | 757 ((SCD_FRAME_LIMIT << 758 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & 759 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); 760 } 761 762 iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK, 763 IWL_MASK(0, priv->hw_params.max_txq_num)); 764 765 /* Activate all Tx DMA/FIFO channels */ 766 priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7)); 767 768 iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0); 769 /* map qos queues to fifos one-to-one */ 770 for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) { 771 int ac = iwl5000_default_queue_to_tx_fifo[i]; 772 iwl_txq_ctx_activate(priv, i); 773 iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0); 774 } 775 /* TODO - need to initialize those FIFOs inside the loop above, 776 * not only mark them as active */ 777 iwl_txq_ctx_activate(priv, 4); 778 iwl_txq_ctx_activate(priv, 7); 779 iwl_txq_ctx_activate(priv, 8); 780 iwl_txq_ctx_activate(priv, 9); 781 782 iwl_release_nic_access(priv); 783 spin_unlock_irqrestore(&priv->lock, flags); 784 785 786 iwl5000_send_wimax_coex(priv); 787 788 iwl5000_set_Xtal_calib(priv); 789 iwl_send_calib_results(priv); 790 791 return 0; 792} 793 794static int iwl5000_hw_set_hw_params(struct iwl_priv *priv) 795{ 796 if ((priv->cfg->mod_params->num_of_queues > IWL50_NUM_QUEUES) || 797 (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) { 798 IWL_ERROR("invalid queues_num, should be between %d and %d\n", 799 IWL_MIN_NUM_QUEUES, IWL50_NUM_QUEUES); 800 return -EINVAL; 801 } 802 803 priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues; 804 priv->hw_params.first_ampdu_q = IWL50_FIRST_AMPDU_QUEUE; 805 priv->hw_params.max_stations = IWL5000_STATION_COUNT; 806 priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID; 807 priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE; 808 priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE; 809 priv->hw_params.max_bsm_size = 0; 810 priv->hw_params.fat_channel = BIT(IEEE80211_BAND_2GHZ) | 811 BIT(IEEE80211_BAND_5GHZ); 812 priv->hw_params.sens = &iwl5000_sensitivity; 813 814 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) { 815 case CSR_HW_REV_TYPE_5100: 816 priv->hw_params.tx_chains_num = 1; 817 priv->hw_params.rx_chains_num = 2; 818 priv->hw_params.valid_tx_ant = ANT_B; 819 priv->hw_params.valid_rx_ant = ANT_AB; 820 break; 821 case CSR_HW_REV_TYPE_5150: 822 priv->hw_params.tx_chains_num = 1; 823 priv->hw_params.rx_chains_num = 2; 824 priv->hw_params.valid_tx_ant = ANT_A; 825 priv->hw_params.valid_rx_ant = ANT_AB; 826 break; 827 case CSR_HW_REV_TYPE_5300: 828 case CSR_HW_REV_TYPE_5350: 829 priv->hw_params.tx_chains_num = 3; 830 priv->hw_params.rx_chains_num = 3; 831 priv->hw_params.valid_tx_ant = ANT_ABC; 832 priv->hw_params.valid_rx_ant = ANT_ABC; 833 break; 834 } 835 836 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) { 837 case CSR_HW_REV_TYPE_5100: 838 case CSR_HW_REV_TYPE_5300: 839 case CSR_HW_REV_TYPE_5350: 840 /* 5X00 and 5350 wants in Celsius */ 841 priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD; 842 break; 843 case CSR_HW_REV_TYPE_5150: 844 /* 5150 wants in Kelvin */ 845 priv->hw_params.ct_kill_threshold = 846 CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD); 847 break; 848 } 849 850 /* Set initial calibration set */ 851 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) { 852 case CSR_HW_REV_TYPE_5100: 853 case CSR_HW_REV_TYPE_5300: 854 case CSR_HW_REV_TYPE_5350: 855 priv->hw_params.calib_init_cfg = 856 BIT(IWL5000_CALIB_XTAL) | 857 BIT(IWL5000_CALIB_LO) | 858 BIT(IWL5000_CALIB_TX_IQ) | 859 BIT(IWL5000_CALIB_TX_IQ_PERD); 860 break; 861 case CSR_HW_REV_TYPE_5150: 862 priv->hw_params.calib_init_cfg = 0; 863 break; 864 } 865 866 867 return 0; 868} 869 870static int iwl5000_alloc_shared_mem(struct iwl_priv *priv) 871{ 872 priv->shared_virt = pci_alloc_consistent(priv->pci_dev, 873 sizeof(struct iwl5000_shared), 874 &priv->shared_phys); 875 if (!priv->shared_virt) 876 return -ENOMEM; 877 878 memset(priv->shared_virt, 0, sizeof(struct iwl5000_shared)); 879 880 priv->rb_closed_offset = offsetof(struct iwl5000_shared, rb_closed); 881 882 return 0; 883} 884 885static void iwl5000_free_shared_mem(struct iwl_priv *priv) 886{ 887 if (priv->shared_virt) 888 pci_free_consistent(priv->pci_dev, 889 sizeof(struct iwl5000_shared), 890 priv->shared_virt, 891 priv->shared_phys); 892} 893 894static int iwl5000_shared_mem_rx_idx(struct iwl_priv *priv) 895{ 896 struct iwl5000_shared *s = priv->shared_virt; 897 return le32_to_cpu(s->rb_closed) & 0xFFF; 898} 899 900/** 901 * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array 902 */ 903static void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv, 904 struct iwl_tx_queue *txq, 905 u16 byte_cnt) 906{ 907 struct iwl5000_shared *shared_data = priv->shared_virt; 908 int txq_id = txq->q.id; 909 u8 sec_ctl = 0; 910 u8 sta = 0; 911 int len; 912 913 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE; 914 915 if (txq_id != IWL_CMD_QUEUE_NUM) { 916 sta = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id; 917 sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl; 918 919 switch (sec_ctl & TX_CMD_SEC_MSK) { 920 case TX_CMD_SEC_CCM: 921 len += CCMP_MIC_LEN; 922 break; 923 case TX_CMD_SEC_TKIP: 924 len += TKIP_ICV_LEN; 925 break; 926 case TX_CMD_SEC_WEP: 927 len += WEP_IV_LEN + WEP_ICV_LEN; 928 break; 929 } 930 } 931 932 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id]. 933 tfd_offset[txq->q.write_ptr], byte_cnt, len); 934 935 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id]. 936 tfd_offset[txq->q.write_ptr], sta_id, sta); 937 938 if (txq->q.write_ptr < IWL50_MAX_WIN_SIZE) { 939 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id]. 940 tfd_offset[IWL50_QUEUE_SIZE + txq->q.write_ptr], 941 byte_cnt, len); 942 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id]. 943 tfd_offset[IWL50_QUEUE_SIZE + txq->q.write_ptr], 944 sta_id, sta); 945 } 946} 947 948static void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv, 949 struct iwl_tx_queue *txq) 950{ 951 int txq_id = txq->q.id; 952 struct iwl5000_shared *shared_data = priv->shared_virt; 953 u8 sta = 0; 954 955 if (txq_id != IWL_CMD_QUEUE_NUM) 956 sta = txq->cmd[txq->q.read_ptr]->cmd.tx.sta_id; 957 958 shared_data->queues_byte_cnt_tbls[txq_id].tfd_offset[txq->q.read_ptr]. 959 val = cpu_to_le16(1 | (sta << 12)); 960 961 if (txq->q.write_ptr < IWL50_MAX_WIN_SIZE) { 962 shared_data->queues_byte_cnt_tbls[txq_id]. 963 tfd_offset[IWL50_QUEUE_SIZE + txq->q.read_ptr]. 964 val = cpu_to_le16(1 | (sta << 12)); 965 } 966} 967 968static int iwl5000_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid, 969 u16 txq_id) 970{ 971 u32 tbl_dw_addr; 972 u32 tbl_dw; 973 u16 scd_q2ratid; 974 975 scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK; 976 977 tbl_dw_addr = priv->scd_base_addr + 978 IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id); 979 980 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr); 981 982 if (txq_id & 0x1) 983 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF); 984 else 985 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000); 986 987 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw); 988 989 return 0; 990} 991static void iwl5000_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id) 992{ 993 /* Simply stop the queue, but don't change any configuration; 994 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */ 995 iwl_write_prph(priv, 996 IWL50_SCD_QUEUE_STATUS_BITS(txq_id), 997 (0 << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE)| 998 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN)); 999} 1000 1001static int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id, 1002 int tx_fifo, int sta_id, int tid, u16 ssn_idx) 1003{ 1004 unsigned long flags; 1005 int ret; 1006 u16 ra_tid; 1007 1008 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) || 1009 (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) { 1010 IWL_WARNING("queue number out of range: %d, must be %d to %d\n", 1011 txq_id, IWL50_FIRST_AMPDU_QUEUE, 1012 IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1); 1013 return -EINVAL; 1014 } 1015 1016 ra_tid = BUILD_RAxTID(sta_id, tid); 1017 1018 /* Modify device's station table to Tx this TID */ 1019 iwl_sta_modify_enable_tid_tx(priv, sta_id, tid); 1020 1021 spin_lock_irqsave(&priv->lock, flags); 1022 ret = iwl_grab_nic_access(priv); 1023 if (ret) { 1024 spin_unlock_irqrestore(&priv->lock, flags); 1025 return ret; 1026 } 1027 1028 /* Stop this Tx queue before configuring it */ 1029 iwl5000_tx_queue_stop_scheduler(priv, txq_id); 1030 1031 /* Map receiver-address / traffic-ID to this queue */ 1032 iwl5000_tx_queue_set_q2ratid(priv, ra_tid, txq_id); 1033 1034 /* Set this queue as a chain-building queue */ 1035 iwl_set_bits_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, (1<<txq_id)); 1036 1037 /* enable aggregations for the queue */ 1038 iwl_set_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1<<txq_id)); 1039 1040 /* Place first TFD at index corresponding to start sequence number. 1041 * Assumes that ssn_idx is valid (!= 0xFFF) */ 1042 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff); 1043 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff); 1044 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx); 1045 1046 /* Set up Tx window size and frame limit for this queue */ 1047 iwl_write_targ_mem(priv, priv->scd_base_addr + 1048 IWL50_SCD_CONTEXT_QUEUE_OFFSET(txq_id) + 1049 sizeof(u32), 1050 ((SCD_WIN_SIZE << 1051 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & 1052 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | 1053 ((SCD_FRAME_LIMIT << 1054 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & 1055 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); 1056 1057 iwl_set_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id)); 1058 1059 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */ 1060 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1); 1061 1062 iwl_release_nic_access(priv); 1063 spin_unlock_irqrestore(&priv->lock, flags); 1064 1065 return 0; 1066} 1067 1068static int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id, 1069 u16 ssn_idx, u8 tx_fifo) 1070{ 1071 int ret; 1072 1073 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) || 1074 (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) { 1075 IWL_WARNING("queue number out of range: %d, must be %d to %d\n", 1076 txq_id, IWL50_FIRST_AMPDU_QUEUE, 1077 IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1); 1078 return -EINVAL; 1079 } 1080 1081 ret = iwl_grab_nic_access(priv); 1082 if (ret) 1083 return ret; 1084 1085 iwl5000_tx_queue_stop_scheduler(priv, txq_id); 1086 1087 iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id)); 1088 1089 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff); 1090 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff); 1091 /* supposes that ssn_idx is valid (!= 0xFFF) */ 1092 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx); 1093 1094 iwl_clear_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id)); 1095 iwl_txq_ctx_deactivate(priv, txq_id); 1096 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0); 1097 1098 iwl_release_nic_access(priv); 1099 1100 return 0; 1101} 1102 1103static u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data) 1104{ 1105 u16 size = (u16)sizeof(struct iwl_addsta_cmd); 1106 memcpy(data, cmd, size); 1107 return size; 1108} 1109 1110 1111/* 1112 * Activate/Deactivat Tx DMA/FIFO channels according tx fifos mask 1113 * must be called under priv->lock and mac access 1114 */ 1115static void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask) 1116{ 1117 iwl_write_prph(priv, IWL50_SCD_TXFACT, mask); 1118} 1119 1120 1121static inline u32 iwl5000_get_scd_ssn(struct iwl5000_tx_resp *tx_resp) 1122{ 1123 return le32_to_cpup((__le32 *)&tx_resp->status + 1124 tx_resp->frame_count) & MAX_SN; 1125} 1126 1127static int iwl5000_tx_status_reply_tx(struct iwl_priv *priv, 1128 struct iwl_ht_agg *agg, 1129 struct iwl5000_tx_resp *tx_resp, 1130 int txq_id, u16 start_idx) 1131{ 1132 u16 status; 1133 struct agg_tx_status *frame_status = &tx_resp->status; 1134 struct ieee80211_tx_info *info = NULL; 1135 struct ieee80211_hdr *hdr = NULL; 1136 u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags); 1137 int i, sh, idx; 1138 u16 seq; 1139 1140 if (agg->wait_for_ba) 1141 IWL_DEBUG_TX_REPLY("got tx response w/o block-ack\n"); 1142 1143 agg->frame_count = tx_resp->frame_count; 1144 agg->start_idx = start_idx; 1145 agg->rate_n_flags = rate_n_flags; 1146 agg->bitmap = 0; 1147 1148 /* # frames attempted by Tx command */ 1149 if (agg->frame_count == 1) { 1150 /* Only one frame was attempted; no block-ack will arrive */ 1151 status = le16_to_cpu(frame_status[0].status); 1152 idx = start_idx; 1153 1154 /* FIXME: code repetition */ 1155 IWL_DEBUG_TX_REPLY("FrameCnt = %d, StartIdx=%d idx=%d\n", 1156 agg->frame_count, agg->start_idx, idx); 1157 1158 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]); 1159 info->status.rates[0].count = tx_resp->failure_frame + 1; 1160 info->flags &= ~IEEE80211_TX_CTL_AMPDU; 1161 info->flags |= iwl_is_tx_success(status)? 1162 IEEE80211_TX_STAT_ACK : 0; 1163 iwl_hwrate_to_tx_control(priv, rate_n_flags, info); 1164 1165 /* FIXME: code repetition end */ 1166 1167 IWL_DEBUG_TX_REPLY("1 Frame 0x%x failure :%d\n", 1168 status & 0xff, tx_resp->failure_frame); 1169 IWL_DEBUG_TX_REPLY("Rate Info rate_n_flags=%x\n", rate_n_flags); 1170 1171 agg->wait_for_ba = 0; 1172 } else { 1173 /* Two or more frames were attempted; expect block-ack */ 1174 u64 bitmap = 0; 1175 int start = agg->start_idx; 1176 1177 /* Construct bit-map of pending frames within Tx window */ 1178 for (i = 0; i < agg->frame_count; i++) { 1179 u16 sc; 1180 status = le16_to_cpu(frame_status[i].status); 1181 seq = le16_to_cpu(frame_status[i].sequence); 1182 idx = SEQ_TO_INDEX(seq); 1183 txq_id = SEQ_TO_QUEUE(seq); 1184 1185 if (status & (AGG_TX_STATE_FEW_BYTES_MSK | 1186 AGG_TX_STATE_ABORT_MSK)) 1187 continue; 1188 1189 IWL_DEBUG_TX_REPLY("FrameCnt = %d, txq_id=%d idx=%d\n", 1190 agg->frame_count, txq_id, idx); 1191 1192 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx); 1193 1194 sc = le16_to_cpu(hdr->seq_ctrl); 1195 if (idx != (SEQ_TO_SN(sc) & 0xff)) { 1196 IWL_ERROR("BUG_ON idx doesn't match seq control" 1197 " idx=%d, seq_idx=%d, seq=%d\n", 1198 idx, SEQ_TO_SN(sc), 1199 hdr->seq_ctrl); 1200 return -1; 1201 } 1202 1203 IWL_DEBUG_TX_REPLY("AGG Frame i=%d idx %d seq=%d\n", 1204 i, idx, SEQ_TO_SN(sc)); 1205 1206 sh = idx - start; 1207 if (sh > 64) { 1208 sh = (start - idx) + 0xff; 1209 bitmap = bitmap << sh; 1210 sh = 0; 1211 start = idx; 1212 } else if (sh < -64) 1213 sh = 0xff - (start - idx); 1214 else if (sh < 0) { 1215 sh = start - idx; 1216 start = idx; 1217 bitmap = bitmap << sh; 1218 sh = 0; 1219 } 1220 bitmap |= 1ULL << sh; 1221 IWL_DEBUG_TX_REPLY("start=%d bitmap=0x%llx\n", 1222 start, (unsigned long long)bitmap); 1223 } 1224 1225 agg->bitmap = bitmap; 1226 agg->start_idx = start; 1227 IWL_DEBUG_TX_REPLY("Frames %d start_idx=%d bitmap=0x%llx\n", 1228 agg->frame_count, agg->start_idx, 1229 (unsigned long long)agg->bitmap); 1230 1231 if (bitmap) 1232 agg->wait_for_ba = 1; 1233 } 1234 return 0; 1235} 1236 1237static void iwl5000_rx_reply_tx(struct iwl_priv *priv, 1238 struct iwl_rx_mem_buffer *rxb) 1239{ 1240 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; 1241 u16 sequence = le16_to_cpu(pkt->hdr.sequence); 1242 int txq_id = SEQ_TO_QUEUE(sequence); 1243 int index = SEQ_TO_INDEX(sequence); 1244 struct iwl_tx_queue *txq = &priv->txq[txq_id]; 1245 struct ieee80211_tx_info *info; 1246 struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0]; 1247 u32 status = le16_to_cpu(tx_resp->status.status); 1248 int tid = MAX_TID_COUNT, sta_id = IWL_INVALID_STATION; 1249 struct ieee80211_hdr *hdr; 1250 u8 *qc = NULL; 1251 1252 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) { 1253 IWL_ERROR("Read index for DMA queue txq_id (%d) index %d " 1254 "is out of range [0-%d] %d %d\n", txq_id, 1255 index, txq->q.n_bd, txq->q.write_ptr, 1256 txq->q.read_ptr); 1257 return; 1258 } 1259 1260 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]); 1261 memset(&info->status, 0, sizeof(info->status)); 1262 1263 hdr = iwl_tx_queue_get_hdr(priv, txq_id, index); 1264 if (ieee80211_is_data_qos(hdr->frame_control)) { 1265 qc = ieee80211_get_qos_ctl(hdr); 1266 tid = qc[0] & 0xf; 1267 } 1268 1269 sta_id = iwl_get_ra_sta_id(priv, hdr); 1270 if (txq->sched_retry && unlikely(sta_id == IWL_INVALID_STATION)) { 1271 IWL_ERROR("Station not known\n"); 1272 return; 1273 } 1274 1275 if (txq->sched_retry) { 1276 const u32 scd_ssn = iwl5000_get_scd_ssn(tx_resp); 1277 struct iwl_ht_agg *agg = NULL; 1278 1279 if (!qc) 1280 return; 1281 1282 agg = &priv->stations[sta_id].tid[tid].agg; 1283 1284 iwl5000_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index); 1285 1286 /* check if BAR is needed */ 1287 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status)) 1288 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK; 1289 1290 if (txq->q.read_ptr != (scd_ssn & 0xff)) { 1291 int freed, ampdu_q; 1292 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd); 1293 IWL_DEBUG_TX_REPLY("Retry scheduler reclaim scd_ssn " 1294 "%d index %d\n", scd_ssn , index); 1295 freed = iwl_tx_queue_reclaim(priv, txq_id, index); 1296 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed; 1297 1298 if (iwl_queue_space(&txq->q) > txq->q.low_mark && 1299 txq_id >= 0 && priv->mac80211_registered && 1300 agg->state != IWL_EMPTYING_HW_QUEUE_DELBA) { 1301 /* calculate mac80211 ampdu sw queue to wake */ 1302 ampdu_q = txq_id - IWL50_FIRST_AMPDU_QUEUE + 1303 priv->hw->queues; 1304 if (agg->state == IWL_AGG_OFF) 1305 ieee80211_wake_queue(priv->hw, txq_id); 1306 else 1307 ieee80211_wake_queue(priv->hw, ampdu_q); 1308 } 1309 iwl_txq_check_empty(priv, sta_id, tid, txq_id); 1310 } 1311 } else { 1312 info->status.rates[0].count = tx_resp->failure_frame + 1; 1313 info->flags = 1314 iwl_is_tx_success(status) ? IEEE80211_TX_STAT_ACK : 0; 1315 iwl_hwrate_to_tx_control(priv, 1316 le32_to_cpu(tx_resp->rate_n_flags), 1317 info); 1318 1319 IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) rate_n_flags " 1320 "0x%x retries %d\n", txq_id, 1321 iwl_get_tx_fail_reason(status), 1322 status, le32_to_cpu(tx_resp->rate_n_flags), 1323 tx_resp->failure_frame); 1324 1325 IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index); 1326 if (index != -1) { 1327 int freed = iwl_tx_queue_reclaim(priv, txq_id, index); 1328 if (tid != MAX_TID_COUNT) 1329 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed; 1330 if (iwl_queue_space(&txq->q) > txq->q.low_mark && 1331 (txq_id >= 0) && priv->mac80211_registered) 1332 ieee80211_wake_queue(priv->hw, txq_id); 1333 if (tid != MAX_TID_COUNT) 1334 iwl_txq_check_empty(priv, sta_id, tid, txq_id); 1335 } 1336 } 1337 1338 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK)) 1339 IWL_ERROR("TODO: Implement Tx ABORT REQUIRED!!!\n"); 1340} 1341 1342/* Currently 5000 is the supperset of everything */ 1343static u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len) 1344{ 1345 return len; 1346} 1347 1348static void iwl5000_setup_deferred_work(struct iwl_priv *priv) 1349{ 1350 /* in 5000 the tx power calibration is done in uCode */ 1351 priv->disable_tx_power_cal = 1; 1352} 1353 1354static void iwl5000_rx_handler_setup(struct iwl_priv *priv) 1355{ 1356 /* init calibration handlers */ 1357 priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] = 1358 iwl5000_rx_calib_result; 1359 priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] = 1360 iwl5000_rx_calib_complete; 1361 priv->rx_handlers[REPLY_TX] = iwl5000_rx_reply_tx; 1362} 1363 1364 1365static int iwl5000_hw_valid_rtc_data_addr(u32 addr) 1366{ 1367 return (addr >= RTC_DATA_LOWER_BOUND) && 1368 (addr < IWL50_RTC_DATA_UPPER_BOUND); 1369} 1370 1371static int iwl5000_send_rxon_assoc(struct iwl_priv *priv) 1372{ 1373 int ret = 0; 1374 struct iwl5000_rxon_assoc_cmd rxon_assoc; 1375 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon; 1376 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon; 1377 1378 if ((rxon1->flags == rxon2->flags) && 1379 (rxon1->filter_flags == rxon2->filter_flags) && 1380 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) && 1381 (rxon1->ofdm_ht_single_stream_basic_rates == 1382 rxon2->ofdm_ht_single_stream_basic_rates) && 1383 (rxon1->ofdm_ht_dual_stream_basic_rates == 1384 rxon2->ofdm_ht_dual_stream_basic_rates) && 1385 (rxon1->ofdm_ht_triple_stream_basic_rates == 1386 rxon2->ofdm_ht_triple_stream_basic_rates) && 1387 (rxon1->acquisition_data == rxon2->acquisition_data) && 1388 (rxon1->rx_chain == rxon2->rx_chain) && 1389 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) { 1390 IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n"); 1391 return 0; 1392 } 1393 1394 rxon_assoc.flags = priv->staging_rxon.flags; 1395 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags; 1396 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates; 1397 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates; 1398 rxon_assoc.reserved1 = 0; 1399 rxon_assoc.reserved2 = 0; 1400 rxon_assoc.reserved3 = 0; 1401 rxon_assoc.ofdm_ht_single_stream_basic_rates = 1402 priv->staging_rxon.ofdm_ht_single_stream_basic_rates; 1403 rxon_assoc.ofdm_ht_dual_stream_basic_rates = 1404 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates; 1405 rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain; 1406 rxon_assoc.ofdm_ht_triple_stream_basic_rates = 1407 priv->staging_rxon.ofdm_ht_triple_stream_basic_rates; 1408 rxon_assoc.acquisition_data = priv->staging_rxon.acquisition_data; 1409 1410 ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC, 1411 sizeof(rxon_assoc), &rxon_assoc, NULL); 1412 if (ret) 1413 return ret; 1414 1415 return ret; 1416} 1417static int iwl5000_send_tx_power(struct iwl_priv *priv) 1418{ 1419 struct iwl5000_tx_power_dbm_cmd tx_power_cmd; 1420 1421 /* half dBm need to multiply */ 1422 tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt); 1423 tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED; 1424 tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO; 1425 return iwl_send_cmd_pdu_async(priv, REPLY_TX_POWER_DBM_CMD, 1426 sizeof(tx_power_cmd), &tx_power_cmd, 1427 NULL); 1428} 1429 1430static void iwl5000_temperature(struct iwl_priv *priv) 1431{ 1432 /* store temperature from statistics (in Celsius) */ 1433 priv->temperature = le32_to_cpu(priv->statistics.general.temperature); 1434} 1435 1436/* Calc max signal level (dBm) among 3 possible receivers */ 1437static int iwl5000_calc_rssi(struct iwl_priv *priv, 1438 struct iwl_rx_phy_res *rx_resp) 1439{ 1440 /* data from PHY/DSP regarding signal strength, etc., 1441 * contents are always there, not configurable by host 1442 */ 1443 struct iwl5000_non_cfg_phy *ncphy = 1444 (struct iwl5000_non_cfg_phy *)rx_resp->non_cfg_phy_buf; 1445 u32 val, rssi_a, rssi_b, rssi_c, max_rssi; 1446 u8 agc; 1447 1448 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_AGC_IDX]); 1449 agc = (val & IWL50_OFDM_AGC_MSK) >> IWL50_OFDM_AGC_BIT_POS; 1450 1451 /* Find max rssi among 3 possible receivers. 1452 * These values are measured by the digital signal processor (DSP). 1453 * They should stay fairly constant even as the signal strength varies, 1454 * if the radio's automatic gain control (AGC) is working right. 1455 * AGC value (see below) will provide the "interesting" info. 1456 */ 1457 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_AB_IDX]); 1458 rssi_a = (val & IWL50_OFDM_RSSI_A_MSK) >> IWL50_OFDM_RSSI_A_BIT_POS; 1459 rssi_b = (val & IWL50_OFDM_RSSI_B_MSK) >> IWL50_OFDM_RSSI_B_BIT_POS; 1460 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_C_IDX]); 1461 rssi_c = (val & IWL50_OFDM_RSSI_C_MSK) >> IWL50_OFDM_RSSI_C_BIT_POS; 1462 1463 max_rssi = max_t(u32, rssi_a, rssi_b); 1464 max_rssi = max_t(u32, max_rssi, rssi_c); 1465 1466 IWL_DEBUG_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n", 1467 rssi_a, rssi_b, rssi_c, max_rssi, agc); 1468 1469 /* dBm = max_rssi dB - agc dB - constant. 1470 * Higher AGC (higher radio gain) means lower signal. */ 1471 return max_rssi - agc - IWL_RSSI_OFFSET; 1472} 1473 1474static struct iwl_hcmd_ops iwl5000_hcmd = { 1475 .rxon_assoc = iwl5000_send_rxon_assoc, 1476}; 1477 1478static struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = { 1479 .get_hcmd_size = iwl5000_get_hcmd_size, 1480 .build_addsta_hcmd = iwl5000_build_addsta_hcmd, 1481 .gain_computation = iwl5000_gain_computation, 1482 .chain_noise_reset = iwl5000_chain_noise_reset, 1483 .rts_tx_cmd_flag = iwl5000_rts_tx_cmd_flag, 1484 .calc_rssi = iwl5000_calc_rssi, 1485}; 1486 1487static struct iwl_lib_ops iwl5000_lib = { 1488 .set_hw_params = iwl5000_hw_set_hw_params, 1489 .alloc_shared_mem = iwl5000_alloc_shared_mem, 1490 .free_shared_mem = iwl5000_free_shared_mem, 1491 .shared_mem_rx_idx = iwl5000_shared_mem_rx_idx, 1492 .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl, 1493 .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl, 1494 .txq_set_sched = iwl5000_txq_set_sched, 1495 .txq_agg_enable = iwl5000_txq_agg_enable, 1496 .txq_agg_disable = iwl5000_txq_agg_disable, 1497 .rx_handler_setup = iwl5000_rx_handler_setup, 1498 .setup_deferred_work = iwl5000_setup_deferred_work, 1499 .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr, 1500 .load_ucode = iwl5000_load_ucode, 1501 .init_alive_start = iwl5000_init_alive_start, 1502 .alive_notify = iwl5000_alive_notify, 1503 .send_tx_power = iwl5000_send_tx_power, 1504 .temperature = iwl5000_temperature, 1505 .update_chain_flags = iwl4965_update_chain_flags, 1506 .apm_ops = { 1507 .init = iwl5000_apm_init, 1508 .reset = iwl5000_apm_reset, 1509 .stop = iwl5000_apm_stop, 1510 .config = iwl5000_nic_config, 1511 .set_pwr_src = iwl4965_set_pwr_src, 1512 }, 1513 .eeprom_ops = { 1514 .regulatory_bands = { 1515 EEPROM_5000_REG_BAND_1_CHANNELS, 1516 EEPROM_5000_REG_BAND_2_CHANNELS, 1517 EEPROM_5000_REG_BAND_3_CHANNELS, 1518 EEPROM_5000_REG_BAND_4_CHANNELS, 1519 EEPROM_5000_REG_BAND_5_CHANNELS, 1520 EEPROM_5000_REG_BAND_24_FAT_CHANNELS, 1521 EEPROM_5000_REG_BAND_52_FAT_CHANNELS 1522 }, 1523 .verify_signature = iwlcore_eeprom_verify_signature, 1524 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore, 1525 .release_semaphore = iwlcore_eeprom_release_semaphore, 1526 .check_version = iwl5000_eeprom_check_version, 1527 .query_addr = iwl5000_eeprom_query_addr, 1528 }, 1529}; 1530 1531static struct iwl_ops iwl5000_ops = { 1532 .lib = &iwl5000_lib, 1533 .hcmd = &iwl5000_hcmd, 1534 .utils = &iwl5000_hcmd_utils, 1535}; 1536 1537static struct iwl_mod_params iwl50_mod_params = { 1538 .num_of_queues = IWL50_NUM_QUEUES, 1539 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES, 1540 .enable_qos = 1, 1541 .amsdu_size_8K = 1, 1542 .restart_fw = 1, 1543 /* the rest are 0 by default */ 1544}; 1545 1546 1547struct iwl_cfg iwl5300_agn_cfg = { 1548 .name = "5300AGN", 1549 .fw_name = IWL5000_MODULE_FIRMWARE, 1550 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N, 1551 .ops = &iwl5000_ops, 1552 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, 1553 .mod_params = &iwl50_mod_params, 1554}; 1555 1556struct iwl_cfg iwl5100_bg_cfg = { 1557 .name = "5100BG", 1558 .fw_name = IWL5000_MODULE_FIRMWARE, 1559 .sku = IWL_SKU_G, 1560 .ops = &iwl5000_ops, 1561 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, 1562 .mod_params = &iwl50_mod_params, 1563}; 1564 1565struct iwl_cfg iwl5100_abg_cfg = { 1566 .name = "5100ABG", 1567 .fw_name = IWL5000_MODULE_FIRMWARE, 1568 .sku = IWL_SKU_A|IWL_SKU_G, 1569 .ops = &iwl5000_ops, 1570 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, 1571 .mod_params = &iwl50_mod_params, 1572}; 1573 1574struct iwl_cfg iwl5100_agn_cfg = { 1575 .name = "5100AGN", 1576 .fw_name = IWL5000_MODULE_FIRMWARE, 1577 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N, 1578 .ops = &iwl5000_ops, 1579 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, 1580 .mod_params = &iwl50_mod_params, 1581}; 1582 1583struct iwl_cfg iwl5350_agn_cfg = { 1584 .name = "5350AGN", 1585 .fw_name = IWL5000_MODULE_FIRMWARE, 1586 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N, 1587 .ops = &iwl5000_ops, 1588 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, 1589 .mod_params = &iwl50_mod_params, 1590}; 1591 1592MODULE_FIRMWARE(IWL5000_MODULE_FIRMWARE); 1593 1594module_param_named(disable50, iwl50_mod_params.disable, int, 0444); 1595MODULE_PARM_DESC(disable50, 1596 "manually disable the 50XX radio (default 0 [radio on])"); 1597module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, 0444); 1598MODULE_PARM_DESC(swcrypto50, 1599 "using software crypto engine (default 0 [hardware])\n"); 1600module_param_named(debug50, iwl50_mod_params.debug, int, 0444); 1601MODULE_PARM_DESC(debug50, "50XX debug output mask"); 1602module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, 0444); 1603MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series"); 1604module_param_named(qos_enable50, iwl50_mod_params.enable_qos, int, 0444); 1605MODULE_PARM_DESC(qos_enable50, "enable all 50XX QoS functionality"); 1606module_param_named(11n_disable50, iwl50_mod_params.disable_11n, int, 0444); 1607MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality"); 1608module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K, int, 0444); 1609MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series"); 1610module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, 0444); 1611MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error"); 1612