iwl-5000.c revision a8b50a0a966d7ac313f624c6ab4996231a5fe25a
1/****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2009 Intel Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * The full GNU General Public License is included in this distribution in the 19 * file called LICENSE. 20 * 21 * Contact Information: 22 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 23 * 24 *****************************************************************************/ 25 26#include <linux/kernel.h> 27#include <linux/module.h> 28#include <linux/init.h> 29#include <linux/pci.h> 30#include <linux/dma-mapping.h> 31#include <linux/delay.h> 32#include <linux/skbuff.h> 33#include <linux/netdevice.h> 34#include <linux/wireless.h> 35#include <net/mac80211.h> 36#include <linux/etherdevice.h> 37#include <asm/unaligned.h> 38 39#include "iwl-eeprom.h" 40#include "iwl-dev.h" 41#include "iwl-core.h" 42#include "iwl-io.h" 43#include "iwl-sta.h" 44#include "iwl-helpers.h" 45#include "iwl-5000-hw.h" 46#include "iwl-6000-hw.h" 47 48/* Highest firmware API version supported */ 49#define IWL5000_UCODE_API_MAX 1 50#define IWL5150_UCODE_API_MAX 2 51 52/* Lowest firmware API version supported */ 53#define IWL5000_UCODE_API_MIN 1 54#define IWL5150_UCODE_API_MIN 1 55 56#define IWL5000_FW_PRE "iwlwifi-5000-" 57#define _IWL5000_MODULE_FIRMWARE(api) IWL5000_FW_PRE #api ".ucode" 58#define IWL5000_MODULE_FIRMWARE(api) _IWL5000_MODULE_FIRMWARE(api) 59 60#define IWL5150_FW_PRE "iwlwifi-5150-" 61#define _IWL5150_MODULE_FIRMWARE(api) IWL5150_FW_PRE #api ".ucode" 62#define IWL5150_MODULE_FIRMWARE(api) _IWL5150_MODULE_FIRMWARE(api) 63 64static const u16 iwl5000_default_queue_to_tx_fifo[] = { 65 IWL_TX_FIFO_AC3, 66 IWL_TX_FIFO_AC2, 67 IWL_TX_FIFO_AC1, 68 IWL_TX_FIFO_AC0, 69 IWL50_CMD_FIFO_NUM, 70 IWL_TX_FIFO_HCCA_1, 71 IWL_TX_FIFO_HCCA_2 72}; 73 74/* FIXME: same implementation as 4965 */ 75static int iwl5000_apm_stop_master(struct iwl_priv *priv) 76{ 77 unsigned long flags; 78 79 spin_lock_irqsave(&priv->lock, flags); 80 81 /* set stop master bit */ 82 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); 83 84 iwl_poll_direct_bit(priv, CSR_RESET, 85 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); 86 87 spin_unlock_irqrestore(&priv->lock, flags); 88 IWL_DEBUG_INFO(priv, "stop master\n"); 89 90 return 0; 91} 92 93 94static int iwl5000_apm_init(struct iwl_priv *priv) 95{ 96 int ret = 0; 97 98 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS, 99 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 100 101 /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */ 102 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS, 103 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 104 105 /* Set FH wait threshold to maximum (HW error during stress W/A) */ 106 iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); 107 108 /* enable HAP INTA to move device L1a -> L0s */ 109 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, 110 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); 111 112 if (priv->cfg->need_pll_cfg) 113 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); 114 115 /* set "initialization complete" bit to move adapter 116 * D0U* --> D0A* state */ 117 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 118 119 /* wait for clock stabilization */ 120 ret = iwl_poll_direct_bit(priv, CSR_GP_CNTRL, 121 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); 122 if (ret < 0) { 123 IWL_DEBUG_INFO(priv, "Failed to init the card\n"); 124 return ret; 125 } 126 127 /* enable DMA */ 128 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT); 129 130 udelay(20); 131 132 /* disable L1-Active */ 133 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG, 134 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 135 136 return ret; 137} 138 139/* FIXME: this is identical to 4965 */ 140static void iwl5000_apm_stop(struct iwl_priv *priv) 141{ 142 unsigned long flags; 143 144 iwl5000_apm_stop_master(priv); 145 146 spin_lock_irqsave(&priv->lock, flags); 147 148 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 149 150 udelay(10); 151 152 /* clear "init complete" move adapter D0A* --> D0U state */ 153 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 154 155 spin_unlock_irqrestore(&priv->lock, flags); 156} 157 158 159static int iwl5000_apm_reset(struct iwl_priv *priv) 160{ 161 int ret = 0; 162 163 iwl5000_apm_stop_master(priv); 164 165 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 166 167 udelay(10); 168 169 170 /* FIXME: put here L1A -L0S w/a */ 171 172 if (priv->cfg->need_pll_cfg) 173 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); 174 175 /* set "initialization complete" bit to move adapter 176 * D0U* --> D0A* state */ 177 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 178 179 /* wait for clock stabilization */ 180 ret = iwl_poll_direct_bit(priv, CSR_GP_CNTRL, 181 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); 182 if (ret < 0) { 183 IWL_DEBUG_INFO(priv, "Failed to init the card\n"); 184 goto out; 185 } 186 187 /* enable DMA */ 188 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT); 189 190 udelay(20); 191 192 /* disable L1-Active */ 193 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG, 194 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 195out: 196 197 return ret; 198} 199 200 201static void iwl5000_nic_config(struct iwl_priv *priv) 202{ 203 unsigned long flags; 204 u16 radio_cfg; 205 u16 lctl; 206 207 spin_lock_irqsave(&priv->lock, flags); 208 209 lctl = iwl_pcie_link_ctl(priv); 210 211 /* HW bug W/A */ 212 /* L1-ASPM is enabled by BIOS */ 213 if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) == PCI_CFG_LINK_CTRL_VAL_L1_EN) 214 /* L1-APSM enabled: disable L0S */ 215 iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); 216 else 217 /* L1-ASPM disabled: enable L0S */ 218 iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); 219 220 radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG); 221 222 /* write radio config values to register */ 223 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_5000_RF_CFG_TYPE_MAX) 224 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, 225 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) | 226 EEPROM_RF_CFG_STEP_MSK(radio_cfg) | 227 EEPROM_RF_CFG_DASH_MSK(radio_cfg)); 228 229 /* set CSR_HW_CONFIG_REG for uCode use */ 230 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, 231 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI | 232 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI); 233 234 /* W/A : NIC is stuck in a reset state after Early PCIe power off 235 * (PCIe power is lost before PERST# is asserted), 236 * causing ME FW to lose ownership and not being able to obtain it back. 237 */ 238 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, 239 APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS, 240 ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS); 241 242 spin_unlock_irqrestore(&priv->lock, flags); 243} 244 245 246 247/* 248 * EEPROM 249 */ 250static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address) 251{ 252 u16 offset = 0; 253 254 if ((address & INDIRECT_ADDRESS) == 0) 255 return address; 256 257 switch (address & INDIRECT_TYPE_MSK) { 258 case INDIRECT_HOST: 259 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST); 260 break; 261 case INDIRECT_GENERAL: 262 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL); 263 break; 264 case INDIRECT_REGULATORY: 265 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY); 266 break; 267 case INDIRECT_CALIBRATION: 268 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION); 269 break; 270 case INDIRECT_PROCESS_ADJST: 271 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST); 272 break; 273 case INDIRECT_OTHERS: 274 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS); 275 break; 276 default: 277 IWL_ERR(priv, "illegal indirect type: 0x%X\n", 278 address & INDIRECT_TYPE_MSK); 279 break; 280 } 281 282 /* translate the offset from words to byte */ 283 return (address & ADDRESS_MSK) + (offset << 1); 284} 285 286static u16 iwl5000_eeprom_calib_version(struct iwl_priv *priv) 287{ 288 struct iwl_eeprom_calib_hdr { 289 u8 version; 290 u8 pa_type; 291 u16 voltage; 292 } *hdr; 293 294 hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv, 295 EEPROM_5000_CALIB_ALL); 296 return hdr->version; 297 298} 299 300static void iwl5000_gain_computation(struct iwl_priv *priv, 301 u32 average_noise[NUM_RX_CHAINS], 302 u16 min_average_noise_antenna_i, 303 u32 min_average_noise) 304{ 305 int i; 306 s32 delta_g; 307 struct iwl_chain_noise_data *data = &priv->chain_noise_data; 308 309 /* Find Gain Code for the antennas B and C */ 310 for (i = 1; i < NUM_RX_CHAINS; i++) { 311 if ((data->disconn_array[i])) { 312 data->delta_gain_code[i] = 0; 313 continue; 314 } 315 delta_g = (1000 * ((s32)average_noise[0] - 316 (s32)average_noise[i])) / 1500; 317 /* bound gain by 2 bits value max, 3rd bit is sign */ 318 data->delta_gain_code[i] = 319 min(abs(delta_g), CHAIN_NOISE_MAX_DELTA_GAIN_CODE); 320 321 if (delta_g < 0) 322 /* set negative sign */ 323 data->delta_gain_code[i] |= (1 << 2); 324 } 325 326 IWL_DEBUG_CALIB(priv, "Delta gains: ANT_B = %d ANT_C = %d\n", 327 data->delta_gain_code[1], data->delta_gain_code[2]); 328 329 if (!data->radio_write) { 330 struct iwl_calib_chain_noise_gain_cmd cmd; 331 332 memset(&cmd, 0, sizeof(cmd)); 333 334 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD; 335 cmd.hdr.first_group = 0; 336 cmd.hdr.groups_num = 1; 337 cmd.hdr.data_valid = 1; 338 cmd.delta_gain_1 = data->delta_gain_code[1]; 339 cmd.delta_gain_2 = data->delta_gain_code[2]; 340 iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD, 341 sizeof(cmd), &cmd, NULL); 342 343 data->radio_write = 1; 344 data->state = IWL_CHAIN_NOISE_CALIBRATED; 345 } 346 347 data->chain_noise_a = 0; 348 data->chain_noise_b = 0; 349 data->chain_noise_c = 0; 350 data->chain_signal_a = 0; 351 data->chain_signal_b = 0; 352 data->chain_signal_c = 0; 353 data->beacon_count = 0; 354} 355 356static void iwl5000_chain_noise_reset(struct iwl_priv *priv) 357{ 358 struct iwl_chain_noise_data *data = &priv->chain_noise_data; 359 int ret; 360 361 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) { 362 struct iwl_calib_chain_noise_reset_cmd cmd; 363 memset(&cmd, 0, sizeof(cmd)); 364 365 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD; 366 cmd.hdr.first_group = 0; 367 cmd.hdr.groups_num = 1; 368 cmd.hdr.data_valid = 1; 369 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD, 370 sizeof(cmd), &cmd); 371 if (ret) 372 IWL_ERR(priv, 373 "Could not send REPLY_PHY_CALIBRATION_CMD\n"); 374 data->state = IWL_CHAIN_NOISE_ACCUMULATE; 375 IWL_DEBUG_CALIB(priv, "Run chain_noise_calibrate\n"); 376 } 377} 378 379void iwl5000_rts_tx_cmd_flag(struct ieee80211_tx_info *info, 380 __le32 *tx_flags) 381{ 382 if ((info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) || 383 (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT)) 384 *tx_flags |= TX_CMD_FLG_RTS_CTS_MSK; 385 else 386 *tx_flags &= ~TX_CMD_FLG_RTS_CTS_MSK; 387} 388 389static struct iwl_sensitivity_ranges iwl5000_sensitivity = { 390 .min_nrg_cck = 95, 391 .max_nrg_cck = 0, 392 .auto_corr_min_ofdm = 90, 393 .auto_corr_min_ofdm_mrc = 170, 394 .auto_corr_min_ofdm_x1 = 120, 395 .auto_corr_min_ofdm_mrc_x1 = 240, 396 397 .auto_corr_max_ofdm = 120, 398 .auto_corr_max_ofdm_mrc = 210, 399 .auto_corr_max_ofdm_x1 = 155, 400 .auto_corr_max_ofdm_mrc_x1 = 290, 401 402 .auto_corr_min_cck = 125, 403 .auto_corr_max_cck = 200, 404 .auto_corr_min_cck_mrc = 170, 405 .auto_corr_max_cck_mrc = 400, 406 .nrg_th_cck = 95, 407 .nrg_th_ofdm = 95, 408}; 409 410static const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv, 411 size_t offset) 412{ 413 u32 address = eeprom_indirect_address(priv, offset); 414 BUG_ON(address >= priv->cfg->eeprom_size); 415 return &priv->eeprom[address]; 416} 417 418static void iwl5150_set_ct_threshold(struct iwl_priv *priv) 419{ 420 const s32 volt2temp_coef = IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF; 421 s32 threshold = (s32)CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD) - 422 iwl_temp_calib_to_offset(priv); 423 424 priv->hw_params.ct_kill_threshold = threshold * volt2temp_coef; 425} 426 427static void iwl5000_set_ct_threshold(struct iwl_priv *priv) 428{ 429 /* want Celsius */ 430 priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD; 431} 432 433/* 434 * Calibration 435 */ 436static int iwl5000_set_Xtal_calib(struct iwl_priv *priv) 437{ 438 struct iwl_calib_xtal_freq_cmd cmd; 439 u16 *xtal_calib = (u16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_XTAL); 440 441 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD; 442 cmd.hdr.first_group = 0; 443 cmd.hdr.groups_num = 1; 444 cmd.hdr.data_valid = 1; 445 cmd.cap_pin1 = (u8)xtal_calib[0]; 446 cmd.cap_pin2 = (u8)xtal_calib[1]; 447 return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL], 448 (u8 *)&cmd, sizeof(cmd)); 449} 450 451static int iwl5000_send_calib_cfg(struct iwl_priv *priv) 452{ 453 struct iwl_calib_cfg_cmd calib_cfg_cmd; 454 struct iwl_host_cmd cmd = { 455 .id = CALIBRATION_CFG_CMD, 456 .len = sizeof(struct iwl_calib_cfg_cmd), 457 .data = &calib_cfg_cmd, 458 }; 459 460 memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd)); 461 calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL; 462 calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL; 463 calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL; 464 calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL; 465 466 return iwl_send_cmd(priv, &cmd); 467} 468 469static void iwl5000_rx_calib_result(struct iwl_priv *priv, 470 struct iwl_rx_mem_buffer *rxb) 471{ 472 struct iwl_rx_packet *pkt = (void *)rxb->skb->data; 473 struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw; 474 int len = le32_to_cpu(pkt->len) & FH_RSCSR_FRAME_SIZE_MSK; 475 int index; 476 477 /* reduce the size of the length field itself */ 478 len -= 4; 479 480 /* Define the order in which the results will be sent to the runtime 481 * uCode. iwl_send_calib_results sends them in a row according to their 482 * index. We sort them here */ 483 switch (hdr->op_code) { 484 case IWL_PHY_CALIBRATE_DC_CMD: 485 index = IWL_CALIB_DC; 486 break; 487 case IWL_PHY_CALIBRATE_LO_CMD: 488 index = IWL_CALIB_LO; 489 break; 490 case IWL_PHY_CALIBRATE_TX_IQ_CMD: 491 index = IWL_CALIB_TX_IQ; 492 break; 493 case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD: 494 index = IWL_CALIB_TX_IQ_PERD; 495 break; 496 case IWL_PHY_CALIBRATE_BASE_BAND_CMD: 497 index = IWL_CALIB_BASE_BAND; 498 break; 499 default: 500 IWL_ERR(priv, "Unknown calibration notification %d\n", 501 hdr->op_code); 502 return; 503 } 504 iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len); 505} 506 507static void iwl5000_rx_calib_complete(struct iwl_priv *priv, 508 struct iwl_rx_mem_buffer *rxb) 509{ 510 IWL_DEBUG_INFO(priv, "Init. calibration is completed, restarting fw.\n"); 511 queue_work(priv->workqueue, &priv->restart); 512} 513 514/* 515 * ucode 516 */ 517static int iwl5000_load_section(struct iwl_priv *priv, 518 struct fw_desc *image, 519 u32 dst_addr) 520{ 521 dma_addr_t phy_addr = image->p_addr; 522 u32 byte_cnt = image->len; 523 524 iwl_write_direct32(priv, 525 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 526 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); 527 528 iwl_write_direct32(priv, 529 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr); 530 531 iwl_write_direct32(priv, 532 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), 533 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); 534 535 iwl_write_direct32(priv, 536 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), 537 (iwl_get_dma_hi_addr(phy_addr) 538 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); 539 540 iwl_write_direct32(priv, 541 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), 542 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM | 543 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX | 544 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); 545 546 iwl_write_direct32(priv, 547 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 548 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 549 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | 550 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); 551 552 return 0; 553} 554 555static int iwl5000_load_given_ucode(struct iwl_priv *priv, 556 struct fw_desc *inst_image, 557 struct fw_desc *data_image) 558{ 559 int ret = 0; 560 561 ret = iwl5000_load_section(priv, inst_image, 562 IWL50_RTC_INST_LOWER_BOUND); 563 if (ret) 564 return ret; 565 566 IWL_DEBUG_INFO(priv, "INST uCode section being loaded...\n"); 567 ret = wait_event_interruptible_timeout(priv->wait_command_queue, 568 priv->ucode_write_complete, 5 * HZ); 569 if (ret == -ERESTARTSYS) { 570 IWL_ERR(priv, "Could not load the INST uCode section due " 571 "to interrupt\n"); 572 return ret; 573 } 574 if (!ret) { 575 IWL_ERR(priv, "Could not load the INST uCode section\n"); 576 return -ETIMEDOUT; 577 } 578 579 priv->ucode_write_complete = 0; 580 581 ret = iwl5000_load_section( 582 priv, data_image, IWL50_RTC_DATA_LOWER_BOUND); 583 if (ret) 584 return ret; 585 586 IWL_DEBUG_INFO(priv, "DATA uCode section being loaded...\n"); 587 588 ret = wait_event_interruptible_timeout(priv->wait_command_queue, 589 priv->ucode_write_complete, 5 * HZ); 590 if (ret == -ERESTARTSYS) { 591 IWL_ERR(priv, "Could not load the INST uCode section due " 592 "to interrupt\n"); 593 return ret; 594 } else if (!ret) { 595 IWL_ERR(priv, "Could not load the DATA uCode section\n"); 596 return -ETIMEDOUT; 597 } else 598 ret = 0; 599 600 priv->ucode_write_complete = 0; 601 602 return ret; 603} 604 605static int iwl5000_load_ucode(struct iwl_priv *priv) 606{ 607 int ret = 0; 608 609 /* check whether init ucode should be loaded, or rather runtime ucode */ 610 if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) { 611 IWL_DEBUG_INFO(priv, "Init ucode found. Loading init ucode...\n"); 612 ret = iwl5000_load_given_ucode(priv, 613 &priv->ucode_init, &priv->ucode_init_data); 614 if (!ret) { 615 IWL_DEBUG_INFO(priv, "Init ucode load complete.\n"); 616 priv->ucode_type = UCODE_INIT; 617 } 618 } else { 619 IWL_DEBUG_INFO(priv, "Init ucode not found, or already loaded. " 620 "Loading runtime ucode...\n"); 621 ret = iwl5000_load_given_ucode(priv, 622 &priv->ucode_code, &priv->ucode_data); 623 if (!ret) { 624 IWL_DEBUG_INFO(priv, "Runtime ucode load complete.\n"); 625 priv->ucode_type = UCODE_RT; 626 } 627 } 628 629 return ret; 630} 631 632static void iwl5000_init_alive_start(struct iwl_priv *priv) 633{ 634 int ret = 0; 635 636 /* Check alive response for "valid" sign from uCode */ 637 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) { 638 /* We had an error bringing up the hardware, so take it 639 * all the way back down so we can try again */ 640 IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n"); 641 goto restart; 642 } 643 644 /* initialize uCode was loaded... verify inst image. 645 * This is a paranoid check, because we would not have gotten the 646 * "initialize" alive if code weren't properly loaded. */ 647 if (iwl_verify_ucode(priv)) { 648 /* Runtime instruction load was bad; 649 * take it all the way back down so we can try again */ 650 IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n"); 651 goto restart; 652 } 653 654 priv->cfg->ops->smgmt->clear_station_table(priv); 655 ret = priv->cfg->ops->lib->alive_notify(priv); 656 if (ret) { 657 IWL_WARN(priv, 658 "Could not complete ALIVE transition: %d\n", ret); 659 goto restart; 660 } 661 662 iwl5000_send_calib_cfg(priv); 663 return; 664 665restart: 666 /* real restart (first load init_ucode) */ 667 queue_work(priv->workqueue, &priv->restart); 668} 669 670static void iwl5000_set_wr_ptrs(struct iwl_priv *priv, 671 int txq_id, u32 index) 672{ 673 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 674 (index & 0xff) | (txq_id << 8)); 675 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index); 676} 677 678static void iwl5000_tx_queue_set_status(struct iwl_priv *priv, 679 struct iwl_tx_queue *txq, 680 int tx_fifo_id, int scd_retry) 681{ 682 int txq_id = txq->q.id; 683 int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0; 684 685 iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id), 686 (active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) | 687 (tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) | 688 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) | 689 IWL50_SCD_QUEUE_STTS_REG_MSK); 690 691 txq->sched_retry = scd_retry; 692 693 IWL_DEBUG_INFO(priv, "%s %s Queue %d on AC %d\n", 694 active ? "Activate" : "Deactivate", 695 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id); 696} 697 698static int iwl5000_send_wimax_coex(struct iwl_priv *priv) 699{ 700 struct iwl_wimax_coex_cmd coex_cmd; 701 702 memset(&coex_cmd, 0, sizeof(coex_cmd)); 703 704 return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD, 705 sizeof(coex_cmd), &coex_cmd); 706} 707 708static int iwl5000_alive_notify(struct iwl_priv *priv) 709{ 710 u32 a; 711 unsigned long flags; 712 int i, chan; 713 u32 reg_val; 714 715 spin_lock_irqsave(&priv->lock, flags); 716 717 priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR); 718 a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET; 719 for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET; 720 a += 4) 721 iwl_write_targ_mem(priv, a, 0); 722 for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET; 723 a += 4) 724 iwl_write_targ_mem(priv, a, 0); 725 for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4) 726 iwl_write_targ_mem(priv, a, 0); 727 728 iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR, 729 priv->scd_bc_tbls.dma >> 10); 730 731 /* Enable DMA channel */ 732 for (chan = 0; chan < FH50_TCSR_CHNL_NUM ; chan++) 733 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan), 734 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 735 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE); 736 737 /* Update FH chicken bits */ 738 reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG); 739 iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG, 740 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN); 741 742 iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, 743 IWL50_SCD_QUEUECHAIN_SEL_ALL(priv->hw_params.max_txq_num)); 744 iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0); 745 746 /* initiate the queues */ 747 for (i = 0; i < priv->hw_params.max_txq_num; i++) { 748 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0); 749 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8)); 750 iwl_write_targ_mem(priv, priv->scd_base_addr + 751 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0); 752 iwl_write_targ_mem(priv, priv->scd_base_addr + 753 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) + 754 sizeof(u32), 755 ((SCD_WIN_SIZE << 756 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & 757 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | 758 ((SCD_FRAME_LIMIT << 759 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & 760 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); 761 } 762 763 iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK, 764 IWL_MASK(0, priv->hw_params.max_txq_num)); 765 766 /* Activate all Tx DMA/FIFO channels */ 767 priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7)); 768 769 iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0); 770 771 /* map qos queues to fifos one-to-one */ 772 for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) { 773 int ac = iwl5000_default_queue_to_tx_fifo[i]; 774 iwl_txq_ctx_activate(priv, i); 775 iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0); 776 } 777 /* TODO - need to initialize those FIFOs inside the loop above, 778 * not only mark them as active */ 779 iwl_txq_ctx_activate(priv, 4); 780 iwl_txq_ctx_activate(priv, 7); 781 iwl_txq_ctx_activate(priv, 8); 782 iwl_txq_ctx_activate(priv, 9); 783 784 spin_unlock_irqrestore(&priv->lock, flags); 785 786 787 iwl5000_send_wimax_coex(priv); 788 789 iwl5000_set_Xtal_calib(priv); 790 iwl_send_calib_results(priv); 791 792 return 0; 793} 794 795static int iwl5000_hw_set_hw_params(struct iwl_priv *priv) 796{ 797 if ((priv->cfg->mod_params->num_of_queues > IWL50_NUM_QUEUES) || 798 (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) { 799 IWL_ERR(priv, 800 "invalid queues_num, should be between %d and %d\n", 801 IWL_MIN_NUM_QUEUES, IWL50_NUM_QUEUES); 802 return -EINVAL; 803 } 804 805 priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues; 806 priv->hw_params.dma_chnl_num = FH50_TCSR_CHNL_NUM; 807 priv->hw_params.scd_bc_tbls_size = 808 IWL50_NUM_QUEUES * sizeof(struct iwl5000_scd_bc_tbl); 809 priv->hw_params.tfd_size = sizeof(struct iwl_tfd); 810 priv->hw_params.max_stations = IWL5000_STATION_COUNT; 811 priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID; 812 813 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) { 814 case CSR_HW_REV_TYPE_6x00: 815 case CSR_HW_REV_TYPE_6x50: 816 priv->hw_params.max_data_size = IWL60_RTC_DATA_SIZE; 817 priv->hw_params.max_inst_size = IWL60_RTC_INST_SIZE; 818 break; 819 default: 820 priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE; 821 priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE; 822 } 823 824 priv->hw_params.max_bsm_size = 0; 825 priv->hw_params.fat_channel = BIT(IEEE80211_BAND_2GHZ) | 826 BIT(IEEE80211_BAND_5GHZ); 827 priv->hw_params.rx_wrt_ptr_reg = FH_RSCSR_CHNL0_WPTR; 828 829 priv->hw_params.sens = &iwl5000_sensitivity; 830 831 priv->hw_params.tx_chains_num = num_of_ant(priv->cfg->valid_tx_ant); 832 priv->hw_params.rx_chains_num = num_of_ant(priv->cfg->valid_rx_ant); 833 priv->hw_params.valid_tx_ant = priv->cfg->valid_tx_ant; 834 priv->hw_params.valid_rx_ant = priv->cfg->valid_rx_ant; 835 836 if (priv->cfg->ops->lib->temp_ops.set_ct_kill) 837 priv->cfg->ops->lib->temp_ops.set_ct_kill(priv); 838 839 /* Set initial calibration set */ 840 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) { 841 case CSR_HW_REV_TYPE_5150: 842 priv->hw_params.calib_init_cfg = 843 BIT(IWL_CALIB_DC) | 844 BIT(IWL_CALIB_LO) | 845 BIT(IWL_CALIB_TX_IQ) | 846 BIT(IWL_CALIB_BASE_BAND); 847 848 break; 849 default: 850 priv->hw_params.calib_init_cfg = 851 BIT(IWL_CALIB_XTAL) | 852 BIT(IWL_CALIB_LO) | 853 BIT(IWL_CALIB_TX_IQ) | 854 BIT(IWL_CALIB_TX_IQ_PERD) | 855 BIT(IWL_CALIB_BASE_BAND); 856 break; 857 } 858 859 return 0; 860} 861 862/** 863 * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array 864 */ 865static void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv, 866 struct iwl_tx_queue *txq, 867 u16 byte_cnt) 868{ 869 struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr; 870 int write_ptr = txq->q.write_ptr; 871 int txq_id = txq->q.id; 872 u8 sec_ctl = 0; 873 u8 sta_id = 0; 874 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE; 875 __le16 bc_ent; 876 877 WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX); 878 879 if (txq_id != IWL_CMD_QUEUE_NUM) { 880 sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id; 881 sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl; 882 883 switch (sec_ctl & TX_CMD_SEC_MSK) { 884 case TX_CMD_SEC_CCM: 885 len += CCMP_MIC_LEN; 886 break; 887 case TX_CMD_SEC_TKIP: 888 len += TKIP_ICV_LEN; 889 break; 890 case TX_CMD_SEC_WEP: 891 len += WEP_IV_LEN + WEP_ICV_LEN; 892 break; 893 } 894 } 895 896 bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12)); 897 898 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent; 899 900 if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP) 901 scd_bc_tbl[txq_id]. 902 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent; 903} 904 905static void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv, 906 struct iwl_tx_queue *txq) 907{ 908 struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr; 909 int txq_id = txq->q.id; 910 int read_ptr = txq->q.read_ptr; 911 u8 sta_id = 0; 912 __le16 bc_ent; 913 914 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX); 915 916 if (txq_id != IWL_CMD_QUEUE_NUM) 917 sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id; 918 919 bc_ent = cpu_to_le16(1 | (sta_id << 12)); 920 scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent; 921 922 if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP) 923 scd_bc_tbl[txq_id]. 924 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent; 925} 926 927static int iwl5000_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid, 928 u16 txq_id) 929{ 930 u32 tbl_dw_addr; 931 u32 tbl_dw; 932 u16 scd_q2ratid; 933 934 scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK; 935 936 tbl_dw_addr = priv->scd_base_addr + 937 IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id); 938 939 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr); 940 941 if (txq_id & 0x1) 942 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF); 943 else 944 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000); 945 946 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw); 947 948 return 0; 949} 950static void iwl5000_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id) 951{ 952 /* Simply stop the queue, but don't change any configuration; 953 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */ 954 iwl_write_prph(priv, 955 IWL50_SCD_QUEUE_STATUS_BITS(txq_id), 956 (0 << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE)| 957 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN)); 958} 959 960static int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id, 961 int tx_fifo, int sta_id, int tid, u16 ssn_idx) 962{ 963 unsigned long flags; 964 u16 ra_tid; 965 966 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) || 967 (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) { 968 IWL_WARN(priv, 969 "queue number out of range: %d, must be %d to %d\n", 970 txq_id, IWL50_FIRST_AMPDU_QUEUE, 971 IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1); 972 return -EINVAL; 973 } 974 975 ra_tid = BUILD_RAxTID(sta_id, tid); 976 977 /* Modify device's station table to Tx this TID */ 978 iwl_sta_tx_modify_enable_tid(priv, sta_id, tid); 979 980 spin_lock_irqsave(&priv->lock, flags); 981 982 /* Stop this Tx queue before configuring it */ 983 iwl5000_tx_queue_stop_scheduler(priv, txq_id); 984 985 /* Map receiver-address / traffic-ID to this queue */ 986 iwl5000_tx_queue_set_q2ratid(priv, ra_tid, txq_id); 987 988 /* Set this queue as a chain-building queue */ 989 iwl_set_bits_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, (1<<txq_id)); 990 991 /* enable aggregations for the queue */ 992 iwl_set_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1<<txq_id)); 993 994 /* Place first TFD at index corresponding to start sequence number. 995 * Assumes that ssn_idx is valid (!= 0xFFF) */ 996 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff); 997 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff); 998 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx); 999 1000 /* Set up Tx window size and frame limit for this queue */ 1001 iwl_write_targ_mem(priv, priv->scd_base_addr + 1002 IWL50_SCD_CONTEXT_QUEUE_OFFSET(txq_id) + 1003 sizeof(u32), 1004 ((SCD_WIN_SIZE << 1005 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & 1006 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | 1007 ((SCD_FRAME_LIMIT << 1008 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & 1009 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); 1010 1011 iwl_set_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id)); 1012 1013 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */ 1014 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1); 1015 1016 spin_unlock_irqrestore(&priv->lock, flags); 1017 1018 return 0; 1019} 1020 1021static int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id, 1022 u16 ssn_idx, u8 tx_fifo) 1023{ 1024 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) || 1025 (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) { 1026 IWL_ERR(priv, 1027 "queue number out of range: %d, must be %d to %d\n", 1028 txq_id, IWL50_FIRST_AMPDU_QUEUE, 1029 IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1); 1030 return -EINVAL; 1031 } 1032 1033 iwl5000_tx_queue_stop_scheduler(priv, txq_id); 1034 1035 iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id)); 1036 1037 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff); 1038 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff); 1039 /* supposes that ssn_idx is valid (!= 0xFFF) */ 1040 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx); 1041 1042 iwl_clear_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id)); 1043 iwl_txq_ctx_deactivate(priv, txq_id); 1044 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0); 1045 1046 return 0; 1047} 1048 1049u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data) 1050{ 1051 u16 size = (u16)sizeof(struct iwl_addsta_cmd); 1052 memcpy(data, cmd, size); 1053 return size; 1054} 1055 1056 1057/* 1058 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask 1059 * must be called under priv->lock and mac access 1060 */ 1061static void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask) 1062{ 1063 iwl_write_prph(priv, IWL50_SCD_TXFACT, mask); 1064} 1065 1066 1067static inline u32 iwl5000_get_scd_ssn(struct iwl5000_tx_resp *tx_resp) 1068{ 1069 return le32_to_cpup((__le32 *)&tx_resp->status + 1070 tx_resp->frame_count) & MAX_SN; 1071} 1072 1073static int iwl5000_tx_status_reply_tx(struct iwl_priv *priv, 1074 struct iwl_ht_agg *agg, 1075 struct iwl5000_tx_resp *tx_resp, 1076 int txq_id, u16 start_idx) 1077{ 1078 u16 status; 1079 struct agg_tx_status *frame_status = &tx_resp->status; 1080 struct ieee80211_tx_info *info = NULL; 1081 struct ieee80211_hdr *hdr = NULL; 1082 u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags); 1083 int i, sh, idx; 1084 u16 seq; 1085 1086 if (agg->wait_for_ba) 1087 IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n"); 1088 1089 agg->frame_count = tx_resp->frame_count; 1090 agg->start_idx = start_idx; 1091 agg->rate_n_flags = rate_n_flags; 1092 agg->bitmap = 0; 1093 1094 /* # frames attempted by Tx command */ 1095 if (agg->frame_count == 1) { 1096 /* Only one frame was attempted; no block-ack will arrive */ 1097 status = le16_to_cpu(frame_status[0].status); 1098 idx = start_idx; 1099 1100 /* FIXME: code repetition */ 1101 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n", 1102 agg->frame_count, agg->start_idx, idx); 1103 1104 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]); 1105 info->status.rates[0].count = tx_resp->failure_frame + 1; 1106 info->flags &= ~IEEE80211_TX_CTL_AMPDU; 1107 info->flags |= iwl_is_tx_success(status) ? 1108 IEEE80211_TX_STAT_ACK : 0; 1109 iwl_hwrate_to_tx_control(priv, rate_n_flags, info); 1110 1111 /* FIXME: code repetition end */ 1112 1113 IWL_DEBUG_TX_REPLY(priv, "1 Frame 0x%x failure :%d\n", 1114 status & 0xff, tx_resp->failure_frame); 1115 IWL_DEBUG_TX_REPLY(priv, "Rate Info rate_n_flags=%x\n", rate_n_flags); 1116 1117 agg->wait_for_ba = 0; 1118 } else { 1119 /* Two or more frames were attempted; expect block-ack */ 1120 u64 bitmap = 0; 1121 int start = agg->start_idx; 1122 1123 /* Construct bit-map of pending frames within Tx window */ 1124 for (i = 0; i < agg->frame_count; i++) { 1125 u16 sc; 1126 status = le16_to_cpu(frame_status[i].status); 1127 seq = le16_to_cpu(frame_status[i].sequence); 1128 idx = SEQ_TO_INDEX(seq); 1129 txq_id = SEQ_TO_QUEUE(seq); 1130 1131 if (status & (AGG_TX_STATE_FEW_BYTES_MSK | 1132 AGG_TX_STATE_ABORT_MSK)) 1133 continue; 1134 1135 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n", 1136 agg->frame_count, txq_id, idx); 1137 1138 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx); 1139 1140 sc = le16_to_cpu(hdr->seq_ctrl); 1141 if (idx != (SEQ_TO_SN(sc) & 0xff)) { 1142 IWL_ERR(priv, 1143 "BUG_ON idx doesn't match seq control" 1144 " idx=%d, seq_idx=%d, seq=%d\n", 1145 idx, SEQ_TO_SN(sc), 1146 hdr->seq_ctrl); 1147 return -1; 1148 } 1149 1150 IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n", 1151 i, idx, SEQ_TO_SN(sc)); 1152 1153 sh = idx - start; 1154 if (sh > 64) { 1155 sh = (start - idx) + 0xff; 1156 bitmap = bitmap << sh; 1157 sh = 0; 1158 start = idx; 1159 } else if (sh < -64) 1160 sh = 0xff - (start - idx); 1161 else if (sh < 0) { 1162 sh = start - idx; 1163 start = idx; 1164 bitmap = bitmap << sh; 1165 sh = 0; 1166 } 1167 bitmap |= 1ULL << sh; 1168 IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n", 1169 start, (unsigned long long)bitmap); 1170 } 1171 1172 agg->bitmap = bitmap; 1173 agg->start_idx = start; 1174 IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n", 1175 agg->frame_count, agg->start_idx, 1176 (unsigned long long)agg->bitmap); 1177 1178 if (bitmap) 1179 agg->wait_for_ba = 1; 1180 } 1181 return 0; 1182} 1183 1184static void iwl5000_rx_reply_tx(struct iwl_priv *priv, 1185 struct iwl_rx_mem_buffer *rxb) 1186{ 1187 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; 1188 u16 sequence = le16_to_cpu(pkt->hdr.sequence); 1189 int txq_id = SEQ_TO_QUEUE(sequence); 1190 int index = SEQ_TO_INDEX(sequence); 1191 struct iwl_tx_queue *txq = &priv->txq[txq_id]; 1192 struct ieee80211_tx_info *info; 1193 struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0]; 1194 u32 status = le16_to_cpu(tx_resp->status.status); 1195 int tid; 1196 int sta_id; 1197 int freed; 1198 1199 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) { 1200 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d " 1201 "is out of range [0-%d] %d %d\n", txq_id, 1202 index, txq->q.n_bd, txq->q.write_ptr, 1203 txq->q.read_ptr); 1204 return; 1205 } 1206 1207 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]); 1208 memset(&info->status, 0, sizeof(info->status)); 1209 1210 tid = (tx_resp->ra_tid & IWL50_TX_RES_TID_MSK) >> IWL50_TX_RES_TID_POS; 1211 sta_id = (tx_resp->ra_tid & IWL50_TX_RES_RA_MSK) >> IWL50_TX_RES_RA_POS; 1212 1213 if (txq->sched_retry) { 1214 const u32 scd_ssn = iwl5000_get_scd_ssn(tx_resp); 1215 struct iwl_ht_agg *agg = NULL; 1216 1217 agg = &priv->stations[sta_id].tid[tid].agg; 1218 1219 iwl5000_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index); 1220 1221 /* check if BAR is needed */ 1222 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status)) 1223 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK; 1224 1225 if (txq->q.read_ptr != (scd_ssn & 0xff)) { 1226 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd); 1227 IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim " 1228 "scd_ssn=%d idx=%d txq=%d swq=%d\n", 1229 scd_ssn , index, txq_id, txq->swq_id); 1230 1231 freed = iwl_tx_queue_reclaim(priv, txq_id, index); 1232 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed; 1233 1234 if (priv->mac80211_registered && 1235 (iwl_queue_space(&txq->q) > txq->q.low_mark) && 1236 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) { 1237 if (agg->state == IWL_AGG_OFF) 1238 iwl_wake_queue(priv, txq_id); 1239 else 1240 iwl_wake_queue(priv, txq->swq_id); 1241 } 1242 } 1243 } else { 1244 BUG_ON(txq_id != txq->swq_id); 1245 1246 info->status.rates[0].count = tx_resp->failure_frame + 1; 1247 info->flags |= iwl_is_tx_success(status) ? 1248 IEEE80211_TX_STAT_ACK : 0; 1249 iwl_hwrate_to_tx_control(priv, 1250 le32_to_cpu(tx_resp->rate_n_flags), 1251 info); 1252 1253 IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) rate_n_flags " 1254 "0x%x retries %d\n", 1255 txq_id, 1256 iwl_get_tx_fail_reason(status), status, 1257 le32_to_cpu(tx_resp->rate_n_flags), 1258 tx_resp->failure_frame); 1259 1260 freed = iwl_tx_queue_reclaim(priv, txq_id, index); 1261 if (ieee80211_is_data_qos(tx_resp->frame_ctrl)) 1262 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed; 1263 1264 if (priv->mac80211_registered && 1265 (iwl_queue_space(&txq->q) > txq->q.low_mark)) 1266 iwl_wake_queue(priv, txq_id); 1267 } 1268 1269 if (ieee80211_is_data_qos(tx_resp->frame_ctrl)) 1270 iwl_txq_check_empty(priv, sta_id, tid, txq_id); 1271 1272 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK)) 1273 IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n"); 1274} 1275 1276/* Currently 5000 is the superset of everything */ 1277u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len) 1278{ 1279 return len; 1280} 1281 1282static void iwl5000_setup_deferred_work(struct iwl_priv *priv) 1283{ 1284 /* in 5000 the tx power calibration is done in uCode */ 1285 priv->disable_tx_power_cal = 1; 1286} 1287 1288static void iwl5000_rx_handler_setup(struct iwl_priv *priv) 1289{ 1290 /* init calibration handlers */ 1291 priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] = 1292 iwl5000_rx_calib_result; 1293 priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] = 1294 iwl5000_rx_calib_complete; 1295 priv->rx_handlers[REPLY_TX] = iwl5000_rx_reply_tx; 1296} 1297 1298 1299static int iwl5000_hw_valid_rtc_data_addr(u32 addr) 1300{ 1301 return (addr >= IWL50_RTC_DATA_LOWER_BOUND) && 1302 (addr < IWL50_RTC_DATA_UPPER_BOUND); 1303} 1304 1305static int iwl5000_send_rxon_assoc(struct iwl_priv *priv) 1306{ 1307 int ret = 0; 1308 struct iwl5000_rxon_assoc_cmd rxon_assoc; 1309 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon; 1310 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon; 1311 1312 if ((rxon1->flags == rxon2->flags) && 1313 (rxon1->filter_flags == rxon2->filter_flags) && 1314 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) && 1315 (rxon1->ofdm_ht_single_stream_basic_rates == 1316 rxon2->ofdm_ht_single_stream_basic_rates) && 1317 (rxon1->ofdm_ht_dual_stream_basic_rates == 1318 rxon2->ofdm_ht_dual_stream_basic_rates) && 1319 (rxon1->ofdm_ht_triple_stream_basic_rates == 1320 rxon2->ofdm_ht_triple_stream_basic_rates) && 1321 (rxon1->acquisition_data == rxon2->acquisition_data) && 1322 (rxon1->rx_chain == rxon2->rx_chain) && 1323 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) { 1324 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC. Not resending.\n"); 1325 return 0; 1326 } 1327 1328 rxon_assoc.flags = priv->staging_rxon.flags; 1329 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags; 1330 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates; 1331 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates; 1332 rxon_assoc.reserved1 = 0; 1333 rxon_assoc.reserved2 = 0; 1334 rxon_assoc.reserved3 = 0; 1335 rxon_assoc.ofdm_ht_single_stream_basic_rates = 1336 priv->staging_rxon.ofdm_ht_single_stream_basic_rates; 1337 rxon_assoc.ofdm_ht_dual_stream_basic_rates = 1338 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates; 1339 rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain; 1340 rxon_assoc.ofdm_ht_triple_stream_basic_rates = 1341 priv->staging_rxon.ofdm_ht_triple_stream_basic_rates; 1342 rxon_assoc.acquisition_data = priv->staging_rxon.acquisition_data; 1343 1344 ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC, 1345 sizeof(rxon_assoc), &rxon_assoc, NULL); 1346 if (ret) 1347 return ret; 1348 1349 return ret; 1350} 1351static int iwl5000_send_tx_power(struct iwl_priv *priv) 1352{ 1353 struct iwl5000_tx_power_dbm_cmd tx_power_cmd; 1354 u8 tx_ant_cfg_cmd; 1355 1356 /* half dBm need to multiply */ 1357 tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt); 1358 tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED; 1359 tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO; 1360 1361 if (IWL_UCODE_API(priv->ucode_ver) == 1) 1362 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD_V1; 1363 else 1364 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD; 1365 1366 return iwl_send_cmd_pdu_async(priv, tx_ant_cfg_cmd, 1367 sizeof(tx_power_cmd), &tx_power_cmd, 1368 NULL); 1369} 1370 1371static void iwl5000_temperature(struct iwl_priv *priv) 1372{ 1373 /* store temperature from statistics (in Celsius) */ 1374 priv->temperature = le32_to_cpu(priv->statistics.general.temperature); 1375} 1376 1377static void iwl5150_temperature(struct iwl_priv *priv) 1378{ 1379 u32 vt = 0; 1380 s32 offset = iwl_temp_calib_to_offset(priv); 1381 1382 vt = le32_to_cpu(priv->statistics.general.temperature); 1383 vt = vt / IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF + offset; 1384 /* now vt hold the temperature in Kelvin */ 1385 priv->temperature = KELVIN_TO_CELSIUS(vt); 1386} 1387 1388/* Calc max signal level (dBm) among 3 possible receivers */ 1389int iwl5000_calc_rssi(struct iwl_priv *priv, 1390 struct iwl_rx_phy_res *rx_resp) 1391{ 1392 /* data from PHY/DSP regarding signal strength, etc., 1393 * contents are always there, not configurable by host 1394 */ 1395 struct iwl5000_non_cfg_phy *ncphy = 1396 (struct iwl5000_non_cfg_phy *)rx_resp->non_cfg_phy_buf; 1397 u32 val, rssi_a, rssi_b, rssi_c, max_rssi; 1398 u8 agc; 1399 1400 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_AGC_IDX]); 1401 agc = (val & IWL50_OFDM_AGC_MSK) >> IWL50_OFDM_AGC_BIT_POS; 1402 1403 /* Find max rssi among 3 possible receivers. 1404 * These values are measured by the digital signal processor (DSP). 1405 * They should stay fairly constant even as the signal strength varies, 1406 * if the radio's automatic gain control (AGC) is working right. 1407 * AGC value (see below) will provide the "interesting" info. 1408 */ 1409 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_AB_IDX]); 1410 rssi_a = (val & IWL50_OFDM_RSSI_A_MSK) >> IWL50_OFDM_RSSI_A_BIT_POS; 1411 rssi_b = (val & IWL50_OFDM_RSSI_B_MSK) >> IWL50_OFDM_RSSI_B_BIT_POS; 1412 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_C_IDX]); 1413 rssi_c = (val & IWL50_OFDM_RSSI_C_MSK) >> IWL50_OFDM_RSSI_C_BIT_POS; 1414 1415 max_rssi = max_t(u32, rssi_a, rssi_b); 1416 max_rssi = max_t(u32, max_rssi, rssi_c); 1417 1418 IWL_DEBUG_STATS(priv, "Rssi In A %d B %d C %d Max %d AGC dB %d\n", 1419 rssi_a, rssi_b, rssi_c, max_rssi, agc); 1420 1421 /* dBm = max_rssi dB - agc dB - constant. 1422 * Higher AGC (higher radio gain) means lower signal. */ 1423 return max_rssi - agc - IWL49_RSSI_OFFSET; 1424} 1425 1426struct iwl_station_mgmt_ops iwl5000_station_mgmt = { 1427 .add_station = iwl_add_station_flags, 1428 .remove_station = iwl_remove_station, 1429 .find_station = iwl_find_station, 1430 .clear_station_table = iwl_clear_stations_table, 1431}; 1432 1433struct iwl_hcmd_ops iwl5000_hcmd = { 1434 .rxon_assoc = iwl5000_send_rxon_assoc, 1435 .commit_rxon = iwl_commit_rxon, 1436 .set_rxon_chain = iwl_set_rxon_chain, 1437}; 1438 1439struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = { 1440 .get_hcmd_size = iwl5000_get_hcmd_size, 1441 .build_addsta_hcmd = iwl5000_build_addsta_hcmd, 1442 .gain_computation = iwl5000_gain_computation, 1443 .chain_noise_reset = iwl5000_chain_noise_reset, 1444 .rts_tx_cmd_flag = iwl5000_rts_tx_cmd_flag, 1445 .calc_rssi = iwl5000_calc_rssi, 1446}; 1447 1448struct iwl_lib_ops iwl5000_lib = { 1449 .set_hw_params = iwl5000_hw_set_hw_params, 1450 .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl, 1451 .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl, 1452 .txq_set_sched = iwl5000_txq_set_sched, 1453 .txq_agg_enable = iwl5000_txq_agg_enable, 1454 .txq_agg_disable = iwl5000_txq_agg_disable, 1455 .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd, 1456 .txq_free_tfd = iwl_hw_txq_free_tfd, 1457 .txq_init = iwl_hw_tx_queue_init, 1458 .rx_handler_setup = iwl5000_rx_handler_setup, 1459 .setup_deferred_work = iwl5000_setup_deferred_work, 1460 .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr, 1461 .load_ucode = iwl5000_load_ucode, 1462 .init_alive_start = iwl5000_init_alive_start, 1463 .alive_notify = iwl5000_alive_notify, 1464 .send_tx_power = iwl5000_send_tx_power, 1465 .update_chain_flags = iwl_update_chain_flags, 1466 .apm_ops = { 1467 .init = iwl5000_apm_init, 1468 .reset = iwl5000_apm_reset, 1469 .stop = iwl5000_apm_stop, 1470 .config = iwl5000_nic_config, 1471 .set_pwr_src = iwl_set_pwr_src, 1472 }, 1473 .eeprom_ops = { 1474 .regulatory_bands = { 1475 EEPROM_5000_REG_BAND_1_CHANNELS, 1476 EEPROM_5000_REG_BAND_2_CHANNELS, 1477 EEPROM_5000_REG_BAND_3_CHANNELS, 1478 EEPROM_5000_REG_BAND_4_CHANNELS, 1479 EEPROM_5000_REG_BAND_5_CHANNELS, 1480 EEPROM_5000_REG_BAND_24_FAT_CHANNELS, 1481 EEPROM_5000_REG_BAND_52_FAT_CHANNELS 1482 }, 1483 .verify_signature = iwlcore_eeprom_verify_signature, 1484 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore, 1485 .release_semaphore = iwlcore_eeprom_release_semaphore, 1486 .calib_version = iwl5000_eeprom_calib_version, 1487 .query_addr = iwl5000_eeprom_query_addr, 1488 }, 1489 .post_associate = iwl_post_associate, 1490 .config_ap = iwl_config_ap, 1491 .temp_ops = { 1492 .temperature = iwl5000_temperature, 1493 .set_ct_kill = iwl5000_set_ct_threshold, 1494 }, 1495}; 1496 1497static struct iwl_lib_ops iwl5150_lib = { 1498 .set_hw_params = iwl5000_hw_set_hw_params, 1499 .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl, 1500 .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl, 1501 .txq_set_sched = iwl5000_txq_set_sched, 1502 .txq_agg_enable = iwl5000_txq_agg_enable, 1503 .txq_agg_disable = iwl5000_txq_agg_disable, 1504 .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd, 1505 .txq_free_tfd = iwl_hw_txq_free_tfd, 1506 .txq_init = iwl_hw_tx_queue_init, 1507 .rx_handler_setup = iwl5000_rx_handler_setup, 1508 .setup_deferred_work = iwl5000_setup_deferred_work, 1509 .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr, 1510 .load_ucode = iwl5000_load_ucode, 1511 .init_alive_start = iwl5000_init_alive_start, 1512 .alive_notify = iwl5000_alive_notify, 1513 .send_tx_power = iwl5000_send_tx_power, 1514 .update_chain_flags = iwl_update_chain_flags, 1515 .apm_ops = { 1516 .init = iwl5000_apm_init, 1517 .reset = iwl5000_apm_reset, 1518 .stop = iwl5000_apm_stop, 1519 .config = iwl5000_nic_config, 1520 .set_pwr_src = iwl_set_pwr_src, 1521 }, 1522 .eeprom_ops = { 1523 .regulatory_bands = { 1524 EEPROM_5000_REG_BAND_1_CHANNELS, 1525 EEPROM_5000_REG_BAND_2_CHANNELS, 1526 EEPROM_5000_REG_BAND_3_CHANNELS, 1527 EEPROM_5000_REG_BAND_4_CHANNELS, 1528 EEPROM_5000_REG_BAND_5_CHANNELS, 1529 EEPROM_5000_REG_BAND_24_FAT_CHANNELS, 1530 EEPROM_5000_REG_BAND_52_FAT_CHANNELS 1531 }, 1532 .verify_signature = iwlcore_eeprom_verify_signature, 1533 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore, 1534 .release_semaphore = iwlcore_eeprom_release_semaphore, 1535 .calib_version = iwl5000_eeprom_calib_version, 1536 .query_addr = iwl5000_eeprom_query_addr, 1537 }, 1538 .post_associate = iwl_post_associate, 1539 .config_ap = iwl_config_ap, 1540 .temp_ops = { 1541 .temperature = iwl5150_temperature, 1542 .set_ct_kill = iwl5150_set_ct_threshold, 1543 }, 1544}; 1545 1546struct iwl_ops iwl5000_ops = { 1547 .lib = &iwl5000_lib, 1548 .hcmd = &iwl5000_hcmd, 1549 .utils = &iwl5000_hcmd_utils, 1550 .smgmt = &iwl5000_station_mgmt, 1551}; 1552 1553static struct iwl_ops iwl5150_ops = { 1554 .lib = &iwl5150_lib, 1555 .hcmd = &iwl5000_hcmd, 1556 .utils = &iwl5000_hcmd_utils, 1557 .smgmt = &iwl5000_station_mgmt, 1558}; 1559 1560struct iwl_mod_params iwl50_mod_params = { 1561 .num_of_queues = IWL50_NUM_QUEUES, 1562 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES, 1563 .amsdu_size_8K = 1, 1564 .restart_fw = 1, 1565 /* the rest are 0 by default */ 1566}; 1567 1568 1569struct iwl_cfg iwl5300_agn_cfg = { 1570 .name = "5300AGN", 1571 .fw_name_pre = IWL5000_FW_PRE, 1572 .ucode_api_max = IWL5000_UCODE_API_MAX, 1573 .ucode_api_min = IWL5000_UCODE_API_MIN, 1574 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N, 1575 .ops = &iwl5000_ops, 1576 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, 1577 .eeprom_ver = EEPROM_5000_EEPROM_VERSION, 1578 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION, 1579 .mod_params = &iwl50_mod_params, 1580 .valid_tx_ant = ANT_ABC, 1581 .valid_rx_ant = ANT_ABC, 1582 .need_pll_cfg = true, 1583}; 1584 1585struct iwl_cfg iwl5100_bg_cfg = { 1586 .name = "5100BG", 1587 .fw_name_pre = IWL5000_FW_PRE, 1588 .ucode_api_max = IWL5000_UCODE_API_MAX, 1589 .ucode_api_min = IWL5000_UCODE_API_MIN, 1590 .sku = IWL_SKU_G, 1591 .ops = &iwl5000_ops, 1592 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, 1593 .eeprom_ver = EEPROM_5000_EEPROM_VERSION, 1594 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION, 1595 .mod_params = &iwl50_mod_params, 1596 .valid_tx_ant = ANT_B, 1597 .valid_rx_ant = ANT_AB, 1598 .need_pll_cfg = true, 1599}; 1600 1601struct iwl_cfg iwl5100_abg_cfg = { 1602 .name = "5100ABG", 1603 .fw_name_pre = IWL5000_FW_PRE, 1604 .ucode_api_max = IWL5000_UCODE_API_MAX, 1605 .ucode_api_min = IWL5000_UCODE_API_MIN, 1606 .sku = IWL_SKU_A|IWL_SKU_G, 1607 .ops = &iwl5000_ops, 1608 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, 1609 .eeprom_ver = EEPROM_5000_EEPROM_VERSION, 1610 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION, 1611 .mod_params = &iwl50_mod_params, 1612 .valid_tx_ant = ANT_B, 1613 .valid_rx_ant = ANT_AB, 1614 .need_pll_cfg = true, 1615}; 1616 1617struct iwl_cfg iwl5100_agn_cfg = { 1618 .name = "5100AGN", 1619 .fw_name_pre = IWL5000_FW_PRE, 1620 .ucode_api_max = IWL5000_UCODE_API_MAX, 1621 .ucode_api_min = IWL5000_UCODE_API_MIN, 1622 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N, 1623 .ops = &iwl5000_ops, 1624 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, 1625 .eeprom_ver = EEPROM_5000_EEPROM_VERSION, 1626 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION, 1627 .mod_params = &iwl50_mod_params, 1628 .valid_tx_ant = ANT_B, 1629 .valid_rx_ant = ANT_AB, 1630 .need_pll_cfg = true, 1631}; 1632 1633struct iwl_cfg iwl5350_agn_cfg = { 1634 .name = "5350AGN", 1635 .fw_name_pre = IWL5000_FW_PRE, 1636 .ucode_api_max = IWL5000_UCODE_API_MAX, 1637 .ucode_api_min = IWL5000_UCODE_API_MIN, 1638 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N, 1639 .ops = &iwl5000_ops, 1640 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, 1641 .eeprom_ver = EEPROM_5050_EEPROM_VERSION, 1642 .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION, 1643 .mod_params = &iwl50_mod_params, 1644 .valid_tx_ant = ANT_ABC, 1645 .valid_rx_ant = ANT_ABC, 1646 .need_pll_cfg = true, 1647}; 1648 1649struct iwl_cfg iwl5150_agn_cfg = { 1650 .name = "5150AGN", 1651 .fw_name_pre = IWL5150_FW_PRE, 1652 .ucode_api_max = IWL5150_UCODE_API_MAX, 1653 .ucode_api_min = IWL5150_UCODE_API_MIN, 1654 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N, 1655 .ops = &iwl5150_ops, 1656 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, 1657 .eeprom_ver = EEPROM_5050_EEPROM_VERSION, 1658 .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION, 1659 .mod_params = &iwl50_mod_params, 1660 .valid_tx_ant = ANT_A, 1661 .valid_rx_ant = ANT_AB, 1662 .need_pll_cfg = true, 1663}; 1664 1665MODULE_FIRMWARE(IWL5000_MODULE_FIRMWARE(IWL5000_UCODE_API_MAX)); 1666MODULE_FIRMWARE(IWL5150_MODULE_FIRMWARE(IWL5150_UCODE_API_MAX)); 1667 1668module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, 0444); 1669MODULE_PARM_DESC(swcrypto50, 1670 "using software crypto engine (default 0 [hardware])\n"); 1671module_param_named(debug50, iwl50_mod_params.debug, uint, 0444); 1672MODULE_PARM_DESC(debug50, "50XX debug output mask"); 1673module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, 0444); 1674MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series"); 1675module_param_named(11n_disable50, iwl50_mod_params.disable_11n, int, 0444); 1676MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality"); 1677module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K, int, 0444); 1678MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series"); 1679module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, 0444); 1680MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error"); 1681