iwl-5000.c revision b74e31a9bc1013e69b85b139072485dc153453dd
1/****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2010 Intel Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * The full GNU General Public License is included in this distribution in the 19 * file called LICENSE. 20 * 21 * Contact Information: 22 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 23 * 24 *****************************************************************************/ 25 26#include <linux/kernel.h> 27#include <linux/module.h> 28#include <linux/init.h> 29#include <linux/pci.h> 30#include <linux/dma-mapping.h> 31#include <linux/delay.h> 32#include <linux/sched.h> 33#include <linux/skbuff.h> 34#include <linux/netdevice.h> 35#include <linux/wireless.h> 36#include <net/mac80211.h> 37#include <linux/etherdevice.h> 38#include <asm/unaligned.h> 39 40#include "iwl-eeprom.h" 41#include "iwl-dev.h" 42#include "iwl-core.h" 43#include "iwl-io.h" 44#include "iwl-sta.h" 45#include "iwl-helpers.h" 46#include "iwl-agn.h" 47#include "iwl-agn-led.h" 48#include "iwl-5000-hw.h" 49#include "iwl-6000-hw.h" 50 51/* Highest firmware API version supported */ 52#define IWL5000_UCODE_API_MAX 2 53#define IWL5150_UCODE_API_MAX 2 54 55/* Lowest firmware API version supported */ 56#define IWL5000_UCODE_API_MIN 1 57#define IWL5150_UCODE_API_MIN 1 58 59#define IWL5000_FW_PRE "iwlwifi-5000-" 60#define _IWL5000_MODULE_FIRMWARE(api) IWL5000_FW_PRE #api ".ucode" 61#define IWL5000_MODULE_FIRMWARE(api) _IWL5000_MODULE_FIRMWARE(api) 62 63#define IWL5150_FW_PRE "iwlwifi-5150-" 64#define _IWL5150_MODULE_FIRMWARE(api) IWL5150_FW_PRE #api ".ucode" 65#define IWL5150_MODULE_FIRMWARE(api) _IWL5150_MODULE_FIRMWARE(api) 66 67static const s8 iwl5000_default_queue_to_tx_fifo[] = { 68 IWL_TX_FIFO_VO, 69 IWL_TX_FIFO_VI, 70 IWL_TX_FIFO_BE, 71 IWL_TX_FIFO_BK, 72 IWL50_CMD_FIFO_NUM, 73 IWL_TX_FIFO_UNUSED, 74 IWL_TX_FIFO_UNUSED, 75 IWL_TX_FIFO_UNUSED, 76 IWL_TX_FIFO_UNUSED, 77 IWL_TX_FIFO_UNUSED, 78}; 79 80/* NIC configuration for 5000 series */ 81void iwl5000_nic_config(struct iwl_priv *priv) 82{ 83 unsigned long flags; 84 u16 radio_cfg; 85 86 spin_lock_irqsave(&priv->lock, flags); 87 88 radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG); 89 90 /* write radio config values to register */ 91 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_RF_CONFIG_TYPE_MAX) 92 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, 93 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) | 94 EEPROM_RF_CFG_STEP_MSK(radio_cfg) | 95 EEPROM_RF_CFG_DASH_MSK(radio_cfg)); 96 97 /* set CSR_HW_CONFIG_REG for uCode use */ 98 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, 99 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI | 100 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI); 101 102 /* W/A : NIC is stuck in a reset state after Early PCIe power off 103 * (PCIe power is lost before PERST# is asserted), 104 * causing ME FW to lose ownership and not being able to obtain it back. 105 */ 106 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, 107 APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS, 108 ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS); 109 110 111 spin_unlock_irqrestore(&priv->lock, flags); 112} 113 114 115/* 116 * EEPROM 117 */ 118static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address) 119{ 120 u16 offset = 0; 121 122 if ((address & INDIRECT_ADDRESS) == 0) 123 return address; 124 125 switch (address & INDIRECT_TYPE_MSK) { 126 case INDIRECT_HOST: 127 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST); 128 break; 129 case INDIRECT_GENERAL: 130 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL); 131 break; 132 case INDIRECT_REGULATORY: 133 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY); 134 break; 135 case INDIRECT_CALIBRATION: 136 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION); 137 break; 138 case INDIRECT_PROCESS_ADJST: 139 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST); 140 break; 141 case INDIRECT_OTHERS: 142 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS); 143 break; 144 default: 145 IWL_ERR(priv, "illegal indirect type: 0x%X\n", 146 address & INDIRECT_TYPE_MSK); 147 break; 148 } 149 150 /* translate the offset from words to byte */ 151 return (address & ADDRESS_MSK) + (offset << 1); 152} 153 154u16 iwl5000_eeprom_calib_version(struct iwl_priv *priv) 155{ 156 struct iwl_eeprom_calib_hdr { 157 u8 version; 158 u8 pa_type; 159 u16 voltage; 160 } *hdr; 161 162 hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv, 163 EEPROM_5000_CALIB_ALL); 164 return hdr->version; 165 166} 167 168static void iwl5000_gain_computation(struct iwl_priv *priv, 169 u32 average_noise[NUM_RX_CHAINS], 170 u16 min_average_noise_antenna_i, 171 u32 min_average_noise, 172 u8 default_chain) 173{ 174 int i; 175 s32 delta_g; 176 struct iwl_chain_noise_data *data = &priv->chain_noise_data; 177 178 /* 179 * Find Gain Code for the chains based on "default chain" 180 */ 181 for (i = default_chain + 1; i < NUM_RX_CHAINS; i++) { 182 if ((data->disconn_array[i])) { 183 data->delta_gain_code[i] = 0; 184 continue; 185 } 186 187 delta_g = (priv->cfg->chain_noise_scale * 188 ((s32)average_noise[default_chain] - 189 (s32)average_noise[i])) / 1500; 190 191 /* bound gain by 2 bits value max, 3rd bit is sign */ 192 data->delta_gain_code[i] = 193 min(abs(delta_g), (long) CHAIN_NOISE_MAX_DELTA_GAIN_CODE); 194 195 if (delta_g < 0) 196 /* 197 * set negative sign ... 198 * note to Intel developers: This is uCode API format, 199 * not the format of any internal device registers. 200 * Do not change this format for e.g. 6050 or similar 201 * devices. Change format only if more resolution 202 * (i.e. more than 2 bits magnitude) is needed. 203 */ 204 data->delta_gain_code[i] |= (1 << 2); 205 } 206 207 IWL_DEBUG_CALIB(priv, "Delta gains: ANT_B = %d ANT_C = %d\n", 208 data->delta_gain_code[1], data->delta_gain_code[2]); 209 210 if (!data->radio_write) { 211 struct iwl_calib_chain_noise_gain_cmd cmd; 212 213 memset(&cmd, 0, sizeof(cmd)); 214 215 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD; 216 cmd.hdr.first_group = 0; 217 cmd.hdr.groups_num = 1; 218 cmd.hdr.data_valid = 1; 219 cmd.delta_gain_1 = data->delta_gain_code[1]; 220 cmd.delta_gain_2 = data->delta_gain_code[2]; 221 iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD, 222 sizeof(cmd), &cmd, NULL); 223 224 data->radio_write = 1; 225 data->state = IWL_CHAIN_NOISE_CALIBRATED; 226 } 227 228 data->chain_noise_a = 0; 229 data->chain_noise_b = 0; 230 data->chain_noise_c = 0; 231 data->chain_signal_a = 0; 232 data->chain_signal_b = 0; 233 data->chain_signal_c = 0; 234 data->beacon_count = 0; 235} 236 237static void iwl5000_chain_noise_reset(struct iwl_priv *priv) 238{ 239 struct iwl_chain_noise_data *data = &priv->chain_noise_data; 240 int ret; 241 242 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) { 243 struct iwl_calib_chain_noise_reset_cmd cmd; 244 memset(&cmd, 0, sizeof(cmd)); 245 246 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD; 247 cmd.hdr.first_group = 0; 248 cmd.hdr.groups_num = 1; 249 cmd.hdr.data_valid = 1; 250 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD, 251 sizeof(cmd), &cmd); 252 if (ret) 253 IWL_ERR(priv, 254 "Could not send REPLY_PHY_CALIBRATION_CMD\n"); 255 data->state = IWL_CHAIN_NOISE_ACCUMULATE; 256 IWL_DEBUG_CALIB(priv, "Run chain_noise_calibrate\n"); 257 } 258} 259 260void iwl5000_rts_tx_cmd_flag(struct ieee80211_tx_info *info, 261 __le32 *tx_flags) 262{ 263 if ((info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) || 264 (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT)) 265 *tx_flags |= TX_CMD_FLG_RTS_CTS_MSK; 266 else 267 *tx_flags &= ~TX_CMD_FLG_RTS_CTS_MSK; 268} 269 270static struct iwl_sensitivity_ranges iwl5000_sensitivity = { 271 .min_nrg_cck = 95, 272 .max_nrg_cck = 0, /* not used, set to 0 */ 273 .auto_corr_min_ofdm = 90, 274 .auto_corr_min_ofdm_mrc = 170, 275 .auto_corr_min_ofdm_x1 = 120, 276 .auto_corr_min_ofdm_mrc_x1 = 240, 277 278 .auto_corr_max_ofdm = 120, 279 .auto_corr_max_ofdm_mrc = 210, 280 .auto_corr_max_ofdm_x1 = 120, 281 .auto_corr_max_ofdm_mrc_x1 = 240, 282 283 .auto_corr_min_cck = 125, 284 .auto_corr_max_cck = 200, 285 .auto_corr_min_cck_mrc = 170, 286 .auto_corr_max_cck_mrc = 400, 287 .nrg_th_cck = 95, 288 .nrg_th_ofdm = 95, 289 290 .barker_corr_th_min = 190, 291 .barker_corr_th_min_mrc = 390, 292 .nrg_th_cca = 62, 293}; 294 295static struct iwl_sensitivity_ranges iwl5150_sensitivity = { 296 .min_nrg_cck = 95, 297 .max_nrg_cck = 0, /* not used, set to 0 */ 298 .auto_corr_min_ofdm = 90, 299 .auto_corr_min_ofdm_mrc = 170, 300 .auto_corr_min_ofdm_x1 = 105, 301 .auto_corr_min_ofdm_mrc_x1 = 220, 302 303 .auto_corr_max_ofdm = 120, 304 .auto_corr_max_ofdm_mrc = 210, 305 /* max = min for performance bug in 5150 DSP */ 306 .auto_corr_max_ofdm_x1 = 105, 307 .auto_corr_max_ofdm_mrc_x1 = 220, 308 309 .auto_corr_min_cck = 125, 310 .auto_corr_max_cck = 200, 311 .auto_corr_min_cck_mrc = 170, 312 .auto_corr_max_cck_mrc = 400, 313 .nrg_th_cck = 95, 314 .nrg_th_ofdm = 95, 315 316 .barker_corr_th_min = 190, 317 .barker_corr_th_min_mrc = 390, 318 .nrg_th_cca = 62, 319}; 320 321const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv, 322 size_t offset) 323{ 324 u32 address = eeprom_indirect_address(priv, offset); 325 BUG_ON(address >= priv->cfg->eeprom_size); 326 return &priv->eeprom[address]; 327} 328 329static void iwl5150_set_ct_threshold(struct iwl_priv *priv) 330{ 331 const s32 volt2temp_coef = IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF; 332 s32 threshold = (s32)CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD_LEGACY) - 333 iwl_temp_calib_to_offset(priv); 334 335 priv->hw_params.ct_kill_threshold = threshold * volt2temp_coef; 336} 337 338static void iwl5000_set_ct_threshold(struct iwl_priv *priv) 339{ 340 /* want Celsius */ 341 priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD_LEGACY; 342} 343 344/* 345 * Calibration 346 */ 347static int iwl5000_set_Xtal_calib(struct iwl_priv *priv) 348{ 349 struct iwl_calib_xtal_freq_cmd cmd; 350 __le16 *xtal_calib = 351 (__le16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_XTAL); 352 353 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD; 354 cmd.hdr.first_group = 0; 355 cmd.hdr.groups_num = 1; 356 cmd.hdr.data_valid = 1; 357 cmd.cap_pin1 = le16_to_cpu(xtal_calib[0]); 358 cmd.cap_pin2 = le16_to_cpu(xtal_calib[1]); 359 return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL], 360 (u8 *)&cmd, sizeof(cmd)); 361} 362 363static int iwl5000_send_calib_cfg(struct iwl_priv *priv) 364{ 365 struct iwl_calib_cfg_cmd calib_cfg_cmd; 366 struct iwl_host_cmd cmd = { 367 .id = CALIBRATION_CFG_CMD, 368 .len = sizeof(struct iwl_calib_cfg_cmd), 369 .data = &calib_cfg_cmd, 370 }; 371 372 memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd)); 373 calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL; 374 calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL; 375 calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL; 376 calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL; 377 378 return iwl_send_cmd(priv, &cmd); 379} 380 381static void iwl5000_rx_calib_result(struct iwl_priv *priv, 382 struct iwl_rx_mem_buffer *rxb) 383{ 384 struct iwl_rx_packet *pkt = rxb_addr(rxb); 385 struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw; 386 int len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK; 387 int index; 388 389 /* reduce the size of the length field itself */ 390 len -= 4; 391 392 /* Define the order in which the results will be sent to the runtime 393 * uCode. iwl_send_calib_results sends them in a row according to their 394 * index. We sort them here */ 395 switch (hdr->op_code) { 396 case IWL_PHY_CALIBRATE_DC_CMD: 397 index = IWL_CALIB_DC; 398 break; 399 case IWL_PHY_CALIBRATE_LO_CMD: 400 index = IWL_CALIB_LO; 401 break; 402 case IWL_PHY_CALIBRATE_TX_IQ_CMD: 403 index = IWL_CALIB_TX_IQ; 404 break; 405 case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD: 406 index = IWL_CALIB_TX_IQ_PERD; 407 break; 408 case IWL_PHY_CALIBRATE_BASE_BAND_CMD: 409 index = IWL_CALIB_BASE_BAND; 410 break; 411 default: 412 IWL_ERR(priv, "Unknown calibration notification %d\n", 413 hdr->op_code); 414 return; 415 } 416 iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len); 417} 418 419static void iwl5000_rx_calib_complete(struct iwl_priv *priv, 420 struct iwl_rx_mem_buffer *rxb) 421{ 422 IWL_DEBUG_INFO(priv, "Init. calibration is completed, restarting fw.\n"); 423 queue_work(priv->workqueue, &priv->restart); 424} 425 426/* 427 * ucode 428 */ 429static int iwl5000_load_section(struct iwl_priv *priv, const char *name, 430 struct fw_desc *image, u32 dst_addr) 431{ 432 dma_addr_t phy_addr = image->p_addr; 433 u32 byte_cnt = image->len; 434 int ret; 435 436 priv->ucode_write_complete = 0; 437 438 iwl_write_direct32(priv, 439 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 440 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); 441 442 iwl_write_direct32(priv, 443 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr); 444 445 iwl_write_direct32(priv, 446 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), 447 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); 448 449 iwl_write_direct32(priv, 450 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), 451 (iwl_get_dma_hi_addr(phy_addr) 452 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); 453 454 iwl_write_direct32(priv, 455 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), 456 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM | 457 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX | 458 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); 459 460 iwl_write_direct32(priv, 461 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 462 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 463 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | 464 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); 465 466 IWL_DEBUG_INFO(priv, "%s uCode section being loaded...\n", name); 467 ret = wait_event_interruptible_timeout(priv->wait_command_queue, 468 priv->ucode_write_complete, 5 * HZ); 469 if (ret == -ERESTARTSYS) { 470 IWL_ERR(priv, "Could not load the %s uCode section due " 471 "to interrupt\n", name); 472 return ret; 473 } 474 if (!ret) { 475 IWL_ERR(priv, "Could not load the %s uCode section\n", 476 name); 477 return -ETIMEDOUT; 478 } 479 480 return 0; 481} 482 483static int iwl5000_load_given_ucode(struct iwl_priv *priv, 484 struct fw_desc *inst_image, 485 struct fw_desc *data_image) 486{ 487 int ret = 0; 488 489 ret = iwl5000_load_section(priv, "INST", inst_image, 490 IWL50_RTC_INST_LOWER_BOUND); 491 if (ret) 492 return ret; 493 494 return iwl5000_load_section(priv, "DATA", data_image, 495 IWL50_RTC_DATA_LOWER_BOUND); 496} 497 498int iwl5000_load_ucode(struct iwl_priv *priv) 499{ 500 int ret = 0; 501 502 /* check whether init ucode should be loaded, or rather runtime ucode */ 503 if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) { 504 IWL_DEBUG_INFO(priv, "Init ucode found. Loading init ucode...\n"); 505 ret = iwl5000_load_given_ucode(priv, 506 &priv->ucode_init, &priv->ucode_init_data); 507 if (!ret) { 508 IWL_DEBUG_INFO(priv, "Init ucode load complete.\n"); 509 priv->ucode_type = UCODE_INIT; 510 } 511 } else { 512 IWL_DEBUG_INFO(priv, "Init ucode not found, or already loaded. " 513 "Loading runtime ucode...\n"); 514 ret = iwl5000_load_given_ucode(priv, 515 &priv->ucode_code, &priv->ucode_data); 516 if (!ret) { 517 IWL_DEBUG_INFO(priv, "Runtime ucode load complete.\n"); 518 priv->ucode_type = UCODE_RT; 519 } 520 } 521 522 return ret; 523} 524 525void iwl5000_init_alive_start(struct iwl_priv *priv) 526{ 527 int ret = 0; 528 529 /* Check alive response for "valid" sign from uCode */ 530 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) { 531 /* We had an error bringing up the hardware, so take it 532 * all the way back down so we can try again */ 533 IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n"); 534 goto restart; 535 } 536 537 /* initialize uCode was loaded... verify inst image. 538 * This is a paranoid check, because we would not have gotten the 539 * "initialize" alive if code weren't properly loaded. */ 540 if (iwl_verify_ucode(priv)) { 541 /* Runtime instruction load was bad; 542 * take it all the way back down so we can try again */ 543 IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n"); 544 goto restart; 545 } 546 547 ret = priv->cfg->ops->lib->alive_notify(priv); 548 if (ret) { 549 IWL_WARN(priv, 550 "Could not complete ALIVE transition: %d\n", ret); 551 goto restart; 552 } 553 554 iwl5000_send_calib_cfg(priv); 555 return; 556 557restart: 558 /* real restart (first load init_ucode) */ 559 queue_work(priv->workqueue, &priv->restart); 560} 561 562static void iwl5000_set_wr_ptrs(struct iwl_priv *priv, 563 int txq_id, u32 index) 564{ 565 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 566 (index & 0xff) | (txq_id << 8)); 567 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index); 568} 569 570static void iwl5000_tx_queue_set_status(struct iwl_priv *priv, 571 struct iwl_tx_queue *txq, 572 int tx_fifo_id, int scd_retry) 573{ 574 int txq_id = txq->q.id; 575 int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0; 576 577 iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id), 578 (active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) | 579 (tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) | 580 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) | 581 IWL50_SCD_QUEUE_STTS_REG_MSK); 582 583 txq->sched_retry = scd_retry; 584 585 IWL_DEBUG_INFO(priv, "%s %s Queue %d on FIFO %d\n", 586 active ? "Activate" : "Deactivate", 587 scd_retry ? "BA" : "AC/CMD", txq_id, tx_fifo_id); 588} 589 590int iwl5000_alive_notify(struct iwl_priv *priv) 591{ 592 u32 a; 593 unsigned long flags; 594 int i, chan; 595 u32 reg_val; 596 597 spin_lock_irqsave(&priv->lock, flags); 598 599 priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR); 600 a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET; 601 for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET; 602 a += 4) 603 iwl_write_targ_mem(priv, a, 0); 604 for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET; 605 a += 4) 606 iwl_write_targ_mem(priv, a, 0); 607 for (; a < priv->scd_base_addr + 608 IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(priv->hw_params.max_txq_num); a += 4) 609 iwl_write_targ_mem(priv, a, 0); 610 611 iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR, 612 priv->scd_bc_tbls.dma >> 10); 613 614 /* Enable DMA channel */ 615 for (chan = 0; chan < FH50_TCSR_CHNL_NUM ; chan++) 616 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan), 617 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 618 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE); 619 620 /* Update FH chicken bits */ 621 reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG); 622 iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG, 623 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN); 624 625 iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, 626 IWL50_SCD_QUEUECHAIN_SEL_ALL(priv->hw_params.max_txq_num)); 627 iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0); 628 629 /* initiate the queues */ 630 for (i = 0; i < priv->hw_params.max_txq_num; i++) { 631 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0); 632 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8)); 633 iwl_write_targ_mem(priv, priv->scd_base_addr + 634 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0); 635 iwl_write_targ_mem(priv, priv->scd_base_addr + 636 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) + 637 sizeof(u32), 638 ((SCD_WIN_SIZE << 639 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & 640 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | 641 ((SCD_FRAME_LIMIT << 642 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & 643 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); 644 } 645 646 iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK, 647 IWL_MASK(0, priv->hw_params.max_txq_num)); 648 649 /* Activate all Tx DMA/FIFO channels */ 650 priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7)); 651 652 iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0); 653 654 /* make sure all queue are not stopped */ 655 memset(&priv->queue_stopped[0], 0, sizeof(priv->queue_stopped)); 656 for (i = 0; i < 4; i++) 657 atomic_set(&priv->queue_stop_count[i], 0); 658 659 /* reset to 0 to enable all the queue first */ 660 priv->txq_ctx_active_msk = 0; 661 /* map qos queues to fifos one-to-one */ 662 BUILD_BUG_ON(ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo) != 10); 663 664 for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) { 665 int ac = iwl5000_default_queue_to_tx_fifo[i]; 666 667 iwl_txq_ctx_activate(priv, i); 668 669 if (ac == IWL_TX_FIFO_UNUSED) 670 continue; 671 672 iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0); 673 } 674 675 spin_unlock_irqrestore(&priv->lock, flags); 676 677 iwl_send_wimax_coex(priv); 678 679 iwl5000_set_Xtal_calib(priv); 680 iwl_send_calib_results(priv); 681 682 return 0; 683} 684 685int iwl5000_hw_set_hw_params(struct iwl_priv *priv) 686{ 687 if (priv->cfg->mod_params->num_of_queues >= IWL_MIN_NUM_QUEUES && 688 priv->cfg->mod_params->num_of_queues <= IWL50_NUM_QUEUES) 689 priv->cfg->num_of_queues = 690 priv->cfg->mod_params->num_of_queues; 691 692 priv->hw_params.max_txq_num = priv->cfg->num_of_queues; 693 priv->hw_params.dma_chnl_num = FH50_TCSR_CHNL_NUM; 694 priv->hw_params.scd_bc_tbls_size = 695 priv->cfg->num_of_queues * 696 sizeof(struct iwl5000_scd_bc_tbl); 697 priv->hw_params.tfd_size = sizeof(struct iwl_tfd); 698 priv->hw_params.max_stations = IWL5000_STATION_COUNT; 699 priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID; 700 701 priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE; 702 priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE; 703 704 priv->hw_params.max_bsm_size = 0; 705 priv->hw_params.ht40_channel = BIT(IEEE80211_BAND_2GHZ) | 706 BIT(IEEE80211_BAND_5GHZ); 707 priv->hw_params.rx_wrt_ptr_reg = FH_RSCSR_CHNL0_WPTR; 708 709 priv->hw_params.tx_chains_num = num_of_ant(priv->cfg->valid_tx_ant); 710 priv->hw_params.rx_chains_num = num_of_ant(priv->cfg->valid_rx_ant); 711 priv->hw_params.valid_tx_ant = priv->cfg->valid_tx_ant; 712 priv->hw_params.valid_rx_ant = priv->cfg->valid_rx_ant; 713 714 if (priv->cfg->ops->lib->temp_ops.set_ct_kill) 715 priv->cfg->ops->lib->temp_ops.set_ct_kill(priv); 716 717 /* Set initial sensitivity parameters */ 718 /* Set initial calibration set */ 719 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) { 720 case CSR_HW_REV_TYPE_5150: 721 priv->hw_params.sens = &iwl5150_sensitivity; 722 priv->hw_params.calib_init_cfg = 723 BIT(IWL_CALIB_DC) | 724 BIT(IWL_CALIB_LO) | 725 BIT(IWL_CALIB_TX_IQ) | 726 BIT(IWL_CALIB_BASE_BAND); 727 728 break; 729 default: 730 priv->hw_params.sens = &iwl5000_sensitivity; 731 priv->hw_params.calib_init_cfg = 732 BIT(IWL_CALIB_XTAL) | 733 BIT(IWL_CALIB_LO) | 734 BIT(IWL_CALIB_TX_IQ) | 735 BIT(IWL_CALIB_TX_IQ_PERD) | 736 BIT(IWL_CALIB_BASE_BAND); 737 break; 738 } 739 740 return 0; 741} 742 743/** 744 * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array 745 */ 746void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv, 747 struct iwl_tx_queue *txq, 748 u16 byte_cnt) 749{ 750 struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr; 751 int write_ptr = txq->q.write_ptr; 752 int txq_id = txq->q.id; 753 u8 sec_ctl = 0; 754 u8 sta_id = 0; 755 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE; 756 __le16 bc_ent; 757 758 WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX); 759 760 if (txq_id != IWL_CMD_QUEUE_NUM) { 761 sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id; 762 sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl; 763 764 switch (sec_ctl & TX_CMD_SEC_MSK) { 765 case TX_CMD_SEC_CCM: 766 len += CCMP_MIC_LEN; 767 break; 768 case TX_CMD_SEC_TKIP: 769 len += TKIP_ICV_LEN; 770 break; 771 case TX_CMD_SEC_WEP: 772 len += WEP_IV_LEN + WEP_ICV_LEN; 773 break; 774 } 775 } 776 777 bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12)); 778 779 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent; 780 781 if (write_ptr < TFD_QUEUE_SIZE_BC_DUP) 782 scd_bc_tbl[txq_id]. 783 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent; 784} 785 786void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv, 787 struct iwl_tx_queue *txq) 788{ 789 struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr; 790 int txq_id = txq->q.id; 791 int read_ptr = txq->q.read_ptr; 792 u8 sta_id = 0; 793 __le16 bc_ent; 794 795 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX); 796 797 if (txq_id != IWL_CMD_QUEUE_NUM) 798 sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id; 799 800 bc_ent = cpu_to_le16(1 | (sta_id << 12)); 801 scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent; 802 803 if (read_ptr < TFD_QUEUE_SIZE_BC_DUP) 804 scd_bc_tbl[txq_id]. 805 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent; 806} 807 808static int iwl5000_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid, 809 u16 txq_id) 810{ 811 u32 tbl_dw_addr; 812 u32 tbl_dw; 813 u16 scd_q2ratid; 814 815 scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK; 816 817 tbl_dw_addr = priv->scd_base_addr + 818 IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id); 819 820 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr); 821 822 if (txq_id & 0x1) 823 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF); 824 else 825 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000); 826 827 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw); 828 829 return 0; 830} 831static void iwl5000_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id) 832{ 833 /* Simply stop the queue, but don't change any configuration; 834 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */ 835 iwl_write_prph(priv, 836 IWL50_SCD_QUEUE_STATUS_BITS(txq_id), 837 (0 << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE)| 838 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN)); 839} 840 841int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id, 842 int tx_fifo, int sta_id, int tid, u16 ssn_idx) 843{ 844 unsigned long flags; 845 u16 ra_tid; 846 847 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) || 848 (IWL50_FIRST_AMPDU_QUEUE + priv->cfg->num_of_ampdu_queues 849 <= txq_id)) { 850 IWL_WARN(priv, 851 "queue number out of range: %d, must be %d to %d\n", 852 txq_id, IWL50_FIRST_AMPDU_QUEUE, 853 IWL50_FIRST_AMPDU_QUEUE + 854 priv->cfg->num_of_ampdu_queues - 1); 855 return -EINVAL; 856 } 857 858 ra_tid = BUILD_RAxTID(sta_id, tid); 859 860 /* Modify device's station table to Tx this TID */ 861 iwl_sta_tx_modify_enable_tid(priv, sta_id, tid); 862 863 spin_lock_irqsave(&priv->lock, flags); 864 865 /* Stop this Tx queue before configuring it */ 866 iwl5000_tx_queue_stop_scheduler(priv, txq_id); 867 868 /* Map receiver-address / traffic-ID to this queue */ 869 iwl5000_tx_queue_set_q2ratid(priv, ra_tid, txq_id); 870 871 /* Set this queue as a chain-building queue */ 872 iwl_set_bits_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, (1<<txq_id)); 873 874 /* enable aggregations for the queue */ 875 iwl_set_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1<<txq_id)); 876 877 /* Place first TFD at index corresponding to start sequence number. 878 * Assumes that ssn_idx is valid (!= 0xFFF) */ 879 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff); 880 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff); 881 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx); 882 883 /* Set up Tx window size and frame limit for this queue */ 884 iwl_write_targ_mem(priv, priv->scd_base_addr + 885 IWL50_SCD_CONTEXT_QUEUE_OFFSET(txq_id) + 886 sizeof(u32), 887 ((SCD_WIN_SIZE << 888 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & 889 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | 890 ((SCD_FRAME_LIMIT << 891 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & 892 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); 893 894 iwl_set_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id)); 895 896 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */ 897 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1); 898 899 spin_unlock_irqrestore(&priv->lock, flags); 900 901 return 0; 902} 903 904int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id, 905 u16 ssn_idx, u8 tx_fifo) 906{ 907 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) || 908 (IWL50_FIRST_AMPDU_QUEUE + priv->cfg->num_of_ampdu_queues 909 <= txq_id)) { 910 IWL_ERR(priv, 911 "queue number out of range: %d, must be %d to %d\n", 912 txq_id, IWL50_FIRST_AMPDU_QUEUE, 913 IWL50_FIRST_AMPDU_QUEUE + 914 priv->cfg->num_of_ampdu_queues - 1); 915 return -EINVAL; 916 } 917 918 iwl5000_tx_queue_stop_scheduler(priv, txq_id); 919 920 iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id)); 921 922 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff); 923 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff); 924 /* supposes that ssn_idx is valid (!= 0xFFF) */ 925 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx); 926 927 iwl_clear_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id)); 928 iwl_txq_ctx_deactivate(priv, txq_id); 929 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0); 930 931 return 0; 932} 933 934u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data) 935{ 936 u16 size = (u16)sizeof(struct iwl_addsta_cmd); 937 struct iwl_addsta_cmd *addsta = (struct iwl_addsta_cmd *)data; 938 memcpy(addsta, cmd, size); 939 /* resrved in 5000 */ 940 addsta->rate_n_flags = cpu_to_le16(0); 941 return size; 942} 943 944 945/* 946 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask 947 * must be called under priv->lock and mac access 948 */ 949void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask) 950{ 951 iwl_write_prph(priv, IWL50_SCD_TXFACT, mask); 952} 953 954 955static inline u32 iwl5000_get_scd_ssn(struct iwl5000_tx_resp *tx_resp) 956{ 957 return le32_to_cpup((__le32 *)&tx_resp->status + 958 tx_resp->frame_count) & MAX_SN; 959} 960 961static int iwl5000_tx_status_reply_tx(struct iwl_priv *priv, 962 struct iwl_ht_agg *agg, 963 struct iwl5000_tx_resp *tx_resp, 964 int txq_id, u16 start_idx) 965{ 966 u16 status; 967 struct agg_tx_status *frame_status = &tx_resp->status; 968 struct ieee80211_tx_info *info = NULL; 969 struct ieee80211_hdr *hdr = NULL; 970 u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags); 971 int i, sh, idx; 972 u16 seq; 973 974 if (agg->wait_for_ba) 975 IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n"); 976 977 agg->frame_count = tx_resp->frame_count; 978 agg->start_idx = start_idx; 979 agg->rate_n_flags = rate_n_flags; 980 agg->bitmap = 0; 981 982 /* # frames attempted by Tx command */ 983 if (agg->frame_count == 1) { 984 /* Only one frame was attempted; no block-ack will arrive */ 985 status = le16_to_cpu(frame_status[0].status); 986 idx = start_idx; 987 988 /* FIXME: code repetition */ 989 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n", 990 agg->frame_count, agg->start_idx, idx); 991 992 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]); 993 info->status.rates[0].count = tx_resp->failure_frame + 1; 994 info->flags &= ~IEEE80211_TX_CTL_AMPDU; 995 info->flags |= iwl_tx_status_to_mac80211(status); 996 iwl_hwrate_to_tx_control(priv, rate_n_flags, info); 997 998 /* FIXME: code repetition end */ 999 1000 IWL_DEBUG_TX_REPLY(priv, "1 Frame 0x%x failure :%d\n", 1001 status & 0xff, tx_resp->failure_frame); 1002 IWL_DEBUG_TX_REPLY(priv, "Rate Info rate_n_flags=%x\n", rate_n_flags); 1003 1004 agg->wait_for_ba = 0; 1005 } else { 1006 /* Two or more frames were attempted; expect block-ack */ 1007 u64 bitmap = 0; 1008 int start = agg->start_idx; 1009 1010 /* Construct bit-map of pending frames within Tx window */ 1011 for (i = 0; i < agg->frame_count; i++) { 1012 u16 sc; 1013 status = le16_to_cpu(frame_status[i].status); 1014 seq = le16_to_cpu(frame_status[i].sequence); 1015 idx = SEQ_TO_INDEX(seq); 1016 txq_id = SEQ_TO_QUEUE(seq); 1017 1018 if (status & (AGG_TX_STATE_FEW_BYTES_MSK | 1019 AGG_TX_STATE_ABORT_MSK)) 1020 continue; 1021 1022 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n", 1023 agg->frame_count, txq_id, idx); 1024 1025 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx); 1026 if (!hdr) { 1027 IWL_ERR(priv, 1028 "BUG_ON idx doesn't point to valid skb" 1029 " idx=%d, txq_id=%d\n", idx, txq_id); 1030 return -1; 1031 } 1032 1033 sc = le16_to_cpu(hdr->seq_ctrl); 1034 if (idx != (SEQ_TO_SN(sc) & 0xff)) { 1035 IWL_ERR(priv, 1036 "BUG_ON idx doesn't match seq control" 1037 " idx=%d, seq_idx=%d, seq=%d\n", 1038 idx, SEQ_TO_SN(sc), 1039 hdr->seq_ctrl); 1040 return -1; 1041 } 1042 1043 IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n", 1044 i, idx, SEQ_TO_SN(sc)); 1045 1046 sh = idx - start; 1047 if (sh > 64) { 1048 sh = (start - idx) + 0xff; 1049 bitmap = bitmap << sh; 1050 sh = 0; 1051 start = idx; 1052 } else if (sh < -64) 1053 sh = 0xff - (start - idx); 1054 else if (sh < 0) { 1055 sh = start - idx; 1056 start = idx; 1057 bitmap = bitmap << sh; 1058 sh = 0; 1059 } 1060 bitmap |= 1ULL << sh; 1061 IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n", 1062 start, (unsigned long long)bitmap); 1063 } 1064 1065 agg->bitmap = bitmap; 1066 agg->start_idx = start; 1067 IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n", 1068 agg->frame_count, agg->start_idx, 1069 (unsigned long long)agg->bitmap); 1070 1071 if (bitmap) 1072 agg->wait_for_ba = 1; 1073 } 1074 return 0; 1075} 1076 1077static void iwl5000_rx_reply_tx(struct iwl_priv *priv, 1078 struct iwl_rx_mem_buffer *rxb) 1079{ 1080 struct iwl_rx_packet *pkt = rxb_addr(rxb); 1081 u16 sequence = le16_to_cpu(pkt->hdr.sequence); 1082 int txq_id = SEQ_TO_QUEUE(sequence); 1083 int index = SEQ_TO_INDEX(sequence); 1084 struct iwl_tx_queue *txq = &priv->txq[txq_id]; 1085 struct ieee80211_tx_info *info; 1086 struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0]; 1087 u32 status = le16_to_cpu(tx_resp->status.status); 1088 int tid; 1089 int sta_id; 1090 int freed; 1091 1092 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) { 1093 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d " 1094 "is out of range [0-%d] %d %d\n", txq_id, 1095 index, txq->q.n_bd, txq->q.write_ptr, 1096 txq->q.read_ptr); 1097 return; 1098 } 1099 1100 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]); 1101 memset(&info->status, 0, sizeof(info->status)); 1102 1103 tid = (tx_resp->ra_tid & IWL50_TX_RES_TID_MSK) >> IWL50_TX_RES_TID_POS; 1104 sta_id = (tx_resp->ra_tid & IWL50_TX_RES_RA_MSK) >> IWL50_TX_RES_RA_POS; 1105 1106 if (txq->sched_retry) { 1107 const u32 scd_ssn = iwl5000_get_scd_ssn(tx_resp); 1108 struct iwl_ht_agg *agg = NULL; 1109 1110 agg = &priv->stations[sta_id].tid[tid].agg; 1111 1112 iwl5000_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index); 1113 1114 /* check if BAR is needed */ 1115 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status)) 1116 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK; 1117 1118 if (txq->q.read_ptr != (scd_ssn & 0xff)) { 1119 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd); 1120 IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim " 1121 "scd_ssn=%d idx=%d txq=%d swq=%d\n", 1122 scd_ssn , index, txq_id, txq->swq_id); 1123 1124 freed = iwl_tx_queue_reclaim(priv, txq_id, index); 1125 iwl_free_tfds_in_queue(priv, sta_id, tid, freed); 1126 1127 if (priv->mac80211_registered && 1128 (iwl_queue_space(&txq->q) > txq->q.low_mark) && 1129 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) { 1130 if (agg->state == IWL_AGG_OFF) 1131 iwl_wake_queue(priv, txq_id); 1132 else 1133 iwl_wake_queue(priv, txq->swq_id); 1134 } 1135 } 1136 } else { 1137 BUG_ON(txq_id != txq->swq_id); 1138 1139 info->status.rates[0].count = tx_resp->failure_frame + 1; 1140 info->flags |= iwl_tx_status_to_mac80211(status); 1141 iwl_hwrate_to_tx_control(priv, 1142 le32_to_cpu(tx_resp->rate_n_flags), 1143 info); 1144 1145 IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) rate_n_flags " 1146 "0x%x retries %d\n", 1147 txq_id, 1148 iwl_get_tx_fail_reason(status), status, 1149 le32_to_cpu(tx_resp->rate_n_flags), 1150 tx_resp->failure_frame); 1151 1152 freed = iwl_tx_queue_reclaim(priv, txq_id, index); 1153 iwl_free_tfds_in_queue(priv, sta_id, tid, freed); 1154 1155 if (priv->mac80211_registered && 1156 (iwl_queue_space(&txq->q) > txq->q.low_mark)) 1157 iwl_wake_queue(priv, txq_id); 1158 } 1159 1160 iwl_txq_check_empty(priv, sta_id, tid, txq_id); 1161 1162 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK)) 1163 IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n"); 1164} 1165 1166/* Currently 5000 is the superset of everything */ 1167u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len) 1168{ 1169 return len; 1170} 1171 1172void iwl5000_setup_deferred_work(struct iwl_priv *priv) 1173{ 1174 /* in 5000 the tx power calibration is done in uCode */ 1175 priv->disable_tx_power_cal = 1; 1176} 1177 1178void iwl5000_rx_handler_setup(struct iwl_priv *priv) 1179{ 1180 /* init calibration handlers */ 1181 priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] = 1182 iwl5000_rx_calib_result; 1183 priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] = 1184 iwl5000_rx_calib_complete; 1185 priv->rx_handlers[REPLY_TX] = iwl5000_rx_reply_tx; 1186} 1187 1188 1189int iwl5000_hw_valid_rtc_data_addr(u32 addr) 1190{ 1191 return (addr >= IWL50_RTC_DATA_LOWER_BOUND) && 1192 (addr < IWL50_RTC_DATA_UPPER_BOUND); 1193} 1194 1195static int iwl5000_send_rxon_assoc(struct iwl_priv *priv) 1196{ 1197 int ret = 0; 1198 struct iwl5000_rxon_assoc_cmd rxon_assoc; 1199 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon; 1200 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon; 1201 1202 if ((rxon1->flags == rxon2->flags) && 1203 (rxon1->filter_flags == rxon2->filter_flags) && 1204 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) && 1205 (rxon1->ofdm_ht_single_stream_basic_rates == 1206 rxon2->ofdm_ht_single_stream_basic_rates) && 1207 (rxon1->ofdm_ht_dual_stream_basic_rates == 1208 rxon2->ofdm_ht_dual_stream_basic_rates) && 1209 (rxon1->ofdm_ht_triple_stream_basic_rates == 1210 rxon2->ofdm_ht_triple_stream_basic_rates) && 1211 (rxon1->acquisition_data == rxon2->acquisition_data) && 1212 (rxon1->rx_chain == rxon2->rx_chain) && 1213 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) { 1214 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC. Not resending.\n"); 1215 return 0; 1216 } 1217 1218 rxon_assoc.flags = priv->staging_rxon.flags; 1219 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags; 1220 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates; 1221 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates; 1222 rxon_assoc.reserved1 = 0; 1223 rxon_assoc.reserved2 = 0; 1224 rxon_assoc.reserved3 = 0; 1225 rxon_assoc.ofdm_ht_single_stream_basic_rates = 1226 priv->staging_rxon.ofdm_ht_single_stream_basic_rates; 1227 rxon_assoc.ofdm_ht_dual_stream_basic_rates = 1228 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates; 1229 rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain; 1230 rxon_assoc.ofdm_ht_triple_stream_basic_rates = 1231 priv->staging_rxon.ofdm_ht_triple_stream_basic_rates; 1232 rxon_assoc.acquisition_data = priv->staging_rxon.acquisition_data; 1233 1234 ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC, 1235 sizeof(rxon_assoc), &rxon_assoc, NULL); 1236 if (ret) 1237 return ret; 1238 1239 return ret; 1240} 1241int iwl5000_send_tx_power(struct iwl_priv *priv) 1242{ 1243 struct iwl5000_tx_power_dbm_cmd tx_power_cmd; 1244 u8 tx_ant_cfg_cmd; 1245 1246 /* half dBm need to multiply */ 1247 tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt); 1248 1249 if (priv->tx_power_lmt_in_half_dbm && 1250 priv->tx_power_lmt_in_half_dbm < tx_power_cmd.global_lmt) { 1251 /* 1252 * For the newer devices which using enhanced/extend tx power 1253 * table in EEPROM, the format is in half dBm. driver need to 1254 * convert to dBm format before report to mac80211. 1255 * By doing so, there is a possibility of 1/2 dBm resolution 1256 * lost. driver will perform "round-up" operation before 1257 * reporting, but it will cause 1/2 dBm tx power over the 1258 * regulatory limit. Perform the checking here, if the 1259 * "tx_power_user_lmt" is higher than EEPROM value (in 1260 * half-dBm format), lower the tx power based on EEPROM 1261 */ 1262 tx_power_cmd.global_lmt = priv->tx_power_lmt_in_half_dbm; 1263 } 1264 tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED; 1265 tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO; 1266 1267 if (IWL_UCODE_API(priv->ucode_ver) == 1) 1268 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD_V1; 1269 else 1270 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD; 1271 1272 return iwl_send_cmd_pdu_async(priv, tx_ant_cfg_cmd, 1273 sizeof(tx_power_cmd), &tx_power_cmd, 1274 NULL); 1275} 1276 1277void iwl5000_temperature(struct iwl_priv *priv) 1278{ 1279 /* store temperature from statistics (in Celsius) */ 1280 priv->temperature = le32_to_cpu(priv->statistics.general.temperature); 1281 iwl_tt_handler(priv); 1282} 1283 1284static void iwl5150_temperature(struct iwl_priv *priv) 1285{ 1286 u32 vt = 0; 1287 s32 offset = iwl_temp_calib_to_offset(priv); 1288 1289 vt = le32_to_cpu(priv->statistics.general.temperature); 1290 vt = vt / IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF + offset; 1291 /* now vt hold the temperature in Kelvin */ 1292 priv->temperature = KELVIN_TO_CELSIUS(vt); 1293 iwl_tt_handler(priv); 1294} 1295 1296/* Calc max signal level (dBm) among 3 possible receivers */ 1297int iwl5000_calc_rssi(struct iwl_priv *priv, 1298 struct iwl_rx_phy_res *rx_resp) 1299{ 1300 /* data from PHY/DSP regarding signal strength, etc., 1301 * contents are always there, not configurable by host 1302 */ 1303 struct iwl5000_non_cfg_phy *ncphy = 1304 (struct iwl5000_non_cfg_phy *)rx_resp->non_cfg_phy_buf; 1305 u32 val, rssi_a, rssi_b, rssi_c, max_rssi; 1306 u8 agc; 1307 1308 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_AGC_IDX]); 1309 agc = (val & IWL50_OFDM_AGC_MSK) >> IWL50_OFDM_AGC_BIT_POS; 1310 1311 /* Find max rssi among 3 possible receivers. 1312 * These values are measured by the digital signal processor (DSP). 1313 * They should stay fairly constant even as the signal strength varies, 1314 * if the radio's automatic gain control (AGC) is working right. 1315 * AGC value (see below) will provide the "interesting" info. 1316 */ 1317 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_AB_IDX]); 1318 rssi_a = (val & IWL50_OFDM_RSSI_A_MSK) >> IWL50_OFDM_RSSI_A_BIT_POS; 1319 rssi_b = (val & IWL50_OFDM_RSSI_B_MSK) >> IWL50_OFDM_RSSI_B_BIT_POS; 1320 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_C_IDX]); 1321 rssi_c = (val & IWL50_OFDM_RSSI_C_MSK) >> IWL50_OFDM_RSSI_C_BIT_POS; 1322 1323 max_rssi = max_t(u32, rssi_a, rssi_b); 1324 max_rssi = max_t(u32, max_rssi, rssi_c); 1325 1326 IWL_DEBUG_STATS(priv, "Rssi In A %d B %d C %d Max %d AGC dB %d\n", 1327 rssi_a, rssi_b, rssi_c, max_rssi, agc); 1328 1329 /* dBm = max_rssi dB - agc dB - constant. 1330 * Higher AGC (higher radio gain) means lower signal. */ 1331 return max_rssi - agc - IWL49_RSSI_OFFSET; 1332} 1333 1334static int iwl5000_send_tx_ant_config(struct iwl_priv *priv, u8 valid_tx_ant) 1335{ 1336 struct iwl_tx_ant_config_cmd tx_ant_cmd = { 1337 .valid = cpu_to_le32(valid_tx_ant), 1338 }; 1339 1340 if (IWL_UCODE_API(priv->ucode_ver) > 1) { 1341 IWL_DEBUG_HC(priv, "select valid tx ant: %u\n", valid_tx_ant); 1342 return iwl_send_cmd_pdu(priv, TX_ANT_CONFIGURATION_CMD, 1343 sizeof(struct iwl_tx_ant_config_cmd), 1344 &tx_ant_cmd); 1345 } else { 1346 IWL_DEBUG_HC(priv, "TX_ANT_CONFIGURATION_CMD not supported\n"); 1347 return -EOPNOTSUPP; 1348 } 1349} 1350 1351 1352#define IWL5000_UCODE_GET(item) \ 1353static u32 iwl5000_ucode_get_##item(const struct iwl_ucode_header *ucode,\ 1354 u32 api_ver) \ 1355{ \ 1356 if (api_ver <= 2) \ 1357 return le32_to_cpu(ucode->u.v1.item); \ 1358 return le32_to_cpu(ucode->u.v2.item); \ 1359} 1360 1361static u32 iwl5000_ucode_get_header_size(u32 api_ver) 1362{ 1363 if (api_ver <= 2) 1364 return UCODE_HEADER_SIZE(1); 1365 return UCODE_HEADER_SIZE(2); 1366} 1367 1368static u32 iwl5000_ucode_get_build(const struct iwl_ucode_header *ucode, 1369 u32 api_ver) 1370{ 1371 if (api_ver <= 2) 1372 return 0; 1373 return le32_to_cpu(ucode->u.v2.build); 1374} 1375 1376static u8 *iwl5000_ucode_get_data(const struct iwl_ucode_header *ucode, 1377 u32 api_ver) 1378{ 1379 if (api_ver <= 2) 1380 return (u8 *) ucode->u.v1.data; 1381 return (u8 *) ucode->u.v2.data; 1382} 1383 1384IWL5000_UCODE_GET(inst_size); 1385IWL5000_UCODE_GET(data_size); 1386IWL5000_UCODE_GET(init_size); 1387IWL5000_UCODE_GET(init_data_size); 1388IWL5000_UCODE_GET(boot_size); 1389 1390static int iwl5000_hw_channel_switch(struct iwl_priv *priv, u16 channel) 1391{ 1392 struct iwl5000_channel_switch_cmd cmd; 1393 const struct iwl_channel_info *ch_info; 1394 struct iwl_host_cmd hcmd = { 1395 .id = REPLY_CHANNEL_SWITCH, 1396 .len = sizeof(cmd), 1397 .flags = CMD_SIZE_HUGE, 1398 .data = &cmd, 1399 }; 1400 1401 IWL_DEBUG_11H(priv, "channel switch from %d to %d\n", 1402 priv->active_rxon.channel, channel); 1403 cmd.band = priv->band == IEEE80211_BAND_2GHZ; 1404 cmd.channel = cpu_to_le16(channel); 1405 cmd.rxon_flags = priv->staging_rxon.flags; 1406 cmd.rxon_filter_flags = priv->staging_rxon.filter_flags; 1407 cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time); 1408 ch_info = iwl_get_channel_info(priv, priv->band, channel); 1409 if (ch_info) 1410 cmd.expect_beacon = is_channel_radar(ch_info); 1411 else { 1412 IWL_ERR(priv, "invalid channel switch from %u to %u\n", 1413 priv->active_rxon.channel, channel); 1414 return -EFAULT; 1415 } 1416 priv->switch_rxon.channel = cpu_to_le16(channel); 1417 priv->switch_rxon.switch_in_progress = true; 1418 1419 return iwl_send_cmd_sync(priv, &hcmd); 1420} 1421 1422struct iwl_hcmd_ops iwl5000_hcmd = { 1423 .rxon_assoc = iwl5000_send_rxon_assoc, 1424 .commit_rxon = iwl_commit_rxon, 1425 .set_rxon_chain = iwl_set_rxon_chain, 1426 .set_tx_ant = iwl5000_send_tx_ant_config, 1427}; 1428 1429struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = { 1430 .get_hcmd_size = iwl5000_get_hcmd_size, 1431 .build_addsta_hcmd = iwl5000_build_addsta_hcmd, 1432 .gain_computation = iwl5000_gain_computation, 1433 .chain_noise_reset = iwl5000_chain_noise_reset, 1434 .rts_tx_cmd_flag = iwl5000_rts_tx_cmd_flag, 1435 .calc_rssi = iwl5000_calc_rssi, 1436}; 1437 1438struct iwl_ucode_ops iwl5000_ucode = { 1439 .get_header_size = iwl5000_ucode_get_header_size, 1440 .get_build = iwl5000_ucode_get_build, 1441 .get_inst_size = iwl5000_ucode_get_inst_size, 1442 .get_data_size = iwl5000_ucode_get_data_size, 1443 .get_init_size = iwl5000_ucode_get_init_size, 1444 .get_init_data_size = iwl5000_ucode_get_init_data_size, 1445 .get_boot_size = iwl5000_ucode_get_boot_size, 1446 .get_data = iwl5000_ucode_get_data, 1447}; 1448 1449struct iwl_lib_ops iwl5000_lib = { 1450 .set_hw_params = iwl5000_hw_set_hw_params, 1451 .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl, 1452 .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl, 1453 .txq_set_sched = iwl5000_txq_set_sched, 1454 .txq_agg_enable = iwl5000_txq_agg_enable, 1455 .txq_agg_disable = iwl5000_txq_agg_disable, 1456 .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd, 1457 .txq_free_tfd = iwl_hw_txq_free_tfd, 1458 .txq_init = iwl_hw_tx_queue_init, 1459 .rx_handler_setup = iwl5000_rx_handler_setup, 1460 .setup_deferred_work = iwl5000_setup_deferred_work, 1461 .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr, 1462 .dump_nic_event_log = iwl_dump_nic_event_log, 1463 .dump_nic_error_log = iwl_dump_nic_error_log, 1464 .dump_csr = iwl_dump_csr, 1465 .dump_fh = iwl_dump_fh, 1466 .load_ucode = iwl5000_load_ucode, 1467 .init_alive_start = iwl5000_init_alive_start, 1468 .alive_notify = iwl5000_alive_notify, 1469 .send_tx_power = iwl5000_send_tx_power, 1470 .update_chain_flags = iwl_update_chain_flags, 1471 .set_channel_switch = iwl5000_hw_channel_switch, 1472 .apm_ops = { 1473 .init = iwl_apm_init, 1474 .stop = iwl_apm_stop, 1475 .config = iwl5000_nic_config, 1476 .set_pwr_src = iwl_set_pwr_src, 1477 }, 1478 .eeprom_ops = { 1479 .regulatory_bands = { 1480 EEPROM_5000_REG_BAND_1_CHANNELS, 1481 EEPROM_5000_REG_BAND_2_CHANNELS, 1482 EEPROM_5000_REG_BAND_3_CHANNELS, 1483 EEPROM_5000_REG_BAND_4_CHANNELS, 1484 EEPROM_5000_REG_BAND_5_CHANNELS, 1485 EEPROM_5000_REG_BAND_24_HT40_CHANNELS, 1486 EEPROM_5000_REG_BAND_52_HT40_CHANNELS 1487 }, 1488 .verify_signature = iwlcore_eeprom_verify_signature, 1489 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore, 1490 .release_semaphore = iwlcore_eeprom_release_semaphore, 1491 .calib_version = iwl5000_eeprom_calib_version, 1492 .query_addr = iwl5000_eeprom_query_addr, 1493 }, 1494 .post_associate = iwl_post_associate, 1495 .isr = iwl_isr_ict, 1496 .config_ap = iwl_config_ap, 1497 .temp_ops = { 1498 .temperature = iwl5000_temperature, 1499 .set_ct_kill = iwl5000_set_ct_threshold, 1500 }, 1501 .add_bcast_station = iwl_add_bcast_station, 1502 .recover_from_tx_stall = iwl_bg_monitor_recover, 1503}; 1504 1505static struct iwl_lib_ops iwl5150_lib = { 1506 .set_hw_params = iwl5000_hw_set_hw_params, 1507 .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl, 1508 .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl, 1509 .txq_set_sched = iwl5000_txq_set_sched, 1510 .txq_agg_enable = iwl5000_txq_agg_enable, 1511 .txq_agg_disable = iwl5000_txq_agg_disable, 1512 .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd, 1513 .txq_free_tfd = iwl_hw_txq_free_tfd, 1514 .txq_init = iwl_hw_tx_queue_init, 1515 .rx_handler_setup = iwl5000_rx_handler_setup, 1516 .setup_deferred_work = iwl5000_setup_deferred_work, 1517 .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr, 1518 .dump_nic_event_log = iwl_dump_nic_event_log, 1519 .dump_nic_error_log = iwl_dump_nic_error_log, 1520 .dump_csr = iwl_dump_csr, 1521 .load_ucode = iwl5000_load_ucode, 1522 .init_alive_start = iwl5000_init_alive_start, 1523 .alive_notify = iwl5000_alive_notify, 1524 .send_tx_power = iwl5000_send_tx_power, 1525 .update_chain_flags = iwl_update_chain_flags, 1526 .set_channel_switch = iwl5000_hw_channel_switch, 1527 .apm_ops = { 1528 .init = iwl_apm_init, 1529 .stop = iwl_apm_stop, 1530 .config = iwl5000_nic_config, 1531 .set_pwr_src = iwl_set_pwr_src, 1532 }, 1533 .eeprom_ops = { 1534 .regulatory_bands = { 1535 EEPROM_5000_REG_BAND_1_CHANNELS, 1536 EEPROM_5000_REG_BAND_2_CHANNELS, 1537 EEPROM_5000_REG_BAND_3_CHANNELS, 1538 EEPROM_5000_REG_BAND_4_CHANNELS, 1539 EEPROM_5000_REG_BAND_5_CHANNELS, 1540 EEPROM_5000_REG_BAND_24_HT40_CHANNELS, 1541 EEPROM_5000_REG_BAND_52_HT40_CHANNELS 1542 }, 1543 .verify_signature = iwlcore_eeprom_verify_signature, 1544 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore, 1545 .release_semaphore = iwlcore_eeprom_release_semaphore, 1546 .calib_version = iwl5000_eeprom_calib_version, 1547 .query_addr = iwl5000_eeprom_query_addr, 1548 }, 1549 .post_associate = iwl_post_associate, 1550 .isr = iwl_isr_ict, 1551 .config_ap = iwl_config_ap, 1552 .temp_ops = { 1553 .temperature = iwl5150_temperature, 1554 .set_ct_kill = iwl5150_set_ct_threshold, 1555 }, 1556 .add_bcast_station = iwl_add_bcast_station, 1557 .recover_from_tx_stall = iwl_bg_monitor_recover, 1558}; 1559 1560static const struct iwl_ops iwl5000_ops = { 1561 .ucode = &iwl5000_ucode, 1562 .lib = &iwl5000_lib, 1563 .hcmd = &iwl5000_hcmd, 1564 .utils = &iwl5000_hcmd_utils, 1565 .led = &iwlagn_led_ops, 1566}; 1567 1568static const struct iwl_ops iwl5150_ops = { 1569 .ucode = &iwl5000_ucode, 1570 .lib = &iwl5150_lib, 1571 .hcmd = &iwl5000_hcmd, 1572 .utils = &iwl5000_hcmd_utils, 1573 .led = &iwlagn_led_ops, 1574}; 1575 1576struct iwl_mod_params iwl50_mod_params = { 1577 .amsdu_size_8K = 1, 1578 .restart_fw = 1, 1579 /* the rest are 0 by default */ 1580}; 1581 1582 1583struct iwl_cfg iwl5300_agn_cfg = { 1584 .name = "Intel(R) Ultimate N WiFi Link 5300 AGN", 1585 .fw_name_pre = IWL5000_FW_PRE, 1586 .ucode_api_max = IWL5000_UCODE_API_MAX, 1587 .ucode_api_min = IWL5000_UCODE_API_MIN, 1588 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N, 1589 .ops = &iwl5000_ops, 1590 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, 1591 .eeprom_ver = EEPROM_5000_EEPROM_VERSION, 1592 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION, 1593 .num_of_queues = IWL50_NUM_QUEUES, 1594 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES, 1595 .mod_params = &iwl50_mod_params, 1596 .valid_tx_ant = ANT_ABC, 1597 .valid_rx_ant = ANT_ABC, 1598 .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL, 1599 .set_l0s = true, 1600 .use_bsm = false, 1601 .ht_greenfield_support = true, 1602 .led_compensation = 51, 1603 .use_rts_for_ht = true, /* use rts/cts protection */ 1604 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS, 1605 .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF, 1606 .chain_noise_scale = 1000, 1607 .monitor_recover_period = IWL_MONITORING_PERIOD, 1608}; 1609 1610struct iwl_cfg iwl5100_bgn_cfg = { 1611 .name = "Intel(R) WiFi Link 5100 BGN", 1612 .fw_name_pre = IWL5000_FW_PRE, 1613 .ucode_api_max = IWL5000_UCODE_API_MAX, 1614 .ucode_api_min = IWL5000_UCODE_API_MIN, 1615 .sku = IWL_SKU_G|IWL_SKU_N, 1616 .ops = &iwl5000_ops, 1617 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, 1618 .eeprom_ver = EEPROM_5000_EEPROM_VERSION, 1619 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION, 1620 .num_of_queues = IWL50_NUM_QUEUES, 1621 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES, 1622 .mod_params = &iwl50_mod_params, 1623 .valid_tx_ant = ANT_B, 1624 .valid_rx_ant = ANT_AB, 1625 .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL, 1626 .set_l0s = true, 1627 .use_bsm = false, 1628 .ht_greenfield_support = true, 1629 .led_compensation = 51, 1630 .use_rts_for_ht = true, /* use rts/cts protection */ 1631 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS, 1632 .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF, 1633 .chain_noise_scale = 1000, 1634 .monitor_recover_period = IWL_MONITORING_PERIOD, 1635}; 1636 1637struct iwl_cfg iwl5100_abg_cfg = { 1638 .name = "Intel(R) WiFi Link 5100 ABG", 1639 .fw_name_pre = IWL5000_FW_PRE, 1640 .ucode_api_max = IWL5000_UCODE_API_MAX, 1641 .ucode_api_min = IWL5000_UCODE_API_MIN, 1642 .sku = IWL_SKU_A|IWL_SKU_G, 1643 .ops = &iwl5000_ops, 1644 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, 1645 .eeprom_ver = EEPROM_5000_EEPROM_VERSION, 1646 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION, 1647 .num_of_queues = IWL50_NUM_QUEUES, 1648 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES, 1649 .mod_params = &iwl50_mod_params, 1650 .valid_tx_ant = ANT_B, 1651 .valid_rx_ant = ANT_AB, 1652 .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL, 1653 .set_l0s = true, 1654 .use_bsm = false, 1655 .led_compensation = 51, 1656 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS, 1657 .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF, 1658 .chain_noise_scale = 1000, 1659 .monitor_recover_period = IWL_MONITORING_PERIOD, 1660}; 1661 1662struct iwl_cfg iwl5100_agn_cfg = { 1663 .name = "Intel(R) WiFi Link 5100 AGN", 1664 .fw_name_pre = IWL5000_FW_PRE, 1665 .ucode_api_max = IWL5000_UCODE_API_MAX, 1666 .ucode_api_min = IWL5000_UCODE_API_MIN, 1667 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N, 1668 .ops = &iwl5000_ops, 1669 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, 1670 .eeprom_ver = EEPROM_5000_EEPROM_VERSION, 1671 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION, 1672 .num_of_queues = IWL50_NUM_QUEUES, 1673 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES, 1674 .mod_params = &iwl50_mod_params, 1675 .valid_tx_ant = ANT_B, 1676 .valid_rx_ant = ANT_AB, 1677 .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL, 1678 .set_l0s = true, 1679 .use_bsm = false, 1680 .ht_greenfield_support = true, 1681 .led_compensation = 51, 1682 .use_rts_for_ht = true, /* use rts/cts protection */ 1683 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS, 1684 .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF, 1685 .chain_noise_scale = 1000, 1686 .monitor_recover_period = IWL_MONITORING_PERIOD, 1687}; 1688 1689struct iwl_cfg iwl5350_agn_cfg = { 1690 .name = "Intel(R) WiMAX/WiFi Link 5350 AGN", 1691 .fw_name_pre = IWL5000_FW_PRE, 1692 .ucode_api_max = IWL5000_UCODE_API_MAX, 1693 .ucode_api_min = IWL5000_UCODE_API_MIN, 1694 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N, 1695 .ops = &iwl5000_ops, 1696 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, 1697 .eeprom_ver = EEPROM_5050_EEPROM_VERSION, 1698 .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION, 1699 .num_of_queues = IWL50_NUM_QUEUES, 1700 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES, 1701 .mod_params = &iwl50_mod_params, 1702 .valid_tx_ant = ANT_ABC, 1703 .valid_rx_ant = ANT_ABC, 1704 .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL, 1705 .set_l0s = true, 1706 .use_bsm = false, 1707 .ht_greenfield_support = true, 1708 .led_compensation = 51, 1709 .use_rts_for_ht = true, /* use rts/cts protection */ 1710 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS, 1711 .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF, 1712 .chain_noise_scale = 1000, 1713 .monitor_recover_period = IWL_MONITORING_PERIOD, 1714}; 1715 1716struct iwl_cfg iwl5150_agn_cfg = { 1717 .name = "Intel(R) WiMAX/WiFi Link 5150 AGN", 1718 .fw_name_pre = IWL5150_FW_PRE, 1719 .ucode_api_max = IWL5150_UCODE_API_MAX, 1720 .ucode_api_min = IWL5150_UCODE_API_MIN, 1721 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N, 1722 .ops = &iwl5150_ops, 1723 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, 1724 .eeprom_ver = EEPROM_5050_EEPROM_VERSION, 1725 .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION, 1726 .num_of_queues = IWL50_NUM_QUEUES, 1727 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES, 1728 .mod_params = &iwl50_mod_params, 1729 .valid_tx_ant = ANT_A, 1730 .valid_rx_ant = ANT_AB, 1731 .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL, 1732 .set_l0s = true, 1733 .use_bsm = false, 1734 .ht_greenfield_support = true, 1735 .led_compensation = 51, 1736 .use_rts_for_ht = true, /* use rts/cts protection */ 1737 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS, 1738 .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF, 1739 .chain_noise_scale = 1000, 1740 .monitor_recover_period = IWL_MONITORING_PERIOD, 1741}; 1742 1743struct iwl_cfg iwl5150_abg_cfg = { 1744 .name = "Intel(R) WiMAX/WiFi Link 5150 ABG", 1745 .fw_name_pre = IWL5150_FW_PRE, 1746 .ucode_api_max = IWL5150_UCODE_API_MAX, 1747 .ucode_api_min = IWL5150_UCODE_API_MIN, 1748 .sku = IWL_SKU_A|IWL_SKU_G, 1749 .ops = &iwl5150_ops, 1750 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, 1751 .eeprom_ver = EEPROM_5050_EEPROM_VERSION, 1752 .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION, 1753 .num_of_queues = IWL50_NUM_QUEUES, 1754 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES, 1755 .mod_params = &iwl50_mod_params, 1756 .valid_tx_ant = ANT_A, 1757 .valid_rx_ant = ANT_AB, 1758 .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL, 1759 .set_l0s = true, 1760 .use_bsm = false, 1761 .led_compensation = 51, 1762 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS, 1763 .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF, 1764 .chain_noise_scale = 1000, 1765 .monitor_recover_period = IWL_MONITORING_PERIOD, 1766}; 1767 1768MODULE_FIRMWARE(IWL5000_MODULE_FIRMWARE(IWL5000_UCODE_API_MAX)); 1769MODULE_FIRMWARE(IWL5150_MODULE_FIRMWARE(IWL5150_UCODE_API_MAX)); 1770 1771module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, S_IRUGO); 1772MODULE_PARM_DESC(swcrypto50, 1773 "using software crypto engine (default 0 [hardware])\n"); 1774module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, S_IRUGO); 1775MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series"); 1776module_param_named(11n_disable50, iwl50_mod_params.disable_11n, int, S_IRUGO); 1777MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality"); 1778module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K, 1779 int, S_IRUGO); 1780MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series"); 1781module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, S_IRUGO); 1782MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error"); 1783