iwl-5000.c revision c3056065400aeb437390e1a86b85f9c32fb1c1df
1/****************************************************************************** 2 * 3 * Copyright(c) 2007-2008 Intel Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * The full GNU General Public License is included in this distribution in the 19 * file called LICENSE. 20 * 21 * Contact Information: 22 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 23 * 24 *****************************************************************************/ 25 26#include <linux/kernel.h> 27#include <linux/module.h> 28#include <linux/init.h> 29#include <linux/pci.h> 30#include <linux/dma-mapping.h> 31#include <linux/delay.h> 32#include <linux/skbuff.h> 33#include <linux/netdevice.h> 34#include <linux/wireless.h> 35#include <net/mac80211.h> 36#include <linux/etherdevice.h> 37#include <asm/unaligned.h> 38 39#include "iwl-eeprom.h" 40#include "iwl-dev.h" 41#include "iwl-core.h" 42#include "iwl-io.h" 43#include "iwl-sta.h" 44#include "iwl-helpers.h" 45#include "iwl-5000-hw.h" 46 47#define IWL5000_UCODE_API "-1" 48 49#define IWL5000_MODULE_FIRMWARE "iwlwifi-5000" IWL5000_UCODE_API ".ucode" 50 51static const u16 iwl5000_default_queue_to_tx_fifo[] = { 52 IWL_TX_FIFO_AC3, 53 IWL_TX_FIFO_AC2, 54 IWL_TX_FIFO_AC1, 55 IWL_TX_FIFO_AC0, 56 IWL50_CMD_FIFO_NUM, 57 IWL_TX_FIFO_HCCA_1, 58 IWL_TX_FIFO_HCCA_2 59}; 60 61/* FIXME: same implementation as 4965 */ 62static int iwl5000_apm_stop_master(struct iwl_priv *priv) 63{ 64 int ret = 0; 65 unsigned long flags; 66 67 spin_lock_irqsave(&priv->lock, flags); 68 69 /* set stop master bit */ 70 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); 71 72 ret = iwl_poll_bit(priv, CSR_RESET, 73 CSR_RESET_REG_FLAG_MASTER_DISABLED, 74 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); 75 if (ret < 0) 76 goto out; 77 78out: 79 spin_unlock_irqrestore(&priv->lock, flags); 80 IWL_DEBUG_INFO("stop master\n"); 81 82 return ret; 83} 84 85 86static int iwl5000_apm_init(struct iwl_priv *priv) 87{ 88 int ret = 0; 89 90 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS, 91 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 92 93 /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */ 94 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS, 95 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 96 97 /* Set FH wait threshold to maximum (HW error during stress W/A) */ 98 iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); 99 100 /* enable HAP INTA to move device L1a -> L0s */ 101 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, 102 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); 103 104 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); 105 106 /* set "initialization complete" bit to move adapter 107 * D0U* --> D0A* state */ 108 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 109 110 /* wait for clock stabilization */ 111 ret = iwl_poll_bit(priv, CSR_GP_CNTRL, 112 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 113 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); 114 if (ret < 0) { 115 IWL_DEBUG_INFO("Failed to init the card\n"); 116 return ret; 117 } 118 119 ret = iwl_grab_nic_access(priv); 120 if (ret) 121 return ret; 122 123 /* enable DMA */ 124 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT); 125 126 udelay(20); 127 128 /* disable L1-Active */ 129 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG, 130 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 131 132 iwl_release_nic_access(priv); 133 134 return ret; 135} 136 137/* FIXME: this is identical to 4965 */ 138static void iwl5000_apm_stop(struct iwl_priv *priv) 139{ 140 unsigned long flags; 141 142 iwl5000_apm_stop_master(priv); 143 144 spin_lock_irqsave(&priv->lock, flags); 145 146 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 147 148 udelay(10); 149 150 /* clear "init complete" move adapter D0A* --> D0U state */ 151 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 152 153 spin_unlock_irqrestore(&priv->lock, flags); 154} 155 156 157static int iwl5000_apm_reset(struct iwl_priv *priv) 158{ 159 int ret = 0; 160 unsigned long flags; 161 162 iwl5000_apm_stop_master(priv); 163 164 spin_lock_irqsave(&priv->lock, flags); 165 166 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 167 168 udelay(10); 169 170 171 /* FIXME: put here L1A -L0S w/a */ 172 173 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); 174 175 /* set "initialization complete" bit to move adapter 176 * D0U* --> D0A* state */ 177 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 178 179 /* wait for clock stabilization */ 180 ret = iwl_poll_bit(priv, CSR_GP_CNTRL, 181 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 182 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); 183 if (ret < 0) { 184 IWL_DEBUG_INFO("Failed to init the card\n"); 185 goto out; 186 } 187 188 ret = iwl_grab_nic_access(priv); 189 if (ret) 190 goto out; 191 192 /* enable DMA */ 193 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT); 194 195 udelay(20); 196 197 /* disable L1-Active */ 198 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG, 199 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 200 201 iwl_release_nic_access(priv); 202 203out: 204 spin_unlock_irqrestore(&priv->lock, flags); 205 206 return ret; 207} 208 209 210static void iwl5000_nic_config(struct iwl_priv *priv) 211{ 212 unsigned long flags; 213 u16 radio_cfg; 214 u16 link; 215 216 spin_lock_irqsave(&priv->lock, flags); 217 218 pci_read_config_word(priv->pci_dev, PCI_CFG_LINK_CTRL, &link); 219 220 /* L1 is enabled by BIOS */ 221 if ((link & PCI_CFG_LINK_CTRL_VAL_L1_EN) == PCI_CFG_LINK_CTRL_VAL_L1_EN) 222 /* disable L0S disabled L1A enabled */ 223 iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); 224 else 225 /* L0S enabled L1A disabled */ 226 iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); 227 228 radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG); 229 230 /* write radio config values to register */ 231 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_5000_RF_CFG_TYPE_MAX) 232 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, 233 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) | 234 EEPROM_RF_CFG_STEP_MSK(radio_cfg) | 235 EEPROM_RF_CFG_DASH_MSK(radio_cfg)); 236 237 /* set CSR_HW_CONFIG_REG for uCode use */ 238 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, 239 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI | 240 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI); 241 242 /* W/A : NIC is stuck in a reset state after Early PCIe power off 243 * (PCIe power is lost before PERST# is asserted), 244 * causing ME FW to lose ownership and not being able to obtain it back. 245 */ 246 iwl_grab_nic_access(priv); 247 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, 248 APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS, 249 ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS); 250 iwl_release_nic_access(priv); 251 252 spin_unlock_irqrestore(&priv->lock, flags); 253} 254 255 256 257/* 258 * EEPROM 259 */ 260static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address) 261{ 262 u16 offset = 0; 263 264 if ((address & INDIRECT_ADDRESS) == 0) 265 return address; 266 267 switch (address & INDIRECT_TYPE_MSK) { 268 case INDIRECT_HOST: 269 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST); 270 break; 271 case INDIRECT_GENERAL: 272 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL); 273 break; 274 case INDIRECT_REGULATORY: 275 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY); 276 break; 277 case INDIRECT_CALIBRATION: 278 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION); 279 break; 280 case INDIRECT_PROCESS_ADJST: 281 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST); 282 break; 283 case INDIRECT_OTHERS: 284 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS); 285 break; 286 default: 287 IWL_ERROR("illegal indirect type: 0x%X\n", 288 address & INDIRECT_TYPE_MSK); 289 break; 290 } 291 292 /* translate the offset from words to byte */ 293 return (address & ADDRESS_MSK) + (offset << 1); 294} 295 296static u16 iwl5000_eeprom_calib_version(struct iwl_priv *priv) 297{ 298 struct iwl_eeprom_calib_hdr { 299 u8 version; 300 u8 pa_type; 301 u16 voltage; 302 } *hdr; 303 304 hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv, 305 EEPROM_5000_CALIB_ALL); 306 return hdr->version; 307 308} 309 310static void iwl5000_gain_computation(struct iwl_priv *priv, 311 u32 average_noise[NUM_RX_CHAINS], 312 u16 min_average_noise_antenna_i, 313 u32 min_average_noise) 314{ 315 int i; 316 s32 delta_g; 317 struct iwl_chain_noise_data *data = &priv->chain_noise_data; 318 319 /* Find Gain Code for the antennas B and C */ 320 for (i = 1; i < NUM_RX_CHAINS; i++) { 321 if ((data->disconn_array[i])) { 322 data->delta_gain_code[i] = 0; 323 continue; 324 } 325 delta_g = (1000 * ((s32)average_noise[0] - 326 (s32)average_noise[i])) / 1500; 327 /* bound gain by 2 bits value max, 3rd bit is sign */ 328 data->delta_gain_code[i] = 329 min(abs(delta_g), CHAIN_NOISE_MAX_DELTA_GAIN_CODE); 330 331 if (delta_g < 0) 332 /* set negative sign */ 333 data->delta_gain_code[i] |= (1 << 2); 334 } 335 336 IWL_DEBUG_CALIB("Delta gains: ANT_B = %d ANT_C = %d\n", 337 data->delta_gain_code[1], data->delta_gain_code[2]); 338 339 if (!data->radio_write) { 340 struct iwl_calib_chain_noise_gain_cmd cmd; 341 memset(&cmd, 0, sizeof(cmd)); 342 343 cmd.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD; 344 cmd.delta_gain_1 = data->delta_gain_code[1]; 345 cmd.delta_gain_2 = data->delta_gain_code[2]; 346 iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD, 347 sizeof(cmd), &cmd, NULL); 348 349 data->radio_write = 1; 350 data->state = IWL_CHAIN_NOISE_CALIBRATED; 351 } 352 353 data->chain_noise_a = 0; 354 data->chain_noise_b = 0; 355 data->chain_noise_c = 0; 356 data->chain_signal_a = 0; 357 data->chain_signal_b = 0; 358 data->chain_signal_c = 0; 359 data->beacon_count = 0; 360} 361 362static void iwl5000_chain_noise_reset(struct iwl_priv *priv) 363{ 364 struct iwl_chain_noise_data *data = &priv->chain_noise_data; 365 366 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) { 367 struct iwl_calib_chain_noise_reset_cmd cmd; 368 369 memset(&cmd, 0, sizeof(cmd)); 370 cmd.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD; 371 if (iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD, 372 sizeof(cmd), &cmd)) 373 IWL_ERROR("Could not send REPLY_PHY_CALIBRATION_CMD\n"); 374 data->state = IWL_CHAIN_NOISE_ACCUMULATE; 375 IWL_DEBUG_CALIB("Run chain_noise_calibrate\n"); 376 } 377} 378 379static void iwl5000_rts_tx_cmd_flag(struct ieee80211_tx_info *info, 380 __le32 *tx_flags) 381{ 382 if ((info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) || 383 (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT)) 384 *tx_flags |= TX_CMD_FLG_RTS_CTS_MSK; 385 else 386 *tx_flags &= ~TX_CMD_FLG_RTS_CTS_MSK; 387} 388 389static struct iwl_sensitivity_ranges iwl5000_sensitivity = { 390 .min_nrg_cck = 95, 391 .max_nrg_cck = 0, 392 .auto_corr_min_ofdm = 90, 393 .auto_corr_min_ofdm_mrc = 170, 394 .auto_corr_min_ofdm_x1 = 120, 395 .auto_corr_min_ofdm_mrc_x1 = 240, 396 397 .auto_corr_max_ofdm = 120, 398 .auto_corr_max_ofdm_mrc = 210, 399 .auto_corr_max_ofdm_x1 = 155, 400 .auto_corr_max_ofdm_mrc_x1 = 290, 401 402 .auto_corr_min_cck = 125, 403 .auto_corr_max_cck = 200, 404 .auto_corr_min_cck_mrc = 170, 405 .auto_corr_max_cck_mrc = 400, 406 .nrg_th_cck = 95, 407 .nrg_th_ofdm = 95, 408}; 409 410static const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv, 411 size_t offset) 412{ 413 u32 address = eeprom_indirect_address(priv, offset); 414 BUG_ON(address >= priv->cfg->eeprom_size); 415 return &priv->eeprom[address]; 416} 417 418/* 419 * Calibration 420 */ 421static int iwl5000_set_Xtal_calib(struct iwl_priv *priv) 422{ 423 u8 data[sizeof(struct iwl_calib_hdr) + 424 sizeof(struct iwl_cal_xtal_freq)]; 425 struct iwl_calib_cmd *cmd = (struct iwl_calib_cmd *)data; 426 struct iwl_cal_xtal_freq *xtal = (struct iwl_cal_xtal_freq *)cmd->data; 427 u16 *xtal_calib = (u16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_XTAL); 428 429 cmd->hdr.op_code = IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD; 430 xtal->cap_pin1 = (u8)xtal_calib[0]; 431 xtal->cap_pin2 = (u8)xtal_calib[1]; 432 return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL], 433 data, sizeof(data)); 434} 435 436static int iwl5000_send_calib_cfg(struct iwl_priv *priv) 437{ 438 struct iwl_calib_cfg_cmd calib_cfg_cmd; 439 struct iwl_host_cmd cmd = { 440 .id = CALIBRATION_CFG_CMD, 441 .len = sizeof(struct iwl_calib_cfg_cmd), 442 .data = &calib_cfg_cmd, 443 }; 444 445 memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd)); 446 calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL; 447 calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL; 448 calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL; 449 calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL; 450 451 return iwl_send_cmd(priv, &cmd); 452} 453 454static void iwl5000_rx_calib_result(struct iwl_priv *priv, 455 struct iwl_rx_mem_buffer *rxb) 456{ 457 struct iwl_rx_packet *pkt = (void *)rxb->skb->data; 458 struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw; 459 int len = le32_to_cpu(pkt->len) & FH_RSCSR_FRAME_SIZE_MSK; 460 int index; 461 462 /* reduce the size of the length field itself */ 463 len -= 4; 464 465 /* Define the order in which the results will be sent to the runtime 466 * uCode. iwl_send_calib_results sends them in a row according to their 467 * index. We sort them here */ 468 switch (hdr->op_code) { 469 case IWL_PHY_CALIBRATE_LO_CMD: 470 index = IWL_CALIB_LO; 471 break; 472 case IWL_PHY_CALIBRATE_TX_IQ_CMD: 473 index = IWL_CALIB_TX_IQ; 474 break; 475 case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD: 476 index = IWL_CALIB_TX_IQ_PERD; 477 break; 478 default: 479 IWL_ERROR("Unknown calibration notification %d\n", 480 hdr->op_code); 481 return; 482 } 483 iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len); 484} 485 486static void iwl5000_rx_calib_complete(struct iwl_priv *priv, 487 struct iwl_rx_mem_buffer *rxb) 488{ 489 IWL_DEBUG_INFO("Init. calibration is completed, restarting fw.\n"); 490 queue_work(priv->workqueue, &priv->restart); 491} 492 493/* 494 * ucode 495 */ 496static int iwl5000_load_section(struct iwl_priv *priv, 497 struct fw_desc *image, 498 u32 dst_addr) 499{ 500 int ret = 0; 501 unsigned long flags; 502 503 dma_addr_t phy_addr = image->p_addr; 504 u32 byte_cnt = image->len; 505 506 spin_lock_irqsave(&priv->lock, flags); 507 ret = iwl_grab_nic_access(priv); 508 if (ret) { 509 spin_unlock_irqrestore(&priv->lock, flags); 510 return ret; 511 } 512 513 iwl_write_direct32(priv, 514 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 515 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); 516 517 iwl_write_direct32(priv, 518 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr); 519 520 iwl_write_direct32(priv, 521 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), 522 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); 523 524 iwl_write_direct32(priv, 525 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), 526 (iwl_get_dma_hi_addr(phy_addr) 527 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); 528 529 iwl_write_direct32(priv, 530 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), 531 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM | 532 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX | 533 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); 534 535 iwl_write_direct32(priv, 536 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 537 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 538 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | 539 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); 540 541 iwl_release_nic_access(priv); 542 spin_unlock_irqrestore(&priv->lock, flags); 543 return 0; 544} 545 546static int iwl5000_load_given_ucode(struct iwl_priv *priv, 547 struct fw_desc *inst_image, 548 struct fw_desc *data_image) 549{ 550 int ret = 0; 551 552 ret = iwl5000_load_section(priv, inst_image, RTC_INST_LOWER_BOUND); 553 if (ret) 554 return ret; 555 556 IWL_DEBUG_INFO("INST uCode section being loaded...\n"); 557 ret = wait_event_interruptible_timeout(priv->wait_command_queue, 558 priv->ucode_write_complete, 5 * HZ); 559 if (ret == -ERESTARTSYS) { 560 IWL_ERROR("Could not load the INST uCode section due " 561 "to interrupt\n"); 562 return ret; 563 } 564 if (!ret) { 565 IWL_ERROR("Could not load the INST uCode section\n"); 566 return -ETIMEDOUT; 567 } 568 569 priv->ucode_write_complete = 0; 570 571 ret = iwl5000_load_section( 572 priv, data_image, RTC_DATA_LOWER_BOUND); 573 if (ret) 574 return ret; 575 576 IWL_DEBUG_INFO("DATA uCode section being loaded...\n"); 577 578 ret = wait_event_interruptible_timeout(priv->wait_command_queue, 579 priv->ucode_write_complete, 5 * HZ); 580 if (ret == -ERESTARTSYS) { 581 IWL_ERROR("Could not load the INST uCode section due " 582 "to interrupt\n"); 583 return ret; 584 } else if (!ret) { 585 IWL_ERROR("Could not load the DATA uCode section\n"); 586 return -ETIMEDOUT; 587 } else 588 ret = 0; 589 590 priv->ucode_write_complete = 0; 591 592 return ret; 593} 594 595static int iwl5000_load_ucode(struct iwl_priv *priv) 596{ 597 int ret = 0; 598 599 /* check whether init ucode should be loaded, or rather runtime ucode */ 600 if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) { 601 IWL_DEBUG_INFO("Init ucode found. Loading init ucode...\n"); 602 ret = iwl5000_load_given_ucode(priv, 603 &priv->ucode_init, &priv->ucode_init_data); 604 if (!ret) { 605 IWL_DEBUG_INFO("Init ucode load complete.\n"); 606 priv->ucode_type = UCODE_INIT; 607 } 608 } else { 609 IWL_DEBUG_INFO("Init ucode not found, or already loaded. " 610 "Loading runtime ucode...\n"); 611 ret = iwl5000_load_given_ucode(priv, 612 &priv->ucode_code, &priv->ucode_data); 613 if (!ret) { 614 IWL_DEBUG_INFO("Runtime ucode load complete.\n"); 615 priv->ucode_type = UCODE_RT; 616 } 617 } 618 619 return ret; 620} 621 622static void iwl5000_init_alive_start(struct iwl_priv *priv) 623{ 624 int ret = 0; 625 626 /* Check alive response for "valid" sign from uCode */ 627 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) { 628 /* We had an error bringing up the hardware, so take it 629 * all the way back down so we can try again */ 630 IWL_DEBUG_INFO("Initialize Alive failed.\n"); 631 goto restart; 632 } 633 634 /* initialize uCode was loaded... verify inst image. 635 * This is a paranoid check, because we would not have gotten the 636 * "initialize" alive if code weren't properly loaded. */ 637 if (iwl_verify_ucode(priv)) { 638 /* Runtime instruction load was bad; 639 * take it all the way back down so we can try again */ 640 IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n"); 641 goto restart; 642 } 643 644 iwl_clear_stations_table(priv); 645 ret = priv->cfg->ops->lib->alive_notify(priv); 646 if (ret) { 647 IWL_WARNING("Could not complete ALIVE transition: %d\n", ret); 648 goto restart; 649 } 650 651 iwl5000_send_calib_cfg(priv); 652 return; 653 654restart: 655 /* real restart (first load init_ucode) */ 656 queue_work(priv->workqueue, &priv->restart); 657} 658 659static void iwl5000_set_wr_ptrs(struct iwl_priv *priv, 660 int txq_id, u32 index) 661{ 662 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 663 (index & 0xff) | (txq_id << 8)); 664 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index); 665} 666 667static void iwl5000_tx_queue_set_status(struct iwl_priv *priv, 668 struct iwl_tx_queue *txq, 669 int tx_fifo_id, int scd_retry) 670{ 671 int txq_id = txq->q.id; 672 int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0; 673 674 iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id), 675 (active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) | 676 (tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) | 677 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) | 678 IWL50_SCD_QUEUE_STTS_REG_MSK); 679 680 txq->sched_retry = scd_retry; 681 682 IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n", 683 active ? "Activate" : "Deactivate", 684 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id); 685} 686 687static int iwl5000_send_wimax_coex(struct iwl_priv *priv) 688{ 689 struct iwl_wimax_coex_cmd coex_cmd; 690 691 memset(&coex_cmd, 0, sizeof(coex_cmd)); 692 693 return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD, 694 sizeof(coex_cmd), &coex_cmd); 695} 696 697static int iwl5000_alive_notify(struct iwl_priv *priv) 698{ 699 u32 a; 700 int i = 0; 701 unsigned long flags; 702 int ret; 703 704 spin_lock_irqsave(&priv->lock, flags); 705 706 ret = iwl_grab_nic_access(priv); 707 if (ret) { 708 spin_unlock_irqrestore(&priv->lock, flags); 709 return ret; 710 } 711 712 priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR); 713 a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET; 714 for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET; 715 a += 4) 716 iwl_write_targ_mem(priv, a, 0); 717 for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET; 718 a += 4) 719 iwl_write_targ_mem(priv, a, 0); 720 for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4) 721 iwl_write_targ_mem(priv, a, 0); 722 723 iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR, 724 priv->scd_bc_tbls.dma >> 10); 725 iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, 726 IWL50_SCD_QUEUECHAIN_SEL_ALL(priv->hw_params.max_txq_num)); 727 iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0); 728 729 /* initiate the queues */ 730 for (i = 0; i < priv->hw_params.max_txq_num; i++) { 731 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0); 732 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8)); 733 iwl_write_targ_mem(priv, priv->scd_base_addr + 734 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0); 735 iwl_write_targ_mem(priv, priv->scd_base_addr + 736 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) + 737 sizeof(u32), 738 ((SCD_WIN_SIZE << 739 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & 740 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | 741 ((SCD_FRAME_LIMIT << 742 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & 743 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); 744 } 745 746 iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK, 747 IWL_MASK(0, priv->hw_params.max_txq_num)); 748 749 /* Activate all Tx DMA/FIFO channels */ 750 priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7)); 751 752 iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0); 753 754 /* map qos queues to fifos one-to-one */ 755 for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) { 756 int ac = iwl5000_default_queue_to_tx_fifo[i]; 757 iwl_txq_ctx_activate(priv, i); 758 iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0); 759 } 760 /* TODO - need to initialize those FIFOs inside the loop above, 761 * not only mark them as active */ 762 iwl_txq_ctx_activate(priv, 4); 763 iwl_txq_ctx_activate(priv, 7); 764 iwl_txq_ctx_activate(priv, 8); 765 iwl_txq_ctx_activate(priv, 9); 766 767 iwl_release_nic_access(priv); 768 spin_unlock_irqrestore(&priv->lock, flags); 769 770 771 iwl5000_send_wimax_coex(priv); 772 773 iwl5000_set_Xtal_calib(priv); 774 iwl_send_calib_results(priv); 775 776 return 0; 777} 778 779static int iwl5000_hw_set_hw_params(struct iwl_priv *priv) 780{ 781 if ((priv->cfg->mod_params->num_of_queues > IWL50_NUM_QUEUES) || 782 (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) { 783 IWL_ERROR("invalid queues_num, should be between %d and %d\n", 784 IWL_MIN_NUM_QUEUES, IWL50_NUM_QUEUES); 785 return -EINVAL; 786 } 787 788 priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues; 789 priv->hw_params.scd_bc_tbls_size = 790 IWL50_NUM_QUEUES * sizeof(struct iwl5000_scd_bc_tbl); 791 priv->hw_params.max_stations = IWL5000_STATION_COUNT; 792 priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID; 793 priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE; 794 priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE; 795 priv->hw_params.max_bsm_size = 0; 796 priv->hw_params.fat_channel = BIT(IEEE80211_BAND_2GHZ) | 797 BIT(IEEE80211_BAND_5GHZ); 798 priv->hw_params.sens = &iwl5000_sensitivity; 799 800 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) { 801 case CSR_HW_REV_TYPE_5100: 802 priv->hw_params.tx_chains_num = 1; 803 priv->hw_params.rx_chains_num = 2; 804 priv->hw_params.valid_tx_ant = ANT_B; 805 priv->hw_params.valid_rx_ant = ANT_AB; 806 break; 807 case CSR_HW_REV_TYPE_5150: 808 priv->hw_params.tx_chains_num = 1; 809 priv->hw_params.rx_chains_num = 2; 810 priv->hw_params.valid_tx_ant = ANT_A; 811 priv->hw_params.valid_rx_ant = ANT_AB; 812 break; 813 case CSR_HW_REV_TYPE_5300: 814 case CSR_HW_REV_TYPE_5350: 815 priv->hw_params.tx_chains_num = 3; 816 priv->hw_params.rx_chains_num = 3; 817 priv->hw_params.valid_tx_ant = ANT_ABC; 818 priv->hw_params.valid_rx_ant = ANT_ABC; 819 break; 820 } 821 822 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) { 823 case CSR_HW_REV_TYPE_5100: 824 case CSR_HW_REV_TYPE_5300: 825 case CSR_HW_REV_TYPE_5350: 826 /* 5X00 and 5350 wants in Celsius */ 827 priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD; 828 break; 829 case CSR_HW_REV_TYPE_5150: 830 /* 5150 wants in Kelvin */ 831 priv->hw_params.ct_kill_threshold = 832 CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD); 833 break; 834 } 835 836 /* Set initial calibration set */ 837 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) { 838 case CSR_HW_REV_TYPE_5100: 839 case CSR_HW_REV_TYPE_5300: 840 case CSR_HW_REV_TYPE_5350: 841 priv->hw_params.calib_init_cfg = 842 BIT(IWL_CALIB_XTAL) | 843 BIT(IWL_CALIB_LO) | 844 BIT(IWL_CALIB_TX_IQ) | 845 BIT(IWL_CALIB_TX_IQ_PERD); 846 break; 847 case CSR_HW_REV_TYPE_5150: 848 priv->hw_params.calib_init_cfg = 0; 849 break; 850 } 851 852 853 return 0; 854} 855 856/** 857 * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array 858 */ 859static void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv, 860 struct iwl_tx_queue *txq, 861 u16 byte_cnt) 862{ 863 struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr; 864 int write_ptr = txq->q.write_ptr; 865 int txq_id = txq->q.id; 866 u8 sec_ctl = 0; 867 u8 sta_id = 0; 868 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE; 869 __le16 bc_ent; 870 871 WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX); 872 873 if (txq_id != IWL_CMD_QUEUE_NUM) { 874 sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id; 875 sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl; 876 877 switch (sec_ctl & TX_CMD_SEC_MSK) { 878 case TX_CMD_SEC_CCM: 879 len += CCMP_MIC_LEN; 880 break; 881 case TX_CMD_SEC_TKIP: 882 len += TKIP_ICV_LEN; 883 break; 884 case TX_CMD_SEC_WEP: 885 len += WEP_IV_LEN + WEP_ICV_LEN; 886 break; 887 } 888 } 889 890 bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12)); 891 892 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent; 893 894 if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP) 895 scd_bc_tbl[txq_id]. 896 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent; 897} 898 899static void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv, 900 struct iwl_tx_queue *txq) 901{ 902 struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr; 903 int txq_id = txq->q.id; 904 int read_ptr = txq->q.read_ptr; 905 u8 sta_id = 0; 906 __le16 bc_ent; 907 908 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX); 909 910 if (txq_id != IWL_CMD_QUEUE_NUM) 911 sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id; 912 913 bc_ent = cpu_to_le16(1 | (sta_id << 12)); 914 scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent; 915 916 if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP) 917 scd_bc_tbl[txq_id]. 918 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent; 919} 920 921static int iwl5000_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid, 922 u16 txq_id) 923{ 924 u32 tbl_dw_addr; 925 u32 tbl_dw; 926 u16 scd_q2ratid; 927 928 scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK; 929 930 tbl_dw_addr = priv->scd_base_addr + 931 IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id); 932 933 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr); 934 935 if (txq_id & 0x1) 936 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF); 937 else 938 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000); 939 940 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw); 941 942 return 0; 943} 944static void iwl5000_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id) 945{ 946 /* Simply stop the queue, but don't change any configuration; 947 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */ 948 iwl_write_prph(priv, 949 IWL50_SCD_QUEUE_STATUS_BITS(txq_id), 950 (0 << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE)| 951 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN)); 952} 953 954static int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id, 955 int tx_fifo, int sta_id, int tid, u16 ssn_idx) 956{ 957 unsigned long flags; 958 int ret; 959 u16 ra_tid; 960 961 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) || 962 (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) { 963 IWL_WARNING("queue number out of range: %d, must be %d to %d\n", 964 txq_id, IWL50_FIRST_AMPDU_QUEUE, 965 IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1); 966 return -EINVAL; 967 } 968 969 ra_tid = BUILD_RAxTID(sta_id, tid); 970 971 /* Modify device's station table to Tx this TID */ 972 iwl_sta_tx_modify_enable_tid(priv, sta_id, tid); 973 974 spin_lock_irqsave(&priv->lock, flags); 975 ret = iwl_grab_nic_access(priv); 976 if (ret) { 977 spin_unlock_irqrestore(&priv->lock, flags); 978 return ret; 979 } 980 981 /* Stop this Tx queue before configuring it */ 982 iwl5000_tx_queue_stop_scheduler(priv, txq_id); 983 984 /* Map receiver-address / traffic-ID to this queue */ 985 iwl5000_tx_queue_set_q2ratid(priv, ra_tid, txq_id); 986 987 /* Set this queue as a chain-building queue */ 988 iwl_set_bits_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, (1<<txq_id)); 989 990 /* enable aggregations for the queue */ 991 iwl_set_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1<<txq_id)); 992 993 /* Place first TFD at index corresponding to start sequence number. 994 * Assumes that ssn_idx is valid (!= 0xFFF) */ 995 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff); 996 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff); 997 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx); 998 999 /* Set up Tx window size and frame limit for this queue */ 1000 iwl_write_targ_mem(priv, priv->scd_base_addr + 1001 IWL50_SCD_CONTEXT_QUEUE_OFFSET(txq_id) + 1002 sizeof(u32), 1003 ((SCD_WIN_SIZE << 1004 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & 1005 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | 1006 ((SCD_FRAME_LIMIT << 1007 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & 1008 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); 1009 1010 iwl_set_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id)); 1011 1012 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */ 1013 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1); 1014 1015 iwl_release_nic_access(priv); 1016 spin_unlock_irqrestore(&priv->lock, flags); 1017 1018 return 0; 1019} 1020 1021static int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id, 1022 u16 ssn_idx, u8 tx_fifo) 1023{ 1024 int ret; 1025 1026 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) || 1027 (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) { 1028 IWL_WARNING("queue number out of range: %d, must be %d to %d\n", 1029 txq_id, IWL50_FIRST_AMPDU_QUEUE, 1030 IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1); 1031 return -EINVAL; 1032 } 1033 1034 ret = iwl_grab_nic_access(priv); 1035 if (ret) 1036 return ret; 1037 1038 iwl5000_tx_queue_stop_scheduler(priv, txq_id); 1039 1040 iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id)); 1041 1042 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff); 1043 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff); 1044 /* supposes that ssn_idx is valid (!= 0xFFF) */ 1045 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx); 1046 1047 iwl_clear_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id)); 1048 iwl_txq_ctx_deactivate(priv, txq_id); 1049 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0); 1050 1051 iwl_release_nic_access(priv); 1052 1053 return 0; 1054} 1055 1056static u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data) 1057{ 1058 u16 size = (u16)sizeof(struct iwl_addsta_cmd); 1059 memcpy(data, cmd, size); 1060 return size; 1061} 1062 1063 1064/* 1065 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask 1066 * must be called under priv->lock and mac access 1067 */ 1068static void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask) 1069{ 1070 iwl_write_prph(priv, IWL50_SCD_TXFACT, mask); 1071} 1072 1073 1074static inline u32 iwl5000_get_scd_ssn(struct iwl5000_tx_resp *tx_resp) 1075{ 1076 return le32_to_cpup((__le32 *)&tx_resp->status + 1077 tx_resp->frame_count) & MAX_SN; 1078} 1079 1080static int iwl5000_tx_status_reply_tx(struct iwl_priv *priv, 1081 struct iwl_ht_agg *agg, 1082 struct iwl5000_tx_resp *tx_resp, 1083 int txq_id, u16 start_idx) 1084{ 1085 u16 status; 1086 struct agg_tx_status *frame_status = &tx_resp->status; 1087 struct ieee80211_tx_info *info = NULL; 1088 struct ieee80211_hdr *hdr = NULL; 1089 u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags); 1090 int i, sh, idx; 1091 u16 seq; 1092 1093 if (agg->wait_for_ba) 1094 IWL_DEBUG_TX_REPLY("got tx response w/o block-ack\n"); 1095 1096 agg->frame_count = tx_resp->frame_count; 1097 agg->start_idx = start_idx; 1098 agg->rate_n_flags = rate_n_flags; 1099 agg->bitmap = 0; 1100 1101 /* # frames attempted by Tx command */ 1102 if (agg->frame_count == 1) { 1103 /* Only one frame was attempted; no block-ack will arrive */ 1104 status = le16_to_cpu(frame_status[0].status); 1105 idx = start_idx; 1106 1107 /* FIXME: code repetition */ 1108 IWL_DEBUG_TX_REPLY("FrameCnt = %d, StartIdx=%d idx=%d\n", 1109 agg->frame_count, agg->start_idx, idx); 1110 1111 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]); 1112 info->status.rates[0].count = tx_resp->failure_frame + 1; 1113 info->flags &= ~IEEE80211_TX_CTL_AMPDU; 1114 info->flags |= iwl_is_tx_success(status) ? 1115 IEEE80211_TX_STAT_ACK : 0; 1116 iwl_hwrate_to_tx_control(priv, rate_n_flags, info); 1117 1118 /* FIXME: code repetition end */ 1119 1120 IWL_DEBUG_TX_REPLY("1 Frame 0x%x failure :%d\n", 1121 status & 0xff, tx_resp->failure_frame); 1122 IWL_DEBUG_TX_REPLY("Rate Info rate_n_flags=%x\n", rate_n_flags); 1123 1124 agg->wait_for_ba = 0; 1125 } else { 1126 /* Two or more frames were attempted; expect block-ack */ 1127 u64 bitmap = 0; 1128 int start = agg->start_idx; 1129 1130 /* Construct bit-map of pending frames within Tx window */ 1131 for (i = 0; i < agg->frame_count; i++) { 1132 u16 sc; 1133 status = le16_to_cpu(frame_status[i].status); 1134 seq = le16_to_cpu(frame_status[i].sequence); 1135 idx = SEQ_TO_INDEX(seq); 1136 txq_id = SEQ_TO_QUEUE(seq); 1137 1138 if (status & (AGG_TX_STATE_FEW_BYTES_MSK | 1139 AGG_TX_STATE_ABORT_MSK)) 1140 continue; 1141 1142 IWL_DEBUG_TX_REPLY("FrameCnt = %d, txq_id=%d idx=%d\n", 1143 agg->frame_count, txq_id, idx); 1144 1145 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx); 1146 1147 sc = le16_to_cpu(hdr->seq_ctrl); 1148 if (idx != (SEQ_TO_SN(sc) & 0xff)) { 1149 IWL_ERROR("BUG_ON idx doesn't match seq control" 1150 " idx=%d, seq_idx=%d, seq=%d\n", 1151 idx, SEQ_TO_SN(sc), 1152 hdr->seq_ctrl); 1153 return -1; 1154 } 1155 1156 IWL_DEBUG_TX_REPLY("AGG Frame i=%d idx %d seq=%d\n", 1157 i, idx, SEQ_TO_SN(sc)); 1158 1159 sh = idx - start; 1160 if (sh > 64) { 1161 sh = (start - idx) + 0xff; 1162 bitmap = bitmap << sh; 1163 sh = 0; 1164 start = idx; 1165 } else if (sh < -64) 1166 sh = 0xff - (start - idx); 1167 else if (sh < 0) { 1168 sh = start - idx; 1169 start = idx; 1170 bitmap = bitmap << sh; 1171 sh = 0; 1172 } 1173 bitmap |= 1ULL << sh; 1174 IWL_DEBUG_TX_REPLY("start=%d bitmap=0x%llx\n", 1175 start, (unsigned long long)bitmap); 1176 } 1177 1178 agg->bitmap = bitmap; 1179 agg->start_idx = start; 1180 IWL_DEBUG_TX_REPLY("Frames %d start_idx=%d bitmap=0x%llx\n", 1181 agg->frame_count, agg->start_idx, 1182 (unsigned long long)agg->bitmap); 1183 1184 if (bitmap) 1185 agg->wait_for_ba = 1; 1186 } 1187 return 0; 1188} 1189 1190static void iwl5000_rx_reply_tx(struct iwl_priv *priv, 1191 struct iwl_rx_mem_buffer *rxb) 1192{ 1193 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; 1194 u16 sequence = le16_to_cpu(pkt->hdr.sequence); 1195 int txq_id = SEQ_TO_QUEUE(sequence); 1196 int index = SEQ_TO_INDEX(sequence); 1197 struct iwl_tx_queue *txq = &priv->txq[txq_id]; 1198 struct ieee80211_tx_info *info; 1199 struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0]; 1200 u32 status = le16_to_cpu(tx_resp->status.status); 1201 int tid; 1202 int sta_id; 1203 int freed; 1204 1205 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) { 1206 IWL_ERROR("Read index for DMA queue txq_id (%d) index %d " 1207 "is out of range [0-%d] %d %d\n", txq_id, 1208 index, txq->q.n_bd, txq->q.write_ptr, 1209 txq->q.read_ptr); 1210 return; 1211 } 1212 1213 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]); 1214 memset(&info->status, 0, sizeof(info->status)); 1215 1216 tid = (tx_resp->ra_tid & IWL50_TX_RES_TID_MSK) >> IWL50_TX_RES_TID_POS; 1217 sta_id = (tx_resp->ra_tid & IWL50_TX_RES_RA_MSK) >> IWL50_TX_RES_RA_POS; 1218 1219 if (txq->sched_retry) { 1220 const u32 scd_ssn = iwl5000_get_scd_ssn(tx_resp); 1221 struct iwl_ht_agg *agg = NULL; 1222 1223 agg = &priv->stations[sta_id].tid[tid].agg; 1224 1225 iwl5000_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index); 1226 1227 /* check if BAR is needed */ 1228 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status)) 1229 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK; 1230 1231 if (txq->q.read_ptr != (scd_ssn & 0xff)) { 1232 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd); 1233 IWL_DEBUG_TX_REPLY("Retry scheduler reclaim " 1234 "scd_ssn=%d idx=%d txq=%d swq=%d\n", 1235 scd_ssn , index, txq_id, txq->swq_id); 1236 1237 freed = iwl_tx_queue_reclaim(priv, txq_id, index); 1238 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed; 1239 1240 if (priv->mac80211_registered && 1241 (iwl_queue_space(&txq->q) > txq->q.low_mark) && 1242 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) { 1243 if (agg->state == IWL_AGG_OFF) 1244 ieee80211_wake_queue(priv->hw, txq_id); 1245 else 1246 ieee80211_wake_queue(priv->hw, 1247 txq->swq_id); 1248 } 1249 } 1250 } else { 1251 BUG_ON(txq_id != txq->swq_id); 1252 1253 info->status.rates[0].count = tx_resp->failure_frame + 1; 1254 info->flags |= iwl_is_tx_success(status) ? 1255 IEEE80211_TX_STAT_ACK : 0; 1256 iwl_hwrate_to_tx_control(priv, 1257 le32_to_cpu(tx_resp->rate_n_flags), 1258 info); 1259 1260 IWL_DEBUG_TX_REPLY("TXQ %d status %s (0x%08x) rate_n_flags " 1261 "0x%x retries %d\n", 1262 txq_id, 1263 iwl_get_tx_fail_reason(status), status, 1264 le32_to_cpu(tx_resp->rate_n_flags), 1265 tx_resp->failure_frame); 1266 1267 freed = iwl_tx_queue_reclaim(priv, txq_id, index); 1268 if (ieee80211_is_data_qos(tx_resp->frame_ctrl)) 1269 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed; 1270 1271 if (priv->mac80211_registered && 1272 (iwl_queue_space(&txq->q) > txq->q.low_mark)) 1273 ieee80211_wake_queue(priv->hw, txq_id); 1274 } 1275 1276 if (ieee80211_is_data_qos(tx_resp->frame_ctrl)) 1277 iwl_txq_check_empty(priv, sta_id, tid, txq_id); 1278 1279 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK)) 1280 IWL_ERROR("TODO: Implement Tx ABORT REQUIRED!!!\n"); 1281} 1282 1283/* Currently 5000 is the superset of everything */ 1284static u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len) 1285{ 1286 return len; 1287} 1288 1289static void iwl5000_setup_deferred_work(struct iwl_priv *priv) 1290{ 1291 /* in 5000 the tx power calibration is done in uCode */ 1292 priv->disable_tx_power_cal = 1; 1293} 1294 1295static void iwl5000_rx_handler_setup(struct iwl_priv *priv) 1296{ 1297 /* init calibration handlers */ 1298 priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] = 1299 iwl5000_rx_calib_result; 1300 priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] = 1301 iwl5000_rx_calib_complete; 1302 priv->rx_handlers[REPLY_TX] = iwl5000_rx_reply_tx; 1303} 1304 1305 1306static int iwl5000_hw_valid_rtc_data_addr(u32 addr) 1307{ 1308 return (addr >= RTC_DATA_LOWER_BOUND) && 1309 (addr < IWL50_RTC_DATA_UPPER_BOUND); 1310} 1311 1312static int iwl5000_send_rxon_assoc(struct iwl_priv *priv) 1313{ 1314 int ret = 0; 1315 struct iwl5000_rxon_assoc_cmd rxon_assoc; 1316 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon; 1317 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon; 1318 1319 if ((rxon1->flags == rxon2->flags) && 1320 (rxon1->filter_flags == rxon2->filter_flags) && 1321 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) && 1322 (rxon1->ofdm_ht_single_stream_basic_rates == 1323 rxon2->ofdm_ht_single_stream_basic_rates) && 1324 (rxon1->ofdm_ht_dual_stream_basic_rates == 1325 rxon2->ofdm_ht_dual_stream_basic_rates) && 1326 (rxon1->ofdm_ht_triple_stream_basic_rates == 1327 rxon2->ofdm_ht_triple_stream_basic_rates) && 1328 (rxon1->acquisition_data == rxon2->acquisition_data) && 1329 (rxon1->rx_chain == rxon2->rx_chain) && 1330 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) { 1331 IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n"); 1332 return 0; 1333 } 1334 1335 rxon_assoc.flags = priv->staging_rxon.flags; 1336 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags; 1337 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates; 1338 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates; 1339 rxon_assoc.reserved1 = 0; 1340 rxon_assoc.reserved2 = 0; 1341 rxon_assoc.reserved3 = 0; 1342 rxon_assoc.ofdm_ht_single_stream_basic_rates = 1343 priv->staging_rxon.ofdm_ht_single_stream_basic_rates; 1344 rxon_assoc.ofdm_ht_dual_stream_basic_rates = 1345 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates; 1346 rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain; 1347 rxon_assoc.ofdm_ht_triple_stream_basic_rates = 1348 priv->staging_rxon.ofdm_ht_triple_stream_basic_rates; 1349 rxon_assoc.acquisition_data = priv->staging_rxon.acquisition_data; 1350 1351 ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC, 1352 sizeof(rxon_assoc), &rxon_assoc, NULL); 1353 if (ret) 1354 return ret; 1355 1356 return ret; 1357} 1358static int iwl5000_send_tx_power(struct iwl_priv *priv) 1359{ 1360 struct iwl5000_tx_power_dbm_cmd tx_power_cmd; 1361 1362 /* half dBm need to multiply */ 1363 tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt); 1364 tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED; 1365 tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO; 1366 return iwl_send_cmd_pdu_async(priv, REPLY_TX_POWER_DBM_CMD, 1367 sizeof(tx_power_cmd), &tx_power_cmd, 1368 NULL); 1369} 1370 1371static void iwl5000_temperature(struct iwl_priv *priv) 1372{ 1373 /* store temperature from statistics (in Celsius) */ 1374 priv->temperature = le32_to_cpu(priv->statistics.general.temperature); 1375} 1376 1377/* Calc max signal level (dBm) among 3 possible receivers */ 1378static int iwl5000_calc_rssi(struct iwl_priv *priv, 1379 struct iwl_rx_phy_res *rx_resp) 1380{ 1381 /* data from PHY/DSP regarding signal strength, etc., 1382 * contents are always there, not configurable by host 1383 */ 1384 struct iwl5000_non_cfg_phy *ncphy = 1385 (struct iwl5000_non_cfg_phy *)rx_resp->non_cfg_phy_buf; 1386 u32 val, rssi_a, rssi_b, rssi_c, max_rssi; 1387 u8 agc; 1388 1389 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_AGC_IDX]); 1390 agc = (val & IWL50_OFDM_AGC_MSK) >> IWL50_OFDM_AGC_BIT_POS; 1391 1392 /* Find max rssi among 3 possible receivers. 1393 * These values are measured by the digital signal processor (DSP). 1394 * They should stay fairly constant even as the signal strength varies, 1395 * if the radio's automatic gain control (AGC) is working right. 1396 * AGC value (see below) will provide the "interesting" info. 1397 */ 1398 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_AB_IDX]); 1399 rssi_a = (val & IWL50_OFDM_RSSI_A_MSK) >> IWL50_OFDM_RSSI_A_BIT_POS; 1400 rssi_b = (val & IWL50_OFDM_RSSI_B_MSK) >> IWL50_OFDM_RSSI_B_BIT_POS; 1401 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_C_IDX]); 1402 rssi_c = (val & IWL50_OFDM_RSSI_C_MSK) >> IWL50_OFDM_RSSI_C_BIT_POS; 1403 1404 max_rssi = max_t(u32, rssi_a, rssi_b); 1405 max_rssi = max_t(u32, max_rssi, rssi_c); 1406 1407 IWL_DEBUG_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n", 1408 rssi_a, rssi_b, rssi_c, max_rssi, agc); 1409 1410 /* dBm = max_rssi dB - agc dB - constant. 1411 * Higher AGC (higher radio gain) means lower signal. */ 1412 return max_rssi - agc - IWL_RSSI_OFFSET; 1413} 1414 1415static struct iwl_hcmd_ops iwl5000_hcmd = { 1416 .rxon_assoc = iwl5000_send_rxon_assoc, 1417}; 1418 1419static struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = { 1420 .get_hcmd_size = iwl5000_get_hcmd_size, 1421 .build_addsta_hcmd = iwl5000_build_addsta_hcmd, 1422 .gain_computation = iwl5000_gain_computation, 1423 .chain_noise_reset = iwl5000_chain_noise_reset, 1424 .rts_tx_cmd_flag = iwl5000_rts_tx_cmd_flag, 1425 .calc_rssi = iwl5000_calc_rssi, 1426}; 1427 1428static struct iwl_lib_ops iwl5000_lib = { 1429 .set_hw_params = iwl5000_hw_set_hw_params, 1430 .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl, 1431 .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl, 1432 .txq_set_sched = iwl5000_txq_set_sched, 1433 .txq_agg_enable = iwl5000_txq_agg_enable, 1434 .txq_agg_disable = iwl5000_txq_agg_disable, 1435 .rx_handler_setup = iwl5000_rx_handler_setup, 1436 .setup_deferred_work = iwl5000_setup_deferred_work, 1437 .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr, 1438 .load_ucode = iwl5000_load_ucode, 1439 .init_alive_start = iwl5000_init_alive_start, 1440 .alive_notify = iwl5000_alive_notify, 1441 .send_tx_power = iwl5000_send_tx_power, 1442 .temperature = iwl5000_temperature, 1443 .update_chain_flags = iwl_update_chain_flags, 1444 .apm_ops = { 1445 .init = iwl5000_apm_init, 1446 .reset = iwl5000_apm_reset, 1447 .stop = iwl5000_apm_stop, 1448 .config = iwl5000_nic_config, 1449 .set_pwr_src = iwl_set_pwr_src, 1450 }, 1451 .eeprom_ops = { 1452 .regulatory_bands = { 1453 EEPROM_5000_REG_BAND_1_CHANNELS, 1454 EEPROM_5000_REG_BAND_2_CHANNELS, 1455 EEPROM_5000_REG_BAND_3_CHANNELS, 1456 EEPROM_5000_REG_BAND_4_CHANNELS, 1457 EEPROM_5000_REG_BAND_5_CHANNELS, 1458 EEPROM_5000_REG_BAND_24_FAT_CHANNELS, 1459 EEPROM_5000_REG_BAND_52_FAT_CHANNELS 1460 }, 1461 .verify_signature = iwlcore_eeprom_verify_signature, 1462 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore, 1463 .release_semaphore = iwlcore_eeprom_release_semaphore, 1464 .calib_version = iwl5000_eeprom_calib_version, 1465 .query_addr = iwl5000_eeprom_query_addr, 1466 }, 1467}; 1468 1469static struct iwl_ops iwl5000_ops = { 1470 .lib = &iwl5000_lib, 1471 .hcmd = &iwl5000_hcmd, 1472 .utils = &iwl5000_hcmd_utils, 1473}; 1474 1475static struct iwl_mod_params iwl50_mod_params = { 1476 .num_of_queues = IWL50_NUM_QUEUES, 1477 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES, 1478 .enable_qos = 1, 1479 .amsdu_size_8K = 1, 1480 .restart_fw = 1, 1481 /* the rest are 0 by default */ 1482}; 1483 1484 1485struct iwl_cfg iwl5300_agn_cfg = { 1486 .name = "5300AGN", 1487 .fw_name = IWL5000_MODULE_FIRMWARE, 1488 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N, 1489 .ops = &iwl5000_ops, 1490 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, 1491 .eeprom_ver = EEPROM_5000_EEPROM_VERSION, 1492 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION, 1493 .mod_params = &iwl50_mod_params, 1494}; 1495 1496struct iwl_cfg iwl5100_bg_cfg = { 1497 .name = "5100BG", 1498 .fw_name = IWL5000_MODULE_FIRMWARE, 1499 .sku = IWL_SKU_G, 1500 .ops = &iwl5000_ops, 1501 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, 1502 .eeprom_ver = EEPROM_5000_EEPROM_VERSION, 1503 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION, 1504 .mod_params = &iwl50_mod_params, 1505}; 1506 1507struct iwl_cfg iwl5100_abg_cfg = { 1508 .name = "5100ABG", 1509 .fw_name = IWL5000_MODULE_FIRMWARE, 1510 .sku = IWL_SKU_A|IWL_SKU_G, 1511 .ops = &iwl5000_ops, 1512 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, 1513 .eeprom_ver = EEPROM_5000_EEPROM_VERSION, 1514 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION, 1515 .mod_params = &iwl50_mod_params, 1516}; 1517 1518struct iwl_cfg iwl5100_agn_cfg = { 1519 .name = "5100AGN", 1520 .fw_name = IWL5000_MODULE_FIRMWARE, 1521 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N, 1522 .ops = &iwl5000_ops, 1523 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, 1524 .eeprom_ver = EEPROM_5000_EEPROM_VERSION, 1525 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION, 1526 .mod_params = &iwl50_mod_params, 1527}; 1528 1529struct iwl_cfg iwl5350_agn_cfg = { 1530 .name = "5350AGN", 1531 .fw_name = IWL5000_MODULE_FIRMWARE, 1532 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N, 1533 .ops = &iwl5000_ops, 1534 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, 1535 .eeprom_ver = EEPROM_5050_EEPROM_VERSION, 1536 .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION, 1537 .mod_params = &iwl50_mod_params, 1538}; 1539 1540MODULE_FIRMWARE(IWL5000_MODULE_FIRMWARE); 1541 1542module_param_named(disable50, iwl50_mod_params.disable, int, 0444); 1543MODULE_PARM_DESC(disable50, 1544 "manually disable the 50XX radio (default 0 [radio on])"); 1545module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, 0444); 1546MODULE_PARM_DESC(swcrypto50, 1547 "using software crypto engine (default 0 [hardware])\n"); 1548module_param_named(debug50, iwl50_mod_params.debug, int, 0444); 1549MODULE_PARM_DESC(debug50, "50XX debug output mask"); 1550module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, 0444); 1551MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series"); 1552module_param_named(qos_enable50, iwl50_mod_params.enable_qos, int, 0444); 1553MODULE_PARM_DESC(qos_enable50, "enable all 50XX QoS functionality"); 1554module_param_named(11n_disable50, iwl50_mod_params.disable_11n, int, 0444); 1555MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality"); 1556module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K, int, 0444); 1557MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series"); 1558module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, 0444); 1559MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error"); 1560