iwl-5000.c revision d2f18bfd9bc6b51c8bb72b272ecca902a88387d4
1/****************************************************************************** 2 * 3 * Copyright(c) 2007-2008 Intel Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * The full GNU General Public License is included in this distribution in the 19 * file called LICENSE. 20 * 21 * Contact Information: 22 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 23 * 24 *****************************************************************************/ 25 26#include <linux/kernel.h> 27#include <linux/module.h> 28#include <linux/version.h> 29#include <linux/init.h> 30#include <linux/pci.h> 31#include <linux/dma-mapping.h> 32#include <linux/delay.h> 33#include <linux/skbuff.h> 34#include <linux/netdevice.h> 35#include <linux/wireless.h> 36#include <net/mac80211.h> 37#include <linux/etherdevice.h> 38#include <asm/unaligned.h> 39 40#include "iwl-eeprom.h" 41#include "iwl-dev.h" 42#include "iwl-core.h" 43#include "iwl-io.h" 44#include "iwl-helpers.h" 45#include "iwl-5000-hw.h" 46 47#define IWL5000_UCODE_API "-1" 48 49static const u16 iwl5000_default_queue_to_tx_fifo[] = { 50 IWL_TX_FIFO_AC3, 51 IWL_TX_FIFO_AC2, 52 IWL_TX_FIFO_AC1, 53 IWL_TX_FIFO_AC0, 54 IWL50_CMD_FIFO_NUM, 55 IWL_TX_FIFO_HCCA_1, 56 IWL_TX_FIFO_HCCA_2 57}; 58 59/* FIXME: same implementation as 4965 */ 60static int iwl5000_apm_stop_master(struct iwl_priv *priv) 61{ 62 int ret = 0; 63 unsigned long flags; 64 65 spin_lock_irqsave(&priv->lock, flags); 66 67 /* set stop master bit */ 68 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); 69 70 ret = iwl_poll_bit(priv, CSR_RESET, 71 CSR_RESET_REG_FLAG_MASTER_DISABLED, 72 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); 73 if (ret < 0) 74 goto out; 75 76out: 77 spin_unlock_irqrestore(&priv->lock, flags); 78 IWL_DEBUG_INFO("stop master\n"); 79 80 return ret; 81} 82 83 84static int iwl5000_apm_init(struct iwl_priv *priv) 85{ 86 int ret = 0; 87 88 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS, 89 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 90 91 /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */ 92 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS, 93 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 94 95 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); 96 97 /* set "initialization complete" bit to move adapter 98 * D0U* --> D0A* state */ 99 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 100 101 /* wait for clock stabilization */ 102 ret = iwl_poll_bit(priv, CSR_GP_CNTRL, 103 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 104 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); 105 if (ret < 0) { 106 IWL_DEBUG_INFO("Failed to init the card\n"); 107 return ret; 108 } 109 110 ret = iwl_grab_nic_access(priv); 111 if (ret) 112 return ret; 113 114 /* enable DMA */ 115 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT); 116 117 udelay(20); 118 119 /* disable L1-Active */ 120 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG, 121 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 122 123 iwl_release_nic_access(priv); 124 125 return ret; 126} 127 128/* FIXME: this is indentical to 4965 */ 129static void iwl5000_apm_stop(struct iwl_priv *priv) 130{ 131 unsigned long flags; 132 133 iwl5000_apm_stop_master(priv); 134 135 spin_lock_irqsave(&priv->lock, flags); 136 137 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 138 139 udelay(10); 140 141 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 142 143 spin_unlock_irqrestore(&priv->lock, flags); 144} 145 146 147static int iwl5000_apm_reset(struct iwl_priv *priv) 148{ 149 int ret = 0; 150 unsigned long flags; 151 152 iwl5000_apm_stop_master(priv); 153 154 spin_lock_irqsave(&priv->lock, flags); 155 156 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 157 158 udelay(10); 159 160 161 /* FIXME: put here L1A -L0S w/a */ 162 163 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); 164 165 /* set "initialization complete" bit to move adapter 166 * D0U* --> D0A* state */ 167 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 168 169 /* wait for clock stabilization */ 170 ret = iwl_poll_bit(priv, CSR_GP_CNTRL, 171 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 172 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); 173 if (ret < 0) { 174 IWL_DEBUG_INFO("Failed to init the card\n"); 175 goto out; 176 } 177 178 ret = iwl_grab_nic_access(priv); 179 if (ret) 180 goto out; 181 182 /* enable DMA */ 183 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT); 184 185 udelay(20); 186 187 /* disable L1-Active */ 188 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG, 189 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 190 191 iwl_release_nic_access(priv); 192 193out: 194 spin_unlock_irqrestore(&priv->lock, flags); 195 196 return ret; 197} 198 199 200static void iwl5000_nic_config(struct iwl_priv *priv) 201{ 202 unsigned long flags; 203 u16 radio_cfg; 204 u8 val_link; 205 206 spin_lock_irqsave(&priv->lock, flags); 207 208 pci_read_config_byte(priv->pci_dev, PCI_LINK_CTRL, &val_link); 209 210 /* L1 is enabled by BIOS */ 211 if ((val_link & PCI_LINK_VAL_L1_EN) == PCI_LINK_VAL_L1_EN) 212 /* diable L0S disabled L1A enabled */ 213 iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); 214 else 215 /* L0S enabled L1A disabled */ 216 iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); 217 218 radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG); 219 220 /* write radio config values to register */ 221 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_5000_RF_CFG_TYPE_MAX) 222 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, 223 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) | 224 EEPROM_RF_CFG_STEP_MSK(radio_cfg) | 225 EEPROM_RF_CFG_DASH_MSK(radio_cfg)); 226 227 /* set CSR_HW_CONFIG_REG for uCode use */ 228 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, 229 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI | 230 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI); 231 232 spin_unlock_irqrestore(&priv->lock, flags); 233} 234 235 236 237/* 238 * EEPROM 239 */ 240static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address) 241{ 242 u16 offset = 0; 243 244 if ((address & INDIRECT_ADDRESS) == 0) 245 return address; 246 247 switch (address & INDIRECT_TYPE_MSK) { 248 case INDIRECT_HOST: 249 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST); 250 break; 251 case INDIRECT_GENERAL: 252 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL); 253 break; 254 case INDIRECT_REGULATORY: 255 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY); 256 break; 257 case INDIRECT_CALIBRATION: 258 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION); 259 break; 260 case INDIRECT_PROCESS_ADJST: 261 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST); 262 break; 263 case INDIRECT_OTHERS: 264 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS); 265 break; 266 default: 267 IWL_ERROR("illegal indirect type: 0x%X\n", 268 address & INDIRECT_TYPE_MSK); 269 break; 270 } 271 272 /* translate the offset from words to byte */ 273 return (address & ADDRESS_MSK) + (offset << 1); 274} 275 276static int iwl5000_eeprom_check_version(struct iwl_priv *priv) 277{ 278 u16 eeprom_ver; 279 struct iwl_eeprom_calib_hdr { 280 u8 version; 281 u8 pa_type; 282 u16 voltage; 283 } *hdr; 284 285 eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION); 286 287 hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv, 288 EEPROM_5000_CALIB_ALL); 289 290 if (eeprom_ver < EEPROM_5000_EEPROM_VERSION || 291 hdr->version < EEPROM_5000_TX_POWER_VERSION) 292 goto err; 293 294 return 0; 295err: 296 IWL_ERROR("Unsuported EEPROM VER=0x%x < 0x%x CALIB=0x%x < 0x%x\n", 297 eeprom_ver, EEPROM_5000_EEPROM_VERSION, 298 hdr->version, EEPROM_5000_TX_POWER_VERSION); 299 return -EINVAL; 300 301} 302 303#ifdef CONFIG_IWL5000_RUN_TIME_CALIB 304 305static void iwl5000_gain_computation(struct iwl_priv *priv, 306 u32 average_noise[NUM_RX_CHAINS], 307 u16 min_average_noise_antenna_i, 308 u32 min_average_noise) 309{ 310 int i; 311 s32 delta_g; 312 struct iwl_chain_noise_data *data = &priv->chain_noise_data; 313 314 /* Find Gain Code for the antennas B and C */ 315 for (i = 1; i < NUM_RX_CHAINS; i++) { 316 if ((data->disconn_array[i])) { 317 data->delta_gain_code[i] = 0; 318 continue; 319 } 320 delta_g = (1000 * ((s32)average_noise[0] - 321 (s32)average_noise[i])) / 1500; 322 /* bound gain by 2 bits value max, 3rd bit is sign */ 323 data->delta_gain_code[i] = 324 min(abs(delta_g), CHAIN_NOISE_MAX_DELTA_GAIN_CODE); 325 326 if (delta_g < 0) 327 /* set negative sign */ 328 data->delta_gain_code[i] |= (1 << 2); 329 } 330 331 IWL_DEBUG_CALIB("Delta gains: ANT_B = %d ANT_C = %d\n", 332 data->delta_gain_code[1], data->delta_gain_code[2]); 333 334 if (!data->radio_write) { 335 struct iwl5000_calibration_chain_noise_gain_cmd cmd; 336 memset(&cmd, 0, sizeof(cmd)); 337 338 cmd.op_code = IWL5000_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD; 339 cmd.delta_gain_1 = data->delta_gain_code[1]; 340 cmd.delta_gain_2 = data->delta_gain_code[2]; 341 iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD, 342 sizeof(cmd), &cmd, NULL); 343 344 data->radio_write = 1; 345 data->state = IWL_CHAIN_NOISE_CALIBRATED; 346 } 347 348 data->chain_noise_a = 0; 349 data->chain_noise_b = 0; 350 data->chain_noise_c = 0; 351 data->chain_signal_a = 0; 352 data->chain_signal_b = 0; 353 data->chain_signal_c = 0; 354 data->beacon_count = 0; 355} 356 357 358static void iwl5000_chain_noise_reset(struct iwl_priv *priv) 359{ 360 struct iwl_chain_noise_data *data = &priv->chain_noise_data; 361 362 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) { 363 struct iwl5000_calibration_chain_noise_reset_cmd cmd; 364 365 memset(&cmd, 0, sizeof(cmd)); 366 cmd.op_code = IWL5000_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD; 367 if (iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD, 368 sizeof(cmd), &cmd)) 369 IWL_ERROR("Could not send REPLY_PHY_CALIBRATION_CMD\n"); 370 data->state = IWL_CHAIN_NOISE_ACCUMULATE; 371 IWL_DEBUG_CALIB("Run chain_noise_calibrate\n"); 372 } 373} 374 375static struct iwl_sensitivity_ranges iwl5000_sensitivity = { 376 .min_nrg_cck = 95, 377 .max_nrg_cck = 0, 378 .auto_corr_min_ofdm = 90, 379 .auto_corr_min_ofdm_mrc = 170, 380 .auto_corr_min_ofdm_x1 = 120, 381 .auto_corr_min_ofdm_mrc_x1 = 240, 382 383 .auto_corr_max_ofdm = 120, 384 .auto_corr_max_ofdm_mrc = 210, 385 .auto_corr_max_ofdm_x1 = 155, 386 .auto_corr_max_ofdm_mrc_x1 = 290, 387 388 .auto_corr_min_cck = 125, 389 .auto_corr_max_cck = 200, 390 .auto_corr_min_cck_mrc = 170, 391 .auto_corr_max_cck_mrc = 400, 392 .nrg_th_cck = 95, 393 .nrg_th_ofdm = 95, 394}; 395 396#endif /* CONFIG_IWL5000_RUN_TIME_CALIB */ 397 398 399 400static const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv, 401 size_t offset) 402{ 403 u32 address = eeprom_indirect_address(priv, offset); 404 BUG_ON(address >= priv->cfg->eeprom_size); 405 return &priv->eeprom[address]; 406} 407 408/* 409 * Calibration 410 */ 411static int iwl5000_send_Xtal_calib(struct iwl_priv *priv) 412{ 413 u16 *xtal_calib = (u16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_XTAL); 414 415 struct iwl5000_calibration cal_cmd = { 416 .op_code = IWL5000_PHY_CALIBRATE_CRYSTAL_FRQ_CMD, 417 .data = { 418 (u8)xtal_calib[0], 419 (u8)xtal_calib[1], 420 } 421 }; 422 423 return iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD, 424 sizeof(cal_cmd), &cal_cmd); 425} 426 427static int iwl5000_send_calib_results(struct iwl_priv *priv) 428{ 429 int ret = 0; 430 431 struct iwl_host_cmd hcmd = { 432 .id = REPLY_PHY_CALIBRATION_CMD, 433 .meta.flags = CMD_SIZE_HUGE, 434 }; 435 436 if (priv->calib_results.lo_res) { 437 hcmd.len = priv->calib_results.lo_res_len; 438 hcmd.data = priv->calib_results.lo_res; 439 ret = iwl_send_cmd_sync(priv, &hcmd); 440 441 if (ret) 442 goto err; 443 } 444 445 if (priv->calib_results.tx_iq_res) { 446 hcmd.len = priv->calib_results.tx_iq_res_len; 447 hcmd.data = priv->calib_results.tx_iq_res; 448 ret = iwl_send_cmd_sync(priv, &hcmd); 449 450 if (ret) 451 goto err; 452 } 453 454 if (priv->calib_results.tx_iq_perd_res) { 455 hcmd.len = priv->calib_results.tx_iq_perd_res_len; 456 hcmd.data = priv->calib_results.tx_iq_perd_res; 457 ret = iwl_send_cmd_sync(priv, &hcmd); 458 459 if (ret) 460 goto err; 461 } 462 463 return 0; 464err: 465 IWL_ERROR("Error %d\n", ret); 466 return ret; 467} 468 469static int iwl5000_send_calib_cfg(struct iwl_priv *priv) 470{ 471 struct iwl5000_calib_cfg_cmd calib_cfg_cmd; 472 struct iwl_host_cmd cmd = { 473 .id = CALIBRATION_CFG_CMD, 474 .len = sizeof(struct iwl5000_calib_cfg_cmd), 475 .data = &calib_cfg_cmd, 476 }; 477 478 memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd)); 479 calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL; 480 calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL; 481 calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL; 482 calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL; 483 484 return iwl_send_cmd(priv, &cmd); 485} 486 487static void iwl5000_rx_calib_result(struct iwl_priv *priv, 488 struct iwl_rx_mem_buffer *rxb) 489{ 490 struct iwl_rx_packet *pkt = (void *)rxb->skb->data; 491 struct iwl5000_calib_hdr *hdr = (struct iwl5000_calib_hdr *)pkt->u.raw; 492 int len = le32_to_cpu(pkt->len) & FH_RSCSR_FRAME_SIZE_MSK; 493 494 iwl_free_calib_results(priv); 495 496 /* reduce the size of the length field itself */ 497 len -= 4; 498 499 switch (hdr->op_code) { 500 case IWL5000_PHY_CALIBRATE_LO_CMD: 501 priv->calib_results.lo_res = kzalloc(len, GFP_ATOMIC); 502 priv->calib_results.lo_res_len = len; 503 memcpy(priv->calib_results.lo_res, pkt->u.raw, len); 504 break; 505 case IWL5000_PHY_CALIBRATE_TX_IQ_CMD: 506 priv->calib_results.tx_iq_res = kzalloc(len, GFP_ATOMIC); 507 priv->calib_results.tx_iq_res_len = len; 508 memcpy(priv->calib_results.tx_iq_res, pkt->u.raw, len); 509 break; 510 case IWL5000_PHY_CALIBRATE_TX_IQ_PERD_CMD: 511 priv->calib_results.tx_iq_perd_res = kzalloc(len, GFP_ATOMIC); 512 priv->calib_results.tx_iq_perd_res_len = len; 513 memcpy(priv->calib_results.tx_iq_perd_res, pkt->u.raw, len); 514 break; 515 default: 516 IWL_ERROR("Unknown calibration notification %d\n", 517 hdr->op_code); 518 return; 519 } 520} 521 522static void iwl5000_rx_calib_complete(struct iwl_priv *priv, 523 struct iwl_rx_mem_buffer *rxb) 524{ 525 IWL_DEBUG_INFO("Init. calibration is completed, restarting fw.\n"); 526 queue_work(priv->workqueue, &priv->restart); 527} 528 529/* 530 * ucode 531 */ 532static int iwl5000_load_section(struct iwl_priv *priv, 533 struct fw_desc *image, 534 u32 dst_addr) 535{ 536 int ret = 0; 537 unsigned long flags; 538 539 dma_addr_t phy_addr = image->p_addr; 540 u32 byte_cnt = image->len; 541 542 spin_lock_irqsave(&priv->lock, flags); 543 ret = iwl_grab_nic_access(priv); 544 if (ret) { 545 spin_unlock_irqrestore(&priv->lock, flags); 546 return ret; 547 } 548 549 iwl_write_direct32(priv, 550 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 551 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); 552 553 iwl_write_direct32(priv, 554 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr); 555 556 iwl_write_direct32(priv, 557 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), 558 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); 559 560 /* FIME: write the MSB of the phy_addr in CTRL1 561 * iwl_write_direct32(priv, 562 IWL_FH_TFDIB_CTRL1_REG(IWL_FH_SRVC_CHNL), 563 ((phy_addr & MSB_MSK) 564 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_count); 565 */ 566 iwl_write_direct32(priv, 567 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), byte_cnt); 568 iwl_write_direct32(priv, 569 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), 570 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM | 571 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX | 572 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); 573 574 iwl_write_direct32(priv, 575 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 576 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 577 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL | 578 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); 579 580 iwl_release_nic_access(priv); 581 spin_unlock_irqrestore(&priv->lock, flags); 582 return 0; 583} 584 585static int iwl5000_load_given_ucode(struct iwl_priv *priv, 586 struct fw_desc *inst_image, 587 struct fw_desc *data_image) 588{ 589 int ret = 0; 590 591 ret = iwl5000_load_section( 592 priv, inst_image, RTC_INST_LOWER_BOUND); 593 if (ret) 594 return ret; 595 596 IWL_DEBUG_INFO("INST uCode section being loaded...\n"); 597 ret = wait_event_interruptible_timeout(priv->wait_command_queue, 598 priv->ucode_write_complete, 5 * HZ); 599 if (ret == -ERESTARTSYS) { 600 IWL_ERROR("Could not load the INST uCode section due " 601 "to interrupt\n"); 602 return ret; 603 } 604 if (!ret) { 605 IWL_ERROR("Could not load the INST uCode section\n"); 606 return -ETIMEDOUT; 607 } 608 609 priv->ucode_write_complete = 0; 610 611 ret = iwl5000_load_section( 612 priv, data_image, RTC_DATA_LOWER_BOUND); 613 if (ret) 614 return ret; 615 616 IWL_DEBUG_INFO("DATA uCode section being loaded...\n"); 617 618 ret = wait_event_interruptible_timeout(priv->wait_command_queue, 619 priv->ucode_write_complete, 5 * HZ); 620 if (ret == -ERESTARTSYS) { 621 IWL_ERROR("Could not load the INST uCode section due " 622 "to interrupt\n"); 623 return ret; 624 } else if (!ret) { 625 IWL_ERROR("Could not load the DATA uCode section\n"); 626 return -ETIMEDOUT; 627 } else 628 ret = 0; 629 630 priv->ucode_write_complete = 0; 631 632 return ret; 633} 634 635static int iwl5000_load_ucode(struct iwl_priv *priv) 636{ 637 int ret = 0; 638 639 /* check whether init ucode should be loaded, or rather runtime ucode */ 640 if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) { 641 IWL_DEBUG_INFO("Init ucode found. Loading init ucode...\n"); 642 ret = iwl5000_load_given_ucode(priv, 643 &priv->ucode_init, &priv->ucode_init_data); 644 if (!ret) { 645 IWL_DEBUG_INFO("Init ucode load complete.\n"); 646 priv->ucode_type = UCODE_INIT; 647 } 648 } else { 649 IWL_DEBUG_INFO("Init ucode not found, or already loaded. " 650 "Loading runtime ucode...\n"); 651 ret = iwl5000_load_given_ucode(priv, 652 &priv->ucode_code, &priv->ucode_data); 653 if (!ret) { 654 IWL_DEBUG_INFO("Runtime ucode load complete.\n"); 655 priv->ucode_type = UCODE_RT; 656 } 657 } 658 659 return ret; 660} 661 662static void iwl5000_init_alive_start(struct iwl_priv *priv) 663{ 664 int ret = 0; 665 666 /* Check alive response for "valid" sign from uCode */ 667 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) { 668 /* We had an error bringing up the hardware, so take it 669 * all the way back down so we can try again */ 670 IWL_DEBUG_INFO("Initialize Alive failed.\n"); 671 goto restart; 672 } 673 674 /* initialize uCode was loaded... verify inst image. 675 * This is a paranoid check, because we would not have gotten the 676 * "initialize" alive if code weren't properly loaded. */ 677 if (iwl_verify_ucode(priv)) { 678 /* Runtime instruction load was bad; 679 * take it all the way back down so we can try again */ 680 IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n"); 681 goto restart; 682 } 683 684 iwlcore_clear_stations_table(priv); 685 ret = priv->cfg->ops->lib->alive_notify(priv); 686 if (ret) { 687 IWL_WARNING("Could not complete ALIVE transition: %d\n", ret); 688 goto restart; 689 } 690 691 iwl5000_send_calib_cfg(priv); 692 return; 693 694restart: 695 /* real restart (first load init_ucode) */ 696 queue_work(priv->workqueue, &priv->restart); 697} 698 699static void iwl5000_set_wr_ptrs(struct iwl_priv *priv, 700 int txq_id, u32 index) 701{ 702 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 703 (index & 0xff) | (txq_id << 8)); 704 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index); 705} 706 707static void iwl5000_tx_queue_set_status(struct iwl_priv *priv, 708 struct iwl_tx_queue *txq, 709 int tx_fifo_id, int scd_retry) 710{ 711 int txq_id = txq->q.id; 712 int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0; 713 714 iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id), 715 (active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) | 716 (tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) | 717 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) | 718 IWL50_SCD_QUEUE_STTS_REG_MSK); 719 720 txq->sched_retry = scd_retry; 721 722 IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n", 723 active ? "Activate" : "Deactivate", 724 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id); 725} 726 727static int iwl5000_send_wimax_coex(struct iwl_priv *priv) 728{ 729 struct iwl_wimax_coex_cmd coex_cmd; 730 731 memset(&coex_cmd, 0, sizeof(coex_cmd)); 732 733 return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD, 734 sizeof(coex_cmd), &coex_cmd); 735} 736 737static int iwl5000_alive_notify(struct iwl_priv *priv) 738{ 739 u32 a; 740 int i = 0; 741 unsigned long flags; 742 int ret; 743 744 spin_lock_irqsave(&priv->lock, flags); 745 746 ret = iwl_grab_nic_access(priv); 747 if (ret) { 748 spin_unlock_irqrestore(&priv->lock, flags); 749 return ret; 750 } 751 752 priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR); 753 a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET; 754 for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET; 755 a += 4) 756 iwl_write_targ_mem(priv, a, 0); 757 for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET; 758 a += 4) 759 iwl_write_targ_mem(priv, a, 0); 760 for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4) 761 iwl_write_targ_mem(priv, a, 0); 762 763 iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR, 764 (priv->shared_phys + 765 offsetof(struct iwl5000_shared, queues_byte_cnt_tbls)) >> 10); 766 iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, 767 IWL50_SCD_QUEUECHAIN_SEL_ALL( 768 priv->hw_params.max_txq_num)); 769 iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0); 770 771 /* initiate the queues */ 772 for (i = 0; i < priv->hw_params.max_txq_num; i++) { 773 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0); 774 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8)); 775 iwl_write_targ_mem(priv, priv->scd_base_addr + 776 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0); 777 iwl_write_targ_mem(priv, priv->scd_base_addr + 778 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) + 779 sizeof(u32), 780 ((SCD_WIN_SIZE << 781 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & 782 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | 783 ((SCD_FRAME_LIMIT << 784 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & 785 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); 786 } 787 788 iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK, 789 IWL_MASK(0, priv->hw_params.max_txq_num)); 790 791 /* Activate all Tx DMA/FIFO channels */ 792 priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7)); 793 794 iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0); 795 /* map qos queues to fifos one-to-one */ 796 for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) { 797 int ac = iwl5000_default_queue_to_tx_fifo[i]; 798 iwl_txq_ctx_activate(priv, i); 799 iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0); 800 } 801 /* TODO - need to initialize those FIFOs inside the loop above, 802 * not only mark them as active */ 803 iwl_txq_ctx_activate(priv, 4); 804 iwl_txq_ctx_activate(priv, 7); 805 iwl_txq_ctx_activate(priv, 8); 806 iwl_txq_ctx_activate(priv, 9); 807 808 iwl_release_nic_access(priv); 809 spin_unlock_irqrestore(&priv->lock, flags); 810 811 812 iwl5000_send_wimax_coex(priv); 813 814 iwl5000_send_Xtal_calib(priv); 815 816 if (priv->ucode_type == UCODE_RT) { 817 iwl5000_send_calib_results(priv); 818 set_bit(STATUS_READY, &priv->status); 819 priv->is_open = 1; 820 } 821 822 return 0; 823} 824 825static int iwl5000_hw_set_hw_params(struct iwl_priv *priv) 826{ 827 if ((priv->cfg->mod_params->num_of_queues > IWL50_NUM_QUEUES) || 828 (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) { 829 IWL_ERROR("invalid queues_num, should be between %d and %d\n", 830 IWL_MIN_NUM_QUEUES, IWL50_NUM_QUEUES); 831 return -EINVAL; 832 } 833 834 priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues; 835 priv->hw_params.sw_crypto = priv->cfg->mod_params->sw_crypto; 836 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE; 837 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG; 838 if (priv->cfg->mod_params->amsdu_size_8K) 839 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_8K; 840 else 841 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_4K; 842 priv->hw_params.max_pkt_size = priv->hw_params.rx_buf_size - 256; 843 priv->hw_params.max_stations = IWL5000_STATION_COUNT; 844 priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID; 845 priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE; 846 priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE; 847 priv->hw_params.max_bsm_size = BSM_SRAM_SIZE; 848 priv->hw_params.fat_channel = BIT(IEEE80211_BAND_2GHZ) | 849 BIT(IEEE80211_BAND_5GHZ); 850#ifdef CONFIG_IWL5000_RUN_TIME_CALIB 851 priv->hw_params.sens = &iwl5000_sensitivity; 852#endif 853 854 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) { 855 case CSR_HW_REV_TYPE_5100: 856 case CSR_HW_REV_TYPE_5150: 857 priv->hw_params.tx_chains_num = 1; 858 priv->hw_params.rx_chains_num = 2; 859 /* FIXME: move to ANT_A, ANT_B, ANT_C enum */ 860 priv->hw_params.valid_tx_ant = ANT_A; 861 priv->hw_params.valid_rx_ant = ANT_AB; 862 break; 863 case CSR_HW_REV_TYPE_5300: 864 case CSR_HW_REV_TYPE_5350: 865 priv->hw_params.tx_chains_num = 3; 866 priv->hw_params.rx_chains_num = 3; 867 priv->hw_params.valid_tx_ant = ANT_ABC; 868 priv->hw_params.valid_rx_ant = ANT_ABC; 869 break; 870 } 871 872 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) { 873 case CSR_HW_REV_TYPE_5100: 874 case CSR_HW_REV_TYPE_5300: 875 /* 5X00 wants in Celsius */ 876 priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD; 877 break; 878 case CSR_HW_REV_TYPE_5150: 879 case CSR_HW_REV_TYPE_5350: 880 /* 5X50 wants in Kelvin */ 881 priv->hw_params.ct_kill_threshold = 882 CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD); 883 break; 884 } 885 886 return 0; 887} 888 889static int iwl5000_alloc_shared_mem(struct iwl_priv *priv) 890{ 891 priv->shared_virt = pci_alloc_consistent(priv->pci_dev, 892 sizeof(struct iwl5000_shared), 893 &priv->shared_phys); 894 if (!priv->shared_virt) 895 return -ENOMEM; 896 897 memset(priv->shared_virt, 0, sizeof(struct iwl5000_shared)); 898 899 priv->rb_closed_offset = offsetof(struct iwl5000_shared, rb_closed); 900 901 return 0; 902} 903 904static void iwl5000_free_shared_mem(struct iwl_priv *priv) 905{ 906 if (priv->shared_virt) 907 pci_free_consistent(priv->pci_dev, 908 sizeof(struct iwl5000_shared), 909 priv->shared_virt, 910 priv->shared_phys); 911} 912 913static int iwl5000_shared_mem_rx_idx(struct iwl_priv *priv) 914{ 915 struct iwl5000_shared *s = priv->shared_virt; 916 return le32_to_cpu(s->rb_closed) & 0xFFF; 917} 918 919/** 920 * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array 921 */ 922static void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv, 923 struct iwl_tx_queue *txq, 924 u16 byte_cnt) 925{ 926 struct iwl5000_shared *shared_data = priv->shared_virt; 927 int txq_id = txq->q.id; 928 u8 sec_ctl = 0; 929 u8 sta = 0; 930 int len; 931 932 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE; 933 934 if (txq_id != IWL_CMD_QUEUE_NUM) { 935 sta = txq->cmd[txq->q.write_ptr].cmd.tx.sta_id; 936 sec_ctl = txq->cmd[txq->q.write_ptr].cmd.tx.sec_ctl; 937 938 switch (sec_ctl & TX_CMD_SEC_MSK) { 939 case TX_CMD_SEC_CCM: 940 len += CCMP_MIC_LEN; 941 break; 942 case TX_CMD_SEC_TKIP: 943 len += TKIP_ICV_LEN; 944 break; 945 case TX_CMD_SEC_WEP: 946 len += WEP_IV_LEN + WEP_ICV_LEN; 947 break; 948 } 949 } 950 951 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id]. 952 tfd_offset[txq->q.write_ptr], byte_cnt, len); 953 954 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id]. 955 tfd_offset[txq->q.write_ptr], sta_id, sta); 956 957 if (txq->q.write_ptr < IWL50_MAX_WIN_SIZE) { 958 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id]. 959 tfd_offset[IWL50_QUEUE_SIZE + txq->q.write_ptr], 960 byte_cnt, len); 961 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id]. 962 tfd_offset[IWL50_QUEUE_SIZE + txq->q.write_ptr], 963 sta_id, sta); 964 } 965} 966 967static void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv, 968 struct iwl_tx_queue *txq) 969{ 970 int txq_id = txq->q.id; 971 struct iwl5000_shared *shared_data = priv->shared_virt; 972 u8 sta = 0; 973 974 if (txq_id != IWL_CMD_QUEUE_NUM) 975 sta = txq->cmd[txq->q.read_ptr].cmd.tx.sta_id; 976 977 shared_data->queues_byte_cnt_tbls[txq_id].tfd_offset[txq->q.read_ptr]. 978 val = cpu_to_le16(1 | (sta << 12)); 979 980 if (txq->q.write_ptr < IWL50_MAX_WIN_SIZE) { 981 shared_data->queues_byte_cnt_tbls[txq_id]. 982 tfd_offset[IWL50_QUEUE_SIZE + txq->q.read_ptr]. 983 val = cpu_to_le16(1 | (sta << 12)); 984 } 985} 986 987static u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data) 988{ 989 u16 size = (u16)sizeof(struct iwl_addsta_cmd); 990 memcpy(data, cmd, size); 991 return size; 992} 993 994 995/* 996 * Activate/Deactivat Tx DMA/FIFO channels according tx fifos mask 997 * must be called under priv->lock and mac access 998 */ 999static void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask) 1000{ 1001 iwl_write_prph(priv, IWL50_SCD_TXFACT, mask); 1002} 1003 1004 1005static inline u32 iwl5000_get_scd_ssn(struct iwl5000_tx_resp *tx_resp) 1006{ 1007 __le32 *scd_ssn = (__le32 *)((u32 *)&tx_resp->status + 1008 tx_resp->frame_count); 1009 return le32_to_cpu(*scd_ssn) & MAX_SN; 1010 1011} 1012 1013static int iwl5000_tx_status_reply_tx(struct iwl_priv *priv, 1014 struct iwl_ht_agg *agg, 1015 struct iwl5000_tx_resp *tx_resp, 1016 u16 start_idx) 1017{ 1018 u16 status; 1019 struct agg_tx_status *frame_status = &tx_resp->status; 1020 struct ieee80211_tx_info *info = NULL; 1021 struct ieee80211_hdr *hdr = NULL; 1022 int i, sh; 1023 int txq_id, idx; 1024 u16 seq; 1025 1026 if (agg->wait_for_ba) 1027 IWL_DEBUG_TX_REPLY("got tx response w/o block-ack\n"); 1028 1029 agg->frame_count = tx_resp->frame_count; 1030 agg->start_idx = start_idx; 1031 agg->rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags); 1032 agg->bitmap = 0; 1033 1034 /* # frames attempted by Tx command */ 1035 if (agg->frame_count == 1) { 1036 /* Only one frame was attempted; no block-ack will arrive */ 1037 status = le16_to_cpu(frame_status[0].status); 1038 seq = le16_to_cpu(frame_status[0].sequence); 1039 idx = SEQ_TO_INDEX(seq); 1040 txq_id = SEQ_TO_QUEUE(seq); 1041 1042 /* FIXME: code repetition */ 1043 IWL_DEBUG_TX_REPLY("FrameCnt = %d, StartIdx=%d idx=%d\n", 1044 agg->frame_count, agg->start_idx, idx); 1045 1046 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]); 1047 info->status.retry_count = tx_resp->failure_frame; 1048 info->flags &= ~IEEE80211_TX_CTL_AMPDU; 1049 info->flags |= iwl_is_tx_success(status)? 1050 IEEE80211_TX_STAT_ACK : 0; 1051 iwl4965_hwrate_to_tx_control(priv, 1052 le32_to_cpu(tx_resp->rate_n_flags), 1053 info); 1054 /* FIXME: code repetition end */ 1055 1056 IWL_DEBUG_TX_REPLY("1 Frame 0x%x failure :%d\n", 1057 status & 0xff, tx_resp->failure_frame); 1058 IWL_DEBUG_TX_REPLY("Rate Info rate_n_flags=%x\n", 1059 iwl4965_hw_get_rate_n_flags(tx_resp->rate_n_flags)); 1060 1061 agg->wait_for_ba = 0; 1062 } else { 1063 /* Two or more frames were attempted; expect block-ack */ 1064 u64 bitmap = 0; 1065 int start = agg->start_idx; 1066 1067 /* Construct bit-map of pending frames within Tx window */ 1068 for (i = 0; i < agg->frame_count; i++) { 1069 u16 sc; 1070 status = le16_to_cpu(frame_status[i].status); 1071 seq = le16_to_cpu(frame_status[i].sequence); 1072 idx = SEQ_TO_INDEX(seq); 1073 txq_id = SEQ_TO_QUEUE(seq); 1074 1075 if (status & (AGG_TX_STATE_FEW_BYTES_MSK | 1076 AGG_TX_STATE_ABORT_MSK)) 1077 continue; 1078 1079 IWL_DEBUG_TX_REPLY("FrameCnt = %d, txq_id=%d idx=%d\n", 1080 agg->frame_count, txq_id, idx); 1081 1082 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx); 1083 1084 sc = le16_to_cpu(hdr->seq_ctrl); 1085 if (idx != (SEQ_TO_SN(sc) & 0xff)) { 1086 IWL_ERROR("BUG_ON idx doesn't match seq control" 1087 " idx=%d, seq_idx=%d, seq=%d\n", 1088 idx, SEQ_TO_SN(sc), 1089 hdr->seq_ctrl); 1090 return -1; 1091 } 1092 1093 IWL_DEBUG_TX_REPLY("AGG Frame i=%d idx %d seq=%d\n", 1094 i, idx, SEQ_TO_SN(sc)); 1095 1096 sh = idx - start; 1097 if (sh > 64) { 1098 sh = (start - idx) + 0xff; 1099 bitmap = bitmap << sh; 1100 sh = 0; 1101 start = idx; 1102 } else if (sh < -64) 1103 sh = 0xff - (start - idx); 1104 else if (sh < 0) { 1105 sh = start - idx; 1106 start = idx; 1107 bitmap = bitmap << sh; 1108 sh = 0; 1109 } 1110 bitmap |= (1 << sh); 1111 IWL_DEBUG_TX_REPLY("start=%d bitmap=0x%x\n", 1112 start, (u32)(bitmap & 0xFFFFFFFF)); 1113 } 1114 1115 agg->bitmap = bitmap; 1116 agg->start_idx = start; 1117 agg->rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags); 1118 IWL_DEBUG_TX_REPLY("Frames %d start_idx=%d bitmap=0x%llx\n", 1119 agg->frame_count, agg->start_idx, 1120 (unsigned long long)agg->bitmap); 1121 1122 if (bitmap) 1123 agg->wait_for_ba = 1; 1124 } 1125 return 0; 1126} 1127 1128static void iwl5000_rx_reply_tx(struct iwl_priv *priv, 1129 struct iwl_rx_mem_buffer *rxb) 1130{ 1131 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; 1132 u16 sequence = le16_to_cpu(pkt->hdr.sequence); 1133 int txq_id = SEQ_TO_QUEUE(sequence); 1134 int index = SEQ_TO_INDEX(sequence); 1135 struct iwl_tx_queue *txq = &priv->txq[txq_id]; 1136 struct ieee80211_tx_info *info; 1137 struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0]; 1138 u32 status = le16_to_cpu(tx_resp->status.status); 1139#ifdef CONFIG_IWL4965_HT 1140 int tid = MAX_TID_COUNT, sta_id = IWL_INVALID_STATION; 1141 u16 fc; 1142 struct ieee80211_hdr *hdr; 1143 u8 *qc = NULL; 1144#endif 1145 1146 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) { 1147 IWL_ERROR("Read index for DMA queue txq_id (%d) index %d " 1148 "is out of range [0-%d] %d %d\n", txq_id, 1149 index, txq->q.n_bd, txq->q.write_ptr, 1150 txq->q.read_ptr); 1151 return; 1152 } 1153 1154 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]); 1155 memset(&info->status, 0, sizeof(info->status)); 1156 1157#ifdef CONFIG_IWL4965_HT 1158 hdr = iwl_tx_queue_get_hdr(priv, txq_id, index); 1159 fc = le16_to_cpu(hdr->frame_control); 1160 if (ieee80211_is_qos_data(fc)) { 1161 qc = ieee80211_get_qos_ctrl(hdr, ieee80211_get_hdrlen(fc)); 1162 tid = qc[0] & 0xf; 1163 } 1164 1165 sta_id = iwl_get_ra_sta_id(priv, hdr); 1166 if (txq->sched_retry && unlikely(sta_id == IWL_INVALID_STATION)) { 1167 IWL_ERROR("Station not known\n"); 1168 return; 1169 } 1170 1171 if (txq->sched_retry) { 1172 const u32 scd_ssn = iwl5000_get_scd_ssn(tx_resp); 1173 struct iwl_ht_agg *agg = NULL; 1174 1175 if (!qc) 1176 return; 1177 1178 agg = &priv->stations[sta_id].tid[tid].agg; 1179 1180 iwl5000_tx_status_reply_tx(priv, agg, tx_resp, index); 1181 1182 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status)) { 1183 /* TODO: send BAR */ 1184 } 1185 1186 if (txq->q.read_ptr != (scd_ssn & 0xff)) { 1187 int freed, ampdu_q; 1188 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd); 1189 IWL_DEBUG_TX_REPLY("Retry scheduler reclaim scd_ssn " 1190 "%d index %d\n", scd_ssn , index); 1191 freed = iwl_tx_queue_reclaim(priv, txq_id, index); 1192 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed; 1193 1194 if (iwl_queue_space(&txq->q) > txq->q.low_mark && 1195 txq_id >= 0 && priv->mac80211_registered && 1196 agg->state != IWL_EMPTYING_HW_QUEUE_DELBA) { 1197 /* calculate mac80211 ampdu sw queue to wake */ 1198 ampdu_q = txq_id - IWL_BACK_QUEUE_FIRST_ID + 1199 priv->hw->queues; 1200 if (agg->state == IWL_AGG_OFF) 1201 ieee80211_wake_queue(priv->hw, txq_id); 1202 else 1203 ieee80211_wake_queue(priv->hw, ampdu_q); 1204 } 1205 iwl_txq_check_empty(priv, sta_id, tid, txq_id); 1206 } 1207 } else { 1208#endif /* CONFIG_IWL4965_HT */ 1209 1210 info->status.retry_count = tx_resp->failure_frame; 1211 info->flags = iwl_is_tx_success(status) ? IEEE80211_TX_STAT_ACK : 0; 1212 iwl4965_hwrate_to_tx_control(priv, le32_to_cpu(tx_resp->rate_n_flags), 1213 info); 1214 1215 IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) rate_n_flags 0x%x " 1216 "retries %d\n", txq_id, iwl_get_tx_fail_reason(status), 1217 status, le32_to_cpu(tx_resp->rate_n_flags), 1218 tx_resp->failure_frame); 1219 1220 IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index); 1221#ifdef CONFIG_IWL4965_HT 1222 if (index != -1) { 1223 int freed = iwl_tx_queue_reclaim(priv, txq_id, index); 1224 if (tid != MAX_TID_COUNT) 1225 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed; 1226 if (iwl_queue_space(&txq->q) > txq->q.low_mark && 1227 (txq_id >= 0) && priv->mac80211_registered) 1228 ieee80211_wake_queue(priv->hw, txq_id); 1229 if (tid != MAX_TID_COUNT) 1230 iwl_txq_check_empty(priv, sta_id, tid, txq_id); 1231 } 1232 } 1233#endif /* CONFIG_IWL4965_HT */ 1234 1235 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK)) 1236 IWL_ERROR("TODO: Implement Tx ABORT REQUIRED!!!\n"); 1237} 1238 1239/* Currently 5000 is the supperset of everything */ 1240static u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len) 1241{ 1242 return len; 1243} 1244 1245static void iwl5000_rx_handler_setup(struct iwl_priv *priv) 1246{ 1247 /* init calibration handlers */ 1248 priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] = 1249 iwl5000_rx_calib_result; 1250 priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] = 1251 iwl5000_rx_calib_complete; 1252 priv->rx_handlers[REPLY_TX] = iwl5000_rx_reply_tx; 1253} 1254 1255 1256static int iwl5000_hw_valid_rtc_data_addr(u32 addr) 1257{ 1258 return (addr >= RTC_DATA_LOWER_BOUND) && 1259 (addr < IWL50_RTC_DATA_UPPER_BOUND); 1260} 1261 1262static int iwl5000_send_rxon_assoc(struct iwl_priv *priv) 1263{ 1264 int ret = 0; 1265 struct iwl5000_rxon_assoc_cmd rxon_assoc; 1266 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon; 1267 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon; 1268 1269 if ((rxon1->flags == rxon2->flags) && 1270 (rxon1->filter_flags == rxon2->filter_flags) && 1271 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) && 1272 (rxon1->ofdm_ht_single_stream_basic_rates == 1273 rxon2->ofdm_ht_single_stream_basic_rates) && 1274 (rxon1->ofdm_ht_dual_stream_basic_rates == 1275 rxon2->ofdm_ht_dual_stream_basic_rates) && 1276 (rxon1->ofdm_ht_triple_stream_basic_rates == 1277 rxon2->ofdm_ht_triple_stream_basic_rates) && 1278 (rxon1->acquisition_data == rxon2->acquisition_data) && 1279 (rxon1->rx_chain == rxon2->rx_chain) && 1280 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) { 1281 IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n"); 1282 return 0; 1283 } 1284 1285 rxon_assoc.flags = priv->staging_rxon.flags; 1286 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags; 1287 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates; 1288 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates; 1289 rxon_assoc.reserved1 = 0; 1290 rxon_assoc.reserved2 = 0; 1291 rxon_assoc.reserved3 = 0; 1292 rxon_assoc.ofdm_ht_single_stream_basic_rates = 1293 priv->staging_rxon.ofdm_ht_single_stream_basic_rates; 1294 rxon_assoc.ofdm_ht_dual_stream_basic_rates = 1295 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates; 1296 rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain; 1297 rxon_assoc.ofdm_ht_triple_stream_basic_rates = 1298 priv->staging_rxon.ofdm_ht_triple_stream_basic_rates; 1299 rxon_assoc.acquisition_data = priv->staging_rxon.acquisition_data; 1300 1301 ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC, 1302 sizeof(rxon_assoc), &rxon_assoc, NULL); 1303 if (ret) 1304 return ret; 1305 1306 return ret; 1307} 1308 1309static struct iwl_hcmd_ops iwl5000_hcmd = { 1310 .rxon_assoc = iwl5000_send_rxon_assoc, 1311}; 1312 1313static struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = { 1314 .get_hcmd_size = iwl5000_get_hcmd_size, 1315 .build_addsta_hcmd = iwl5000_build_addsta_hcmd, 1316#ifdef CONFIG_IWL5000_RUN_TIME_CALIB 1317 .gain_computation = iwl5000_gain_computation, 1318 .chain_noise_reset = iwl5000_chain_noise_reset, 1319#endif 1320}; 1321 1322static struct iwl_lib_ops iwl5000_lib = { 1323 .set_hw_params = iwl5000_hw_set_hw_params, 1324 .alloc_shared_mem = iwl5000_alloc_shared_mem, 1325 .free_shared_mem = iwl5000_free_shared_mem, 1326 .shared_mem_rx_idx = iwl5000_shared_mem_rx_idx, 1327 .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl, 1328 .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl, 1329 .txq_set_sched = iwl5000_txq_set_sched, 1330 .rx_handler_setup = iwl5000_rx_handler_setup, 1331 .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr, 1332 .load_ucode = iwl5000_load_ucode, 1333 .init_alive_start = iwl5000_init_alive_start, 1334 .alive_notify = iwl5000_alive_notify, 1335 .apm_ops = { 1336 .init = iwl5000_apm_init, 1337 .reset = iwl5000_apm_reset, 1338 .stop = iwl5000_apm_stop, 1339 .config = iwl5000_nic_config, 1340 .set_pwr_src = iwl4965_set_pwr_src, 1341 }, 1342 .eeprom_ops = { 1343 .regulatory_bands = { 1344 EEPROM_5000_REG_BAND_1_CHANNELS, 1345 EEPROM_5000_REG_BAND_2_CHANNELS, 1346 EEPROM_5000_REG_BAND_3_CHANNELS, 1347 EEPROM_5000_REG_BAND_4_CHANNELS, 1348 EEPROM_5000_REG_BAND_5_CHANNELS, 1349 EEPROM_5000_REG_BAND_24_FAT_CHANNELS, 1350 EEPROM_5000_REG_BAND_52_FAT_CHANNELS 1351 }, 1352 .verify_signature = iwlcore_eeprom_verify_signature, 1353 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore, 1354 .release_semaphore = iwlcore_eeprom_release_semaphore, 1355 .check_version = iwl5000_eeprom_check_version, 1356 .query_addr = iwl5000_eeprom_query_addr, 1357 }, 1358}; 1359 1360static struct iwl_ops iwl5000_ops = { 1361 .lib = &iwl5000_lib, 1362 .hcmd = &iwl5000_hcmd, 1363 .utils = &iwl5000_hcmd_utils, 1364}; 1365 1366static struct iwl_mod_params iwl50_mod_params = { 1367 .num_of_queues = IWL50_NUM_QUEUES, 1368 .enable_qos = 1, 1369 .amsdu_size_8K = 1, 1370 .restart_fw = 1, 1371 /* the rest are 0 by default */ 1372}; 1373 1374 1375struct iwl_cfg iwl5300_agn_cfg = { 1376 .name = "5300AGN", 1377 .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode", 1378 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N, 1379 .ops = &iwl5000_ops, 1380 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, 1381 .mod_params = &iwl50_mod_params, 1382}; 1383 1384struct iwl_cfg iwl5100_agn_cfg = { 1385 .name = "5100AGN", 1386 .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode", 1387 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N, 1388 .ops = &iwl5000_ops, 1389 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, 1390 .mod_params = &iwl50_mod_params, 1391}; 1392 1393struct iwl_cfg iwl5350_agn_cfg = { 1394 .name = "5350AGN", 1395 .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode", 1396 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N, 1397 .ops = &iwl5000_ops, 1398 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, 1399 .mod_params = &iwl50_mod_params, 1400}; 1401 1402module_param_named(disable50, iwl50_mod_params.disable, int, 0444); 1403MODULE_PARM_DESC(disable50, 1404 "manually disable the 50XX radio (default 0 [radio on])"); 1405module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, 0444); 1406MODULE_PARM_DESC(swcrypto50, 1407 "using software crypto engine (default 0 [hardware])\n"); 1408module_param_named(debug50, iwl50_mod_params.debug, int, 0444); 1409MODULE_PARM_DESC(debug50, "50XX debug output mask"); 1410module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, 0444); 1411MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series"); 1412module_param_named(qos_enable50, iwl50_mod_params.enable_qos, int, 0444); 1413MODULE_PARM_DESC(qos_enable50, "enable all 50XX QoS functionality"); 1414module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K, int, 0444); 1415MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series"); 1416module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, 0444); 1417MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error"); 1418