iwl-5000.c revision d68b603cf01a6e7d8c85c5a86db751ed3960c0c7
1/****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2009 Intel Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * The full GNU General Public License is included in this distribution in the 19 * file called LICENSE. 20 * 21 * Contact Information: 22 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 23 * 24 *****************************************************************************/ 25 26#include <linux/kernel.h> 27#include <linux/module.h> 28#include <linux/init.h> 29#include <linux/pci.h> 30#include <linux/dma-mapping.h> 31#include <linux/delay.h> 32#include <linux/skbuff.h> 33#include <linux/netdevice.h> 34#include <linux/wireless.h> 35#include <net/mac80211.h> 36#include <linux/etherdevice.h> 37#include <asm/unaligned.h> 38 39#include "iwl-eeprom.h" 40#include "iwl-dev.h" 41#include "iwl-core.h" 42#include "iwl-io.h" 43#include "iwl-sta.h" 44#include "iwl-helpers.h" 45#include "iwl-agn-led.h" 46#include "iwl-5000-hw.h" 47#include "iwl-6000-hw.h" 48 49/* Highest firmware API version supported */ 50#define IWL5000_UCODE_API_MAX 2 51#define IWL5150_UCODE_API_MAX 2 52 53/* Lowest firmware API version supported */ 54#define IWL5000_UCODE_API_MIN 1 55#define IWL5150_UCODE_API_MIN 1 56 57#define IWL5000_FW_PRE "iwlwifi-5000-" 58#define _IWL5000_MODULE_FIRMWARE(api) IWL5000_FW_PRE #api ".ucode" 59#define IWL5000_MODULE_FIRMWARE(api) _IWL5000_MODULE_FIRMWARE(api) 60 61#define IWL5150_FW_PRE "iwlwifi-5150-" 62#define _IWL5150_MODULE_FIRMWARE(api) IWL5150_FW_PRE #api ".ucode" 63#define IWL5150_MODULE_FIRMWARE(api) _IWL5150_MODULE_FIRMWARE(api) 64 65static const u16 iwl5000_default_queue_to_tx_fifo[] = { 66 IWL_TX_FIFO_AC3, 67 IWL_TX_FIFO_AC2, 68 IWL_TX_FIFO_AC1, 69 IWL_TX_FIFO_AC0, 70 IWL50_CMD_FIFO_NUM, 71 IWL_TX_FIFO_HCCA_1, 72 IWL_TX_FIFO_HCCA_2 73}; 74 75int iwl5000_apm_init(struct iwl_priv *priv) 76{ 77 int ret = 0; 78 79 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS, 80 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 81 82 /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */ 83 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS, 84 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 85 86 /* Set FH wait threshold to maximum (HW error during stress W/A) */ 87 iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); 88 89 /* enable HAP INTA to move device L1a -> L0s */ 90 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, 91 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); 92 93 if (priv->cfg->need_pll_cfg) 94 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); 95 96 /* set "initialization complete" bit to move adapter 97 * D0U* --> D0A* state */ 98 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 99 100 /* wait for clock stabilization */ 101 ret = iwl_poll_direct_bit(priv, CSR_GP_CNTRL, 102 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); 103 if (ret < 0) { 104 IWL_DEBUG_INFO(priv, "Failed to init the card\n"); 105 return ret; 106 } 107 108 /* enable DMA */ 109 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT); 110 111 udelay(20); 112 113 /* disable L1-Active */ 114 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG, 115 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 116 117 return ret; 118} 119 120int iwl5000_apm_reset(struct iwl_priv *priv) 121{ 122 int ret = 0; 123 124 iwl_apm_stop_master(priv); 125 126 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 127 128 udelay(10); 129 130 131 /* FIXME: put here L1A -L0S w/a */ 132 133 if (priv->cfg->need_pll_cfg) 134 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); 135 136 /* set "initialization complete" bit to move adapter 137 * D0U* --> D0A* state */ 138 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 139 140 /* wait for clock stabilization */ 141 ret = iwl_poll_direct_bit(priv, CSR_GP_CNTRL, 142 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); 143 if (ret < 0) { 144 IWL_DEBUG_INFO(priv, "Failed to init the card\n"); 145 goto out; 146 } 147 148 /* enable DMA */ 149 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT); 150 151 udelay(20); 152 153 /* disable L1-Active */ 154 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG, 155 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 156out: 157 158 return ret; 159} 160 161 162/* NIC configuration for 5000 series */ 163void iwl5000_nic_config(struct iwl_priv *priv) 164{ 165 unsigned long flags; 166 u16 radio_cfg; 167 u16 lctl; 168 169 spin_lock_irqsave(&priv->lock, flags); 170 171 lctl = iwl_pcie_link_ctl(priv); 172 173 /* HW bug W/A */ 174 /* L1-ASPM is enabled by BIOS */ 175 if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) == PCI_CFG_LINK_CTRL_VAL_L1_EN) 176 /* L1-APSM enabled: disable L0S */ 177 iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); 178 else 179 /* L1-ASPM disabled: enable L0S */ 180 iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); 181 182 radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG); 183 184 /* write radio config values to register */ 185 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_RF_CONFIG_TYPE_MAX) 186 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, 187 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) | 188 EEPROM_RF_CFG_STEP_MSK(radio_cfg) | 189 EEPROM_RF_CFG_DASH_MSK(radio_cfg)); 190 191 /* set CSR_HW_CONFIG_REG for uCode use */ 192 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, 193 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI | 194 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI); 195 196 /* W/A : NIC is stuck in a reset state after Early PCIe power off 197 * (PCIe power is lost before PERST# is asserted), 198 * causing ME FW to lose ownership and not being able to obtain it back. 199 */ 200 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, 201 APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS, 202 ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS); 203 204 205 spin_unlock_irqrestore(&priv->lock, flags); 206} 207 208 209/* 210 * EEPROM 211 */ 212static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address) 213{ 214 u16 offset = 0; 215 216 if ((address & INDIRECT_ADDRESS) == 0) 217 return address; 218 219 switch (address & INDIRECT_TYPE_MSK) { 220 case INDIRECT_HOST: 221 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST); 222 break; 223 case INDIRECT_GENERAL: 224 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL); 225 break; 226 case INDIRECT_REGULATORY: 227 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY); 228 break; 229 case INDIRECT_CALIBRATION: 230 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION); 231 break; 232 case INDIRECT_PROCESS_ADJST: 233 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST); 234 break; 235 case INDIRECT_OTHERS: 236 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS); 237 break; 238 default: 239 IWL_ERR(priv, "illegal indirect type: 0x%X\n", 240 address & INDIRECT_TYPE_MSK); 241 break; 242 } 243 244 /* translate the offset from words to byte */ 245 return (address & ADDRESS_MSK) + (offset << 1); 246} 247 248u16 iwl5000_eeprom_calib_version(struct iwl_priv *priv) 249{ 250 struct iwl_eeprom_calib_hdr { 251 u8 version; 252 u8 pa_type; 253 u16 voltage; 254 } *hdr; 255 256 hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv, 257 EEPROM_5000_CALIB_ALL); 258 return hdr->version; 259 260} 261 262static void iwl5000_gain_computation(struct iwl_priv *priv, 263 u32 average_noise[NUM_RX_CHAINS], 264 u16 min_average_noise_antenna_i, 265 u32 min_average_noise, 266 u8 default_chain) 267{ 268 int i; 269 s32 delta_g; 270 struct iwl_chain_noise_data *data = &priv->chain_noise_data; 271 272 /* 273 * Find Gain Code for the chains based on "default chain" 274 */ 275 for (i = default_chain + 1; i < NUM_RX_CHAINS; i++) { 276 if ((data->disconn_array[i])) { 277 data->delta_gain_code[i] = 0; 278 continue; 279 } 280 delta_g = (1000 * ((s32)average_noise[0] - 281 (s32)average_noise[i])) / 1500; 282 /* bound gain by 2 bits value max, 3rd bit is sign */ 283 data->delta_gain_code[i] = 284 min(abs(delta_g), CHAIN_NOISE_MAX_DELTA_GAIN_CODE); 285 286 if (delta_g < 0) 287 /* set negative sign */ 288 data->delta_gain_code[i] |= (1 << 2); 289 } 290 291 IWL_DEBUG_CALIB(priv, "Delta gains: ANT_B = %d ANT_C = %d\n", 292 data->delta_gain_code[1], data->delta_gain_code[2]); 293 294 if (!data->radio_write) { 295 struct iwl_calib_chain_noise_gain_cmd cmd; 296 297 memset(&cmd, 0, sizeof(cmd)); 298 299 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD; 300 cmd.hdr.first_group = 0; 301 cmd.hdr.groups_num = 1; 302 cmd.hdr.data_valid = 1; 303 cmd.delta_gain_1 = data->delta_gain_code[1]; 304 cmd.delta_gain_2 = data->delta_gain_code[2]; 305 iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD, 306 sizeof(cmd), &cmd, NULL); 307 308 data->radio_write = 1; 309 data->state = IWL_CHAIN_NOISE_CALIBRATED; 310 } 311 312 data->chain_noise_a = 0; 313 data->chain_noise_b = 0; 314 data->chain_noise_c = 0; 315 data->chain_signal_a = 0; 316 data->chain_signal_b = 0; 317 data->chain_signal_c = 0; 318 data->beacon_count = 0; 319} 320 321static void iwl5000_chain_noise_reset(struct iwl_priv *priv) 322{ 323 struct iwl_chain_noise_data *data = &priv->chain_noise_data; 324 int ret; 325 326 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) { 327 struct iwl_calib_chain_noise_reset_cmd cmd; 328 memset(&cmd, 0, sizeof(cmd)); 329 330 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD; 331 cmd.hdr.first_group = 0; 332 cmd.hdr.groups_num = 1; 333 cmd.hdr.data_valid = 1; 334 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD, 335 sizeof(cmd), &cmd); 336 if (ret) 337 IWL_ERR(priv, 338 "Could not send REPLY_PHY_CALIBRATION_CMD\n"); 339 data->state = IWL_CHAIN_NOISE_ACCUMULATE; 340 IWL_DEBUG_CALIB(priv, "Run chain_noise_calibrate\n"); 341 } 342} 343 344void iwl5000_rts_tx_cmd_flag(struct ieee80211_tx_info *info, 345 __le32 *tx_flags) 346{ 347 if ((info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) || 348 (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT)) 349 *tx_flags |= TX_CMD_FLG_RTS_CTS_MSK; 350 else 351 *tx_flags &= ~TX_CMD_FLG_RTS_CTS_MSK; 352} 353 354static struct iwl_sensitivity_ranges iwl5000_sensitivity = { 355 .min_nrg_cck = 95, 356 .max_nrg_cck = 0, /* not used, set to 0 */ 357 .auto_corr_min_ofdm = 90, 358 .auto_corr_min_ofdm_mrc = 170, 359 .auto_corr_min_ofdm_x1 = 120, 360 .auto_corr_min_ofdm_mrc_x1 = 240, 361 362 .auto_corr_max_ofdm = 120, 363 .auto_corr_max_ofdm_mrc = 210, 364 .auto_corr_max_ofdm_x1 = 155, 365 .auto_corr_max_ofdm_mrc_x1 = 290, 366 367 .auto_corr_min_cck = 125, 368 .auto_corr_max_cck = 200, 369 .auto_corr_min_cck_mrc = 170, 370 .auto_corr_max_cck_mrc = 400, 371 .nrg_th_cck = 95, 372 .nrg_th_ofdm = 95, 373}; 374 375static struct iwl_sensitivity_ranges iwl5150_sensitivity = { 376 .min_nrg_cck = 95, 377 .max_nrg_cck = 0, /* not used, set to 0 */ 378 .auto_corr_min_ofdm = 90, 379 .auto_corr_min_ofdm_mrc = 170, 380 .auto_corr_min_ofdm_x1 = 105, 381 .auto_corr_min_ofdm_mrc_x1 = 220, 382 383 .auto_corr_max_ofdm = 120, 384 .auto_corr_max_ofdm_mrc = 210, 385 /* max = min for performance bug in 5150 DSP */ 386 .auto_corr_max_ofdm_x1 = 105, 387 .auto_corr_max_ofdm_mrc_x1 = 220, 388 389 .auto_corr_min_cck = 125, 390 .auto_corr_max_cck = 200, 391 .auto_corr_min_cck_mrc = 170, 392 .auto_corr_max_cck_mrc = 400, 393 .nrg_th_cck = 95, 394 .nrg_th_ofdm = 95, 395}; 396 397const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv, 398 size_t offset) 399{ 400 u32 address = eeprom_indirect_address(priv, offset); 401 BUG_ON(address >= priv->cfg->eeprom_size); 402 return &priv->eeprom[address]; 403} 404 405static void iwl5150_set_ct_threshold(struct iwl_priv *priv) 406{ 407 const s32 volt2temp_coef = IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF; 408 s32 threshold = (s32)CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD_LEGACY) - 409 iwl_temp_calib_to_offset(priv); 410 411 priv->hw_params.ct_kill_threshold = threshold * volt2temp_coef; 412} 413 414static void iwl5000_set_ct_threshold(struct iwl_priv *priv) 415{ 416 /* want Celsius */ 417 priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD_LEGACY; 418} 419 420/* 421 * Calibration 422 */ 423static int iwl5000_set_Xtal_calib(struct iwl_priv *priv) 424{ 425 struct iwl_calib_xtal_freq_cmd cmd; 426 u16 *xtal_calib = (u16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_XTAL); 427 428 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD; 429 cmd.hdr.first_group = 0; 430 cmd.hdr.groups_num = 1; 431 cmd.hdr.data_valid = 1; 432 cmd.cap_pin1 = (u8)xtal_calib[0]; 433 cmd.cap_pin2 = (u8)xtal_calib[1]; 434 return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL], 435 (u8 *)&cmd, sizeof(cmd)); 436} 437 438static int iwl5000_send_calib_cfg(struct iwl_priv *priv) 439{ 440 struct iwl_calib_cfg_cmd calib_cfg_cmd; 441 struct iwl_host_cmd cmd = { 442 .id = CALIBRATION_CFG_CMD, 443 .len = sizeof(struct iwl_calib_cfg_cmd), 444 .data = &calib_cfg_cmd, 445 }; 446 447 memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd)); 448 calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL; 449 calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL; 450 calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL; 451 calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL; 452 453 return iwl_send_cmd(priv, &cmd); 454} 455 456static void iwl5000_rx_calib_result(struct iwl_priv *priv, 457 struct iwl_rx_mem_buffer *rxb) 458{ 459 struct iwl_rx_packet *pkt = (void *)rxb->skb->data; 460 struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw; 461 int len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK; 462 int index; 463 464 /* reduce the size of the length field itself */ 465 len -= 4; 466 467 /* Define the order in which the results will be sent to the runtime 468 * uCode. iwl_send_calib_results sends them in a row according to their 469 * index. We sort them here */ 470 switch (hdr->op_code) { 471 case IWL_PHY_CALIBRATE_DC_CMD: 472 index = IWL_CALIB_DC; 473 break; 474 case IWL_PHY_CALIBRATE_LO_CMD: 475 index = IWL_CALIB_LO; 476 break; 477 case IWL_PHY_CALIBRATE_TX_IQ_CMD: 478 index = IWL_CALIB_TX_IQ; 479 break; 480 case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD: 481 index = IWL_CALIB_TX_IQ_PERD; 482 break; 483 case IWL_PHY_CALIBRATE_BASE_BAND_CMD: 484 index = IWL_CALIB_BASE_BAND; 485 break; 486 default: 487 IWL_ERR(priv, "Unknown calibration notification %d\n", 488 hdr->op_code); 489 return; 490 } 491 iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len); 492} 493 494static void iwl5000_rx_calib_complete(struct iwl_priv *priv, 495 struct iwl_rx_mem_buffer *rxb) 496{ 497 IWL_DEBUG_INFO(priv, "Init. calibration is completed, restarting fw.\n"); 498 queue_work(priv->workqueue, &priv->restart); 499} 500 501/* 502 * ucode 503 */ 504static int iwl5000_load_section(struct iwl_priv *priv, 505 struct fw_desc *image, 506 u32 dst_addr) 507{ 508 dma_addr_t phy_addr = image->p_addr; 509 u32 byte_cnt = image->len; 510 511 iwl_write_direct32(priv, 512 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 513 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); 514 515 iwl_write_direct32(priv, 516 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr); 517 518 iwl_write_direct32(priv, 519 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), 520 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); 521 522 iwl_write_direct32(priv, 523 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), 524 (iwl_get_dma_hi_addr(phy_addr) 525 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); 526 527 iwl_write_direct32(priv, 528 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), 529 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM | 530 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX | 531 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); 532 533 iwl_write_direct32(priv, 534 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 535 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 536 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | 537 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); 538 539 return 0; 540} 541 542static int iwl5000_load_given_ucode(struct iwl_priv *priv, 543 struct fw_desc *inst_image, 544 struct fw_desc *data_image) 545{ 546 int ret = 0; 547 548 ret = iwl5000_load_section(priv, inst_image, 549 IWL50_RTC_INST_LOWER_BOUND); 550 if (ret) 551 return ret; 552 553 IWL_DEBUG_INFO(priv, "INST uCode section being loaded...\n"); 554 ret = wait_event_interruptible_timeout(priv->wait_command_queue, 555 priv->ucode_write_complete, 5 * HZ); 556 if (ret == -ERESTARTSYS) { 557 IWL_ERR(priv, "Could not load the INST uCode section due " 558 "to interrupt\n"); 559 return ret; 560 } 561 if (!ret) { 562 IWL_ERR(priv, "Could not load the INST uCode section\n"); 563 return -ETIMEDOUT; 564 } 565 566 priv->ucode_write_complete = 0; 567 568 ret = iwl5000_load_section( 569 priv, data_image, IWL50_RTC_DATA_LOWER_BOUND); 570 if (ret) 571 return ret; 572 573 IWL_DEBUG_INFO(priv, "DATA uCode section being loaded...\n"); 574 575 ret = wait_event_interruptible_timeout(priv->wait_command_queue, 576 priv->ucode_write_complete, 5 * HZ); 577 if (ret == -ERESTARTSYS) { 578 IWL_ERR(priv, "Could not load the INST uCode section due " 579 "to interrupt\n"); 580 return ret; 581 } else if (!ret) { 582 IWL_ERR(priv, "Could not load the DATA uCode section\n"); 583 return -ETIMEDOUT; 584 } else 585 ret = 0; 586 587 priv->ucode_write_complete = 0; 588 589 return ret; 590} 591 592int iwl5000_load_ucode(struct iwl_priv *priv) 593{ 594 int ret = 0; 595 596 /* check whether init ucode should be loaded, or rather runtime ucode */ 597 if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) { 598 IWL_DEBUG_INFO(priv, "Init ucode found. Loading init ucode...\n"); 599 ret = iwl5000_load_given_ucode(priv, 600 &priv->ucode_init, &priv->ucode_init_data); 601 if (!ret) { 602 IWL_DEBUG_INFO(priv, "Init ucode load complete.\n"); 603 priv->ucode_type = UCODE_INIT; 604 } 605 } else { 606 IWL_DEBUG_INFO(priv, "Init ucode not found, or already loaded. " 607 "Loading runtime ucode...\n"); 608 ret = iwl5000_load_given_ucode(priv, 609 &priv->ucode_code, &priv->ucode_data); 610 if (!ret) { 611 IWL_DEBUG_INFO(priv, "Runtime ucode load complete.\n"); 612 priv->ucode_type = UCODE_RT; 613 } 614 } 615 616 return ret; 617} 618 619void iwl5000_init_alive_start(struct iwl_priv *priv) 620{ 621 int ret = 0; 622 623 /* Check alive response for "valid" sign from uCode */ 624 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) { 625 /* We had an error bringing up the hardware, so take it 626 * all the way back down so we can try again */ 627 IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n"); 628 goto restart; 629 } 630 631 /* initialize uCode was loaded... verify inst image. 632 * This is a paranoid check, because we would not have gotten the 633 * "initialize" alive if code weren't properly loaded. */ 634 if (iwl_verify_ucode(priv)) { 635 /* Runtime instruction load was bad; 636 * take it all the way back down so we can try again */ 637 IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n"); 638 goto restart; 639 } 640 641 iwl_clear_stations_table(priv); 642 ret = priv->cfg->ops->lib->alive_notify(priv); 643 if (ret) { 644 IWL_WARN(priv, 645 "Could not complete ALIVE transition: %d\n", ret); 646 goto restart; 647 } 648 649 iwl5000_send_calib_cfg(priv); 650 return; 651 652restart: 653 /* real restart (first load init_ucode) */ 654 queue_work(priv->workqueue, &priv->restart); 655} 656 657static void iwl5000_set_wr_ptrs(struct iwl_priv *priv, 658 int txq_id, u32 index) 659{ 660 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 661 (index & 0xff) | (txq_id << 8)); 662 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index); 663} 664 665static void iwl5000_tx_queue_set_status(struct iwl_priv *priv, 666 struct iwl_tx_queue *txq, 667 int tx_fifo_id, int scd_retry) 668{ 669 int txq_id = txq->q.id; 670 int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0; 671 672 iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id), 673 (active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) | 674 (tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) | 675 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) | 676 IWL50_SCD_QUEUE_STTS_REG_MSK); 677 678 txq->sched_retry = scd_retry; 679 680 IWL_DEBUG_INFO(priv, "%s %s Queue %d on AC %d\n", 681 active ? "Activate" : "Deactivate", 682 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id); 683} 684 685static int iwl5000_send_wimax_coex(struct iwl_priv *priv) 686{ 687 struct iwl_wimax_coex_cmd coex_cmd; 688 689 memset(&coex_cmd, 0, sizeof(coex_cmd)); 690 691 return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD, 692 sizeof(coex_cmd), &coex_cmd); 693} 694 695int iwl5000_alive_notify(struct iwl_priv *priv) 696{ 697 u32 a; 698 unsigned long flags; 699 int i, chan; 700 u32 reg_val; 701 702 spin_lock_irqsave(&priv->lock, flags); 703 704 priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR); 705 a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET; 706 for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET; 707 a += 4) 708 iwl_write_targ_mem(priv, a, 0); 709 for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET; 710 a += 4) 711 iwl_write_targ_mem(priv, a, 0); 712 for (; a < priv->scd_base_addr + 713 IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(priv->hw_params.max_txq_num); a += 4) 714 iwl_write_targ_mem(priv, a, 0); 715 716 iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR, 717 priv->scd_bc_tbls.dma >> 10); 718 719 /* Enable DMA channel */ 720 for (chan = 0; chan < FH50_TCSR_CHNL_NUM ; chan++) 721 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan), 722 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 723 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE); 724 725 /* Update FH chicken bits */ 726 reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG); 727 iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG, 728 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN); 729 730 iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, 731 IWL50_SCD_QUEUECHAIN_SEL_ALL(priv->hw_params.max_txq_num)); 732 iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0); 733 734 /* initiate the queues */ 735 for (i = 0; i < priv->hw_params.max_txq_num; i++) { 736 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0); 737 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8)); 738 iwl_write_targ_mem(priv, priv->scd_base_addr + 739 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0); 740 iwl_write_targ_mem(priv, priv->scd_base_addr + 741 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) + 742 sizeof(u32), 743 ((SCD_WIN_SIZE << 744 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & 745 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | 746 ((SCD_FRAME_LIMIT << 747 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & 748 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); 749 } 750 751 iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK, 752 IWL_MASK(0, priv->hw_params.max_txq_num)); 753 754 /* Activate all Tx DMA/FIFO channels */ 755 priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7)); 756 757 iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0); 758 759 /* map qos queues to fifos one-to-one */ 760 for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) { 761 int ac = iwl5000_default_queue_to_tx_fifo[i]; 762 iwl_txq_ctx_activate(priv, i); 763 iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0); 764 } 765 /* TODO - need to initialize those FIFOs inside the loop above, 766 * not only mark them as active */ 767 iwl_txq_ctx_activate(priv, 4); 768 iwl_txq_ctx_activate(priv, 7); 769 iwl_txq_ctx_activate(priv, 8); 770 iwl_txq_ctx_activate(priv, 9); 771 772 spin_unlock_irqrestore(&priv->lock, flags); 773 774 775 iwl5000_send_wimax_coex(priv); 776 777 iwl5000_set_Xtal_calib(priv); 778 iwl_send_calib_results(priv); 779 780 return 0; 781} 782 783int iwl5000_hw_set_hw_params(struct iwl_priv *priv) 784{ 785 if ((priv->cfg->mod_params->num_of_queues > IWL50_NUM_QUEUES) || 786 (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) { 787 IWL_ERR(priv, 788 "invalid queues_num, should be between %d and %d\n", 789 IWL_MIN_NUM_QUEUES, IWL50_NUM_QUEUES); 790 return -EINVAL; 791 } 792 793 priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues; 794 priv->hw_params.dma_chnl_num = FH50_TCSR_CHNL_NUM; 795 priv->hw_params.scd_bc_tbls_size = 796 IWL50_NUM_QUEUES * sizeof(struct iwl5000_scd_bc_tbl); 797 priv->hw_params.tfd_size = sizeof(struct iwl_tfd); 798 priv->hw_params.max_stations = IWL5000_STATION_COUNT; 799 priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID; 800 801 priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE; 802 priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE; 803 804 priv->hw_params.max_bsm_size = 0; 805 priv->hw_params.ht40_channel = BIT(IEEE80211_BAND_2GHZ) | 806 BIT(IEEE80211_BAND_5GHZ); 807 priv->hw_params.rx_wrt_ptr_reg = FH_RSCSR_CHNL0_WPTR; 808 809 priv->hw_params.tx_chains_num = num_of_ant(priv->cfg->valid_tx_ant); 810 priv->hw_params.rx_chains_num = num_of_ant(priv->cfg->valid_rx_ant); 811 priv->hw_params.valid_tx_ant = priv->cfg->valid_tx_ant; 812 priv->hw_params.valid_rx_ant = priv->cfg->valid_rx_ant; 813 814 if (priv->cfg->ops->lib->temp_ops.set_ct_kill) 815 priv->cfg->ops->lib->temp_ops.set_ct_kill(priv); 816 817 /* Set initial sensitivity parameters */ 818 /* Set initial calibration set */ 819 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) { 820 case CSR_HW_REV_TYPE_5150: 821 priv->hw_params.sens = &iwl5150_sensitivity; 822 priv->hw_params.calib_init_cfg = 823 BIT(IWL_CALIB_DC) | 824 BIT(IWL_CALIB_LO) | 825 BIT(IWL_CALIB_TX_IQ) | 826 BIT(IWL_CALIB_BASE_BAND); 827 828 break; 829 default: 830 priv->hw_params.sens = &iwl5000_sensitivity; 831 priv->hw_params.calib_init_cfg = 832 BIT(IWL_CALIB_XTAL) | 833 BIT(IWL_CALIB_LO) | 834 BIT(IWL_CALIB_TX_IQ) | 835 BIT(IWL_CALIB_TX_IQ_PERD) | 836 BIT(IWL_CALIB_BASE_BAND); 837 break; 838 } 839 840 return 0; 841} 842 843/** 844 * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array 845 */ 846void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv, 847 struct iwl_tx_queue *txq, 848 u16 byte_cnt) 849{ 850 struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr; 851 int write_ptr = txq->q.write_ptr; 852 int txq_id = txq->q.id; 853 u8 sec_ctl = 0; 854 u8 sta_id = 0; 855 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE; 856 __le16 bc_ent; 857 858 WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX); 859 860 if (txq_id != IWL_CMD_QUEUE_NUM) { 861 sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id; 862 sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl; 863 864 switch (sec_ctl & TX_CMD_SEC_MSK) { 865 case TX_CMD_SEC_CCM: 866 len += CCMP_MIC_LEN; 867 break; 868 case TX_CMD_SEC_TKIP: 869 len += TKIP_ICV_LEN; 870 break; 871 case TX_CMD_SEC_WEP: 872 len += WEP_IV_LEN + WEP_ICV_LEN; 873 break; 874 } 875 } 876 877 bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12)); 878 879 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent; 880 881 if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP) 882 scd_bc_tbl[txq_id]. 883 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent; 884} 885 886void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv, 887 struct iwl_tx_queue *txq) 888{ 889 struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr; 890 int txq_id = txq->q.id; 891 int read_ptr = txq->q.read_ptr; 892 u8 sta_id = 0; 893 __le16 bc_ent; 894 895 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX); 896 897 if (txq_id != IWL_CMD_QUEUE_NUM) 898 sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id; 899 900 bc_ent = cpu_to_le16(1 | (sta_id << 12)); 901 scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent; 902 903 if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP) 904 scd_bc_tbl[txq_id]. 905 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent; 906} 907 908static int iwl5000_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid, 909 u16 txq_id) 910{ 911 u32 tbl_dw_addr; 912 u32 tbl_dw; 913 u16 scd_q2ratid; 914 915 scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK; 916 917 tbl_dw_addr = priv->scd_base_addr + 918 IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id); 919 920 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr); 921 922 if (txq_id & 0x1) 923 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF); 924 else 925 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000); 926 927 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw); 928 929 return 0; 930} 931static void iwl5000_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id) 932{ 933 /* Simply stop the queue, but don't change any configuration; 934 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */ 935 iwl_write_prph(priv, 936 IWL50_SCD_QUEUE_STATUS_BITS(txq_id), 937 (0 << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE)| 938 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN)); 939} 940 941int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id, 942 int tx_fifo, int sta_id, int tid, u16 ssn_idx) 943{ 944 unsigned long flags; 945 u16 ra_tid; 946 947 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) || 948 (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) { 949 IWL_WARN(priv, 950 "queue number out of range: %d, must be %d to %d\n", 951 txq_id, IWL50_FIRST_AMPDU_QUEUE, 952 IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1); 953 return -EINVAL; 954 } 955 956 ra_tid = BUILD_RAxTID(sta_id, tid); 957 958 /* Modify device's station table to Tx this TID */ 959 iwl_sta_tx_modify_enable_tid(priv, sta_id, tid); 960 961 spin_lock_irqsave(&priv->lock, flags); 962 963 /* Stop this Tx queue before configuring it */ 964 iwl5000_tx_queue_stop_scheduler(priv, txq_id); 965 966 /* Map receiver-address / traffic-ID to this queue */ 967 iwl5000_tx_queue_set_q2ratid(priv, ra_tid, txq_id); 968 969 /* Set this queue as a chain-building queue */ 970 iwl_set_bits_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, (1<<txq_id)); 971 972 /* enable aggregations for the queue */ 973 iwl_set_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1<<txq_id)); 974 975 /* Place first TFD at index corresponding to start sequence number. 976 * Assumes that ssn_idx is valid (!= 0xFFF) */ 977 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff); 978 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff); 979 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx); 980 981 /* Set up Tx window size and frame limit for this queue */ 982 iwl_write_targ_mem(priv, priv->scd_base_addr + 983 IWL50_SCD_CONTEXT_QUEUE_OFFSET(txq_id) + 984 sizeof(u32), 985 ((SCD_WIN_SIZE << 986 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & 987 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | 988 ((SCD_FRAME_LIMIT << 989 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & 990 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); 991 992 iwl_set_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id)); 993 994 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */ 995 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1); 996 997 spin_unlock_irqrestore(&priv->lock, flags); 998 999 return 0; 1000} 1001 1002int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id, 1003 u16 ssn_idx, u8 tx_fifo) 1004{ 1005 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) || 1006 (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) { 1007 IWL_ERR(priv, 1008 "queue number out of range: %d, must be %d to %d\n", 1009 txq_id, IWL50_FIRST_AMPDU_QUEUE, 1010 IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1); 1011 return -EINVAL; 1012 } 1013 1014 iwl5000_tx_queue_stop_scheduler(priv, txq_id); 1015 1016 iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id)); 1017 1018 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff); 1019 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff); 1020 /* supposes that ssn_idx is valid (!= 0xFFF) */ 1021 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx); 1022 1023 iwl_clear_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id)); 1024 iwl_txq_ctx_deactivate(priv, txq_id); 1025 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0); 1026 1027 return 0; 1028} 1029 1030u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data) 1031{ 1032 u16 size = (u16)sizeof(struct iwl_addsta_cmd); 1033 struct iwl_addsta_cmd *addsta = (struct iwl_addsta_cmd *)data; 1034 memcpy(addsta, cmd, size); 1035 /* resrved in 5000 */ 1036 addsta->rate_n_flags = cpu_to_le16(0); 1037 return size; 1038} 1039 1040 1041/* 1042 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask 1043 * must be called under priv->lock and mac access 1044 */ 1045void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask) 1046{ 1047 iwl_write_prph(priv, IWL50_SCD_TXFACT, mask); 1048} 1049 1050 1051static inline u32 iwl5000_get_scd_ssn(struct iwl5000_tx_resp *tx_resp) 1052{ 1053 return le32_to_cpup((__le32 *)&tx_resp->status + 1054 tx_resp->frame_count) & MAX_SN; 1055} 1056 1057static int iwl5000_tx_status_reply_tx(struct iwl_priv *priv, 1058 struct iwl_ht_agg *agg, 1059 struct iwl5000_tx_resp *tx_resp, 1060 int txq_id, u16 start_idx) 1061{ 1062 u16 status; 1063 struct agg_tx_status *frame_status = &tx_resp->status; 1064 struct ieee80211_tx_info *info = NULL; 1065 struct ieee80211_hdr *hdr = NULL; 1066 u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags); 1067 int i, sh, idx; 1068 u16 seq; 1069 1070 if (agg->wait_for_ba) 1071 IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n"); 1072 1073 agg->frame_count = tx_resp->frame_count; 1074 agg->start_idx = start_idx; 1075 agg->rate_n_flags = rate_n_flags; 1076 agg->bitmap = 0; 1077 1078 /* # frames attempted by Tx command */ 1079 if (agg->frame_count == 1) { 1080 /* Only one frame was attempted; no block-ack will arrive */ 1081 status = le16_to_cpu(frame_status[0].status); 1082 idx = start_idx; 1083 1084 /* FIXME: code repetition */ 1085 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n", 1086 agg->frame_count, agg->start_idx, idx); 1087 1088 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]); 1089 info->status.rates[0].count = tx_resp->failure_frame + 1; 1090 info->flags &= ~IEEE80211_TX_CTL_AMPDU; 1091 info->flags |= iwl_is_tx_success(status) ? 1092 IEEE80211_TX_STAT_ACK : 0; 1093 iwl_hwrate_to_tx_control(priv, rate_n_flags, info); 1094 1095 /* FIXME: code repetition end */ 1096 1097 IWL_DEBUG_TX_REPLY(priv, "1 Frame 0x%x failure :%d\n", 1098 status & 0xff, tx_resp->failure_frame); 1099 IWL_DEBUG_TX_REPLY(priv, "Rate Info rate_n_flags=%x\n", rate_n_flags); 1100 1101 agg->wait_for_ba = 0; 1102 } else { 1103 /* Two or more frames were attempted; expect block-ack */ 1104 u64 bitmap = 0; 1105 int start = agg->start_idx; 1106 1107 /* Construct bit-map of pending frames within Tx window */ 1108 for (i = 0; i < agg->frame_count; i++) { 1109 u16 sc; 1110 status = le16_to_cpu(frame_status[i].status); 1111 seq = le16_to_cpu(frame_status[i].sequence); 1112 idx = SEQ_TO_INDEX(seq); 1113 txq_id = SEQ_TO_QUEUE(seq); 1114 1115 if (status & (AGG_TX_STATE_FEW_BYTES_MSK | 1116 AGG_TX_STATE_ABORT_MSK)) 1117 continue; 1118 1119 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n", 1120 agg->frame_count, txq_id, idx); 1121 1122 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx); 1123 if (!hdr) { 1124 IWL_ERR(priv, 1125 "BUG_ON idx doesn't point to valid skb" 1126 " idx=%d, txq_id=%d\n", idx, txq_id); 1127 return -1; 1128 } 1129 1130 sc = le16_to_cpu(hdr->seq_ctrl); 1131 if (idx != (SEQ_TO_SN(sc) & 0xff)) { 1132 IWL_ERR(priv, 1133 "BUG_ON idx doesn't match seq control" 1134 " idx=%d, seq_idx=%d, seq=%d\n", 1135 idx, SEQ_TO_SN(sc), 1136 hdr->seq_ctrl); 1137 return -1; 1138 } 1139 1140 IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n", 1141 i, idx, SEQ_TO_SN(sc)); 1142 1143 sh = idx - start; 1144 if (sh > 64) { 1145 sh = (start - idx) + 0xff; 1146 bitmap = bitmap << sh; 1147 sh = 0; 1148 start = idx; 1149 } else if (sh < -64) 1150 sh = 0xff - (start - idx); 1151 else if (sh < 0) { 1152 sh = start - idx; 1153 start = idx; 1154 bitmap = bitmap << sh; 1155 sh = 0; 1156 } 1157 bitmap |= 1ULL << sh; 1158 IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n", 1159 start, (unsigned long long)bitmap); 1160 } 1161 1162 agg->bitmap = bitmap; 1163 agg->start_idx = start; 1164 IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n", 1165 agg->frame_count, agg->start_idx, 1166 (unsigned long long)agg->bitmap); 1167 1168 if (bitmap) 1169 agg->wait_for_ba = 1; 1170 } 1171 return 0; 1172} 1173 1174static void iwl5000_rx_reply_tx(struct iwl_priv *priv, 1175 struct iwl_rx_mem_buffer *rxb) 1176{ 1177 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; 1178 u16 sequence = le16_to_cpu(pkt->hdr.sequence); 1179 int txq_id = SEQ_TO_QUEUE(sequence); 1180 int index = SEQ_TO_INDEX(sequence); 1181 struct iwl_tx_queue *txq = &priv->txq[txq_id]; 1182 struct ieee80211_tx_info *info; 1183 struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0]; 1184 u32 status = le16_to_cpu(tx_resp->status.status); 1185 int tid; 1186 int sta_id; 1187 int freed; 1188 1189 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) { 1190 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d " 1191 "is out of range [0-%d] %d %d\n", txq_id, 1192 index, txq->q.n_bd, txq->q.write_ptr, 1193 txq->q.read_ptr); 1194 return; 1195 } 1196 1197 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]); 1198 memset(&info->status, 0, sizeof(info->status)); 1199 1200 tid = (tx_resp->ra_tid & IWL50_TX_RES_TID_MSK) >> IWL50_TX_RES_TID_POS; 1201 sta_id = (tx_resp->ra_tid & IWL50_TX_RES_RA_MSK) >> IWL50_TX_RES_RA_POS; 1202 1203 if (txq->sched_retry) { 1204 const u32 scd_ssn = iwl5000_get_scd_ssn(tx_resp); 1205 struct iwl_ht_agg *agg = NULL; 1206 1207 agg = &priv->stations[sta_id].tid[tid].agg; 1208 1209 iwl5000_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index); 1210 1211 /* check if BAR is needed */ 1212 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status)) 1213 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK; 1214 1215 if (txq->q.read_ptr != (scd_ssn & 0xff)) { 1216 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd); 1217 IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim " 1218 "scd_ssn=%d idx=%d txq=%d swq=%d\n", 1219 scd_ssn , index, txq_id, txq->swq_id); 1220 1221 freed = iwl_tx_queue_reclaim(priv, txq_id, index); 1222 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed; 1223 1224 if (priv->mac80211_registered && 1225 (iwl_queue_space(&txq->q) > txq->q.low_mark) && 1226 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) { 1227 if (agg->state == IWL_AGG_OFF) 1228 iwl_wake_queue(priv, txq_id); 1229 else 1230 iwl_wake_queue(priv, txq->swq_id); 1231 } 1232 } 1233 } else { 1234 BUG_ON(txq_id != txq->swq_id); 1235 1236 info->status.rates[0].count = tx_resp->failure_frame + 1; 1237 info->flags |= iwl_is_tx_success(status) ? 1238 IEEE80211_TX_STAT_ACK : 0; 1239 iwl_hwrate_to_tx_control(priv, 1240 le32_to_cpu(tx_resp->rate_n_flags), 1241 info); 1242 1243 IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) rate_n_flags " 1244 "0x%x retries %d\n", 1245 txq_id, 1246 iwl_get_tx_fail_reason(status), status, 1247 le32_to_cpu(tx_resp->rate_n_flags), 1248 tx_resp->failure_frame); 1249 1250 freed = iwl_tx_queue_reclaim(priv, txq_id, index); 1251 if (ieee80211_is_data_qos(tx_resp->frame_ctrl)) 1252 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed; 1253 1254 if (priv->mac80211_registered && 1255 (iwl_queue_space(&txq->q) > txq->q.low_mark)) 1256 iwl_wake_queue(priv, txq_id); 1257 } 1258 1259 if (ieee80211_is_data_qos(tx_resp->frame_ctrl)) 1260 iwl_txq_check_empty(priv, sta_id, tid, txq_id); 1261 1262 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK)) 1263 IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n"); 1264} 1265 1266/* Currently 5000 is the superset of everything */ 1267u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len) 1268{ 1269 return len; 1270} 1271 1272void iwl5000_setup_deferred_work(struct iwl_priv *priv) 1273{ 1274 /* in 5000 the tx power calibration is done in uCode */ 1275 priv->disable_tx_power_cal = 1; 1276} 1277 1278void iwl5000_rx_handler_setup(struct iwl_priv *priv) 1279{ 1280 /* init calibration handlers */ 1281 priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] = 1282 iwl5000_rx_calib_result; 1283 priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] = 1284 iwl5000_rx_calib_complete; 1285 priv->rx_handlers[REPLY_TX] = iwl5000_rx_reply_tx; 1286} 1287 1288 1289int iwl5000_hw_valid_rtc_data_addr(u32 addr) 1290{ 1291 return (addr >= IWL50_RTC_DATA_LOWER_BOUND) && 1292 (addr < IWL50_RTC_DATA_UPPER_BOUND); 1293} 1294 1295static int iwl5000_send_rxon_assoc(struct iwl_priv *priv) 1296{ 1297 int ret = 0; 1298 struct iwl5000_rxon_assoc_cmd rxon_assoc; 1299 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon; 1300 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon; 1301 1302 if ((rxon1->flags == rxon2->flags) && 1303 (rxon1->filter_flags == rxon2->filter_flags) && 1304 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) && 1305 (rxon1->ofdm_ht_single_stream_basic_rates == 1306 rxon2->ofdm_ht_single_stream_basic_rates) && 1307 (rxon1->ofdm_ht_dual_stream_basic_rates == 1308 rxon2->ofdm_ht_dual_stream_basic_rates) && 1309 (rxon1->ofdm_ht_triple_stream_basic_rates == 1310 rxon2->ofdm_ht_triple_stream_basic_rates) && 1311 (rxon1->acquisition_data == rxon2->acquisition_data) && 1312 (rxon1->rx_chain == rxon2->rx_chain) && 1313 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) { 1314 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC. Not resending.\n"); 1315 return 0; 1316 } 1317 1318 rxon_assoc.flags = priv->staging_rxon.flags; 1319 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags; 1320 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates; 1321 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates; 1322 rxon_assoc.reserved1 = 0; 1323 rxon_assoc.reserved2 = 0; 1324 rxon_assoc.reserved3 = 0; 1325 rxon_assoc.ofdm_ht_single_stream_basic_rates = 1326 priv->staging_rxon.ofdm_ht_single_stream_basic_rates; 1327 rxon_assoc.ofdm_ht_dual_stream_basic_rates = 1328 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates; 1329 rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain; 1330 rxon_assoc.ofdm_ht_triple_stream_basic_rates = 1331 priv->staging_rxon.ofdm_ht_triple_stream_basic_rates; 1332 rxon_assoc.acquisition_data = priv->staging_rxon.acquisition_data; 1333 1334 ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC, 1335 sizeof(rxon_assoc), &rxon_assoc, NULL); 1336 if (ret) 1337 return ret; 1338 1339 return ret; 1340} 1341int iwl5000_send_tx_power(struct iwl_priv *priv) 1342{ 1343 struct iwl5000_tx_power_dbm_cmd tx_power_cmd; 1344 u8 tx_ant_cfg_cmd; 1345 1346 /* half dBm need to multiply */ 1347 tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt); 1348 tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED; 1349 tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO; 1350 1351 if (IWL_UCODE_API(priv->ucode_ver) == 1) 1352 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD_V1; 1353 else 1354 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD; 1355 1356 return iwl_send_cmd_pdu_async(priv, tx_ant_cfg_cmd, 1357 sizeof(tx_power_cmd), &tx_power_cmd, 1358 NULL); 1359} 1360 1361void iwl5000_temperature(struct iwl_priv *priv) 1362{ 1363 /* store temperature from statistics (in Celsius) */ 1364 priv->temperature = le32_to_cpu(priv->statistics.general.temperature); 1365 iwl_tt_handler(priv); 1366} 1367 1368static void iwl5150_temperature(struct iwl_priv *priv) 1369{ 1370 u32 vt = 0; 1371 s32 offset = iwl_temp_calib_to_offset(priv); 1372 1373 vt = le32_to_cpu(priv->statistics.general.temperature); 1374 vt = vt / IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF + offset; 1375 /* now vt hold the temperature in Kelvin */ 1376 priv->temperature = KELVIN_TO_CELSIUS(vt); 1377 iwl_tt_handler(priv); 1378} 1379 1380/* Calc max signal level (dBm) among 3 possible receivers */ 1381int iwl5000_calc_rssi(struct iwl_priv *priv, 1382 struct iwl_rx_phy_res *rx_resp) 1383{ 1384 /* data from PHY/DSP regarding signal strength, etc., 1385 * contents are always there, not configurable by host 1386 */ 1387 struct iwl5000_non_cfg_phy *ncphy = 1388 (struct iwl5000_non_cfg_phy *)rx_resp->non_cfg_phy_buf; 1389 u32 val, rssi_a, rssi_b, rssi_c, max_rssi; 1390 u8 agc; 1391 1392 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_AGC_IDX]); 1393 agc = (val & IWL50_OFDM_AGC_MSK) >> IWL50_OFDM_AGC_BIT_POS; 1394 1395 /* Find max rssi among 3 possible receivers. 1396 * These values are measured by the digital signal processor (DSP). 1397 * They should stay fairly constant even as the signal strength varies, 1398 * if the radio's automatic gain control (AGC) is working right. 1399 * AGC value (see below) will provide the "interesting" info. 1400 */ 1401 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_AB_IDX]); 1402 rssi_a = (val & IWL50_OFDM_RSSI_A_MSK) >> IWL50_OFDM_RSSI_A_BIT_POS; 1403 rssi_b = (val & IWL50_OFDM_RSSI_B_MSK) >> IWL50_OFDM_RSSI_B_BIT_POS; 1404 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_C_IDX]); 1405 rssi_c = (val & IWL50_OFDM_RSSI_C_MSK) >> IWL50_OFDM_RSSI_C_BIT_POS; 1406 1407 max_rssi = max_t(u32, rssi_a, rssi_b); 1408 max_rssi = max_t(u32, max_rssi, rssi_c); 1409 1410 IWL_DEBUG_STATS(priv, "Rssi In A %d B %d C %d Max %d AGC dB %d\n", 1411 rssi_a, rssi_b, rssi_c, max_rssi, agc); 1412 1413 /* dBm = max_rssi dB - agc dB - constant. 1414 * Higher AGC (higher radio gain) means lower signal. */ 1415 return max_rssi - agc - IWL49_RSSI_OFFSET; 1416} 1417 1418static int iwl5000_send_tx_ant_config(struct iwl_priv *priv, u8 valid_tx_ant) 1419{ 1420 struct iwl_tx_ant_config_cmd tx_ant_cmd = { 1421 .valid = cpu_to_le32(valid_tx_ant), 1422 }; 1423 1424 if (IWL_UCODE_API(priv->ucode_ver) > 1) { 1425 IWL_DEBUG_HC(priv, "select valid tx ant: %u\n", valid_tx_ant); 1426 return iwl_send_cmd_pdu(priv, TX_ANT_CONFIGURATION_CMD, 1427 sizeof(struct iwl_tx_ant_config_cmd), 1428 &tx_ant_cmd); 1429 } else { 1430 IWL_DEBUG_HC(priv, "TX_ANT_CONFIGURATION_CMD not supported\n"); 1431 return -EOPNOTSUPP; 1432 } 1433} 1434 1435 1436#define IWL5000_UCODE_GET(item) \ 1437static u32 iwl5000_ucode_get_##item(const struct iwl_ucode_header *ucode,\ 1438 u32 api_ver) \ 1439{ \ 1440 if (api_ver <= 2) \ 1441 return le32_to_cpu(ucode->u.v1.item); \ 1442 return le32_to_cpu(ucode->u.v2.item); \ 1443} 1444 1445static u32 iwl5000_ucode_get_header_size(u32 api_ver) 1446{ 1447 if (api_ver <= 2) 1448 return UCODE_HEADER_SIZE(1); 1449 return UCODE_HEADER_SIZE(2); 1450} 1451 1452static u32 iwl5000_ucode_get_build(const struct iwl_ucode_header *ucode, 1453 u32 api_ver) 1454{ 1455 if (api_ver <= 2) 1456 return 0; 1457 return le32_to_cpu(ucode->u.v2.build); 1458} 1459 1460static u8 *iwl5000_ucode_get_data(const struct iwl_ucode_header *ucode, 1461 u32 api_ver) 1462{ 1463 if (api_ver <= 2) 1464 return (u8 *) ucode->u.v1.data; 1465 return (u8 *) ucode->u.v2.data; 1466} 1467 1468IWL5000_UCODE_GET(inst_size); 1469IWL5000_UCODE_GET(data_size); 1470IWL5000_UCODE_GET(init_size); 1471IWL5000_UCODE_GET(init_data_size); 1472IWL5000_UCODE_GET(boot_size); 1473 1474struct iwl_hcmd_ops iwl5000_hcmd = { 1475 .rxon_assoc = iwl5000_send_rxon_assoc, 1476 .commit_rxon = iwl_commit_rxon, 1477 .set_rxon_chain = iwl_set_rxon_chain, 1478 .set_tx_ant = iwl5000_send_tx_ant_config, 1479}; 1480 1481struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = { 1482 .get_hcmd_size = iwl5000_get_hcmd_size, 1483 .build_addsta_hcmd = iwl5000_build_addsta_hcmd, 1484 .gain_computation = iwl5000_gain_computation, 1485 .chain_noise_reset = iwl5000_chain_noise_reset, 1486 .rts_tx_cmd_flag = iwl5000_rts_tx_cmd_flag, 1487 .calc_rssi = iwl5000_calc_rssi, 1488}; 1489 1490struct iwl_ucode_ops iwl5000_ucode = { 1491 .get_header_size = iwl5000_ucode_get_header_size, 1492 .get_build = iwl5000_ucode_get_build, 1493 .get_inst_size = iwl5000_ucode_get_inst_size, 1494 .get_data_size = iwl5000_ucode_get_data_size, 1495 .get_init_size = iwl5000_ucode_get_init_size, 1496 .get_init_data_size = iwl5000_ucode_get_init_data_size, 1497 .get_boot_size = iwl5000_ucode_get_boot_size, 1498 .get_data = iwl5000_ucode_get_data, 1499}; 1500 1501struct iwl_lib_ops iwl5000_lib = { 1502 .set_hw_params = iwl5000_hw_set_hw_params, 1503 .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl, 1504 .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl, 1505 .txq_set_sched = iwl5000_txq_set_sched, 1506 .txq_agg_enable = iwl5000_txq_agg_enable, 1507 .txq_agg_disable = iwl5000_txq_agg_disable, 1508 .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd, 1509 .txq_free_tfd = iwl_hw_txq_free_tfd, 1510 .txq_init = iwl_hw_tx_queue_init, 1511 .rx_handler_setup = iwl5000_rx_handler_setup, 1512 .setup_deferred_work = iwl5000_setup_deferred_work, 1513 .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr, 1514 .dump_nic_event_log = iwl_dump_nic_event_log, 1515 .dump_nic_error_log = iwl_dump_nic_error_log, 1516 .load_ucode = iwl5000_load_ucode, 1517 .init_alive_start = iwl5000_init_alive_start, 1518 .alive_notify = iwl5000_alive_notify, 1519 .send_tx_power = iwl5000_send_tx_power, 1520 .update_chain_flags = iwl_update_chain_flags, 1521 .apm_ops = { 1522 .init = iwl5000_apm_init, 1523 .reset = iwl5000_apm_reset, 1524 .stop = iwl_apm_stop, 1525 .config = iwl5000_nic_config, 1526 .set_pwr_src = iwl_set_pwr_src, 1527 }, 1528 .eeprom_ops = { 1529 .regulatory_bands = { 1530 EEPROM_5000_REG_BAND_1_CHANNELS, 1531 EEPROM_5000_REG_BAND_2_CHANNELS, 1532 EEPROM_5000_REG_BAND_3_CHANNELS, 1533 EEPROM_5000_REG_BAND_4_CHANNELS, 1534 EEPROM_5000_REG_BAND_5_CHANNELS, 1535 EEPROM_5000_REG_BAND_24_HT40_CHANNELS, 1536 EEPROM_5000_REG_BAND_52_HT40_CHANNELS 1537 }, 1538 .verify_signature = iwlcore_eeprom_verify_signature, 1539 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore, 1540 .release_semaphore = iwlcore_eeprom_release_semaphore, 1541 .calib_version = iwl5000_eeprom_calib_version, 1542 .query_addr = iwl5000_eeprom_query_addr, 1543 }, 1544 .post_associate = iwl_post_associate, 1545 .isr = iwl_isr_ict, 1546 .config_ap = iwl_config_ap, 1547 .temp_ops = { 1548 .temperature = iwl5000_temperature, 1549 .set_ct_kill = iwl5000_set_ct_threshold, 1550 }, 1551}; 1552 1553static struct iwl_lib_ops iwl5150_lib = { 1554 .set_hw_params = iwl5000_hw_set_hw_params, 1555 .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl, 1556 .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl, 1557 .txq_set_sched = iwl5000_txq_set_sched, 1558 .txq_agg_enable = iwl5000_txq_agg_enable, 1559 .txq_agg_disable = iwl5000_txq_agg_disable, 1560 .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd, 1561 .txq_free_tfd = iwl_hw_txq_free_tfd, 1562 .txq_init = iwl_hw_tx_queue_init, 1563 .rx_handler_setup = iwl5000_rx_handler_setup, 1564 .setup_deferred_work = iwl5000_setup_deferred_work, 1565 .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr, 1566 .dump_nic_event_log = iwl_dump_nic_event_log, 1567 .dump_nic_error_log = iwl_dump_nic_error_log, 1568 .load_ucode = iwl5000_load_ucode, 1569 .init_alive_start = iwl5000_init_alive_start, 1570 .alive_notify = iwl5000_alive_notify, 1571 .send_tx_power = iwl5000_send_tx_power, 1572 .update_chain_flags = iwl_update_chain_flags, 1573 .apm_ops = { 1574 .init = iwl5000_apm_init, 1575 .reset = iwl5000_apm_reset, 1576 .stop = iwl_apm_stop, 1577 .config = iwl5000_nic_config, 1578 .set_pwr_src = iwl_set_pwr_src, 1579 }, 1580 .eeprom_ops = { 1581 .regulatory_bands = { 1582 EEPROM_5000_REG_BAND_1_CHANNELS, 1583 EEPROM_5000_REG_BAND_2_CHANNELS, 1584 EEPROM_5000_REG_BAND_3_CHANNELS, 1585 EEPROM_5000_REG_BAND_4_CHANNELS, 1586 EEPROM_5000_REG_BAND_5_CHANNELS, 1587 EEPROM_5000_REG_BAND_24_HT40_CHANNELS, 1588 EEPROM_5000_REG_BAND_52_HT40_CHANNELS 1589 }, 1590 .verify_signature = iwlcore_eeprom_verify_signature, 1591 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore, 1592 .release_semaphore = iwlcore_eeprom_release_semaphore, 1593 .calib_version = iwl5000_eeprom_calib_version, 1594 .query_addr = iwl5000_eeprom_query_addr, 1595 }, 1596 .post_associate = iwl_post_associate, 1597 .isr = iwl_isr_ict, 1598 .config_ap = iwl_config_ap, 1599 .temp_ops = { 1600 .temperature = iwl5150_temperature, 1601 .set_ct_kill = iwl5150_set_ct_threshold, 1602 }, 1603}; 1604 1605static struct iwl_ops iwl5000_ops = { 1606 .ucode = &iwl5000_ucode, 1607 .lib = &iwl5000_lib, 1608 .hcmd = &iwl5000_hcmd, 1609 .utils = &iwl5000_hcmd_utils, 1610 .led = &iwlagn_led_ops, 1611}; 1612 1613static struct iwl_ops iwl5150_ops = { 1614 .ucode = &iwl5000_ucode, 1615 .lib = &iwl5150_lib, 1616 .hcmd = &iwl5000_hcmd, 1617 .utils = &iwl5000_hcmd_utils, 1618 .led = &iwlagn_led_ops, 1619}; 1620 1621struct iwl_mod_params iwl50_mod_params = { 1622 .num_of_queues = IWL50_NUM_QUEUES, 1623 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES, 1624 .amsdu_size_8K = 1, 1625 .restart_fw = 1, 1626 /* the rest are 0 by default */ 1627}; 1628 1629 1630struct iwl_cfg iwl5300_agn_cfg = { 1631 .name = "5300AGN", 1632 .fw_name_pre = IWL5000_FW_PRE, 1633 .ucode_api_max = IWL5000_UCODE_API_MAX, 1634 .ucode_api_min = IWL5000_UCODE_API_MIN, 1635 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N, 1636 .ops = &iwl5000_ops, 1637 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, 1638 .eeprom_ver = EEPROM_5000_EEPROM_VERSION, 1639 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION, 1640 .mod_params = &iwl50_mod_params, 1641 .valid_tx_ant = ANT_ABC, 1642 .valid_rx_ant = ANT_ABC, 1643 .need_pll_cfg = true, 1644 .ht_greenfield_support = true, 1645 .led_compensation = 51, 1646 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS, 1647}; 1648 1649struct iwl_cfg iwl5100_bg_cfg = { 1650 .name = "5100BG", 1651 .fw_name_pre = IWL5000_FW_PRE, 1652 .ucode_api_max = IWL5000_UCODE_API_MAX, 1653 .ucode_api_min = IWL5000_UCODE_API_MIN, 1654 .sku = IWL_SKU_G, 1655 .ops = &iwl5000_ops, 1656 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, 1657 .eeprom_ver = EEPROM_5000_EEPROM_VERSION, 1658 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION, 1659 .mod_params = &iwl50_mod_params, 1660 .valid_tx_ant = ANT_B, 1661 .valid_rx_ant = ANT_AB, 1662 .need_pll_cfg = true, 1663 .ht_greenfield_support = true, 1664 .led_compensation = 51, 1665 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS, 1666}; 1667 1668struct iwl_cfg iwl5100_abg_cfg = { 1669 .name = "5100ABG", 1670 .fw_name_pre = IWL5000_FW_PRE, 1671 .ucode_api_max = IWL5000_UCODE_API_MAX, 1672 .ucode_api_min = IWL5000_UCODE_API_MIN, 1673 .sku = IWL_SKU_A|IWL_SKU_G, 1674 .ops = &iwl5000_ops, 1675 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, 1676 .eeprom_ver = EEPROM_5000_EEPROM_VERSION, 1677 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION, 1678 .mod_params = &iwl50_mod_params, 1679 .valid_tx_ant = ANT_B, 1680 .valid_rx_ant = ANT_AB, 1681 .need_pll_cfg = true, 1682 .ht_greenfield_support = true, 1683 .led_compensation = 51, 1684 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS, 1685}; 1686 1687struct iwl_cfg iwl5100_agn_cfg = { 1688 .name = "5100AGN", 1689 .fw_name_pre = IWL5000_FW_PRE, 1690 .ucode_api_max = IWL5000_UCODE_API_MAX, 1691 .ucode_api_min = IWL5000_UCODE_API_MIN, 1692 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N, 1693 .ops = &iwl5000_ops, 1694 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, 1695 .eeprom_ver = EEPROM_5000_EEPROM_VERSION, 1696 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION, 1697 .mod_params = &iwl50_mod_params, 1698 .valid_tx_ant = ANT_B, 1699 .valid_rx_ant = ANT_AB, 1700 .need_pll_cfg = true, 1701 .ht_greenfield_support = true, 1702 .led_compensation = 51, 1703 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS, 1704}; 1705 1706struct iwl_cfg iwl5350_agn_cfg = { 1707 .name = "5350AGN", 1708 .fw_name_pre = IWL5000_FW_PRE, 1709 .ucode_api_max = IWL5000_UCODE_API_MAX, 1710 .ucode_api_min = IWL5000_UCODE_API_MIN, 1711 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N, 1712 .ops = &iwl5000_ops, 1713 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, 1714 .eeprom_ver = EEPROM_5050_EEPROM_VERSION, 1715 .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION, 1716 .mod_params = &iwl50_mod_params, 1717 .valid_tx_ant = ANT_ABC, 1718 .valid_rx_ant = ANT_ABC, 1719 .need_pll_cfg = true, 1720 .ht_greenfield_support = true, 1721 .led_compensation = 51, 1722 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS, 1723}; 1724 1725struct iwl_cfg iwl5150_agn_cfg = { 1726 .name = "5150AGN", 1727 .fw_name_pre = IWL5150_FW_PRE, 1728 .ucode_api_max = IWL5150_UCODE_API_MAX, 1729 .ucode_api_min = IWL5150_UCODE_API_MIN, 1730 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N, 1731 .ops = &iwl5150_ops, 1732 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, 1733 .eeprom_ver = EEPROM_5050_EEPROM_VERSION, 1734 .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION, 1735 .mod_params = &iwl50_mod_params, 1736 .valid_tx_ant = ANT_A, 1737 .valid_rx_ant = ANT_AB, 1738 .need_pll_cfg = true, 1739 .ht_greenfield_support = true, 1740 .led_compensation = 51, 1741 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS, 1742}; 1743 1744MODULE_FIRMWARE(IWL5000_MODULE_FIRMWARE(IWL5000_UCODE_API_MAX)); 1745MODULE_FIRMWARE(IWL5150_MODULE_FIRMWARE(IWL5150_UCODE_API_MAX)); 1746 1747module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, S_IRUGO); 1748MODULE_PARM_DESC(swcrypto50, 1749 "using software crypto engine (default 0 [hardware])\n"); 1750module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, S_IRUGO); 1751MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series"); 1752module_param_named(11n_disable50, iwl50_mod_params.disable_11n, int, S_IRUGO); 1753MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality"); 1754module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K, 1755 int, S_IRUGO); 1756MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series"); 1757module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, S_IRUGO); 1758MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error"); 1759