iwl-5000.c revision fadb3582a38c33d0f7c58ab7905d4dbc67f4c4d9
1/****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2009 Intel Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * The full GNU General Public License is included in this distribution in the 19 * file called LICENSE. 20 * 21 * Contact Information: 22 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 23 * 24 *****************************************************************************/ 25 26#include <linux/kernel.h> 27#include <linux/module.h> 28#include <linux/init.h> 29#include <linux/pci.h> 30#include <linux/dma-mapping.h> 31#include <linux/delay.h> 32#include <linux/skbuff.h> 33#include <linux/netdevice.h> 34#include <linux/wireless.h> 35#include <net/mac80211.h> 36#include <linux/etherdevice.h> 37#include <asm/unaligned.h> 38 39#include "iwl-eeprom.h" 40#include "iwl-dev.h" 41#include "iwl-core.h" 42#include "iwl-io.h" 43#include "iwl-sta.h" 44#include "iwl-helpers.h" 45#include "iwl-agn-led.h" 46#include "iwl-5000-hw.h" 47#include "iwl-6000-hw.h" 48 49/* Highest firmware API version supported */ 50#define IWL5000_UCODE_API_MAX 2 51#define IWL5150_UCODE_API_MAX 2 52 53/* Lowest firmware API version supported */ 54#define IWL5000_UCODE_API_MIN 1 55#define IWL5150_UCODE_API_MIN 1 56 57#define IWL5000_FW_PRE "iwlwifi-5000-" 58#define _IWL5000_MODULE_FIRMWARE(api) IWL5000_FW_PRE #api ".ucode" 59#define IWL5000_MODULE_FIRMWARE(api) _IWL5000_MODULE_FIRMWARE(api) 60 61#define IWL5150_FW_PRE "iwlwifi-5150-" 62#define _IWL5150_MODULE_FIRMWARE(api) IWL5150_FW_PRE #api ".ucode" 63#define IWL5150_MODULE_FIRMWARE(api) _IWL5150_MODULE_FIRMWARE(api) 64 65static const u16 iwl5000_default_queue_to_tx_fifo[] = { 66 IWL_TX_FIFO_AC3, 67 IWL_TX_FIFO_AC2, 68 IWL_TX_FIFO_AC1, 69 IWL_TX_FIFO_AC0, 70 IWL50_CMD_FIFO_NUM, 71 IWL_TX_FIFO_HCCA_1, 72 IWL_TX_FIFO_HCCA_2 73}; 74 75/* NIC configuration for 5000 series */ 76void iwl5000_nic_config(struct iwl_priv *priv) 77{ 78 unsigned long flags; 79 u16 radio_cfg; 80 81 spin_lock_irqsave(&priv->lock, flags); 82 83 radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG); 84 85 /* write radio config values to register */ 86 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_RF_CONFIG_TYPE_MAX) 87 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, 88 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) | 89 EEPROM_RF_CFG_STEP_MSK(radio_cfg) | 90 EEPROM_RF_CFG_DASH_MSK(radio_cfg)); 91 92 /* set CSR_HW_CONFIG_REG for uCode use */ 93 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, 94 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI | 95 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI); 96 97 /* W/A : NIC is stuck in a reset state after Early PCIe power off 98 * (PCIe power is lost before PERST# is asserted), 99 * causing ME FW to lose ownership and not being able to obtain it back. 100 */ 101 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, 102 APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS, 103 ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS); 104 105 106 spin_unlock_irqrestore(&priv->lock, flags); 107} 108 109 110/* 111 * EEPROM 112 */ 113static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address) 114{ 115 u16 offset = 0; 116 117 if ((address & INDIRECT_ADDRESS) == 0) 118 return address; 119 120 switch (address & INDIRECT_TYPE_MSK) { 121 case INDIRECT_HOST: 122 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST); 123 break; 124 case INDIRECT_GENERAL: 125 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL); 126 break; 127 case INDIRECT_REGULATORY: 128 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY); 129 break; 130 case INDIRECT_CALIBRATION: 131 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION); 132 break; 133 case INDIRECT_PROCESS_ADJST: 134 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST); 135 break; 136 case INDIRECT_OTHERS: 137 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS); 138 break; 139 default: 140 IWL_ERR(priv, "illegal indirect type: 0x%X\n", 141 address & INDIRECT_TYPE_MSK); 142 break; 143 } 144 145 /* translate the offset from words to byte */ 146 return (address & ADDRESS_MSK) + (offset << 1); 147} 148 149u16 iwl5000_eeprom_calib_version(struct iwl_priv *priv) 150{ 151 struct iwl_eeprom_calib_hdr { 152 u8 version; 153 u8 pa_type; 154 u16 voltage; 155 } *hdr; 156 157 hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv, 158 EEPROM_5000_CALIB_ALL); 159 return hdr->version; 160 161} 162 163static void iwl5000_gain_computation(struct iwl_priv *priv, 164 u32 average_noise[NUM_RX_CHAINS], 165 u16 min_average_noise_antenna_i, 166 u32 min_average_noise, 167 u8 default_chain) 168{ 169 int i; 170 s32 delta_g; 171 struct iwl_chain_noise_data *data = &priv->chain_noise_data; 172 173 /* 174 * Find Gain Code for the chains based on "default chain" 175 */ 176 for (i = default_chain + 1; i < NUM_RX_CHAINS; i++) { 177 if ((data->disconn_array[i])) { 178 data->delta_gain_code[i] = 0; 179 continue; 180 } 181 delta_g = (1000 * ((s32)average_noise[default_chain] - 182 (s32)average_noise[i])) / 1500; 183 /* bound gain by 2 bits value max, 3rd bit is sign */ 184 data->delta_gain_code[i] = 185 min(abs(delta_g), (long) CHAIN_NOISE_MAX_DELTA_GAIN_CODE); 186 187 if (delta_g < 0) 188 /* set negative sign */ 189 data->delta_gain_code[i] |= (1 << 2); 190 } 191 192 IWL_DEBUG_CALIB(priv, "Delta gains: ANT_B = %d ANT_C = %d\n", 193 data->delta_gain_code[1], data->delta_gain_code[2]); 194 195 if (!data->radio_write) { 196 struct iwl_calib_chain_noise_gain_cmd cmd; 197 198 memset(&cmd, 0, sizeof(cmd)); 199 200 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD; 201 cmd.hdr.first_group = 0; 202 cmd.hdr.groups_num = 1; 203 cmd.hdr.data_valid = 1; 204 cmd.delta_gain_1 = data->delta_gain_code[1]; 205 cmd.delta_gain_2 = data->delta_gain_code[2]; 206 iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD, 207 sizeof(cmd), &cmd, NULL); 208 209 data->radio_write = 1; 210 data->state = IWL_CHAIN_NOISE_CALIBRATED; 211 } 212 213 data->chain_noise_a = 0; 214 data->chain_noise_b = 0; 215 data->chain_noise_c = 0; 216 data->chain_signal_a = 0; 217 data->chain_signal_b = 0; 218 data->chain_signal_c = 0; 219 data->beacon_count = 0; 220} 221 222static void iwl5000_chain_noise_reset(struct iwl_priv *priv) 223{ 224 struct iwl_chain_noise_data *data = &priv->chain_noise_data; 225 int ret; 226 227 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) { 228 struct iwl_calib_chain_noise_reset_cmd cmd; 229 memset(&cmd, 0, sizeof(cmd)); 230 231 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD; 232 cmd.hdr.first_group = 0; 233 cmd.hdr.groups_num = 1; 234 cmd.hdr.data_valid = 1; 235 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD, 236 sizeof(cmd), &cmd); 237 if (ret) 238 IWL_ERR(priv, 239 "Could not send REPLY_PHY_CALIBRATION_CMD\n"); 240 data->state = IWL_CHAIN_NOISE_ACCUMULATE; 241 IWL_DEBUG_CALIB(priv, "Run chain_noise_calibrate\n"); 242 } 243} 244 245void iwl5000_rts_tx_cmd_flag(struct ieee80211_tx_info *info, 246 __le32 *tx_flags) 247{ 248 if ((info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) || 249 (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT)) 250 *tx_flags |= TX_CMD_FLG_RTS_CTS_MSK; 251 else 252 *tx_flags &= ~TX_CMD_FLG_RTS_CTS_MSK; 253} 254 255static struct iwl_sensitivity_ranges iwl5000_sensitivity = { 256 .min_nrg_cck = 95, 257 .max_nrg_cck = 0, /* not used, set to 0 */ 258 .auto_corr_min_ofdm = 90, 259 .auto_corr_min_ofdm_mrc = 170, 260 .auto_corr_min_ofdm_x1 = 120, 261 .auto_corr_min_ofdm_mrc_x1 = 240, 262 263 .auto_corr_max_ofdm = 120, 264 .auto_corr_max_ofdm_mrc = 210, 265 .auto_corr_max_ofdm_x1 = 155, 266 .auto_corr_max_ofdm_mrc_x1 = 290, 267 268 .auto_corr_min_cck = 125, 269 .auto_corr_max_cck = 200, 270 .auto_corr_min_cck_mrc = 170, 271 .auto_corr_max_cck_mrc = 400, 272 .nrg_th_cck = 95, 273 .nrg_th_ofdm = 95, 274 275 .barker_corr_th_min = 190, 276 .barker_corr_th_min_mrc = 390, 277 .nrg_th_cca = 62, 278}; 279 280static struct iwl_sensitivity_ranges iwl5150_sensitivity = { 281 .min_nrg_cck = 95, 282 .max_nrg_cck = 0, /* not used, set to 0 */ 283 .auto_corr_min_ofdm = 90, 284 .auto_corr_min_ofdm_mrc = 170, 285 .auto_corr_min_ofdm_x1 = 105, 286 .auto_corr_min_ofdm_mrc_x1 = 220, 287 288 .auto_corr_max_ofdm = 120, 289 .auto_corr_max_ofdm_mrc = 210, 290 /* max = min for performance bug in 5150 DSP */ 291 .auto_corr_max_ofdm_x1 = 105, 292 .auto_corr_max_ofdm_mrc_x1 = 220, 293 294 .auto_corr_min_cck = 125, 295 .auto_corr_max_cck = 200, 296 .auto_corr_min_cck_mrc = 170, 297 .auto_corr_max_cck_mrc = 400, 298 .nrg_th_cck = 95, 299 .nrg_th_ofdm = 95, 300 301 .barker_corr_th_min = 190, 302 .barker_corr_th_min_mrc = 390, 303 .nrg_th_cca = 62, 304}; 305 306const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv, 307 size_t offset) 308{ 309 u32 address = eeprom_indirect_address(priv, offset); 310 BUG_ON(address >= priv->cfg->eeprom_size); 311 return &priv->eeprom[address]; 312} 313 314static void iwl5150_set_ct_threshold(struct iwl_priv *priv) 315{ 316 const s32 volt2temp_coef = IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF; 317 s32 threshold = (s32)CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD_LEGACY) - 318 iwl_temp_calib_to_offset(priv); 319 320 priv->hw_params.ct_kill_threshold = threshold * volt2temp_coef; 321} 322 323static void iwl5000_set_ct_threshold(struct iwl_priv *priv) 324{ 325 /* want Celsius */ 326 priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD_LEGACY; 327} 328 329/* 330 * Calibration 331 */ 332static int iwl5000_set_Xtal_calib(struct iwl_priv *priv) 333{ 334 struct iwl_calib_xtal_freq_cmd cmd; 335 u16 *xtal_calib = (u16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_XTAL); 336 337 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD; 338 cmd.hdr.first_group = 0; 339 cmd.hdr.groups_num = 1; 340 cmd.hdr.data_valid = 1; 341 cmd.cap_pin1 = (u8)xtal_calib[0]; 342 cmd.cap_pin2 = (u8)xtal_calib[1]; 343 return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL], 344 (u8 *)&cmd, sizeof(cmd)); 345} 346 347static int iwl5000_send_calib_cfg(struct iwl_priv *priv) 348{ 349 struct iwl_calib_cfg_cmd calib_cfg_cmd; 350 struct iwl_host_cmd cmd = { 351 .id = CALIBRATION_CFG_CMD, 352 .len = sizeof(struct iwl_calib_cfg_cmd), 353 .data = &calib_cfg_cmd, 354 }; 355 356 memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd)); 357 calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL; 358 calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL; 359 calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL; 360 calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL; 361 362 return iwl_send_cmd(priv, &cmd); 363} 364 365static void iwl5000_rx_calib_result(struct iwl_priv *priv, 366 struct iwl_rx_mem_buffer *rxb) 367{ 368 struct iwl_rx_packet *pkt = rxb_addr(rxb); 369 struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw; 370 int len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK; 371 int index; 372 373 /* reduce the size of the length field itself */ 374 len -= 4; 375 376 /* Define the order in which the results will be sent to the runtime 377 * uCode. iwl_send_calib_results sends them in a row according to their 378 * index. We sort them here */ 379 switch (hdr->op_code) { 380 case IWL_PHY_CALIBRATE_DC_CMD: 381 index = IWL_CALIB_DC; 382 break; 383 case IWL_PHY_CALIBRATE_LO_CMD: 384 index = IWL_CALIB_LO; 385 break; 386 case IWL_PHY_CALIBRATE_TX_IQ_CMD: 387 index = IWL_CALIB_TX_IQ; 388 break; 389 case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD: 390 index = IWL_CALIB_TX_IQ_PERD; 391 break; 392 case IWL_PHY_CALIBRATE_BASE_BAND_CMD: 393 index = IWL_CALIB_BASE_BAND; 394 break; 395 default: 396 IWL_ERR(priv, "Unknown calibration notification %d\n", 397 hdr->op_code); 398 return; 399 } 400 iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len); 401} 402 403static void iwl5000_rx_calib_complete(struct iwl_priv *priv, 404 struct iwl_rx_mem_buffer *rxb) 405{ 406 IWL_DEBUG_INFO(priv, "Init. calibration is completed, restarting fw.\n"); 407 queue_work(priv->workqueue, &priv->restart); 408} 409 410/* 411 * ucode 412 */ 413static int iwl5000_load_section(struct iwl_priv *priv, 414 struct fw_desc *image, 415 u32 dst_addr) 416{ 417 dma_addr_t phy_addr = image->p_addr; 418 u32 byte_cnt = image->len; 419 420 iwl_write_direct32(priv, 421 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 422 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); 423 424 iwl_write_direct32(priv, 425 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr); 426 427 iwl_write_direct32(priv, 428 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), 429 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); 430 431 iwl_write_direct32(priv, 432 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), 433 (iwl_get_dma_hi_addr(phy_addr) 434 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); 435 436 iwl_write_direct32(priv, 437 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), 438 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM | 439 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX | 440 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); 441 442 iwl_write_direct32(priv, 443 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 444 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 445 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | 446 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); 447 448 return 0; 449} 450 451static int iwl5000_load_given_ucode(struct iwl_priv *priv, 452 struct fw_desc *inst_image, 453 struct fw_desc *data_image) 454{ 455 int ret = 0; 456 457 ret = iwl5000_load_section(priv, inst_image, 458 IWL50_RTC_INST_LOWER_BOUND); 459 if (ret) 460 return ret; 461 462 IWL_DEBUG_INFO(priv, "INST uCode section being loaded...\n"); 463 ret = wait_event_interruptible_timeout(priv->wait_command_queue, 464 priv->ucode_write_complete, 5 * HZ); 465 if (ret == -ERESTARTSYS) { 466 IWL_ERR(priv, "Could not load the INST uCode section due " 467 "to interrupt\n"); 468 return ret; 469 } 470 if (!ret) { 471 IWL_ERR(priv, "Could not load the INST uCode section\n"); 472 return -ETIMEDOUT; 473 } 474 475 priv->ucode_write_complete = 0; 476 477 ret = iwl5000_load_section( 478 priv, data_image, IWL50_RTC_DATA_LOWER_BOUND); 479 if (ret) 480 return ret; 481 482 IWL_DEBUG_INFO(priv, "DATA uCode section being loaded...\n"); 483 484 ret = wait_event_interruptible_timeout(priv->wait_command_queue, 485 priv->ucode_write_complete, 5 * HZ); 486 if (ret == -ERESTARTSYS) { 487 IWL_ERR(priv, "Could not load the INST uCode section due " 488 "to interrupt\n"); 489 return ret; 490 } else if (!ret) { 491 IWL_ERR(priv, "Could not load the DATA uCode section\n"); 492 return -ETIMEDOUT; 493 } else 494 ret = 0; 495 496 priv->ucode_write_complete = 0; 497 498 return ret; 499} 500 501int iwl5000_load_ucode(struct iwl_priv *priv) 502{ 503 int ret = 0; 504 505 /* check whether init ucode should be loaded, or rather runtime ucode */ 506 if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) { 507 IWL_DEBUG_INFO(priv, "Init ucode found. Loading init ucode...\n"); 508 ret = iwl5000_load_given_ucode(priv, 509 &priv->ucode_init, &priv->ucode_init_data); 510 if (!ret) { 511 IWL_DEBUG_INFO(priv, "Init ucode load complete.\n"); 512 priv->ucode_type = UCODE_INIT; 513 } 514 } else { 515 IWL_DEBUG_INFO(priv, "Init ucode not found, or already loaded. " 516 "Loading runtime ucode...\n"); 517 ret = iwl5000_load_given_ucode(priv, 518 &priv->ucode_code, &priv->ucode_data); 519 if (!ret) { 520 IWL_DEBUG_INFO(priv, "Runtime ucode load complete.\n"); 521 priv->ucode_type = UCODE_RT; 522 } 523 } 524 525 return ret; 526} 527 528void iwl5000_init_alive_start(struct iwl_priv *priv) 529{ 530 int ret = 0; 531 532 /* Check alive response for "valid" sign from uCode */ 533 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) { 534 /* We had an error bringing up the hardware, so take it 535 * all the way back down so we can try again */ 536 IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n"); 537 goto restart; 538 } 539 540 /* initialize uCode was loaded... verify inst image. 541 * This is a paranoid check, because we would not have gotten the 542 * "initialize" alive if code weren't properly loaded. */ 543 if (iwl_verify_ucode(priv)) { 544 /* Runtime instruction load was bad; 545 * take it all the way back down so we can try again */ 546 IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n"); 547 goto restart; 548 } 549 550 iwl_clear_stations_table(priv); 551 ret = priv->cfg->ops->lib->alive_notify(priv); 552 if (ret) { 553 IWL_WARN(priv, 554 "Could not complete ALIVE transition: %d\n", ret); 555 goto restart; 556 } 557 558 iwl5000_send_calib_cfg(priv); 559 return; 560 561restart: 562 /* real restart (first load init_ucode) */ 563 queue_work(priv->workqueue, &priv->restart); 564} 565 566static void iwl5000_set_wr_ptrs(struct iwl_priv *priv, 567 int txq_id, u32 index) 568{ 569 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 570 (index & 0xff) | (txq_id << 8)); 571 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index); 572} 573 574static void iwl5000_tx_queue_set_status(struct iwl_priv *priv, 575 struct iwl_tx_queue *txq, 576 int tx_fifo_id, int scd_retry) 577{ 578 int txq_id = txq->q.id; 579 int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0; 580 581 iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id), 582 (active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) | 583 (tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) | 584 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) | 585 IWL50_SCD_QUEUE_STTS_REG_MSK); 586 587 txq->sched_retry = scd_retry; 588 589 IWL_DEBUG_INFO(priv, "%s %s Queue %d on AC %d\n", 590 active ? "Activate" : "Deactivate", 591 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id); 592} 593 594static int iwl5000_send_wimax_coex(struct iwl_priv *priv) 595{ 596 struct iwl_wimax_coex_cmd coex_cmd; 597 598 memset(&coex_cmd, 0, sizeof(coex_cmd)); 599 600 return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD, 601 sizeof(coex_cmd), &coex_cmd); 602} 603 604int iwl5000_alive_notify(struct iwl_priv *priv) 605{ 606 u32 a; 607 unsigned long flags; 608 int i, chan; 609 u32 reg_val; 610 611 spin_lock_irqsave(&priv->lock, flags); 612 613 priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR); 614 a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET; 615 for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET; 616 a += 4) 617 iwl_write_targ_mem(priv, a, 0); 618 for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET; 619 a += 4) 620 iwl_write_targ_mem(priv, a, 0); 621 for (; a < priv->scd_base_addr + 622 IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(priv->hw_params.max_txq_num); a += 4) 623 iwl_write_targ_mem(priv, a, 0); 624 625 iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR, 626 priv->scd_bc_tbls.dma >> 10); 627 628 /* Enable DMA channel */ 629 for (chan = 0; chan < FH50_TCSR_CHNL_NUM ; chan++) 630 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan), 631 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 632 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE); 633 634 /* Update FH chicken bits */ 635 reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG); 636 iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG, 637 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN); 638 639 iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, 640 IWL50_SCD_QUEUECHAIN_SEL_ALL(priv->hw_params.max_txq_num)); 641 iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0); 642 643 /* initiate the queues */ 644 for (i = 0; i < priv->hw_params.max_txq_num; i++) { 645 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0); 646 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8)); 647 iwl_write_targ_mem(priv, priv->scd_base_addr + 648 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0); 649 iwl_write_targ_mem(priv, priv->scd_base_addr + 650 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) + 651 sizeof(u32), 652 ((SCD_WIN_SIZE << 653 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & 654 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | 655 ((SCD_FRAME_LIMIT << 656 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & 657 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); 658 } 659 660 iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK, 661 IWL_MASK(0, priv->hw_params.max_txq_num)); 662 663 /* Activate all Tx DMA/FIFO channels */ 664 priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7)); 665 666 iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0); 667 668 /* map qos queues to fifos one-to-one */ 669 for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) { 670 int ac = iwl5000_default_queue_to_tx_fifo[i]; 671 iwl_txq_ctx_activate(priv, i); 672 iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0); 673 } 674 /* TODO - need to initialize those FIFOs inside the loop above, 675 * not only mark them as active */ 676 iwl_txq_ctx_activate(priv, 4); 677 iwl_txq_ctx_activate(priv, 7); 678 iwl_txq_ctx_activate(priv, 8); 679 iwl_txq_ctx_activate(priv, 9); 680 681 spin_unlock_irqrestore(&priv->lock, flags); 682 683 684 iwl5000_send_wimax_coex(priv); 685 686 iwl5000_set_Xtal_calib(priv); 687 iwl_send_calib_results(priv); 688 689 return 0; 690} 691 692int iwl5000_hw_set_hw_params(struct iwl_priv *priv) 693{ 694 if (priv->cfg->mod_params->num_of_queues >= IWL_MIN_NUM_QUEUES && 695 priv->cfg->mod_params->num_of_queues <= IWL50_NUM_QUEUES) 696 priv->cfg->num_of_queues = 697 priv->cfg->mod_params->num_of_queues; 698 699 priv->hw_params.max_txq_num = priv->cfg->num_of_queues; 700 priv->hw_params.dma_chnl_num = FH50_TCSR_CHNL_NUM; 701 priv->hw_params.scd_bc_tbls_size = 702 priv->cfg->num_of_queues * 703 sizeof(struct iwl5000_scd_bc_tbl); 704 priv->hw_params.tfd_size = sizeof(struct iwl_tfd); 705 priv->hw_params.max_stations = IWL5000_STATION_COUNT; 706 priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID; 707 708 priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE; 709 priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE; 710 711 priv->hw_params.max_bsm_size = 0; 712 priv->hw_params.ht40_channel = BIT(IEEE80211_BAND_2GHZ) | 713 BIT(IEEE80211_BAND_5GHZ); 714 priv->hw_params.rx_wrt_ptr_reg = FH_RSCSR_CHNL0_WPTR; 715 716 priv->hw_params.tx_chains_num = num_of_ant(priv->cfg->valid_tx_ant); 717 priv->hw_params.rx_chains_num = num_of_ant(priv->cfg->valid_rx_ant); 718 priv->hw_params.valid_tx_ant = priv->cfg->valid_tx_ant; 719 priv->hw_params.valid_rx_ant = priv->cfg->valid_rx_ant; 720 721 if (priv->cfg->ops->lib->temp_ops.set_ct_kill) 722 priv->cfg->ops->lib->temp_ops.set_ct_kill(priv); 723 724 /* Set initial sensitivity parameters */ 725 /* Set initial calibration set */ 726 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) { 727 case CSR_HW_REV_TYPE_5150: 728 priv->hw_params.sens = &iwl5150_sensitivity; 729 priv->hw_params.calib_init_cfg = 730 BIT(IWL_CALIB_DC) | 731 BIT(IWL_CALIB_LO) | 732 BIT(IWL_CALIB_TX_IQ) | 733 BIT(IWL_CALIB_BASE_BAND); 734 735 break; 736 default: 737 priv->hw_params.sens = &iwl5000_sensitivity; 738 priv->hw_params.calib_init_cfg = 739 BIT(IWL_CALIB_XTAL) | 740 BIT(IWL_CALIB_LO) | 741 BIT(IWL_CALIB_TX_IQ) | 742 BIT(IWL_CALIB_TX_IQ_PERD) | 743 BIT(IWL_CALIB_BASE_BAND); 744 break; 745 } 746 747 return 0; 748} 749 750/** 751 * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array 752 */ 753void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv, 754 struct iwl_tx_queue *txq, 755 u16 byte_cnt) 756{ 757 struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr; 758 int write_ptr = txq->q.write_ptr; 759 int txq_id = txq->q.id; 760 u8 sec_ctl = 0; 761 u8 sta_id = 0; 762 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE; 763 __le16 bc_ent; 764 765 WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX); 766 767 if (txq_id != IWL_CMD_QUEUE_NUM) { 768 sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id; 769 sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl; 770 771 switch (sec_ctl & TX_CMD_SEC_MSK) { 772 case TX_CMD_SEC_CCM: 773 len += CCMP_MIC_LEN; 774 break; 775 case TX_CMD_SEC_TKIP: 776 len += TKIP_ICV_LEN; 777 break; 778 case TX_CMD_SEC_WEP: 779 len += WEP_IV_LEN + WEP_ICV_LEN; 780 break; 781 } 782 } 783 784 bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12)); 785 786 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent; 787 788 if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP) 789 scd_bc_tbl[txq_id]. 790 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent; 791} 792 793void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv, 794 struct iwl_tx_queue *txq) 795{ 796 struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr; 797 int txq_id = txq->q.id; 798 int read_ptr = txq->q.read_ptr; 799 u8 sta_id = 0; 800 __le16 bc_ent; 801 802 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX); 803 804 if (txq_id != IWL_CMD_QUEUE_NUM) 805 sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id; 806 807 bc_ent = cpu_to_le16(1 | (sta_id << 12)); 808 scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent; 809 810 if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP) 811 scd_bc_tbl[txq_id]. 812 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent; 813} 814 815static int iwl5000_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid, 816 u16 txq_id) 817{ 818 u32 tbl_dw_addr; 819 u32 tbl_dw; 820 u16 scd_q2ratid; 821 822 scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK; 823 824 tbl_dw_addr = priv->scd_base_addr + 825 IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id); 826 827 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr); 828 829 if (txq_id & 0x1) 830 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF); 831 else 832 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000); 833 834 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw); 835 836 return 0; 837} 838static void iwl5000_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id) 839{ 840 /* Simply stop the queue, but don't change any configuration; 841 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */ 842 iwl_write_prph(priv, 843 IWL50_SCD_QUEUE_STATUS_BITS(txq_id), 844 (0 << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE)| 845 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN)); 846} 847 848int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id, 849 int tx_fifo, int sta_id, int tid, u16 ssn_idx) 850{ 851 unsigned long flags; 852 u16 ra_tid; 853 854 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) || 855 (IWL50_FIRST_AMPDU_QUEUE + priv->cfg->num_of_ampdu_queues 856 <= txq_id)) { 857 IWL_WARN(priv, 858 "queue number out of range: %d, must be %d to %d\n", 859 txq_id, IWL50_FIRST_AMPDU_QUEUE, 860 IWL50_FIRST_AMPDU_QUEUE + 861 priv->cfg->num_of_ampdu_queues - 1); 862 return -EINVAL; 863 } 864 865 ra_tid = BUILD_RAxTID(sta_id, tid); 866 867 /* Modify device's station table to Tx this TID */ 868 iwl_sta_tx_modify_enable_tid(priv, sta_id, tid); 869 870 spin_lock_irqsave(&priv->lock, flags); 871 872 /* Stop this Tx queue before configuring it */ 873 iwl5000_tx_queue_stop_scheduler(priv, txq_id); 874 875 /* Map receiver-address / traffic-ID to this queue */ 876 iwl5000_tx_queue_set_q2ratid(priv, ra_tid, txq_id); 877 878 /* Set this queue as a chain-building queue */ 879 iwl_set_bits_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, (1<<txq_id)); 880 881 /* enable aggregations for the queue */ 882 iwl_set_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1<<txq_id)); 883 884 /* Place first TFD at index corresponding to start sequence number. 885 * Assumes that ssn_idx is valid (!= 0xFFF) */ 886 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff); 887 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff); 888 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx); 889 890 /* Set up Tx window size and frame limit for this queue */ 891 iwl_write_targ_mem(priv, priv->scd_base_addr + 892 IWL50_SCD_CONTEXT_QUEUE_OFFSET(txq_id) + 893 sizeof(u32), 894 ((SCD_WIN_SIZE << 895 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & 896 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | 897 ((SCD_FRAME_LIMIT << 898 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & 899 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); 900 901 iwl_set_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id)); 902 903 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */ 904 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1); 905 906 spin_unlock_irqrestore(&priv->lock, flags); 907 908 return 0; 909} 910 911int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id, 912 u16 ssn_idx, u8 tx_fifo) 913{ 914 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) || 915 (IWL50_FIRST_AMPDU_QUEUE + priv->cfg->num_of_ampdu_queues 916 <= txq_id)) { 917 IWL_ERR(priv, 918 "queue number out of range: %d, must be %d to %d\n", 919 txq_id, IWL50_FIRST_AMPDU_QUEUE, 920 IWL50_FIRST_AMPDU_QUEUE + 921 priv->cfg->num_of_ampdu_queues - 1); 922 return -EINVAL; 923 } 924 925 iwl5000_tx_queue_stop_scheduler(priv, txq_id); 926 927 iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id)); 928 929 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff); 930 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff); 931 /* supposes that ssn_idx is valid (!= 0xFFF) */ 932 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx); 933 934 iwl_clear_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id)); 935 iwl_txq_ctx_deactivate(priv, txq_id); 936 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0); 937 938 return 0; 939} 940 941u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data) 942{ 943 u16 size = (u16)sizeof(struct iwl_addsta_cmd); 944 struct iwl_addsta_cmd *addsta = (struct iwl_addsta_cmd *)data; 945 memcpy(addsta, cmd, size); 946 /* resrved in 5000 */ 947 addsta->rate_n_flags = cpu_to_le16(0); 948 return size; 949} 950 951 952/* 953 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask 954 * must be called under priv->lock and mac access 955 */ 956void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask) 957{ 958 iwl_write_prph(priv, IWL50_SCD_TXFACT, mask); 959} 960 961 962static inline u32 iwl5000_get_scd_ssn(struct iwl5000_tx_resp *tx_resp) 963{ 964 return le32_to_cpup((__le32 *)&tx_resp->status + 965 tx_resp->frame_count) & MAX_SN; 966} 967 968static int iwl5000_tx_status_reply_tx(struct iwl_priv *priv, 969 struct iwl_ht_agg *agg, 970 struct iwl5000_tx_resp *tx_resp, 971 int txq_id, u16 start_idx) 972{ 973 u16 status; 974 struct agg_tx_status *frame_status = &tx_resp->status; 975 struct ieee80211_tx_info *info = NULL; 976 struct ieee80211_hdr *hdr = NULL; 977 u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags); 978 int i, sh, idx; 979 u16 seq; 980 981 if (agg->wait_for_ba) 982 IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n"); 983 984 agg->frame_count = tx_resp->frame_count; 985 agg->start_idx = start_idx; 986 agg->rate_n_flags = rate_n_flags; 987 agg->bitmap = 0; 988 989 /* # frames attempted by Tx command */ 990 if (agg->frame_count == 1) { 991 /* Only one frame was attempted; no block-ack will arrive */ 992 status = le16_to_cpu(frame_status[0].status); 993 idx = start_idx; 994 995 /* FIXME: code repetition */ 996 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n", 997 agg->frame_count, agg->start_idx, idx); 998 999 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]); 1000 info->status.rates[0].count = tx_resp->failure_frame + 1; 1001 info->flags &= ~IEEE80211_TX_CTL_AMPDU; 1002 info->flags |= iwl_is_tx_success(status) ? 1003 IEEE80211_TX_STAT_ACK : 0; 1004 iwl_hwrate_to_tx_control(priv, rate_n_flags, info); 1005 1006 /* FIXME: code repetition end */ 1007 1008 IWL_DEBUG_TX_REPLY(priv, "1 Frame 0x%x failure :%d\n", 1009 status & 0xff, tx_resp->failure_frame); 1010 IWL_DEBUG_TX_REPLY(priv, "Rate Info rate_n_flags=%x\n", rate_n_flags); 1011 1012 agg->wait_for_ba = 0; 1013 } else { 1014 /* Two or more frames were attempted; expect block-ack */ 1015 u64 bitmap = 0; 1016 int start = agg->start_idx; 1017 1018 /* Construct bit-map of pending frames within Tx window */ 1019 for (i = 0; i < agg->frame_count; i++) { 1020 u16 sc; 1021 status = le16_to_cpu(frame_status[i].status); 1022 seq = le16_to_cpu(frame_status[i].sequence); 1023 idx = SEQ_TO_INDEX(seq); 1024 txq_id = SEQ_TO_QUEUE(seq); 1025 1026 if (status & (AGG_TX_STATE_FEW_BYTES_MSK | 1027 AGG_TX_STATE_ABORT_MSK)) 1028 continue; 1029 1030 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n", 1031 agg->frame_count, txq_id, idx); 1032 1033 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx); 1034 if (!hdr) { 1035 IWL_ERR(priv, 1036 "BUG_ON idx doesn't point to valid skb" 1037 " idx=%d, txq_id=%d\n", idx, txq_id); 1038 return -1; 1039 } 1040 1041 sc = le16_to_cpu(hdr->seq_ctrl); 1042 if (idx != (SEQ_TO_SN(sc) & 0xff)) { 1043 IWL_ERR(priv, 1044 "BUG_ON idx doesn't match seq control" 1045 " idx=%d, seq_idx=%d, seq=%d\n", 1046 idx, SEQ_TO_SN(sc), 1047 hdr->seq_ctrl); 1048 return -1; 1049 } 1050 1051 IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n", 1052 i, idx, SEQ_TO_SN(sc)); 1053 1054 sh = idx - start; 1055 if (sh > 64) { 1056 sh = (start - idx) + 0xff; 1057 bitmap = bitmap << sh; 1058 sh = 0; 1059 start = idx; 1060 } else if (sh < -64) 1061 sh = 0xff - (start - idx); 1062 else if (sh < 0) { 1063 sh = start - idx; 1064 start = idx; 1065 bitmap = bitmap << sh; 1066 sh = 0; 1067 } 1068 bitmap |= 1ULL << sh; 1069 IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n", 1070 start, (unsigned long long)bitmap); 1071 } 1072 1073 agg->bitmap = bitmap; 1074 agg->start_idx = start; 1075 IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n", 1076 agg->frame_count, agg->start_idx, 1077 (unsigned long long)agg->bitmap); 1078 1079 if (bitmap) 1080 agg->wait_for_ba = 1; 1081 } 1082 return 0; 1083} 1084 1085static void iwl5000_rx_reply_tx(struct iwl_priv *priv, 1086 struct iwl_rx_mem_buffer *rxb) 1087{ 1088 struct iwl_rx_packet *pkt = rxb_addr(rxb); 1089 u16 sequence = le16_to_cpu(pkt->hdr.sequence); 1090 int txq_id = SEQ_TO_QUEUE(sequence); 1091 int index = SEQ_TO_INDEX(sequence); 1092 struct iwl_tx_queue *txq = &priv->txq[txq_id]; 1093 struct ieee80211_tx_info *info; 1094 struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0]; 1095 u32 status = le16_to_cpu(tx_resp->status.status); 1096 int tid; 1097 int sta_id; 1098 int freed; 1099 1100 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) { 1101 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d " 1102 "is out of range [0-%d] %d %d\n", txq_id, 1103 index, txq->q.n_bd, txq->q.write_ptr, 1104 txq->q.read_ptr); 1105 return; 1106 } 1107 1108 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]); 1109 memset(&info->status, 0, sizeof(info->status)); 1110 1111 tid = (tx_resp->ra_tid & IWL50_TX_RES_TID_MSK) >> IWL50_TX_RES_TID_POS; 1112 sta_id = (tx_resp->ra_tid & IWL50_TX_RES_RA_MSK) >> IWL50_TX_RES_RA_POS; 1113 1114 if (txq->sched_retry) { 1115 const u32 scd_ssn = iwl5000_get_scd_ssn(tx_resp); 1116 struct iwl_ht_agg *agg = NULL; 1117 1118 agg = &priv->stations[sta_id].tid[tid].agg; 1119 1120 iwl5000_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index); 1121 1122 /* check if BAR is needed */ 1123 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status)) 1124 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK; 1125 1126 if (txq->q.read_ptr != (scd_ssn & 0xff)) { 1127 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd); 1128 IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim " 1129 "scd_ssn=%d idx=%d txq=%d swq=%d\n", 1130 scd_ssn , index, txq_id, txq->swq_id); 1131 1132 freed = iwl_tx_queue_reclaim(priv, txq_id, index); 1133 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed; 1134 1135 if (priv->mac80211_registered && 1136 (iwl_queue_space(&txq->q) > txq->q.low_mark) && 1137 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) { 1138 if (agg->state == IWL_AGG_OFF) 1139 iwl_wake_queue(priv, txq_id); 1140 else 1141 iwl_wake_queue(priv, txq->swq_id); 1142 } 1143 } 1144 } else { 1145 BUG_ON(txq_id != txq->swq_id); 1146 1147 info->status.rates[0].count = tx_resp->failure_frame + 1; 1148 info->flags |= iwl_is_tx_success(status) ? 1149 IEEE80211_TX_STAT_ACK : 0; 1150 iwl_hwrate_to_tx_control(priv, 1151 le32_to_cpu(tx_resp->rate_n_flags), 1152 info); 1153 1154 IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) rate_n_flags " 1155 "0x%x retries %d\n", 1156 txq_id, 1157 iwl_get_tx_fail_reason(status), status, 1158 le32_to_cpu(tx_resp->rate_n_flags), 1159 tx_resp->failure_frame); 1160 1161 freed = iwl_tx_queue_reclaim(priv, txq_id, index); 1162 if (ieee80211_is_data_qos(tx_resp->frame_ctrl)) 1163 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed; 1164 1165 if (priv->mac80211_registered && 1166 (iwl_queue_space(&txq->q) > txq->q.low_mark)) 1167 iwl_wake_queue(priv, txq_id); 1168 } 1169 1170 if (ieee80211_is_data_qos(tx_resp->frame_ctrl)) 1171 iwl_txq_check_empty(priv, sta_id, tid, txq_id); 1172 1173 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK)) 1174 IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n"); 1175} 1176 1177/* Currently 5000 is the superset of everything */ 1178u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len) 1179{ 1180 return len; 1181} 1182 1183void iwl5000_setup_deferred_work(struct iwl_priv *priv) 1184{ 1185 /* in 5000 the tx power calibration is done in uCode */ 1186 priv->disable_tx_power_cal = 1; 1187} 1188 1189void iwl5000_rx_handler_setup(struct iwl_priv *priv) 1190{ 1191 /* init calibration handlers */ 1192 priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] = 1193 iwl5000_rx_calib_result; 1194 priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] = 1195 iwl5000_rx_calib_complete; 1196 priv->rx_handlers[REPLY_TX] = iwl5000_rx_reply_tx; 1197} 1198 1199 1200int iwl5000_hw_valid_rtc_data_addr(u32 addr) 1201{ 1202 return (addr >= IWL50_RTC_DATA_LOWER_BOUND) && 1203 (addr < IWL50_RTC_DATA_UPPER_BOUND); 1204} 1205 1206static int iwl5000_send_rxon_assoc(struct iwl_priv *priv) 1207{ 1208 int ret = 0; 1209 struct iwl5000_rxon_assoc_cmd rxon_assoc; 1210 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon; 1211 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon; 1212 1213 if ((rxon1->flags == rxon2->flags) && 1214 (rxon1->filter_flags == rxon2->filter_flags) && 1215 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) && 1216 (rxon1->ofdm_ht_single_stream_basic_rates == 1217 rxon2->ofdm_ht_single_stream_basic_rates) && 1218 (rxon1->ofdm_ht_dual_stream_basic_rates == 1219 rxon2->ofdm_ht_dual_stream_basic_rates) && 1220 (rxon1->ofdm_ht_triple_stream_basic_rates == 1221 rxon2->ofdm_ht_triple_stream_basic_rates) && 1222 (rxon1->acquisition_data == rxon2->acquisition_data) && 1223 (rxon1->rx_chain == rxon2->rx_chain) && 1224 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) { 1225 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC. Not resending.\n"); 1226 return 0; 1227 } 1228 1229 rxon_assoc.flags = priv->staging_rxon.flags; 1230 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags; 1231 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates; 1232 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates; 1233 rxon_assoc.reserved1 = 0; 1234 rxon_assoc.reserved2 = 0; 1235 rxon_assoc.reserved3 = 0; 1236 rxon_assoc.ofdm_ht_single_stream_basic_rates = 1237 priv->staging_rxon.ofdm_ht_single_stream_basic_rates; 1238 rxon_assoc.ofdm_ht_dual_stream_basic_rates = 1239 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates; 1240 rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain; 1241 rxon_assoc.ofdm_ht_triple_stream_basic_rates = 1242 priv->staging_rxon.ofdm_ht_triple_stream_basic_rates; 1243 rxon_assoc.acquisition_data = priv->staging_rxon.acquisition_data; 1244 1245 ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC, 1246 sizeof(rxon_assoc), &rxon_assoc, NULL); 1247 if (ret) 1248 return ret; 1249 1250 return ret; 1251} 1252int iwl5000_send_tx_power(struct iwl_priv *priv) 1253{ 1254 struct iwl5000_tx_power_dbm_cmd tx_power_cmd; 1255 u8 tx_ant_cfg_cmd; 1256 1257 /* half dBm need to multiply */ 1258 tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt); 1259 tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED; 1260 tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO; 1261 1262 if (IWL_UCODE_API(priv->ucode_ver) == 1) 1263 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD_V1; 1264 else 1265 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD; 1266 1267 return iwl_send_cmd_pdu_async(priv, tx_ant_cfg_cmd, 1268 sizeof(tx_power_cmd), &tx_power_cmd, 1269 NULL); 1270} 1271 1272void iwl5000_temperature(struct iwl_priv *priv) 1273{ 1274 /* store temperature from statistics (in Celsius) */ 1275 priv->temperature = le32_to_cpu(priv->statistics.general.temperature); 1276 iwl_tt_handler(priv); 1277} 1278 1279static void iwl5150_temperature(struct iwl_priv *priv) 1280{ 1281 u32 vt = 0; 1282 s32 offset = iwl_temp_calib_to_offset(priv); 1283 1284 vt = le32_to_cpu(priv->statistics.general.temperature); 1285 vt = vt / IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF + offset; 1286 /* now vt hold the temperature in Kelvin */ 1287 priv->temperature = KELVIN_TO_CELSIUS(vt); 1288 iwl_tt_handler(priv); 1289} 1290 1291/* Calc max signal level (dBm) among 3 possible receivers */ 1292int iwl5000_calc_rssi(struct iwl_priv *priv, 1293 struct iwl_rx_phy_res *rx_resp) 1294{ 1295 /* data from PHY/DSP regarding signal strength, etc., 1296 * contents are always there, not configurable by host 1297 */ 1298 struct iwl5000_non_cfg_phy *ncphy = 1299 (struct iwl5000_non_cfg_phy *)rx_resp->non_cfg_phy_buf; 1300 u32 val, rssi_a, rssi_b, rssi_c, max_rssi; 1301 u8 agc; 1302 1303 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_AGC_IDX]); 1304 agc = (val & IWL50_OFDM_AGC_MSK) >> IWL50_OFDM_AGC_BIT_POS; 1305 1306 /* Find max rssi among 3 possible receivers. 1307 * These values are measured by the digital signal processor (DSP). 1308 * They should stay fairly constant even as the signal strength varies, 1309 * if the radio's automatic gain control (AGC) is working right. 1310 * AGC value (see below) will provide the "interesting" info. 1311 */ 1312 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_AB_IDX]); 1313 rssi_a = (val & IWL50_OFDM_RSSI_A_MSK) >> IWL50_OFDM_RSSI_A_BIT_POS; 1314 rssi_b = (val & IWL50_OFDM_RSSI_B_MSK) >> IWL50_OFDM_RSSI_B_BIT_POS; 1315 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_C_IDX]); 1316 rssi_c = (val & IWL50_OFDM_RSSI_C_MSK) >> IWL50_OFDM_RSSI_C_BIT_POS; 1317 1318 max_rssi = max_t(u32, rssi_a, rssi_b); 1319 max_rssi = max_t(u32, max_rssi, rssi_c); 1320 1321 IWL_DEBUG_STATS(priv, "Rssi In A %d B %d C %d Max %d AGC dB %d\n", 1322 rssi_a, rssi_b, rssi_c, max_rssi, agc); 1323 1324 /* dBm = max_rssi dB - agc dB - constant. 1325 * Higher AGC (higher radio gain) means lower signal. */ 1326 return max_rssi - agc - IWL49_RSSI_OFFSET; 1327} 1328 1329static int iwl5000_send_tx_ant_config(struct iwl_priv *priv, u8 valid_tx_ant) 1330{ 1331 struct iwl_tx_ant_config_cmd tx_ant_cmd = { 1332 .valid = cpu_to_le32(valid_tx_ant), 1333 }; 1334 1335 if (IWL_UCODE_API(priv->ucode_ver) > 1) { 1336 IWL_DEBUG_HC(priv, "select valid tx ant: %u\n", valid_tx_ant); 1337 return iwl_send_cmd_pdu(priv, TX_ANT_CONFIGURATION_CMD, 1338 sizeof(struct iwl_tx_ant_config_cmd), 1339 &tx_ant_cmd); 1340 } else { 1341 IWL_DEBUG_HC(priv, "TX_ANT_CONFIGURATION_CMD not supported\n"); 1342 return -EOPNOTSUPP; 1343 } 1344} 1345 1346 1347#define IWL5000_UCODE_GET(item) \ 1348static u32 iwl5000_ucode_get_##item(const struct iwl_ucode_header *ucode,\ 1349 u32 api_ver) \ 1350{ \ 1351 if (api_ver <= 2) \ 1352 return le32_to_cpu(ucode->u.v1.item); \ 1353 return le32_to_cpu(ucode->u.v2.item); \ 1354} 1355 1356static u32 iwl5000_ucode_get_header_size(u32 api_ver) 1357{ 1358 if (api_ver <= 2) 1359 return UCODE_HEADER_SIZE(1); 1360 return UCODE_HEADER_SIZE(2); 1361} 1362 1363static u32 iwl5000_ucode_get_build(const struct iwl_ucode_header *ucode, 1364 u32 api_ver) 1365{ 1366 if (api_ver <= 2) 1367 return 0; 1368 return le32_to_cpu(ucode->u.v2.build); 1369} 1370 1371static u8 *iwl5000_ucode_get_data(const struct iwl_ucode_header *ucode, 1372 u32 api_ver) 1373{ 1374 if (api_ver <= 2) 1375 return (u8 *) ucode->u.v1.data; 1376 return (u8 *) ucode->u.v2.data; 1377} 1378 1379IWL5000_UCODE_GET(inst_size); 1380IWL5000_UCODE_GET(data_size); 1381IWL5000_UCODE_GET(init_size); 1382IWL5000_UCODE_GET(init_data_size); 1383IWL5000_UCODE_GET(boot_size); 1384 1385struct iwl_hcmd_ops iwl5000_hcmd = { 1386 .rxon_assoc = iwl5000_send_rxon_assoc, 1387 .commit_rxon = iwl_commit_rxon, 1388 .set_rxon_chain = iwl_set_rxon_chain, 1389 .set_tx_ant = iwl5000_send_tx_ant_config, 1390}; 1391 1392struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = { 1393 .get_hcmd_size = iwl5000_get_hcmd_size, 1394 .build_addsta_hcmd = iwl5000_build_addsta_hcmd, 1395 .gain_computation = iwl5000_gain_computation, 1396 .chain_noise_reset = iwl5000_chain_noise_reset, 1397 .rts_tx_cmd_flag = iwl5000_rts_tx_cmd_flag, 1398 .calc_rssi = iwl5000_calc_rssi, 1399}; 1400 1401struct iwl_ucode_ops iwl5000_ucode = { 1402 .get_header_size = iwl5000_ucode_get_header_size, 1403 .get_build = iwl5000_ucode_get_build, 1404 .get_inst_size = iwl5000_ucode_get_inst_size, 1405 .get_data_size = iwl5000_ucode_get_data_size, 1406 .get_init_size = iwl5000_ucode_get_init_size, 1407 .get_init_data_size = iwl5000_ucode_get_init_data_size, 1408 .get_boot_size = iwl5000_ucode_get_boot_size, 1409 .get_data = iwl5000_ucode_get_data, 1410}; 1411 1412struct iwl_lib_ops iwl5000_lib = { 1413 .set_hw_params = iwl5000_hw_set_hw_params, 1414 .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl, 1415 .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl, 1416 .txq_set_sched = iwl5000_txq_set_sched, 1417 .txq_agg_enable = iwl5000_txq_agg_enable, 1418 .txq_agg_disable = iwl5000_txq_agg_disable, 1419 .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd, 1420 .txq_free_tfd = iwl_hw_txq_free_tfd, 1421 .txq_init = iwl_hw_tx_queue_init, 1422 .rx_handler_setup = iwl5000_rx_handler_setup, 1423 .setup_deferred_work = iwl5000_setup_deferred_work, 1424 .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr, 1425 .dump_nic_event_log = iwl_dump_nic_event_log, 1426 .dump_nic_error_log = iwl_dump_nic_error_log, 1427 .load_ucode = iwl5000_load_ucode, 1428 .init_alive_start = iwl5000_init_alive_start, 1429 .alive_notify = iwl5000_alive_notify, 1430 .send_tx_power = iwl5000_send_tx_power, 1431 .update_chain_flags = iwl_update_chain_flags, 1432 .apm_ops = { 1433 .init = iwl_apm_init, 1434 .stop = iwl_apm_stop, 1435 .config = iwl5000_nic_config, 1436 .set_pwr_src = iwl_set_pwr_src, 1437 }, 1438 .eeprom_ops = { 1439 .regulatory_bands = { 1440 EEPROM_5000_REG_BAND_1_CHANNELS, 1441 EEPROM_5000_REG_BAND_2_CHANNELS, 1442 EEPROM_5000_REG_BAND_3_CHANNELS, 1443 EEPROM_5000_REG_BAND_4_CHANNELS, 1444 EEPROM_5000_REG_BAND_5_CHANNELS, 1445 EEPROM_5000_REG_BAND_24_HT40_CHANNELS, 1446 EEPROM_5000_REG_BAND_52_HT40_CHANNELS 1447 }, 1448 .verify_signature = iwlcore_eeprom_verify_signature, 1449 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore, 1450 .release_semaphore = iwlcore_eeprom_release_semaphore, 1451 .calib_version = iwl5000_eeprom_calib_version, 1452 .query_addr = iwl5000_eeprom_query_addr, 1453 }, 1454 .post_associate = iwl_post_associate, 1455 .isr = iwl_isr_ict, 1456 .config_ap = iwl_config_ap, 1457 .temp_ops = { 1458 .temperature = iwl5000_temperature, 1459 .set_ct_kill = iwl5000_set_ct_threshold, 1460 }, 1461}; 1462 1463static struct iwl_lib_ops iwl5150_lib = { 1464 .set_hw_params = iwl5000_hw_set_hw_params, 1465 .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl, 1466 .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl, 1467 .txq_set_sched = iwl5000_txq_set_sched, 1468 .txq_agg_enable = iwl5000_txq_agg_enable, 1469 .txq_agg_disable = iwl5000_txq_agg_disable, 1470 .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd, 1471 .txq_free_tfd = iwl_hw_txq_free_tfd, 1472 .txq_init = iwl_hw_tx_queue_init, 1473 .rx_handler_setup = iwl5000_rx_handler_setup, 1474 .setup_deferred_work = iwl5000_setup_deferred_work, 1475 .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr, 1476 .dump_nic_event_log = iwl_dump_nic_event_log, 1477 .dump_nic_error_log = iwl_dump_nic_error_log, 1478 .load_ucode = iwl5000_load_ucode, 1479 .init_alive_start = iwl5000_init_alive_start, 1480 .alive_notify = iwl5000_alive_notify, 1481 .send_tx_power = iwl5000_send_tx_power, 1482 .update_chain_flags = iwl_update_chain_flags, 1483 .apm_ops = { 1484 .init = iwl_apm_init, 1485 .stop = iwl_apm_stop, 1486 .config = iwl5000_nic_config, 1487 .set_pwr_src = iwl_set_pwr_src, 1488 }, 1489 .eeprom_ops = { 1490 .regulatory_bands = { 1491 EEPROM_5000_REG_BAND_1_CHANNELS, 1492 EEPROM_5000_REG_BAND_2_CHANNELS, 1493 EEPROM_5000_REG_BAND_3_CHANNELS, 1494 EEPROM_5000_REG_BAND_4_CHANNELS, 1495 EEPROM_5000_REG_BAND_5_CHANNELS, 1496 EEPROM_5000_REG_BAND_24_HT40_CHANNELS, 1497 EEPROM_5000_REG_BAND_52_HT40_CHANNELS 1498 }, 1499 .verify_signature = iwlcore_eeprom_verify_signature, 1500 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore, 1501 .release_semaphore = iwlcore_eeprom_release_semaphore, 1502 .calib_version = iwl5000_eeprom_calib_version, 1503 .query_addr = iwl5000_eeprom_query_addr, 1504 }, 1505 .post_associate = iwl_post_associate, 1506 .isr = iwl_isr_ict, 1507 .config_ap = iwl_config_ap, 1508 .temp_ops = { 1509 .temperature = iwl5150_temperature, 1510 .set_ct_kill = iwl5150_set_ct_threshold, 1511 }, 1512}; 1513 1514static struct iwl_ops iwl5000_ops = { 1515 .ucode = &iwl5000_ucode, 1516 .lib = &iwl5000_lib, 1517 .hcmd = &iwl5000_hcmd, 1518 .utils = &iwl5000_hcmd_utils, 1519 .led = &iwlagn_led_ops, 1520}; 1521 1522static struct iwl_ops iwl5150_ops = { 1523 .ucode = &iwl5000_ucode, 1524 .lib = &iwl5150_lib, 1525 .hcmd = &iwl5000_hcmd, 1526 .utils = &iwl5000_hcmd_utils, 1527 .led = &iwlagn_led_ops, 1528}; 1529 1530struct iwl_mod_params iwl50_mod_params = { 1531 .amsdu_size_8K = 1, 1532 .restart_fw = 1, 1533 /* the rest are 0 by default */ 1534}; 1535 1536 1537struct iwl_cfg iwl5300_agn_cfg = { 1538 .name = "5300AGN", 1539 .fw_name_pre = IWL5000_FW_PRE, 1540 .ucode_api_max = IWL5000_UCODE_API_MAX, 1541 .ucode_api_min = IWL5000_UCODE_API_MIN, 1542 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N, 1543 .ops = &iwl5000_ops, 1544 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, 1545 .eeprom_ver = EEPROM_5000_EEPROM_VERSION, 1546 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION, 1547 .num_of_queues = IWL50_NUM_QUEUES, 1548 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES, 1549 .mod_params = &iwl50_mod_params, 1550 .valid_tx_ant = ANT_ABC, 1551 .valid_rx_ant = ANT_ABC, 1552 .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL, 1553 .set_l0s = true, 1554 .use_bsm = false, 1555 .ht_greenfield_support = true, 1556 .led_compensation = 51, 1557 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS, 1558}; 1559 1560struct iwl_cfg iwl5100_bg_cfg = { 1561 .name = "5100BG", 1562 .fw_name_pre = IWL5000_FW_PRE, 1563 .ucode_api_max = IWL5000_UCODE_API_MAX, 1564 .ucode_api_min = IWL5000_UCODE_API_MIN, 1565 .sku = IWL_SKU_G, 1566 .ops = &iwl5000_ops, 1567 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, 1568 .eeprom_ver = EEPROM_5000_EEPROM_VERSION, 1569 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION, 1570 .num_of_queues = IWL50_NUM_QUEUES, 1571 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES, 1572 .mod_params = &iwl50_mod_params, 1573 .valid_tx_ant = ANT_B, 1574 .valid_rx_ant = ANT_AB, 1575 .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL, 1576 .set_l0s = true, 1577 .use_bsm = false, 1578 .ht_greenfield_support = true, 1579 .led_compensation = 51, 1580 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS, 1581}; 1582 1583struct iwl_cfg iwl5100_abg_cfg = { 1584 .name = "5100ABG", 1585 .fw_name_pre = IWL5000_FW_PRE, 1586 .ucode_api_max = IWL5000_UCODE_API_MAX, 1587 .ucode_api_min = IWL5000_UCODE_API_MIN, 1588 .sku = IWL_SKU_A|IWL_SKU_G, 1589 .ops = &iwl5000_ops, 1590 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, 1591 .eeprom_ver = EEPROM_5000_EEPROM_VERSION, 1592 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION, 1593 .num_of_queues = IWL50_NUM_QUEUES, 1594 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES, 1595 .mod_params = &iwl50_mod_params, 1596 .valid_tx_ant = ANT_B, 1597 .valid_rx_ant = ANT_AB, 1598 .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL, 1599 .set_l0s = true, 1600 .use_bsm = false, 1601 .ht_greenfield_support = true, 1602 .led_compensation = 51, 1603 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS, 1604}; 1605 1606struct iwl_cfg iwl5100_agn_cfg = { 1607 .name = "5100AGN", 1608 .fw_name_pre = IWL5000_FW_PRE, 1609 .ucode_api_max = IWL5000_UCODE_API_MAX, 1610 .ucode_api_min = IWL5000_UCODE_API_MIN, 1611 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N, 1612 .ops = &iwl5000_ops, 1613 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, 1614 .eeprom_ver = EEPROM_5000_EEPROM_VERSION, 1615 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION, 1616 .num_of_queues = IWL50_NUM_QUEUES, 1617 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES, 1618 .mod_params = &iwl50_mod_params, 1619 .valid_tx_ant = ANT_B, 1620 .valid_rx_ant = ANT_AB, 1621 .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL, 1622 .set_l0s = true, 1623 .use_bsm = false, 1624 .ht_greenfield_support = true, 1625 .led_compensation = 51, 1626 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS, 1627}; 1628 1629struct iwl_cfg iwl5350_agn_cfg = { 1630 .name = "5350AGN", 1631 .fw_name_pre = IWL5000_FW_PRE, 1632 .ucode_api_max = IWL5000_UCODE_API_MAX, 1633 .ucode_api_min = IWL5000_UCODE_API_MIN, 1634 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N, 1635 .ops = &iwl5000_ops, 1636 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, 1637 .eeprom_ver = EEPROM_5050_EEPROM_VERSION, 1638 .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION, 1639 .num_of_queues = IWL50_NUM_QUEUES, 1640 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES, 1641 .mod_params = &iwl50_mod_params, 1642 .valid_tx_ant = ANT_ABC, 1643 .valid_rx_ant = ANT_ABC, 1644 .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL, 1645 .set_l0s = true, 1646 .use_bsm = false, 1647 .ht_greenfield_support = true, 1648 .led_compensation = 51, 1649 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS, 1650}; 1651 1652struct iwl_cfg iwl5150_agn_cfg = { 1653 .name = "5150AGN", 1654 .fw_name_pre = IWL5150_FW_PRE, 1655 .ucode_api_max = IWL5150_UCODE_API_MAX, 1656 .ucode_api_min = IWL5150_UCODE_API_MIN, 1657 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N, 1658 .ops = &iwl5150_ops, 1659 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, 1660 .eeprom_ver = EEPROM_5050_EEPROM_VERSION, 1661 .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION, 1662 .num_of_queues = IWL50_NUM_QUEUES, 1663 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES, 1664 .mod_params = &iwl50_mod_params, 1665 .valid_tx_ant = ANT_A, 1666 .valid_rx_ant = ANT_AB, 1667 .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL, 1668 .set_l0s = true, 1669 .use_bsm = false, 1670 .ht_greenfield_support = true, 1671 .led_compensation = 51, 1672 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS, 1673}; 1674 1675MODULE_FIRMWARE(IWL5000_MODULE_FIRMWARE(IWL5000_UCODE_API_MAX)); 1676MODULE_FIRMWARE(IWL5150_MODULE_FIRMWARE(IWL5150_UCODE_API_MAX)); 1677 1678module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, S_IRUGO); 1679MODULE_PARM_DESC(swcrypto50, 1680 "using software crypto engine (default 0 [hardware])\n"); 1681module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, S_IRUGO); 1682MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series"); 1683module_param_named(11n_disable50, iwl50_mod_params.disable_11n, int, S_IRUGO); 1684MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality"); 1685module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K, 1686 int, S_IRUGO); 1687MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series"); 1688module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, S_IRUGO); 1689MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error"); 1690