iwl-5000.c revision fe6efb4b423c923fb491a9ca4fa419e843548740
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2009 Intel Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
23 *
24 *****************************************************************************/
25
26#include <linux/kernel.h>
27#include <linux/module.h>
28#include <linux/init.h>
29#include <linux/pci.h>
30#include <linux/dma-mapping.h>
31#include <linux/delay.h>
32#include <linux/skbuff.h>
33#include <linux/netdevice.h>
34#include <linux/wireless.h>
35#include <net/mac80211.h>
36#include <linux/etherdevice.h>
37#include <asm/unaligned.h>
38
39#include "iwl-eeprom.h"
40#include "iwl-dev.h"
41#include "iwl-core.h"
42#include "iwl-io.h"
43#include "iwl-sta.h"
44#include "iwl-helpers.h"
45#include "iwl-5000-hw.h"
46#include "iwl-6000-hw.h"
47
48/* Highest firmware API version supported */
49#define IWL5000_UCODE_API_MAX 2
50#define IWL5150_UCODE_API_MAX 2
51
52/* Lowest firmware API version supported */
53#define IWL5000_UCODE_API_MIN 1
54#define IWL5150_UCODE_API_MIN 1
55
56#define IWL5000_FW_PRE "iwlwifi-5000-"
57#define _IWL5000_MODULE_FIRMWARE(api) IWL5000_FW_PRE #api ".ucode"
58#define IWL5000_MODULE_FIRMWARE(api) _IWL5000_MODULE_FIRMWARE(api)
59
60#define IWL5150_FW_PRE "iwlwifi-5150-"
61#define _IWL5150_MODULE_FIRMWARE(api) IWL5150_FW_PRE #api ".ucode"
62#define IWL5150_MODULE_FIRMWARE(api) _IWL5150_MODULE_FIRMWARE(api)
63
64static const u16 iwl5000_default_queue_to_tx_fifo[] = {
65	IWL_TX_FIFO_AC3,
66	IWL_TX_FIFO_AC2,
67	IWL_TX_FIFO_AC1,
68	IWL_TX_FIFO_AC0,
69	IWL50_CMD_FIFO_NUM,
70	IWL_TX_FIFO_HCCA_1,
71	IWL_TX_FIFO_HCCA_2
72};
73
74/* FIXME: same implementation as 4965 */
75static int iwl5000_apm_stop_master(struct iwl_priv *priv)
76{
77	unsigned long flags;
78
79	spin_lock_irqsave(&priv->lock, flags);
80
81	/* set stop master bit */
82	iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
83
84	iwl_poll_direct_bit(priv, CSR_RESET,
85				  CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
86
87	spin_unlock_irqrestore(&priv->lock, flags);
88	IWL_DEBUG_INFO(priv, "stop master\n");
89
90	return 0;
91}
92
93
94static int iwl5000_apm_init(struct iwl_priv *priv)
95{
96	int ret = 0;
97
98	iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
99		    CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
100
101	/* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
102	iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
103		    CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
104
105	/* Set FH wait threshold to maximum (HW error during stress W/A) */
106	iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
107
108	/* enable HAP INTA to move device L1a -> L0s */
109	iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
110		    CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
111
112	if (priv->cfg->need_pll_cfg)
113		iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
114
115	/* set "initialization complete" bit to move adapter
116	 * D0U* --> D0A* state */
117	iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
118
119	/* wait for clock stabilization */
120	ret = iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
121			CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
122	if (ret < 0) {
123		IWL_DEBUG_INFO(priv, "Failed to init the card\n");
124		return ret;
125	}
126
127	/* enable DMA */
128	iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
129
130	udelay(20);
131
132	/* disable L1-Active */
133	iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
134			  APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
135
136	return ret;
137}
138
139/* FIXME: this is identical to 4965 */
140static void iwl5000_apm_stop(struct iwl_priv *priv)
141{
142	unsigned long flags;
143
144	iwl5000_apm_stop_master(priv);
145
146	spin_lock_irqsave(&priv->lock, flags);
147
148	iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
149
150	udelay(10);
151
152	/* clear "init complete"  move adapter D0A* --> D0U state */
153	iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
154
155	spin_unlock_irqrestore(&priv->lock, flags);
156}
157
158
159static int iwl5000_apm_reset(struct iwl_priv *priv)
160{
161	int ret = 0;
162
163	iwl5000_apm_stop_master(priv);
164
165	iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
166
167	udelay(10);
168
169
170	/* FIXME: put here L1A -L0S w/a */
171
172	if (priv->cfg->need_pll_cfg)
173		iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
174
175	/* set "initialization complete" bit to move adapter
176	 * D0U* --> D0A* state */
177	iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
178
179	/* wait for clock stabilization */
180	ret = iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
181			CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
182	if (ret < 0) {
183		IWL_DEBUG_INFO(priv, "Failed to init the card\n");
184		goto out;
185	}
186
187	/* enable DMA */
188	iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
189
190	udelay(20);
191
192	/* disable L1-Active */
193	iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
194			  APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
195out:
196
197	return ret;
198}
199
200
201static void iwl5000_nic_config(struct iwl_priv *priv)
202{
203	unsigned long flags;
204	u16 radio_cfg;
205	u16 lctl;
206
207	spin_lock_irqsave(&priv->lock, flags);
208
209	lctl = iwl_pcie_link_ctl(priv);
210
211	/* HW bug W/A */
212	/* L1-ASPM is enabled by BIOS */
213	if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) == PCI_CFG_LINK_CTRL_VAL_L1_EN)
214		/* L1-APSM enabled: disable L0S  */
215		iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
216	else
217		/* L1-ASPM disabled: enable L0S */
218		iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
219
220	radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
221
222	/* write radio config values to register */
223	if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_5000_RF_CFG_TYPE_MAX)
224		iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
225			    EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
226			    EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
227			    EEPROM_RF_CFG_DASH_MSK(radio_cfg));
228
229	/* set CSR_HW_CONFIG_REG for uCode use */
230	iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
231		    CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
232		    CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
233
234	/* W/A : NIC is stuck in a reset state after Early PCIe power off
235	 * (PCIe power is lost before PERST# is asserted),
236	 * causing ME FW to lose ownership and not being able to obtain it back.
237	 */
238	iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
239				APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS,
240				~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS);
241
242	spin_unlock_irqrestore(&priv->lock, flags);
243}
244
245
246
247/*
248 * EEPROM
249 */
250static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
251{
252	u16 offset = 0;
253
254	if ((address & INDIRECT_ADDRESS) == 0)
255		return address;
256
257	switch (address & INDIRECT_TYPE_MSK) {
258	case INDIRECT_HOST:
259		offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST);
260		break;
261	case INDIRECT_GENERAL:
262		offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL);
263		break;
264	case INDIRECT_REGULATORY:
265		offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY);
266		break;
267	case INDIRECT_CALIBRATION:
268		offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION);
269		break;
270	case INDIRECT_PROCESS_ADJST:
271		offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST);
272		break;
273	case INDIRECT_OTHERS:
274		offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS);
275		break;
276	default:
277		IWL_ERR(priv, "illegal indirect type: 0x%X\n",
278		address & INDIRECT_TYPE_MSK);
279		break;
280	}
281
282	/* translate the offset from words to byte */
283	return (address & ADDRESS_MSK) + (offset << 1);
284}
285
286static u16 iwl5000_eeprom_calib_version(struct iwl_priv *priv)
287{
288	struct iwl_eeprom_calib_hdr {
289		u8 version;
290		u8 pa_type;
291		u16 voltage;
292	} *hdr;
293
294	hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
295							EEPROM_5000_CALIB_ALL);
296	return hdr->version;
297
298}
299
300static void iwl5000_gain_computation(struct iwl_priv *priv,
301		u32 average_noise[NUM_RX_CHAINS],
302		u16 min_average_noise_antenna_i,
303		u32 min_average_noise)
304{
305	int i;
306	s32 delta_g;
307	struct iwl_chain_noise_data *data = &priv->chain_noise_data;
308
309	/* Find Gain Code for the antennas B and C */
310	for (i = 1; i < NUM_RX_CHAINS; i++) {
311		if ((data->disconn_array[i])) {
312			data->delta_gain_code[i] = 0;
313			continue;
314		}
315		delta_g = (1000 * ((s32)average_noise[0] -
316			(s32)average_noise[i])) / 1500;
317		/* bound gain by 2 bits value max, 3rd bit is sign */
318		data->delta_gain_code[i] =
319			min(abs(delta_g), CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
320
321		if (delta_g < 0)
322			/* set negative sign */
323			data->delta_gain_code[i] |= (1 << 2);
324	}
325
326	IWL_DEBUG_CALIB(priv, "Delta gains: ANT_B = %d  ANT_C = %d\n",
327			data->delta_gain_code[1], data->delta_gain_code[2]);
328
329	if (!data->radio_write) {
330		struct iwl_calib_chain_noise_gain_cmd cmd;
331
332		memset(&cmd, 0, sizeof(cmd));
333
334		cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD;
335		cmd.hdr.first_group = 0;
336		cmd.hdr.groups_num = 1;
337		cmd.hdr.data_valid = 1;
338		cmd.delta_gain_1 = data->delta_gain_code[1];
339		cmd.delta_gain_2 = data->delta_gain_code[2];
340		iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD,
341			sizeof(cmd), &cmd, NULL);
342
343		data->radio_write = 1;
344		data->state = IWL_CHAIN_NOISE_CALIBRATED;
345	}
346
347	data->chain_noise_a = 0;
348	data->chain_noise_b = 0;
349	data->chain_noise_c = 0;
350	data->chain_signal_a = 0;
351	data->chain_signal_b = 0;
352	data->chain_signal_c = 0;
353	data->beacon_count = 0;
354}
355
356static void iwl5000_chain_noise_reset(struct iwl_priv *priv)
357{
358	struct iwl_chain_noise_data *data = &priv->chain_noise_data;
359	int ret;
360
361	if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
362		struct iwl_calib_chain_noise_reset_cmd cmd;
363		memset(&cmd, 0, sizeof(cmd));
364
365		cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD;
366		cmd.hdr.first_group = 0;
367		cmd.hdr.groups_num = 1;
368		cmd.hdr.data_valid = 1;
369		ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
370					sizeof(cmd), &cmd);
371		if (ret)
372			IWL_ERR(priv,
373				"Could not send REPLY_PHY_CALIBRATION_CMD\n");
374		data->state = IWL_CHAIN_NOISE_ACCUMULATE;
375		IWL_DEBUG_CALIB(priv, "Run chain_noise_calibrate\n");
376	}
377}
378
379void iwl5000_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
380			__le32 *tx_flags)
381{
382	if ((info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) ||
383	    (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT))
384		*tx_flags |= TX_CMD_FLG_RTS_CTS_MSK;
385	else
386		*tx_flags &= ~TX_CMD_FLG_RTS_CTS_MSK;
387}
388
389static struct iwl_sensitivity_ranges iwl5000_sensitivity = {
390	.min_nrg_cck = 95,
391	.max_nrg_cck = 0, /* not used, set to 0 */
392	.auto_corr_min_ofdm = 90,
393	.auto_corr_min_ofdm_mrc = 170,
394	.auto_corr_min_ofdm_x1 = 120,
395	.auto_corr_min_ofdm_mrc_x1 = 240,
396
397	.auto_corr_max_ofdm = 120,
398	.auto_corr_max_ofdm_mrc = 210,
399	.auto_corr_max_ofdm_x1 = 155,
400	.auto_corr_max_ofdm_mrc_x1 = 290,
401
402	.auto_corr_min_cck = 125,
403	.auto_corr_max_cck = 200,
404	.auto_corr_min_cck_mrc = 170,
405	.auto_corr_max_cck_mrc = 400,
406	.nrg_th_cck = 95,
407	.nrg_th_ofdm = 95,
408};
409
410static struct iwl_sensitivity_ranges iwl5150_sensitivity = {
411	.min_nrg_cck = 95,
412	.max_nrg_cck = 0, /* not used, set to 0 */
413	.auto_corr_min_ofdm = 90,
414	.auto_corr_min_ofdm_mrc = 170,
415	.auto_corr_min_ofdm_x1 = 105,
416	.auto_corr_min_ofdm_mrc_x1 = 220,
417
418	.auto_corr_max_ofdm = 120,
419	.auto_corr_max_ofdm_mrc = 210,
420	/* max = min for performance bug in 5150 DSP */
421	.auto_corr_max_ofdm_x1 = 105,
422	.auto_corr_max_ofdm_mrc_x1 = 220,
423
424	.auto_corr_min_cck = 125,
425	.auto_corr_max_cck = 200,
426	.auto_corr_min_cck_mrc = 170,
427	.auto_corr_max_cck_mrc = 400,
428	.nrg_th_cck = 95,
429	.nrg_th_ofdm = 95,
430};
431
432static const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv,
433					   size_t offset)
434{
435	u32 address = eeprom_indirect_address(priv, offset);
436	BUG_ON(address >= priv->cfg->eeprom_size);
437	return &priv->eeprom[address];
438}
439
440static void iwl5150_set_ct_threshold(struct iwl_priv *priv)
441{
442	const s32 volt2temp_coef = IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF;
443	s32 threshold = (s32)CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD) -
444			iwl_temp_calib_to_offset(priv);
445
446	priv->hw_params.ct_kill_threshold = threshold * volt2temp_coef;
447}
448
449static void iwl5000_set_ct_threshold(struct iwl_priv *priv)
450{
451	/* want Celsius */
452	priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD;
453}
454
455/*
456 *  Calibration
457 */
458static int iwl5000_set_Xtal_calib(struct iwl_priv *priv)
459{
460	struct iwl_calib_xtal_freq_cmd cmd;
461	u16 *xtal_calib = (u16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_XTAL);
462
463	cmd.hdr.op_code = IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD;
464	cmd.hdr.first_group = 0;
465	cmd.hdr.groups_num = 1;
466	cmd.hdr.data_valid = 1;
467	cmd.cap_pin1 = (u8)xtal_calib[0];
468	cmd.cap_pin2 = (u8)xtal_calib[1];
469	return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL],
470			     (u8 *)&cmd, sizeof(cmd));
471}
472
473static int iwl5000_send_calib_cfg(struct iwl_priv *priv)
474{
475	struct iwl_calib_cfg_cmd calib_cfg_cmd;
476	struct iwl_host_cmd cmd = {
477		.id = CALIBRATION_CFG_CMD,
478		.len = sizeof(struct iwl_calib_cfg_cmd),
479		.data = &calib_cfg_cmd,
480	};
481
482	memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
483	calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
484	calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
485	calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
486	calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL;
487
488	return iwl_send_cmd(priv, &cmd);
489}
490
491static void iwl5000_rx_calib_result(struct iwl_priv *priv,
492			     struct iwl_rx_mem_buffer *rxb)
493{
494	struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
495	struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw;
496	int len = le32_to_cpu(pkt->len) & FH_RSCSR_FRAME_SIZE_MSK;
497	int index;
498
499	/* reduce the size of the length field itself */
500	len -= 4;
501
502	/* Define the order in which the results will be sent to the runtime
503	 * uCode. iwl_send_calib_results sends them in a row according to their
504	 * index. We sort them here */
505	switch (hdr->op_code) {
506	case IWL_PHY_CALIBRATE_DC_CMD:
507		index = IWL_CALIB_DC;
508		break;
509	case IWL_PHY_CALIBRATE_LO_CMD:
510		index = IWL_CALIB_LO;
511		break;
512	case IWL_PHY_CALIBRATE_TX_IQ_CMD:
513		index = IWL_CALIB_TX_IQ;
514		break;
515	case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD:
516		index = IWL_CALIB_TX_IQ_PERD;
517		break;
518	case IWL_PHY_CALIBRATE_BASE_BAND_CMD:
519		index = IWL_CALIB_BASE_BAND;
520		break;
521	default:
522		IWL_ERR(priv, "Unknown calibration notification %d\n",
523			  hdr->op_code);
524		return;
525	}
526	iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len);
527}
528
529static void iwl5000_rx_calib_complete(struct iwl_priv *priv,
530			       struct iwl_rx_mem_buffer *rxb)
531{
532	IWL_DEBUG_INFO(priv, "Init. calibration is completed, restarting fw.\n");
533	queue_work(priv->workqueue, &priv->restart);
534}
535
536/*
537 * ucode
538 */
539static int iwl5000_load_section(struct iwl_priv *priv,
540				struct fw_desc *image,
541				u32 dst_addr)
542{
543	dma_addr_t phy_addr = image->p_addr;
544	u32 byte_cnt = image->len;
545
546	iwl_write_direct32(priv,
547		FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
548		FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
549
550	iwl_write_direct32(priv,
551		FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
552
553	iwl_write_direct32(priv,
554		FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
555		phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
556
557	iwl_write_direct32(priv,
558		FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
559		(iwl_get_dma_hi_addr(phy_addr)
560			<< FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
561
562	iwl_write_direct32(priv,
563		FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
564		1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
565		1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
566		FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
567
568	iwl_write_direct32(priv,
569		FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
570		FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE	|
571		FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE	|
572		FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
573
574	return 0;
575}
576
577static int iwl5000_load_given_ucode(struct iwl_priv *priv,
578		struct fw_desc *inst_image,
579		struct fw_desc *data_image)
580{
581	int ret = 0;
582
583	ret = iwl5000_load_section(priv, inst_image,
584				   IWL50_RTC_INST_LOWER_BOUND);
585	if (ret)
586		return ret;
587
588	IWL_DEBUG_INFO(priv, "INST uCode section being loaded...\n");
589	ret = wait_event_interruptible_timeout(priv->wait_command_queue,
590					priv->ucode_write_complete, 5 * HZ);
591	if (ret == -ERESTARTSYS) {
592		IWL_ERR(priv, "Could not load the INST uCode section due "
593			"to interrupt\n");
594		return ret;
595	}
596	if (!ret) {
597		IWL_ERR(priv, "Could not load the INST uCode section\n");
598		return -ETIMEDOUT;
599	}
600
601	priv->ucode_write_complete = 0;
602
603	ret = iwl5000_load_section(
604		priv, data_image, IWL50_RTC_DATA_LOWER_BOUND);
605	if (ret)
606		return ret;
607
608	IWL_DEBUG_INFO(priv, "DATA uCode section being loaded...\n");
609
610	ret = wait_event_interruptible_timeout(priv->wait_command_queue,
611				priv->ucode_write_complete, 5 * HZ);
612	if (ret == -ERESTARTSYS) {
613		IWL_ERR(priv, "Could not load the INST uCode section due "
614			"to interrupt\n");
615		return ret;
616	} else if (!ret) {
617		IWL_ERR(priv, "Could not load the DATA uCode section\n");
618		return -ETIMEDOUT;
619	} else
620		ret = 0;
621
622	priv->ucode_write_complete = 0;
623
624	return ret;
625}
626
627static int iwl5000_load_ucode(struct iwl_priv *priv)
628{
629	int ret = 0;
630
631	/* check whether init ucode should be loaded, or rather runtime ucode */
632	if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) {
633		IWL_DEBUG_INFO(priv, "Init ucode found. Loading init ucode...\n");
634		ret = iwl5000_load_given_ucode(priv,
635			&priv->ucode_init, &priv->ucode_init_data);
636		if (!ret) {
637			IWL_DEBUG_INFO(priv, "Init ucode load complete.\n");
638			priv->ucode_type = UCODE_INIT;
639		}
640	} else {
641		IWL_DEBUG_INFO(priv, "Init ucode not found, or already loaded. "
642			"Loading runtime ucode...\n");
643		ret = iwl5000_load_given_ucode(priv,
644			&priv->ucode_code, &priv->ucode_data);
645		if (!ret) {
646			IWL_DEBUG_INFO(priv, "Runtime ucode load complete.\n");
647			priv->ucode_type = UCODE_RT;
648		}
649	}
650
651	return ret;
652}
653
654static void iwl5000_init_alive_start(struct iwl_priv *priv)
655{
656	int ret = 0;
657
658	/* Check alive response for "valid" sign from uCode */
659	if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
660		/* We had an error bringing up the hardware, so take it
661		 * all the way back down so we can try again */
662		IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n");
663		goto restart;
664	}
665
666	/* initialize uCode was loaded... verify inst image.
667	 * This is a paranoid check, because we would not have gotten the
668	 * "initialize" alive if code weren't properly loaded.  */
669	if (iwl_verify_ucode(priv)) {
670		/* Runtime instruction load was bad;
671		 * take it all the way back down so we can try again */
672		IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n");
673		goto restart;
674	}
675
676	iwl_clear_stations_table(priv);
677	ret = priv->cfg->ops->lib->alive_notify(priv);
678	if (ret) {
679		IWL_WARN(priv,
680			"Could not complete ALIVE transition: %d\n", ret);
681		goto restart;
682	}
683
684	iwl5000_send_calib_cfg(priv);
685	return;
686
687restart:
688	/* real restart (first load init_ucode) */
689	queue_work(priv->workqueue, &priv->restart);
690}
691
692static void iwl5000_set_wr_ptrs(struct iwl_priv *priv,
693				int txq_id, u32 index)
694{
695	iwl_write_direct32(priv, HBUS_TARG_WRPTR,
696			(index & 0xff) | (txq_id << 8));
697	iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index);
698}
699
700static void iwl5000_tx_queue_set_status(struct iwl_priv *priv,
701					struct iwl_tx_queue *txq,
702					int tx_fifo_id, int scd_retry)
703{
704	int txq_id = txq->q.id;
705	int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
706
707	iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
708			(active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
709			(tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) |
710			(1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) |
711			IWL50_SCD_QUEUE_STTS_REG_MSK);
712
713	txq->sched_retry = scd_retry;
714
715	IWL_DEBUG_INFO(priv, "%s %s Queue %d on AC %d\n",
716		       active ? "Activate" : "Deactivate",
717		       scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
718}
719
720static int iwl5000_send_wimax_coex(struct iwl_priv *priv)
721{
722	struct iwl_wimax_coex_cmd coex_cmd;
723
724	memset(&coex_cmd, 0, sizeof(coex_cmd));
725
726	return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD,
727				sizeof(coex_cmd), &coex_cmd);
728}
729
730static int iwl5000_alive_notify(struct iwl_priv *priv)
731{
732	u32 a;
733	unsigned long flags;
734	int i, chan;
735	u32 reg_val;
736
737	spin_lock_irqsave(&priv->lock, flags);
738
739	priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR);
740	a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET;
741	for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET;
742		a += 4)
743		iwl_write_targ_mem(priv, a, 0);
744	for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET;
745		a += 4)
746		iwl_write_targ_mem(priv, a, 0);
747	for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4)
748		iwl_write_targ_mem(priv, a, 0);
749
750	iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR,
751		       priv->scd_bc_tbls.dma >> 10);
752
753	/* Enable DMA channel */
754	for (chan = 0; chan < FH50_TCSR_CHNL_NUM ; chan++)
755		iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
756				FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
757				FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
758
759	/* Update FH chicken bits */
760	reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
761	iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
762			   reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
763
764	iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL,
765		IWL50_SCD_QUEUECHAIN_SEL_ALL(priv->hw_params.max_txq_num));
766	iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0);
767
768	/* initiate the queues */
769	for (i = 0; i < priv->hw_params.max_txq_num; i++) {
770		iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0);
771		iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
772		iwl_write_targ_mem(priv, priv->scd_base_addr +
773				IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0);
774		iwl_write_targ_mem(priv, priv->scd_base_addr +
775				IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) +
776				sizeof(u32),
777				((SCD_WIN_SIZE <<
778				IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
779				IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
780				((SCD_FRAME_LIMIT <<
781				IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
782				IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
783	}
784
785	iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK,
786			IWL_MASK(0, priv->hw_params.max_txq_num));
787
788	/* Activate all Tx DMA/FIFO channels */
789	priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
790
791	iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
792
793	/* map qos queues to fifos one-to-one */
794	for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) {
795		int ac = iwl5000_default_queue_to_tx_fifo[i];
796		iwl_txq_ctx_activate(priv, i);
797		iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
798	}
799	/* TODO - need to initialize those FIFOs inside the loop above,
800	 * not only mark them as active */
801	iwl_txq_ctx_activate(priv, 4);
802	iwl_txq_ctx_activate(priv, 7);
803	iwl_txq_ctx_activate(priv, 8);
804	iwl_txq_ctx_activate(priv, 9);
805
806	spin_unlock_irqrestore(&priv->lock, flags);
807
808
809	iwl5000_send_wimax_coex(priv);
810
811	iwl5000_set_Xtal_calib(priv);
812	iwl_send_calib_results(priv);
813
814	return 0;
815}
816
817static int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
818{
819	if ((priv->cfg->mod_params->num_of_queues > IWL50_NUM_QUEUES) ||
820	    (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
821		IWL_ERR(priv,
822			"invalid queues_num, should be between %d and %d\n",
823			IWL_MIN_NUM_QUEUES, IWL50_NUM_QUEUES);
824		return -EINVAL;
825	}
826
827	priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
828	priv->hw_params.dma_chnl_num = FH50_TCSR_CHNL_NUM;
829	priv->hw_params.scd_bc_tbls_size =
830			IWL50_NUM_QUEUES * sizeof(struct iwl5000_scd_bc_tbl);
831	priv->hw_params.tfd_size = sizeof(struct iwl_tfd);
832	priv->hw_params.max_stations = IWL5000_STATION_COUNT;
833	priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID;
834
835	switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
836	case CSR_HW_REV_TYPE_6x00:
837	case CSR_HW_REV_TYPE_6x50:
838		priv->hw_params.max_data_size = IWL60_RTC_DATA_SIZE;
839		priv->hw_params.max_inst_size = IWL60_RTC_INST_SIZE;
840		break;
841	default:
842		priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE;
843		priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE;
844	}
845
846	priv->hw_params.max_bsm_size = 0;
847	priv->hw_params.fat_channel =  BIT(IEEE80211_BAND_2GHZ) |
848					BIT(IEEE80211_BAND_5GHZ);
849	priv->hw_params.rx_wrt_ptr_reg = FH_RSCSR_CHNL0_WPTR;
850
851	priv->hw_params.tx_chains_num = num_of_ant(priv->cfg->valid_tx_ant);
852	priv->hw_params.rx_chains_num = num_of_ant(priv->cfg->valid_rx_ant);
853	priv->hw_params.valid_tx_ant = priv->cfg->valid_tx_ant;
854	priv->hw_params.valid_rx_ant = priv->cfg->valid_rx_ant;
855
856	if (priv->cfg->ops->lib->temp_ops.set_ct_kill)
857		priv->cfg->ops->lib->temp_ops.set_ct_kill(priv);
858
859	/* Set initial sensitivity parameters */
860	/* Set initial calibration set */
861	switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
862	case CSR_HW_REV_TYPE_5150:
863		priv->hw_params.sens = &iwl5150_sensitivity;
864		priv->hw_params.calib_init_cfg =
865			BIT(IWL_CALIB_DC)		|
866			BIT(IWL_CALIB_LO)		|
867			BIT(IWL_CALIB_TX_IQ) 		|
868			BIT(IWL_CALIB_BASE_BAND);
869
870		break;
871	default:
872		priv->hw_params.sens = &iwl5000_sensitivity;
873		priv->hw_params.calib_init_cfg =
874			BIT(IWL_CALIB_XTAL)		|
875			BIT(IWL_CALIB_LO)		|
876			BIT(IWL_CALIB_TX_IQ) 		|
877			BIT(IWL_CALIB_TX_IQ_PERD)	|
878			BIT(IWL_CALIB_BASE_BAND);
879		break;
880	}
881
882	return 0;
883}
884
885/**
886 * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
887 */
888static void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
889					    struct iwl_tx_queue *txq,
890					    u16 byte_cnt)
891{
892	struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
893	int write_ptr = txq->q.write_ptr;
894	int txq_id = txq->q.id;
895	u8 sec_ctl = 0;
896	u8 sta_id = 0;
897	u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
898	__le16 bc_ent;
899
900	WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
901
902	if (txq_id != IWL_CMD_QUEUE_NUM) {
903		sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id;
904		sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl;
905
906		switch (sec_ctl & TX_CMD_SEC_MSK) {
907		case TX_CMD_SEC_CCM:
908			len += CCMP_MIC_LEN;
909			break;
910		case TX_CMD_SEC_TKIP:
911			len += TKIP_ICV_LEN;
912			break;
913		case TX_CMD_SEC_WEP:
914			len += WEP_IV_LEN + WEP_ICV_LEN;
915			break;
916		}
917	}
918
919	bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12));
920
921	scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
922
923	if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP)
924		scd_bc_tbl[txq_id].
925			tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
926}
927
928static void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
929					   struct iwl_tx_queue *txq)
930{
931	struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
932	int txq_id = txq->q.id;
933	int read_ptr = txq->q.read_ptr;
934	u8 sta_id = 0;
935	__le16 bc_ent;
936
937	WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
938
939	if (txq_id != IWL_CMD_QUEUE_NUM)
940		sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id;
941
942	bc_ent =  cpu_to_le16(1 | (sta_id << 12));
943	scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
944
945	if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP)
946		scd_bc_tbl[txq_id].
947			tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] =  bc_ent;
948}
949
950static int iwl5000_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
951					u16 txq_id)
952{
953	u32 tbl_dw_addr;
954	u32 tbl_dw;
955	u16 scd_q2ratid;
956
957	scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
958
959	tbl_dw_addr = priv->scd_base_addr +
960			IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
961
962	tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
963
964	if (txq_id & 0x1)
965		tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
966	else
967		tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
968
969	iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
970
971	return 0;
972}
973static void iwl5000_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
974{
975	/* Simply stop the queue, but don't change any configuration;
976	 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
977	iwl_write_prph(priv,
978		IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
979		(0 << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
980		(1 << IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
981}
982
983static int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id,
984				  int tx_fifo, int sta_id, int tid, u16 ssn_idx)
985{
986	unsigned long flags;
987	u16 ra_tid;
988
989	if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
990	    (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) {
991		IWL_WARN(priv,
992			"queue number out of range: %d, must be %d to %d\n",
993			txq_id, IWL50_FIRST_AMPDU_QUEUE,
994			IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1);
995		return -EINVAL;
996	}
997
998	ra_tid = BUILD_RAxTID(sta_id, tid);
999
1000	/* Modify device's station table to Tx this TID */
1001	iwl_sta_tx_modify_enable_tid(priv, sta_id, tid);
1002
1003	spin_lock_irqsave(&priv->lock, flags);
1004
1005	/* Stop this Tx queue before configuring it */
1006	iwl5000_tx_queue_stop_scheduler(priv, txq_id);
1007
1008	/* Map receiver-address / traffic-ID to this queue */
1009	iwl5000_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
1010
1011	/* Set this queue as a chain-building queue */
1012	iwl_set_bits_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, (1<<txq_id));
1013
1014	/* enable aggregations for the queue */
1015	iwl_set_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1<<txq_id));
1016
1017	/* Place first TFD at index corresponding to start sequence number.
1018	 * Assumes that ssn_idx is valid (!= 0xFFF) */
1019	priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1020	priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1021	iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
1022
1023	/* Set up Tx window size and frame limit for this queue */
1024	iwl_write_targ_mem(priv, priv->scd_base_addr +
1025			IWL50_SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
1026			sizeof(u32),
1027			((SCD_WIN_SIZE <<
1028			IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1029			IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1030			((SCD_FRAME_LIMIT <<
1031			IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1032			IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1033
1034	iwl_set_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
1035
1036	/* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
1037	iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
1038
1039	spin_unlock_irqrestore(&priv->lock, flags);
1040
1041	return 0;
1042}
1043
1044static int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
1045				   u16 ssn_idx, u8 tx_fifo)
1046{
1047	if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
1048	    (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) {
1049		IWL_ERR(priv,
1050			"queue number out of range: %d, must be %d to %d\n",
1051			txq_id, IWL50_FIRST_AMPDU_QUEUE,
1052			IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1);
1053		return -EINVAL;
1054	}
1055
1056	iwl5000_tx_queue_stop_scheduler(priv, txq_id);
1057
1058	iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id));
1059
1060	priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1061	priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1062	/* supposes that ssn_idx is valid (!= 0xFFF) */
1063	iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
1064
1065	iwl_clear_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
1066	iwl_txq_ctx_deactivate(priv, txq_id);
1067	iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
1068
1069	return 0;
1070}
1071
1072u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
1073{
1074	u16 size = (u16)sizeof(struct iwl_addsta_cmd);
1075	struct iwl_addsta_cmd *addsta = (struct iwl_addsta_cmd *)data;
1076	memcpy(addsta, cmd, size);
1077	/* resrved in 5000 */
1078	addsta->rate_n_flags = cpu_to_le16(0);
1079	return size;
1080}
1081
1082
1083/*
1084 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
1085 * must be called under priv->lock and mac access
1086 */
1087static void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask)
1088{
1089	iwl_write_prph(priv, IWL50_SCD_TXFACT, mask);
1090}
1091
1092
1093static inline u32 iwl5000_get_scd_ssn(struct iwl5000_tx_resp *tx_resp)
1094{
1095	return le32_to_cpup((__le32 *)&tx_resp->status +
1096			    tx_resp->frame_count) & MAX_SN;
1097}
1098
1099static int iwl5000_tx_status_reply_tx(struct iwl_priv *priv,
1100				      struct iwl_ht_agg *agg,
1101				      struct iwl5000_tx_resp *tx_resp,
1102				      int txq_id, u16 start_idx)
1103{
1104	u16 status;
1105	struct agg_tx_status *frame_status = &tx_resp->status;
1106	struct ieee80211_tx_info *info = NULL;
1107	struct ieee80211_hdr *hdr = NULL;
1108	u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
1109	int i, sh, idx;
1110	u16 seq;
1111
1112	if (agg->wait_for_ba)
1113		IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n");
1114
1115	agg->frame_count = tx_resp->frame_count;
1116	agg->start_idx = start_idx;
1117	agg->rate_n_flags = rate_n_flags;
1118	agg->bitmap = 0;
1119
1120	/* # frames attempted by Tx command */
1121	if (agg->frame_count == 1) {
1122		/* Only one frame was attempted; no block-ack will arrive */
1123		status = le16_to_cpu(frame_status[0].status);
1124		idx = start_idx;
1125
1126		/* FIXME: code repetition */
1127		IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n",
1128				   agg->frame_count, agg->start_idx, idx);
1129
1130		info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
1131		info->status.rates[0].count = tx_resp->failure_frame + 1;
1132		info->flags &= ~IEEE80211_TX_CTL_AMPDU;
1133		info->flags |= iwl_is_tx_success(status) ?
1134					IEEE80211_TX_STAT_ACK : 0;
1135		iwl_hwrate_to_tx_control(priv, rate_n_flags, info);
1136
1137		/* FIXME: code repetition end */
1138
1139		IWL_DEBUG_TX_REPLY(priv, "1 Frame 0x%x failure :%d\n",
1140				    status & 0xff, tx_resp->failure_frame);
1141		IWL_DEBUG_TX_REPLY(priv, "Rate Info rate_n_flags=%x\n", rate_n_flags);
1142
1143		agg->wait_for_ba = 0;
1144	} else {
1145		/* Two or more frames were attempted; expect block-ack */
1146		u64 bitmap = 0;
1147		int start = agg->start_idx;
1148
1149		/* Construct bit-map of pending frames within Tx window */
1150		for (i = 0; i < agg->frame_count; i++) {
1151			u16 sc;
1152			status = le16_to_cpu(frame_status[i].status);
1153			seq  = le16_to_cpu(frame_status[i].sequence);
1154			idx = SEQ_TO_INDEX(seq);
1155			txq_id = SEQ_TO_QUEUE(seq);
1156
1157			if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
1158				      AGG_TX_STATE_ABORT_MSK))
1159				continue;
1160
1161			IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n",
1162					   agg->frame_count, txq_id, idx);
1163
1164			hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
1165
1166			sc = le16_to_cpu(hdr->seq_ctrl);
1167			if (idx != (SEQ_TO_SN(sc) & 0xff)) {
1168				IWL_ERR(priv,
1169					"BUG_ON idx doesn't match seq control"
1170					" idx=%d, seq_idx=%d, seq=%d\n",
1171					  idx, SEQ_TO_SN(sc),
1172					  hdr->seq_ctrl);
1173				return -1;
1174			}
1175
1176			IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n",
1177					   i, idx, SEQ_TO_SN(sc));
1178
1179			sh = idx - start;
1180			if (sh > 64) {
1181				sh = (start - idx) + 0xff;
1182				bitmap = bitmap << sh;
1183				sh = 0;
1184				start = idx;
1185			} else if (sh < -64)
1186				sh  = 0xff - (start - idx);
1187			else if (sh < 0) {
1188				sh = start - idx;
1189				start = idx;
1190				bitmap = bitmap << sh;
1191				sh = 0;
1192			}
1193			bitmap |= 1ULL << sh;
1194			IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n",
1195					   start, (unsigned long long)bitmap);
1196		}
1197
1198		agg->bitmap = bitmap;
1199		agg->start_idx = start;
1200		IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n",
1201				   agg->frame_count, agg->start_idx,
1202				   (unsigned long long)agg->bitmap);
1203
1204		if (bitmap)
1205			agg->wait_for_ba = 1;
1206	}
1207	return 0;
1208}
1209
1210static void iwl5000_rx_reply_tx(struct iwl_priv *priv,
1211				struct iwl_rx_mem_buffer *rxb)
1212{
1213	struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1214	u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1215	int txq_id = SEQ_TO_QUEUE(sequence);
1216	int index = SEQ_TO_INDEX(sequence);
1217	struct iwl_tx_queue *txq = &priv->txq[txq_id];
1218	struct ieee80211_tx_info *info;
1219	struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
1220	u32  status = le16_to_cpu(tx_resp->status.status);
1221	int tid;
1222	int sta_id;
1223	int freed;
1224
1225	if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
1226		IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
1227			  "is out of range [0-%d] %d %d\n", txq_id,
1228			  index, txq->q.n_bd, txq->q.write_ptr,
1229			  txq->q.read_ptr);
1230		return;
1231	}
1232
1233	info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
1234	memset(&info->status, 0, sizeof(info->status));
1235
1236	tid = (tx_resp->ra_tid & IWL50_TX_RES_TID_MSK) >> IWL50_TX_RES_TID_POS;
1237	sta_id = (tx_resp->ra_tid & IWL50_TX_RES_RA_MSK) >> IWL50_TX_RES_RA_POS;
1238
1239	if (txq->sched_retry) {
1240		const u32 scd_ssn = iwl5000_get_scd_ssn(tx_resp);
1241		struct iwl_ht_agg *agg = NULL;
1242
1243		agg = &priv->stations[sta_id].tid[tid].agg;
1244
1245		iwl5000_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
1246
1247		/* check if BAR is needed */
1248		if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
1249			info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1250
1251		if (txq->q.read_ptr != (scd_ssn & 0xff)) {
1252			index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
1253			IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim "
1254					"scd_ssn=%d idx=%d txq=%d swq=%d\n",
1255					scd_ssn , index, txq_id, txq->swq_id);
1256
1257			freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1258			priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1259
1260			if (priv->mac80211_registered &&
1261			    (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
1262			    (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
1263				if (agg->state == IWL_AGG_OFF)
1264					iwl_wake_queue(priv, txq_id);
1265				else
1266					iwl_wake_queue(priv, txq->swq_id);
1267			}
1268		}
1269	} else {
1270		BUG_ON(txq_id != txq->swq_id);
1271
1272		info->status.rates[0].count = tx_resp->failure_frame + 1;
1273		info->flags |= iwl_is_tx_success(status) ?
1274					IEEE80211_TX_STAT_ACK : 0;
1275		iwl_hwrate_to_tx_control(priv,
1276					le32_to_cpu(tx_resp->rate_n_flags),
1277					info);
1278
1279		IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) rate_n_flags "
1280				   "0x%x retries %d\n",
1281				   txq_id,
1282				   iwl_get_tx_fail_reason(status), status,
1283				   le32_to_cpu(tx_resp->rate_n_flags),
1284				   tx_resp->failure_frame);
1285
1286		freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1287		if (ieee80211_is_data_qos(tx_resp->frame_ctrl))
1288			priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1289
1290		if (priv->mac80211_registered &&
1291		    (iwl_queue_space(&txq->q) > txq->q.low_mark))
1292			iwl_wake_queue(priv, txq_id);
1293	}
1294
1295	if (ieee80211_is_data_qos(tx_resp->frame_ctrl))
1296		iwl_txq_check_empty(priv, sta_id, tid, txq_id);
1297
1298	if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
1299		IWL_ERR(priv, "TODO:  Implement Tx ABORT REQUIRED!!!\n");
1300}
1301
1302/* Currently 5000 is the superset of everything */
1303u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len)
1304{
1305	return len;
1306}
1307
1308static void iwl5000_setup_deferred_work(struct iwl_priv *priv)
1309{
1310	/* in 5000 the tx power calibration is done in uCode */
1311	priv->disable_tx_power_cal = 1;
1312}
1313
1314static void iwl5000_rx_handler_setup(struct iwl_priv *priv)
1315{
1316	/* init calibration handlers */
1317	priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
1318					iwl5000_rx_calib_result;
1319	priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
1320					iwl5000_rx_calib_complete;
1321	priv->rx_handlers[REPLY_TX] = iwl5000_rx_reply_tx;
1322}
1323
1324
1325static int iwl5000_hw_valid_rtc_data_addr(u32 addr)
1326{
1327	return (addr >= IWL50_RTC_DATA_LOWER_BOUND) &&
1328		(addr < IWL50_RTC_DATA_UPPER_BOUND);
1329}
1330
1331static int iwl5000_send_rxon_assoc(struct iwl_priv *priv)
1332{
1333	int ret = 0;
1334	struct iwl5000_rxon_assoc_cmd rxon_assoc;
1335	const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1336	const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1337
1338	if ((rxon1->flags == rxon2->flags) &&
1339	    (rxon1->filter_flags == rxon2->filter_flags) &&
1340	    (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1341	    (rxon1->ofdm_ht_single_stream_basic_rates ==
1342	     rxon2->ofdm_ht_single_stream_basic_rates) &&
1343	    (rxon1->ofdm_ht_dual_stream_basic_rates ==
1344	     rxon2->ofdm_ht_dual_stream_basic_rates) &&
1345	    (rxon1->ofdm_ht_triple_stream_basic_rates ==
1346	     rxon2->ofdm_ht_triple_stream_basic_rates) &&
1347	    (rxon1->acquisition_data == rxon2->acquisition_data) &&
1348	    (rxon1->rx_chain == rxon2->rx_chain) &&
1349	    (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1350		IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC.  Not resending.\n");
1351		return 0;
1352	}
1353
1354	rxon_assoc.flags = priv->staging_rxon.flags;
1355	rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1356	rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1357	rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1358	rxon_assoc.reserved1 = 0;
1359	rxon_assoc.reserved2 = 0;
1360	rxon_assoc.reserved3 = 0;
1361	rxon_assoc.ofdm_ht_single_stream_basic_rates =
1362	    priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
1363	rxon_assoc.ofdm_ht_dual_stream_basic_rates =
1364	    priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
1365	rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
1366	rxon_assoc.ofdm_ht_triple_stream_basic_rates =
1367		 priv->staging_rxon.ofdm_ht_triple_stream_basic_rates;
1368	rxon_assoc.acquisition_data = priv->staging_rxon.acquisition_data;
1369
1370	ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
1371				     sizeof(rxon_assoc), &rxon_assoc, NULL);
1372	if (ret)
1373		return ret;
1374
1375	return ret;
1376}
1377static int  iwl5000_send_tx_power(struct iwl_priv *priv)
1378{
1379	struct iwl5000_tx_power_dbm_cmd tx_power_cmd;
1380	u8 tx_ant_cfg_cmd;
1381
1382	/* half dBm need to multiply */
1383	tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
1384	tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED;
1385	tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO;
1386
1387	if (IWL_UCODE_API(priv->ucode_ver) == 1)
1388		tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD_V1;
1389	else
1390		tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD;
1391
1392	return  iwl_send_cmd_pdu_async(priv, tx_ant_cfg_cmd,
1393				       sizeof(tx_power_cmd), &tx_power_cmd,
1394				       NULL);
1395}
1396
1397static void iwl5000_temperature(struct iwl_priv *priv)
1398{
1399	/* store temperature from statistics (in Celsius) */
1400	priv->temperature = le32_to_cpu(priv->statistics.general.temperature);
1401}
1402
1403static void iwl5150_temperature(struct iwl_priv *priv)
1404{
1405	u32 vt = 0;
1406	s32 offset =  iwl_temp_calib_to_offset(priv);
1407
1408	vt = le32_to_cpu(priv->statistics.general.temperature);
1409	vt = vt / IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF + offset;
1410	/* now vt hold the temperature in Kelvin */
1411	priv->temperature = KELVIN_TO_CELSIUS(vt);
1412}
1413
1414/* Calc max signal level (dBm) among 3 possible receivers */
1415int iwl5000_calc_rssi(struct iwl_priv *priv,
1416			     struct iwl_rx_phy_res *rx_resp)
1417{
1418	/* data from PHY/DSP regarding signal strength, etc.,
1419	 *   contents are always there, not configurable by host
1420	 */
1421	struct iwl5000_non_cfg_phy *ncphy =
1422		(struct iwl5000_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
1423	u32 val, rssi_a, rssi_b, rssi_c, max_rssi;
1424	u8 agc;
1425
1426	val  = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_AGC_IDX]);
1427	agc = (val & IWL50_OFDM_AGC_MSK) >> IWL50_OFDM_AGC_BIT_POS;
1428
1429	/* Find max rssi among 3 possible receivers.
1430	 * These values are measured by the digital signal processor (DSP).
1431	 * They should stay fairly constant even as the signal strength varies,
1432	 *   if the radio's automatic gain control (AGC) is working right.
1433	 * AGC value (see below) will provide the "interesting" info.
1434	 */
1435	val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_AB_IDX]);
1436	rssi_a = (val & IWL50_OFDM_RSSI_A_MSK) >> IWL50_OFDM_RSSI_A_BIT_POS;
1437	rssi_b = (val & IWL50_OFDM_RSSI_B_MSK) >> IWL50_OFDM_RSSI_B_BIT_POS;
1438	val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_C_IDX]);
1439	rssi_c = (val & IWL50_OFDM_RSSI_C_MSK) >> IWL50_OFDM_RSSI_C_BIT_POS;
1440
1441	max_rssi = max_t(u32, rssi_a, rssi_b);
1442	max_rssi = max_t(u32, max_rssi, rssi_c);
1443
1444	IWL_DEBUG_STATS(priv, "Rssi In A %d B %d C %d Max %d AGC dB %d\n",
1445		rssi_a, rssi_b, rssi_c, max_rssi, agc);
1446
1447	/* dBm = max_rssi dB - agc dB - constant.
1448	 * Higher AGC (higher radio gain) means lower signal. */
1449	return max_rssi - agc - IWL49_RSSI_OFFSET;
1450}
1451
1452struct iwl_hcmd_ops iwl5000_hcmd = {
1453	.rxon_assoc = iwl5000_send_rxon_assoc,
1454	.commit_rxon = iwl_commit_rxon,
1455	.set_rxon_chain = iwl_set_rxon_chain,
1456};
1457
1458struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = {
1459	.get_hcmd_size = iwl5000_get_hcmd_size,
1460	.build_addsta_hcmd = iwl5000_build_addsta_hcmd,
1461	.gain_computation = iwl5000_gain_computation,
1462	.chain_noise_reset = iwl5000_chain_noise_reset,
1463	.rts_tx_cmd_flag = iwl5000_rts_tx_cmd_flag,
1464	.calc_rssi = iwl5000_calc_rssi,
1465};
1466
1467struct iwl_lib_ops iwl5000_lib = {
1468	.set_hw_params = iwl5000_hw_set_hw_params,
1469	.txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
1470	.txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
1471	.txq_set_sched = iwl5000_txq_set_sched,
1472	.txq_agg_enable = iwl5000_txq_agg_enable,
1473	.txq_agg_disable = iwl5000_txq_agg_disable,
1474	.txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
1475	.txq_free_tfd = iwl_hw_txq_free_tfd,
1476	.txq_init = iwl_hw_tx_queue_init,
1477	.rx_handler_setup = iwl5000_rx_handler_setup,
1478	.setup_deferred_work = iwl5000_setup_deferred_work,
1479	.is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
1480	.load_ucode = iwl5000_load_ucode,
1481	.init_alive_start = iwl5000_init_alive_start,
1482	.alive_notify = iwl5000_alive_notify,
1483	.send_tx_power = iwl5000_send_tx_power,
1484	.update_chain_flags = iwl_update_chain_flags,
1485	.apm_ops = {
1486		.init =	iwl5000_apm_init,
1487		.reset = iwl5000_apm_reset,
1488		.stop = iwl5000_apm_stop,
1489		.config = iwl5000_nic_config,
1490		.set_pwr_src = iwl_set_pwr_src,
1491	},
1492	.eeprom_ops = {
1493		.regulatory_bands = {
1494			EEPROM_5000_REG_BAND_1_CHANNELS,
1495			EEPROM_5000_REG_BAND_2_CHANNELS,
1496			EEPROM_5000_REG_BAND_3_CHANNELS,
1497			EEPROM_5000_REG_BAND_4_CHANNELS,
1498			EEPROM_5000_REG_BAND_5_CHANNELS,
1499			EEPROM_5000_REG_BAND_24_FAT_CHANNELS,
1500			EEPROM_5000_REG_BAND_52_FAT_CHANNELS
1501		},
1502		.verify_signature  = iwlcore_eeprom_verify_signature,
1503		.acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1504		.release_semaphore = iwlcore_eeprom_release_semaphore,
1505		.calib_version	= iwl5000_eeprom_calib_version,
1506		.query_addr = iwl5000_eeprom_query_addr,
1507	},
1508	.post_associate = iwl_post_associate,
1509	.isr = iwl_isr_ict,
1510	.config_ap = iwl_config_ap,
1511	.temp_ops = {
1512		.temperature = iwl5000_temperature,
1513		.set_ct_kill = iwl5000_set_ct_threshold,
1514	 },
1515};
1516
1517static struct iwl_lib_ops iwl5150_lib = {
1518	.set_hw_params = iwl5000_hw_set_hw_params,
1519	.txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
1520	.txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
1521	.txq_set_sched = iwl5000_txq_set_sched,
1522	.txq_agg_enable = iwl5000_txq_agg_enable,
1523	.txq_agg_disable = iwl5000_txq_agg_disable,
1524	.txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
1525	.txq_free_tfd = iwl_hw_txq_free_tfd,
1526	.txq_init = iwl_hw_tx_queue_init,
1527	.rx_handler_setup = iwl5000_rx_handler_setup,
1528	.setup_deferred_work = iwl5000_setup_deferred_work,
1529	.is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
1530	.load_ucode = iwl5000_load_ucode,
1531	.init_alive_start = iwl5000_init_alive_start,
1532	.alive_notify = iwl5000_alive_notify,
1533	.send_tx_power = iwl5000_send_tx_power,
1534	.update_chain_flags = iwl_update_chain_flags,
1535	.apm_ops = {
1536		.init =	iwl5000_apm_init,
1537		.reset = iwl5000_apm_reset,
1538		.stop = iwl5000_apm_stop,
1539		.config = iwl5000_nic_config,
1540		.set_pwr_src = iwl_set_pwr_src,
1541	},
1542	.eeprom_ops = {
1543		.regulatory_bands = {
1544			EEPROM_5000_REG_BAND_1_CHANNELS,
1545			EEPROM_5000_REG_BAND_2_CHANNELS,
1546			EEPROM_5000_REG_BAND_3_CHANNELS,
1547			EEPROM_5000_REG_BAND_4_CHANNELS,
1548			EEPROM_5000_REG_BAND_5_CHANNELS,
1549			EEPROM_5000_REG_BAND_24_FAT_CHANNELS,
1550			EEPROM_5000_REG_BAND_52_FAT_CHANNELS
1551		},
1552		.verify_signature  = iwlcore_eeprom_verify_signature,
1553		.acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1554		.release_semaphore = iwlcore_eeprom_release_semaphore,
1555		.calib_version	= iwl5000_eeprom_calib_version,
1556		.query_addr = iwl5000_eeprom_query_addr,
1557	},
1558	.post_associate = iwl_post_associate,
1559	.isr = iwl_isr_ict,
1560	.config_ap = iwl_config_ap,
1561	.temp_ops = {
1562		.temperature = iwl5150_temperature,
1563		.set_ct_kill = iwl5150_set_ct_threshold,
1564	 },
1565};
1566
1567struct iwl_ops iwl5000_ops = {
1568	.lib = &iwl5000_lib,
1569	.hcmd = &iwl5000_hcmd,
1570	.utils = &iwl5000_hcmd_utils,
1571};
1572
1573static struct iwl_ops iwl5150_ops = {
1574	.lib = &iwl5150_lib,
1575	.hcmd = &iwl5000_hcmd,
1576	.utils = &iwl5000_hcmd_utils,
1577};
1578
1579struct iwl_mod_params iwl50_mod_params = {
1580	.num_of_queues = IWL50_NUM_QUEUES,
1581	.num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1582	.amsdu_size_8K = 1,
1583	.restart_fw = 1,
1584	/* the rest are 0 by default */
1585};
1586
1587
1588struct iwl_cfg iwl5300_agn_cfg = {
1589	.name = "5300AGN",
1590	.fw_name_pre = IWL5000_FW_PRE,
1591	.ucode_api_max = IWL5000_UCODE_API_MAX,
1592	.ucode_api_min = IWL5000_UCODE_API_MIN,
1593	.sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1594	.ops = &iwl5000_ops,
1595	.eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1596	.eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1597	.eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1598	.mod_params = &iwl50_mod_params,
1599	.valid_tx_ant = ANT_ABC,
1600	.valid_rx_ant = ANT_ABC,
1601	.need_pll_cfg = true,
1602};
1603
1604struct iwl_cfg iwl5100_bg_cfg = {
1605	.name = "5100BG",
1606	.fw_name_pre = IWL5000_FW_PRE,
1607	.ucode_api_max = IWL5000_UCODE_API_MAX,
1608	.ucode_api_min = IWL5000_UCODE_API_MIN,
1609	.sku = IWL_SKU_G,
1610	.ops = &iwl5000_ops,
1611	.eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1612	.eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1613	.eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1614	.mod_params = &iwl50_mod_params,
1615	.valid_tx_ant = ANT_B,
1616	.valid_rx_ant = ANT_AB,
1617	.need_pll_cfg = true,
1618};
1619
1620struct iwl_cfg iwl5100_abg_cfg = {
1621	.name = "5100ABG",
1622	.fw_name_pre = IWL5000_FW_PRE,
1623	.ucode_api_max = IWL5000_UCODE_API_MAX,
1624	.ucode_api_min = IWL5000_UCODE_API_MIN,
1625	.sku = IWL_SKU_A|IWL_SKU_G,
1626	.ops = &iwl5000_ops,
1627	.eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1628	.eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1629	.eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1630	.mod_params = &iwl50_mod_params,
1631	.valid_tx_ant = ANT_B,
1632	.valid_rx_ant = ANT_AB,
1633	.need_pll_cfg = true,
1634};
1635
1636struct iwl_cfg iwl5100_agn_cfg = {
1637	.name = "5100AGN",
1638	.fw_name_pre = IWL5000_FW_PRE,
1639	.ucode_api_max = IWL5000_UCODE_API_MAX,
1640	.ucode_api_min = IWL5000_UCODE_API_MIN,
1641	.sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1642	.ops = &iwl5000_ops,
1643	.eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1644	.eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1645	.eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1646	.mod_params = &iwl50_mod_params,
1647	.valid_tx_ant = ANT_B,
1648	.valid_rx_ant = ANT_AB,
1649	.need_pll_cfg = true,
1650};
1651
1652struct iwl_cfg iwl5350_agn_cfg = {
1653	.name = "5350AGN",
1654	.fw_name_pre = IWL5000_FW_PRE,
1655	.ucode_api_max = IWL5000_UCODE_API_MAX,
1656	.ucode_api_min = IWL5000_UCODE_API_MIN,
1657	.sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1658	.ops = &iwl5000_ops,
1659	.eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1660	.eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1661	.eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
1662	.mod_params = &iwl50_mod_params,
1663	.valid_tx_ant = ANT_ABC,
1664	.valid_rx_ant = ANT_ABC,
1665	.need_pll_cfg = true,
1666};
1667
1668struct iwl_cfg iwl5150_agn_cfg = {
1669	.name = "5150AGN",
1670	.fw_name_pre = IWL5150_FW_PRE,
1671	.ucode_api_max = IWL5150_UCODE_API_MAX,
1672	.ucode_api_min = IWL5150_UCODE_API_MIN,
1673	.sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1674	.ops = &iwl5150_ops,
1675	.eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1676	.eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1677	.eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
1678	.mod_params = &iwl50_mod_params,
1679	.valid_tx_ant = ANT_A,
1680	.valid_rx_ant = ANT_AB,
1681	.need_pll_cfg = true,
1682};
1683
1684MODULE_FIRMWARE(IWL5000_MODULE_FIRMWARE(IWL5000_UCODE_API_MAX));
1685MODULE_FIRMWARE(IWL5150_MODULE_FIRMWARE(IWL5150_UCODE_API_MAX));
1686
1687module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, 0444);
1688MODULE_PARM_DESC(swcrypto50,
1689		  "using software crypto engine (default 0 [hardware])\n");
1690module_param_named(debug50, iwl50_mod_params.debug, uint, 0444);
1691MODULE_PARM_DESC(debug50, "50XX debug output mask");
1692module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, 0444);
1693MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series");
1694module_param_named(11n_disable50, iwl50_mod_params.disable_11n, int, 0444);
1695MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality");
1696module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K, int, 0444);
1697MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series");
1698module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, 0444);
1699MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error");
1700