1ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach/****************************************************************************** 2ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * 351368bf792c79eb917694a4155d62f04359e3734Emmanuel Grumbach * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved. 48b4139dc9f2171f313fc703c08269f6f8a6f6fc4Johannes Berg * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH 5ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * 6ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * Portions of this file are derived from the ipw3945 project, as well 7ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * as portions of the ieee80211 subsystem header files. 8ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * 9ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * This program is free software; you can redistribute it and/or modify it 10ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * under the terms of version 2 of the GNU General Public License as 11ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * published by the Free Software Foundation. 12ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * 13ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * This program is distributed in the hope that it will be useful, but WITHOUT 14ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 16ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * more details. 17ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * 18ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * You should have received a copy of the GNU General Public License along with 19ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * this program; if not, write to the Free Software Foundation, Inc., 20ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 21ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * 22ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * The full GNU General Public License is included in this distribution in the 23ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * file called LICENSE. 24ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * 25ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * Contact Information: 26ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * Intel Linux Wireless <ilw@linux.intel.com> 27ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 28ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * 29ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach *****************************************************************************/ 30ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach#ifndef __iwl_trans_int_pcie_h__ 31ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach#define __iwl_trans_int_pcie_h__ 32ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach 33a72b8b088c3465b28192c1a14ba97be8223a8cecEmmanuel Grumbach#include <linux/spinlock.h> 34a72b8b088c3465b28192c1a14ba97be8223a8cecEmmanuel Grumbach#include <linux/interrupt.h> 35a72b8b088c3465b28192c1a14ba97be8223a8cecEmmanuel Grumbach#include <linux/skbuff.h> 3613df1aab4aa3cd99693c0cdeb7177e5359218431Johannes Berg#include <linux/wait.h> 37522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach#include <linux/pci.h> 387c5ba4a830cbb730770129b0004e2a06e47dbac5Johannes Berg#include <linux/timer.h> 39a72b8b088c3465b28192c1a14ba97be8223a8cecEmmanuel Grumbach 40dda61a4482661d71034cc132d1f474f19ce34a4dEmmanuel Grumbach#include "iwl-fh.h" 41a72b8b088c3465b28192c1a14ba97be8223a8cecEmmanuel Grumbach#include "iwl-csr.h" 42a72b8b088c3465b28192c1a14ba97be8223a8cecEmmanuel Grumbach#include "iwl-trans.h" 43a72b8b088c3465b28192c1a14ba97be8223a8cecEmmanuel Grumbach#include "iwl-debug.h" 44a72b8b088c3465b28192c1a14ba97be8223a8cecEmmanuel Grumbach#include "iwl-io.h" 4502e3835884f352ac707dcf14d8bf455c0c0acbc5Emmanuel Grumbach#include "iwl-op-mode.h" 46a72b8b088c3465b28192c1a14ba97be8223a8cecEmmanuel Grumbach 47a72b8b088c3465b28192c1a14ba97be8223a8cecEmmanuel Grumbachstruct iwl_host_cmd; 48dda61a4482661d71034cc132d1f474f19ce34a4dEmmanuel Grumbach 49ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach/*This file includes the declaration that are internal to the 50ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * trans_pcie layer */ 51ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach 5248a2d66f58d2bf1818acf5ff7ed9897a9977a96eJohannes Bergstruct iwl_rx_mem_buffer { 5348a2d66f58d2bf1818acf5ff7ed9897a9977a96eJohannes Berg dma_addr_t page_dma; 5448a2d66f58d2bf1818acf5ff7ed9897a9977a96eJohannes Berg struct page *page; 5548a2d66f58d2bf1818acf5ff7ed9897a9977a96eJohannes Berg struct list_head list; 5648a2d66f58d2bf1818acf5ff7ed9897a9977a96eJohannes Berg}; 5748a2d66f58d2bf1818acf5ff7ed9897a9977a96eJohannes Berg 58e6bb4c9c00892c488f3218ea317dc6a71674faf4Emmanuel Grumbach/** 591f7b6172db86e9ab2b4cd794441bb2c40ab287fcEmmanuel Grumbach * struct isr_statistics - interrupt statistics 601f7b6172db86e9ab2b4cd794441bb2c40ab287fcEmmanuel Grumbach * 611f7b6172db86e9ab2b4cd794441bb2c40ab287fcEmmanuel Grumbach */ 621f7b6172db86e9ab2b4cd794441bb2c40ab287fcEmmanuel Grumbachstruct isr_statistics { 631f7b6172db86e9ab2b4cd794441bb2c40ab287fcEmmanuel Grumbach u32 hw; 641f7b6172db86e9ab2b4cd794441bb2c40ab287fcEmmanuel Grumbach u32 sw; 651f7b6172db86e9ab2b4cd794441bb2c40ab287fcEmmanuel Grumbach u32 err_code; 661f7b6172db86e9ab2b4cd794441bb2c40ab287fcEmmanuel Grumbach u32 sch; 671f7b6172db86e9ab2b4cd794441bb2c40ab287fcEmmanuel Grumbach u32 alive; 681f7b6172db86e9ab2b4cd794441bb2c40ab287fcEmmanuel Grumbach u32 rfkill; 691f7b6172db86e9ab2b4cd794441bb2c40ab287fcEmmanuel Grumbach u32 ctkill; 701f7b6172db86e9ab2b4cd794441bb2c40ab287fcEmmanuel Grumbach u32 wakeup; 711f7b6172db86e9ab2b4cd794441bb2c40ab287fcEmmanuel Grumbach u32 rx; 721f7b6172db86e9ab2b4cd794441bb2c40ab287fcEmmanuel Grumbach u32 tx; 731f7b6172db86e9ab2b4cd794441bb2c40ab287fcEmmanuel Grumbach u32 unhandled; 741f7b6172db86e9ab2b4cd794441bb2c40ab287fcEmmanuel Grumbach}; 751f7b6172db86e9ab2b4cd794441bb2c40ab287fcEmmanuel Grumbach 761f7b6172db86e9ab2b4cd794441bb2c40ab287fcEmmanuel Grumbach/** 77990aa6d7b28d26bf22171410b49f191e8e9b09fcEmmanuel Grumbach * struct iwl_rxq - Rx queue 785a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach * @bd: driver's pointer to buffer of receive buffer descriptors (rbd) 795a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach * @bd_dma: bus address of buffer of receive buffer descriptors (rbd) 805a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach * @pool: 815a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach * @queue: 825a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach * @read: Shared index to newest available Rx buffer 835a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach * @write: Shared index to oldest written Rx packet 845a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach * @free_count: Number of pre-allocated buffers in rx_free 855a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach * @write_actual: 865a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach * @rx_free: list of free SKBs for use 875a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach * @rx_used: List of Rx buffers with no SKB 885a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach * @need_update: flag to indicate we need to update read/write index 895a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach * @rb_stts: driver's pointer to receive buffer status 905a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach * @rb_stts_dma: bus address of receive buffer status 915a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach * @lock: 925a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach * 935a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers 945a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach */ 95990aa6d7b28d26bf22171410b49f191e8e9b09fcEmmanuel Grumbachstruct iwl_rxq { 965a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach __le32 *bd; 975a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach dma_addr_t bd_dma; 985a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS]; 995a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE]; 1005a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach u32 read; 1015a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach u32 write; 1025a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach u32 free_count; 1035a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach u32 write_actual; 1045a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach struct list_head rx_free; 1055a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach struct list_head rx_used; 1065d63f926d119ff2394514ade4d489566a575f897Johannes Berg bool need_update; 1075a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach struct iwl_rb_status *rb_stts; 1085a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach dma_addr_t rb_stts_dma; 1095a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach spinlock_t lock; 1105a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach}; 1115a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach 112a72b8b088c3465b28192c1a14ba97be8223a8cecEmmanuel Grumbachstruct iwl_dma_ptr { 113a72b8b088c3465b28192c1a14ba97be8223a8cecEmmanuel Grumbach dma_addr_t dma; 114a72b8b088c3465b28192c1a14ba97be8223a8cecEmmanuel Grumbach void *addr; 115a72b8b088c3465b28192c1a14ba97be8223a8cecEmmanuel Grumbach size_t size; 116a72b8b088c3465b28192c1a14ba97be8223a8cecEmmanuel Grumbach}; 117a72b8b088c3465b28192c1a14ba97be8223a8cecEmmanuel Grumbach 118bffc66ce2210b149fd171eccad2aef9802c0b35dJohannes Berg/** 119bffc66ce2210b149fd171eccad2aef9802c0b35dJohannes Berg * iwl_queue_inc_wrap - increment queue index, wrap back to beginning 120bffc66ce2210b149fd171eccad2aef9802c0b35dJohannes Berg * @index -- current index 121bffc66ce2210b149fd171eccad2aef9802c0b35dJohannes Berg */ 12283f32a4b4aa73f36ecc799e22174fe78ed5cb2afJohannes Bergstatic inline int iwl_queue_inc_wrap(int index) 123bffc66ce2210b149fd171eccad2aef9802c0b35dJohannes Berg{ 12483f32a4b4aa73f36ecc799e22174fe78ed5cb2afJohannes Berg return ++index & (TFD_QUEUE_SIZE_MAX - 1); 125bffc66ce2210b149fd171eccad2aef9802c0b35dJohannes Berg} 126bffc66ce2210b149fd171eccad2aef9802c0b35dJohannes Berg 127bffc66ce2210b149fd171eccad2aef9802c0b35dJohannes Berg/** 128bffc66ce2210b149fd171eccad2aef9802c0b35dJohannes Berg * iwl_queue_dec_wrap - decrement queue index, wrap back to end 129bffc66ce2210b149fd171eccad2aef9802c0b35dJohannes Berg * @index -- current index 130bffc66ce2210b149fd171eccad2aef9802c0b35dJohannes Berg */ 13183f32a4b4aa73f36ecc799e22174fe78ed5cb2afJohannes Bergstatic inline int iwl_queue_dec_wrap(int index) 132bffc66ce2210b149fd171eccad2aef9802c0b35dJohannes Berg{ 13383f32a4b4aa73f36ecc799e22174fe78ed5cb2afJohannes Berg return --index & (TFD_QUEUE_SIZE_MAX - 1); 134bffc66ce2210b149fd171eccad2aef9802c0b35dJohannes Berg} 135bffc66ce2210b149fd171eccad2aef9802c0b35dJohannes Berg 136522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbachstruct iwl_cmd_meta { 137522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach /* only for SYNC commands, iff the reply skb is wanted */ 138522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach struct iwl_host_cmd *source; 139c14c73728b8feb01d9142f9241bf14601cfb86f7Johannes Berg u32 flags; 140522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach}; 141522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach 142522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach/* 143522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * Generic queue structure 144522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * 145522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * Contains common data for Rx and Tx queues. 146522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * 14783f32a4b4aa73f36ecc799e22174fe78ed5cb2afJohannes Berg * Note the difference between TFD_QUEUE_SIZE_MAX and n_window: the hardware 14883f32a4b4aa73f36ecc799e22174fe78ed5cb2afJohannes Berg * always assumes 256 descriptors, so TFD_QUEUE_SIZE_MAX is always 256 (unless 149522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * there might be HW changes in the future). For the normal TX 150522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * queues, n_window, which is the size of the software queue data 151522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * is also 256; however, for the command queue, n_window is only 152522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * 32 since we don't need so many commands pending. Since the HW 15383f32a4b4aa73f36ecc799e22174fe78ed5cb2afJohannes Berg * still uses 256 BDs for DMA though, TFD_QUEUE_SIZE_MAX stays 256. As a result, 154522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * the software buffers (in the variables @meta, @txb in struct 155990aa6d7b28d26bf22171410b49f191e8e9b09fcEmmanuel Grumbach * iwl_txq) only have 32 entries, while the HW buffers (@tfds in 156990aa6d7b28d26bf22171410b49f191e8e9b09fcEmmanuel Grumbach * the same struct) have 256. 157522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * This means that we end up with the following: 158522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * HW entries: | 0 | ... | N * 32 | ... | N * 32 + 31 | ... | 255 | 159522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * SW entries: | 0 | ... | 31 | 160522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * where N is a number between 0 and 7. This means that the SW 161522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * data is a window overlayed over the HW queue. 162522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach */ 163522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbachstruct iwl_queue { 164522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach int write_ptr; /* 1-st empty entry (index) host_w*/ 165522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach int read_ptr; /* last used entry (index) host_r*/ 166522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach /* use for monitoring and recovering the stuck queue */ 167522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach dma_addr_t dma_addr; /* physical addr for BD's */ 168522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach int n_window; /* safe queue window */ 169522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach u32 id; 170522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach int low_mark; /* low watermark, resume queue if free 171522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * space more than this */ 172522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach int high_mark; /* high watermark, stop queue if free 173522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * space less than this */ 174522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach}; 175522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach 176bf8440e6a6f5fabf7843dbfecb1745e49182fa1cJohannes Berg#define TFD_TX_CMD_SLOTS 256 177bf8440e6a6f5fabf7843dbfecb1745e49182fa1cJohannes Berg#define TFD_CMD_SLOTS 32 178bf8440e6a6f5fabf7843dbfecb1745e49182fa1cJohannes Berg 1798a964f44e01ad3bbc208c3e80d931ba91b9ea786Johannes Berg/* 1808a964f44e01ad3bbc208c3e80d931ba91b9ea786Johannes Berg * The FH will write back to the first TB only, so we need 1818a964f44e01ad3bbc208c3e80d931ba91b9ea786Johannes Berg * to copy some data into the buffer regardless of whether 18238c0f334b359953f010e9b921e0b55278d3918f7Johannes Berg * it should be mapped or not. This indicates how big the 18338c0f334b359953f010e9b921e0b55278d3918f7Johannes Berg * first TB must be to include the scratch buffer. Since 18438c0f334b359953f010e9b921e0b55278d3918f7Johannes Berg * the scratch is 4 bytes at offset 12, it's 16 now. If we 18538c0f334b359953f010e9b921e0b55278d3918f7Johannes Berg * make it bigger then allocations will be bigger and copy 18638c0f334b359953f010e9b921e0b55278d3918f7Johannes Berg * slower, so that's probably not useful. 1878a964f44e01ad3bbc208c3e80d931ba91b9ea786Johannes Berg */ 18838c0f334b359953f010e9b921e0b55278d3918f7Johannes Berg#define IWL_HCMD_SCRATCHBUF_SIZE 16 1898a964f44e01ad3bbc208c3e80d931ba91b9ea786Johannes Berg 190990aa6d7b28d26bf22171410b49f191e8e9b09fcEmmanuel Grumbachstruct iwl_pcie_txq_entry { 191bf8440e6a6f5fabf7843dbfecb1745e49182fa1cJohannes Berg struct iwl_device_cmd *cmd; 192bf8440e6a6f5fabf7843dbfecb1745e49182fa1cJohannes Berg struct sk_buff *skb; 193f4feb8ac6e666d2ca37cf722166bbfadf2c6adf8Johannes Berg /* buffer to free after command completes */ 194f4feb8ac6e666d2ca37cf722166bbfadf2c6adf8Johannes Berg const void *free_buf; 195bf8440e6a6f5fabf7843dbfecb1745e49182fa1cJohannes Berg struct iwl_cmd_meta meta; 196bf8440e6a6f5fabf7843dbfecb1745e49182fa1cJohannes Berg}; 197bf8440e6a6f5fabf7843dbfecb1745e49182fa1cJohannes Berg 19838c0f334b359953f010e9b921e0b55278d3918f7Johannes Bergstruct iwl_pcie_txq_scratch_buf { 19938c0f334b359953f010e9b921e0b55278d3918f7Johannes Berg struct iwl_cmd_header hdr; 20038c0f334b359953f010e9b921e0b55278d3918f7Johannes Berg u8 buf[8]; 20138c0f334b359953f010e9b921e0b55278d3918f7Johannes Berg __le32 scratch; 20238c0f334b359953f010e9b921e0b55278d3918f7Johannes Berg}; 20338c0f334b359953f010e9b921e0b55278d3918f7Johannes Berg 204522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach/** 205990aa6d7b28d26bf22171410b49f191e8e9b09fcEmmanuel Grumbach * struct iwl_txq - Tx Queue for DMA 206522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * @q: generic Rx/Tx queue descriptor 207bf8440e6a6f5fabf7843dbfecb1745e49182fa1cJohannes Berg * @tfds: transmit frame descriptors (DMA memory) 20838c0f334b359953f010e9b921e0b55278d3918f7Johannes Berg * @scratchbufs: start of command headers, including scratch buffers, for 20938c0f334b359953f010e9b921e0b55278d3918f7Johannes Berg * the writeback -- this is DMA memory and an array holding one buffer 21038c0f334b359953f010e9b921e0b55278d3918f7Johannes Berg * for each command on the queue 21138c0f334b359953f010e9b921e0b55278d3918f7Johannes Berg * @scratchbufs_dma: DMA address for the scratchbufs start 212bf8440e6a6f5fabf7843dbfecb1745e49182fa1cJohannes Berg * @entries: transmit entries (driver state) 213bf8440e6a6f5fabf7843dbfecb1745e49182fa1cJohannes Berg * @lock: queue lock 214bf8440e6a6f5fabf7843dbfecb1745e49182fa1cJohannes Berg * @stuck_timer: timer that fires if queue gets stuck 215bf8440e6a6f5fabf7843dbfecb1745e49182fa1cJohannes Berg * @trans_pcie: pointer back to transport (for timer) 216522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * @need_update: indicates need to update read/write index 217bf8440e6a6f5fabf7843dbfecb1745e49182fa1cJohannes Berg * @active: stores if queue is active 21868972c46f2975d3d61f9dc9f311f77bfc8a8b12bJohannes Berg * @ampdu: true if this queue is an ampdu queue for an specific RA/TID 219522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * 220522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame 221522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * descriptors) and required locking structures. 222522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach */ 223990aa6d7b28d26bf22171410b49f191e8e9b09fcEmmanuel Grumbachstruct iwl_txq { 224522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach struct iwl_queue q; 225522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach struct iwl_tfd *tfds; 22638c0f334b359953f010e9b921e0b55278d3918f7Johannes Berg struct iwl_pcie_txq_scratch_buf *scratchbufs; 22738c0f334b359953f010e9b921e0b55278d3918f7Johannes Berg dma_addr_t scratchbufs_dma; 228990aa6d7b28d26bf22171410b49f191e8e9b09fcEmmanuel Grumbach struct iwl_pcie_txq_entry *entries; 229015c15e1067c988fc87fb550b222f075c8d3f47cJohannes Berg spinlock_t lock; 2307c5ba4a830cbb730770129b0004e2a06e47dbac5Johannes Berg struct timer_list stuck_timer; 2317c5ba4a830cbb730770129b0004e2a06e47dbac5Johannes Berg struct iwl_trans_pcie *trans_pcie; 23243aa616f325554ed20dafce3678c2adaddd15f08Johannes Berg bool need_update; 233522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach u8 active; 23468972c46f2975d3d61f9dc9f311f77bfc8a8b12bJohannes Berg bool ampdu; 235522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach}; 236522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach 23738c0f334b359953f010e9b921e0b55278d3918f7Johannes Bergstatic inline dma_addr_t 23838c0f334b359953f010e9b921e0b55278d3918f7Johannes Bergiwl_pcie_get_scratchbuf_dma(struct iwl_txq *txq, int idx) 23938c0f334b359953f010e9b921e0b55278d3918f7Johannes Berg{ 24038c0f334b359953f010e9b921e0b55278d3918f7Johannes Berg return txq->scratchbufs_dma + 24138c0f334b359953f010e9b921e0b55278d3918f7Johannes Berg sizeof(struct iwl_pcie_txq_scratch_buf) * idx; 24238c0f334b359953f010e9b921e0b55278d3918f7Johannes Berg} 24338c0f334b359953f010e9b921e0b55278d3918f7Johannes Berg 2445a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach/** 245e6bb4c9c00892c488f3218ea317dc6a71674faf4Emmanuel Grumbach * struct iwl_trans_pcie - PCIe transport specific data 2465a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach * @rxq: all the RX queue data 2475a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach * @rx_replenish: work that will be called when buffers need to be allocated 2489130bab137844d9ad3db6ab524de299cd2b9e39dEmmanuel Grumbach * @drv - pointer to iwl_drv 2495a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach * @trans: pointer to the generic transport area 250105183b156b7c220b47c3162e087101a0a6abc9fEmmanuel Grumbach * @scd_base_addr: scheduler sram base address in SRAM 251105183b156b7c220b47c3162e087101a0a6abc9fEmmanuel Grumbach * @scd_bc_tbls: pointer to the byte count table of the scheduler 2529d6b2cb1ccf9c1e00a0891eff78b93eb1a1fc372Emmanuel Grumbach * @kw: keep warm address 253a42a184458ae95937893cb873c988385637c5e14Emmanuel Grumbach * @pci_dev: basic pci-network driver stuff 254a42a184458ae95937893cb873c988385637c5e14Emmanuel Grumbach * @hw_base: pci hardware address support 25513df1aab4aa3cd99693c0cdeb7177e5359218431Johannes Berg * @ucode_write_complete: indicates that the ucode has been copied. 25613df1aab4aa3cd99693c0cdeb7177e5359218431Johannes Berg * @ucode_write_waitq: wait queue for uCode load 257c6f600fcfe8a7e4f594fc4c80b2c7b66f248958bMeenakshi Venkataraman * @cmd_queue - command queue number 258b2cf410ccb927141e69aa610b6dcf5137701f3afJohannes Berg * @rx_buf_size_8k: 8 kB RX buffer size 259046db346386661906dffa33f5ed3dfcdccfddc0bEmmanuel Grumbach * @bc_table_dword: true if the BC table expects DWORD (as opposed to bytes) 2603a736bcb18f797996064cf18f4eecc4b3e46d39aEmmanuel Grumbach * @scd_set_active: should the transport configure the SCD for HCMD queue 261b2cf410ccb927141e69aa610b6dcf5137701f3afJohannes Berg * @rx_page_order: page order for receive buffer size 2627c5ba4a830cbb730770129b0004e2a06e47dbac5Johannes Berg * @wd_timeout: queue watchdog timeout (jiffies) 263e56b04efc1f795da42cf1d9651b52a4a5bebd730Lilach Edelstein * @reg_lock: protect hw register access 264b9439491055a18ee075614139abadfd74c1b887fEmmanuel Grumbach * @cmd_in_flight: true when we have a host command in flight 265c2d202017da18ebd6567862bd9a50392970f048fEmmanuel Grumbach * @fw_mon_phys: physical address of the buffer for the firmware monitor 266c2d202017da18ebd6567862bd9a50392970f048fEmmanuel Grumbach * @fw_mon_page: points to the first page of the buffer for the firmware monitor 267c2d202017da18ebd6567862bd9a50392970f048fEmmanuel Grumbach * @fw_mon_size: size of the buffer for the firmware monitor 268e6bb4c9c00892c488f3218ea317dc6a71674faf4Emmanuel Grumbach */ 269e6bb4c9c00892c488f3218ea317dc6a71674faf4Emmanuel Grumbachstruct iwl_trans_pcie { 270990aa6d7b28d26bf22171410b49f191e8e9b09fcEmmanuel Grumbach struct iwl_rxq rxq; 2715a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach struct work_struct rx_replenish; 2725a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach struct iwl_trans *trans; 2739130bab137844d9ad3db6ab524de299cd2b9e39dEmmanuel Grumbach struct iwl_drv *drv; 2740c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach 275f14d6b39c0b3519f8148e1371d2149c148893b61Johannes Berg struct net_device napi_dev; 276f14d6b39c0b3519f8148e1371d2149c148893b61Johannes Berg struct napi_struct napi; 277f14d6b39c0b3519f8148e1371d2149c148893b61Johannes Berg 2780c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach /* INT ICT Table */ 2790c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach __le32 *ict_tbl; 2800c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach dma_addr_t ict_tbl_dma; 2810c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach int ict_index; 2820c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach bool use_ict; 2831f7b6172db86e9ab2b4cd794441bb2c40ab287fcEmmanuel Grumbach struct isr_statistics isr_stats; 2840c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach 2857b11488fbbbe06ada39a396dec16532db8c933e6Johannes Berg spinlock_t irq_lock; 2860c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach u32 inta_mask; 287105183b156b7c220b47c3162e087101a0a6abc9fEmmanuel Grumbach u32 scd_base_addr; 288105183b156b7c220b47c3162e087101a0a6abc9fEmmanuel Grumbach struct iwl_dma_ptr scd_bc_tbls; 2899d6b2cb1ccf9c1e00a0891eff78b93eb1a1fc372Emmanuel Grumbach struct iwl_dma_ptr kw; 290e13c0c59e0ec38558ac853d56555e915b4dc7dc2Emmanuel Grumbach 291990aa6d7b28d26bf22171410b49f191e8e9b09fcEmmanuel Grumbach struct iwl_txq *txq; 2929eae88fa9a02e31af69a215beaa5e1194da3a5a1Johannes Berg unsigned long queue_used[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)]; 2938ad71bef4a9d8173cbcfbb2f796b08d33d4ca01bEmmanuel Grumbach unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)]; 294a42a184458ae95937893cb873c988385637c5e14Emmanuel Grumbach 295a42a184458ae95937893cb873c988385637c5e14Emmanuel Grumbach /* PCI bus related data */ 296a42a184458ae95937893cb873c988385637c5e14Emmanuel Grumbach struct pci_dev *pci_dev; 297a42a184458ae95937893cb873c988385637c5e14Emmanuel Grumbach void __iomem *hw_base; 29813df1aab4aa3cd99693c0cdeb7177e5359218431Johannes Berg 29913df1aab4aa3cd99693c0cdeb7177e5359218431Johannes Berg bool ucode_write_complete; 30013df1aab4aa3cd99693c0cdeb7177e5359218431Johannes Berg wait_queue_head_t ucode_write_waitq; 301f946b529502399d09471c5d13845fefbfe8555a6Emmanuel Grumbach wait_queue_head_t wait_command_queue; 302f946b529502399d09471c5d13845fefbfe8555a6Emmanuel Grumbach 303c6f600fcfe8a7e4f594fc4c80b2c7b66f248958bMeenakshi Venkataraman u8 cmd_queue; 304b04db9ac4f7641332e0133b2fd8f82e6e4553947Emmanuel Grumbach u8 cmd_fifo; 305d663ee73f62903aed334eca25832a76c4a7e4c1cJohannes Berg u8 n_no_reclaim_cmds; 306d663ee73f62903aed334eca25832a76c4a7e4c1cJohannes Berg u8 no_reclaim_cmds[MAX_NO_RECLAIM_CMDS]; 307b2cf410ccb927141e69aa610b6dcf5137701f3afJohannes Berg 308b2cf410ccb927141e69aa610b6dcf5137701f3afJohannes Berg bool rx_buf_size_8k; 309046db346386661906dffa33f5ed3dfcdccfddc0bEmmanuel Grumbach bool bc_table_dword; 3103a736bcb18f797996064cf18f4eecc4b3e46d39aEmmanuel Grumbach bool scd_set_active; 311b2cf410ccb927141e69aa610b6dcf5137701f3afJohannes Berg u32 rx_page_order; 3127c5ba4a830cbb730770129b0004e2a06e47dbac5Johannes Berg 313e5209263df94a41090199c95b21939139760fd85Johannes Berg const char *const *command_names; 3147c5ba4a830cbb730770129b0004e2a06e47dbac5Johannes Berg 3157c5ba4a830cbb730770129b0004e2a06e47dbac5Johannes Berg /* queue watchdog */ 3167c5ba4a830cbb730770129b0004e2a06e47dbac5Johannes Berg unsigned long wd_timeout; 317e56b04efc1f795da42cf1d9651b52a4a5bebd730Lilach Edelstein 318e56b04efc1f795da42cf1d9651b52a4a5bebd730Lilach Edelstein /*protect hw register */ 319e56b04efc1f795da42cf1d9651b52a4a5bebd730Lilach Edelstein spinlock_t reg_lock; 320b9439491055a18ee075614139abadfd74c1b887fEmmanuel Grumbach bool cmd_in_flight; 321c2d202017da18ebd6567862bd9a50392970f048fEmmanuel Grumbach 322c2d202017da18ebd6567862bd9a50392970f048fEmmanuel Grumbach dma_addr_t fw_mon_phys; 323c2d202017da18ebd6567862bd9a50392970f048fEmmanuel Grumbach struct page *fw_mon_page; 324c2d202017da18ebd6567862bd9a50392970f048fEmmanuel Grumbach u32 fw_mon_size; 325e6bb4c9c00892c488f3218ea317dc6a71674faf4Emmanuel Grumbach}; 326e6bb4c9c00892c488f3218ea317dc6a71674faf4Emmanuel Grumbach 3275a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach#define IWL_TRANS_GET_PCIE_TRANS(_iwl_trans) \ 3285a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach ((struct iwl_trans_pcie *) ((_iwl_trans)->trans_specific)) 3295a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach 3307c5ba4a830cbb730770129b0004e2a06e47dbac5Johannes Bergstatic inline struct iwl_trans * 3317c5ba4a830cbb730770129b0004e2a06e47dbac5Johannes Bergiwl_trans_pcie_get_trans(struct iwl_trans_pcie *trans_pcie) 3327c5ba4a830cbb730770129b0004e2a06e47dbac5Johannes Berg{ 3337c5ba4a830cbb730770129b0004e2a06e47dbac5Johannes Berg return container_of((void *)trans_pcie, struct iwl_trans, 3347c5ba4a830cbb730770129b0004e2a06e47dbac5Johannes Berg trans_specific); 3357c5ba4a830cbb730770129b0004e2a06e47dbac5Johannes Berg} 3367c5ba4a830cbb730770129b0004e2a06e47dbac5Johannes Berg 337f02831be962c7be68c72110fa779e916ab1a8cddEmmanuel Grumbach/* 338f02831be962c7be68c72110fa779e916ab1a8cddEmmanuel Grumbach * Convention: trans API functions: iwl_trans_pcie_XXX 339f02831be962c7be68c72110fa779e916ab1a8cddEmmanuel Grumbach * Other functions: iwl_pcie_XXX 340f02831be962c7be68c72110fa779e916ab1a8cddEmmanuel Grumbach */ 341d1ff52536a0d1bd516a628ef43dfaf6fe9c90fe2Johannes Bergstruct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, 342d1ff52536a0d1bd516a628ef43dfaf6fe9c90fe2Johannes Berg const struct pci_device_id *ent, 343d1ff52536a0d1bd516a628ef43dfaf6fe9c90fe2Johannes Berg const struct iwl_cfg *cfg); 344d1ff52536a0d1bd516a628ef43dfaf6fe9c90fe2Johannes Bergvoid iwl_trans_pcie_free(struct iwl_trans *trans); 345d1ff52536a0d1bd516a628ef43dfaf6fe9c90fe2Johannes Berg 346253a634ccd1b291282cd0cade219bd90eb0371ebEmmanuel Grumbach/***************************************************** 347253a634ccd1b291282cd0cade219bd90eb0371ebEmmanuel Grumbach* RX 348253a634ccd1b291282cd0cade219bd90eb0371ebEmmanuel Grumbach******************************************************/ 3499805c4460ae37aa9328a470c7aebea32f0667e24Emmanuel Grumbachint iwl_pcie_rx_init(struct iwl_trans *trans); 3502bfb50924c7e92362ac937aef2ab56bc7bd3ca52Johannes Bergirqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id); 3519805c4460ae37aa9328a470c7aebea32f0667e24Emmanuel Grumbachint iwl_pcie_rx_stop(struct iwl_trans *trans); 3529805c4460ae37aa9328a470c7aebea32f0667e24Emmanuel Grumbachvoid iwl_pcie_rx_free(struct iwl_trans *trans); 353ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach 354253a634ccd1b291282cd0cade219bd90eb0371ebEmmanuel Grumbach/***************************************************** 355990aa6d7b28d26bf22171410b49f191e8e9b09fcEmmanuel Grumbach* ICT - interrupt handling 3561a361cd838173879672cb0f0ebe1e7654d7edff6Emmanuel Grumbach******************************************************/ 35785bf9da1936bb0a0d81afab05b67beed2f253343Emmanuel Grumbachirqreturn_t iwl_pcie_isr(int irq, void *data); 358990aa6d7b28d26bf22171410b49f191e8e9b09fcEmmanuel Grumbachint iwl_pcie_alloc_ict(struct iwl_trans *trans); 359990aa6d7b28d26bf22171410b49f191e8e9b09fcEmmanuel Grumbachvoid iwl_pcie_free_ict(struct iwl_trans *trans); 360990aa6d7b28d26bf22171410b49f191e8e9b09fcEmmanuel Grumbachvoid iwl_pcie_reset_ict(struct iwl_trans *trans); 361990aa6d7b28d26bf22171410b49f191e8e9b09fcEmmanuel Grumbachvoid iwl_pcie_disable_ict(struct iwl_trans *trans); 3621a361cd838173879672cb0f0ebe1e7654d7edff6Emmanuel Grumbach 3631a361cd838173879672cb0f0ebe1e7654d7edff6Emmanuel Grumbach/***************************************************** 364253a634ccd1b291282cd0cade219bd90eb0371ebEmmanuel Grumbach* TX / HCMD 365253a634ccd1b291282cd0cade219bd90eb0371ebEmmanuel Grumbach******************************************************/ 366f02831be962c7be68c72110fa779e916ab1a8cddEmmanuel Grumbachint iwl_pcie_tx_init(struct iwl_trans *trans); 367f02831be962c7be68c72110fa779e916ab1a8cddEmmanuel Grumbachvoid iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr); 368f02831be962c7be68c72110fa779e916ab1a8cddEmmanuel Grumbachint iwl_pcie_tx_stop(struct iwl_trans *trans); 369f02831be962c7be68c72110fa779e916ab1a8cddEmmanuel Grumbachvoid iwl_pcie_tx_free(struct iwl_trans *trans); 370fea7795f1c976513a3262284c4001606075abf5cJohannes Bergvoid iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int queue, u16 ssn, 371fea7795f1c976513a3262284c4001606075abf5cJohannes Berg const struct iwl_trans_txq_scd_cfg *cfg); 372d4578ea810ce468fdb8e1b7014818c31db9be5e2Johannes Bergvoid iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int queue, 373d4578ea810ce468fdb8e1b7014818c31db9be5e2Johannes Berg bool configure_scd); 374f02831be962c7be68c72110fa779e916ab1a8cddEmmanuel Grumbachint iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb, 375f02831be962c7be68c72110fa779e916ab1a8cddEmmanuel Grumbach struct iwl_device_cmd *dev_cmd, int txq_id); 376ea68f46070c7bae608c619ae048f0ad995db74c3Johannes Bergvoid iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans); 377f02831be962c7be68c72110fa779e916ab1a8cddEmmanuel Grumbachint iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd); 378990aa6d7b28d26bf22171410b49f191e8e9b09fcEmmanuel Grumbachvoid iwl_pcie_hcmd_complete(struct iwl_trans *trans, 379990aa6d7b28d26bf22171410b49f191e8e9b09fcEmmanuel Grumbach struct iwl_rx_cmd_buffer *rxb, int handler_status); 380f02831be962c7be68c72110fa779e916ab1a8cddEmmanuel Grumbachvoid iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn, 381f02831be962c7be68c72110fa779e916ab1a8cddEmmanuel Grumbach struct sk_buff_head *skbs); 382ddaf5a5b300b8f9d3591b509fd8bedab1c9887beJohannes Bergvoid iwl_trans_pcie_tx_reset(struct iwl_trans *trans); 383ddaf5a5b300b8f9d3591b509fd8bedab1c9887beJohannes Berg 3844d075007d60f871a1d8842809f92b0d23487173aJohannes Bergstatic inline u16 iwl_pcie_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx) 3854d075007d60f871a1d8842809f92b0d23487173aJohannes Berg{ 3864d075007d60f871a1d8842809f92b0d23487173aJohannes Berg struct iwl_tfd_tb *tb = &tfd->tbs[idx]; 3874d075007d60f871a1d8842809f92b0d23487173aJohannes Berg 3884d075007d60f871a1d8842809f92b0d23487173aJohannes Berg return le16_to_cpu(tb->hi_n_len) >> 4; 3894d075007d60f871a1d8842809f92b0d23487173aJohannes Berg} 3904d075007d60f871a1d8842809f92b0d23487173aJohannes Berg 3917ff94706a055f3e21710b08ffbe3979d7db615dbEmmanuel Grumbach/***************************************************** 3927ff94706a055f3e21710b08ffbe3979d7db615dbEmmanuel Grumbach* Error handling 3937ff94706a055f3e21710b08ffbe3979d7db615dbEmmanuel Grumbach******************************************************/ 394990aa6d7b28d26bf22171410b49f191e8e9b09fcEmmanuel Grumbachvoid iwl_pcie_dump_csr(struct iwl_trans *trans); 39516db88ba51d669ef63c58990771a47208913152cEmmanuel Grumbach 3968ad71bef4a9d8173cbcfbb2f796b08d33d4ca01bEmmanuel Grumbach/***************************************************** 3978ad71bef4a9d8173cbcfbb2f796b08d33d4ca01bEmmanuel Grumbach* Helpers 3988ad71bef4a9d8173cbcfbb2f796b08d33d4ca01bEmmanuel Grumbach******************************************************/ 3990c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbachstatic inline void iwl_disable_interrupts(struct iwl_trans *trans) 4000c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach{ 401eb7ff77edd391f215deee3ee5d957c857121cd72Arik Nemtsov clear_bit(STATUS_INT_ENABLED, &trans->status); 4020c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach 4030c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach /* disable interrupts from uCode/NIC to host */ 4041042db2af183b96cdce5972014d85e8bca0634adEmmanuel Grumbach iwl_write32(trans, CSR_INT_MASK, 0x00000000); 4050c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach 4060c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach /* acknowledge/clear/reset any interrupts still pending 4070c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach * from uCode or flow handler (Rx/Tx DMA) */ 4081042db2af183b96cdce5972014d85e8bca0634adEmmanuel Grumbach iwl_write32(trans, CSR_INT, 0xffffffff); 4091042db2af183b96cdce5972014d85e8bca0634adEmmanuel Grumbach iwl_write32(trans, CSR_FH_INT_STATUS, 0xffffffff); 4100c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach IWL_DEBUG_ISR(trans, "Disabled interrupts\n"); 4110c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach} 4120c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach 4130c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbachstatic inline void iwl_enable_interrupts(struct iwl_trans *trans) 4140c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach{ 41583626404a70da74c67f32f119e53c0ba032ba2d8Don Fry struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 4160c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach 4170c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach IWL_DEBUG_ISR(trans, "Enabling interrupts\n"); 418eb7ff77edd391f215deee3ee5d957c857121cd72Arik Nemtsov set_bit(STATUS_INT_ENABLED, &trans->status); 4192dbc368d7fded35ed221a3751405b15e06eb8925Emmanuel Grumbach trans_pcie->inta_mask = CSR_INI_SET_MASK; 4201042db2af183b96cdce5972014d85e8bca0634adEmmanuel Grumbach iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); 4210c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach} 4220c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach 4238722c899a07f45457464803142bd1c2d2a2c3bd8Stanislaw Gruszkastatic inline void iwl_enable_rfkill_int(struct iwl_trans *trans) 4248722c899a07f45457464803142bd1c2d2a2c3bd8Stanislaw Gruszka{ 4252dbc368d7fded35ed221a3751405b15e06eb8925Emmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 4262dbc368d7fded35ed221a3751405b15e06eb8925Emmanuel Grumbach 4278722c899a07f45457464803142bd1c2d2a2c3bd8Stanislaw Gruszka IWL_DEBUG_ISR(trans, "Enabling rfkill interrupt\n"); 4282dbc368d7fded35ed221a3751405b15e06eb8925Emmanuel Grumbach trans_pcie->inta_mask = CSR_INT_BIT_RF_KILL; 4292dbc368d7fded35ed221a3751405b15e06eb8925Emmanuel Grumbach iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); 4308722c899a07f45457464803142bd1c2d2a2c3bd8Stanislaw Gruszka} 4318722c899a07f45457464803142bd1c2d2a2c3bd8Stanislaw Gruszka 432e20d434170c3a7f388d5e916825499c9c0738606Emmanuel Grumbachstatic inline void iwl_wake_queue(struct iwl_trans *trans, 433990aa6d7b28d26bf22171410b49f191e8e9b09fcEmmanuel Grumbach struct iwl_txq *txq) 434e20d434170c3a7f388d5e916825499c9c0738606Emmanuel Grumbach{ 4359eae88fa9a02e31af69a215beaa5e1194da3a5a1Johannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 4369eae88fa9a02e31af69a215beaa5e1194da3a5a1Johannes Berg 4379eae88fa9a02e31af69a215beaa5e1194da3a5a1Johannes Berg if (test_and_clear_bit(txq->q.id, trans_pcie->queue_stopped)) { 4389eae88fa9a02e31af69a215beaa5e1194da3a5a1Johannes Berg IWL_DEBUG_TX_QUEUES(trans, "Wake hwq %d\n", txq->q.id); 4399eae88fa9a02e31af69a215beaa5e1194da3a5a1Johannes Berg iwl_op_mode_queue_not_full(trans->op_mode, txq->q.id); 44081a3de1ce2929fef2b112c048c50bc52b686f94dEmmanuel Grumbach } 441e20d434170c3a7f388d5e916825499c9c0738606Emmanuel Grumbach} 442e20d434170c3a7f388d5e916825499c9c0738606Emmanuel Grumbach 443e20d434170c3a7f388d5e916825499c9c0738606Emmanuel Grumbachstatic inline void iwl_stop_queue(struct iwl_trans *trans, 444990aa6d7b28d26bf22171410b49f191e8e9b09fcEmmanuel Grumbach struct iwl_txq *txq) 445e20d434170c3a7f388d5e916825499c9c0738606Emmanuel Grumbach{ 4469eae88fa9a02e31af69a215beaa5e1194da3a5a1Johannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 4478ad71bef4a9d8173cbcfbb2f796b08d33d4ca01bEmmanuel Grumbach 4489eae88fa9a02e31af69a215beaa5e1194da3a5a1Johannes Berg if (!test_and_set_bit(txq->q.id, trans_pcie->queue_stopped)) { 4499eae88fa9a02e31af69a215beaa5e1194da3a5a1Johannes Berg iwl_op_mode_queue_full(trans->op_mode, txq->q.id); 4509eae88fa9a02e31af69a215beaa5e1194da3a5a1Johannes Berg IWL_DEBUG_TX_QUEUES(trans, "Stop hwq %d\n", txq->q.id); 4519eae88fa9a02e31af69a215beaa5e1194da3a5a1Johannes Berg } else 4529eae88fa9a02e31af69a215beaa5e1194da3a5a1Johannes Berg IWL_DEBUG_TX_QUEUES(trans, "hwq %d already stopped\n", 4539eae88fa9a02e31af69a215beaa5e1194da3a5a1Johannes Berg txq->q.id); 4548ad71bef4a9d8173cbcfbb2f796b08d33d4ca01bEmmanuel Grumbach} 4558ad71bef4a9d8173cbcfbb2f796b08d33d4ca01bEmmanuel Grumbach 4566ca6ebc1606c6fa7e8931445e84f21f4843e3babEmmanuel Grumbachstatic inline bool iwl_queue_used(const struct iwl_queue *q, int i) 4578ad71bef4a9d8173cbcfbb2f796b08d33d4ca01bEmmanuel Grumbach{ 4588ad71bef4a9d8173cbcfbb2f796b08d33d4ca01bEmmanuel Grumbach return q->write_ptr >= q->read_ptr ? 4598ad71bef4a9d8173cbcfbb2f796b08d33d4ca01bEmmanuel Grumbach (i >= q->read_ptr && i < q->write_ptr) : 4608ad71bef4a9d8173cbcfbb2f796b08d33d4ca01bEmmanuel Grumbach !(i < q->read_ptr && i >= q->write_ptr); 4618ad71bef4a9d8173cbcfbb2f796b08d33d4ca01bEmmanuel Grumbach} 4628ad71bef4a9d8173cbcfbb2f796b08d33d4ca01bEmmanuel Grumbach 4638ad71bef4a9d8173cbcfbb2f796b08d33d4ca01bEmmanuel Grumbachstatic inline u8 get_cmd_index(struct iwl_queue *q, u32 index) 4648ad71bef4a9d8173cbcfbb2f796b08d33d4ca01bEmmanuel Grumbach{ 4658ad71bef4a9d8173cbcfbb2f796b08d33d4ca01bEmmanuel Grumbach return index & (q->n_window - 1); 4668ad71bef4a9d8173cbcfbb2f796b08d33d4ca01bEmmanuel Grumbach} 4678ad71bef4a9d8173cbcfbb2f796b08d33d4ca01bEmmanuel Grumbach 468990aa6d7b28d26bf22171410b49f191e8e9b09fcEmmanuel Grumbachstatic inline const char *get_cmd_string(struct iwl_trans_pcie *trans_pcie, 469990aa6d7b28d26bf22171410b49f191e8e9b09fcEmmanuel Grumbach u8 cmd) 470d9fb6465802c2279ea14cc26eb66d17c133478b1Johannes Berg{ 471d9fb6465802c2279ea14cc26eb66d17c133478b1Johannes Berg if (!trans_pcie->command_names || !trans_pcie->command_names[cmd]) 472d9fb6465802c2279ea14cc26eb66d17c133478b1Johannes Berg return "UNKNOWN"; 473d9fb6465802c2279ea14cc26eb66d17c133478b1Johannes Berg return trans_pcie->command_names[cmd]; 474d9fb6465802c2279ea14cc26eb66d17c133478b1Johannes Berg} 475d9fb6465802c2279ea14cc26eb66d17c133478b1Johannes Berg 4768d425517f1f08f01a6171d22e05be62ef6ad93fcEmmanuel Grumbachstatic inline bool iwl_is_rfkill_set(struct iwl_trans *trans) 4778d425517f1f08f01a6171d22e05be62ef6ad93fcEmmanuel Grumbach{ 4788d425517f1f08f01a6171d22e05be62ef6ad93fcEmmanuel Grumbach return !(iwl_read32(trans, CSR_GP_CNTRL) & 4798d425517f1f08f01a6171d22e05be62ef6ad93fcEmmanuel Grumbach CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW); 4808d425517f1f08f01a6171d22e05be62ef6ad93fcEmmanuel Grumbach} 4818d425517f1f08f01a6171d22e05be62ef6ad93fcEmmanuel Grumbach 482b9439491055a18ee075614139abadfd74c1b887fEmmanuel Grumbachstatic inline void __iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, 483b9439491055a18ee075614139abadfd74c1b887fEmmanuel Grumbach u32 reg, u32 mask, u32 value) 484b9439491055a18ee075614139abadfd74c1b887fEmmanuel Grumbach{ 485b9439491055a18ee075614139abadfd74c1b887fEmmanuel Grumbach u32 v; 486b9439491055a18ee075614139abadfd74c1b887fEmmanuel Grumbach 487b9439491055a18ee075614139abadfd74c1b887fEmmanuel Grumbach#ifdef CONFIG_IWLWIFI_DEBUG 488b9439491055a18ee075614139abadfd74c1b887fEmmanuel Grumbach WARN_ON_ONCE(value & ~mask); 489b9439491055a18ee075614139abadfd74c1b887fEmmanuel Grumbach#endif 490b9439491055a18ee075614139abadfd74c1b887fEmmanuel Grumbach 491b9439491055a18ee075614139abadfd74c1b887fEmmanuel Grumbach v = iwl_read32(trans, reg); 492b9439491055a18ee075614139abadfd74c1b887fEmmanuel Grumbach v &= ~mask; 493b9439491055a18ee075614139abadfd74c1b887fEmmanuel Grumbach v |= value; 494b9439491055a18ee075614139abadfd74c1b887fEmmanuel Grumbach iwl_write32(trans, reg, v); 495b9439491055a18ee075614139abadfd74c1b887fEmmanuel Grumbach} 496b9439491055a18ee075614139abadfd74c1b887fEmmanuel Grumbach 497b9439491055a18ee075614139abadfd74c1b887fEmmanuel Grumbachstatic inline void __iwl_trans_pcie_clear_bit(struct iwl_trans *trans, 498b9439491055a18ee075614139abadfd74c1b887fEmmanuel Grumbach u32 reg, u32 mask) 499b9439491055a18ee075614139abadfd74c1b887fEmmanuel Grumbach{ 500b9439491055a18ee075614139abadfd74c1b887fEmmanuel Grumbach __iwl_trans_pcie_set_bits_mask(trans, reg, mask, 0); 501b9439491055a18ee075614139abadfd74c1b887fEmmanuel Grumbach} 502b9439491055a18ee075614139abadfd74c1b887fEmmanuel Grumbach 503b9439491055a18ee075614139abadfd74c1b887fEmmanuel Grumbachstatic inline void __iwl_trans_pcie_set_bit(struct iwl_trans *trans, 504b9439491055a18ee075614139abadfd74c1b887fEmmanuel Grumbach u32 reg, u32 mask) 505b9439491055a18ee075614139abadfd74c1b887fEmmanuel Grumbach{ 506b9439491055a18ee075614139abadfd74c1b887fEmmanuel Grumbach __iwl_trans_pcie_set_bits_mask(trans, reg, mask, mask); 507b9439491055a18ee075614139abadfd74c1b887fEmmanuel Grumbach} 508b9439491055a18ee075614139abadfd74c1b887fEmmanuel Grumbach 50914cfca7152ae5d10b15baf01c7fd60f0f0871062Johannes Bergvoid iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state); 51014cfca7152ae5d10b15baf01c7fd60f0f0871062Johannes Berg 511ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach#endif /* __iwl_trans_int_pcie_h__ */ 512