internal.h revision 51368bf792c79eb917694a4155d62f04359e3734
1ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach/****************************************************************************** 2ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * 351368bf792c79eb917694a4155d62f04359e3734Emmanuel Grumbach * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved. 4ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * 5ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * Portions of this file are derived from the ipw3945 project, as well 6ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * as portions of the ieee80211 subsystem header files. 7ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * 8ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * This program is free software; you can redistribute it and/or modify it 9ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * under the terms of version 2 of the GNU General Public License as 10ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * published by the Free Software Foundation. 11ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * 12ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * This program is distributed in the hope that it will be useful, but WITHOUT 13ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * more details. 16ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * 17ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * You should have received a copy of the GNU General Public License along with 18ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * this program; if not, write to the Free Software Foundation, Inc., 19ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 20ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * 21ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * The full GNU General Public License is included in this distribution in the 22ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * file called LICENSE. 23ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * 24ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * Contact Information: 25ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * Intel Linux Wireless <ilw@linux.intel.com> 26ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 27ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * 28ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach *****************************************************************************/ 29ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach#ifndef __iwl_trans_int_pcie_h__ 30ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach#define __iwl_trans_int_pcie_h__ 31ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach 32a72b8b088c3465b28192c1a14ba97be8223a8cecEmmanuel Grumbach#include <linux/spinlock.h> 33a72b8b088c3465b28192c1a14ba97be8223a8cecEmmanuel Grumbach#include <linux/interrupt.h> 34a72b8b088c3465b28192c1a14ba97be8223a8cecEmmanuel Grumbach#include <linux/skbuff.h> 3513df1aab4aa3cd99693c0cdeb7177e5359218431Johannes Berg#include <linux/wait.h> 36522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach#include <linux/pci.h> 377c5ba4a830cbb730770129b0004e2a06e47dbac5Johannes Berg#include <linux/timer.h> 38a72b8b088c3465b28192c1a14ba97be8223a8cecEmmanuel Grumbach 39dda61a4482661d71034cc132d1f474f19ce34a4dEmmanuel Grumbach#include "iwl-fh.h" 40a72b8b088c3465b28192c1a14ba97be8223a8cecEmmanuel Grumbach#include "iwl-csr.h" 41a72b8b088c3465b28192c1a14ba97be8223a8cecEmmanuel Grumbach#include "iwl-trans.h" 42a72b8b088c3465b28192c1a14ba97be8223a8cecEmmanuel Grumbach#include "iwl-debug.h" 43a72b8b088c3465b28192c1a14ba97be8223a8cecEmmanuel Grumbach#include "iwl-io.h" 4402e3835884f352ac707dcf14d8bf455c0c0acbc5Emmanuel Grumbach#include "iwl-op-mode.h" 45a72b8b088c3465b28192c1a14ba97be8223a8cecEmmanuel Grumbach 46a72b8b088c3465b28192c1a14ba97be8223a8cecEmmanuel Grumbachstruct iwl_host_cmd; 47dda61a4482661d71034cc132d1f474f19ce34a4dEmmanuel Grumbach 48ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach/*This file includes the declaration that are internal to the 49ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * trans_pcie layer */ 50ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach 5148a2d66f58d2bf1818acf5ff7ed9897a9977a96eJohannes Bergstruct iwl_rx_mem_buffer { 5248a2d66f58d2bf1818acf5ff7ed9897a9977a96eJohannes Berg dma_addr_t page_dma; 5348a2d66f58d2bf1818acf5ff7ed9897a9977a96eJohannes Berg struct page *page; 5448a2d66f58d2bf1818acf5ff7ed9897a9977a96eJohannes Berg struct list_head list; 5548a2d66f58d2bf1818acf5ff7ed9897a9977a96eJohannes Berg}; 5648a2d66f58d2bf1818acf5ff7ed9897a9977a96eJohannes Berg 57e6bb4c9c00892c488f3218ea317dc6a71674faf4Emmanuel Grumbach/** 581f7b6172db86e9ab2b4cd794441bb2c40ab287fcEmmanuel Grumbach * struct isr_statistics - interrupt statistics 591f7b6172db86e9ab2b4cd794441bb2c40ab287fcEmmanuel Grumbach * 601f7b6172db86e9ab2b4cd794441bb2c40ab287fcEmmanuel Grumbach */ 611f7b6172db86e9ab2b4cd794441bb2c40ab287fcEmmanuel Grumbachstruct isr_statistics { 621f7b6172db86e9ab2b4cd794441bb2c40ab287fcEmmanuel Grumbach u32 hw; 631f7b6172db86e9ab2b4cd794441bb2c40ab287fcEmmanuel Grumbach u32 sw; 641f7b6172db86e9ab2b4cd794441bb2c40ab287fcEmmanuel Grumbach u32 err_code; 651f7b6172db86e9ab2b4cd794441bb2c40ab287fcEmmanuel Grumbach u32 sch; 661f7b6172db86e9ab2b4cd794441bb2c40ab287fcEmmanuel Grumbach u32 alive; 671f7b6172db86e9ab2b4cd794441bb2c40ab287fcEmmanuel Grumbach u32 rfkill; 681f7b6172db86e9ab2b4cd794441bb2c40ab287fcEmmanuel Grumbach u32 ctkill; 691f7b6172db86e9ab2b4cd794441bb2c40ab287fcEmmanuel Grumbach u32 wakeup; 701f7b6172db86e9ab2b4cd794441bb2c40ab287fcEmmanuel Grumbach u32 rx; 711f7b6172db86e9ab2b4cd794441bb2c40ab287fcEmmanuel Grumbach u32 tx; 721f7b6172db86e9ab2b4cd794441bb2c40ab287fcEmmanuel Grumbach u32 unhandled; 731f7b6172db86e9ab2b4cd794441bb2c40ab287fcEmmanuel Grumbach}; 741f7b6172db86e9ab2b4cd794441bb2c40ab287fcEmmanuel Grumbach 751f7b6172db86e9ab2b4cd794441bb2c40ab287fcEmmanuel Grumbach/** 76990aa6d7b28d26bf22171410b49f191e8e9b09fcEmmanuel Grumbach * struct iwl_rxq - Rx queue 775a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach * @bd: driver's pointer to buffer of receive buffer descriptors (rbd) 785a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach * @bd_dma: bus address of buffer of receive buffer descriptors (rbd) 795a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach * @pool: 805a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach * @queue: 815a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach * @read: Shared index to newest available Rx buffer 825a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach * @write: Shared index to oldest written Rx packet 835a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach * @free_count: Number of pre-allocated buffers in rx_free 845a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach * @write_actual: 855a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach * @rx_free: list of free SKBs for use 865a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach * @rx_used: List of Rx buffers with no SKB 875a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach * @need_update: flag to indicate we need to update read/write index 885a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach * @rb_stts: driver's pointer to receive buffer status 895a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach * @rb_stts_dma: bus address of receive buffer status 905a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach * @lock: 915a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach * 925a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers 935a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach */ 94990aa6d7b28d26bf22171410b49f191e8e9b09fcEmmanuel Grumbachstruct iwl_rxq { 955a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach __le32 *bd; 965a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach dma_addr_t bd_dma; 975a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS]; 985a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE]; 995a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach u32 read; 1005a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach u32 write; 1015a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach u32 free_count; 1025a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach u32 write_actual; 1035a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach struct list_head rx_free; 1045a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach struct list_head rx_used; 1055a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach int need_update; 1065a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach struct iwl_rb_status *rb_stts; 1075a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach dma_addr_t rb_stts_dma; 1085a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach spinlock_t lock; 1095a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach}; 1105a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach 111a72b8b088c3465b28192c1a14ba97be8223a8cecEmmanuel Grumbachstruct iwl_dma_ptr { 112a72b8b088c3465b28192c1a14ba97be8223a8cecEmmanuel Grumbach dma_addr_t dma; 113a72b8b088c3465b28192c1a14ba97be8223a8cecEmmanuel Grumbach void *addr; 114a72b8b088c3465b28192c1a14ba97be8223a8cecEmmanuel Grumbach size_t size; 115a72b8b088c3465b28192c1a14ba97be8223a8cecEmmanuel Grumbach}; 116a72b8b088c3465b28192c1a14ba97be8223a8cecEmmanuel Grumbach 117bffc66ce2210b149fd171eccad2aef9802c0b35dJohannes Berg/** 118bffc66ce2210b149fd171eccad2aef9802c0b35dJohannes Berg * iwl_queue_inc_wrap - increment queue index, wrap back to beginning 119bffc66ce2210b149fd171eccad2aef9802c0b35dJohannes Berg * @index -- current index 120bffc66ce2210b149fd171eccad2aef9802c0b35dJohannes Berg * @n_bd -- total number of entries in queue (must be power of 2) 121bffc66ce2210b149fd171eccad2aef9802c0b35dJohannes Berg */ 122bffc66ce2210b149fd171eccad2aef9802c0b35dJohannes Bergstatic inline int iwl_queue_inc_wrap(int index, int n_bd) 123bffc66ce2210b149fd171eccad2aef9802c0b35dJohannes Berg{ 124bffc66ce2210b149fd171eccad2aef9802c0b35dJohannes Berg return ++index & (n_bd - 1); 125bffc66ce2210b149fd171eccad2aef9802c0b35dJohannes Berg} 126bffc66ce2210b149fd171eccad2aef9802c0b35dJohannes Berg 127bffc66ce2210b149fd171eccad2aef9802c0b35dJohannes Berg/** 128bffc66ce2210b149fd171eccad2aef9802c0b35dJohannes Berg * iwl_queue_dec_wrap - decrement queue index, wrap back to end 129bffc66ce2210b149fd171eccad2aef9802c0b35dJohannes Berg * @index -- current index 130bffc66ce2210b149fd171eccad2aef9802c0b35dJohannes Berg * @n_bd -- total number of entries in queue (must be power of 2) 131bffc66ce2210b149fd171eccad2aef9802c0b35dJohannes Berg */ 132bffc66ce2210b149fd171eccad2aef9802c0b35dJohannes Bergstatic inline int iwl_queue_dec_wrap(int index, int n_bd) 133bffc66ce2210b149fd171eccad2aef9802c0b35dJohannes Berg{ 134bffc66ce2210b149fd171eccad2aef9802c0b35dJohannes Berg return --index & (n_bd - 1); 135bffc66ce2210b149fd171eccad2aef9802c0b35dJohannes Berg} 136bffc66ce2210b149fd171eccad2aef9802c0b35dJohannes Berg 137522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbachstruct iwl_cmd_meta { 138522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach /* only for SYNC commands, iff the reply skb is wanted */ 139522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach struct iwl_host_cmd *source; 140c14c73728b8feb01d9142f9241bf14601cfb86f7Johannes Berg u32 flags; 141522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach}; 142522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach 143522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach/* 144522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * Generic queue structure 145522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * 146522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * Contains common data for Rx and Tx queues. 147522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * 148522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * Note the difference between n_bd and n_window: the hardware 149522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * always assumes 256 descriptors, so n_bd is always 256 (unless 150522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * there might be HW changes in the future). For the normal TX 151522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * queues, n_window, which is the size of the software queue data 152522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * is also 256; however, for the command queue, n_window is only 153522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * 32 since we don't need so many commands pending. Since the HW 154522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * still uses 256 BDs for DMA though, n_bd stays 256. As a result, 155522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * the software buffers (in the variables @meta, @txb in struct 156990aa6d7b28d26bf22171410b49f191e8e9b09fcEmmanuel Grumbach * iwl_txq) only have 32 entries, while the HW buffers (@tfds in 157990aa6d7b28d26bf22171410b49f191e8e9b09fcEmmanuel Grumbach * the same struct) have 256. 158522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * This means that we end up with the following: 159522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * HW entries: | 0 | ... | N * 32 | ... | N * 32 + 31 | ... | 255 | 160522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * SW entries: | 0 | ... | 31 | 161522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * where N is a number between 0 and 7. This means that the SW 162522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * data is a window overlayed over the HW queue. 163522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach */ 164522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbachstruct iwl_queue { 165522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach int n_bd; /* number of BDs in this queue */ 166522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach int write_ptr; /* 1-st empty entry (index) host_w*/ 167522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach int read_ptr; /* last used entry (index) host_r*/ 168522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach /* use for monitoring and recovering the stuck queue */ 169522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach dma_addr_t dma_addr; /* physical addr for BD's */ 170522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach int n_window; /* safe queue window */ 171522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach u32 id; 172522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach int low_mark; /* low watermark, resume queue if free 173522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * space more than this */ 174522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach int high_mark; /* high watermark, stop queue if free 175522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * space less than this */ 176522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach}; 177522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach 178bf8440e6a6f5fabf7843dbfecb1745e49182fa1cJohannes Berg#define TFD_TX_CMD_SLOTS 256 179bf8440e6a6f5fabf7843dbfecb1745e49182fa1cJohannes Berg#define TFD_CMD_SLOTS 32 180bf8440e6a6f5fabf7843dbfecb1745e49182fa1cJohannes Berg 1818a964f44e01ad3bbc208c3e80d931ba91b9ea786Johannes Berg/* 1828a964f44e01ad3bbc208c3e80d931ba91b9ea786Johannes Berg * The FH will write back to the first TB only, so we need 1838a964f44e01ad3bbc208c3e80d931ba91b9ea786Johannes Berg * to copy some data into the buffer regardless of whether 18438c0f334b359953f010e9b921e0b55278d3918f7Johannes Berg * it should be mapped or not. This indicates how big the 18538c0f334b359953f010e9b921e0b55278d3918f7Johannes Berg * first TB must be to include the scratch buffer. Since 18638c0f334b359953f010e9b921e0b55278d3918f7Johannes Berg * the scratch is 4 bytes at offset 12, it's 16 now. If we 18738c0f334b359953f010e9b921e0b55278d3918f7Johannes Berg * make it bigger then allocations will be bigger and copy 18838c0f334b359953f010e9b921e0b55278d3918f7Johannes Berg * slower, so that's probably not useful. 1898a964f44e01ad3bbc208c3e80d931ba91b9ea786Johannes Berg */ 19038c0f334b359953f010e9b921e0b55278d3918f7Johannes Berg#define IWL_HCMD_SCRATCHBUF_SIZE 16 1918a964f44e01ad3bbc208c3e80d931ba91b9ea786Johannes Berg 192990aa6d7b28d26bf22171410b49f191e8e9b09fcEmmanuel Grumbachstruct iwl_pcie_txq_entry { 193bf8440e6a6f5fabf7843dbfecb1745e49182fa1cJohannes Berg struct iwl_device_cmd *cmd; 194bf8440e6a6f5fabf7843dbfecb1745e49182fa1cJohannes Berg struct sk_buff *skb; 195f4feb8ac6e666d2ca37cf722166bbfadf2c6adf8Johannes Berg /* buffer to free after command completes */ 196f4feb8ac6e666d2ca37cf722166bbfadf2c6adf8Johannes Berg const void *free_buf; 197bf8440e6a6f5fabf7843dbfecb1745e49182fa1cJohannes Berg struct iwl_cmd_meta meta; 198bf8440e6a6f5fabf7843dbfecb1745e49182fa1cJohannes Berg}; 199bf8440e6a6f5fabf7843dbfecb1745e49182fa1cJohannes Berg 20038c0f334b359953f010e9b921e0b55278d3918f7Johannes Bergstruct iwl_pcie_txq_scratch_buf { 20138c0f334b359953f010e9b921e0b55278d3918f7Johannes Berg struct iwl_cmd_header hdr; 20238c0f334b359953f010e9b921e0b55278d3918f7Johannes Berg u8 buf[8]; 20338c0f334b359953f010e9b921e0b55278d3918f7Johannes Berg __le32 scratch; 20438c0f334b359953f010e9b921e0b55278d3918f7Johannes Berg}; 20538c0f334b359953f010e9b921e0b55278d3918f7Johannes Berg 206522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach/** 207990aa6d7b28d26bf22171410b49f191e8e9b09fcEmmanuel Grumbach * struct iwl_txq - Tx Queue for DMA 208522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * @q: generic Rx/Tx queue descriptor 209bf8440e6a6f5fabf7843dbfecb1745e49182fa1cJohannes Berg * @tfds: transmit frame descriptors (DMA memory) 21038c0f334b359953f010e9b921e0b55278d3918f7Johannes Berg * @scratchbufs: start of command headers, including scratch buffers, for 21138c0f334b359953f010e9b921e0b55278d3918f7Johannes Berg * the writeback -- this is DMA memory and an array holding one buffer 21238c0f334b359953f010e9b921e0b55278d3918f7Johannes Berg * for each command on the queue 21338c0f334b359953f010e9b921e0b55278d3918f7Johannes Berg * @scratchbufs_dma: DMA address for the scratchbufs start 214bf8440e6a6f5fabf7843dbfecb1745e49182fa1cJohannes Berg * @entries: transmit entries (driver state) 215bf8440e6a6f5fabf7843dbfecb1745e49182fa1cJohannes Berg * @lock: queue lock 216bf8440e6a6f5fabf7843dbfecb1745e49182fa1cJohannes Berg * @stuck_timer: timer that fires if queue gets stuck 217bf8440e6a6f5fabf7843dbfecb1745e49182fa1cJohannes Berg * @trans_pcie: pointer back to transport (for timer) 218522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * @need_update: indicates need to update read/write index 219bf8440e6a6f5fabf7843dbfecb1745e49182fa1cJohannes Berg * @active: stores if queue is active 22068972c46f2975d3d61f9dc9f311f77bfc8a8b12bJohannes Berg * @ampdu: true if this queue is an ampdu queue for an specific RA/TID 221522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * 222522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame 223522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * descriptors) and required locking structures. 224522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach */ 225990aa6d7b28d26bf22171410b49f191e8e9b09fcEmmanuel Grumbachstruct iwl_txq { 226522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach struct iwl_queue q; 227522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach struct iwl_tfd *tfds; 22838c0f334b359953f010e9b921e0b55278d3918f7Johannes Berg struct iwl_pcie_txq_scratch_buf *scratchbufs; 22938c0f334b359953f010e9b921e0b55278d3918f7Johannes Berg dma_addr_t scratchbufs_dma; 230990aa6d7b28d26bf22171410b49f191e8e9b09fcEmmanuel Grumbach struct iwl_pcie_txq_entry *entries; 231015c15e1067c988fc87fb550b222f075c8d3f47cJohannes Berg spinlock_t lock; 2327c5ba4a830cbb730770129b0004e2a06e47dbac5Johannes Berg struct timer_list stuck_timer; 2337c5ba4a830cbb730770129b0004e2a06e47dbac5Johannes Berg struct iwl_trans_pcie *trans_pcie; 234522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach u8 need_update; 235522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach u8 active; 23668972c46f2975d3d61f9dc9f311f77bfc8a8b12bJohannes Berg bool ampdu; 237522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach}; 238522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach 23938c0f334b359953f010e9b921e0b55278d3918f7Johannes Bergstatic inline dma_addr_t 24038c0f334b359953f010e9b921e0b55278d3918f7Johannes Bergiwl_pcie_get_scratchbuf_dma(struct iwl_txq *txq, int idx) 24138c0f334b359953f010e9b921e0b55278d3918f7Johannes Berg{ 24238c0f334b359953f010e9b921e0b55278d3918f7Johannes Berg return txq->scratchbufs_dma + 24338c0f334b359953f010e9b921e0b55278d3918f7Johannes Berg sizeof(struct iwl_pcie_txq_scratch_buf) * idx; 24438c0f334b359953f010e9b921e0b55278d3918f7Johannes Berg} 24538c0f334b359953f010e9b921e0b55278d3918f7Johannes Berg 2465a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach/** 247e6bb4c9c00892c488f3218ea317dc6a71674faf4Emmanuel Grumbach * struct iwl_trans_pcie - PCIe transport specific data 2485a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach * @rxq: all the RX queue data 2495a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach * @rx_replenish: work that will be called when buffers need to be allocated 2509130bab137844d9ad3db6ab524de299cd2b9e39dEmmanuel Grumbach * @drv - pointer to iwl_drv 2515a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach * @trans: pointer to the generic transport area 252105183b156b7c220b47c3162e087101a0a6abc9fEmmanuel Grumbach * @scd_base_addr: scheduler sram base address in SRAM 253105183b156b7c220b47c3162e087101a0a6abc9fEmmanuel Grumbach * @scd_bc_tbls: pointer to the byte count table of the scheduler 2549d6b2cb1ccf9c1e00a0891eff78b93eb1a1fc372Emmanuel Grumbach * @kw: keep warm address 255a42a184458ae95937893cb873c988385637c5e14Emmanuel Grumbach * @pci_dev: basic pci-network driver stuff 256a42a184458ae95937893cb873c988385637c5e14Emmanuel Grumbach * @hw_base: pci hardware address support 25713df1aab4aa3cd99693c0cdeb7177e5359218431Johannes Berg * @ucode_write_complete: indicates that the ucode has been copied. 25813df1aab4aa3cd99693c0cdeb7177e5359218431Johannes Berg * @ucode_write_waitq: wait queue for uCode load 259c6f600fcfe8a7e4f594fc4c80b2c7b66f248958bMeenakshi Venkataraman * @cmd_queue - command queue number 260b2cf410ccb927141e69aa610b6dcf5137701f3afJohannes Berg * @rx_buf_size_8k: 8 kB RX buffer size 261046db346386661906dffa33f5ed3dfcdccfddc0bEmmanuel Grumbach * @bc_table_dword: true if the BC table expects DWORD (as opposed to bytes) 262b2cf410ccb927141e69aa610b6dcf5137701f3afJohannes Berg * @rx_page_order: page order for receive buffer size 2637c5ba4a830cbb730770129b0004e2a06e47dbac5Johannes Berg * @wd_timeout: queue watchdog timeout (jiffies) 264e56b04efc1f795da42cf1d9651b52a4a5bebd730Lilach Edelstein * @reg_lock: protect hw register access 265b9439491055a18ee075614139abadfd74c1b887fEmmanuel Grumbach * @cmd_in_flight: true when we have a host command in flight 266e6bb4c9c00892c488f3218ea317dc6a71674faf4Emmanuel Grumbach */ 267e6bb4c9c00892c488f3218ea317dc6a71674faf4Emmanuel Grumbachstruct iwl_trans_pcie { 268990aa6d7b28d26bf22171410b49f191e8e9b09fcEmmanuel Grumbach struct iwl_rxq rxq; 2695a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach struct work_struct rx_replenish; 2705a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach struct iwl_trans *trans; 2719130bab137844d9ad3db6ab524de299cd2b9e39dEmmanuel Grumbach struct iwl_drv *drv; 2720c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach 2730c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach /* INT ICT Table */ 2740c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach __le32 *ict_tbl; 2750c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach dma_addr_t ict_tbl_dma; 2760c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach int ict_index; 2770c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach bool use_ict; 2781f7b6172db86e9ab2b4cd794441bb2c40ab287fcEmmanuel Grumbach struct isr_statistics isr_stats; 2790c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach 2807b11488fbbbe06ada39a396dec16532db8c933e6Johannes Berg spinlock_t irq_lock; 2810c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach u32 inta_mask; 282105183b156b7c220b47c3162e087101a0a6abc9fEmmanuel Grumbach u32 scd_base_addr; 283105183b156b7c220b47c3162e087101a0a6abc9fEmmanuel Grumbach struct iwl_dma_ptr scd_bc_tbls; 2849d6b2cb1ccf9c1e00a0891eff78b93eb1a1fc372Emmanuel Grumbach struct iwl_dma_ptr kw; 285e13c0c59e0ec38558ac853d56555e915b4dc7dc2Emmanuel Grumbach 286990aa6d7b28d26bf22171410b49f191e8e9b09fcEmmanuel Grumbach struct iwl_txq *txq; 2879eae88fa9a02e31af69a215beaa5e1194da3a5a1Johannes Berg unsigned long queue_used[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)]; 2888ad71bef4a9d8173cbcfbb2f796b08d33d4ca01bEmmanuel Grumbach unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)]; 289a42a184458ae95937893cb873c988385637c5e14Emmanuel Grumbach 290a42a184458ae95937893cb873c988385637c5e14Emmanuel Grumbach /* PCI bus related data */ 291a42a184458ae95937893cb873c988385637c5e14Emmanuel Grumbach struct pci_dev *pci_dev; 292a42a184458ae95937893cb873c988385637c5e14Emmanuel Grumbach void __iomem *hw_base; 29313df1aab4aa3cd99693c0cdeb7177e5359218431Johannes Berg 29413df1aab4aa3cd99693c0cdeb7177e5359218431Johannes Berg bool ucode_write_complete; 29513df1aab4aa3cd99693c0cdeb7177e5359218431Johannes Berg wait_queue_head_t ucode_write_waitq; 296f946b529502399d09471c5d13845fefbfe8555a6Emmanuel Grumbach wait_queue_head_t wait_command_queue; 297f946b529502399d09471c5d13845fefbfe8555a6Emmanuel Grumbach 298c6f600fcfe8a7e4f594fc4c80b2c7b66f248958bMeenakshi Venkataraman u8 cmd_queue; 299b04db9ac4f7641332e0133b2fd8f82e6e4553947Emmanuel Grumbach u8 cmd_fifo; 300d663ee73f62903aed334eca25832a76c4a7e4c1cJohannes Berg u8 n_no_reclaim_cmds; 301d663ee73f62903aed334eca25832a76c4a7e4c1cJohannes Berg u8 no_reclaim_cmds[MAX_NO_RECLAIM_CMDS]; 302b2cf410ccb927141e69aa610b6dcf5137701f3afJohannes Berg 303b2cf410ccb927141e69aa610b6dcf5137701f3afJohannes Berg bool rx_buf_size_8k; 304046db346386661906dffa33f5ed3dfcdccfddc0bEmmanuel Grumbach bool bc_table_dword; 305b2cf410ccb927141e69aa610b6dcf5137701f3afJohannes Berg u32 rx_page_order; 3067c5ba4a830cbb730770129b0004e2a06e47dbac5Johannes Berg 307d9fb6465802c2279ea14cc26eb66d17c133478b1Johannes Berg const char **command_names; 3087c5ba4a830cbb730770129b0004e2a06e47dbac5Johannes Berg 3097c5ba4a830cbb730770129b0004e2a06e47dbac5Johannes Berg /* queue watchdog */ 3107c5ba4a830cbb730770129b0004e2a06e47dbac5Johannes Berg unsigned long wd_timeout; 311e56b04efc1f795da42cf1d9651b52a4a5bebd730Lilach Edelstein 312e56b04efc1f795da42cf1d9651b52a4a5bebd730Lilach Edelstein /*protect hw register */ 313e56b04efc1f795da42cf1d9651b52a4a5bebd730Lilach Edelstein spinlock_t reg_lock; 314b9439491055a18ee075614139abadfd74c1b887fEmmanuel Grumbach bool cmd_in_flight; 315e6bb4c9c00892c488f3218ea317dc6a71674faf4Emmanuel Grumbach}; 316e6bb4c9c00892c488f3218ea317dc6a71674faf4Emmanuel Grumbach 3175a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach#define IWL_TRANS_GET_PCIE_TRANS(_iwl_trans) \ 3185a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach ((struct iwl_trans_pcie *) ((_iwl_trans)->trans_specific)) 3195a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach 3207c5ba4a830cbb730770129b0004e2a06e47dbac5Johannes Bergstatic inline struct iwl_trans * 3217c5ba4a830cbb730770129b0004e2a06e47dbac5Johannes Bergiwl_trans_pcie_get_trans(struct iwl_trans_pcie *trans_pcie) 3227c5ba4a830cbb730770129b0004e2a06e47dbac5Johannes Berg{ 3237c5ba4a830cbb730770129b0004e2a06e47dbac5Johannes Berg return container_of((void *)trans_pcie, struct iwl_trans, 3247c5ba4a830cbb730770129b0004e2a06e47dbac5Johannes Berg trans_specific); 3257c5ba4a830cbb730770129b0004e2a06e47dbac5Johannes Berg} 3267c5ba4a830cbb730770129b0004e2a06e47dbac5Johannes Berg 327f02831be962c7be68c72110fa779e916ab1a8cddEmmanuel Grumbach/* 328f02831be962c7be68c72110fa779e916ab1a8cddEmmanuel Grumbach * Convention: trans API functions: iwl_trans_pcie_XXX 329f02831be962c7be68c72110fa779e916ab1a8cddEmmanuel Grumbach * Other functions: iwl_pcie_XXX 330f02831be962c7be68c72110fa779e916ab1a8cddEmmanuel Grumbach */ 331d1ff52536a0d1bd516a628ef43dfaf6fe9c90fe2Johannes Bergstruct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, 332d1ff52536a0d1bd516a628ef43dfaf6fe9c90fe2Johannes Berg const struct pci_device_id *ent, 333d1ff52536a0d1bd516a628ef43dfaf6fe9c90fe2Johannes Berg const struct iwl_cfg *cfg); 334d1ff52536a0d1bd516a628ef43dfaf6fe9c90fe2Johannes Bergvoid iwl_trans_pcie_free(struct iwl_trans *trans); 335d1ff52536a0d1bd516a628ef43dfaf6fe9c90fe2Johannes Berg 336253a634ccd1b291282cd0cade219bd90eb0371ebEmmanuel Grumbach/***************************************************** 337253a634ccd1b291282cd0cade219bd90eb0371ebEmmanuel Grumbach* RX 338253a634ccd1b291282cd0cade219bd90eb0371ebEmmanuel Grumbach******************************************************/ 3399805c4460ae37aa9328a470c7aebea32f0667e24Emmanuel Grumbachint iwl_pcie_rx_init(struct iwl_trans *trans); 3402bfb50924c7e92362ac937aef2ab56bc7bd3ca52Johannes Bergirqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id); 3419805c4460ae37aa9328a470c7aebea32f0667e24Emmanuel Grumbachint iwl_pcie_rx_stop(struct iwl_trans *trans); 3429805c4460ae37aa9328a470c7aebea32f0667e24Emmanuel Grumbachvoid iwl_pcie_rx_free(struct iwl_trans *trans); 343ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach 344253a634ccd1b291282cd0cade219bd90eb0371ebEmmanuel Grumbach/***************************************************** 345990aa6d7b28d26bf22171410b49f191e8e9b09fcEmmanuel Grumbach* ICT - interrupt handling 3461a361cd838173879672cb0f0ebe1e7654d7edff6Emmanuel Grumbach******************************************************/ 34785bf9da1936bb0a0d81afab05b67beed2f253343Emmanuel Grumbachirqreturn_t iwl_pcie_isr(int irq, void *data); 348990aa6d7b28d26bf22171410b49f191e8e9b09fcEmmanuel Grumbachint iwl_pcie_alloc_ict(struct iwl_trans *trans); 349990aa6d7b28d26bf22171410b49f191e8e9b09fcEmmanuel Grumbachvoid iwl_pcie_free_ict(struct iwl_trans *trans); 350990aa6d7b28d26bf22171410b49f191e8e9b09fcEmmanuel Grumbachvoid iwl_pcie_reset_ict(struct iwl_trans *trans); 351990aa6d7b28d26bf22171410b49f191e8e9b09fcEmmanuel Grumbachvoid iwl_pcie_disable_ict(struct iwl_trans *trans); 3521a361cd838173879672cb0f0ebe1e7654d7edff6Emmanuel Grumbach 3531a361cd838173879672cb0f0ebe1e7654d7edff6Emmanuel Grumbach/***************************************************** 354253a634ccd1b291282cd0cade219bd90eb0371ebEmmanuel Grumbach* TX / HCMD 355253a634ccd1b291282cd0cade219bd90eb0371ebEmmanuel Grumbach******************************************************/ 356f02831be962c7be68c72110fa779e916ab1a8cddEmmanuel Grumbachint iwl_pcie_tx_init(struct iwl_trans *trans); 357f02831be962c7be68c72110fa779e916ab1a8cddEmmanuel Grumbachvoid iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr); 358f02831be962c7be68c72110fa779e916ab1a8cddEmmanuel Grumbachint iwl_pcie_tx_stop(struct iwl_trans *trans); 359f02831be962c7be68c72110fa779e916ab1a8cddEmmanuel Grumbachvoid iwl_pcie_tx_free(struct iwl_trans *trans); 360f02831be962c7be68c72110fa779e916ab1a8cddEmmanuel Grumbachvoid iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, int fifo, 361f02831be962c7be68c72110fa779e916ab1a8cddEmmanuel Grumbach int sta_id, int tid, int frame_limit, u16 ssn); 362f02831be962c7be68c72110fa779e916ab1a8cddEmmanuel Grumbachvoid iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int queue); 363f02831be962c7be68c72110fa779e916ab1a8cddEmmanuel Grumbachint iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb, 364f02831be962c7be68c72110fa779e916ab1a8cddEmmanuel Grumbach struct iwl_device_cmd *dev_cmd, int txq_id); 365990aa6d7b28d26bf22171410b49f191e8e9b09fcEmmanuel Grumbachvoid iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans, struct iwl_txq *txq); 366f02831be962c7be68c72110fa779e916ab1a8cddEmmanuel Grumbachint iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd); 367990aa6d7b28d26bf22171410b49f191e8e9b09fcEmmanuel Grumbachvoid iwl_pcie_hcmd_complete(struct iwl_trans *trans, 368990aa6d7b28d26bf22171410b49f191e8e9b09fcEmmanuel Grumbach struct iwl_rx_cmd_buffer *rxb, int handler_status); 369f02831be962c7be68c72110fa779e916ab1a8cddEmmanuel Grumbachvoid iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn, 370f02831be962c7be68c72110fa779e916ab1a8cddEmmanuel Grumbach struct sk_buff_head *skbs); 371ddaf5a5b300b8f9d3591b509fd8bedab1c9887beJohannes Bergvoid iwl_trans_pcie_tx_reset(struct iwl_trans *trans); 372ddaf5a5b300b8f9d3591b509fd8bedab1c9887beJohannes Berg 3737ff94706a055f3e21710b08ffbe3979d7db615dbEmmanuel Grumbach/***************************************************** 3747ff94706a055f3e21710b08ffbe3979d7db615dbEmmanuel Grumbach* Error handling 3757ff94706a055f3e21710b08ffbe3979d7db615dbEmmanuel Grumbach******************************************************/ 376990aa6d7b28d26bf22171410b49f191e8e9b09fcEmmanuel Grumbachvoid iwl_pcie_dump_csr(struct iwl_trans *trans); 37716db88ba51d669ef63c58990771a47208913152cEmmanuel Grumbach 3788ad71bef4a9d8173cbcfbb2f796b08d33d4ca01bEmmanuel Grumbach/***************************************************** 3798ad71bef4a9d8173cbcfbb2f796b08d33d4ca01bEmmanuel Grumbach* Helpers 3808ad71bef4a9d8173cbcfbb2f796b08d33d4ca01bEmmanuel Grumbach******************************************************/ 3810c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbachstatic inline void iwl_disable_interrupts(struct iwl_trans *trans) 3820c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach{ 383eb7ff77edd391f215deee3ee5d957c857121cd72Arik Nemtsov clear_bit(STATUS_INT_ENABLED, &trans->status); 3840c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach 3850c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach /* disable interrupts from uCode/NIC to host */ 3861042db2af183b96cdce5972014d85e8bca0634adEmmanuel Grumbach iwl_write32(trans, CSR_INT_MASK, 0x00000000); 3870c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach 3880c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach /* acknowledge/clear/reset any interrupts still pending 3890c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach * from uCode or flow handler (Rx/Tx DMA) */ 3901042db2af183b96cdce5972014d85e8bca0634adEmmanuel Grumbach iwl_write32(trans, CSR_INT, 0xffffffff); 3911042db2af183b96cdce5972014d85e8bca0634adEmmanuel Grumbach iwl_write32(trans, CSR_FH_INT_STATUS, 0xffffffff); 3920c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach IWL_DEBUG_ISR(trans, "Disabled interrupts\n"); 3930c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach} 3940c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach 3950c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbachstatic inline void iwl_enable_interrupts(struct iwl_trans *trans) 3960c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach{ 39783626404a70da74c67f32f119e53c0ba032ba2d8Don Fry struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3980c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach 3990c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach IWL_DEBUG_ISR(trans, "Enabling interrupts\n"); 400eb7ff77edd391f215deee3ee5d957c857121cd72Arik Nemtsov set_bit(STATUS_INT_ENABLED, &trans->status); 4012dbc368d7fded35ed221a3751405b15e06eb8925Emmanuel Grumbach trans_pcie->inta_mask = CSR_INI_SET_MASK; 4021042db2af183b96cdce5972014d85e8bca0634adEmmanuel Grumbach iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); 4030c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach} 4040c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach 4058722c899a07f45457464803142bd1c2d2a2c3bd8Stanislaw Gruszkastatic inline void iwl_enable_rfkill_int(struct iwl_trans *trans) 4068722c899a07f45457464803142bd1c2d2a2c3bd8Stanislaw Gruszka{ 4072dbc368d7fded35ed221a3751405b15e06eb8925Emmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 4082dbc368d7fded35ed221a3751405b15e06eb8925Emmanuel Grumbach 4098722c899a07f45457464803142bd1c2d2a2c3bd8Stanislaw Gruszka IWL_DEBUG_ISR(trans, "Enabling rfkill interrupt\n"); 4102dbc368d7fded35ed221a3751405b15e06eb8925Emmanuel Grumbach trans_pcie->inta_mask = CSR_INT_BIT_RF_KILL; 4112dbc368d7fded35ed221a3751405b15e06eb8925Emmanuel Grumbach iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); 4128722c899a07f45457464803142bd1c2d2a2c3bd8Stanislaw Gruszka} 4138722c899a07f45457464803142bd1c2d2a2c3bd8Stanislaw Gruszka 414e20d434170c3a7f388d5e916825499c9c0738606Emmanuel Grumbachstatic inline void iwl_wake_queue(struct iwl_trans *trans, 415990aa6d7b28d26bf22171410b49f191e8e9b09fcEmmanuel Grumbach struct iwl_txq *txq) 416e20d434170c3a7f388d5e916825499c9c0738606Emmanuel Grumbach{ 4179eae88fa9a02e31af69a215beaa5e1194da3a5a1Johannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 4189eae88fa9a02e31af69a215beaa5e1194da3a5a1Johannes Berg 4199eae88fa9a02e31af69a215beaa5e1194da3a5a1Johannes Berg if (test_and_clear_bit(txq->q.id, trans_pcie->queue_stopped)) { 4209eae88fa9a02e31af69a215beaa5e1194da3a5a1Johannes Berg IWL_DEBUG_TX_QUEUES(trans, "Wake hwq %d\n", txq->q.id); 4219eae88fa9a02e31af69a215beaa5e1194da3a5a1Johannes Berg iwl_op_mode_queue_not_full(trans->op_mode, txq->q.id); 42281a3de1ce2929fef2b112c048c50bc52b686f94dEmmanuel Grumbach } 423e20d434170c3a7f388d5e916825499c9c0738606Emmanuel Grumbach} 424e20d434170c3a7f388d5e916825499c9c0738606Emmanuel Grumbach 425e20d434170c3a7f388d5e916825499c9c0738606Emmanuel Grumbachstatic inline void iwl_stop_queue(struct iwl_trans *trans, 426990aa6d7b28d26bf22171410b49f191e8e9b09fcEmmanuel Grumbach struct iwl_txq *txq) 427e20d434170c3a7f388d5e916825499c9c0738606Emmanuel Grumbach{ 4289eae88fa9a02e31af69a215beaa5e1194da3a5a1Johannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 4298ad71bef4a9d8173cbcfbb2f796b08d33d4ca01bEmmanuel Grumbach 4309eae88fa9a02e31af69a215beaa5e1194da3a5a1Johannes Berg if (!test_and_set_bit(txq->q.id, trans_pcie->queue_stopped)) { 4319eae88fa9a02e31af69a215beaa5e1194da3a5a1Johannes Berg iwl_op_mode_queue_full(trans->op_mode, txq->q.id); 4329eae88fa9a02e31af69a215beaa5e1194da3a5a1Johannes Berg IWL_DEBUG_TX_QUEUES(trans, "Stop hwq %d\n", txq->q.id); 4339eae88fa9a02e31af69a215beaa5e1194da3a5a1Johannes Berg } else 4349eae88fa9a02e31af69a215beaa5e1194da3a5a1Johannes Berg IWL_DEBUG_TX_QUEUES(trans, "hwq %d already stopped\n", 4359eae88fa9a02e31af69a215beaa5e1194da3a5a1Johannes Berg txq->q.id); 4368ad71bef4a9d8173cbcfbb2f796b08d33d4ca01bEmmanuel Grumbach} 4378ad71bef4a9d8173cbcfbb2f796b08d33d4ca01bEmmanuel Grumbach 4386ca6ebc1606c6fa7e8931445e84f21f4843e3babEmmanuel Grumbachstatic inline bool iwl_queue_used(const struct iwl_queue *q, int i) 4398ad71bef4a9d8173cbcfbb2f796b08d33d4ca01bEmmanuel Grumbach{ 4408ad71bef4a9d8173cbcfbb2f796b08d33d4ca01bEmmanuel Grumbach return q->write_ptr >= q->read_ptr ? 4418ad71bef4a9d8173cbcfbb2f796b08d33d4ca01bEmmanuel Grumbach (i >= q->read_ptr && i < q->write_ptr) : 4428ad71bef4a9d8173cbcfbb2f796b08d33d4ca01bEmmanuel Grumbach !(i < q->read_ptr && i >= q->write_ptr); 4438ad71bef4a9d8173cbcfbb2f796b08d33d4ca01bEmmanuel Grumbach} 4448ad71bef4a9d8173cbcfbb2f796b08d33d4ca01bEmmanuel Grumbach 4458ad71bef4a9d8173cbcfbb2f796b08d33d4ca01bEmmanuel Grumbachstatic inline u8 get_cmd_index(struct iwl_queue *q, u32 index) 4468ad71bef4a9d8173cbcfbb2f796b08d33d4ca01bEmmanuel Grumbach{ 4478ad71bef4a9d8173cbcfbb2f796b08d33d4ca01bEmmanuel Grumbach return index & (q->n_window - 1); 4488ad71bef4a9d8173cbcfbb2f796b08d33d4ca01bEmmanuel Grumbach} 4498ad71bef4a9d8173cbcfbb2f796b08d33d4ca01bEmmanuel Grumbach 450990aa6d7b28d26bf22171410b49f191e8e9b09fcEmmanuel Grumbachstatic inline const char *get_cmd_string(struct iwl_trans_pcie *trans_pcie, 451990aa6d7b28d26bf22171410b49f191e8e9b09fcEmmanuel Grumbach u8 cmd) 452d9fb6465802c2279ea14cc26eb66d17c133478b1Johannes Berg{ 453d9fb6465802c2279ea14cc26eb66d17c133478b1Johannes Berg if (!trans_pcie->command_names || !trans_pcie->command_names[cmd]) 454d9fb6465802c2279ea14cc26eb66d17c133478b1Johannes Berg return "UNKNOWN"; 455d9fb6465802c2279ea14cc26eb66d17c133478b1Johannes Berg return trans_pcie->command_names[cmd]; 456d9fb6465802c2279ea14cc26eb66d17c133478b1Johannes Berg} 457d9fb6465802c2279ea14cc26eb66d17c133478b1Johannes Berg 4588d425517f1f08f01a6171d22e05be62ef6ad93fcEmmanuel Grumbachstatic inline bool iwl_is_rfkill_set(struct iwl_trans *trans) 4598d425517f1f08f01a6171d22e05be62ef6ad93fcEmmanuel Grumbach{ 4608d425517f1f08f01a6171d22e05be62ef6ad93fcEmmanuel Grumbach return !(iwl_read32(trans, CSR_GP_CNTRL) & 4618d425517f1f08f01a6171d22e05be62ef6ad93fcEmmanuel Grumbach CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW); 4628d425517f1f08f01a6171d22e05be62ef6ad93fcEmmanuel Grumbach} 4638d425517f1f08f01a6171d22e05be62ef6ad93fcEmmanuel Grumbach 464b9439491055a18ee075614139abadfd74c1b887fEmmanuel Grumbachstatic inline void __iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, 465b9439491055a18ee075614139abadfd74c1b887fEmmanuel Grumbach u32 reg, u32 mask, u32 value) 466b9439491055a18ee075614139abadfd74c1b887fEmmanuel Grumbach{ 467b9439491055a18ee075614139abadfd74c1b887fEmmanuel Grumbach u32 v; 468b9439491055a18ee075614139abadfd74c1b887fEmmanuel Grumbach 469b9439491055a18ee075614139abadfd74c1b887fEmmanuel Grumbach#ifdef CONFIG_IWLWIFI_DEBUG 470b9439491055a18ee075614139abadfd74c1b887fEmmanuel Grumbach WARN_ON_ONCE(value & ~mask); 471b9439491055a18ee075614139abadfd74c1b887fEmmanuel Grumbach#endif 472b9439491055a18ee075614139abadfd74c1b887fEmmanuel Grumbach 473b9439491055a18ee075614139abadfd74c1b887fEmmanuel Grumbach v = iwl_read32(trans, reg); 474b9439491055a18ee075614139abadfd74c1b887fEmmanuel Grumbach v &= ~mask; 475b9439491055a18ee075614139abadfd74c1b887fEmmanuel Grumbach v |= value; 476b9439491055a18ee075614139abadfd74c1b887fEmmanuel Grumbach iwl_write32(trans, reg, v); 477b9439491055a18ee075614139abadfd74c1b887fEmmanuel Grumbach} 478b9439491055a18ee075614139abadfd74c1b887fEmmanuel Grumbach 479b9439491055a18ee075614139abadfd74c1b887fEmmanuel Grumbachstatic inline void __iwl_trans_pcie_clear_bit(struct iwl_trans *trans, 480b9439491055a18ee075614139abadfd74c1b887fEmmanuel Grumbach u32 reg, u32 mask) 481b9439491055a18ee075614139abadfd74c1b887fEmmanuel Grumbach{ 482b9439491055a18ee075614139abadfd74c1b887fEmmanuel Grumbach __iwl_trans_pcie_set_bits_mask(trans, reg, mask, 0); 483b9439491055a18ee075614139abadfd74c1b887fEmmanuel Grumbach} 484b9439491055a18ee075614139abadfd74c1b887fEmmanuel Grumbach 485b9439491055a18ee075614139abadfd74c1b887fEmmanuel Grumbachstatic inline void __iwl_trans_pcie_set_bit(struct iwl_trans *trans, 486b9439491055a18ee075614139abadfd74c1b887fEmmanuel Grumbach u32 reg, u32 mask) 487b9439491055a18ee075614139abadfd74c1b887fEmmanuel Grumbach{ 488b9439491055a18ee075614139abadfd74c1b887fEmmanuel Grumbach __iwl_trans_pcie_set_bits_mask(trans, reg, mask, mask); 489b9439491055a18ee075614139abadfd74c1b887fEmmanuel Grumbach} 490b9439491055a18ee075614139abadfd74c1b887fEmmanuel Grumbach 491ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach#endif /* __iwl_trans_int_pcie_h__ */ 492