internal.h revision b55e57f53f8740a2d1432e4963372d303b798530
1ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach/****************************************************************************** 2ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * 34e3182626a914443a5e0fbe014813f03e51a75dfWey-Yi Guy * Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved. 4ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * 5ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * Portions of this file are derived from the ipw3945 project, as well 6ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * as portions of the ieee80211 subsystem header files. 7ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * 8ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * This program is free software; you can redistribute it and/or modify it 9ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * under the terms of version 2 of the GNU General Public License as 10ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * published by the Free Software Foundation. 11ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * 12ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * This program is distributed in the hope that it will be useful, but WITHOUT 13ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * more details. 16ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * 17ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * You should have received a copy of the GNU General Public License along with 18ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * this program; if not, write to the Free Software Foundation, Inc., 19ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 20ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * 21ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * The full GNU General Public License is included in this distribution in the 22ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * file called LICENSE. 23ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * 24ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * Contact Information: 25ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * Intel Linux Wireless <ilw@linux.intel.com> 26ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 27ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * 28ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach *****************************************************************************/ 29ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach#ifndef __iwl_trans_int_pcie_h__ 30ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach#define __iwl_trans_int_pcie_h__ 31ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach 32a72b8b088c3465b28192c1a14ba97be8223a8cecEmmanuel Grumbach#include <linux/spinlock.h> 33a72b8b088c3465b28192c1a14ba97be8223a8cecEmmanuel Grumbach#include <linux/interrupt.h> 34a72b8b088c3465b28192c1a14ba97be8223a8cecEmmanuel Grumbach#include <linux/skbuff.h> 3513df1aab4aa3cd99693c0cdeb7177e5359218431Johannes Berg#include <linux/wait.h> 36522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach#include <linux/pci.h> 377c5ba4a830cbb730770129b0004e2a06e47dbac5Johannes Berg#include <linux/timer.h> 38a72b8b088c3465b28192c1a14ba97be8223a8cecEmmanuel Grumbach 39dda61a4482661d71034cc132d1f474f19ce34a4dEmmanuel Grumbach#include "iwl-fh.h" 40a72b8b088c3465b28192c1a14ba97be8223a8cecEmmanuel Grumbach#include "iwl-csr.h" 41a72b8b088c3465b28192c1a14ba97be8223a8cecEmmanuel Grumbach#include "iwl-trans.h" 42a72b8b088c3465b28192c1a14ba97be8223a8cecEmmanuel Grumbach#include "iwl-debug.h" 43a72b8b088c3465b28192c1a14ba97be8223a8cecEmmanuel Grumbach#include "iwl-io.h" 4402e3835884f352ac707dcf14d8bf455c0c0acbc5Emmanuel Grumbach#include "iwl-op-mode.h" 45a72b8b088c3465b28192c1a14ba97be8223a8cecEmmanuel Grumbach 46a72b8b088c3465b28192c1a14ba97be8223a8cecEmmanuel Grumbachstruct iwl_host_cmd; 47dda61a4482661d71034cc132d1f474f19ce34a4dEmmanuel Grumbach 48ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach/*This file includes the declaration that are internal to the 49ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach * trans_pcie layer */ 50ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach 5148a2d66f58d2bf1818acf5ff7ed9897a9977a96eJohannes Bergstruct iwl_rx_mem_buffer { 5248a2d66f58d2bf1818acf5ff7ed9897a9977a96eJohannes Berg dma_addr_t page_dma; 5348a2d66f58d2bf1818acf5ff7ed9897a9977a96eJohannes Berg struct page *page; 5448a2d66f58d2bf1818acf5ff7ed9897a9977a96eJohannes Berg struct list_head list; 5548a2d66f58d2bf1818acf5ff7ed9897a9977a96eJohannes Berg}; 5648a2d66f58d2bf1818acf5ff7ed9897a9977a96eJohannes Berg 57e6bb4c9c00892c488f3218ea317dc6a71674faf4Emmanuel Grumbach/** 581f7b6172db86e9ab2b4cd794441bb2c40ab287fcEmmanuel Grumbach * struct isr_statistics - interrupt statistics 591f7b6172db86e9ab2b4cd794441bb2c40ab287fcEmmanuel Grumbach * 601f7b6172db86e9ab2b4cd794441bb2c40ab287fcEmmanuel Grumbach */ 611f7b6172db86e9ab2b4cd794441bb2c40ab287fcEmmanuel Grumbachstruct isr_statistics { 621f7b6172db86e9ab2b4cd794441bb2c40ab287fcEmmanuel Grumbach u32 hw; 631f7b6172db86e9ab2b4cd794441bb2c40ab287fcEmmanuel Grumbach u32 sw; 641f7b6172db86e9ab2b4cd794441bb2c40ab287fcEmmanuel Grumbach u32 err_code; 651f7b6172db86e9ab2b4cd794441bb2c40ab287fcEmmanuel Grumbach u32 sch; 661f7b6172db86e9ab2b4cd794441bb2c40ab287fcEmmanuel Grumbach u32 alive; 671f7b6172db86e9ab2b4cd794441bb2c40ab287fcEmmanuel Grumbach u32 rfkill; 681f7b6172db86e9ab2b4cd794441bb2c40ab287fcEmmanuel Grumbach u32 ctkill; 691f7b6172db86e9ab2b4cd794441bb2c40ab287fcEmmanuel Grumbach u32 wakeup; 701f7b6172db86e9ab2b4cd794441bb2c40ab287fcEmmanuel Grumbach u32 rx; 711f7b6172db86e9ab2b4cd794441bb2c40ab287fcEmmanuel Grumbach u32 tx; 721f7b6172db86e9ab2b4cd794441bb2c40ab287fcEmmanuel Grumbach u32 unhandled; 731f7b6172db86e9ab2b4cd794441bb2c40ab287fcEmmanuel Grumbach}; 741f7b6172db86e9ab2b4cd794441bb2c40ab287fcEmmanuel Grumbach 751f7b6172db86e9ab2b4cd794441bb2c40ab287fcEmmanuel Grumbach/** 765a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach * struct iwl_rx_queue - Rx queue 775a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach * @bd: driver's pointer to buffer of receive buffer descriptors (rbd) 785a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach * @bd_dma: bus address of buffer of receive buffer descriptors (rbd) 795a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach * @pool: 805a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach * @queue: 815a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach * @read: Shared index to newest available Rx buffer 825a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach * @write: Shared index to oldest written Rx packet 835a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach * @free_count: Number of pre-allocated buffers in rx_free 845a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach * @write_actual: 855a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach * @rx_free: list of free SKBs for use 865a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach * @rx_used: List of Rx buffers with no SKB 875a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach * @need_update: flag to indicate we need to update read/write index 885a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach * @rb_stts: driver's pointer to receive buffer status 895a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach * @rb_stts_dma: bus address of receive buffer status 905a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach * @lock: 915a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach * 925a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers 935a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach */ 945a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbachstruct iwl_rx_queue { 955a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach __le32 *bd; 965a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach dma_addr_t bd_dma; 975a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS]; 985a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE]; 995a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach u32 read; 1005a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach u32 write; 1015a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach u32 free_count; 1025a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach u32 write_actual; 1035a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach struct list_head rx_free; 1045a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach struct list_head rx_used; 1055a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach int need_update; 1065a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach struct iwl_rb_status *rb_stts; 1075a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach dma_addr_t rb_stts_dma; 1085a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach spinlock_t lock; 1095a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach}; 1105a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach 111a72b8b088c3465b28192c1a14ba97be8223a8cecEmmanuel Grumbachstruct iwl_dma_ptr { 112a72b8b088c3465b28192c1a14ba97be8223a8cecEmmanuel Grumbach dma_addr_t dma; 113a72b8b088c3465b28192c1a14ba97be8223a8cecEmmanuel Grumbach void *addr; 114a72b8b088c3465b28192c1a14ba97be8223a8cecEmmanuel Grumbach size_t size; 115a72b8b088c3465b28192c1a14ba97be8223a8cecEmmanuel Grumbach}; 116a72b8b088c3465b28192c1a14ba97be8223a8cecEmmanuel Grumbach 117bffc66ce2210b149fd171eccad2aef9802c0b35dJohannes Berg/** 118bffc66ce2210b149fd171eccad2aef9802c0b35dJohannes Berg * iwl_queue_inc_wrap - increment queue index, wrap back to beginning 119bffc66ce2210b149fd171eccad2aef9802c0b35dJohannes Berg * @index -- current index 120bffc66ce2210b149fd171eccad2aef9802c0b35dJohannes Berg * @n_bd -- total number of entries in queue (must be power of 2) 121bffc66ce2210b149fd171eccad2aef9802c0b35dJohannes Berg */ 122bffc66ce2210b149fd171eccad2aef9802c0b35dJohannes Bergstatic inline int iwl_queue_inc_wrap(int index, int n_bd) 123bffc66ce2210b149fd171eccad2aef9802c0b35dJohannes Berg{ 124bffc66ce2210b149fd171eccad2aef9802c0b35dJohannes Berg return ++index & (n_bd - 1); 125bffc66ce2210b149fd171eccad2aef9802c0b35dJohannes Berg} 126bffc66ce2210b149fd171eccad2aef9802c0b35dJohannes Berg 127bffc66ce2210b149fd171eccad2aef9802c0b35dJohannes Berg/** 128bffc66ce2210b149fd171eccad2aef9802c0b35dJohannes Berg * iwl_queue_dec_wrap - decrement queue index, wrap back to end 129bffc66ce2210b149fd171eccad2aef9802c0b35dJohannes Berg * @index -- current index 130bffc66ce2210b149fd171eccad2aef9802c0b35dJohannes Berg * @n_bd -- total number of entries in queue (must be power of 2) 131bffc66ce2210b149fd171eccad2aef9802c0b35dJohannes Berg */ 132bffc66ce2210b149fd171eccad2aef9802c0b35dJohannes Bergstatic inline int iwl_queue_dec_wrap(int index, int n_bd) 133bffc66ce2210b149fd171eccad2aef9802c0b35dJohannes Berg{ 134bffc66ce2210b149fd171eccad2aef9802c0b35dJohannes Berg return --index & (n_bd - 1); 135bffc66ce2210b149fd171eccad2aef9802c0b35dJohannes Berg} 136bffc66ce2210b149fd171eccad2aef9802c0b35dJohannes Berg 137522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbachstruct iwl_cmd_meta { 138522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach /* only for SYNC commands, iff the reply skb is wanted */ 139522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach struct iwl_host_cmd *source; 140522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach 141522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach DEFINE_DMA_UNMAP_ADDR(mapping); 142522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach DEFINE_DMA_UNMAP_LEN(len); 143c14c73728b8feb01d9142f9241bf14601cfb86f7Johannes Berg 144c14c73728b8feb01d9142f9241bf14601cfb86f7Johannes Berg u32 flags; 145522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach}; 146522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach 147522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach/* 148522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * Generic queue structure 149522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * 150522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * Contains common data for Rx and Tx queues. 151522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * 152522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * Note the difference between n_bd and n_window: the hardware 153522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * always assumes 256 descriptors, so n_bd is always 256 (unless 154522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * there might be HW changes in the future). For the normal TX 155522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * queues, n_window, which is the size of the software queue data 156522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * is also 256; however, for the command queue, n_window is only 157522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * 32 since we don't need so many commands pending. Since the HW 158522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * still uses 256 BDs for DMA though, n_bd stays 256. As a result, 159522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * the software buffers (in the variables @meta, @txb in struct 160522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * iwl_tx_queue) only have 32 entries, while the HW buffers (@tfds 161522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * in the same struct) have 256. 162522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * This means that we end up with the following: 163522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * HW entries: | 0 | ... | N * 32 | ... | N * 32 + 31 | ... | 255 | 164522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * SW entries: | 0 | ... | 31 | 165522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * where N is a number between 0 and 7. This means that the SW 166522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * data is a window overlayed over the HW queue. 167522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach */ 168522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbachstruct iwl_queue { 169522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach int n_bd; /* number of BDs in this queue */ 170522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach int write_ptr; /* 1-st empty entry (index) host_w*/ 171522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach int read_ptr; /* last used entry (index) host_r*/ 172522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach /* use for monitoring and recovering the stuck queue */ 173522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach dma_addr_t dma_addr; /* physical addr for BD's */ 174522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach int n_window; /* safe queue window */ 175522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach u32 id; 176522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach int low_mark; /* low watermark, resume queue if free 177522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * space more than this */ 178522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach int high_mark; /* high watermark, stop queue if free 179522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * space less than this */ 180522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach}; 181522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach 182bf8440e6a6f5fabf7843dbfecb1745e49182fa1cJohannes Berg#define TFD_TX_CMD_SLOTS 256 183bf8440e6a6f5fabf7843dbfecb1745e49182fa1cJohannes Berg#define TFD_CMD_SLOTS 32 184bf8440e6a6f5fabf7843dbfecb1745e49182fa1cJohannes Berg 185bf8440e6a6f5fabf7843dbfecb1745e49182fa1cJohannes Bergstruct iwl_pcie_tx_queue_entry { 186bf8440e6a6f5fabf7843dbfecb1745e49182fa1cJohannes Berg struct iwl_device_cmd *cmd; 1879679142291f51515bd1bf492535e8a12515558e9Emmanuel Grumbach struct iwl_device_cmd *copy_cmd; 188bf8440e6a6f5fabf7843dbfecb1745e49182fa1cJohannes Berg struct sk_buff *skb; 189f4feb8ac6e666d2ca37cf722166bbfadf2c6adf8Johannes Berg /* buffer to free after command completes */ 190f4feb8ac6e666d2ca37cf722166bbfadf2c6adf8Johannes Berg const void *free_buf; 191bf8440e6a6f5fabf7843dbfecb1745e49182fa1cJohannes Berg struct iwl_cmd_meta meta; 192bf8440e6a6f5fabf7843dbfecb1745e49182fa1cJohannes Berg}; 193bf8440e6a6f5fabf7843dbfecb1745e49182fa1cJohannes Berg 194522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach/** 195522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * struct iwl_tx_queue - Tx Queue for DMA 196522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * @q: generic Rx/Tx queue descriptor 197bf8440e6a6f5fabf7843dbfecb1745e49182fa1cJohannes Berg * @tfds: transmit frame descriptors (DMA memory) 198bf8440e6a6f5fabf7843dbfecb1745e49182fa1cJohannes Berg * @entries: transmit entries (driver state) 199bf8440e6a6f5fabf7843dbfecb1745e49182fa1cJohannes Berg * @lock: queue lock 200bf8440e6a6f5fabf7843dbfecb1745e49182fa1cJohannes Berg * @stuck_timer: timer that fires if queue gets stuck 201bf8440e6a6f5fabf7843dbfecb1745e49182fa1cJohannes Berg * @trans_pcie: pointer back to transport (for timer) 202522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * @need_update: indicates need to update read/write index 203bf8440e6a6f5fabf7843dbfecb1745e49182fa1cJohannes Berg * @active: stores if queue is active 204522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * 205522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame 206522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach * descriptors) and required locking structures. 207522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach */ 208522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbachstruct iwl_tx_queue { 209522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach struct iwl_queue q; 210522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach struct iwl_tfd *tfds; 211bf8440e6a6f5fabf7843dbfecb1745e49182fa1cJohannes Berg struct iwl_pcie_tx_queue_entry *entries; 212015c15e1067c988fc87fb550b222f075c8d3f47cJohannes Berg spinlock_t lock; 2137c5ba4a830cbb730770129b0004e2a06e47dbac5Johannes Berg struct timer_list stuck_timer; 2147c5ba4a830cbb730770129b0004e2a06e47dbac5Johannes Berg struct iwl_trans_pcie *trans_pcie; 215522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach u8 need_update; 216522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach u8 active; 217522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach}; 218522376d206da66cecc90929134ad70c0446e874bEmmanuel Grumbach 2195a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach/** 220e6bb4c9c00892c488f3218ea317dc6a71674faf4Emmanuel Grumbach * struct iwl_trans_pcie - PCIe transport specific data 2215a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach * @rxq: all the RX queue data 2225a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach * @rx_replenish: work that will be called when buffers need to be allocated 2239130bab137844d9ad3db6ab524de299cd2b9e39dEmmanuel Grumbach * @drv - pointer to iwl_drv 2245a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach * @trans: pointer to the generic transport area 2257559553660da6cda3aa798c4e8eb681b63402819Johannes Berg * @irq - the irq number for the device 22657a1dc89097982874f50a0e6f68ab08f62e9e5aaEmmanuel Grumbach * @irq_requested: true when the irq has been requested 227105183b156b7c220b47c3162e087101a0a6abc9fEmmanuel Grumbach * @scd_base_addr: scheduler sram base address in SRAM 228105183b156b7c220b47c3162e087101a0a6abc9fEmmanuel Grumbach * @scd_bc_tbls: pointer to the byte count table of the scheduler 2299d6b2cb1ccf9c1e00a0891eff78b93eb1a1fc372Emmanuel Grumbach * @kw: keep warm address 230a42a184458ae95937893cb873c988385637c5e14Emmanuel Grumbach * @pci_dev: basic pci-network driver stuff 231a42a184458ae95937893cb873c988385637c5e14Emmanuel Grumbach * @hw_base: pci hardware address support 23213df1aab4aa3cd99693c0cdeb7177e5359218431Johannes Berg * @ucode_write_complete: indicates that the ucode has been copied. 23313df1aab4aa3cd99693c0cdeb7177e5359218431Johannes Berg * @ucode_write_waitq: wait queue for uCode load 2349a716863ae4a2f039bc4d0b2b2bb4b24a1dc7a91Don Fry * @status - transport specific status flags 235c6f600fcfe8a7e4f594fc4c80b2c7b66f248958bMeenakshi Venkataraman * @cmd_queue - command queue number 236b2cf410ccb927141e69aa610b6dcf5137701f3afJohannes Berg * @rx_buf_size_8k: 8 kB RX buffer size 237b2cf410ccb927141e69aa610b6dcf5137701f3afJohannes Berg * @rx_page_order: page order for receive buffer size 2387c5ba4a830cbb730770129b0004e2a06e47dbac5Johannes Berg * @wd_timeout: queue watchdog timeout (jiffies) 239e6bb4c9c00892c488f3218ea317dc6a71674faf4Emmanuel Grumbach */ 240e6bb4c9c00892c488f3218ea317dc6a71674faf4Emmanuel Grumbachstruct iwl_trans_pcie { 2415a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach struct iwl_rx_queue rxq; 2425a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach struct work_struct rx_replenish; 2435a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach struct iwl_trans *trans; 2449130bab137844d9ad3db6ab524de299cd2b9e39dEmmanuel Grumbach struct iwl_drv *drv; 2450c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach 2460c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach /* INT ICT Table */ 2470c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach __le32 *ict_tbl; 2480c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach dma_addr_t ict_tbl_dma; 2490c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach int ict_index; 2500c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach u32 inta; 2510c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach bool use_ict; 25257a1dc89097982874f50a0e6f68ab08f62e9e5aaEmmanuel Grumbach bool irq_requested; 2530c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach struct tasklet_struct irq_tasklet; 2541f7b6172db86e9ab2b4cd794441bb2c40ab287fcEmmanuel Grumbach struct isr_statistics isr_stats; 2550c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach 2567559553660da6cda3aa798c4e8eb681b63402819Johannes Berg unsigned int irq; 2577b11488fbbbe06ada39a396dec16532db8c933e6Johannes Berg spinlock_t irq_lock; 2580c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach u32 inta_mask; 259105183b156b7c220b47c3162e087101a0a6abc9fEmmanuel Grumbach u32 scd_base_addr; 260105183b156b7c220b47c3162e087101a0a6abc9fEmmanuel Grumbach struct iwl_dma_ptr scd_bc_tbls; 2619d6b2cb1ccf9c1e00a0891eff78b93eb1a1fc372Emmanuel Grumbach struct iwl_dma_ptr kw; 262e13c0c59e0ec38558ac853d56555e915b4dc7dc2Emmanuel Grumbach 2638ad71bef4a9d8173cbcfbb2f796b08d33d4ca01bEmmanuel Grumbach struct iwl_tx_queue *txq; 2649eae88fa9a02e31af69a215beaa5e1194da3a5a1Johannes Berg unsigned long queue_used[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)]; 2658ad71bef4a9d8173cbcfbb2f796b08d33d4ca01bEmmanuel Grumbach unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)]; 266a42a184458ae95937893cb873c988385637c5e14Emmanuel Grumbach 267a42a184458ae95937893cb873c988385637c5e14Emmanuel Grumbach /* PCI bus related data */ 268a42a184458ae95937893cb873c988385637c5e14Emmanuel Grumbach struct pci_dev *pci_dev; 269a42a184458ae95937893cb873c988385637c5e14Emmanuel Grumbach void __iomem *hw_base; 27013df1aab4aa3cd99693c0cdeb7177e5359218431Johannes Berg 27113df1aab4aa3cd99693c0cdeb7177e5359218431Johannes Berg bool ucode_write_complete; 27213df1aab4aa3cd99693c0cdeb7177e5359218431Johannes Berg wait_queue_head_t ucode_write_waitq; 273f946b529502399d09471c5d13845fefbfe8555a6Emmanuel Grumbach wait_queue_head_t wait_command_queue; 274f946b529502399d09471c5d13845fefbfe8555a6Emmanuel Grumbach 2759a716863ae4a2f039bc4d0b2b2bb4b24a1dc7a91Don Fry unsigned long status; 276c6f600fcfe8a7e4f594fc4c80b2c7b66f248958bMeenakshi Venkataraman u8 cmd_queue; 277b04db9ac4f7641332e0133b2fd8f82e6e4553947Emmanuel Grumbach u8 cmd_fifo; 278d663ee73f62903aed334eca25832a76c4a7e4c1cJohannes Berg u8 n_no_reclaim_cmds; 279d663ee73f62903aed334eca25832a76c4a7e4c1cJohannes Berg u8 no_reclaim_cmds[MAX_NO_RECLAIM_CMDS]; 280b2cf410ccb927141e69aa610b6dcf5137701f3afJohannes Berg 281b2cf410ccb927141e69aa610b6dcf5137701f3afJohannes Berg bool rx_buf_size_8k; 282b2cf410ccb927141e69aa610b6dcf5137701f3afJohannes Berg u32 rx_page_order; 2837c5ba4a830cbb730770129b0004e2a06e47dbac5Johannes Berg 284d9fb6465802c2279ea14cc26eb66d17c133478b1Johannes Berg const char **command_names; 2857c5ba4a830cbb730770129b0004e2a06e47dbac5Johannes Berg 2867c5ba4a830cbb730770129b0004e2a06e47dbac5Johannes Berg /* queue watchdog */ 2877c5ba4a830cbb730770129b0004e2a06e47dbac5Johannes Berg unsigned long wd_timeout; 288e6bb4c9c00892c488f3218ea317dc6a71674faf4Emmanuel Grumbach}; 289e6bb4c9c00892c488f3218ea317dc6a71674faf4Emmanuel Grumbach 290b55e57f53f8740a2d1432e4963372d303b798530Emmanuel Grumbach/** 291b55e57f53f8740a2d1432e4963372d303b798530Emmanuel Grumbach * enum iwl_pcie_status: status of the PCIe transport 292b55e57f53f8740a2d1432e4963372d303b798530Emmanuel Grumbach * @STATUS_HCMD_ACTIVE: a SYNC command is being processed 293b55e57f53f8740a2d1432e4963372d303b798530Emmanuel Grumbach * @STATUS_DEVICE_ENABLED: APM is enabled 294b55e57f53f8740a2d1432e4963372d303b798530Emmanuel Grumbach * @STATUS_TPOWER_PMI: the device might be asleep (need to wake it up) 295b55e57f53f8740a2d1432e4963372d303b798530Emmanuel Grumbach * @STATUS_INT_ENABLED: interrupts are enabled 296b55e57f53f8740a2d1432e4963372d303b798530Emmanuel Grumbach * @STATUS_RFKILL: the HW RFkill switch is in KILL position 297b55e57f53f8740a2d1432e4963372d303b798530Emmanuel Grumbach * @STATUS_FW_ERROR: the fw is in error state 298b55e57f53f8740a2d1432e4963372d303b798530Emmanuel Grumbach */ 299b55e57f53f8740a2d1432e4963372d303b798530Emmanuel Grumbachenum iwl_pcie_status { 300f946b529502399d09471c5d13845fefbfe8555a6Emmanuel Grumbach STATUS_HCMD_ACTIVE, 301f946b529502399d09471c5d13845fefbfe8555a6Emmanuel Grumbach STATUS_DEVICE_ENABLED, 302f946b529502399d09471c5d13845fefbfe8555a6Emmanuel Grumbach STATUS_TPOWER_PMI, 303f946b529502399d09471c5d13845fefbfe8555a6Emmanuel Grumbach STATUS_INT_ENABLED, 304f946b529502399d09471c5d13845fefbfe8555a6Emmanuel Grumbach STATUS_RFKILL, 305d18aa87fbfe80f33076942d11f19c9d813e835b1Johannes Berg STATUS_FW_ERROR, 306f946b529502399d09471c5d13845fefbfe8555a6Emmanuel Grumbach}; 30701d651d4b7f40c90821e104963dc04800fbde8cfDon Fry 3085a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach#define IWL_TRANS_GET_PCIE_TRANS(_iwl_trans) \ 3095a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach ((struct iwl_trans_pcie *) ((_iwl_trans)->trans_specific)) 3105a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbach 3117c5ba4a830cbb730770129b0004e2a06e47dbac5Johannes Bergstatic inline struct iwl_trans * 3127c5ba4a830cbb730770129b0004e2a06e47dbac5Johannes Bergiwl_trans_pcie_get_trans(struct iwl_trans_pcie *trans_pcie) 3137c5ba4a830cbb730770129b0004e2a06e47dbac5Johannes Berg{ 3147c5ba4a830cbb730770129b0004e2a06e47dbac5Johannes Berg return container_of((void *)trans_pcie, struct iwl_trans, 3157c5ba4a830cbb730770129b0004e2a06e47dbac5Johannes Berg trans_specific); 3167c5ba4a830cbb730770129b0004e2a06e47dbac5Johannes Berg} 3177c5ba4a830cbb730770129b0004e2a06e47dbac5Johannes Berg 318d1ff52536a0d1bd516a628ef43dfaf6fe9c90fe2Johannes Bergstruct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, 319d1ff52536a0d1bd516a628ef43dfaf6fe9c90fe2Johannes Berg const struct pci_device_id *ent, 320d1ff52536a0d1bd516a628ef43dfaf6fe9c90fe2Johannes Berg const struct iwl_cfg *cfg); 321d1ff52536a0d1bd516a628ef43dfaf6fe9c90fe2Johannes Bergvoid iwl_trans_pcie_free(struct iwl_trans *trans); 322d1ff52536a0d1bd516a628ef43dfaf6fe9c90fe2Johannes Berg 323253a634ccd1b291282cd0cade219bd90eb0371ebEmmanuel Grumbach/***************************************************** 324253a634ccd1b291282cd0cade219bd90eb0371ebEmmanuel Grumbach* RX 325253a634ccd1b291282cd0cade219bd90eb0371ebEmmanuel Grumbach******************************************************/ 326ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbachvoid iwl_bg_rx_replenish(struct work_struct *data); 3270c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbachvoid iwl_irq_tasklet(struct iwl_trans *trans); 328358a46d47eefadd5be67495682426bd743ce455cEmmanuel Grumbachvoid iwl_rx_replenish(struct iwl_trans *trans); 3295a878bf60b2bb1f1509f49b8b1784e3c9f204c64Emmanuel Grumbachvoid iwl_rx_queue_update_write_ptr(struct iwl_trans *trans, 33020d3b6475226fbde372b1ce51f26b5379e340759Johannes Berg struct iwl_rx_queue *q); 331ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach 332253a634ccd1b291282cd0cade219bd90eb0371ebEmmanuel Grumbach/***************************************************** 3331a361cd838173879672cb0f0ebe1e7654d7edff6Emmanuel Grumbach* ICT 3341a361cd838173879672cb0f0ebe1e7654d7edff6Emmanuel Grumbach******************************************************/ 335ed6a3803408f18da387463d569b4edc5078fd9aaEmmanuel Grumbachvoid iwl_reset_ict(struct iwl_trans *trans); 3360c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbachvoid iwl_disable_ict(struct iwl_trans *trans); 3370c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbachint iwl_alloc_isr_ict(struct iwl_trans *trans); 3380c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbachvoid iwl_free_isr_ict(struct iwl_trans *trans); 3391a361cd838173879672cb0f0ebe1e7654d7edff6Emmanuel Grumbachirqreturn_t iwl_isr_ict(int irq, void *data); 3401a361cd838173879672cb0f0ebe1e7654d7edff6Emmanuel Grumbach 3411a361cd838173879672cb0f0ebe1e7654d7edff6Emmanuel Grumbach/***************************************************** 342253a634ccd1b291282cd0cade219bd90eb0371ebEmmanuel Grumbach* TX / HCMD 343253a634ccd1b291282cd0cade219bd90eb0371ebEmmanuel Grumbach******************************************************/ 344fd656935cd05f522d7db97386633f6a0d7751218Emmanuel Grumbachvoid iwl_txq_update_write_ptr(struct iwl_trans *trans, 34520d3b6475226fbde372b1ce51f26b5379e340759Johannes Berg struct iwl_tx_queue *txq); 3466d8f6eeb350696050a1f5cf8f9d0daabab68eaf5Emmanuel Grumbachint iwlagn_txq_attach_buf_to_tfd(struct iwl_trans *trans, 347253a634ccd1b291282cd0cade219bd90eb0371ebEmmanuel Grumbach struct iwl_tx_queue *txq, 348253a634ccd1b291282cd0cade219bd90eb0371ebEmmanuel Grumbach dma_addr_t addr, u16 len, u8 reset); 3496d8f6eeb350696050a1f5cf8f9d0daabab68eaf5Emmanuel Grumbachint iwl_queue_init(struct iwl_queue *q, int count, int slots_num, u32 id); 3506d8f6eeb350696050a1f5cf8f9d0daabab68eaf5Emmanuel Grumbachint iwl_trans_pcie_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd); 3513e10caeb55b2693b38f1f80c67c79d918fc42e42Emmanuel Grumbachvoid iwl_tx_cmd_complete(struct iwl_trans *trans, 35248a2d66f58d2bf1818acf5ff7ed9897a9977a96eJohannes Berg struct iwl_rx_cmd_buffer *rxb, int handler_status); 3536d8f6eeb350696050a1f5cf8f9d0daabab68eaf5Emmanuel Grumbachvoid iwl_trans_txq_update_byte_cnt_tbl(struct iwl_trans *trans, 35420d3b6475226fbde372b1ce51f26b5379e340759Johannes Berg struct iwl_tx_queue *txq, 35520d3b6475226fbde372b1ce51f26b5379e340759Johannes Berg u16 byte_cnt); 3564beaf6c2f8af52902bcd55b51f9ff8c8f547d485Emmanuel Grumbachvoid iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, int fifo, 3574beaf6c2f8af52902bcd55b51f9ff8c8f547d485Emmanuel Grumbach int sta_id, int tid, int frame_limit, u16 ssn); 3585bf9a89d9a2eaa136a23d872db4195ca8cada4c8Emmanuel Grumbachvoid iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int queue); 359bc2529c337fe7ea1a37cd5cdc17586f7ef73c4f1Emmanuel Grumbachvoid iwl_txq_free_tfd(struct iwl_trans *trans, struct iwl_tx_queue *txq, 360bc2529c337fe7ea1a37cd5cdc17586f7ef73c4f1Emmanuel Grumbach enum dma_data_direction dma_dir); 361464021ffc1c080283e67729d966d76612728a08cEmmanuel Grumbachint iwl_tx_queue_reclaim(struct iwl_trans *trans, int txq_id, int index, 362464021ffc1c080283e67729d966d76612728a08cEmmanuel Grumbach struct sk_buff_head *skbs); 3636c3fd3f00c67105b49d57525614fcfa6816d604dEmmanuel Grumbachvoid iwl_tx_queue_unmap(struct iwl_trans *trans, int txq_id); 3648ad71bef4a9d8173cbcfbb2f796b08d33d4ca01bEmmanuel Grumbachint iwl_queue_space(const struct iwl_queue *q); 365253a634ccd1b291282cd0cade219bd90eb0371ebEmmanuel Grumbach 3667ff94706a055f3e21710b08ffbe3979d7db615dbEmmanuel Grumbach/***************************************************** 3677ff94706a055f3e21710b08ffbe3979d7db615dbEmmanuel Grumbach* Error handling 3687ff94706a055f3e21710b08ffbe3979d7db615dbEmmanuel Grumbach******************************************************/ 36994543a8d4fb302817014981489f15cb3b92ec3c2Johannes Bergint iwl_dump_fh(struct iwl_trans *trans, char **buf); 37016db88ba51d669ef63c58990771a47208913152cEmmanuel Grumbachvoid iwl_dump_csr(struct iwl_trans *trans); 37116db88ba51d669ef63c58990771a47208913152cEmmanuel Grumbach 3728ad71bef4a9d8173cbcfbb2f796b08d33d4ca01bEmmanuel Grumbach/***************************************************** 3738ad71bef4a9d8173cbcfbb2f796b08d33d4ca01bEmmanuel Grumbach* Helpers 3748ad71bef4a9d8173cbcfbb2f796b08d33d4ca01bEmmanuel Grumbach******************************************************/ 3750c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbachstatic inline void iwl_disable_interrupts(struct iwl_trans *trans) 3760c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach{ 37783626404a70da74c67f32f119e53c0ba032ba2d8Don Fry struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 37883626404a70da74c67f32f119e53c0ba032ba2d8Don Fry clear_bit(STATUS_INT_ENABLED, &trans_pcie->status); 3790c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach 3800c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach /* disable interrupts from uCode/NIC to host */ 3811042db2af183b96cdce5972014d85e8bca0634adEmmanuel Grumbach iwl_write32(trans, CSR_INT_MASK, 0x00000000); 3820c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach 3830c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach /* acknowledge/clear/reset any interrupts still pending 3840c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach * from uCode or flow handler (Rx/Tx DMA) */ 3851042db2af183b96cdce5972014d85e8bca0634adEmmanuel Grumbach iwl_write32(trans, CSR_INT, 0xffffffff); 3861042db2af183b96cdce5972014d85e8bca0634adEmmanuel Grumbach iwl_write32(trans, CSR_FH_INT_STATUS, 0xffffffff); 3870c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach IWL_DEBUG_ISR(trans, "Disabled interrupts\n"); 3880c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach} 3890c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach 3900c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbachstatic inline void iwl_enable_interrupts(struct iwl_trans *trans) 3910c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach{ 39283626404a70da74c67f32f119e53c0ba032ba2d8Don Fry struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3930c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach 3940c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach IWL_DEBUG_ISR(trans, "Enabling interrupts\n"); 39583626404a70da74c67f32f119e53c0ba032ba2d8Don Fry set_bit(STATUS_INT_ENABLED, &trans_pcie->status); 3961042db2af183b96cdce5972014d85e8bca0634adEmmanuel Grumbach iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); 3970c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach} 3980c325769a394559941acda83e888a1d9b1ef8b7fEmmanuel Grumbach 3998722c899a07f45457464803142bd1c2d2a2c3bd8Stanislaw Gruszkastatic inline void iwl_enable_rfkill_int(struct iwl_trans *trans) 4008722c899a07f45457464803142bd1c2d2a2c3bd8Stanislaw Gruszka{ 4018722c899a07f45457464803142bd1c2d2a2c3bd8Stanislaw Gruszka IWL_DEBUG_ISR(trans, "Enabling rfkill interrupt\n"); 4028722c899a07f45457464803142bd1c2d2a2c3bd8Stanislaw Gruszka iwl_write32(trans, CSR_INT_MASK, CSR_INT_BIT_RF_KILL); 4038722c899a07f45457464803142bd1c2d2a2c3bd8Stanislaw Gruszka} 4048722c899a07f45457464803142bd1c2d2a2c3bd8Stanislaw Gruszka 405e20d434170c3a7f388d5e916825499c9c0738606Emmanuel Grumbachstatic inline void iwl_wake_queue(struct iwl_trans *trans, 406bada991b4590122c847520ed2b651b679c16afd3Johannes Berg struct iwl_tx_queue *txq) 407e20d434170c3a7f388d5e916825499c9c0738606Emmanuel Grumbach{ 4089eae88fa9a02e31af69a215beaa5e1194da3a5a1Johannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 4099eae88fa9a02e31af69a215beaa5e1194da3a5a1Johannes Berg 4109eae88fa9a02e31af69a215beaa5e1194da3a5a1Johannes Berg if (test_and_clear_bit(txq->q.id, trans_pcie->queue_stopped)) { 4119eae88fa9a02e31af69a215beaa5e1194da3a5a1Johannes Berg IWL_DEBUG_TX_QUEUES(trans, "Wake hwq %d\n", txq->q.id); 4129eae88fa9a02e31af69a215beaa5e1194da3a5a1Johannes Berg iwl_op_mode_queue_not_full(trans->op_mode, txq->q.id); 41381a3de1ce2929fef2b112c048c50bc52b686f94dEmmanuel Grumbach } 414e20d434170c3a7f388d5e916825499c9c0738606Emmanuel Grumbach} 415e20d434170c3a7f388d5e916825499c9c0738606Emmanuel Grumbach 416e20d434170c3a7f388d5e916825499c9c0738606Emmanuel Grumbachstatic inline void iwl_stop_queue(struct iwl_trans *trans, 417bada991b4590122c847520ed2b651b679c16afd3Johannes Berg struct iwl_tx_queue *txq) 418e20d434170c3a7f388d5e916825499c9c0738606Emmanuel Grumbach{ 4199eae88fa9a02e31af69a215beaa5e1194da3a5a1Johannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 4208ad71bef4a9d8173cbcfbb2f796b08d33d4ca01bEmmanuel Grumbach 4219eae88fa9a02e31af69a215beaa5e1194da3a5a1Johannes Berg if (!test_and_set_bit(txq->q.id, trans_pcie->queue_stopped)) { 4229eae88fa9a02e31af69a215beaa5e1194da3a5a1Johannes Berg iwl_op_mode_queue_full(trans->op_mode, txq->q.id); 4239eae88fa9a02e31af69a215beaa5e1194da3a5a1Johannes Berg IWL_DEBUG_TX_QUEUES(trans, "Stop hwq %d\n", txq->q.id); 4249eae88fa9a02e31af69a215beaa5e1194da3a5a1Johannes Berg } else 4259eae88fa9a02e31af69a215beaa5e1194da3a5a1Johannes Berg IWL_DEBUG_TX_QUEUES(trans, "hwq %d already stopped\n", 4269eae88fa9a02e31af69a215beaa5e1194da3a5a1Johannes Berg txq->q.id); 4278ad71bef4a9d8173cbcfbb2f796b08d33d4ca01bEmmanuel Grumbach} 4288ad71bef4a9d8173cbcfbb2f796b08d33d4ca01bEmmanuel Grumbach 4298ad71bef4a9d8173cbcfbb2f796b08d33d4ca01bEmmanuel Grumbachstatic inline int iwl_queue_used(const struct iwl_queue *q, int i) 4308ad71bef4a9d8173cbcfbb2f796b08d33d4ca01bEmmanuel Grumbach{ 4318ad71bef4a9d8173cbcfbb2f796b08d33d4ca01bEmmanuel Grumbach return q->write_ptr >= q->read_ptr ? 4328ad71bef4a9d8173cbcfbb2f796b08d33d4ca01bEmmanuel Grumbach (i >= q->read_ptr && i < q->write_ptr) : 4338ad71bef4a9d8173cbcfbb2f796b08d33d4ca01bEmmanuel Grumbach !(i < q->read_ptr && i >= q->write_ptr); 4348ad71bef4a9d8173cbcfbb2f796b08d33d4ca01bEmmanuel Grumbach} 4358ad71bef4a9d8173cbcfbb2f796b08d33d4ca01bEmmanuel Grumbach 4368ad71bef4a9d8173cbcfbb2f796b08d33d4ca01bEmmanuel Grumbachstatic inline u8 get_cmd_index(struct iwl_queue *q, u32 index) 4378ad71bef4a9d8173cbcfbb2f796b08d33d4ca01bEmmanuel Grumbach{ 4388ad71bef4a9d8173cbcfbb2f796b08d33d4ca01bEmmanuel Grumbach return index & (q->n_window - 1); 4398ad71bef4a9d8173cbcfbb2f796b08d33d4ca01bEmmanuel Grumbach} 4408ad71bef4a9d8173cbcfbb2f796b08d33d4ca01bEmmanuel Grumbach 441d9fb6465802c2279ea14cc26eb66d17c133478b1Johannes Bergstatic inline const char * 442d9fb6465802c2279ea14cc26eb66d17c133478b1Johannes Bergtrans_pcie_get_cmd_string(struct iwl_trans_pcie *trans_pcie, u8 cmd) 443d9fb6465802c2279ea14cc26eb66d17c133478b1Johannes Berg{ 444d9fb6465802c2279ea14cc26eb66d17c133478b1Johannes Berg if (!trans_pcie->command_names || !trans_pcie->command_names[cmd]) 445d9fb6465802c2279ea14cc26eb66d17c133478b1Johannes Berg return "UNKNOWN"; 446d9fb6465802c2279ea14cc26eb66d17c133478b1Johannes Berg return trans_pcie->command_names[cmd]; 447d9fb6465802c2279ea14cc26eb66d17c133478b1Johannes Berg} 448d9fb6465802c2279ea14cc26eb66d17c133478b1Johannes Berg 4498d425517f1f08f01a6171d22e05be62ef6ad93fcEmmanuel Grumbachstatic inline bool iwl_is_rfkill_set(struct iwl_trans *trans) 4508d425517f1f08f01a6171d22e05be62ef6ad93fcEmmanuel Grumbach{ 4518d425517f1f08f01a6171d22e05be62ef6ad93fcEmmanuel Grumbach return !(iwl_read32(trans, CSR_GP_CNTRL) & 4528d425517f1f08f01a6171d22e05be62ef6ad93fcEmmanuel Grumbach CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW); 4538d425517f1f08f01a6171d22e05be62ef6ad93fcEmmanuel Grumbach} 4548d425517f1f08f01a6171d22e05be62ef6ad93fcEmmanuel Grumbach 455ab697a9f1e73ba817955e15bd899a8a0627f9fd6Emmanuel Grumbach#endif /* __iwl_trans_int_pcie_h__ */ 456