mwl8k.c revision 088aab8b62666a002907c912cd346ae6dc9f42b7
1/* 2 * drivers/net/wireless/mwl8k.c 3 * Driver for Marvell TOPDOG 802.11 Wireless cards 4 * 5 * Copyright (C) 2008-2009 Marvell Semiconductor Inc. 6 * 7 * This file is licensed under the terms of the GNU General Public 8 * License version 2. This program is licensed "as is" without any 9 * warranty of any kind, whether express or implied. 10 */ 11 12#include <linux/init.h> 13#include <linux/module.h> 14#include <linux/kernel.h> 15#include <linux/sched.h> 16#include <linux/spinlock.h> 17#include <linux/list.h> 18#include <linux/pci.h> 19#include <linux/delay.h> 20#include <linux/completion.h> 21#include <linux/etherdevice.h> 22#include <net/mac80211.h> 23#include <linux/moduleparam.h> 24#include <linux/firmware.h> 25#include <linux/workqueue.h> 26 27#define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver" 28#define MWL8K_NAME KBUILD_MODNAME 29#define MWL8K_VERSION "0.11" 30 31/* Register definitions */ 32#define MWL8K_HIU_GEN_PTR 0x00000c10 33#define MWL8K_MODE_STA 0x0000005a 34#define MWL8K_MODE_AP 0x000000a5 35#define MWL8K_HIU_INT_CODE 0x00000c14 36#define MWL8K_FWSTA_READY 0xf0f1f2f4 37#define MWL8K_FWAP_READY 0xf1f2f4a5 38#define MWL8K_INT_CODE_CMD_FINISHED 0x00000005 39#define MWL8K_HIU_SCRATCH 0x00000c40 40 41/* Host->device communications */ 42#define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18 43#define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c 44#define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20 45#define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24 46#define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28 47#define MWL8K_H2A_INT_DUMMY (1 << 20) 48#define MWL8K_H2A_INT_RESET (1 << 15) 49#define MWL8K_H2A_INT_DOORBELL (1 << 1) 50#define MWL8K_H2A_INT_PPA_READY (1 << 0) 51 52/* Device->host communications */ 53#define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c 54#define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30 55#define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34 56#define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38 57#define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c 58#define MWL8K_A2H_INT_DUMMY (1 << 20) 59#define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11) 60#define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10) 61#define MWL8K_A2H_INT_RADAR_DETECT (1 << 7) 62#define MWL8K_A2H_INT_RADIO_ON (1 << 6) 63#define MWL8K_A2H_INT_RADIO_OFF (1 << 5) 64#define MWL8K_A2H_INT_MAC_EVENT (1 << 3) 65#define MWL8K_A2H_INT_OPC_DONE (1 << 2) 66#define MWL8K_A2H_INT_RX_READY (1 << 1) 67#define MWL8K_A2H_INT_TX_DONE (1 << 0) 68 69#define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \ 70 MWL8K_A2H_INT_CHNL_SWITCHED | \ 71 MWL8K_A2H_INT_QUEUE_EMPTY | \ 72 MWL8K_A2H_INT_RADAR_DETECT | \ 73 MWL8K_A2H_INT_RADIO_ON | \ 74 MWL8K_A2H_INT_RADIO_OFF | \ 75 MWL8K_A2H_INT_MAC_EVENT | \ 76 MWL8K_A2H_INT_OPC_DONE | \ 77 MWL8K_A2H_INT_RX_READY | \ 78 MWL8K_A2H_INT_TX_DONE) 79 80#define MWL8K_RX_QUEUES 1 81#define MWL8K_TX_QUEUES 4 82 83struct rxd_ops { 84 int rxd_size; 85 void (*rxd_init)(void *rxd, dma_addr_t next_dma_addr); 86 void (*rxd_refill)(void *rxd, dma_addr_t addr, int len); 87 int (*rxd_process)(void *rxd, struct ieee80211_rx_status *status, 88 __le16 *qos); 89}; 90 91struct mwl8k_device_info { 92 char *part_name; 93 char *helper_image; 94 char *fw_image; 95 struct rxd_ops *ap_rxd_ops; 96}; 97 98struct mwl8k_rx_queue { 99 int rxd_count; 100 101 /* hw receives here */ 102 int head; 103 104 /* refill descs here */ 105 int tail; 106 107 void *rxd; 108 dma_addr_t rxd_dma; 109 struct { 110 struct sk_buff *skb; 111 DECLARE_PCI_UNMAP_ADDR(dma) 112 } *buf; 113}; 114 115struct mwl8k_tx_queue { 116 /* hw transmits here */ 117 int head; 118 119 /* sw appends here */ 120 int tail; 121 122 struct ieee80211_tx_queue_stats stats; 123 struct mwl8k_tx_desc *txd; 124 dma_addr_t txd_dma; 125 struct sk_buff **skb; 126}; 127 128struct mwl8k_priv { 129 struct ieee80211_hw *hw; 130 struct pci_dev *pdev; 131 132 struct mwl8k_device_info *device_info; 133 134 void __iomem *sram; 135 void __iomem *regs; 136 137 /* firmware */ 138 struct firmware *fw_helper; 139 struct firmware *fw_ucode; 140 141 /* hardware/firmware parameters */ 142 bool ap_fw; 143 struct rxd_ops *rxd_ops; 144 145 /* firmware access */ 146 struct mutex fw_mutex; 147 struct task_struct *fw_mutex_owner; 148 int fw_mutex_depth; 149 struct completion *hostcmd_wait; 150 151 /* lock held over TX and TX reap */ 152 spinlock_t tx_lock; 153 154 /* TX quiesce completion, protected by fw_mutex and tx_lock */ 155 struct completion *tx_wait; 156 157 struct ieee80211_vif *vif; 158 159 struct ieee80211_channel *current_channel; 160 161 /* power management status cookie from firmware */ 162 u32 *cookie; 163 dma_addr_t cookie_dma; 164 165 u16 num_mcaddrs; 166 u8 hw_rev; 167 u32 fw_rev; 168 169 /* 170 * Running count of TX packets in flight, to avoid 171 * iterating over the transmit rings each time. 172 */ 173 int pending_tx_pkts; 174 175 struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES]; 176 struct mwl8k_tx_queue txq[MWL8K_TX_QUEUES]; 177 178 /* PHY parameters */ 179 struct ieee80211_supported_band band; 180 struct ieee80211_channel channels[14]; 181 struct ieee80211_rate rates[14]; 182 183 bool radio_on; 184 bool radio_short_preamble; 185 bool sniffer_enabled; 186 bool wmm_enabled; 187 188 struct work_struct sta_notify_worker; 189 spinlock_t sta_notify_list_lock; 190 struct list_head sta_notify_list; 191 192 /* XXX need to convert this to handle multiple interfaces */ 193 bool capture_beacon; 194 u8 capture_bssid[ETH_ALEN]; 195 struct sk_buff *beacon_skb; 196 197 /* 198 * This FJ worker has to be global as it is scheduled from the 199 * RX handler. At this point we don't know which interface it 200 * belongs to until the list of bssids waiting to complete join 201 * is checked. 202 */ 203 struct work_struct finalize_join_worker; 204 205 /* Tasklet to reclaim TX descriptors and buffers after tx */ 206 struct tasklet_struct tx_reclaim_task; 207}; 208 209/* Per interface specific private data */ 210struct mwl8k_vif { 211 /* Non AMPDU sequence number assigned by driver. */ 212 u16 seqno; 213}; 214#define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv)) 215 216struct mwl8k_sta { 217 /* Index into station database. Returned by UPDATE_STADB. */ 218 u8 peer_id; 219}; 220#define MWL8K_STA(_sta) ((struct mwl8k_sta *)&((_sta)->drv_priv)) 221 222static const struct ieee80211_channel mwl8k_channels[] = { 223 { .center_freq = 2412, .hw_value = 1, }, 224 { .center_freq = 2417, .hw_value = 2, }, 225 { .center_freq = 2422, .hw_value = 3, }, 226 { .center_freq = 2427, .hw_value = 4, }, 227 { .center_freq = 2432, .hw_value = 5, }, 228 { .center_freq = 2437, .hw_value = 6, }, 229 { .center_freq = 2442, .hw_value = 7, }, 230 { .center_freq = 2447, .hw_value = 8, }, 231 { .center_freq = 2452, .hw_value = 9, }, 232 { .center_freq = 2457, .hw_value = 10, }, 233 { .center_freq = 2462, .hw_value = 11, }, 234 { .center_freq = 2467, .hw_value = 12, }, 235 { .center_freq = 2472, .hw_value = 13, }, 236 { .center_freq = 2484, .hw_value = 14, }, 237}; 238 239static const struct ieee80211_rate mwl8k_rates[] = { 240 { .bitrate = 10, .hw_value = 2, }, 241 { .bitrate = 20, .hw_value = 4, }, 242 { .bitrate = 55, .hw_value = 11, }, 243 { .bitrate = 110, .hw_value = 22, }, 244 { .bitrate = 220, .hw_value = 44, }, 245 { .bitrate = 60, .hw_value = 12, }, 246 { .bitrate = 90, .hw_value = 18, }, 247 { .bitrate = 120, .hw_value = 24, }, 248 { .bitrate = 180, .hw_value = 36, }, 249 { .bitrate = 240, .hw_value = 48, }, 250 { .bitrate = 360, .hw_value = 72, }, 251 { .bitrate = 480, .hw_value = 96, }, 252 { .bitrate = 540, .hw_value = 108, }, 253 { .bitrate = 720, .hw_value = 144, }, 254}; 255 256/* Set or get info from Firmware */ 257#define MWL8K_CMD_SET 0x0001 258#define MWL8K_CMD_GET 0x0000 259 260/* Firmware command codes */ 261#define MWL8K_CMD_CODE_DNLD 0x0001 262#define MWL8K_CMD_GET_HW_SPEC 0x0003 263#define MWL8K_CMD_SET_HW_SPEC 0x0004 264#define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010 265#define MWL8K_CMD_GET_STAT 0x0014 266#define MWL8K_CMD_RADIO_CONTROL 0x001c 267#define MWL8K_CMD_RF_TX_POWER 0x001e 268#define MWL8K_CMD_RF_ANTENNA 0x0020 269#define MWL8K_CMD_SET_PRE_SCAN 0x0107 270#define MWL8K_CMD_SET_POST_SCAN 0x0108 271#define MWL8K_CMD_SET_RF_CHANNEL 0x010a 272#define MWL8K_CMD_SET_AID 0x010d 273#define MWL8K_CMD_SET_RATE 0x0110 274#define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111 275#define MWL8K_CMD_RTS_THRESHOLD 0x0113 276#define MWL8K_CMD_SET_SLOT 0x0114 277#define MWL8K_CMD_SET_EDCA_PARAMS 0x0115 278#define MWL8K_CMD_SET_WMM_MODE 0x0123 279#define MWL8K_CMD_MIMO_CONFIG 0x0125 280#define MWL8K_CMD_USE_FIXED_RATE 0x0126 281#define MWL8K_CMD_ENABLE_SNIFFER 0x0150 282#define MWL8K_CMD_SET_MAC_ADDR 0x0202 283#define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203 284#define MWL8K_CMD_UPDATE_STADB 0x1123 285 286static const char *mwl8k_cmd_name(u16 cmd, char *buf, int bufsize) 287{ 288#define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\ 289 snprintf(buf, bufsize, "%s", #x);\ 290 return buf;\ 291 } while (0) 292 switch (cmd & ~0x8000) { 293 MWL8K_CMDNAME(CODE_DNLD); 294 MWL8K_CMDNAME(GET_HW_SPEC); 295 MWL8K_CMDNAME(SET_HW_SPEC); 296 MWL8K_CMDNAME(MAC_MULTICAST_ADR); 297 MWL8K_CMDNAME(GET_STAT); 298 MWL8K_CMDNAME(RADIO_CONTROL); 299 MWL8K_CMDNAME(RF_TX_POWER); 300 MWL8K_CMDNAME(RF_ANTENNA); 301 MWL8K_CMDNAME(SET_PRE_SCAN); 302 MWL8K_CMDNAME(SET_POST_SCAN); 303 MWL8K_CMDNAME(SET_RF_CHANNEL); 304 MWL8K_CMDNAME(SET_AID); 305 MWL8K_CMDNAME(SET_RATE); 306 MWL8K_CMDNAME(SET_FINALIZE_JOIN); 307 MWL8K_CMDNAME(RTS_THRESHOLD); 308 MWL8K_CMDNAME(SET_SLOT); 309 MWL8K_CMDNAME(SET_EDCA_PARAMS); 310 MWL8K_CMDNAME(SET_WMM_MODE); 311 MWL8K_CMDNAME(MIMO_CONFIG); 312 MWL8K_CMDNAME(USE_FIXED_RATE); 313 MWL8K_CMDNAME(ENABLE_SNIFFER); 314 MWL8K_CMDNAME(SET_MAC_ADDR); 315 MWL8K_CMDNAME(SET_RATEADAPT_MODE); 316 MWL8K_CMDNAME(UPDATE_STADB); 317 default: 318 snprintf(buf, bufsize, "0x%x", cmd); 319 } 320#undef MWL8K_CMDNAME 321 322 return buf; 323} 324 325/* Hardware and firmware reset */ 326static void mwl8k_hw_reset(struct mwl8k_priv *priv) 327{ 328 iowrite32(MWL8K_H2A_INT_RESET, 329 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); 330 iowrite32(MWL8K_H2A_INT_RESET, 331 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); 332 msleep(20); 333} 334 335/* Release fw image */ 336static void mwl8k_release_fw(struct firmware **fw) 337{ 338 if (*fw == NULL) 339 return; 340 release_firmware(*fw); 341 *fw = NULL; 342} 343 344static void mwl8k_release_firmware(struct mwl8k_priv *priv) 345{ 346 mwl8k_release_fw(&priv->fw_ucode); 347 mwl8k_release_fw(&priv->fw_helper); 348} 349 350/* Request fw image */ 351static int mwl8k_request_fw(struct mwl8k_priv *priv, 352 const char *fname, struct firmware **fw) 353{ 354 /* release current image */ 355 if (*fw != NULL) 356 mwl8k_release_fw(fw); 357 358 return request_firmware((const struct firmware **)fw, 359 fname, &priv->pdev->dev); 360} 361 362static int mwl8k_request_firmware(struct mwl8k_priv *priv) 363{ 364 struct mwl8k_device_info *di = priv->device_info; 365 int rc; 366 367 if (di->helper_image != NULL) { 368 rc = mwl8k_request_fw(priv, di->helper_image, &priv->fw_helper); 369 if (rc) { 370 printk(KERN_ERR "%s: Error requesting helper " 371 "firmware file %s\n", pci_name(priv->pdev), 372 di->helper_image); 373 return rc; 374 } 375 } 376 377 rc = mwl8k_request_fw(priv, di->fw_image, &priv->fw_ucode); 378 if (rc) { 379 printk(KERN_ERR "%s: Error requesting firmware file %s\n", 380 pci_name(priv->pdev), di->fw_image); 381 mwl8k_release_fw(&priv->fw_helper); 382 return rc; 383 } 384 385 return 0; 386} 387 388MODULE_FIRMWARE("mwl8k/helper_8687.fw"); 389MODULE_FIRMWARE("mwl8k/fmimage_8687.fw"); 390 391struct mwl8k_cmd_pkt { 392 __le16 code; 393 __le16 length; 394 __le16 seq_num; 395 __le16 result; 396 char payload[0]; 397} __attribute__((packed)); 398 399/* 400 * Firmware loading. 401 */ 402static int 403mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length) 404{ 405 void __iomem *regs = priv->regs; 406 dma_addr_t dma_addr; 407 int loops; 408 409 dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE); 410 if (pci_dma_mapping_error(priv->pdev, dma_addr)) 411 return -ENOMEM; 412 413 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR); 414 iowrite32(0, regs + MWL8K_HIU_INT_CODE); 415 iowrite32(MWL8K_H2A_INT_DOORBELL, 416 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); 417 iowrite32(MWL8K_H2A_INT_DUMMY, 418 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); 419 420 loops = 1000; 421 do { 422 u32 int_code; 423 424 int_code = ioread32(regs + MWL8K_HIU_INT_CODE); 425 if (int_code == MWL8K_INT_CODE_CMD_FINISHED) { 426 iowrite32(0, regs + MWL8K_HIU_INT_CODE); 427 break; 428 } 429 430 cond_resched(); 431 udelay(1); 432 } while (--loops); 433 434 pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE); 435 436 return loops ? 0 : -ETIMEDOUT; 437} 438 439static int mwl8k_load_fw_image(struct mwl8k_priv *priv, 440 const u8 *data, size_t length) 441{ 442 struct mwl8k_cmd_pkt *cmd; 443 int done; 444 int rc = 0; 445 446 cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL); 447 if (cmd == NULL) 448 return -ENOMEM; 449 450 cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD); 451 cmd->seq_num = 0; 452 cmd->result = 0; 453 454 done = 0; 455 while (length) { 456 int block_size = length > 256 ? 256 : length; 457 458 memcpy(cmd->payload, data + done, block_size); 459 cmd->length = cpu_to_le16(block_size); 460 461 rc = mwl8k_send_fw_load_cmd(priv, cmd, 462 sizeof(*cmd) + block_size); 463 if (rc) 464 break; 465 466 done += block_size; 467 length -= block_size; 468 } 469 470 if (!rc) { 471 cmd->length = 0; 472 rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd)); 473 } 474 475 kfree(cmd); 476 477 return rc; 478} 479 480static int mwl8k_feed_fw_image(struct mwl8k_priv *priv, 481 const u8 *data, size_t length) 482{ 483 unsigned char *buffer; 484 int may_continue, rc = 0; 485 u32 done, prev_block_size; 486 487 buffer = kmalloc(1024, GFP_KERNEL); 488 if (buffer == NULL) 489 return -ENOMEM; 490 491 done = 0; 492 prev_block_size = 0; 493 may_continue = 1000; 494 while (may_continue > 0) { 495 u32 block_size; 496 497 block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH); 498 if (block_size & 1) { 499 block_size &= ~1; 500 may_continue--; 501 } else { 502 done += prev_block_size; 503 length -= prev_block_size; 504 } 505 506 if (block_size > 1024 || block_size > length) { 507 rc = -EOVERFLOW; 508 break; 509 } 510 511 if (length == 0) { 512 rc = 0; 513 break; 514 } 515 516 if (block_size == 0) { 517 rc = -EPROTO; 518 may_continue--; 519 udelay(1); 520 continue; 521 } 522 523 prev_block_size = block_size; 524 memcpy(buffer, data + done, block_size); 525 526 rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size); 527 if (rc) 528 break; 529 } 530 531 if (!rc && length != 0) 532 rc = -EREMOTEIO; 533 534 kfree(buffer); 535 536 return rc; 537} 538 539static int mwl8k_load_firmware(struct ieee80211_hw *hw) 540{ 541 struct mwl8k_priv *priv = hw->priv; 542 struct firmware *fw = priv->fw_ucode; 543 int rc; 544 int loops; 545 546 if (!memcmp(fw->data, "\x01\x00\x00\x00", 4)) { 547 struct firmware *helper = priv->fw_helper; 548 549 if (helper == NULL) { 550 printk(KERN_ERR "%s: helper image needed but none " 551 "given\n", pci_name(priv->pdev)); 552 return -EINVAL; 553 } 554 555 rc = mwl8k_load_fw_image(priv, helper->data, helper->size); 556 if (rc) { 557 printk(KERN_ERR "%s: unable to load firmware " 558 "helper image\n", pci_name(priv->pdev)); 559 return rc; 560 } 561 msleep(5); 562 563 rc = mwl8k_feed_fw_image(priv, fw->data, fw->size); 564 } else { 565 rc = mwl8k_load_fw_image(priv, fw->data, fw->size); 566 } 567 568 if (rc) { 569 printk(KERN_ERR "%s: unable to load firmware image\n", 570 pci_name(priv->pdev)); 571 return rc; 572 } 573 574 iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR); 575 576 loops = 500000; 577 do { 578 u32 ready_code; 579 580 ready_code = ioread32(priv->regs + MWL8K_HIU_INT_CODE); 581 if (ready_code == MWL8K_FWAP_READY) { 582 priv->ap_fw = 1; 583 break; 584 } else if (ready_code == MWL8K_FWSTA_READY) { 585 priv->ap_fw = 0; 586 break; 587 } 588 589 cond_resched(); 590 udelay(1); 591 } while (--loops); 592 593 return loops ? 0 : -ETIMEDOUT; 594} 595 596 597/* DMA header used by firmware and hardware. */ 598struct mwl8k_dma_data { 599 __le16 fwlen; 600 struct ieee80211_hdr wh; 601 char data[0]; 602} __attribute__((packed)); 603 604/* Routines to add/remove DMA header from skb. */ 605static inline void mwl8k_remove_dma_header(struct sk_buff *skb, __le16 qos) 606{ 607 struct mwl8k_dma_data *tr; 608 int hdrlen; 609 610 tr = (struct mwl8k_dma_data *)skb->data; 611 hdrlen = ieee80211_hdrlen(tr->wh.frame_control); 612 613 if (hdrlen != sizeof(tr->wh)) { 614 if (ieee80211_is_data_qos(tr->wh.frame_control)) { 615 memmove(tr->data - hdrlen, &tr->wh, hdrlen - 2); 616 *((__le16 *)(tr->data - 2)) = qos; 617 } else { 618 memmove(tr->data - hdrlen, &tr->wh, hdrlen); 619 } 620 } 621 622 if (hdrlen != sizeof(*tr)) 623 skb_pull(skb, sizeof(*tr) - hdrlen); 624} 625 626static inline void mwl8k_add_dma_header(struct sk_buff *skb) 627{ 628 struct ieee80211_hdr *wh; 629 int hdrlen; 630 struct mwl8k_dma_data *tr; 631 632 /* 633 * Add a firmware DMA header; the firmware requires that we 634 * present a 2-byte payload length followed by a 4-address 635 * header (without QoS field), followed (optionally) by any 636 * WEP/ExtIV header (but only filled in for CCMP). 637 */ 638 wh = (struct ieee80211_hdr *)skb->data; 639 640 hdrlen = ieee80211_hdrlen(wh->frame_control); 641 if (hdrlen != sizeof(*tr)) 642 skb_push(skb, sizeof(*tr) - hdrlen); 643 644 if (ieee80211_is_data_qos(wh->frame_control)) 645 hdrlen -= 2; 646 647 tr = (struct mwl8k_dma_data *)skb->data; 648 if (wh != &tr->wh) 649 memmove(&tr->wh, wh, hdrlen); 650 if (hdrlen != sizeof(tr->wh)) 651 memset(((void *)&tr->wh) + hdrlen, 0, sizeof(tr->wh) - hdrlen); 652 653 /* 654 * Firmware length is the length of the fully formed "802.11 655 * payload". That is, everything except for the 802.11 header. 656 * This includes all crypto material including the MIC. 657 */ 658 tr->fwlen = cpu_to_le16(skb->len - sizeof(*tr)); 659} 660 661 662/* 663 * Packet reception for 88w8366 AP firmware. 664 */ 665struct mwl8k_rxd_8366_ap { 666 __le16 pkt_len; 667 __u8 sq2; 668 __u8 rate; 669 __le32 pkt_phys_addr; 670 __le32 next_rxd_phys_addr; 671 __le16 qos_control; 672 __le16 htsig2; 673 __le32 hw_rssi_info; 674 __le32 hw_noise_floor_info; 675 __u8 noise_floor; 676 __u8 pad0[3]; 677 __u8 rssi; 678 __u8 rx_status; 679 __u8 channel; 680 __u8 rx_ctrl; 681} __attribute__((packed)); 682 683#define MWL8K_8366_AP_RATE_INFO_MCS_FORMAT 0x80 684#define MWL8K_8366_AP_RATE_INFO_40MHZ 0x40 685#define MWL8K_8366_AP_RATE_INFO_RATEID(x) ((x) & 0x3f) 686 687#define MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST 0x80 688 689static void mwl8k_rxd_8366_ap_init(void *_rxd, dma_addr_t next_dma_addr) 690{ 691 struct mwl8k_rxd_8366_ap *rxd = _rxd; 692 693 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr); 694 rxd->rx_ctrl = MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST; 695} 696 697static void mwl8k_rxd_8366_ap_refill(void *_rxd, dma_addr_t addr, int len) 698{ 699 struct mwl8k_rxd_8366_ap *rxd = _rxd; 700 701 rxd->pkt_len = cpu_to_le16(len); 702 rxd->pkt_phys_addr = cpu_to_le32(addr); 703 wmb(); 704 rxd->rx_ctrl = 0; 705} 706 707static int 708mwl8k_rxd_8366_ap_process(void *_rxd, struct ieee80211_rx_status *status, 709 __le16 *qos) 710{ 711 struct mwl8k_rxd_8366_ap *rxd = _rxd; 712 713 if (!(rxd->rx_ctrl & MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST)) 714 return -1; 715 rmb(); 716 717 memset(status, 0, sizeof(*status)); 718 719 status->signal = -rxd->rssi; 720 status->noise = -rxd->noise_floor; 721 722 if (rxd->rate & MWL8K_8366_AP_RATE_INFO_MCS_FORMAT) { 723 status->flag |= RX_FLAG_HT; 724 if (rxd->rate & MWL8K_8366_AP_RATE_INFO_40MHZ) 725 status->flag |= RX_FLAG_40MHZ; 726 status->rate_idx = MWL8K_8366_AP_RATE_INFO_RATEID(rxd->rate); 727 } else { 728 int i; 729 730 for (i = 0; i < ARRAY_SIZE(mwl8k_rates); i++) { 731 if (mwl8k_rates[i].hw_value == rxd->rate) { 732 status->rate_idx = i; 733 break; 734 } 735 } 736 } 737 738 status->band = IEEE80211_BAND_2GHZ; 739 status->freq = ieee80211_channel_to_frequency(rxd->channel); 740 741 *qos = rxd->qos_control; 742 743 return le16_to_cpu(rxd->pkt_len); 744} 745 746static struct rxd_ops rxd_8366_ap_ops = { 747 .rxd_size = sizeof(struct mwl8k_rxd_8366_ap), 748 .rxd_init = mwl8k_rxd_8366_ap_init, 749 .rxd_refill = mwl8k_rxd_8366_ap_refill, 750 .rxd_process = mwl8k_rxd_8366_ap_process, 751}; 752 753/* 754 * Packet reception for STA firmware. 755 */ 756struct mwl8k_rxd_sta { 757 __le16 pkt_len; 758 __u8 link_quality; 759 __u8 noise_level; 760 __le32 pkt_phys_addr; 761 __le32 next_rxd_phys_addr; 762 __le16 qos_control; 763 __le16 rate_info; 764 __le32 pad0[4]; 765 __u8 rssi; 766 __u8 channel; 767 __le16 pad1; 768 __u8 rx_ctrl; 769 __u8 rx_status; 770 __u8 pad2[2]; 771} __attribute__((packed)); 772 773#define MWL8K_STA_RATE_INFO_SHORTPRE 0x8000 774#define MWL8K_STA_RATE_INFO_ANTSELECT(x) (((x) >> 11) & 0x3) 775#define MWL8K_STA_RATE_INFO_RATEID(x) (((x) >> 3) & 0x3f) 776#define MWL8K_STA_RATE_INFO_40MHZ 0x0004 777#define MWL8K_STA_RATE_INFO_SHORTGI 0x0002 778#define MWL8K_STA_RATE_INFO_MCS_FORMAT 0x0001 779 780#define MWL8K_STA_RX_CTRL_OWNED_BY_HOST 0x02 781 782static void mwl8k_rxd_sta_init(void *_rxd, dma_addr_t next_dma_addr) 783{ 784 struct mwl8k_rxd_sta *rxd = _rxd; 785 786 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr); 787 rxd->rx_ctrl = MWL8K_STA_RX_CTRL_OWNED_BY_HOST; 788} 789 790static void mwl8k_rxd_sta_refill(void *_rxd, dma_addr_t addr, int len) 791{ 792 struct mwl8k_rxd_sta *rxd = _rxd; 793 794 rxd->pkt_len = cpu_to_le16(len); 795 rxd->pkt_phys_addr = cpu_to_le32(addr); 796 wmb(); 797 rxd->rx_ctrl = 0; 798} 799 800static int 801mwl8k_rxd_sta_process(void *_rxd, struct ieee80211_rx_status *status, 802 __le16 *qos) 803{ 804 struct mwl8k_rxd_sta *rxd = _rxd; 805 u16 rate_info; 806 807 if (!(rxd->rx_ctrl & MWL8K_STA_RX_CTRL_OWNED_BY_HOST)) 808 return -1; 809 rmb(); 810 811 rate_info = le16_to_cpu(rxd->rate_info); 812 813 memset(status, 0, sizeof(*status)); 814 815 status->signal = -rxd->rssi; 816 status->noise = -rxd->noise_level; 817 status->antenna = MWL8K_STA_RATE_INFO_ANTSELECT(rate_info); 818 status->rate_idx = MWL8K_STA_RATE_INFO_RATEID(rate_info); 819 820 if (rate_info & MWL8K_STA_RATE_INFO_SHORTPRE) 821 status->flag |= RX_FLAG_SHORTPRE; 822 if (rate_info & MWL8K_STA_RATE_INFO_40MHZ) 823 status->flag |= RX_FLAG_40MHZ; 824 if (rate_info & MWL8K_STA_RATE_INFO_SHORTGI) 825 status->flag |= RX_FLAG_SHORT_GI; 826 if (rate_info & MWL8K_STA_RATE_INFO_MCS_FORMAT) 827 status->flag |= RX_FLAG_HT; 828 829 status->band = IEEE80211_BAND_2GHZ; 830 status->freq = ieee80211_channel_to_frequency(rxd->channel); 831 832 *qos = rxd->qos_control; 833 834 return le16_to_cpu(rxd->pkt_len); 835} 836 837static struct rxd_ops rxd_sta_ops = { 838 .rxd_size = sizeof(struct mwl8k_rxd_sta), 839 .rxd_init = mwl8k_rxd_sta_init, 840 .rxd_refill = mwl8k_rxd_sta_refill, 841 .rxd_process = mwl8k_rxd_sta_process, 842}; 843 844 845#define MWL8K_RX_DESCS 256 846#define MWL8K_RX_MAXSZ 3800 847 848static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index) 849{ 850 struct mwl8k_priv *priv = hw->priv; 851 struct mwl8k_rx_queue *rxq = priv->rxq + index; 852 int size; 853 int i; 854 855 rxq->rxd_count = 0; 856 rxq->head = 0; 857 rxq->tail = 0; 858 859 size = MWL8K_RX_DESCS * priv->rxd_ops->rxd_size; 860 861 rxq->rxd = pci_alloc_consistent(priv->pdev, size, &rxq->rxd_dma); 862 if (rxq->rxd == NULL) { 863 printk(KERN_ERR "%s: failed to alloc RX descriptors\n", 864 wiphy_name(hw->wiphy)); 865 return -ENOMEM; 866 } 867 memset(rxq->rxd, 0, size); 868 869 rxq->buf = kmalloc(MWL8K_RX_DESCS * sizeof(*rxq->buf), GFP_KERNEL); 870 if (rxq->buf == NULL) { 871 printk(KERN_ERR "%s: failed to alloc RX skbuff list\n", 872 wiphy_name(hw->wiphy)); 873 pci_free_consistent(priv->pdev, size, rxq->rxd, rxq->rxd_dma); 874 return -ENOMEM; 875 } 876 memset(rxq->buf, 0, MWL8K_RX_DESCS * sizeof(*rxq->buf)); 877 878 for (i = 0; i < MWL8K_RX_DESCS; i++) { 879 int desc_size; 880 void *rxd; 881 int nexti; 882 dma_addr_t next_dma_addr; 883 884 desc_size = priv->rxd_ops->rxd_size; 885 rxd = rxq->rxd + (i * priv->rxd_ops->rxd_size); 886 887 nexti = i + 1; 888 if (nexti == MWL8K_RX_DESCS) 889 nexti = 0; 890 next_dma_addr = rxq->rxd_dma + (nexti * desc_size); 891 892 priv->rxd_ops->rxd_init(rxd, next_dma_addr); 893 } 894 895 return 0; 896} 897 898static int rxq_refill(struct ieee80211_hw *hw, int index, int limit) 899{ 900 struct mwl8k_priv *priv = hw->priv; 901 struct mwl8k_rx_queue *rxq = priv->rxq + index; 902 int refilled; 903 904 refilled = 0; 905 while (rxq->rxd_count < MWL8K_RX_DESCS && limit--) { 906 struct sk_buff *skb; 907 dma_addr_t addr; 908 int rx; 909 void *rxd; 910 911 skb = dev_alloc_skb(MWL8K_RX_MAXSZ); 912 if (skb == NULL) 913 break; 914 915 addr = pci_map_single(priv->pdev, skb->data, 916 MWL8K_RX_MAXSZ, DMA_FROM_DEVICE); 917 918 rxq->rxd_count++; 919 rx = rxq->tail++; 920 if (rxq->tail == MWL8K_RX_DESCS) 921 rxq->tail = 0; 922 rxq->buf[rx].skb = skb; 923 pci_unmap_addr_set(&rxq->buf[rx], dma, addr); 924 925 rxd = rxq->rxd + (rx * priv->rxd_ops->rxd_size); 926 priv->rxd_ops->rxd_refill(rxd, addr, MWL8K_RX_MAXSZ); 927 928 refilled++; 929 } 930 931 return refilled; 932} 933 934/* Must be called only when the card's reception is completely halted */ 935static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index) 936{ 937 struct mwl8k_priv *priv = hw->priv; 938 struct mwl8k_rx_queue *rxq = priv->rxq + index; 939 int i; 940 941 for (i = 0; i < MWL8K_RX_DESCS; i++) { 942 if (rxq->buf[i].skb != NULL) { 943 pci_unmap_single(priv->pdev, 944 pci_unmap_addr(&rxq->buf[i], dma), 945 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE); 946 pci_unmap_addr_set(&rxq->buf[i], dma, 0); 947 948 kfree_skb(rxq->buf[i].skb); 949 rxq->buf[i].skb = NULL; 950 } 951 } 952 953 kfree(rxq->buf); 954 rxq->buf = NULL; 955 956 pci_free_consistent(priv->pdev, 957 MWL8K_RX_DESCS * priv->rxd_ops->rxd_size, 958 rxq->rxd, rxq->rxd_dma); 959 rxq->rxd = NULL; 960} 961 962 963/* 964 * Scan a list of BSSIDs to process for finalize join. 965 * Allows for extension to process multiple BSSIDs. 966 */ 967static inline int 968mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh) 969{ 970 return priv->capture_beacon && 971 ieee80211_is_beacon(wh->frame_control) && 972 !compare_ether_addr(wh->addr3, priv->capture_bssid); 973} 974 975static inline void mwl8k_save_beacon(struct ieee80211_hw *hw, 976 struct sk_buff *skb) 977{ 978 struct mwl8k_priv *priv = hw->priv; 979 980 priv->capture_beacon = false; 981 memset(priv->capture_bssid, 0, ETH_ALEN); 982 983 /* 984 * Use GFP_ATOMIC as rxq_process is called from 985 * the primary interrupt handler, memory allocation call 986 * must not sleep. 987 */ 988 priv->beacon_skb = skb_copy(skb, GFP_ATOMIC); 989 if (priv->beacon_skb != NULL) 990 ieee80211_queue_work(hw, &priv->finalize_join_worker); 991} 992 993static int rxq_process(struct ieee80211_hw *hw, int index, int limit) 994{ 995 struct mwl8k_priv *priv = hw->priv; 996 struct mwl8k_rx_queue *rxq = priv->rxq + index; 997 int processed; 998 999 processed = 0; 1000 while (rxq->rxd_count && limit--) { 1001 struct sk_buff *skb; 1002 void *rxd; 1003 int pkt_len; 1004 struct ieee80211_rx_status status; 1005 __le16 qos; 1006 1007 skb = rxq->buf[rxq->head].skb; 1008 if (skb == NULL) 1009 break; 1010 1011 rxd = rxq->rxd + (rxq->head * priv->rxd_ops->rxd_size); 1012 1013 pkt_len = priv->rxd_ops->rxd_process(rxd, &status, &qos); 1014 if (pkt_len < 0) 1015 break; 1016 1017 rxq->buf[rxq->head].skb = NULL; 1018 1019 pci_unmap_single(priv->pdev, 1020 pci_unmap_addr(&rxq->buf[rxq->head], dma), 1021 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE); 1022 pci_unmap_addr_set(&rxq->buf[rxq->head], dma, 0); 1023 1024 rxq->head++; 1025 if (rxq->head == MWL8K_RX_DESCS) 1026 rxq->head = 0; 1027 1028 rxq->rxd_count--; 1029 1030 skb_put(skb, pkt_len); 1031 mwl8k_remove_dma_header(skb, qos); 1032 1033 /* 1034 * Check for a pending join operation. Save a 1035 * copy of the beacon and schedule a tasklet to 1036 * send a FINALIZE_JOIN command to the firmware. 1037 */ 1038 if (mwl8k_capture_bssid(priv, (void *)skb->data)) 1039 mwl8k_save_beacon(hw, skb); 1040 1041 memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status)); 1042 ieee80211_rx_irqsafe(hw, skb); 1043 1044 processed++; 1045 } 1046 1047 return processed; 1048} 1049 1050 1051/* 1052 * Packet transmission. 1053 */ 1054 1055#define MWL8K_TXD_STATUS_OK 0x00000001 1056#define MWL8K_TXD_STATUS_OK_RETRY 0x00000002 1057#define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004 1058#define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008 1059#define MWL8K_TXD_STATUS_FW_OWNED 0x80000000 1060 1061#define MWL8K_QOS_QLEN_UNSPEC 0xff00 1062#define MWL8K_QOS_ACK_POLICY_MASK 0x0060 1063#define MWL8K_QOS_ACK_POLICY_NORMAL 0x0000 1064#define MWL8K_QOS_ACK_POLICY_BLOCKACK 0x0060 1065#define MWL8K_QOS_EOSP 0x0010 1066 1067struct mwl8k_tx_desc { 1068 __le32 status; 1069 __u8 data_rate; 1070 __u8 tx_priority; 1071 __le16 qos_control; 1072 __le32 pkt_phys_addr; 1073 __le16 pkt_len; 1074 __u8 dest_MAC_addr[ETH_ALEN]; 1075 __le32 next_txd_phys_addr; 1076 __le32 reserved; 1077 __le16 rate_info; 1078 __u8 peer_id; 1079 __u8 tx_frag_cnt; 1080} __attribute__((packed)); 1081 1082#define MWL8K_TX_DESCS 128 1083 1084static int mwl8k_txq_init(struct ieee80211_hw *hw, int index) 1085{ 1086 struct mwl8k_priv *priv = hw->priv; 1087 struct mwl8k_tx_queue *txq = priv->txq + index; 1088 int size; 1089 int i; 1090 1091 memset(&txq->stats, 0, sizeof(struct ieee80211_tx_queue_stats)); 1092 txq->stats.limit = MWL8K_TX_DESCS; 1093 txq->head = 0; 1094 txq->tail = 0; 1095 1096 size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc); 1097 1098 txq->txd = pci_alloc_consistent(priv->pdev, size, &txq->txd_dma); 1099 if (txq->txd == NULL) { 1100 printk(KERN_ERR "%s: failed to alloc TX descriptors\n", 1101 wiphy_name(hw->wiphy)); 1102 return -ENOMEM; 1103 } 1104 memset(txq->txd, 0, size); 1105 1106 txq->skb = kmalloc(MWL8K_TX_DESCS * sizeof(*txq->skb), GFP_KERNEL); 1107 if (txq->skb == NULL) { 1108 printk(KERN_ERR "%s: failed to alloc TX skbuff list\n", 1109 wiphy_name(hw->wiphy)); 1110 pci_free_consistent(priv->pdev, size, txq->txd, txq->txd_dma); 1111 return -ENOMEM; 1112 } 1113 memset(txq->skb, 0, MWL8K_TX_DESCS * sizeof(*txq->skb)); 1114 1115 for (i = 0; i < MWL8K_TX_DESCS; i++) { 1116 struct mwl8k_tx_desc *tx_desc; 1117 int nexti; 1118 1119 tx_desc = txq->txd + i; 1120 nexti = (i + 1) % MWL8K_TX_DESCS; 1121 1122 tx_desc->status = 0; 1123 tx_desc->next_txd_phys_addr = 1124 cpu_to_le32(txq->txd_dma + nexti * sizeof(*tx_desc)); 1125 } 1126 1127 return 0; 1128} 1129 1130static inline void mwl8k_tx_start(struct mwl8k_priv *priv) 1131{ 1132 iowrite32(MWL8K_H2A_INT_PPA_READY, 1133 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); 1134 iowrite32(MWL8K_H2A_INT_DUMMY, 1135 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); 1136 ioread32(priv->regs + MWL8K_HIU_INT_CODE); 1137} 1138 1139static void mwl8k_dump_tx_rings(struct ieee80211_hw *hw) 1140{ 1141 struct mwl8k_priv *priv = hw->priv; 1142 int i; 1143 1144 for (i = 0; i < MWL8K_TX_QUEUES; i++) { 1145 struct mwl8k_tx_queue *txq = priv->txq + i; 1146 int fw_owned = 0; 1147 int drv_owned = 0; 1148 int unused = 0; 1149 int desc; 1150 1151 for (desc = 0; desc < MWL8K_TX_DESCS; desc++) { 1152 struct mwl8k_tx_desc *tx_desc = txq->txd + desc; 1153 u32 status; 1154 1155 status = le32_to_cpu(tx_desc->status); 1156 if (status & MWL8K_TXD_STATUS_FW_OWNED) 1157 fw_owned++; 1158 else 1159 drv_owned++; 1160 1161 if (tx_desc->pkt_len == 0) 1162 unused++; 1163 } 1164 1165 printk(KERN_ERR "%s: txq[%d] len=%d head=%d tail=%d " 1166 "fw_owned=%d drv_owned=%d unused=%d\n", 1167 wiphy_name(hw->wiphy), i, 1168 txq->stats.len, txq->head, txq->tail, 1169 fw_owned, drv_owned, unused); 1170 } 1171} 1172 1173/* 1174 * Must be called with priv->fw_mutex held and tx queues stopped. 1175 */ 1176#define MWL8K_TX_WAIT_TIMEOUT_MS 5000 1177 1178static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw) 1179{ 1180 struct mwl8k_priv *priv = hw->priv; 1181 DECLARE_COMPLETION_ONSTACK(tx_wait); 1182 int retry; 1183 int rc; 1184 1185 might_sleep(); 1186 1187 /* 1188 * The TX queues are stopped at this point, so this test 1189 * doesn't need to take ->tx_lock. 1190 */ 1191 if (!priv->pending_tx_pkts) 1192 return 0; 1193 1194 retry = 0; 1195 rc = 0; 1196 1197 spin_lock_bh(&priv->tx_lock); 1198 priv->tx_wait = &tx_wait; 1199 while (!rc) { 1200 int oldcount; 1201 unsigned long timeout; 1202 1203 oldcount = priv->pending_tx_pkts; 1204 1205 spin_unlock_bh(&priv->tx_lock); 1206 timeout = wait_for_completion_timeout(&tx_wait, 1207 msecs_to_jiffies(MWL8K_TX_WAIT_TIMEOUT_MS)); 1208 spin_lock_bh(&priv->tx_lock); 1209 1210 if (timeout) { 1211 WARN_ON(priv->pending_tx_pkts); 1212 if (retry) { 1213 printk(KERN_NOTICE "%s: tx rings drained\n", 1214 wiphy_name(hw->wiphy)); 1215 } 1216 break; 1217 } 1218 1219 if (priv->pending_tx_pkts < oldcount) { 1220 printk(KERN_NOTICE "%s: waiting for tx rings " 1221 "to drain (%d -> %d pkts)\n", 1222 wiphy_name(hw->wiphy), oldcount, 1223 priv->pending_tx_pkts); 1224 retry = 1; 1225 continue; 1226 } 1227 1228 priv->tx_wait = NULL; 1229 1230 printk(KERN_ERR "%s: tx rings stuck for %d ms\n", 1231 wiphy_name(hw->wiphy), MWL8K_TX_WAIT_TIMEOUT_MS); 1232 mwl8k_dump_tx_rings(hw); 1233 1234 rc = -ETIMEDOUT; 1235 } 1236 spin_unlock_bh(&priv->tx_lock); 1237 1238 return rc; 1239} 1240 1241#define MWL8K_TXD_SUCCESS(status) \ 1242 ((status) & (MWL8K_TXD_STATUS_OK | \ 1243 MWL8K_TXD_STATUS_OK_RETRY | \ 1244 MWL8K_TXD_STATUS_OK_MORE_RETRY)) 1245 1246static void mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int force) 1247{ 1248 struct mwl8k_priv *priv = hw->priv; 1249 struct mwl8k_tx_queue *txq = priv->txq + index; 1250 int wake = 0; 1251 1252 while (txq->stats.len > 0) { 1253 int tx; 1254 struct mwl8k_tx_desc *tx_desc; 1255 unsigned long addr; 1256 int size; 1257 struct sk_buff *skb; 1258 struct ieee80211_tx_info *info; 1259 u32 status; 1260 1261 tx = txq->head; 1262 tx_desc = txq->txd + tx; 1263 1264 status = le32_to_cpu(tx_desc->status); 1265 1266 if (status & MWL8K_TXD_STATUS_FW_OWNED) { 1267 if (!force) 1268 break; 1269 tx_desc->status &= 1270 ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED); 1271 } 1272 1273 txq->head = (tx + 1) % MWL8K_TX_DESCS; 1274 BUG_ON(txq->stats.len == 0); 1275 txq->stats.len--; 1276 priv->pending_tx_pkts--; 1277 1278 addr = le32_to_cpu(tx_desc->pkt_phys_addr); 1279 size = le16_to_cpu(tx_desc->pkt_len); 1280 skb = txq->skb[tx]; 1281 txq->skb[tx] = NULL; 1282 1283 BUG_ON(skb == NULL); 1284 pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE); 1285 1286 mwl8k_remove_dma_header(skb, tx_desc->qos_control); 1287 1288 /* Mark descriptor as unused */ 1289 tx_desc->pkt_phys_addr = 0; 1290 tx_desc->pkt_len = 0; 1291 1292 info = IEEE80211_SKB_CB(skb); 1293 ieee80211_tx_info_clear_status(info); 1294 if (MWL8K_TXD_SUCCESS(status)) 1295 info->flags |= IEEE80211_TX_STAT_ACK; 1296 1297 ieee80211_tx_status_irqsafe(hw, skb); 1298 1299 wake = 1; 1300 } 1301 1302 if (wake && priv->radio_on && !mutex_is_locked(&priv->fw_mutex)) 1303 ieee80211_wake_queue(hw, index); 1304} 1305 1306/* must be called only when the card's transmit is completely halted */ 1307static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index) 1308{ 1309 struct mwl8k_priv *priv = hw->priv; 1310 struct mwl8k_tx_queue *txq = priv->txq + index; 1311 1312 mwl8k_txq_reclaim(hw, index, 1); 1313 1314 kfree(txq->skb); 1315 txq->skb = NULL; 1316 1317 pci_free_consistent(priv->pdev, 1318 MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc), 1319 txq->txd, txq->txd_dma); 1320 txq->txd = NULL; 1321} 1322 1323static int 1324mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb) 1325{ 1326 struct mwl8k_priv *priv = hw->priv; 1327 struct ieee80211_tx_info *tx_info; 1328 struct mwl8k_vif *mwl8k_vif; 1329 struct ieee80211_hdr *wh; 1330 struct mwl8k_tx_queue *txq; 1331 struct mwl8k_tx_desc *tx; 1332 dma_addr_t dma; 1333 u32 txstatus; 1334 u8 txdatarate; 1335 u16 qos; 1336 1337 wh = (struct ieee80211_hdr *)skb->data; 1338 if (ieee80211_is_data_qos(wh->frame_control)) 1339 qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh))); 1340 else 1341 qos = 0; 1342 1343 mwl8k_add_dma_header(skb); 1344 wh = &((struct mwl8k_dma_data *)skb->data)->wh; 1345 1346 tx_info = IEEE80211_SKB_CB(skb); 1347 mwl8k_vif = MWL8K_VIF(tx_info->control.vif); 1348 1349 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { 1350 u16 seqno = mwl8k_vif->seqno; 1351 1352 wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); 1353 wh->seq_ctrl |= cpu_to_le16(seqno << 4); 1354 mwl8k_vif->seqno = seqno++ % 4096; 1355 } 1356 1357 /* Setup firmware control bit fields for each frame type. */ 1358 txstatus = 0; 1359 txdatarate = 0; 1360 if (ieee80211_is_mgmt(wh->frame_control) || 1361 ieee80211_is_ctl(wh->frame_control)) { 1362 txdatarate = 0; 1363 qos |= MWL8K_QOS_QLEN_UNSPEC | MWL8K_QOS_EOSP; 1364 } else if (ieee80211_is_data(wh->frame_control)) { 1365 txdatarate = 1; 1366 if (is_multicast_ether_addr(wh->addr1)) 1367 txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX; 1368 1369 qos &= ~MWL8K_QOS_ACK_POLICY_MASK; 1370 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) 1371 qos |= MWL8K_QOS_ACK_POLICY_BLOCKACK; 1372 else 1373 qos |= MWL8K_QOS_ACK_POLICY_NORMAL; 1374 } 1375 1376 dma = pci_map_single(priv->pdev, skb->data, 1377 skb->len, PCI_DMA_TODEVICE); 1378 1379 if (pci_dma_mapping_error(priv->pdev, dma)) { 1380 printk(KERN_DEBUG "%s: failed to dma map skb, " 1381 "dropping TX frame.\n", wiphy_name(hw->wiphy)); 1382 dev_kfree_skb(skb); 1383 return NETDEV_TX_OK; 1384 } 1385 1386 spin_lock_bh(&priv->tx_lock); 1387 1388 txq = priv->txq + index; 1389 1390 BUG_ON(txq->skb[txq->tail] != NULL); 1391 txq->skb[txq->tail] = skb; 1392 1393 tx = txq->txd + txq->tail; 1394 tx->data_rate = txdatarate; 1395 tx->tx_priority = index; 1396 tx->qos_control = cpu_to_le16(qos); 1397 tx->pkt_phys_addr = cpu_to_le32(dma); 1398 tx->pkt_len = cpu_to_le16(skb->len); 1399 tx->rate_info = 0; 1400 if (!priv->ap_fw && tx_info->control.sta != NULL) 1401 tx->peer_id = MWL8K_STA(tx_info->control.sta)->peer_id; 1402 else 1403 tx->peer_id = 0; 1404 wmb(); 1405 tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus); 1406 1407 txq->stats.count++; 1408 txq->stats.len++; 1409 priv->pending_tx_pkts++; 1410 1411 txq->tail++; 1412 if (txq->tail == MWL8K_TX_DESCS) 1413 txq->tail = 0; 1414 1415 if (txq->head == txq->tail) 1416 ieee80211_stop_queue(hw, index); 1417 1418 mwl8k_tx_start(priv); 1419 1420 spin_unlock_bh(&priv->tx_lock); 1421 1422 return NETDEV_TX_OK; 1423} 1424 1425 1426/* 1427 * Firmware access. 1428 * 1429 * We have the following requirements for issuing firmware commands: 1430 * - Some commands require that the packet transmit path is idle when 1431 * the command is issued. (For simplicity, we'll just quiesce the 1432 * transmit path for every command.) 1433 * - There are certain sequences of commands that need to be issued to 1434 * the hardware sequentially, with no other intervening commands. 1435 * 1436 * This leads to an implementation of a "firmware lock" as a mutex that 1437 * can be taken recursively, and which is taken by both the low-level 1438 * command submission function (mwl8k_post_cmd) as well as any users of 1439 * that function that require issuing of an atomic sequence of commands, 1440 * and quiesces the transmit path whenever it's taken. 1441 */ 1442static int mwl8k_fw_lock(struct ieee80211_hw *hw) 1443{ 1444 struct mwl8k_priv *priv = hw->priv; 1445 1446 if (priv->fw_mutex_owner != current) { 1447 int rc; 1448 1449 mutex_lock(&priv->fw_mutex); 1450 ieee80211_stop_queues(hw); 1451 1452 rc = mwl8k_tx_wait_empty(hw); 1453 if (rc) { 1454 ieee80211_wake_queues(hw); 1455 mutex_unlock(&priv->fw_mutex); 1456 1457 return rc; 1458 } 1459 1460 priv->fw_mutex_owner = current; 1461 } 1462 1463 priv->fw_mutex_depth++; 1464 1465 return 0; 1466} 1467 1468static void mwl8k_fw_unlock(struct ieee80211_hw *hw) 1469{ 1470 struct mwl8k_priv *priv = hw->priv; 1471 1472 if (!--priv->fw_mutex_depth) { 1473 ieee80211_wake_queues(hw); 1474 priv->fw_mutex_owner = NULL; 1475 mutex_unlock(&priv->fw_mutex); 1476 } 1477} 1478 1479 1480/* 1481 * Command processing. 1482 */ 1483 1484/* Timeout firmware commands after 10s */ 1485#define MWL8K_CMD_TIMEOUT_MS 10000 1486 1487static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd) 1488{ 1489 DECLARE_COMPLETION_ONSTACK(cmd_wait); 1490 struct mwl8k_priv *priv = hw->priv; 1491 void __iomem *regs = priv->regs; 1492 dma_addr_t dma_addr; 1493 unsigned int dma_size; 1494 int rc; 1495 unsigned long timeout = 0; 1496 u8 buf[32]; 1497 1498 cmd->result = 0xffff; 1499 dma_size = le16_to_cpu(cmd->length); 1500 dma_addr = pci_map_single(priv->pdev, cmd, dma_size, 1501 PCI_DMA_BIDIRECTIONAL); 1502 if (pci_dma_mapping_error(priv->pdev, dma_addr)) 1503 return -ENOMEM; 1504 1505 rc = mwl8k_fw_lock(hw); 1506 if (rc) { 1507 pci_unmap_single(priv->pdev, dma_addr, dma_size, 1508 PCI_DMA_BIDIRECTIONAL); 1509 return rc; 1510 } 1511 1512 priv->hostcmd_wait = &cmd_wait; 1513 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR); 1514 iowrite32(MWL8K_H2A_INT_DOORBELL, 1515 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); 1516 iowrite32(MWL8K_H2A_INT_DUMMY, 1517 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); 1518 1519 timeout = wait_for_completion_timeout(&cmd_wait, 1520 msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS)); 1521 1522 priv->hostcmd_wait = NULL; 1523 1524 mwl8k_fw_unlock(hw); 1525 1526 pci_unmap_single(priv->pdev, dma_addr, dma_size, 1527 PCI_DMA_BIDIRECTIONAL); 1528 1529 if (!timeout) { 1530 printk(KERN_ERR "%s: Command %s timeout after %u ms\n", 1531 wiphy_name(hw->wiphy), 1532 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)), 1533 MWL8K_CMD_TIMEOUT_MS); 1534 rc = -ETIMEDOUT; 1535 } else { 1536 int ms; 1537 1538 ms = MWL8K_CMD_TIMEOUT_MS - jiffies_to_msecs(timeout); 1539 1540 rc = cmd->result ? -EINVAL : 0; 1541 if (rc) 1542 printk(KERN_ERR "%s: Command %s error 0x%x\n", 1543 wiphy_name(hw->wiphy), 1544 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)), 1545 le16_to_cpu(cmd->result)); 1546 else if (ms > 2000) 1547 printk(KERN_NOTICE "%s: Command %s took %d ms\n", 1548 wiphy_name(hw->wiphy), 1549 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)), 1550 ms); 1551 } 1552 1553 return rc; 1554} 1555 1556/* 1557 * CMD_GET_HW_SPEC (STA version). 1558 */ 1559struct mwl8k_cmd_get_hw_spec_sta { 1560 struct mwl8k_cmd_pkt header; 1561 __u8 hw_rev; 1562 __u8 host_interface; 1563 __le16 num_mcaddrs; 1564 __u8 perm_addr[ETH_ALEN]; 1565 __le16 region_code; 1566 __le32 fw_rev; 1567 __le32 ps_cookie; 1568 __le32 caps; 1569 __u8 mcs_bitmap[16]; 1570 __le32 rx_queue_ptr; 1571 __le32 num_tx_queues; 1572 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES]; 1573 __le32 caps2; 1574 __le32 num_tx_desc_per_queue; 1575 __le32 total_rxd; 1576} __attribute__((packed)); 1577 1578#define MWL8K_CAP_MAX_AMSDU 0x20000000 1579#define MWL8K_CAP_GREENFIELD 0x08000000 1580#define MWL8K_CAP_AMPDU 0x04000000 1581#define MWL8K_CAP_RX_STBC 0x01000000 1582#define MWL8K_CAP_TX_STBC 0x00800000 1583#define MWL8K_CAP_SHORTGI_40MHZ 0x00400000 1584#define MWL8K_CAP_SHORTGI_20MHZ 0x00200000 1585#define MWL8K_CAP_RX_ANTENNA_MASK 0x000e0000 1586#define MWL8K_CAP_TX_ANTENNA_MASK 0x0001c000 1587#define MWL8K_CAP_DELAY_BA 0x00003000 1588#define MWL8K_CAP_MIMO 0x00000200 1589#define MWL8K_CAP_40MHZ 0x00000100 1590 1591static void mwl8k_set_ht_caps(struct ieee80211_hw *hw, u32 cap) 1592{ 1593 struct mwl8k_priv *priv = hw->priv; 1594 int rx_streams; 1595 int tx_streams; 1596 1597 priv->band.ht_cap.ht_supported = 1; 1598 1599 if (cap & MWL8K_CAP_MAX_AMSDU) 1600 priv->band.ht_cap.cap |= IEEE80211_HT_CAP_MAX_AMSDU; 1601 if (cap & MWL8K_CAP_GREENFIELD) 1602 priv->band.ht_cap.cap |= IEEE80211_HT_CAP_GRN_FLD; 1603 if (cap & MWL8K_CAP_AMPDU) { 1604 hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION; 1605 priv->band.ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; 1606 priv->band.ht_cap.ampdu_density = 1607 IEEE80211_HT_MPDU_DENSITY_NONE; 1608 } 1609 if (cap & MWL8K_CAP_RX_STBC) 1610 priv->band.ht_cap.cap |= IEEE80211_HT_CAP_RX_STBC; 1611 if (cap & MWL8K_CAP_TX_STBC) 1612 priv->band.ht_cap.cap |= IEEE80211_HT_CAP_TX_STBC; 1613 if (cap & MWL8K_CAP_SHORTGI_40MHZ) 1614 priv->band.ht_cap.cap |= IEEE80211_HT_CAP_SGI_40; 1615 if (cap & MWL8K_CAP_SHORTGI_20MHZ) 1616 priv->band.ht_cap.cap |= IEEE80211_HT_CAP_SGI_20; 1617 if (cap & MWL8K_CAP_DELAY_BA) 1618 priv->band.ht_cap.cap |= IEEE80211_HT_CAP_DELAY_BA; 1619 if (cap & MWL8K_CAP_40MHZ) 1620 priv->band.ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40; 1621 1622 rx_streams = hweight32(cap & MWL8K_CAP_RX_ANTENNA_MASK); 1623 tx_streams = hweight32(cap & MWL8K_CAP_TX_ANTENNA_MASK); 1624 1625 priv->band.ht_cap.mcs.rx_mask[0] = 0xff; 1626 if (rx_streams >= 2) 1627 priv->band.ht_cap.mcs.rx_mask[1] = 0xff; 1628 if (rx_streams >= 3) 1629 priv->band.ht_cap.mcs.rx_mask[2] = 0xff; 1630 priv->band.ht_cap.mcs.rx_mask[4] = 0x01; 1631 priv->band.ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; 1632 1633 if (rx_streams != tx_streams) { 1634 priv->band.ht_cap.mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF; 1635 priv->band.ht_cap.mcs.tx_params |= (tx_streams - 1) << 1636 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT; 1637 } 1638} 1639 1640static int mwl8k_cmd_get_hw_spec_sta(struct ieee80211_hw *hw) 1641{ 1642 struct mwl8k_priv *priv = hw->priv; 1643 struct mwl8k_cmd_get_hw_spec_sta *cmd; 1644 int rc; 1645 int i; 1646 1647 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); 1648 if (cmd == NULL) 1649 return -ENOMEM; 1650 1651 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC); 1652 cmd->header.length = cpu_to_le16(sizeof(*cmd)); 1653 1654 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr)); 1655 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma); 1656 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma); 1657 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES); 1658 for (i = 0; i < MWL8K_TX_QUEUES; i++) 1659 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma); 1660 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS); 1661 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS); 1662 1663 rc = mwl8k_post_cmd(hw, &cmd->header); 1664 1665 if (!rc) { 1666 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr); 1667 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs); 1668 priv->fw_rev = le32_to_cpu(cmd->fw_rev); 1669 priv->hw_rev = cmd->hw_rev; 1670 if (cmd->caps & cpu_to_le32(MWL8K_CAP_MIMO)) 1671 mwl8k_set_ht_caps(hw, le32_to_cpu(cmd->caps)); 1672 } 1673 1674 kfree(cmd); 1675 return rc; 1676} 1677 1678/* 1679 * CMD_GET_HW_SPEC (AP version). 1680 */ 1681struct mwl8k_cmd_get_hw_spec_ap { 1682 struct mwl8k_cmd_pkt header; 1683 __u8 hw_rev; 1684 __u8 host_interface; 1685 __le16 num_wcb; 1686 __le16 num_mcaddrs; 1687 __u8 perm_addr[ETH_ALEN]; 1688 __le16 region_code; 1689 __le16 num_antenna; 1690 __le32 fw_rev; 1691 __le32 wcbbase0; 1692 __le32 rxwrptr; 1693 __le32 rxrdptr; 1694 __le32 ps_cookie; 1695 __le32 wcbbase1; 1696 __le32 wcbbase2; 1697 __le32 wcbbase3; 1698} __attribute__((packed)); 1699 1700static int mwl8k_cmd_get_hw_spec_ap(struct ieee80211_hw *hw) 1701{ 1702 struct mwl8k_priv *priv = hw->priv; 1703 struct mwl8k_cmd_get_hw_spec_ap *cmd; 1704 int rc; 1705 1706 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); 1707 if (cmd == NULL) 1708 return -ENOMEM; 1709 1710 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC); 1711 cmd->header.length = cpu_to_le16(sizeof(*cmd)); 1712 1713 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr)); 1714 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma); 1715 1716 rc = mwl8k_post_cmd(hw, &cmd->header); 1717 1718 if (!rc) { 1719 int off; 1720 1721 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr); 1722 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs); 1723 priv->fw_rev = le32_to_cpu(cmd->fw_rev); 1724 priv->hw_rev = cmd->hw_rev; 1725 1726 off = le32_to_cpu(cmd->wcbbase0) & 0xffff; 1727 iowrite32(cpu_to_le32(priv->txq[0].txd_dma), priv->sram + off); 1728 1729 off = le32_to_cpu(cmd->rxwrptr) & 0xffff; 1730 iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off); 1731 1732 off = le32_to_cpu(cmd->rxrdptr) & 0xffff; 1733 iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off); 1734 1735 off = le32_to_cpu(cmd->wcbbase1) & 0xffff; 1736 iowrite32(cpu_to_le32(priv->txq[1].txd_dma), priv->sram + off); 1737 1738 off = le32_to_cpu(cmd->wcbbase2) & 0xffff; 1739 iowrite32(cpu_to_le32(priv->txq[2].txd_dma), priv->sram + off); 1740 1741 off = le32_to_cpu(cmd->wcbbase3) & 0xffff; 1742 iowrite32(cpu_to_le32(priv->txq[3].txd_dma), priv->sram + off); 1743 } 1744 1745 kfree(cmd); 1746 return rc; 1747} 1748 1749/* 1750 * CMD_SET_HW_SPEC. 1751 */ 1752struct mwl8k_cmd_set_hw_spec { 1753 struct mwl8k_cmd_pkt header; 1754 __u8 hw_rev; 1755 __u8 host_interface; 1756 __le16 num_mcaddrs; 1757 __u8 perm_addr[ETH_ALEN]; 1758 __le16 region_code; 1759 __le32 fw_rev; 1760 __le32 ps_cookie; 1761 __le32 caps; 1762 __le32 rx_queue_ptr; 1763 __le32 num_tx_queues; 1764 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES]; 1765 __le32 flags; 1766 __le32 num_tx_desc_per_queue; 1767 __le32 total_rxd; 1768} __attribute__((packed)); 1769 1770#define MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT 0x00000080 1771 1772static int mwl8k_cmd_set_hw_spec(struct ieee80211_hw *hw) 1773{ 1774 struct mwl8k_priv *priv = hw->priv; 1775 struct mwl8k_cmd_set_hw_spec *cmd; 1776 int rc; 1777 int i; 1778 1779 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); 1780 if (cmd == NULL) 1781 return -ENOMEM; 1782 1783 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_HW_SPEC); 1784 cmd->header.length = cpu_to_le16(sizeof(*cmd)); 1785 1786 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma); 1787 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma); 1788 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES); 1789 for (i = 0; i < MWL8K_TX_QUEUES; i++) 1790 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma); 1791 cmd->flags = cpu_to_le32(MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT); 1792 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS); 1793 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS); 1794 1795 rc = mwl8k_post_cmd(hw, &cmd->header); 1796 kfree(cmd); 1797 1798 return rc; 1799} 1800 1801/* 1802 * CMD_MAC_MULTICAST_ADR. 1803 */ 1804struct mwl8k_cmd_mac_multicast_adr { 1805 struct mwl8k_cmd_pkt header; 1806 __le16 action; 1807 __le16 numaddr; 1808 __u8 addr[0][ETH_ALEN]; 1809}; 1810 1811#define MWL8K_ENABLE_RX_DIRECTED 0x0001 1812#define MWL8K_ENABLE_RX_MULTICAST 0x0002 1813#define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004 1814#define MWL8K_ENABLE_RX_BROADCAST 0x0008 1815 1816static struct mwl8k_cmd_pkt * 1817__mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw, int allmulti, 1818 int mc_count, struct dev_addr_list *mclist) 1819{ 1820 struct mwl8k_priv *priv = hw->priv; 1821 struct mwl8k_cmd_mac_multicast_adr *cmd; 1822 int size; 1823 1824 if (allmulti || mc_count > priv->num_mcaddrs) { 1825 allmulti = 1; 1826 mc_count = 0; 1827 } 1828 1829 size = sizeof(*cmd) + mc_count * ETH_ALEN; 1830 1831 cmd = kzalloc(size, GFP_ATOMIC); 1832 if (cmd == NULL) 1833 return NULL; 1834 1835 cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR); 1836 cmd->header.length = cpu_to_le16(size); 1837 cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_DIRECTED | 1838 MWL8K_ENABLE_RX_BROADCAST); 1839 1840 if (allmulti) { 1841 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_ALL_MULTICAST); 1842 } else if (mc_count) { 1843 int i; 1844 1845 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST); 1846 cmd->numaddr = cpu_to_le16(mc_count); 1847 for (i = 0; i < mc_count && mclist; i++) { 1848 if (mclist->da_addrlen != ETH_ALEN) { 1849 kfree(cmd); 1850 return NULL; 1851 } 1852 memcpy(cmd->addr[i], mclist->da_addr, ETH_ALEN); 1853 mclist = mclist->next; 1854 } 1855 } 1856 1857 return &cmd->header; 1858} 1859 1860/* 1861 * CMD_GET_STAT. 1862 */ 1863struct mwl8k_cmd_get_stat { 1864 struct mwl8k_cmd_pkt header; 1865 __le32 stats[64]; 1866} __attribute__((packed)); 1867 1868#define MWL8K_STAT_ACK_FAILURE 9 1869#define MWL8K_STAT_RTS_FAILURE 12 1870#define MWL8K_STAT_FCS_ERROR 24 1871#define MWL8K_STAT_RTS_SUCCESS 11 1872 1873static int mwl8k_cmd_get_stat(struct ieee80211_hw *hw, 1874 struct ieee80211_low_level_stats *stats) 1875{ 1876 struct mwl8k_cmd_get_stat *cmd; 1877 int rc; 1878 1879 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); 1880 if (cmd == NULL) 1881 return -ENOMEM; 1882 1883 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT); 1884 cmd->header.length = cpu_to_le16(sizeof(*cmd)); 1885 1886 rc = mwl8k_post_cmd(hw, &cmd->header); 1887 if (!rc) { 1888 stats->dot11ACKFailureCount = 1889 le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]); 1890 stats->dot11RTSFailureCount = 1891 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]); 1892 stats->dot11FCSErrorCount = 1893 le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]); 1894 stats->dot11RTSSuccessCount = 1895 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]); 1896 } 1897 kfree(cmd); 1898 1899 return rc; 1900} 1901 1902/* 1903 * CMD_RADIO_CONTROL. 1904 */ 1905struct mwl8k_cmd_radio_control { 1906 struct mwl8k_cmd_pkt header; 1907 __le16 action; 1908 __le16 control; 1909 __le16 radio_on; 1910} __attribute__((packed)); 1911 1912static int 1913mwl8k_cmd_radio_control(struct ieee80211_hw *hw, bool enable, bool force) 1914{ 1915 struct mwl8k_priv *priv = hw->priv; 1916 struct mwl8k_cmd_radio_control *cmd; 1917 int rc; 1918 1919 if (enable == priv->radio_on && !force) 1920 return 0; 1921 1922 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); 1923 if (cmd == NULL) 1924 return -ENOMEM; 1925 1926 cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL); 1927 cmd->header.length = cpu_to_le16(sizeof(*cmd)); 1928 cmd->action = cpu_to_le16(MWL8K_CMD_SET); 1929 cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1); 1930 cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000); 1931 1932 rc = mwl8k_post_cmd(hw, &cmd->header); 1933 kfree(cmd); 1934 1935 if (!rc) 1936 priv->radio_on = enable; 1937 1938 return rc; 1939} 1940 1941static int mwl8k_cmd_radio_disable(struct ieee80211_hw *hw) 1942{ 1943 return mwl8k_cmd_radio_control(hw, 0, 0); 1944} 1945 1946static int mwl8k_cmd_radio_enable(struct ieee80211_hw *hw) 1947{ 1948 return mwl8k_cmd_radio_control(hw, 1, 0); 1949} 1950 1951static int 1952mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble) 1953{ 1954 struct mwl8k_priv *priv = hw->priv; 1955 1956 priv->radio_short_preamble = short_preamble; 1957 1958 return mwl8k_cmd_radio_control(hw, 1, 1); 1959} 1960 1961/* 1962 * CMD_RF_TX_POWER. 1963 */ 1964#define MWL8K_TX_POWER_LEVEL_TOTAL 8 1965 1966struct mwl8k_cmd_rf_tx_power { 1967 struct mwl8k_cmd_pkt header; 1968 __le16 action; 1969 __le16 support_level; 1970 __le16 current_level; 1971 __le16 reserved; 1972 __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL]; 1973} __attribute__((packed)); 1974 1975static int mwl8k_cmd_rf_tx_power(struct ieee80211_hw *hw, int dBm) 1976{ 1977 struct mwl8k_cmd_rf_tx_power *cmd; 1978 int rc; 1979 1980 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); 1981 if (cmd == NULL) 1982 return -ENOMEM; 1983 1984 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER); 1985 cmd->header.length = cpu_to_le16(sizeof(*cmd)); 1986 cmd->action = cpu_to_le16(MWL8K_CMD_SET); 1987 cmd->support_level = cpu_to_le16(dBm); 1988 1989 rc = mwl8k_post_cmd(hw, &cmd->header); 1990 kfree(cmd); 1991 1992 return rc; 1993} 1994 1995/* 1996 * CMD_RF_ANTENNA. 1997 */ 1998struct mwl8k_cmd_rf_antenna { 1999 struct mwl8k_cmd_pkt header; 2000 __le16 antenna; 2001 __le16 mode; 2002} __attribute__((packed)); 2003 2004#define MWL8K_RF_ANTENNA_RX 1 2005#define MWL8K_RF_ANTENNA_TX 2 2006 2007static int 2008mwl8k_cmd_rf_antenna(struct ieee80211_hw *hw, int antenna, int mask) 2009{ 2010 struct mwl8k_cmd_rf_antenna *cmd; 2011 int rc; 2012 2013 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); 2014 if (cmd == NULL) 2015 return -ENOMEM; 2016 2017 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_ANTENNA); 2018 cmd->header.length = cpu_to_le16(sizeof(*cmd)); 2019 cmd->antenna = cpu_to_le16(antenna); 2020 cmd->mode = cpu_to_le16(mask); 2021 2022 rc = mwl8k_post_cmd(hw, &cmd->header); 2023 kfree(cmd); 2024 2025 return rc; 2026} 2027 2028/* 2029 * CMD_SET_PRE_SCAN. 2030 */ 2031struct mwl8k_cmd_set_pre_scan { 2032 struct mwl8k_cmd_pkt header; 2033} __attribute__((packed)); 2034 2035static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw) 2036{ 2037 struct mwl8k_cmd_set_pre_scan *cmd; 2038 int rc; 2039 2040 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); 2041 if (cmd == NULL) 2042 return -ENOMEM; 2043 2044 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN); 2045 cmd->header.length = cpu_to_le16(sizeof(*cmd)); 2046 2047 rc = mwl8k_post_cmd(hw, &cmd->header); 2048 kfree(cmd); 2049 2050 return rc; 2051} 2052 2053/* 2054 * CMD_SET_POST_SCAN. 2055 */ 2056struct mwl8k_cmd_set_post_scan { 2057 struct mwl8k_cmd_pkt header; 2058 __le32 isibss; 2059 __u8 bssid[ETH_ALEN]; 2060} __attribute__((packed)); 2061 2062static int 2063mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, const __u8 *mac) 2064{ 2065 struct mwl8k_cmd_set_post_scan *cmd; 2066 int rc; 2067 2068 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); 2069 if (cmd == NULL) 2070 return -ENOMEM; 2071 2072 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN); 2073 cmd->header.length = cpu_to_le16(sizeof(*cmd)); 2074 cmd->isibss = 0; 2075 memcpy(cmd->bssid, mac, ETH_ALEN); 2076 2077 rc = mwl8k_post_cmd(hw, &cmd->header); 2078 kfree(cmd); 2079 2080 return rc; 2081} 2082 2083/* 2084 * CMD_SET_RF_CHANNEL. 2085 */ 2086struct mwl8k_cmd_set_rf_channel { 2087 struct mwl8k_cmd_pkt header; 2088 __le16 action; 2089 __u8 current_channel; 2090 __le32 channel_flags; 2091} __attribute__((packed)); 2092 2093static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw, 2094 struct ieee80211_conf *conf) 2095{ 2096 struct ieee80211_channel *channel = conf->channel; 2097 struct mwl8k_cmd_set_rf_channel *cmd; 2098 int rc; 2099 2100 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); 2101 if (cmd == NULL) 2102 return -ENOMEM; 2103 2104 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL); 2105 cmd->header.length = cpu_to_le16(sizeof(*cmd)); 2106 cmd->action = cpu_to_le16(MWL8K_CMD_SET); 2107 cmd->current_channel = channel->hw_value; 2108 2109 if (channel->band == IEEE80211_BAND_2GHZ) 2110 cmd->channel_flags |= cpu_to_le32(0x00000001); 2111 2112 if (conf->channel_type == NL80211_CHAN_NO_HT || 2113 conf->channel_type == NL80211_CHAN_HT20) 2114 cmd->channel_flags |= cpu_to_le32(0x00000080); 2115 else if (conf->channel_type == NL80211_CHAN_HT40MINUS) 2116 cmd->channel_flags |= cpu_to_le32(0x000001900); 2117 else if (conf->channel_type == NL80211_CHAN_HT40PLUS) 2118 cmd->channel_flags |= cpu_to_le32(0x000000900); 2119 2120 rc = mwl8k_post_cmd(hw, &cmd->header); 2121 kfree(cmd); 2122 2123 return rc; 2124} 2125 2126/* 2127 * CMD_SET_AID. 2128 */ 2129#define MWL8K_FRAME_PROT_DISABLED 0x00 2130#define MWL8K_FRAME_PROT_11G 0x07 2131#define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02 2132#define MWL8K_FRAME_PROT_11N_HT_ALL 0x06 2133 2134struct mwl8k_cmd_update_set_aid { 2135 struct mwl8k_cmd_pkt header; 2136 __le16 aid; 2137 2138 /* AP's MAC address (BSSID) */ 2139 __u8 bssid[ETH_ALEN]; 2140 __le16 protection_mode; 2141 __u8 supp_rates[14]; 2142} __attribute__((packed)); 2143 2144static void legacy_rate_mask_to_array(u8 *rates, u32 mask) 2145{ 2146 int i; 2147 int j; 2148 2149 /* 2150 * Clear nonstandard rates 4 and 13. 2151 */ 2152 mask &= 0x1fef; 2153 2154 for (i = 0, j = 0; i < 14; i++) { 2155 if (mask & (1 << i)) 2156 rates[j++] = mwl8k_rates[i].hw_value; 2157 } 2158} 2159 2160static int 2161mwl8k_cmd_set_aid(struct ieee80211_hw *hw, 2162 struct ieee80211_vif *vif, u32 legacy_rate_mask) 2163{ 2164 struct mwl8k_cmd_update_set_aid *cmd; 2165 u16 prot_mode; 2166 int rc; 2167 2168 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); 2169 if (cmd == NULL) 2170 return -ENOMEM; 2171 2172 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID); 2173 cmd->header.length = cpu_to_le16(sizeof(*cmd)); 2174 cmd->aid = cpu_to_le16(vif->bss_conf.aid); 2175 memcpy(cmd->bssid, vif->bss_conf.bssid, ETH_ALEN); 2176 2177 if (vif->bss_conf.use_cts_prot) { 2178 prot_mode = MWL8K_FRAME_PROT_11G; 2179 } else { 2180 switch (vif->bss_conf.ht_operation_mode & 2181 IEEE80211_HT_OP_MODE_PROTECTION) { 2182 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ: 2183 prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY; 2184 break; 2185 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED: 2186 prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL; 2187 break; 2188 default: 2189 prot_mode = MWL8K_FRAME_PROT_DISABLED; 2190 break; 2191 } 2192 } 2193 cmd->protection_mode = cpu_to_le16(prot_mode); 2194 2195 legacy_rate_mask_to_array(cmd->supp_rates, legacy_rate_mask); 2196 2197 rc = mwl8k_post_cmd(hw, &cmd->header); 2198 kfree(cmd); 2199 2200 return rc; 2201} 2202 2203/* 2204 * CMD_SET_RATE. 2205 */ 2206struct mwl8k_cmd_set_rate { 2207 struct mwl8k_cmd_pkt header; 2208 __u8 legacy_rates[14]; 2209 2210 /* Bitmap for supported MCS codes. */ 2211 __u8 mcs_set[16]; 2212 __u8 reserved[16]; 2213} __attribute__((packed)); 2214 2215static int 2216mwl8k_cmd_set_rate(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 2217 u32 legacy_rate_mask, u8 *mcs_rates) 2218{ 2219 struct mwl8k_cmd_set_rate *cmd; 2220 int rc; 2221 2222 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); 2223 if (cmd == NULL) 2224 return -ENOMEM; 2225 2226 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE); 2227 cmd->header.length = cpu_to_le16(sizeof(*cmd)); 2228 legacy_rate_mask_to_array(cmd->legacy_rates, legacy_rate_mask); 2229 memcpy(cmd->mcs_set, mcs_rates, 16); 2230 2231 rc = mwl8k_post_cmd(hw, &cmd->header); 2232 kfree(cmd); 2233 2234 return rc; 2235} 2236 2237/* 2238 * CMD_FINALIZE_JOIN. 2239 */ 2240#define MWL8K_FJ_BEACON_MAXLEN 128 2241 2242struct mwl8k_cmd_finalize_join { 2243 struct mwl8k_cmd_pkt header; 2244 __le32 sleep_interval; /* Number of beacon periods to sleep */ 2245 __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN]; 2246} __attribute__((packed)); 2247 2248static int mwl8k_cmd_finalize_join(struct ieee80211_hw *hw, void *frame, 2249 int framelen, int dtim) 2250{ 2251 struct mwl8k_cmd_finalize_join *cmd; 2252 struct ieee80211_mgmt *payload = frame; 2253 int payload_len; 2254 int rc; 2255 2256 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); 2257 if (cmd == NULL) 2258 return -ENOMEM; 2259 2260 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN); 2261 cmd->header.length = cpu_to_le16(sizeof(*cmd)); 2262 cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1); 2263 2264 payload_len = framelen - ieee80211_hdrlen(payload->frame_control); 2265 if (payload_len < 0) 2266 payload_len = 0; 2267 else if (payload_len > MWL8K_FJ_BEACON_MAXLEN) 2268 payload_len = MWL8K_FJ_BEACON_MAXLEN; 2269 2270 memcpy(cmd->beacon_data, &payload->u.beacon, payload_len); 2271 2272 rc = mwl8k_post_cmd(hw, &cmd->header); 2273 kfree(cmd); 2274 2275 return rc; 2276} 2277 2278/* 2279 * CMD_SET_RTS_THRESHOLD. 2280 */ 2281struct mwl8k_cmd_set_rts_threshold { 2282 struct mwl8k_cmd_pkt header; 2283 __le16 action; 2284 __le16 threshold; 2285} __attribute__((packed)); 2286 2287static int 2288mwl8k_cmd_set_rts_threshold(struct ieee80211_hw *hw, int rts_thresh) 2289{ 2290 struct mwl8k_cmd_set_rts_threshold *cmd; 2291 int rc; 2292 2293 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); 2294 if (cmd == NULL) 2295 return -ENOMEM; 2296 2297 cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD); 2298 cmd->header.length = cpu_to_le16(sizeof(*cmd)); 2299 cmd->action = cpu_to_le16(MWL8K_CMD_SET); 2300 cmd->threshold = cpu_to_le16(rts_thresh); 2301 2302 rc = mwl8k_post_cmd(hw, &cmd->header); 2303 kfree(cmd); 2304 2305 return rc; 2306} 2307 2308/* 2309 * CMD_SET_SLOT. 2310 */ 2311struct mwl8k_cmd_set_slot { 2312 struct mwl8k_cmd_pkt header; 2313 __le16 action; 2314 __u8 short_slot; 2315} __attribute__((packed)); 2316 2317static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time) 2318{ 2319 struct mwl8k_cmd_set_slot *cmd; 2320 int rc; 2321 2322 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); 2323 if (cmd == NULL) 2324 return -ENOMEM; 2325 2326 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT); 2327 cmd->header.length = cpu_to_le16(sizeof(*cmd)); 2328 cmd->action = cpu_to_le16(MWL8K_CMD_SET); 2329 cmd->short_slot = short_slot_time; 2330 2331 rc = mwl8k_post_cmd(hw, &cmd->header); 2332 kfree(cmd); 2333 2334 return rc; 2335} 2336 2337/* 2338 * CMD_SET_EDCA_PARAMS. 2339 */ 2340struct mwl8k_cmd_set_edca_params { 2341 struct mwl8k_cmd_pkt header; 2342 2343 /* See MWL8K_SET_EDCA_XXX below */ 2344 __le16 action; 2345 2346 /* TX opportunity in units of 32 us */ 2347 __le16 txop; 2348 2349 union { 2350 struct { 2351 /* Log exponent of max contention period: 0...15 */ 2352 __le32 log_cw_max; 2353 2354 /* Log exponent of min contention period: 0...15 */ 2355 __le32 log_cw_min; 2356 2357 /* Adaptive interframe spacing in units of 32us */ 2358 __u8 aifs; 2359 2360 /* TX queue to configure */ 2361 __u8 txq; 2362 } ap; 2363 struct { 2364 /* Log exponent of max contention period: 0...15 */ 2365 __u8 log_cw_max; 2366 2367 /* Log exponent of min contention period: 0...15 */ 2368 __u8 log_cw_min; 2369 2370 /* Adaptive interframe spacing in units of 32us */ 2371 __u8 aifs; 2372 2373 /* TX queue to configure */ 2374 __u8 txq; 2375 } sta; 2376 }; 2377} __attribute__((packed)); 2378 2379#define MWL8K_SET_EDCA_CW 0x01 2380#define MWL8K_SET_EDCA_TXOP 0x02 2381#define MWL8K_SET_EDCA_AIFS 0x04 2382 2383#define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \ 2384 MWL8K_SET_EDCA_TXOP | \ 2385 MWL8K_SET_EDCA_AIFS) 2386 2387static int 2388mwl8k_cmd_set_edca_params(struct ieee80211_hw *hw, __u8 qnum, 2389 __u16 cw_min, __u16 cw_max, 2390 __u8 aifs, __u16 txop) 2391{ 2392 struct mwl8k_priv *priv = hw->priv; 2393 struct mwl8k_cmd_set_edca_params *cmd; 2394 int rc; 2395 2396 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); 2397 if (cmd == NULL) 2398 return -ENOMEM; 2399 2400 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS); 2401 cmd->header.length = cpu_to_le16(sizeof(*cmd)); 2402 cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL); 2403 cmd->txop = cpu_to_le16(txop); 2404 if (priv->ap_fw) { 2405 cmd->ap.log_cw_max = cpu_to_le32(ilog2(cw_max + 1)); 2406 cmd->ap.log_cw_min = cpu_to_le32(ilog2(cw_min + 1)); 2407 cmd->ap.aifs = aifs; 2408 cmd->ap.txq = qnum; 2409 } else { 2410 cmd->sta.log_cw_max = (u8)ilog2(cw_max + 1); 2411 cmd->sta.log_cw_min = (u8)ilog2(cw_min + 1); 2412 cmd->sta.aifs = aifs; 2413 cmd->sta.txq = qnum; 2414 } 2415 2416 rc = mwl8k_post_cmd(hw, &cmd->header); 2417 kfree(cmd); 2418 2419 return rc; 2420} 2421 2422/* 2423 * CMD_SET_WMM_MODE. 2424 */ 2425struct mwl8k_cmd_set_wmm_mode { 2426 struct mwl8k_cmd_pkt header; 2427 __le16 action; 2428} __attribute__((packed)); 2429 2430static int mwl8k_cmd_set_wmm_mode(struct ieee80211_hw *hw, bool enable) 2431{ 2432 struct mwl8k_priv *priv = hw->priv; 2433 struct mwl8k_cmd_set_wmm_mode *cmd; 2434 int rc; 2435 2436 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); 2437 if (cmd == NULL) 2438 return -ENOMEM; 2439 2440 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE); 2441 cmd->header.length = cpu_to_le16(sizeof(*cmd)); 2442 cmd->action = cpu_to_le16(!!enable); 2443 2444 rc = mwl8k_post_cmd(hw, &cmd->header); 2445 kfree(cmd); 2446 2447 if (!rc) 2448 priv->wmm_enabled = enable; 2449 2450 return rc; 2451} 2452 2453/* 2454 * CMD_MIMO_CONFIG. 2455 */ 2456struct mwl8k_cmd_mimo_config { 2457 struct mwl8k_cmd_pkt header; 2458 __le32 action; 2459 __u8 rx_antenna_map; 2460 __u8 tx_antenna_map; 2461} __attribute__((packed)); 2462 2463static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx) 2464{ 2465 struct mwl8k_cmd_mimo_config *cmd; 2466 int rc; 2467 2468 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); 2469 if (cmd == NULL) 2470 return -ENOMEM; 2471 2472 cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG); 2473 cmd->header.length = cpu_to_le16(sizeof(*cmd)); 2474 cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET); 2475 cmd->rx_antenna_map = rx; 2476 cmd->tx_antenna_map = tx; 2477 2478 rc = mwl8k_post_cmd(hw, &cmd->header); 2479 kfree(cmd); 2480 2481 return rc; 2482} 2483 2484/* 2485 * CMD_USE_FIXED_RATE (STA version). 2486 */ 2487struct mwl8k_cmd_use_fixed_rate_sta { 2488 struct mwl8k_cmd_pkt header; 2489 __le32 action; 2490 __le32 allow_rate_drop; 2491 __le32 num_rates; 2492 struct { 2493 __le32 is_ht_rate; 2494 __le32 enable_retry; 2495 __le32 rate; 2496 __le32 retry_count; 2497 } rate_entry[8]; 2498 __le32 rate_type; 2499 __le32 reserved1; 2500 __le32 reserved2; 2501} __attribute__((packed)); 2502 2503#define MWL8K_USE_AUTO_RATE 0x0002 2504#define MWL8K_UCAST_RATE 0 2505 2506static int mwl8k_cmd_use_fixed_rate_sta(struct ieee80211_hw *hw) 2507{ 2508 struct mwl8k_cmd_use_fixed_rate_sta *cmd; 2509 int rc; 2510 2511 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); 2512 if (cmd == NULL) 2513 return -ENOMEM; 2514 2515 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE); 2516 cmd->header.length = cpu_to_le16(sizeof(*cmd)); 2517 cmd->action = cpu_to_le32(MWL8K_USE_AUTO_RATE); 2518 cmd->rate_type = cpu_to_le32(MWL8K_UCAST_RATE); 2519 2520 rc = mwl8k_post_cmd(hw, &cmd->header); 2521 kfree(cmd); 2522 2523 return rc; 2524} 2525 2526/* 2527 * CMD_USE_FIXED_RATE (AP version). 2528 */ 2529struct mwl8k_cmd_use_fixed_rate_ap { 2530 struct mwl8k_cmd_pkt header; 2531 __le32 action; 2532 __le32 allow_rate_drop; 2533 __le32 num_rates; 2534 struct mwl8k_rate_entry_ap { 2535 __le32 is_ht_rate; 2536 __le32 enable_retry; 2537 __le32 rate; 2538 __le32 retry_count; 2539 } rate_entry[4]; 2540 u8 multicast_rate; 2541 u8 multicast_rate_type; 2542 u8 management_rate; 2543} __attribute__((packed)); 2544 2545static int 2546mwl8k_cmd_use_fixed_rate_ap(struct ieee80211_hw *hw, int mcast, int mgmt) 2547{ 2548 struct mwl8k_cmd_use_fixed_rate_ap *cmd; 2549 int rc; 2550 2551 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); 2552 if (cmd == NULL) 2553 return -ENOMEM; 2554 2555 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE); 2556 cmd->header.length = cpu_to_le16(sizeof(*cmd)); 2557 cmd->action = cpu_to_le32(MWL8K_USE_AUTO_RATE); 2558 cmd->multicast_rate = mcast; 2559 cmd->management_rate = mgmt; 2560 2561 rc = mwl8k_post_cmd(hw, &cmd->header); 2562 kfree(cmd); 2563 2564 return rc; 2565} 2566 2567/* 2568 * CMD_ENABLE_SNIFFER. 2569 */ 2570struct mwl8k_cmd_enable_sniffer { 2571 struct mwl8k_cmd_pkt header; 2572 __le32 action; 2573} __attribute__((packed)); 2574 2575static int mwl8k_cmd_enable_sniffer(struct ieee80211_hw *hw, bool enable) 2576{ 2577 struct mwl8k_cmd_enable_sniffer *cmd; 2578 int rc; 2579 2580 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); 2581 if (cmd == NULL) 2582 return -ENOMEM; 2583 2584 cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER); 2585 cmd->header.length = cpu_to_le16(sizeof(*cmd)); 2586 cmd->action = cpu_to_le32(!!enable); 2587 2588 rc = mwl8k_post_cmd(hw, &cmd->header); 2589 kfree(cmd); 2590 2591 return rc; 2592} 2593 2594/* 2595 * CMD_SET_MAC_ADDR. 2596 */ 2597struct mwl8k_cmd_set_mac_addr { 2598 struct mwl8k_cmd_pkt header; 2599 union { 2600 struct { 2601 __le16 mac_type; 2602 __u8 mac_addr[ETH_ALEN]; 2603 } mbss; 2604 __u8 mac_addr[ETH_ALEN]; 2605 }; 2606} __attribute__((packed)); 2607 2608static int mwl8k_cmd_set_mac_addr(struct ieee80211_hw *hw, u8 *mac) 2609{ 2610 struct mwl8k_priv *priv = hw->priv; 2611 struct mwl8k_cmd_set_mac_addr *cmd; 2612 int rc; 2613 2614 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); 2615 if (cmd == NULL) 2616 return -ENOMEM; 2617 2618 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_MAC_ADDR); 2619 cmd->header.length = cpu_to_le16(sizeof(*cmd)); 2620 if (priv->ap_fw) { 2621 cmd->mbss.mac_type = 0; 2622 memcpy(cmd->mbss.mac_addr, mac, ETH_ALEN); 2623 } else { 2624 memcpy(cmd->mac_addr, mac, ETH_ALEN); 2625 } 2626 2627 rc = mwl8k_post_cmd(hw, &cmd->header); 2628 kfree(cmd); 2629 2630 return rc; 2631} 2632 2633/* 2634 * CMD_SET_RATEADAPT_MODE. 2635 */ 2636struct mwl8k_cmd_set_rate_adapt_mode { 2637 struct mwl8k_cmd_pkt header; 2638 __le16 action; 2639 __le16 mode; 2640} __attribute__((packed)); 2641 2642static int mwl8k_cmd_set_rateadapt_mode(struct ieee80211_hw *hw, __u16 mode) 2643{ 2644 struct mwl8k_cmd_set_rate_adapt_mode *cmd; 2645 int rc; 2646 2647 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); 2648 if (cmd == NULL) 2649 return -ENOMEM; 2650 2651 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE); 2652 cmd->header.length = cpu_to_le16(sizeof(*cmd)); 2653 cmd->action = cpu_to_le16(MWL8K_CMD_SET); 2654 cmd->mode = cpu_to_le16(mode); 2655 2656 rc = mwl8k_post_cmd(hw, &cmd->header); 2657 kfree(cmd); 2658 2659 return rc; 2660} 2661 2662/* 2663 * CMD_UPDATE_STADB. 2664 */ 2665struct ewc_ht_info { 2666 __le16 control1; 2667 __le16 control2; 2668 __le16 control3; 2669} __attribute__((packed)); 2670 2671struct peer_capability_info { 2672 /* Peer type - AP vs. STA. */ 2673 __u8 peer_type; 2674 2675 /* Basic 802.11 capabilities from assoc resp. */ 2676 __le16 basic_caps; 2677 2678 /* Set if peer supports 802.11n high throughput (HT). */ 2679 __u8 ht_support; 2680 2681 /* Valid if HT is supported. */ 2682 __le16 ht_caps; 2683 __u8 extended_ht_caps; 2684 struct ewc_ht_info ewc_info; 2685 2686 /* Legacy rate table. Intersection of our rates and peer rates. */ 2687 __u8 legacy_rates[12]; 2688 2689 /* HT rate table. Intersection of our rates and peer rates. */ 2690 __u8 ht_rates[16]; 2691 __u8 pad[16]; 2692 2693 /* If set, interoperability mode, no proprietary extensions. */ 2694 __u8 interop; 2695 __u8 pad2; 2696 __u8 station_id; 2697 __le16 amsdu_enabled; 2698} __attribute__((packed)); 2699 2700struct mwl8k_cmd_update_stadb { 2701 struct mwl8k_cmd_pkt header; 2702 2703 /* See STADB_ACTION_TYPE */ 2704 __le32 action; 2705 2706 /* Peer MAC address */ 2707 __u8 peer_addr[ETH_ALEN]; 2708 2709 __le32 reserved; 2710 2711 /* Peer info - valid during add/update. */ 2712 struct peer_capability_info peer_info; 2713} __attribute__((packed)); 2714 2715#define MWL8K_STA_DB_MODIFY_ENTRY 1 2716#define MWL8K_STA_DB_DEL_ENTRY 2 2717 2718/* Peer Entry flags - used to define the type of the peer node */ 2719#define MWL8K_PEER_TYPE_ACCESSPOINT 2 2720 2721static int mwl8k_cmd_update_stadb_add(struct ieee80211_hw *hw, 2722 struct ieee80211_vif *vif, 2723 struct ieee80211_sta *sta) 2724{ 2725 struct mwl8k_cmd_update_stadb *cmd; 2726 struct peer_capability_info *p; 2727 int rc; 2728 2729 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); 2730 if (cmd == NULL) 2731 return -ENOMEM; 2732 2733 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB); 2734 cmd->header.length = cpu_to_le16(sizeof(*cmd)); 2735 cmd->action = cpu_to_le32(MWL8K_STA_DB_MODIFY_ENTRY); 2736 memcpy(cmd->peer_addr, sta->addr, ETH_ALEN); 2737 2738 p = &cmd->peer_info; 2739 p->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT; 2740 p->basic_caps = cpu_to_le16(vif->bss_conf.assoc_capability); 2741 p->ht_support = sta->ht_cap.ht_supported; 2742 p->ht_caps = sta->ht_cap.cap; 2743 p->extended_ht_caps = (sta->ht_cap.ampdu_factor & 3) | 2744 ((sta->ht_cap.ampdu_density & 7) << 2); 2745 legacy_rate_mask_to_array(p->legacy_rates, 2746 sta->supp_rates[IEEE80211_BAND_2GHZ]); 2747 memcpy(p->ht_rates, sta->ht_cap.mcs.rx_mask, 16); 2748 p->interop = 1; 2749 p->amsdu_enabled = 0; 2750 2751 rc = mwl8k_post_cmd(hw, &cmd->header); 2752 kfree(cmd); 2753 2754 return rc ? rc : p->station_id; 2755} 2756 2757static int mwl8k_cmd_update_stadb_del(struct ieee80211_hw *hw, 2758 struct ieee80211_vif *vif, u8 *addr) 2759{ 2760 struct mwl8k_cmd_update_stadb *cmd; 2761 int rc; 2762 2763 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); 2764 if (cmd == NULL) 2765 return -ENOMEM; 2766 2767 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB); 2768 cmd->header.length = cpu_to_le16(sizeof(*cmd)); 2769 cmd->action = cpu_to_le32(MWL8K_STA_DB_DEL_ENTRY); 2770 memcpy(cmd->peer_addr, addr, ETH_ALEN); 2771 2772 rc = mwl8k_post_cmd(hw, &cmd->header); 2773 kfree(cmd); 2774 2775 return rc; 2776} 2777 2778 2779/* 2780 * Interrupt handling. 2781 */ 2782static irqreturn_t mwl8k_interrupt(int irq, void *dev_id) 2783{ 2784 struct ieee80211_hw *hw = dev_id; 2785 struct mwl8k_priv *priv = hw->priv; 2786 u32 status; 2787 2788 status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS); 2789 iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS); 2790 2791 if (!status) 2792 return IRQ_NONE; 2793 2794 if (status & MWL8K_A2H_INT_TX_DONE) 2795 tasklet_schedule(&priv->tx_reclaim_task); 2796 2797 if (status & MWL8K_A2H_INT_RX_READY) { 2798 while (rxq_process(hw, 0, 1)) 2799 rxq_refill(hw, 0, 1); 2800 } 2801 2802 if (status & MWL8K_A2H_INT_OPC_DONE) { 2803 if (priv->hostcmd_wait != NULL) 2804 complete(priv->hostcmd_wait); 2805 } 2806 2807 if (status & MWL8K_A2H_INT_QUEUE_EMPTY) { 2808 if (!mutex_is_locked(&priv->fw_mutex) && 2809 priv->radio_on && priv->pending_tx_pkts) 2810 mwl8k_tx_start(priv); 2811 } 2812 2813 return IRQ_HANDLED; 2814} 2815 2816 2817/* 2818 * Core driver operations. 2819 */ 2820static int mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb) 2821{ 2822 struct mwl8k_priv *priv = hw->priv; 2823 int index = skb_get_queue_mapping(skb); 2824 int rc; 2825 2826 if (priv->current_channel == NULL) { 2827 printk(KERN_DEBUG "%s: dropped TX frame since radio " 2828 "disabled\n", wiphy_name(hw->wiphy)); 2829 dev_kfree_skb(skb); 2830 return NETDEV_TX_OK; 2831 } 2832 2833 rc = mwl8k_txq_xmit(hw, index, skb); 2834 2835 return rc; 2836} 2837 2838static int mwl8k_start(struct ieee80211_hw *hw) 2839{ 2840 struct mwl8k_priv *priv = hw->priv; 2841 int rc; 2842 2843 rc = request_irq(priv->pdev->irq, mwl8k_interrupt, 2844 IRQF_SHARED, MWL8K_NAME, hw); 2845 if (rc) { 2846 printk(KERN_ERR "%s: failed to register IRQ handler\n", 2847 wiphy_name(hw->wiphy)); 2848 return -EIO; 2849 } 2850 2851 /* Enable tx reclaim tasklet */ 2852 tasklet_enable(&priv->tx_reclaim_task); 2853 2854 /* Enable interrupts */ 2855 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK); 2856 2857 rc = mwl8k_fw_lock(hw); 2858 if (!rc) { 2859 rc = mwl8k_cmd_radio_enable(hw); 2860 2861 if (!priv->ap_fw) { 2862 if (!rc) 2863 rc = mwl8k_cmd_enable_sniffer(hw, 0); 2864 2865 if (!rc) 2866 rc = mwl8k_cmd_set_pre_scan(hw); 2867 2868 if (!rc) 2869 rc = mwl8k_cmd_set_post_scan(hw, 2870 "\x00\x00\x00\x00\x00\x00"); 2871 } 2872 2873 if (!rc) 2874 rc = mwl8k_cmd_set_rateadapt_mode(hw, 0); 2875 2876 if (!rc) 2877 rc = mwl8k_cmd_set_wmm_mode(hw, 0); 2878 2879 mwl8k_fw_unlock(hw); 2880 } 2881 2882 if (rc) { 2883 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK); 2884 free_irq(priv->pdev->irq, hw); 2885 tasklet_disable(&priv->tx_reclaim_task); 2886 } 2887 2888 return rc; 2889} 2890 2891static void mwl8k_stop(struct ieee80211_hw *hw) 2892{ 2893 struct mwl8k_priv *priv = hw->priv; 2894 int i; 2895 2896 mwl8k_cmd_radio_disable(hw); 2897 2898 ieee80211_stop_queues(hw); 2899 2900 /* Disable interrupts */ 2901 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK); 2902 free_irq(priv->pdev->irq, hw); 2903 2904 /* Stop finalize join worker */ 2905 cancel_work_sync(&priv->finalize_join_worker); 2906 if (priv->beacon_skb != NULL) 2907 dev_kfree_skb(priv->beacon_skb); 2908 2909 /* Stop tx reclaim tasklet */ 2910 tasklet_disable(&priv->tx_reclaim_task); 2911 2912 /* Return all skbs to mac80211 */ 2913 for (i = 0; i < MWL8K_TX_QUEUES; i++) 2914 mwl8k_txq_reclaim(hw, i, 1); 2915} 2916 2917static int mwl8k_add_interface(struct ieee80211_hw *hw, 2918 struct ieee80211_vif *vif) 2919{ 2920 struct mwl8k_priv *priv = hw->priv; 2921 struct mwl8k_vif *mwl8k_vif; 2922 2923 /* 2924 * We only support one active interface at a time. 2925 */ 2926 if (priv->vif != NULL) 2927 return -EBUSY; 2928 2929 /* 2930 * We only support managed interfaces for now. 2931 */ 2932 if (vif->type != NL80211_IFTYPE_STATION) 2933 return -EINVAL; 2934 2935 /* 2936 * Reject interface creation if sniffer mode is active, as 2937 * STA operation is mutually exclusive with hardware sniffer 2938 * mode. 2939 */ 2940 if (priv->sniffer_enabled) { 2941 printk(KERN_INFO "%s: unable to create STA " 2942 "interface due to sniffer mode being enabled\n", 2943 wiphy_name(hw->wiphy)); 2944 return -EINVAL; 2945 } 2946 2947 /* Set the mac address. */ 2948 mwl8k_cmd_set_mac_addr(hw, vif->addr); 2949 2950 /* Clean out driver private area */ 2951 mwl8k_vif = MWL8K_VIF(vif); 2952 memset(mwl8k_vif, 0, sizeof(*mwl8k_vif)); 2953 2954 /* Set Initial sequence number to zero */ 2955 mwl8k_vif->seqno = 0; 2956 2957 priv->vif = vif; 2958 priv->current_channel = NULL; 2959 2960 return 0; 2961} 2962 2963static void mwl8k_remove_interface(struct ieee80211_hw *hw, 2964 struct ieee80211_vif *vif) 2965{ 2966 struct mwl8k_priv *priv = hw->priv; 2967 2968 mwl8k_cmd_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00"); 2969 2970 priv->vif = NULL; 2971} 2972 2973static int mwl8k_config(struct ieee80211_hw *hw, u32 changed) 2974{ 2975 struct ieee80211_conf *conf = &hw->conf; 2976 struct mwl8k_priv *priv = hw->priv; 2977 int rc; 2978 2979 if (conf->flags & IEEE80211_CONF_IDLE) { 2980 mwl8k_cmd_radio_disable(hw); 2981 priv->current_channel = NULL; 2982 return 0; 2983 } 2984 2985 rc = mwl8k_fw_lock(hw); 2986 if (rc) 2987 return rc; 2988 2989 rc = mwl8k_cmd_radio_enable(hw); 2990 if (rc) 2991 goto out; 2992 2993 rc = mwl8k_cmd_set_rf_channel(hw, conf); 2994 if (rc) 2995 goto out; 2996 2997 priv->current_channel = conf->channel; 2998 2999 if (conf->power_level > 18) 3000 conf->power_level = 18; 3001 rc = mwl8k_cmd_rf_tx_power(hw, conf->power_level); 3002 if (rc) 3003 goto out; 3004 3005 if (priv->ap_fw) { 3006 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_RX, 0x7); 3007 if (!rc) 3008 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_TX, 0x7); 3009 } else { 3010 rc = mwl8k_cmd_mimo_config(hw, 0x7, 0x7); 3011 } 3012 3013out: 3014 mwl8k_fw_unlock(hw); 3015 3016 return rc; 3017} 3018 3019static void mwl8k_bss_info_changed(struct ieee80211_hw *hw, 3020 struct ieee80211_vif *vif, 3021 struct ieee80211_bss_conf *info, 3022 u32 changed) 3023{ 3024 struct mwl8k_priv *priv = hw->priv; 3025 u32 ap_legacy_rates; 3026 u8 ap_mcs_rates[16]; 3027 int rc; 3028 3029 if (mwl8k_fw_lock(hw)) 3030 return; 3031 3032 /* 3033 * No need to capture a beacon if we're no longer associated. 3034 */ 3035 if ((changed & BSS_CHANGED_ASSOC) && !vif->bss_conf.assoc) 3036 priv->capture_beacon = false; 3037 3038 /* 3039 * Get the AP's legacy and MCS rates. 3040 */ 3041 ap_legacy_rates = 0; 3042 if (vif->bss_conf.assoc) { 3043 struct ieee80211_sta *ap; 3044 rcu_read_lock(); 3045 3046 ap = ieee80211_find_sta(vif, vif->bss_conf.bssid); 3047 if (ap == NULL) { 3048 rcu_read_unlock(); 3049 goto out; 3050 } 3051 3052 ap_legacy_rates = ap->supp_rates[IEEE80211_BAND_2GHZ]; 3053 memcpy(ap_mcs_rates, ap->ht_cap.mcs.rx_mask, 16); 3054 3055 rcu_read_unlock(); 3056 } 3057 3058 if ((changed & BSS_CHANGED_ASSOC) && vif->bss_conf.assoc) { 3059 rc = mwl8k_cmd_set_rate(hw, vif, ap_legacy_rates, ap_mcs_rates); 3060 if (rc) 3061 goto out; 3062 3063 rc = mwl8k_cmd_use_fixed_rate_sta(hw); 3064 if (rc) 3065 goto out; 3066 } 3067 3068 if (changed & BSS_CHANGED_ERP_PREAMBLE) { 3069 rc = mwl8k_set_radio_preamble(hw, 3070 vif->bss_conf.use_short_preamble); 3071 if (rc) 3072 goto out; 3073 } 3074 3075 if (changed & BSS_CHANGED_ERP_SLOT) { 3076 rc = mwl8k_cmd_set_slot(hw, vif->bss_conf.use_short_slot); 3077 if (rc) 3078 goto out; 3079 } 3080 3081 if (((changed & BSS_CHANGED_ASSOC) && vif->bss_conf.assoc) || 3082 (changed & (BSS_CHANGED_ERP_CTS_PROT | BSS_CHANGED_HT))) { 3083 rc = mwl8k_cmd_set_aid(hw, vif, ap_legacy_rates); 3084 if (rc) 3085 goto out; 3086 } 3087 3088 if (vif->bss_conf.assoc && 3089 (changed & (BSS_CHANGED_ASSOC | BSS_CHANGED_BEACON_INT))) { 3090 /* 3091 * Finalize the join. Tell rx handler to process 3092 * next beacon from our BSSID. 3093 */ 3094 memcpy(priv->capture_bssid, vif->bss_conf.bssid, ETH_ALEN); 3095 priv->capture_beacon = true; 3096 } 3097 3098out: 3099 mwl8k_fw_unlock(hw); 3100} 3101 3102static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw, 3103 int mc_count, struct dev_addr_list *mclist) 3104{ 3105 struct mwl8k_cmd_pkt *cmd; 3106 3107 /* 3108 * Synthesize and return a command packet that programs the 3109 * hardware multicast address filter. At this point we don't 3110 * know whether FIF_ALLMULTI is being requested, but if it is, 3111 * we'll end up throwing this packet away and creating a new 3112 * one in mwl8k_configure_filter(). 3113 */ 3114 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 0, mc_count, mclist); 3115 3116 return (unsigned long)cmd; 3117} 3118 3119static int 3120mwl8k_configure_filter_sniffer(struct ieee80211_hw *hw, 3121 unsigned int changed_flags, 3122 unsigned int *total_flags) 3123{ 3124 struct mwl8k_priv *priv = hw->priv; 3125 3126 /* 3127 * Hardware sniffer mode is mutually exclusive with STA 3128 * operation, so refuse to enable sniffer mode if a STA 3129 * interface is active. 3130 */ 3131 if (priv->vif != NULL) { 3132 if (net_ratelimit()) 3133 printk(KERN_INFO "%s: not enabling sniffer " 3134 "mode because STA interface is active\n", 3135 wiphy_name(hw->wiphy)); 3136 return 0; 3137 } 3138 3139 if (!priv->sniffer_enabled) { 3140 if (mwl8k_cmd_enable_sniffer(hw, 1)) 3141 return 0; 3142 priv->sniffer_enabled = true; 3143 } 3144 3145 *total_flags &= FIF_PROMISC_IN_BSS | FIF_ALLMULTI | 3146 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL | 3147 FIF_OTHER_BSS; 3148 3149 return 1; 3150} 3151 3152static void mwl8k_configure_filter(struct ieee80211_hw *hw, 3153 unsigned int changed_flags, 3154 unsigned int *total_flags, 3155 u64 multicast) 3156{ 3157 struct mwl8k_priv *priv = hw->priv; 3158 struct mwl8k_cmd_pkt *cmd = (void *)(unsigned long)multicast; 3159 3160 /* 3161 * AP firmware doesn't allow fine-grained control over 3162 * the receive filter. 3163 */ 3164 if (priv->ap_fw) { 3165 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC; 3166 kfree(cmd); 3167 return; 3168 } 3169 3170 /* 3171 * Enable hardware sniffer mode if FIF_CONTROL or 3172 * FIF_OTHER_BSS is requested. 3173 */ 3174 if (*total_flags & (FIF_CONTROL | FIF_OTHER_BSS) && 3175 mwl8k_configure_filter_sniffer(hw, changed_flags, total_flags)) { 3176 kfree(cmd); 3177 return; 3178 } 3179 3180 /* Clear unsupported feature flags */ 3181 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC; 3182 3183 if (mwl8k_fw_lock(hw)) { 3184 kfree(cmd); 3185 return; 3186 } 3187 3188 if (priv->sniffer_enabled) { 3189 mwl8k_cmd_enable_sniffer(hw, 0); 3190 priv->sniffer_enabled = false; 3191 } 3192 3193 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) { 3194 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) { 3195 /* 3196 * Disable the BSS filter. 3197 */ 3198 mwl8k_cmd_set_pre_scan(hw); 3199 } else { 3200 const u8 *bssid; 3201 3202 /* 3203 * Enable the BSS filter. 3204 * 3205 * If there is an active STA interface, use that 3206 * interface's BSSID, otherwise use a dummy one 3207 * (where the OUI part needs to be nonzero for 3208 * the BSSID to be accepted by POST_SCAN). 3209 */ 3210 bssid = "\x01\x00\x00\x00\x00\x00"; 3211 if (priv->vif != NULL) 3212 bssid = priv->vif->bss_conf.bssid; 3213 3214 mwl8k_cmd_set_post_scan(hw, bssid); 3215 } 3216 } 3217 3218 /* 3219 * If FIF_ALLMULTI is being requested, throw away the command 3220 * packet that ->prepare_multicast() built and replace it with 3221 * a command packet that enables reception of all multicast 3222 * packets. 3223 */ 3224 if (*total_flags & FIF_ALLMULTI) { 3225 kfree(cmd); 3226 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 1, 0, NULL); 3227 } 3228 3229 if (cmd != NULL) { 3230 mwl8k_post_cmd(hw, cmd); 3231 kfree(cmd); 3232 } 3233 3234 mwl8k_fw_unlock(hw); 3235} 3236 3237static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value) 3238{ 3239 return mwl8k_cmd_set_rts_threshold(hw, value); 3240} 3241 3242struct mwl8k_sta_notify_item 3243{ 3244 struct list_head list; 3245 struct ieee80211_vif *vif; 3246 enum sta_notify_cmd cmd; 3247 struct ieee80211_sta sta; 3248}; 3249 3250static void mwl8k_sta_notify_worker(struct work_struct *work) 3251{ 3252 struct mwl8k_priv *priv = 3253 container_of(work, struct mwl8k_priv, sta_notify_worker); 3254 struct ieee80211_hw *hw = priv->hw; 3255 3256 spin_lock_bh(&priv->sta_notify_list_lock); 3257 while (!list_empty(&priv->sta_notify_list)) { 3258 struct mwl8k_sta_notify_item *s; 3259 3260 s = list_entry(priv->sta_notify_list.next, 3261 struct mwl8k_sta_notify_item, list); 3262 list_del(&s->list); 3263 3264 spin_unlock_bh(&priv->sta_notify_list_lock); 3265 3266 if (s->cmd == STA_NOTIFY_ADD) { 3267 int rc; 3268 3269 rc = mwl8k_cmd_update_stadb_add(hw, s->vif, &s->sta); 3270 if (rc >= 0) { 3271 struct ieee80211_sta *sta; 3272 3273 rcu_read_lock(); 3274 sta = ieee80211_find_sta(s->vif, s->sta.addr); 3275 if (sta != NULL) 3276 MWL8K_STA(sta)->peer_id = rc; 3277 rcu_read_unlock(); 3278 } 3279 } else { 3280 mwl8k_cmd_update_stadb_del(hw, s->vif, s->sta.addr); 3281 } 3282 3283 kfree(s); 3284 3285 spin_lock_bh(&priv->sta_notify_list_lock); 3286 } 3287 spin_unlock_bh(&priv->sta_notify_list_lock); 3288} 3289 3290static void 3291mwl8k_sta_notify(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 3292 enum sta_notify_cmd cmd, struct ieee80211_sta *sta) 3293{ 3294 struct mwl8k_priv *priv = hw->priv; 3295 struct mwl8k_sta_notify_item *s; 3296 3297 if (cmd != STA_NOTIFY_ADD && cmd != STA_NOTIFY_REMOVE) 3298 return; 3299 3300 s = kmalloc(sizeof(*s), GFP_ATOMIC); 3301 if (s != NULL) { 3302 s->vif = vif; 3303 s->cmd = cmd; 3304 s->sta = *sta; 3305 3306 spin_lock(&priv->sta_notify_list_lock); 3307 list_add_tail(&s->list, &priv->sta_notify_list); 3308 spin_unlock(&priv->sta_notify_list_lock); 3309 3310 ieee80211_queue_work(hw, &priv->sta_notify_worker); 3311 } 3312} 3313 3314static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue, 3315 const struct ieee80211_tx_queue_params *params) 3316{ 3317 struct mwl8k_priv *priv = hw->priv; 3318 int rc; 3319 3320 rc = mwl8k_fw_lock(hw); 3321 if (!rc) { 3322 if (!priv->wmm_enabled) 3323 rc = mwl8k_cmd_set_wmm_mode(hw, 1); 3324 3325 if (!rc) 3326 rc = mwl8k_cmd_set_edca_params(hw, queue, 3327 params->cw_min, 3328 params->cw_max, 3329 params->aifs, 3330 params->txop); 3331 3332 mwl8k_fw_unlock(hw); 3333 } 3334 3335 return rc; 3336} 3337 3338static int mwl8k_get_tx_stats(struct ieee80211_hw *hw, 3339 struct ieee80211_tx_queue_stats *stats) 3340{ 3341 struct mwl8k_priv *priv = hw->priv; 3342 struct mwl8k_tx_queue *txq; 3343 int index; 3344 3345 spin_lock_bh(&priv->tx_lock); 3346 for (index = 0; index < MWL8K_TX_QUEUES; index++) { 3347 txq = priv->txq + index; 3348 memcpy(&stats[index], &txq->stats, 3349 sizeof(struct ieee80211_tx_queue_stats)); 3350 } 3351 spin_unlock_bh(&priv->tx_lock); 3352 3353 return 0; 3354} 3355 3356static int mwl8k_get_stats(struct ieee80211_hw *hw, 3357 struct ieee80211_low_level_stats *stats) 3358{ 3359 return mwl8k_cmd_get_stat(hw, stats); 3360} 3361 3362static int 3363mwl8k_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 3364 enum ieee80211_ampdu_mlme_action action, 3365 struct ieee80211_sta *sta, u16 tid, u16 *ssn) 3366{ 3367 switch (action) { 3368 case IEEE80211_AMPDU_RX_START: 3369 case IEEE80211_AMPDU_RX_STOP: 3370 if (!(hw->flags & IEEE80211_HW_AMPDU_AGGREGATION)) 3371 return -ENOTSUPP; 3372 return 0; 3373 default: 3374 return -ENOTSUPP; 3375 } 3376} 3377 3378static const struct ieee80211_ops mwl8k_ops = { 3379 .tx = mwl8k_tx, 3380 .start = mwl8k_start, 3381 .stop = mwl8k_stop, 3382 .add_interface = mwl8k_add_interface, 3383 .remove_interface = mwl8k_remove_interface, 3384 .config = mwl8k_config, 3385 .bss_info_changed = mwl8k_bss_info_changed, 3386 .prepare_multicast = mwl8k_prepare_multicast, 3387 .configure_filter = mwl8k_configure_filter, 3388 .set_rts_threshold = mwl8k_set_rts_threshold, 3389 .sta_notify = mwl8k_sta_notify, 3390 .conf_tx = mwl8k_conf_tx, 3391 .get_tx_stats = mwl8k_get_tx_stats, 3392 .get_stats = mwl8k_get_stats, 3393 .ampdu_action = mwl8k_ampdu_action, 3394}; 3395 3396static void mwl8k_tx_reclaim_handler(unsigned long data) 3397{ 3398 int i; 3399 struct ieee80211_hw *hw = (struct ieee80211_hw *) data; 3400 struct mwl8k_priv *priv = hw->priv; 3401 3402 spin_lock_bh(&priv->tx_lock); 3403 for (i = 0; i < MWL8K_TX_QUEUES; i++) 3404 mwl8k_txq_reclaim(hw, i, 0); 3405 3406 if (priv->tx_wait != NULL && !priv->pending_tx_pkts) { 3407 complete(priv->tx_wait); 3408 priv->tx_wait = NULL; 3409 } 3410 spin_unlock_bh(&priv->tx_lock); 3411} 3412 3413static void mwl8k_finalize_join_worker(struct work_struct *work) 3414{ 3415 struct mwl8k_priv *priv = 3416 container_of(work, struct mwl8k_priv, finalize_join_worker); 3417 struct sk_buff *skb = priv->beacon_skb; 3418 3419 mwl8k_cmd_finalize_join(priv->hw, skb->data, skb->len, 3420 priv->vif->bss_conf.dtim_period); 3421 dev_kfree_skb(skb); 3422 3423 priv->beacon_skb = NULL; 3424} 3425 3426enum { 3427 MWL8363 = 0, 3428 MWL8687, 3429 MWL8366, 3430}; 3431 3432static struct mwl8k_device_info mwl8k_info_tbl[] __devinitdata = { 3433 [MWL8363] = { 3434 .part_name = "88w8363", 3435 .helper_image = "mwl8k/helper_8363.fw", 3436 .fw_image = "mwl8k/fmimage_8363.fw", 3437 }, 3438 [MWL8687] = { 3439 .part_name = "88w8687", 3440 .helper_image = "mwl8k/helper_8687.fw", 3441 .fw_image = "mwl8k/fmimage_8687.fw", 3442 }, 3443 [MWL8366] = { 3444 .part_name = "88w8366", 3445 .helper_image = "mwl8k/helper_8366.fw", 3446 .fw_image = "mwl8k/fmimage_8366.fw", 3447 .ap_rxd_ops = &rxd_8366_ap_ops, 3448 }, 3449}; 3450 3451static DEFINE_PCI_DEVICE_TABLE(mwl8k_pci_id_table) = { 3452 { PCI_VDEVICE(MARVELL, 0x2a0c), .driver_data = MWL8363, }, 3453 { PCI_VDEVICE(MARVELL, 0x2a24), .driver_data = MWL8363, }, 3454 { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = MWL8687, }, 3455 { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = MWL8687, }, 3456 { PCI_VDEVICE(MARVELL, 0x2a40), .driver_data = MWL8366, }, 3457 { }, 3458}; 3459MODULE_DEVICE_TABLE(pci, mwl8k_pci_id_table); 3460 3461static int __devinit mwl8k_probe(struct pci_dev *pdev, 3462 const struct pci_device_id *id) 3463{ 3464 static int printed_version = 0; 3465 struct ieee80211_hw *hw; 3466 struct mwl8k_priv *priv; 3467 int rc; 3468 int i; 3469 3470 if (!printed_version) { 3471 printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION); 3472 printed_version = 1; 3473 } 3474 3475 3476 rc = pci_enable_device(pdev); 3477 if (rc) { 3478 printk(KERN_ERR "%s: Cannot enable new PCI device\n", 3479 MWL8K_NAME); 3480 return rc; 3481 } 3482 3483 rc = pci_request_regions(pdev, MWL8K_NAME); 3484 if (rc) { 3485 printk(KERN_ERR "%s: Cannot obtain PCI resources\n", 3486 MWL8K_NAME); 3487 goto err_disable_device; 3488 } 3489 3490 pci_set_master(pdev); 3491 3492 3493 hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops); 3494 if (hw == NULL) { 3495 printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME); 3496 rc = -ENOMEM; 3497 goto err_free_reg; 3498 } 3499 3500 SET_IEEE80211_DEV(hw, &pdev->dev); 3501 pci_set_drvdata(pdev, hw); 3502 3503 priv = hw->priv; 3504 priv->hw = hw; 3505 priv->pdev = pdev; 3506 priv->device_info = &mwl8k_info_tbl[id->driver_data]; 3507 3508 3509 priv->sram = pci_iomap(pdev, 0, 0x10000); 3510 if (priv->sram == NULL) { 3511 printk(KERN_ERR "%s: Cannot map device SRAM\n", 3512 wiphy_name(hw->wiphy)); 3513 goto err_iounmap; 3514 } 3515 3516 /* 3517 * If BAR0 is a 32 bit BAR, the register BAR will be BAR1. 3518 * If BAR0 is a 64 bit BAR, the register BAR will be BAR2. 3519 */ 3520 priv->regs = pci_iomap(pdev, 1, 0x10000); 3521 if (priv->regs == NULL) { 3522 priv->regs = pci_iomap(pdev, 2, 0x10000); 3523 if (priv->regs == NULL) { 3524 printk(KERN_ERR "%s: Cannot map device registers\n", 3525 wiphy_name(hw->wiphy)); 3526 goto err_iounmap; 3527 } 3528 } 3529 3530 3531 /* Reset firmware and hardware */ 3532 mwl8k_hw_reset(priv); 3533 3534 /* Ask userland hotplug daemon for the device firmware */ 3535 rc = mwl8k_request_firmware(priv); 3536 if (rc) { 3537 printk(KERN_ERR "%s: Firmware files not found\n", 3538 wiphy_name(hw->wiphy)); 3539 goto err_stop_firmware; 3540 } 3541 3542 /* Load firmware into hardware */ 3543 rc = mwl8k_load_firmware(hw); 3544 if (rc) { 3545 printk(KERN_ERR "%s: Cannot start firmware\n", 3546 wiphy_name(hw->wiphy)); 3547 goto err_stop_firmware; 3548 } 3549 3550 /* Reclaim memory once firmware is successfully loaded */ 3551 mwl8k_release_firmware(priv); 3552 3553 3554 if (priv->ap_fw) { 3555 priv->rxd_ops = priv->device_info->ap_rxd_ops; 3556 if (priv->rxd_ops == NULL) { 3557 printk(KERN_ERR "%s: Driver does not have AP " 3558 "firmware image support for this hardware\n", 3559 wiphy_name(hw->wiphy)); 3560 goto err_stop_firmware; 3561 } 3562 } else { 3563 priv->rxd_ops = &rxd_sta_ops; 3564 } 3565 3566 priv->sniffer_enabled = false; 3567 priv->wmm_enabled = false; 3568 priv->pending_tx_pkts = 0; 3569 3570 3571 memcpy(priv->channels, mwl8k_channels, sizeof(mwl8k_channels)); 3572 priv->band.band = IEEE80211_BAND_2GHZ; 3573 priv->band.channels = priv->channels; 3574 priv->band.n_channels = ARRAY_SIZE(mwl8k_channels); 3575 priv->band.bitrates = priv->rates; 3576 priv->band.n_bitrates = ARRAY_SIZE(mwl8k_rates); 3577 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band; 3578 3579 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(mwl8k_rates)); 3580 memcpy(priv->rates, mwl8k_rates, sizeof(mwl8k_rates)); 3581 3582 /* 3583 * Extra headroom is the size of the required DMA header 3584 * minus the size of the smallest 802.11 frame (CTS frame). 3585 */ 3586 hw->extra_tx_headroom = 3587 sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts); 3588 3589 hw->channel_change_time = 10; 3590 3591 hw->queues = MWL8K_TX_QUEUES; 3592 3593 /* Set rssi and noise values to dBm */ 3594 hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_NOISE_DBM; 3595 hw->vif_data_size = sizeof(struct mwl8k_vif); 3596 hw->sta_data_size = sizeof(struct mwl8k_sta); 3597 priv->vif = NULL; 3598 3599 /* Set default radio state and preamble */ 3600 priv->radio_on = 0; 3601 priv->radio_short_preamble = 0; 3602 3603 /* Station database handling */ 3604 INIT_WORK(&priv->sta_notify_worker, mwl8k_sta_notify_worker); 3605 spin_lock_init(&priv->sta_notify_list_lock); 3606 INIT_LIST_HEAD(&priv->sta_notify_list); 3607 3608 /* Finalize join worker */ 3609 INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker); 3610 3611 /* TX reclaim tasklet */ 3612 tasklet_init(&priv->tx_reclaim_task, 3613 mwl8k_tx_reclaim_handler, (unsigned long)hw); 3614 tasklet_disable(&priv->tx_reclaim_task); 3615 3616 /* Power management cookie */ 3617 priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma); 3618 if (priv->cookie == NULL) 3619 goto err_stop_firmware; 3620 3621 rc = mwl8k_rxq_init(hw, 0); 3622 if (rc) 3623 goto err_free_cookie; 3624 rxq_refill(hw, 0, INT_MAX); 3625 3626 mutex_init(&priv->fw_mutex); 3627 priv->fw_mutex_owner = NULL; 3628 priv->fw_mutex_depth = 0; 3629 priv->hostcmd_wait = NULL; 3630 3631 spin_lock_init(&priv->tx_lock); 3632 3633 priv->tx_wait = NULL; 3634 3635 for (i = 0; i < MWL8K_TX_QUEUES; i++) { 3636 rc = mwl8k_txq_init(hw, i); 3637 if (rc) 3638 goto err_free_queues; 3639 } 3640 3641 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS); 3642 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK); 3643 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL); 3644 iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK); 3645 3646 rc = request_irq(priv->pdev->irq, mwl8k_interrupt, 3647 IRQF_SHARED, MWL8K_NAME, hw); 3648 if (rc) { 3649 printk(KERN_ERR "%s: failed to register IRQ handler\n", 3650 wiphy_name(hw->wiphy)); 3651 goto err_free_queues; 3652 } 3653 3654 /* 3655 * Temporarily enable interrupts. Initial firmware host 3656 * commands use interrupts and avoid polling. Disable 3657 * interrupts when done. 3658 */ 3659 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK); 3660 3661 /* Get config data, mac addrs etc */ 3662 if (priv->ap_fw) { 3663 rc = mwl8k_cmd_get_hw_spec_ap(hw); 3664 if (!rc) 3665 rc = mwl8k_cmd_set_hw_spec(hw); 3666 } else { 3667 rc = mwl8k_cmd_get_hw_spec_sta(hw); 3668 3669 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION); 3670 } 3671 if (rc) { 3672 printk(KERN_ERR "%s: Cannot initialise firmware\n", 3673 wiphy_name(hw->wiphy)); 3674 goto err_free_irq; 3675 } 3676 3677 /* Turn radio off */ 3678 rc = mwl8k_cmd_radio_disable(hw); 3679 if (rc) { 3680 printk(KERN_ERR "%s: Cannot disable\n", wiphy_name(hw->wiphy)); 3681 goto err_free_irq; 3682 } 3683 3684 /* Clear MAC address */ 3685 rc = mwl8k_cmd_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00"); 3686 if (rc) { 3687 printk(KERN_ERR "%s: Cannot clear MAC address\n", 3688 wiphy_name(hw->wiphy)); 3689 goto err_free_irq; 3690 } 3691 3692 /* Disable interrupts */ 3693 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK); 3694 free_irq(priv->pdev->irq, hw); 3695 3696 rc = ieee80211_register_hw(hw); 3697 if (rc) { 3698 printk(KERN_ERR "%s: Cannot register device\n", 3699 wiphy_name(hw->wiphy)); 3700 goto err_free_queues; 3701 } 3702 3703 printk(KERN_INFO "%s: %s v%d, %pM, %s firmware %u.%u.%u.%u\n", 3704 wiphy_name(hw->wiphy), priv->device_info->part_name, 3705 priv->hw_rev, hw->wiphy->perm_addr, 3706 priv->ap_fw ? "AP" : "STA", 3707 (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff, 3708 (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff); 3709 3710 return 0; 3711 3712err_free_irq: 3713 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK); 3714 free_irq(priv->pdev->irq, hw); 3715 3716err_free_queues: 3717 for (i = 0; i < MWL8K_TX_QUEUES; i++) 3718 mwl8k_txq_deinit(hw, i); 3719 mwl8k_rxq_deinit(hw, 0); 3720 3721err_free_cookie: 3722 if (priv->cookie != NULL) 3723 pci_free_consistent(priv->pdev, 4, 3724 priv->cookie, priv->cookie_dma); 3725 3726err_stop_firmware: 3727 mwl8k_hw_reset(priv); 3728 mwl8k_release_firmware(priv); 3729 3730err_iounmap: 3731 if (priv->regs != NULL) 3732 pci_iounmap(pdev, priv->regs); 3733 3734 if (priv->sram != NULL) 3735 pci_iounmap(pdev, priv->sram); 3736 3737 pci_set_drvdata(pdev, NULL); 3738 ieee80211_free_hw(hw); 3739 3740err_free_reg: 3741 pci_release_regions(pdev); 3742 3743err_disable_device: 3744 pci_disable_device(pdev); 3745 3746 return rc; 3747} 3748 3749static void __devexit mwl8k_shutdown(struct pci_dev *pdev) 3750{ 3751 printk(KERN_ERR "===>%s(%u)\n", __func__, __LINE__); 3752} 3753 3754static void __devexit mwl8k_remove(struct pci_dev *pdev) 3755{ 3756 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 3757 struct mwl8k_priv *priv; 3758 int i; 3759 3760 if (hw == NULL) 3761 return; 3762 priv = hw->priv; 3763 3764 ieee80211_stop_queues(hw); 3765 3766 ieee80211_unregister_hw(hw); 3767 3768 /* Remove tx reclaim tasklet */ 3769 tasklet_kill(&priv->tx_reclaim_task); 3770 3771 /* Stop hardware */ 3772 mwl8k_hw_reset(priv); 3773 3774 /* Return all skbs to mac80211 */ 3775 for (i = 0; i < MWL8K_TX_QUEUES; i++) 3776 mwl8k_txq_reclaim(hw, i, 1); 3777 3778 for (i = 0; i < MWL8K_TX_QUEUES; i++) 3779 mwl8k_txq_deinit(hw, i); 3780 3781 mwl8k_rxq_deinit(hw, 0); 3782 3783 pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma); 3784 3785 pci_iounmap(pdev, priv->regs); 3786 pci_iounmap(pdev, priv->sram); 3787 pci_set_drvdata(pdev, NULL); 3788 ieee80211_free_hw(hw); 3789 pci_release_regions(pdev); 3790 pci_disable_device(pdev); 3791} 3792 3793static struct pci_driver mwl8k_driver = { 3794 .name = MWL8K_NAME, 3795 .id_table = mwl8k_pci_id_table, 3796 .probe = mwl8k_probe, 3797 .remove = __devexit_p(mwl8k_remove), 3798 .shutdown = __devexit_p(mwl8k_shutdown), 3799}; 3800 3801static int __init mwl8k_init(void) 3802{ 3803 return pci_register_driver(&mwl8k_driver); 3804} 3805 3806static void __exit mwl8k_exit(void) 3807{ 3808 pci_unregister_driver(&mwl8k_driver); 3809} 3810 3811module_init(mwl8k_init); 3812module_exit(mwl8k_exit); 3813 3814MODULE_DESCRIPTION(MWL8K_DESC); 3815MODULE_VERSION(MWL8K_VERSION); 3816MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>"); 3817MODULE_LICENSE("GPL"); 3818