mwl8k.c revision 7dc6a7a7635365b140af969e972900866d0bf34b
1/* 2 * drivers/net/wireless/mwl8k.c 3 * Driver for Marvell TOPDOG 802.11 Wireless cards 4 * 5 * Copyright (C) 2008-2009 Marvell Semiconductor Inc. 6 * 7 * This file is licensed under the terms of the GNU General Public 8 * License version 2. This program is licensed "as is" without any 9 * warranty of any kind, whether express or implied. 10 */ 11 12#include <linux/init.h> 13#include <linux/module.h> 14#include <linux/kernel.h> 15#include <linux/sched.h> 16#include <linux/spinlock.h> 17#include <linux/list.h> 18#include <linux/pci.h> 19#include <linux/delay.h> 20#include <linux/completion.h> 21#include <linux/etherdevice.h> 22#include <net/mac80211.h> 23#include <linux/moduleparam.h> 24#include <linux/firmware.h> 25#include <linux/workqueue.h> 26 27#define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver" 28#define MWL8K_NAME KBUILD_MODNAME 29#define MWL8K_VERSION "0.10" 30 31/* Register definitions */ 32#define MWL8K_HIU_GEN_PTR 0x00000c10 33#define MWL8K_MODE_STA 0x0000005a 34#define MWL8K_MODE_AP 0x000000a5 35#define MWL8K_HIU_INT_CODE 0x00000c14 36#define MWL8K_FWSTA_READY 0xf0f1f2f4 37#define MWL8K_FWAP_READY 0xf1f2f4a5 38#define MWL8K_INT_CODE_CMD_FINISHED 0x00000005 39#define MWL8K_HIU_SCRATCH 0x00000c40 40 41/* Host->device communications */ 42#define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18 43#define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c 44#define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20 45#define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24 46#define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28 47#define MWL8K_H2A_INT_DUMMY (1 << 20) 48#define MWL8K_H2A_INT_RESET (1 << 15) 49#define MWL8K_H2A_INT_DOORBELL (1 << 1) 50#define MWL8K_H2A_INT_PPA_READY (1 << 0) 51 52/* Device->host communications */ 53#define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c 54#define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30 55#define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34 56#define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38 57#define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c 58#define MWL8K_A2H_INT_DUMMY (1 << 20) 59#define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11) 60#define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10) 61#define MWL8K_A2H_INT_RADAR_DETECT (1 << 7) 62#define MWL8K_A2H_INT_RADIO_ON (1 << 6) 63#define MWL8K_A2H_INT_RADIO_OFF (1 << 5) 64#define MWL8K_A2H_INT_MAC_EVENT (1 << 3) 65#define MWL8K_A2H_INT_OPC_DONE (1 << 2) 66#define MWL8K_A2H_INT_RX_READY (1 << 1) 67#define MWL8K_A2H_INT_TX_DONE (1 << 0) 68 69#define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \ 70 MWL8K_A2H_INT_CHNL_SWITCHED | \ 71 MWL8K_A2H_INT_QUEUE_EMPTY | \ 72 MWL8K_A2H_INT_RADAR_DETECT | \ 73 MWL8K_A2H_INT_RADIO_ON | \ 74 MWL8K_A2H_INT_RADIO_OFF | \ 75 MWL8K_A2H_INT_MAC_EVENT | \ 76 MWL8K_A2H_INT_OPC_DONE | \ 77 MWL8K_A2H_INT_RX_READY | \ 78 MWL8K_A2H_INT_TX_DONE) 79 80#define MWL8K_RX_QUEUES 1 81#define MWL8K_TX_QUEUES 4 82 83struct rxd_ops { 84 int rxd_size; 85 void (*rxd_init)(void *rxd, dma_addr_t next_dma_addr); 86 void (*rxd_refill)(void *rxd, dma_addr_t addr, int len); 87 int (*rxd_process)(void *rxd, struct ieee80211_rx_status *status, 88 __le16 *qos); 89}; 90 91struct mwl8k_device_info { 92 char *part_name; 93 char *helper_image; 94 char *fw_image; 95 struct rxd_ops *ap_rxd_ops; 96}; 97 98struct mwl8k_rx_queue { 99 int rxd_count; 100 101 /* hw receives here */ 102 int head; 103 104 /* refill descs here */ 105 int tail; 106 107 void *rxd; 108 dma_addr_t rxd_dma; 109 struct { 110 struct sk_buff *skb; 111 DECLARE_PCI_UNMAP_ADDR(dma) 112 } *buf; 113}; 114 115struct mwl8k_tx_queue { 116 /* hw transmits here */ 117 int head; 118 119 /* sw appends here */ 120 int tail; 121 122 struct ieee80211_tx_queue_stats stats; 123 struct mwl8k_tx_desc *txd; 124 dma_addr_t txd_dma; 125 struct sk_buff **skb; 126}; 127 128struct mwl8k_priv { 129 struct ieee80211_hw *hw; 130 struct pci_dev *pdev; 131 132 struct mwl8k_device_info *device_info; 133 134 void __iomem *sram; 135 void __iomem *regs; 136 137 /* firmware */ 138 struct firmware *fw_helper; 139 struct firmware *fw_ucode; 140 141 /* hardware/firmware parameters */ 142 bool ap_fw; 143 struct rxd_ops *rxd_ops; 144 145 /* firmware access */ 146 struct mutex fw_mutex; 147 struct task_struct *fw_mutex_owner; 148 int fw_mutex_depth; 149 struct completion *hostcmd_wait; 150 151 /* lock held over TX and TX reap */ 152 spinlock_t tx_lock; 153 154 /* TX quiesce completion, protected by fw_mutex and tx_lock */ 155 struct completion *tx_wait; 156 157 struct ieee80211_vif *vif; 158 159 struct ieee80211_channel *current_channel; 160 161 /* power management status cookie from firmware */ 162 u32 *cookie; 163 dma_addr_t cookie_dma; 164 165 u16 num_mcaddrs; 166 u8 hw_rev; 167 u32 fw_rev; 168 169 /* 170 * Running count of TX packets in flight, to avoid 171 * iterating over the transmit rings each time. 172 */ 173 int pending_tx_pkts; 174 175 struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES]; 176 struct mwl8k_tx_queue txq[MWL8K_TX_QUEUES]; 177 178 /* PHY parameters */ 179 struct ieee80211_supported_band band; 180 struct ieee80211_channel channels[14]; 181 struct ieee80211_rate rates[14]; 182 183 bool radio_on; 184 bool radio_short_preamble; 185 bool sniffer_enabled; 186 bool wmm_enabled; 187 188 /* XXX need to convert this to handle multiple interfaces */ 189 bool capture_beacon; 190 u8 capture_bssid[ETH_ALEN]; 191 struct sk_buff *beacon_skb; 192 193 /* 194 * This FJ worker has to be global as it is scheduled from the 195 * RX handler. At this point we don't know which interface it 196 * belongs to until the list of bssids waiting to complete join 197 * is checked. 198 */ 199 struct work_struct finalize_join_worker; 200 201 /* Tasklet to reclaim TX descriptors and buffers after tx */ 202 struct tasklet_struct tx_reclaim_task; 203}; 204 205/* Per interface specific private data */ 206struct mwl8k_vif { 207 /* Local MAC address. */ 208 u8 mac_addr[ETH_ALEN]; 209 210 /* BSSID of AP. */ 211 u8 bssid[ETH_ALEN]; 212 213 /* Index into station database. Returned by UPDATE_STADB. */ 214 u8 peer_id; 215 216 /* Non AMPDU sequence number assigned by driver */ 217 u16 seqno; 218}; 219 220#define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv)) 221 222static const struct ieee80211_channel mwl8k_channels[] = { 223 { .center_freq = 2412, .hw_value = 1, }, 224 { .center_freq = 2417, .hw_value = 2, }, 225 { .center_freq = 2422, .hw_value = 3, }, 226 { .center_freq = 2427, .hw_value = 4, }, 227 { .center_freq = 2432, .hw_value = 5, }, 228 { .center_freq = 2437, .hw_value = 6, }, 229 { .center_freq = 2442, .hw_value = 7, }, 230 { .center_freq = 2447, .hw_value = 8, }, 231 { .center_freq = 2452, .hw_value = 9, }, 232 { .center_freq = 2457, .hw_value = 10, }, 233 { .center_freq = 2462, .hw_value = 11, }, 234 { .center_freq = 2467, .hw_value = 12, }, 235 { .center_freq = 2472, .hw_value = 13, }, 236 { .center_freq = 2484, .hw_value = 14, }, 237}; 238 239static const struct ieee80211_rate mwl8k_rates[] = { 240 { .bitrate = 10, .hw_value = 2, }, 241 { .bitrate = 20, .hw_value = 4, }, 242 { .bitrate = 55, .hw_value = 11, }, 243 { .bitrate = 110, .hw_value = 22, }, 244 { .bitrate = 220, .hw_value = 44, }, 245 { .bitrate = 60, .hw_value = 12, }, 246 { .bitrate = 90, .hw_value = 18, }, 247 { .bitrate = 120, .hw_value = 24, }, 248 { .bitrate = 180, .hw_value = 36, }, 249 { .bitrate = 240, .hw_value = 48, }, 250 { .bitrate = 360, .hw_value = 72, }, 251 { .bitrate = 480, .hw_value = 96, }, 252 { .bitrate = 540, .hw_value = 108, }, 253 { .bitrate = 720, .hw_value = 144, }, 254}; 255 256static const u8 mwl8k_rateids[12] = { 257 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108, 258}; 259 260/* Set or get info from Firmware */ 261#define MWL8K_CMD_SET 0x0001 262#define MWL8K_CMD_GET 0x0000 263 264/* Firmware command codes */ 265#define MWL8K_CMD_CODE_DNLD 0x0001 266#define MWL8K_CMD_GET_HW_SPEC 0x0003 267#define MWL8K_CMD_SET_HW_SPEC 0x0004 268#define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010 269#define MWL8K_CMD_GET_STAT 0x0014 270#define MWL8K_CMD_RADIO_CONTROL 0x001c 271#define MWL8K_CMD_RF_TX_POWER 0x001e 272#define MWL8K_CMD_RF_ANTENNA 0x0020 273#define MWL8K_CMD_SET_PRE_SCAN 0x0107 274#define MWL8K_CMD_SET_POST_SCAN 0x0108 275#define MWL8K_CMD_SET_RF_CHANNEL 0x010a 276#define MWL8K_CMD_SET_AID 0x010d 277#define MWL8K_CMD_SET_RATE 0x0110 278#define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111 279#define MWL8K_CMD_RTS_THRESHOLD 0x0113 280#define MWL8K_CMD_SET_SLOT 0x0114 281#define MWL8K_CMD_SET_EDCA_PARAMS 0x0115 282#define MWL8K_CMD_SET_WMM_MODE 0x0123 283#define MWL8K_CMD_MIMO_CONFIG 0x0125 284#define MWL8K_CMD_USE_FIXED_RATE 0x0126 285#define MWL8K_CMD_ENABLE_SNIFFER 0x0150 286#define MWL8K_CMD_SET_MAC_ADDR 0x0202 287#define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203 288#define MWL8K_CMD_UPDATE_STADB 0x1123 289 290static const char *mwl8k_cmd_name(u16 cmd, char *buf, int bufsize) 291{ 292#define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\ 293 snprintf(buf, bufsize, "%s", #x);\ 294 return buf;\ 295 } while (0) 296 switch (cmd & ~0x8000) { 297 MWL8K_CMDNAME(CODE_DNLD); 298 MWL8K_CMDNAME(GET_HW_SPEC); 299 MWL8K_CMDNAME(SET_HW_SPEC); 300 MWL8K_CMDNAME(MAC_MULTICAST_ADR); 301 MWL8K_CMDNAME(GET_STAT); 302 MWL8K_CMDNAME(RADIO_CONTROL); 303 MWL8K_CMDNAME(RF_TX_POWER); 304 MWL8K_CMDNAME(RF_ANTENNA); 305 MWL8K_CMDNAME(SET_PRE_SCAN); 306 MWL8K_CMDNAME(SET_POST_SCAN); 307 MWL8K_CMDNAME(SET_RF_CHANNEL); 308 MWL8K_CMDNAME(SET_AID); 309 MWL8K_CMDNAME(SET_RATE); 310 MWL8K_CMDNAME(SET_FINALIZE_JOIN); 311 MWL8K_CMDNAME(RTS_THRESHOLD); 312 MWL8K_CMDNAME(SET_SLOT); 313 MWL8K_CMDNAME(SET_EDCA_PARAMS); 314 MWL8K_CMDNAME(SET_WMM_MODE); 315 MWL8K_CMDNAME(MIMO_CONFIG); 316 MWL8K_CMDNAME(USE_FIXED_RATE); 317 MWL8K_CMDNAME(ENABLE_SNIFFER); 318 MWL8K_CMDNAME(SET_MAC_ADDR); 319 MWL8K_CMDNAME(SET_RATEADAPT_MODE); 320 MWL8K_CMDNAME(UPDATE_STADB); 321 default: 322 snprintf(buf, bufsize, "0x%x", cmd); 323 } 324#undef MWL8K_CMDNAME 325 326 return buf; 327} 328 329/* Hardware and firmware reset */ 330static void mwl8k_hw_reset(struct mwl8k_priv *priv) 331{ 332 iowrite32(MWL8K_H2A_INT_RESET, 333 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); 334 iowrite32(MWL8K_H2A_INT_RESET, 335 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); 336 msleep(20); 337} 338 339/* Release fw image */ 340static void mwl8k_release_fw(struct firmware **fw) 341{ 342 if (*fw == NULL) 343 return; 344 release_firmware(*fw); 345 *fw = NULL; 346} 347 348static void mwl8k_release_firmware(struct mwl8k_priv *priv) 349{ 350 mwl8k_release_fw(&priv->fw_ucode); 351 mwl8k_release_fw(&priv->fw_helper); 352} 353 354/* Request fw image */ 355static int mwl8k_request_fw(struct mwl8k_priv *priv, 356 const char *fname, struct firmware **fw) 357{ 358 /* release current image */ 359 if (*fw != NULL) 360 mwl8k_release_fw(fw); 361 362 return request_firmware((const struct firmware **)fw, 363 fname, &priv->pdev->dev); 364} 365 366static int mwl8k_request_firmware(struct mwl8k_priv *priv) 367{ 368 struct mwl8k_device_info *di = priv->device_info; 369 int rc; 370 371 if (di->helper_image != NULL) { 372 rc = mwl8k_request_fw(priv, di->helper_image, &priv->fw_helper); 373 if (rc) { 374 printk(KERN_ERR "%s: Error requesting helper " 375 "firmware file %s\n", pci_name(priv->pdev), 376 di->helper_image); 377 return rc; 378 } 379 } 380 381 rc = mwl8k_request_fw(priv, di->fw_image, &priv->fw_ucode); 382 if (rc) { 383 printk(KERN_ERR "%s: Error requesting firmware file %s\n", 384 pci_name(priv->pdev), di->fw_image); 385 mwl8k_release_fw(&priv->fw_helper); 386 return rc; 387 } 388 389 return 0; 390} 391 392MODULE_FIRMWARE("mwl8k/helper_8687.fw"); 393MODULE_FIRMWARE("mwl8k/fmimage_8687.fw"); 394 395struct mwl8k_cmd_pkt { 396 __le16 code; 397 __le16 length; 398 __le16 seq_num; 399 __le16 result; 400 char payload[0]; 401} __attribute__((packed)); 402 403/* 404 * Firmware loading. 405 */ 406static int 407mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length) 408{ 409 void __iomem *regs = priv->regs; 410 dma_addr_t dma_addr; 411 int loops; 412 413 dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE); 414 if (pci_dma_mapping_error(priv->pdev, dma_addr)) 415 return -ENOMEM; 416 417 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR); 418 iowrite32(0, regs + MWL8K_HIU_INT_CODE); 419 iowrite32(MWL8K_H2A_INT_DOORBELL, 420 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); 421 iowrite32(MWL8K_H2A_INT_DUMMY, 422 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); 423 424 loops = 1000; 425 do { 426 u32 int_code; 427 428 int_code = ioread32(regs + MWL8K_HIU_INT_CODE); 429 if (int_code == MWL8K_INT_CODE_CMD_FINISHED) { 430 iowrite32(0, regs + MWL8K_HIU_INT_CODE); 431 break; 432 } 433 434 cond_resched(); 435 udelay(1); 436 } while (--loops); 437 438 pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE); 439 440 return loops ? 0 : -ETIMEDOUT; 441} 442 443static int mwl8k_load_fw_image(struct mwl8k_priv *priv, 444 const u8 *data, size_t length) 445{ 446 struct mwl8k_cmd_pkt *cmd; 447 int done; 448 int rc = 0; 449 450 cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL); 451 if (cmd == NULL) 452 return -ENOMEM; 453 454 cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD); 455 cmd->seq_num = 0; 456 cmd->result = 0; 457 458 done = 0; 459 while (length) { 460 int block_size = length > 256 ? 256 : length; 461 462 memcpy(cmd->payload, data + done, block_size); 463 cmd->length = cpu_to_le16(block_size); 464 465 rc = mwl8k_send_fw_load_cmd(priv, cmd, 466 sizeof(*cmd) + block_size); 467 if (rc) 468 break; 469 470 done += block_size; 471 length -= block_size; 472 } 473 474 if (!rc) { 475 cmd->length = 0; 476 rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd)); 477 } 478 479 kfree(cmd); 480 481 return rc; 482} 483 484static int mwl8k_feed_fw_image(struct mwl8k_priv *priv, 485 const u8 *data, size_t length) 486{ 487 unsigned char *buffer; 488 int may_continue, rc = 0; 489 u32 done, prev_block_size; 490 491 buffer = kmalloc(1024, GFP_KERNEL); 492 if (buffer == NULL) 493 return -ENOMEM; 494 495 done = 0; 496 prev_block_size = 0; 497 may_continue = 1000; 498 while (may_continue > 0) { 499 u32 block_size; 500 501 block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH); 502 if (block_size & 1) { 503 block_size &= ~1; 504 may_continue--; 505 } else { 506 done += prev_block_size; 507 length -= prev_block_size; 508 } 509 510 if (block_size > 1024 || block_size > length) { 511 rc = -EOVERFLOW; 512 break; 513 } 514 515 if (length == 0) { 516 rc = 0; 517 break; 518 } 519 520 if (block_size == 0) { 521 rc = -EPROTO; 522 may_continue--; 523 udelay(1); 524 continue; 525 } 526 527 prev_block_size = block_size; 528 memcpy(buffer, data + done, block_size); 529 530 rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size); 531 if (rc) 532 break; 533 } 534 535 if (!rc && length != 0) 536 rc = -EREMOTEIO; 537 538 kfree(buffer); 539 540 return rc; 541} 542 543static int mwl8k_load_firmware(struct ieee80211_hw *hw) 544{ 545 struct mwl8k_priv *priv = hw->priv; 546 struct firmware *fw = priv->fw_ucode; 547 int rc; 548 int loops; 549 550 if (!memcmp(fw->data, "\x01\x00\x00\x00", 4)) { 551 struct firmware *helper = priv->fw_helper; 552 553 if (helper == NULL) { 554 printk(KERN_ERR "%s: helper image needed but none " 555 "given\n", pci_name(priv->pdev)); 556 return -EINVAL; 557 } 558 559 rc = mwl8k_load_fw_image(priv, helper->data, helper->size); 560 if (rc) { 561 printk(KERN_ERR "%s: unable to load firmware " 562 "helper image\n", pci_name(priv->pdev)); 563 return rc; 564 } 565 msleep(5); 566 567 rc = mwl8k_feed_fw_image(priv, fw->data, fw->size); 568 } else { 569 rc = mwl8k_load_fw_image(priv, fw->data, fw->size); 570 } 571 572 if (rc) { 573 printk(KERN_ERR "%s: unable to load firmware image\n", 574 pci_name(priv->pdev)); 575 return rc; 576 } 577 578 iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR); 579 580 loops = 500000; 581 do { 582 u32 ready_code; 583 584 ready_code = ioread32(priv->regs + MWL8K_HIU_INT_CODE); 585 if (ready_code == MWL8K_FWAP_READY) { 586 priv->ap_fw = 1; 587 break; 588 } else if (ready_code == MWL8K_FWSTA_READY) { 589 priv->ap_fw = 0; 590 break; 591 } 592 593 cond_resched(); 594 udelay(1); 595 } while (--loops); 596 597 return loops ? 0 : -ETIMEDOUT; 598} 599 600 601/* 602 * Defines shared between transmission and reception. 603 */ 604/* HT control fields for firmware */ 605struct ewc_ht_info { 606 __le16 control1; 607 __le16 control2; 608 __le16 control3; 609} __attribute__((packed)); 610 611/* Firmware Station database operations */ 612#define MWL8K_STA_DB_ADD_ENTRY 0 613#define MWL8K_STA_DB_MODIFY_ENTRY 1 614#define MWL8K_STA_DB_DEL_ENTRY 2 615#define MWL8K_STA_DB_FLUSH 3 616 617/* Peer Entry flags - used to define the type of the peer node */ 618#define MWL8K_PEER_TYPE_ACCESSPOINT 2 619 620struct peer_capability_info { 621 /* Peer type - AP vs. STA. */ 622 __u8 peer_type; 623 624 /* Basic 802.11 capabilities from assoc resp. */ 625 __le16 basic_caps; 626 627 /* Set if peer supports 802.11n high throughput (HT). */ 628 __u8 ht_support; 629 630 /* Valid if HT is supported. */ 631 __le16 ht_caps; 632 __u8 extended_ht_caps; 633 struct ewc_ht_info ewc_info; 634 635 /* Legacy rate table. Intersection of our rates and peer rates. */ 636 __u8 legacy_rates[12]; 637 638 /* HT rate table. Intersection of our rates and peer rates. */ 639 __u8 ht_rates[16]; 640 __u8 pad[16]; 641 642 /* If set, interoperability mode, no proprietary extensions. */ 643 __u8 interop; 644 __u8 pad2; 645 __u8 station_id; 646 __le16 amsdu_enabled; 647} __attribute__((packed)); 648 649/* DMA header used by firmware and hardware. */ 650struct mwl8k_dma_data { 651 __le16 fwlen; 652 struct ieee80211_hdr wh; 653 char data[0]; 654} __attribute__((packed)); 655 656/* Routines to add/remove DMA header from skb. */ 657static inline void mwl8k_remove_dma_header(struct sk_buff *skb, __le16 qos) 658{ 659 struct mwl8k_dma_data *tr; 660 int hdrlen; 661 662 tr = (struct mwl8k_dma_data *)skb->data; 663 hdrlen = ieee80211_hdrlen(tr->wh.frame_control); 664 665 if (hdrlen != sizeof(tr->wh)) { 666 if (ieee80211_is_data_qos(tr->wh.frame_control)) { 667 memmove(tr->data - hdrlen, &tr->wh, hdrlen - 2); 668 *((__le16 *)(tr->data - 2)) = qos; 669 } else { 670 memmove(tr->data - hdrlen, &tr->wh, hdrlen); 671 } 672 } 673 674 if (hdrlen != sizeof(*tr)) 675 skb_pull(skb, sizeof(*tr) - hdrlen); 676} 677 678static inline void mwl8k_add_dma_header(struct sk_buff *skb) 679{ 680 struct ieee80211_hdr *wh; 681 int hdrlen; 682 struct mwl8k_dma_data *tr; 683 684 /* 685 * Add a firmware DMA header; the firmware requires that we 686 * present a 2-byte payload length followed by a 4-address 687 * header (without QoS field), followed (optionally) by any 688 * WEP/ExtIV header (but only filled in for CCMP). 689 */ 690 wh = (struct ieee80211_hdr *)skb->data; 691 692 hdrlen = ieee80211_hdrlen(wh->frame_control); 693 if (hdrlen != sizeof(*tr)) 694 skb_push(skb, sizeof(*tr) - hdrlen); 695 696 if (ieee80211_is_data_qos(wh->frame_control)) 697 hdrlen -= 2; 698 699 tr = (struct mwl8k_dma_data *)skb->data; 700 if (wh != &tr->wh) 701 memmove(&tr->wh, wh, hdrlen); 702 if (hdrlen != sizeof(tr->wh)) 703 memset(((void *)&tr->wh) + hdrlen, 0, sizeof(tr->wh) - hdrlen); 704 705 /* 706 * Firmware length is the length of the fully formed "802.11 707 * payload". That is, everything except for the 802.11 header. 708 * This includes all crypto material including the MIC. 709 */ 710 tr->fwlen = cpu_to_le16(skb->len - sizeof(*tr)); 711} 712 713 714/* 715 * Packet reception for 88w8366 AP firmware. 716 */ 717struct mwl8k_rxd_8366_ap { 718 __le16 pkt_len; 719 __u8 sq2; 720 __u8 rate; 721 __le32 pkt_phys_addr; 722 __le32 next_rxd_phys_addr; 723 __le16 qos_control; 724 __le16 htsig2; 725 __le32 hw_rssi_info; 726 __le32 hw_noise_floor_info; 727 __u8 noise_floor; 728 __u8 pad0[3]; 729 __u8 rssi; 730 __u8 rx_status; 731 __u8 channel; 732 __u8 rx_ctrl; 733} __attribute__((packed)); 734 735#define MWL8K_8366_AP_RATE_INFO_MCS_FORMAT 0x80 736#define MWL8K_8366_AP_RATE_INFO_40MHZ 0x40 737#define MWL8K_8366_AP_RATE_INFO_RATEID(x) ((x) & 0x3f) 738 739#define MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST 0x80 740 741static void mwl8k_rxd_8366_ap_init(void *_rxd, dma_addr_t next_dma_addr) 742{ 743 struct mwl8k_rxd_8366_ap *rxd = _rxd; 744 745 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr); 746 rxd->rx_ctrl = MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST; 747} 748 749static void mwl8k_rxd_8366_ap_refill(void *_rxd, dma_addr_t addr, int len) 750{ 751 struct mwl8k_rxd_8366_ap *rxd = _rxd; 752 753 rxd->pkt_len = cpu_to_le16(len); 754 rxd->pkt_phys_addr = cpu_to_le32(addr); 755 wmb(); 756 rxd->rx_ctrl = 0; 757} 758 759static int 760mwl8k_rxd_8366_ap_process(void *_rxd, struct ieee80211_rx_status *status, 761 __le16 *qos) 762{ 763 struct mwl8k_rxd_8366_ap *rxd = _rxd; 764 765 if (!(rxd->rx_ctrl & MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST)) 766 return -1; 767 rmb(); 768 769 memset(status, 0, sizeof(*status)); 770 771 status->signal = -rxd->rssi; 772 status->noise = -rxd->noise_floor; 773 774 if (rxd->rate & MWL8K_8366_AP_RATE_INFO_MCS_FORMAT) { 775 status->flag |= RX_FLAG_HT; 776 if (rxd->rate & MWL8K_8366_AP_RATE_INFO_40MHZ) 777 status->flag |= RX_FLAG_40MHZ; 778 status->rate_idx = MWL8K_8366_AP_RATE_INFO_RATEID(rxd->rate); 779 } else { 780 int i; 781 782 for (i = 0; i < ARRAY_SIZE(mwl8k_rates); i++) { 783 if (mwl8k_rates[i].hw_value == rxd->rate) { 784 status->rate_idx = i; 785 break; 786 } 787 } 788 } 789 790 status->band = IEEE80211_BAND_2GHZ; 791 status->freq = ieee80211_channel_to_frequency(rxd->channel); 792 793 *qos = rxd->qos_control; 794 795 return le16_to_cpu(rxd->pkt_len); 796} 797 798static struct rxd_ops rxd_8366_ap_ops = { 799 .rxd_size = sizeof(struct mwl8k_rxd_8366_ap), 800 .rxd_init = mwl8k_rxd_8366_ap_init, 801 .rxd_refill = mwl8k_rxd_8366_ap_refill, 802 .rxd_process = mwl8k_rxd_8366_ap_process, 803}; 804 805/* 806 * Packet reception for STA firmware. 807 */ 808struct mwl8k_rxd_sta { 809 __le16 pkt_len; 810 __u8 link_quality; 811 __u8 noise_level; 812 __le32 pkt_phys_addr; 813 __le32 next_rxd_phys_addr; 814 __le16 qos_control; 815 __le16 rate_info; 816 __le32 pad0[4]; 817 __u8 rssi; 818 __u8 channel; 819 __le16 pad1; 820 __u8 rx_ctrl; 821 __u8 rx_status; 822 __u8 pad2[2]; 823} __attribute__((packed)); 824 825#define MWL8K_STA_RATE_INFO_SHORTPRE 0x8000 826#define MWL8K_STA_RATE_INFO_ANTSELECT(x) (((x) >> 11) & 0x3) 827#define MWL8K_STA_RATE_INFO_RATEID(x) (((x) >> 3) & 0x3f) 828#define MWL8K_STA_RATE_INFO_40MHZ 0x0004 829#define MWL8K_STA_RATE_INFO_SHORTGI 0x0002 830#define MWL8K_STA_RATE_INFO_MCS_FORMAT 0x0001 831 832#define MWL8K_STA_RX_CTRL_OWNED_BY_HOST 0x02 833 834static void mwl8k_rxd_sta_init(void *_rxd, dma_addr_t next_dma_addr) 835{ 836 struct mwl8k_rxd_sta *rxd = _rxd; 837 838 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr); 839 rxd->rx_ctrl = MWL8K_STA_RX_CTRL_OWNED_BY_HOST; 840} 841 842static void mwl8k_rxd_sta_refill(void *_rxd, dma_addr_t addr, int len) 843{ 844 struct mwl8k_rxd_sta *rxd = _rxd; 845 846 rxd->pkt_len = cpu_to_le16(len); 847 rxd->pkt_phys_addr = cpu_to_le32(addr); 848 wmb(); 849 rxd->rx_ctrl = 0; 850} 851 852static int 853mwl8k_rxd_sta_process(void *_rxd, struct ieee80211_rx_status *status, 854 __le16 *qos) 855{ 856 struct mwl8k_rxd_sta *rxd = _rxd; 857 u16 rate_info; 858 859 if (!(rxd->rx_ctrl & MWL8K_STA_RX_CTRL_OWNED_BY_HOST)) 860 return -1; 861 rmb(); 862 863 rate_info = le16_to_cpu(rxd->rate_info); 864 865 memset(status, 0, sizeof(*status)); 866 867 status->signal = -rxd->rssi; 868 status->noise = -rxd->noise_level; 869 status->antenna = MWL8K_STA_RATE_INFO_ANTSELECT(rate_info); 870 status->rate_idx = MWL8K_STA_RATE_INFO_RATEID(rate_info); 871 872 if (rate_info & MWL8K_STA_RATE_INFO_SHORTPRE) 873 status->flag |= RX_FLAG_SHORTPRE; 874 if (rate_info & MWL8K_STA_RATE_INFO_40MHZ) 875 status->flag |= RX_FLAG_40MHZ; 876 if (rate_info & MWL8K_STA_RATE_INFO_SHORTGI) 877 status->flag |= RX_FLAG_SHORT_GI; 878 if (rate_info & MWL8K_STA_RATE_INFO_MCS_FORMAT) 879 status->flag |= RX_FLAG_HT; 880 881 status->band = IEEE80211_BAND_2GHZ; 882 status->freq = ieee80211_channel_to_frequency(rxd->channel); 883 884 *qos = rxd->qos_control; 885 886 return le16_to_cpu(rxd->pkt_len); 887} 888 889static struct rxd_ops rxd_sta_ops = { 890 .rxd_size = sizeof(struct mwl8k_rxd_sta), 891 .rxd_init = mwl8k_rxd_sta_init, 892 .rxd_refill = mwl8k_rxd_sta_refill, 893 .rxd_process = mwl8k_rxd_sta_process, 894}; 895 896 897#define MWL8K_RX_DESCS 256 898#define MWL8K_RX_MAXSZ 3800 899 900static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index) 901{ 902 struct mwl8k_priv *priv = hw->priv; 903 struct mwl8k_rx_queue *rxq = priv->rxq + index; 904 int size; 905 int i; 906 907 rxq->rxd_count = 0; 908 rxq->head = 0; 909 rxq->tail = 0; 910 911 size = MWL8K_RX_DESCS * priv->rxd_ops->rxd_size; 912 913 rxq->rxd = pci_alloc_consistent(priv->pdev, size, &rxq->rxd_dma); 914 if (rxq->rxd == NULL) { 915 printk(KERN_ERR "%s: failed to alloc RX descriptors\n", 916 wiphy_name(hw->wiphy)); 917 return -ENOMEM; 918 } 919 memset(rxq->rxd, 0, size); 920 921 rxq->buf = kmalloc(MWL8K_RX_DESCS * sizeof(*rxq->buf), GFP_KERNEL); 922 if (rxq->buf == NULL) { 923 printk(KERN_ERR "%s: failed to alloc RX skbuff list\n", 924 wiphy_name(hw->wiphy)); 925 pci_free_consistent(priv->pdev, size, rxq->rxd, rxq->rxd_dma); 926 return -ENOMEM; 927 } 928 memset(rxq->buf, 0, MWL8K_RX_DESCS * sizeof(*rxq->buf)); 929 930 for (i = 0; i < MWL8K_RX_DESCS; i++) { 931 int desc_size; 932 void *rxd; 933 int nexti; 934 dma_addr_t next_dma_addr; 935 936 desc_size = priv->rxd_ops->rxd_size; 937 rxd = rxq->rxd + (i * priv->rxd_ops->rxd_size); 938 939 nexti = i + 1; 940 if (nexti == MWL8K_RX_DESCS) 941 nexti = 0; 942 next_dma_addr = rxq->rxd_dma + (nexti * desc_size); 943 944 priv->rxd_ops->rxd_init(rxd, next_dma_addr); 945 } 946 947 return 0; 948} 949 950static int rxq_refill(struct ieee80211_hw *hw, int index, int limit) 951{ 952 struct mwl8k_priv *priv = hw->priv; 953 struct mwl8k_rx_queue *rxq = priv->rxq + index; 954 int refilled; 955 956 refilled = 0; 957 while (rxq->rxd_count < MWL8K_RX_DESCS && limit--) { 958 struct sk_buff *skb; 959 dma_addr_t addr; 960 int rx; 961 void *rxd; 962 963 skb = dev_alloc_skb(MWL8K_RX_MAXSZ); 964 if (skb == NULL) 965 break; 966 967 addr = pci_map_single(priv->pdev, skb->data, 968 MWL8K_RX_MAXSZ, DMA_FROM_DEVICE); 969 970 rxq->rxd_count++; 971 rx = rxq->tail++; 972 if (rxq->tail == MWL8K_RX_DESCS) 973 rxq->tail = 0; 974 rxq->buf[rx].skb = skb; 975 pci_unmap_addr_set(&rxq->buf[rx], dma, addr); 976 977 rxd = rxq->rxd + (rx * priv->rxd_ops->rxd_size); 978 priv->rxd_ops->rxd_refill(rxd, addr, MWL8K_RX_MAXSZ); 979 980 refilled++; 981 } 982 983 return refilled; 984} 985 986/* Must be called only when the card's reception is completely halted */ 987static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index) 988{ 989 struct mwl8k_priv *priv = hw->priv; 990 struct mwl8k_rx_queue *rxq = priv->rxq + index; 991 int i; 992 993 for (i = 0; i < MWL8K_RX_DESCS; i++) { 994 if (rxq->buf[i].skb != NULL) { 995 pci_unmap_single(priv->pdev, 996 pci_unmap_addr(&rxq->buf[i], dma), 997 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE); 998 pci_unmap_addr_set(&rxq->buf[i], dma, 0); 999 1000 kfree_skb(rxq->buf[i].skb); 1001 rxq->buf[i].skb = NULL; 1002 } 1003 } 1004 1005 kfree(rxq->buf); 1006 rxq->buf = NULL; 1007 1008 pci_free_consistent(priv->pdev, 1009 MWL8K_RX_DESCS * priv->rxd_ops->rxd_size, 1010 rxq->rxd, rxq->rxd_dma); 1011 rxq->rxd = NULL; 1012} 1013 1014 1015/* 1016 * Scan a list of BSSIDs to process for finalize join. 1017 * Allows for extension to process multiple BSSIDs. 1018 */ 1019static inline int 1020mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh) 1021{ 1022 return priv->capture_beacon && 1023 ieee80211_is_beacon(wh->frame_control) && 1024 !compare_ether_addr(wh->addr3, priv->capture_bssid); 1025} 1026 1027static inline void mwl8k_save_beacon(struct ieee80211_hw *hw, 1028 struct sk_buff *skb) 1029{ 1030 struct mwl8k_priv *priv = hw->priv; 1031 1032 priv->capture_beacon = false; 1033 memset(priv->capture_bssid, 0, ETH_ALEN); 1034 1035 /* 1036 * Use GFP_ATOMIC as rxq_process is called from 1037 * the primary interrupt handler, memory allocation call 1038 * must not sleep. 1039 */ 1040 priv->beacon_skb = skb_copy(skb, GFP_ATOMIC); 1041 if (priv->beacon_skb != NULL) 1042 ieee80211_queue_work(hw, &priv->finalize_join_worker); 1043} 1044 1045static int rxq_process(struct ieee80211_hw *hw, int index, int limit) 1046{ 1047 struct mwl8k_priv *priv = hw->priv; 1048 struct mwl8k_rx_queue *rxq = priv->rxq + index; 1049 int processed; 1050 1051 processed = 0; 1052 while (rxq->rxd_count && limit--) { 1053 struct sk_buff *skb; 1054 void *rxd; 1055 int pkt_len; 1056 struct ieee80211_rx_status status; 1057 __le16 qos; 1058 1059 skb = rxq->buf[rxq->head].skb; 1060 if (skb == NULL) 1061 break; 1062 1063 rxd = rxq->rxd + (rxq->head * priv->rxd_ops->rxd_size); 1064 1065 pkt_len = priv->rxd_ops->rxd_process(rxd, &status, &qos); 1066 if (pkt_len < 0) 1067 break; 1068 1069 rxq->buf[rxq->head].skb = NULL; 1070 1071 pci_unmap_single(priv->pdev, 1072 pci_unmap_addr(&rxq->buf[rxq->head], dma), 1073 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE); 1074 pci_unmap_addr_set(&rxq->buf[rxq->head], dma, 0); 1075 1076 rxq->head++; 1077 if (rxq->head == MWL8K_RX_DESCS) 1078 rxq->head = 0; 1079 1080 rxq->rxd_count--; 1081 1082 skb_put(skb, pkt_len); 1083 mwl8k_remove_dma_header(skb, qos); 1084 1085 /* 1086 * Check for a pending join operation. Save a 1087 * copy of the beacon and schedule a tasklet to 1088 * send a FINALIZE_JOIN command to the firmware. 1089 */ 1090 if (mwl8k_capture_bssid(priv, (void *)skb->data)) 1091 mwl8k_save_beacon(hw, skb); 1092 1093 memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status)); 1094 ieee80211_rx_irqsafe(hw, skb); 1095 1096 processed++; 1097 } 1098 1099 return processed; 1100} 1101 1102 1103/* 1104 * Packet transmission. 1105 */ 1106 1107#define MWL8K_TXD_STATUS_OK 0x00000001 1108#define MWL8K_TXD_STATUS_OK_RETRY 0x00000002 1109#define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004 1110#define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008 1111#define MWL8K_TXD_STATUS_FW_OWNED 0x80000000 1112 1113#define MWL8K_QOS_QLEN_UNSPEC 0xff00 1114#define MWL8K_QOS_ACK_POLICY_MASK 0x0060 1115#define MWL8K_QOS_ACK_POLICY_NORMAL 0x0000 1116#define MWL8K_QOS_ACK_POLICY_BLOCKACK 0x0060 1117#define MWL8K_QOS_EOSP 0x0010 1118 1119struct mwl8k_tx_desc { 1120 __le32 status; 1121 __u8 data_rate; 1122 __u8 tx_priority; 1123 __le16 qos_control; 1124 __le32 pkt_phys_addr; 1125 __le16 pkt_len; 1126 __u8 dest_MAC_addr[ETH_ALEN]; 1127 __le32 next_txd_phys_addr; 1128 __le32 reserved; 1129 __le16 rate_info; 1130 __u8 peer_id; 1131 __u8 tx_frag_cnt; 1132} __attribute__((packed)); 1133 1134#define MWL8K_TX_DESCS 128 1135 1136static int mwl8k_txq_init(struct ieee80211_hw *hw, int index) 1137{ 1138 struct mwl8k_priv *priv = hw->priv; 1139 struct mwl8k_tx_queue *txq = priv->txq + index; 1140 int size; 1141 int i; 1142 1143 memset(&txq->stats, 0, sizeof(struct ieee80211_tx_queue_stats)); 1144 txq->stats.limit = MWL8K_TX_DESCS; 1145 txq->head = 0; 1146 txq->tail = 0; 1147 1148 size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc); 1149 1150 txq->txd = pci_alloc_consistent(priv->pdev, size, &txq->txd_dma); 1151 if (txq->txd == NULL) { 1152 printk(KERN_ERR "%s: failed to alloc TX descriptors\n", 1153 wiphy_name(hw->wiphy)); 1154 return -ENOMEM; 1155 } 1156 memset(txq->txd, 0, size); 1157 1158 txq->skb = kmalloc(MWL8K_TX_DESCS * sizeof(*txq->skb), GFP_KERNEL); 1159 if (txq->skb == NULL) { 1160 printk(KERN_ERR "%s: failed to alloc TX skbuff list\n", 1161 wiphy_name(hw->wiphy)); 1162 pci_free_consistent(priv->pdev, size, txq->txd, txq->txd_dma); 1163 return -ENOMEM; 1164 } 1165 memset(txq->skb, 0, MWL8K_TX_DESCS * sizeof(*txq->skb)); 1166 1167 for (i = 0; i < MWL8K_TX_DESCS; i++) { 1168 struct mwl8k_tx_desc *tx_desc; 1169 int nexti; 1170 1171 tx_desc = txq->txd + i; 1172 nexti = (i + 1) % MWL8K_TX_DESCS; 1173 1174 tx_desc->status = 0; 1175 tx_desc->next_txd_phys_addr = 1176 cpu_to_le32(txq->txd_dma + nexti * sizeof(*tx_desc)); 1177 } 1178 1179 return 0; 1180} 1181 1182static inline void mwl8k_tx_start(struct mwl8k_priv *priv) 1183{ 1184 iowrite32(MWL8K_H2A_INT_PPA_READY, 1185 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); 1186 iowrite32(MWL8K_H2A_INT_DUMMY, 1187 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); 1188 ioread32(priv->regs + MWL8K_HIU_INT_CODE); 1189} 1190 1191static void mwl8k_dump_tx_rings(struct ieee80211_hw *hw) 1192{ 1193 struct mwl8k_priv *priv = hw->priv; 1194 int i; 1195 1196 for (i = 0; i < MWL8K_TX_QUEUES; i++) { 1197 struct mwl8k_tx_queue *txq = priv->txq + i; 1198 int fw_owned = 0; 1199 int drv_owned = 0; 1200 int unused = 0; 1201 int desc; 1202 1203 for (desc = 0; desc < MWL8K_TX_DESCS; desc++) { 1204 struct mwl8k_tx_desc *tx_desc = txq->txd + desc; 1205 u32 status; 1206 1207 status = le32_to_cpu(tx_desc->status); 1208 if (status & MWL8K_TXD_STATUS_FW_OWNED) 1209 fw_owned++; 1210 else 1211 drv_owned++; 1212 1213 if (tx_desc->pkt_len == 0) 1214 unused++; 1215 } 1216 1217 printk(KERN_ERR "%s: txq[%d] len=%d head=%d tail=%d " 1218 "fw_owned=%d drv_owned=%d unused=%d\n", 1219 wiphy_name(hw->wiphy), i, 1220 txq->stats.len, txq->head, txq->tail, 1221 fw_owned, drv_owned, unused); 1222 } 1223} 1224 1225/* 1226 * Must be called with priv->fw_mutex held and tx queues stopped. 1227 */ 1228#define MWL8K_TX_WAIT_TIMEOUT_MS 1000 1229 1230static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw) 1231{ 1232 struct mwl8k_priv *priv = hw->priv; 1233 DECLARE_COMPLETION_ONSTACK(tx_wait); 1234 int retry; 1235 int rc; 1236 1237 might_sleep(); 1238 1239 /* 1240 * The TX queues are stopped at this point, so this test 1241 * doesn't need to take ->tx_lock. 1242 */ 1243 if (!priv->pending_tx_pkts) 1244 return 0; 1245 1246 retry = 0; 1247 rc = 0; 1248 1249 spin_lock_bh(&priv->tx_lock); 1250 priv->tx_wait = &tx_wait; 1251 while (!rc) { 1252 int oldcount; 1253 unsigned long timeout; 1254 1255 oldcount = priv->pending_tx_pkts; 1256 1257 spin_unlock_bh(&priv->tx_lock); 1258 timeout = wait_for_completion_timeout(&tx_wait, 1259 msecs_to_jiffies(MWL8K_TX_WAIT_TIMEOUT_MS)); 1260 spin_lock_bh(&priv->tx_lock); 1261 1262 if (timeout) { 1263 WARN_ON(priv->pending_tx_pkts); 1264 if (retry) { 1265 printk(KERN_NOTICE "%s: tx rings drained\n", 1266 wiphy_name(hw->wiphy)); 1267 } 1268 break; 1269 } 1270 1271 if (priv->pending_tx_pkts < oldcount) { 1272 printk(KERN_NOTICE "%s: timeout waiting for tx " 1273 "rings to drain (%d -> %d pkts), retrying\n", 1274 wiphy_name(hw->wiphy), oldcount, 1275 priv->pending_tx_pkts); 1276 retry = 1; 1277 continue; 1278 } 1279 1280 priv->tx_wait = NULL; 1281 1282 printk(KERN_ERR "%s: tx rings stuck for %d ms\n", 1283 wiphy_name(hw->wiphy), MWL8K_TX_WAIT_TIMEOUT_MS); 1284 mwl8k_dump_tx_rings(hw); 1285 1286 rc = -ETIMEDOUT; 1287 } 1288 spin_unlock_bh(&priv->tx_lock); 1289 1290 return rc; 1291} 1292 1293#define MWL8K_TXD_SUCCESS(status) \ 1294 ((status) & (MWL8K_TXD_STATUS_OK | \ 1295 MWL8K_TXD_STATUS_OK_RETRY | \ 1296 MWL8K_TXD_STATUS_OK_MORE_RETRY)) 1297 1298static void mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int force) 1299{ 1300 struct mwl8k_priv *priv = hw->priv; 1301 struct mwl8k_tx_queue *txq = priv->txq + index; 1302 int wake = 0; 1303 1304 while (txq->stats.len > 0) { 1305 int tx; 1306 struct mwl8k_tx_desc *tx_desc; 1307 unsigned long addr; 1308 int size; 1309 struct sk_buff *skb; 1310 struct ieee80211_tx_info *info; 1311 u32 status; 1312 1313 tx = txq->head; 1314 tx_desc = txq->txd + tx; 1315 1316 status = le32_to_cpu(tx_desc->status); 1317 1318 if (status & MWL8K_TXD_STATUS_FW_OWNED) { 1319 if (!force) 1320 break; 1321 tx_desc->status &= 1322 ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED); 1323 } 1324 1325 txq->head = (tx + 1) % MWL8K_TX_DESCS; 1326 BUG_ON(txq->stats.len == 0); 1327 txq->stats.len--; 1328 priv->pending_tx_pkts--; 1329 1330 addr = le32_to_cpu(tx_desc->pkt_phys_addr); 1331 size = le16_to_cpu(tx_desc->pkt_len); 1332 skb = txq->skb[tx]; 1333 txq->skb[tx] = NULL; 1334 1335 BUG_ON(skb == NULL); 1336 pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE); 1337 1338 mwl8k_remove_dma_header(skb, tx_desc->qos_control); 1339 1340 /* Mark descriptor as unused */ 1341 tx_desc->pkt_phys_addr = 0; 1342 tx_desc->pkt_len = 0; 1343 1344 info = IEEE80211_SKB_CB(skb); 1345 ieee80211_tx_info_clear_status(info); 1346 if (MWL8K_TXD_SUCCESS(status)) 1347 info->flags |= IEEE80211_TX_STAT_ACK; 1348 1349 ieee80211_tx_status_irqsafe(hw, skb); 1350 1351 wake = 1; 1352 } 1353 1354 if (wake && priv->radio_on && !mutex_is_locked(&priv->fw_mutex)) 1355 ieee80211_wake_queue(hw, index); 1356} 1357 1358/* must be called only when the card's transmit is completely halted */ 1359static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index) 1360{ 1361 struct mwl8k_priv *priv = hw->priv; 1362 struct mwl8k_tx_queue *txq = priv->txq + index; 1363 1364 mwl8k_txq_reclaim(hw, index, 1); 1365 1366 kfree(txq->skb); 1367 txq->skb = NULL; 1368 1369 pci_free_consistent(priv->pdev, 1370 MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc), 1371 txq->txd, txq->txd_dma); 1372 txq->txd = NULL; 1373} 1374 1375static int 1376mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb) 1377{ 1378 struct mwl8k_priv *priv = hw->priv; 1379 struct ieee80211_tx_info *tx_info; 1380 struct mwl8k_vif *mwl8k_vif; 1381 struct ieee80211_hdr *wh; 1382 struct mwl8k_tx_queue *txq; 1383 struct mwl8k_tx_desc *tx; 1384 dma_addr_t dma; 1385 u32 txstatus; 1386 u8 txdatarate; 1387 u16 qos; 1388 1389 wh = (struct ieee80211_hdr *)skb->data; 1390 if (ieee80211_is_data_qos(wh->frame_control)) 1391 qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh))); 1392 else 1393 qos = 0; 1394 1395 mwl8k_add_dma_header(skb); 1396 wh = &((struct mwl8k_dma_data *)skb->data)->wh; 1397 1398 tx_info = IEEE80211_SKB_CB(skb); 1399 mwl8k_vif = MWL8K_VIF(tx_info->control.vif); 1400 1401 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { 1402 u16 seqno = mwl8k_vif->seqno; 1403 1404 wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); 1405 wh->seq_ctrl |= cpu_to_le16(seqno << 4); 1406 mwl8k_vif->seqno = seqno++ % 4096; 1407 } 1408 1409 /* Setup firmware control bit fields for each frame type. */ 1410 txstatus = 0; 1411 txdatarate = 0; 1412 if (ieee80211_is_mgmt(wh->frame_control) || 1413 ieee80211_is_ctl(wh->frame_control)) { 1414 txdatarate = 0; 1415 qos |= MWL8K_QOS_QLEN_UNSPEC | MWL8K_QOS_EOSP; 1416 } else if (ieee80211_is_data(wh->frame_control)) { 1417 txdatarate = 1; 1418 if (is_multicast_ether_addr(wh->addr1)) 1419 txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX; 1420 1421 qos &= ~MWL8K_QOS_ACK_POLICY_MASK; 1422 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) 1423 qos |= MWL8K_QOS_ACK_POLICY_BLOCKACK; 1424 else 1425 qos |= MWL8K_QOS_ACK_POLICY_NORMAL; 1426 } 1427 1428 dma = pci_map_single(priv->pdev, skb->data, 1429 skb->len, PCI_DMA_TODEVICE); 1430 1431 if (pci_dma_mapping_error(priv->pdev, dma)) { 1432 printk(KERN_DEBUG "%s: failed to dma map skb, " 1433 "dropping TX frame.\n", wiphy_name(hw->wiphy)); 1434 dev_kfree_skb(skb); 1435 return NETDEV_TX_OK; 1436 } 1437 1438 spin_lock_bh(&priv->tx_lock); 1439 1440 txq = priv->txq + index; 1441 1442 BUG_ON(txq->skb[txq->tail] != NULL); 1443 txq->skb[txq->tail] = skb; 1444 1445 tx = txq->txd + txq->tail; 1446 tx->data_rate = txdatarate; 1447 tx->tx_priority = index; 1448 tx->qos_control = cpu_to_le16(qos); 1449 tx->pkt_phys_addr = cpu_to_le32(dma); 1450 tx->pkt_len = cpu_to_le16(skb->len); 1451 tx->rate_info = 0; 1452 tx->peer_id = mwl8k_vif->peer_id; 1453 wmb(); 1454 tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus); 1455 1456 txq->stats.count++; 1457 txq->stats.len++; 1458 priv->pending_tx_pkts++; 1459 1460 txq->tail++; 1461 if (txq->tail == MWL8K_TX_DESCS) 1462 txq->tail = 0; 1463 1464 if (txq->head == txq->tail) 1465 ieee80211_stop_queue(hw, index); 1466 1467 mwl8k_tx_start(priv); 1468 1469 spin_unlock_bh(&priv->tx_lock); 1470 1471 return NETDEV_TX_OK; 1472} 1473 1474 1475/* 1476 * Firmware access. 1477 * 1478 * We have the following requirements for issuing firmware commands: 1479 * - Some commands require that the packet transmit path is idle when 1480 * the command is issued. (For simplicity, we'll just quiesce the 1481 * transmit path for every command.) 1482 * - There are certain sequences of commands that need to be issued to 1483 * the hardware sequentially, with no other intervening commands. 1484 * 1485 * This leads to an implementation of a "firmware lock" as a mutex that 1486 * can be taken recursively, and which is taken by both the low-level 1487 * command submission function (mwl8k_post_cmd) as well as any users of 1488 * that function that require issuing of an atomic sequence of commands, 1489 * and quiesces the transmit path whenever it's taken. 1490 */ 1491static int mwl8k_fw_lock(struct ieee80211_hw *hw) 1492{ 1493 struct mwl8k_priv *priv = hw->priv; 1494 1495 if (priv->fw_mutex_owner != current) { 1496 int rc; 1497 1498 mutex_lock(&priv->fw_mutex); 1499 ieee80211_stop_queues(hw); 1500 1501 rc = mwl8k_tx_wait_empty(hw); 1502 if (rc) { 1503 ieee80211_wake_queues(hw); 1504 mutex_unlock(&priv->fw_mutex); 1505 1506 return rc; 1507 } 1508 1509 priv->fw_mutex_owner = current; 1510 } 1511 1512 priv->fw_mutex_depth++; 1513 1514 return 0; 1515} 1516 1517static void mwl8k_fw_unlock(struct ieee80211_hw *hw) 1518{ 1519 struct mwl8k_priv *priv = hw->priv; 1520 1521 if (!--priv->fw_mutex_depth) { 1522 ieee80211_wake_queues(hw); 1523 priv->fw_mutex_owner = NULL; 1524 mutex_unlock(&priv->fw_mutex); 1525 } 1526} 1527 1528 1529/* 1530 * Command processing. 1531 */ 1532 1533/* Timeout firmware commands after 10s */ 1534#define MWL8K_CMD_TIMEOUT_MS 10000 1535 1536static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd) 1537{ 1538 DECLARE_COMPLETION_ONSTACK(cmd_wait); 1539 struct mwl8k_priv *priv = hw->priv; 1540 void __iomem *regs = priv->regs; 1541 dma_addr_t dma_addr; 1542 unsigned int dma_size; 1543 int rc; 1544 unsigned long timeout = 0; 1545 u8 buf[32]; 1546 1547 cmd->result = 0xffff; 1548 dma_size = le16_to_cpu(cmd->length); 1549 dma_addr = pci_map_single(priv->pdev, cmd, dma_size, 1550 PCI_DMA_BIDIRECTIONAL); 1551 if (pci_dma_mapping_error(priv->pdev, dma_addr)) 1552 return -ENOMEM; 1553 1554 rc = mwl8k_fw_lock(hw); 1555 if (rc) { 1556 pci_unmap_single(priv->pdev, dma_addr, dma_size, 1557 PCI_DMA_BIDIRECTIONAL); 1558 return rc; 1559 } 1560 1561 priv->hostcmd_wait = &cmd_wait; 1562 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR); 1563 iowrite32(MWL8K_H2A_INT_DOORBELL, 1564 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); 1565 iowrite32(MWL8K_H2A_INT_DUMMY, 1566 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); 1567 1568 timeout = wait_for_completion_timeout(&cmd_wait, 1569 msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS)); 1570 1571 priv->hostcmd_wait = NULL; 1572 1573 mwl8k_fw_unlock(hw); 1574 1575 pci_unmap_single(priv->pdev, dma_addr, dma_size, 1576 PCI_DMA_BIDIRECTIONAL); 1577 1578 if (!timeout) { 1579 printk(KERN_ERR "%s: Command %s timeout after %u ms\n", 1580 wiphy_name(hw->wiphy), 1581 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)), 1582 MWL8K_CMD_TIMEOUT_MS); 1583 rc = -ETIMEDOUT; 1584 } else { 1585 int ms; 1586 1587 ms = MWL8K_CMD_TIMEOUT_MS - jiffies_to_msecs(timeout); 1588 1589 rc = cmd->result ? -EINVAL : 0; 1590 if (rc) 1591 printk(KERN_ERR "%s: Command %s error 0x%x\n", 1592 wiphy_name(hw->wiphy), 1593 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)), 1594 le16_to_cpu(cmd->result)); 1595 else if (ms > 2000) 1596 printk(KERN_NOTICE "%s: Command %s took %d ms\n", 1597 wiphy_name(hw->wiphy), 1598 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)), 1599 ms); 1600 } 1601 1602 return rc; 1603} 1604 1605/* 1606 * CMD_GET_HW_SPEC (STA version). 1607 */ 1608struct mwl8k_cmd_get_hw_spec_sta { 1609 struct mwl8k_cmd_pkt header; 1610 __u8 hw_rev; 1611 __u8 host_interface; 1612 __le16 num_mcaddrs; 1613 __u8 perm_addr[ETH_ALEN]; 1614 __le16 region_code; 1615 __le32 fw_rev; 1616 __le32 ps_cookie; 1617 __le32 caps; 1618 __u8 mcs_bitmap[16]; 1619 __le32 rx_queue_ptr; 1620 __le32 num_tx_queues; 1621 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES]; 1622 __le32 caps2; 1623 __le32 num_tx_desc_per_queue; 1624 __le32 total_rxd; 1625} __attribute__((packed)); 1626 1627static int mwl8k_cmd_get_hw_spec_sta(struct ieee80211_hw *hw) 1628{ 1629 struct mwl8k_priv *priv = hw->priv; 1630 struct mwl8k_cmd_get_hw_spec_sta *cmd; 1631 int rc; 1632 int i; 1633 1634 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); 1635 if (cmd == NULL) 1636 return -ENOMEM; 1637 1638 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC); 1639 cmd->header.length = cpu_to_le16(sizeof(*cmd)); 1640 1641 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr)); 1642 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma); 1643 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma); 1644 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES); 1645 for (i = 0; i < MWL8K_TX_QUEUES; i++) 1646 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma); 1647 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS); 1648 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS); 1649 1650 rc = mwl8k_post_cmd(hw, &cmd->header); 1651 1652 if (!rc) { 1653 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr); 1654 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs); 1655 priv->fw_rev = le32_to_cpu(cmd->fw_rev); 1656 priv->hw_rev = cmd->hw_rev; 1657 } 1658 1659 kfree(cmd); 1660 return rc; 1661} 1662 1663/* 1664 * CMD_GET_HW_SPEC (AP version). 1665 */ 1666struct mwl8k_cmd_get_hw_spec_ap { 1667 struct mwl8k_cmd_pkt header; 1668 __u8 hw_rev; 1669 __u8 host_interface; 1670 __le16 num_wcb; 1671 __le16 num_mcaddrs; 1672 __u8 perm_addr[ETH_ALEN]; 1673 __le16 region_code; 1674 __le16 num_antenna; 1675 __le32 fw_rev; 1676 __le32 wcbbase0; 1677 __le32 rxwrptr; 1678 __le32 rxrdptr; 1679 __le32 ps_cookie; 1680 __le32 wcbbase1; 1681 __le32 wcbbase2; 1682 __le32 wcbbase3; 1683} __attribute__((packed)); 1684 1685static int mwl8k_cmd_get_hw_spec_ap(struct ieee80211_hw *hw) 1686{ 1687 struct mwl8k_priv *priv = hw->priv; 1688 struct mwl8k_cmd_get_hw_spec_ap *cmd; 1689 int rc; 1690 1691 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); 1692 if (cmd == NULL) 1693 return -ENOMEM; 1694 1695 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC); 1696 cmd->header.length = cpu_to_le16(sizeof(*cmd)); 1697 1698 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr)); 1699 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma); 1700 1701 rc = mwl8k_post_cmd(hw, &cmd->header); 1702 1703 if (!rc) { 1704 int off; 1705 1706 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr); 1707 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs); 1708 priv->fw_rev = le32_to_cpu(cmd->fw_rev); 1709 priv->hw_rev = cmd->hw_rev; 1710 1711 off = le32_to_cpu(cmd->wcbbase0) & 0xffff; 1712 iowrite32(cpu_to_le32(priv->txq[0].txd_dma), priv->sram + off); 1713 1714 off = le32_to_cpu(cmd->rxwrptr) & 0xffff; 1715 iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off); 1716 1717 off = le32_to_cpu(cmd->rxrdptr) & 0xffff; 1718 iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off); 1719 1720 off = le32_to_cpu(cmd->wcbbase1) & 0xffff; 1721 iowrite32(cpu_to_le32(priv->txq[1].txd_dma), priv->sram + off); 1722 1723 off = le32_to_cpu(cmd->wcbbase2) & 0xffff; 1724 iowrite32(cpu_to_le32(priv->txq[2].txd_dma), priv->sram + off); 1725 1726 off = le32_to_cpu(cmd->wcbbase3) & 0xffff; 1727 iowrite32(cpu_to_le32(priv->txq[3].txd_dma), priv->sram + off); 1728 } 1729 1730 kfree(cmd); 1731 return rc; 1732} 1733 1734/* 1735 * CMD_SET_HW_SPEC. 1736 */ 1737struct mwl8k_cmd_set_hw_spec { 1738 struct mwl8k_cmd_pkt header; 1739 __u8 hw_rev; 1740 __u8 host_interface; 1741 __le16 num_mcaddrs; 1742 __u8 perm_addr[ETH_ALEN]; 1743 __le16 region_code; 1744 __le32 fw_rev; 1745 __le32 ps_cookie; 1746 __le32 caps; 1747 __le32 rx_queue_ptr; 1748 __le32 num_tx_queues; 1749 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES]; 1750 __le32 flags; 1751 __le32 num_tx_desc_per_queue; 1752 __le32 total_rxd; 1753} __attribute__((packed)); 1754 1755#define MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT 0x00000080 1756 1757static int mwl8k_cmd_set_hw_spec(struct ieee80211_hw *hw) 1758{ 1759 struct mwl8k_priv *priv = hw->priv; 1760 struct mwl8k_cmd_set_hw_spec *cmd; 1761 int rc; 1762 int i; 1763 1764 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); 1765 if (cmd == NULL) 1766 return -ENOMEM; 1767 1768 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_HW_SPEC); 1769 cmd->header.length = cpu_to_le16(sizeof(*cmd)); 1770 1771 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma); 1772 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma); 1773 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES); 1774 for (i = 0; i < MWL8K_TX_QUEUES; i++) 1775 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma); 1776 cmd->flags = cpu_to_le32(MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT); 1777 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS); 1778 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS); 1779 1780 rc = mwl8k_post_cmd(hw, &cmd->header); 1781 kfree(cmd); 1782 1783 return rc; 1784} 1785 1786/* 1787 * CMD_MAC_MULTICAST_ADR. 1788 */ 1789struct mwl8k_cmd_mac_multicast_adr { 1790 struct mwl8k_cmd_pkt header; 1791 __le16 action; 1792 __le16 numaddr; 1793 __u8 addr[0][ETH_ALEN]; 1794}; 1795 1796#define MWL8K_ENABLE_RX_DIRECTED 0x0001 1797#define MWL8K_ENABLE_RX_MULTICAST 0x0002 1798#define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004 1799#define MWL8K_ENABLE_RX_BROADCAST 0x0008 1800 1801static struct mwl8k_cmd_pkt * 1802__mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw, int allmulti, 1803 int mc_count, struct dev_addr_list *mclist) 1804{ 1805 struct mwl8k_priv *priv = hw->priv; 1806 struct mwl8k_cmd_mac_multicast_adr *cmd; 1807 int size; 1808 1809 if (allmulti || mc_count > priv->num_mcaddrs) { 1810 allmulti = 1; 1811 mc_count = 0; 1812 } 1813 1814 size = sizeof(*cmd) + mc_count * ETH_ALEN; 1815 1816 cmd = kzalloc(size, GFP_ATOMIC); 1817 if (cmd == NULL) 1818 return NULL; 1819 1820 cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR); 1821 cmd->header.length = cpu_to_le16(size); 1822 cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_DIRECTED | 1823 MWL8K_ENABLE_RX_BROADCAST); 1824 1825 if (allmulti) { 1826 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_ALL_MULTICAST); 1827 } else if (mc_count) { 1828 int i; 1829 1830 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST); 1831 cmd->numaddr = cpu_to_le16(mc_count); 1832 for (i = 0; i < mc_count && mclist; i++) { 1833 if (mclist->da_addrlen != ETH_ALEN) { 1834 kfree(cmd); 1835 return NULL; 1836 } 1837 memcpy(cmd->addr[i], mclist->da_addr, ETH_ALEN); 1838 mclist = mclist->next; 1839 } 1840 } 1841 1842 return &cmd->header; 1843} 1844 1845/* 1846 * CMD_GET_STAT. 1847 */ 1848struct mwl8k_cmd_get_stat { 1849 struct mwl8k_cmd_pkt header; 1850 __le32 stats[64]; 1851} __attribute__((packed)); 1852 1853#define MWL8K_STAT_ACK_FAILURE 9 1854#define MWL8K_STAT_RTS_FAILURE 12 1855#define MWL8K_STAT_FCS_ERROR 24 1856#define MWL8K_STAT_RTS_SUCCESS 11 1857 1858static int mwl8k_cmd_get_stat(struct ieee80211_hw *hw, 1859 struct ieee80211_low_level_stats *stats) 1860{ 1861 struct mwl8k_cmd_get_stat *cmd; 1862 int rc; 1863 1864 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); 1865 if (cmd == NULL) 1866 return -ENOMEM; 1867 1868 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT); 1869 cmd->header.length = cpu_to_le16(sizeof(*cmd)); 1870 1871 rc = mwl8k_post_cmd(hw, &cmd->header); 1872 if (!rc) { 1873 stats->dot11ACKFailureCount = 1874 le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]); 1875 stats->dot11RTSFailureCount = 1876 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]); 1877 stats->dot11FCSErrorCount = 1878 le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]); 1879 stats->dot11RTSSuccessCount = 1880 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]); 1881 } 1882 kfree(cmd); 1883 1884 return rc; 1885} 1886 1887/* 1888 * CMD_RADIO_CONTROL. 1889 */ 1890struct mwl8k_cmd_radio_control { 1891 struct mwl8k_cmd_pkt header; 1892 __le16 action; 1893 __le16 control; 1894 __le16 radio_on; 1895} __attribute__((packed)); 1896 1897static int 1898mwl8k_cmd_radio_control(struct ieee80211_hw *hw, bool enable, bool force) 1899{ 1900 struct mwl8k_priv *priv = hw->priv; 1901 struct mwl8k_cmd_radio_control *cmd; 1902 int rc; 1903 1904 if (enable == priv->radio_on && !force) 1905 return 0; 1906 1907 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); 1908 if (cmd == NULL) 1909 return -ENOMEM; 1910 1911 cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL); 1912 cmd->header.length = cpu_to_le16(sizeof(*cmd)); 1913 cmd->action = cpu_to_le16(MWL8K_CMD_SET); 1914 cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1); 1915 cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000); 1916 1917 rc = mwl8k_post_cmd(hw, &cmd->header); 1918 kfree(cmd); 1919 1920 if (!rc) 1921 priv->radio_on = enable; 1922 1923 return rc; 1924} 1925 1926static int mwl8k_cmd_radio_disable(struct ieee80211_hw *hw) 1927{ 1928 return mwl8k_cmd_radio_control(hw, 0, 0); 1929} 1930 1931static int mwl8k_cmd_radio_enable(struct ieee80211_hw *hw) 1932{ 1933 return mwl8k_cmd_radio_control(hw, 1, 0); 1934} 1935 1936static int 1937mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble) 1938{ 1939 struct mwl8k_priv *priv = hw->priv; 1940 1941 priv->radio_short_preamble = short_preamble; 1942 1943 return mwl8k_cmd_radio_control(hw, 1, 1); 1944} 1945 1946/* 1947 * CMD_RF_TX_POWER. 1948 */ 1949#define MWL8K_TX_POWER_LEVEL_TOTAL 8 1950 1951struct mwl8k_cmd_rf_tx_power { 1952 struct mwl8k_cmd_pkt header; 1953 __le16 action; 1954 __le16 support_level; 1955 __le16 current_level; 1956 __le16 reserved; 1957 __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL]; 1958} __attribute__((packed)); 1959 1960static int mwl8k_cmd_rf_tx_power(struct ieee80211_hw *hw, int dBm) 1961{ 1962 struct mwl8k_cmd_rf_tx_power *cmd; 1963 int rc; 1964 1965 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); 1966 if (cmd == NULL) 1967 return -ENOMEM; 1968 1969 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER); 1970 cmd->header.length = cpu_to_le16(sizeof(*cmd)); 1971 cmd->action = cpu_to_le16(MWL8K_CMD_SET); 1972 cmd->support_level = cpu_to_le16(dBm); 1973 1974 rc = mwl8k_post_cmd(hw, &cmd->header); 1975 kfree(cmd); 1976 1977 return rc; 1978} 1979 1980/* 1981 * CMD_RF_ANTENNA. 1982 */ 1983struct mwl8k_cmd_rf_antenna { 1984 struct mwl8k_cmd_pkt header; 1985 __le16 antenna; 1986 __le16 mode; 1987} __attribute__((packed)); 1988 1989#define MWL8K_RF_ANTENNA_RX 1 1990#define MWL8K_RF_ANTENNA_TX 2 1991 1992static int 1993mwl8k_cmd_rf_antenna(struct ieee80211_hw *hw, int antenna, int mask) 1994{ 1995 struct mwl8k_cmd_rf_antenna *cmd; 1996 int rc; 1997 1998 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); 1999 if (cmd == NULL) 2000 return -ENOMEM; 2001 2002 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_ANTENNA); 2003 cmd->header.length = cpu_to_le16(sizeof(*cmd)); 2004 cmd->antenna = cpu_to_le16(antenna); 2005 cmd->mode = cpu_to_le16(mask); 2006 2007 rc = mwl8k_post_cmd(hw, &cmd->header); 2008 kfree(cmd); 2009 2010 return rc; 2011} 2012 2013/* 2014 * CMD_SET_PRE_SCAN. 2015 */ 2016struct mwl8k_cmd_set_pre_scan { 2017 struct mwl8k_cmd_pkt header; 2018} __attribute__((packed)); 2019 2020static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw) 2021{ 2022 struct mwl8k_cmd_set_pre_scan *cmd; 2023 int rc; 2024 2025 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); 2026 if (cmd == NULL) 2027 return -ENOMEM; 2028 2029 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN); 2030 cmd->header.length = cpu_to_le16(sizeof(*cmd)); 2031 2032 rc = mwl8k_post_cmd(hw, &cmd->header); 2033 kfree(cmd); 2034 2035 return rc; 2036} 2037 2038/* 2039 * CMD_SET_POST_SCAN. 2040 */ 2041struct mwl8k_cmd_set_post_scan { 2042 struct mwl8k_cmd_pkt header; 2043 __le32 isibss; 2044 __u8 bssid[ETH_ALEN]; 2045} __attribute__((packed)); 2046 2047static int 2048mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, __u8 *mac) 2049{ 2050 struct mwl8k_cmd_set_post_scan *cmd; 2051 int rc; 2052 2053 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); 2054 if (cmd == NULL) 2055 return -ENOMEM; 2056 2057 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN); 2058 cmd->header.length = cpu_to_le16(sizeof(*cmd)); 2059 cmd->isibss = 0; 2060 memcpy(cmd->bssid, mac, ETH_ALEN); 2061 2062 rc = mwl8k_post_cmd(hw, &cmd->header); 2063 kfree(cmd); 2064 2065 return rc; 2066} 2067 2068/* 2069 * CMD_SET_RF_CHANNEL. 2070 */ 2071struct mwl8k_cmd_set_rf_channel { 2072 struct mwl8k_cmd_pkt header; 2073 __le16 action; 2074 __u8 current_channel; 2075 __le32 channel_flags; 2076} __attribute__((packed)); 2077 2078static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw, 2079 struct ieee80211_channel *channel) 2080{ 2081 struct mwl8k_cmd_set_rf_channel *cmd; 2082 int rc; 2083 2084 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); 2085 if (cmd == NULL) 2086 return -ENOMEM; 2087 2088 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL); 2089 cmd->header.length = cpu_to_le16(sizeof(*cmd)); 2090 cmd->action = cpu_to_le16(MWL8K_CMD_SET); 2091 cmd->current_channel = channel->hw_value; 2092 if (channel->band == IEEE80211_BAND_2GHZ) 2093 cmd->channel_flags = cpu_to_le32(0x00000081); 2094 else 2095 cmd->channel_flags = cpu_to_le32(0x00000000); 2096 2097 rc = mwl8k_post_cmd(hw, &cmd->header); 2098 kfree(cmd); 2099 2100 return rc; 2101} 2102 2103/* 2104 * CMD_SET_AID. 2105 */ 2106#define MWL8K_FRAME_PROT_DISABLED 0x00 2107#define MWL8K_FRAME_PROT_11G 0x07 2108#define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02 2109#define MWL8K_FRAME_PROT_11N_HT_ALL 0x06 2110 2111struct mwl8k_cmd_update_set_aid { 2112 struct mwl8k_cmd_pkt header; 2113 __le16 aid; 2114 2115 /* AP's MAC address (BSSID) */ 2116 __u8 bssid[ETH_ALEN]; 2117 __le16 protection_mode; 2118 __u8 supp_rates[14]; 2119} __attribute__((packed)); 2120 2121static int 2122mwl8k_cmd_set_aid(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 2123{ 2124 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif); 2125 struct mwl8k_cmd_update_set_aid *cmd; 2126 u16 prot_mode; 2127 int rc; 2128 2129 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); 2130 if (cmd == NULL) 2131 return -ENOMEM; 2132 2133 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID); 2134 cmd->header.length = cpu_to_le16(sizeof(*cmd)); 2135 cmd->aid = cpu_to_le16(vif->bss_conf.aid); 2136 2137 memcpy(cmd->bssid, mv_vif->bssid, ETH_ALEN); 2138 2139 if (vif->bss_conf.use_cts_prot) { 2140 prot_mode = MWL8K_FRAME_PROT_11G; 2141 } else { 2142 switch (vif->bss_conf.ht_operation_mode & 2143 IEEE80211_HT_OP_MODE_PROTECTION) { 2144 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ: 2145 prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY; 2146 break; 2147 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED: 2148 prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL; 2149 break; 2150 default: 2151 prot_mode = MWL8K_FRAME_PROT_DISABLED; 2152 break; 2153 } 2154 } 2155 cmd->protection_mode = cpu_to_le16(prot_mode); 2156 2157 memcpy(cmd->supp_rates, mwl8k_rateids, sizeof(mwl8k_rateids)); 2158 2159 rc = mwl8k_post_cmd(hw, &cmd->header); 2160 kfree(cmd); 2161 2162 return rc; 2163} 2164 2165/* 2166 * CMD_SET_RATE. 2167 */ 2168struct mwl8k_cmd_set_rate { 2169 struct mwl8k_cmd_pkt header; 2170 __u8 legacy_rates[14]; 2171 2172 /* Bitmap for supported MCS codes. */ 2173 __u8 mcs_set[16]; 2174 __u8 reserved[16]; 2175} __attribute__((packed)); 2176 2177static int 2178mwl8k_cmd_set_rate(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 2179{ 2180 struct mwl8k_cmd_set_rate *cmd; 2181 int rc; 2182 2183 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); 2184 if (cmd == NULL) 2185 return -ENOMEM; 2186 2187 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE); 2188 cmd->header.length = cpu_to_le16(sizeof(*cmd)); 2189 memcpy(cmd->legacy_rates, mwl8k_rateids, sizeof(mwl8k_rateids)); 2190 2191 rc = mwl8k_post_cmd(hw, &cmd->header); 2192 kfree(cmd); 2193 2194 return rc; 2195} 2196 2197/* 2198 * CMD_FINALIZE_JOIN. 2199 */ 2200#define MWL8K_FJ_BEACON_MAXLEN 128 2201 2202struct mwl8k_cmd_finalize_join { 2203 struct mwl8k_cmd_pkt header; 2204 __le32 sleep_interval; /* Number of beacon periods to sleep */ 2205 __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN]; 2206} __attribute__((packed)); 2207 2208static int mwl8k_cmd_finalize_join(struct ieee80211_hw *hw, void *frame, 2209 int framelen, int dtim) 2210{ 2211 struct mwl8k_cmd_finalize_join *cmd; 2212 struct ieee80211_mgmt *payload = frame; 2213 int payload_len; 2214 int rc; 2215 2216 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); 2217 if (cmd == NULL) 2218 return -ENOMEM; 2219 2220 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN); 2221 cmd->header.length = cpu_to_le16(sizeof(*cmd)); 2222 cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1); 2223 2224 payload_len = framelen - ieee80211_hdrlen(payload->frame_control); 2225 if (payload_len < 0) 2226 payload_len = 0; 2227 else if (payload_len > MWL8K_FJ_BEACON_MAXLEN) 2228 payload_len = MWL8K_FJ_BEACON_MAXLEN; 2229 2230 memcpy(cmd->beacon_data, &payload->u.beacon, payload_len); 2231 2232 rc = mwl8k_post_cmd(hw, &cmd->header); 2233 kfree(cmd); 2234 2235 return rc; 2236} 2237 2238/* 2239 * CMD_SET_RTS_THRESHOLD. 2240 */ 2241struct mwl8k_cmd_set_rts_threshold { 2242 struct mwl8k_cmd_pkt header; 2243 __le16 action; 2244 __le16 threshold; 2245} __attribute__((packed)); 2246 2247static int mwl8k_cmd_set_rts_threshold(struct ieee80211_hw *hw, 2248 u16 action, u16 threshold) 2249{ 2250 struct mwl8k_cmd_set_rts_threshold *cmd; 2251 int rc; 2252 2253 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); 2254 if (cmd == NULL) 2255 return -ENOMEM; 2256 2257 cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD); 2258 cmd->header.length = cpu_to_le16(sizeof(*cmd)); 2259 cmd->action = cpu_to_le16(action); 2260 cmd->threshold = cpu_to_le16(threshold); 2261 2262 rc = mwl8k_post_cmd(hw, &cmd->header); 2263 kfree(cmd); 2264 2265 return rc; 2266} 2267 2268/* 2269 * CMD_SET_SLOT. 2270 */ 2271struct mwl8k_cmd_set_slot { 2272 struct mwl8k_cmd_pkt header; 2273 __le16 action; 2274 __u8 short_slot; 2275} __attribute__((packed)); 2276 2277static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time) 2278{ 2279 struct mwl8k_cmd_set_slot *cmd; 2280 int rc; 2281 2282 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); 2283 if (cmd == NULL) 2284 return -ENOMEM; 2285 2286 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT); 2287 cmd->header.length = cpu_to_le16(sizeof(*cmd)); 2288 cmd->action = cpu_to_le16(MWL8K_CMD_SET); 2289 cmd->short_slot = short_slot_time; 2290 2291 rc = mwl8k_post_cmd(hw, &cmd->header); 2292 kfree(cmd); 2293 2294 return rc; 2295} 2296 2297/* 2298 * CMD_SET_EDCA_PARAMS. 2299 */ 2300struct mwl8k_cmd_set_edca_params { 2301 struct mwl8k_cmd_pkt header; 2302 2303 /* See MWL8K_SET_EDCA_XXX below */ 2304 __le16 action; 2305 2306 /* TX opportunity in units of 32 us */ 2307 __le16 txop; 2308 2309 union { 2310 struct { 2311 /* Log exponent of max contention period: 0...15 */ 2312 __le32 log_cw_max; 2313 2314 /* Log exponent of min contention period: 0...15 */ 2315 __le32 log_cw_min; 2316 2317 /* Adaptive interframe spacing in units of 32us */ 2318 __u8 aifs; 2319 2320 /* TX queue to configure */ 2321 __u8 txq; 2322 } ap; 2323 struct { 2324 /* Log exponent of max contention period: 0...15 */ 2325 __u8 log_cw_max; 2326 2327 /* Log exponent of min contention period: 0...15 */ 2328 __u8 log_cw_min; 2329 2330 /* Adaptive interframe spacing in units of 32us */ 2331 __u8 aifs; 2332 2333 /* TX queue to configure */ 2334 __u8 txq; 2335 } sta; 2336 }; 2337} __attribute__((packed)); 2338 2339#define MWL8K_SET_EDCA_CW 0x01 2340#define MWL8K_SET_EDCA_TXOP 0x02 2341#define MWL8K_SET_EDCA_AIFS 0x04 2342 2343#define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \ 2344 MWL8K_SET_EDCA_TXOP | \ 2345 MWL8K_SET_EDCA_AIFS) 2346 2347static int 2348mwl8k_cmd_set_edca_params(struct ieee80211_hw *hw, __u8 qnum, 2349 __u16 cw_min, __u16 cw_max, 2350 __u8 aifs, __u16 txop) 2351{ 2352 struct mwl8k_priv *priv = hw->priv; 2353 struct mwl8k_cmd_set_edca_params *cmd; 2354 int rc; 2355 2356 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); 2357 if (cmd == NULL) 2358 return -ENOMEM; 2359 2360 /* 2361 * Queues 0 (BE) and 1 (BK) are swapped in hardware for 2362 * this call. 2363 */ 2364 qnum ^= !(qnum >> 1); 2365 2366 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS); 2367 cmd->header.length = cpu_to_le16(sizeof(*cmd)); 2368 cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL); 2369 cmd->txop = cpu_to_le16(txop); 2370 if (priv->ap_fw) { 2371 cmd->ap.log_cw_max = cpu_to_le32(ilog2(cw_max + 1)); 2372 cmd->ap.log_cw_min = cpu_to_le32(ilog2(cw_min + 1)); 2373 cmd->ap.aifs = aifs; 2374 cmd->ap.txq = qnum; 2375 } else { 2376 cmd->sta.log_cw_max = (u8)ilog2(cw_max + 1); 2377 cmd->sta.log_cw_min = (u8)ilog2(cw_min + 1); 2378 cmd->sta.aifs = aifs; 2379 cmd->sta.txq = qnum; 2380 } 2381 2382 rc = mwl8k_post_cmd(hw, &cmd->header); 2383 kfree(cmd); 2384 2385 return rc; 2386} 2387 2388/* 2389 * CMD_SET_WMM_MODE. 2390 */ 2391struct mwl8k_cmd_set_wmm_mode { 2392 struct mwl8k_cmd_pkt header; 2393 __le16 action; 2394} __attribute__((packed)); 2395 2396static int mwl8k_cmd_set_wmm_mode(struct ieee80211_hw *hw, bool enable) 2397{ 2398 struct mwl8k_priv *priv = hw->priv; 2399 struct mwl8k_cmd_set_wmm_mode *cmd; 2400 int rc; 2401 2402 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); 2403 if (cmd == NULL) 2404 return -ENOMEM; 2405 2406 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE); 2407 cmd->header.length = cpu_to_le16(sizeof(*cmd)); 2408 cmd->action = cpu_to_le16(!!enable); 2409 2410 rc = mwl8k_post_cmd(hw, &cmd->header); 2411 kfree(cmd); 2412 2413 if (!rc) 2414 priv->wmm_enabled = enable; 2415 2416 return rc; 2417} 2418 2419/* 2420 * CMD_MIMO_CONFIG. 2421 */ 2422struct mwl8k_cmd_mimo_config { 2423 struct mwl8k_cmd_pkt header; 2424 __le32 action; 2425 __u8 rx_antenna_map; 2426 __u8 tx_antenna_map; 2427} __attribute__((packed)); 2428 2429static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx) 2430{ 2431 struct mwl8k_cmd_mimo_config *cmd; 2432 int rc; 2433 2434 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); 2435 if (cmd == NULL) 2436 return -ENOMEM; 2437 2438 cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG); 2439 cmd->header.length = cpu_to_le16(sizeof(*cmd)); 2440 cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET); 2441 cmd->rx_antenna_map = rx; 2442 cmd->tx_antenna_map = tx; 2443 2444 rc = mwl8k_post_cmd(hw, &cmd->header); 2445 kfree(cmd); 2446 2447 return rc; 2448} 2449 2450/* 2451 * CMD_USE_FIXED_RATE. 2452 */ 2453#define MWL8K_RATE_TABLE_SIZE 8 2454#define MWL8K_UCAST_RATE 0 2455#define MWL8K_USE_AUTO_RATE 0x0002 2456 2457struct mwl8k_rate_entry { 2458 /* Set to 1 if HT rate, 0 if legacy. */ 2459 __le32 is_ht_rate; 2460 2461 /* Set to 1 to use retry_count field. */ 2462 __le32 enable_retry; 2463 2464 /* Specified legacy rate or MCS. */ 2465 __le32 rate; 2466 2467 /* Number of allowed retries. */ 2468 __le32 retry_count; 2469} __attribute__((packed)); 2470 2471struct mwl8k_rate_table { 2472 /* 1 to allow specified rate and below */ 2473 __le32 allow_rate_drop; 2474 __le32 num_rates; 2475 struct mwl8k_rate_entry rate_entry[MWL8K_RATE_TABLE_SIZE]; 2476} __attribute__((packed)); 2477 2478struct mwl8k_cmd_use_fixed_rate { 2479 struct mwl8k_cmd_pkt header; 2480 __le32 action; 2481 struct mwl8k_rate_table rate_table; 2482 2483 /* Unicast, Broadcast or Multicast */ 2484 __le32 rate_type; 2485 __le32 reserved1; 2486 __le32 reserved2; 2487} __attribute__((packed)); 2488 2489static int mwl8k_cmd_use_fixed_rate(struct ieee80211_hw *hw, 2490 u32 action, u32 rate_type, struct mwl8k_rate_table *rate_table) 2491{ 2492 struct mwl8k_cmd_use_fixed_rate *cmd; 2493 int count; 2494 int rc; 2495 2496 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); 2497 if (cmd == NULL) 2498 return -ENOMEM; 2499 2500 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE); 2501 cmd->header.length = cpu_to_le16(sizeof(*cmd)); 2502 2503 cmd->action = cpu_to_le32(action); 2504 cmd->rate_type = cpu_to_le32(rate_type); 2505 2506 if (rate_table != NULL) { 2507 /* 2508 * Copy over each field manually so that endian 2509 * conversion can be done. 2510 */ 2511 cmd->rate_table.allow_rate_drop = 2512 cpu_to_le32(rate_table->allow_rate_drop); 2513 cmd->rate_table.num_rates = 2514 cpu_to_le32(rate_table->num_rates); 2515 2516 for (count = 0; count < rate_table->num_rates; count++) { 2517 struct mwl8k_rate_entry *dst = 2518 &cmd->rate_table.rate_entry[count]; 2519 struct mwl8k_rate_entry *src = 2520 &rate_table->rate_entry[count]; 2521 2522 dst->is_ht_rate = cpu_to_le32(src->is_ht_rate); 2523 dst->enable_retry = cpu_to_le32(src->enable_retry); 2524 dst->rate = cpu_to_le32(src->rate); 2525 dst->retry_count = cpu_to_le32(src->retry_count); 2526 } 2527 } 2528 2529 rc = mwl8k_post_cmd(hw, &cmd->header); 2530 kfree(cmd); 2531 2532 return rc; 2533} 2534 2535/* 2536 * CMD_ENABLE_SNIFFER. 2537 */ 2538struct mwl8k_cmd_enable_sniffer { 2539 struct mwl8k_cmd_pkt header; 2540 __le32 action; 2541} __attribute__((packed)); 2542 2543static int mwl8k_cmd_enable_sniffer(struct ieee80211_hw *hw, bool enable) 2544{ 2545 struct mwl8k_cmd_enable_sniffer *cmd; 2546 int rc; 2547 2548 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); 2549 if (cmd == NULL) 2550 return -ENOMEM; 2551 2552 cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER); 2553 cmd->header.length = cpu_to_le16(sizeof(*cmd)); 2554 cmd->action = cpu_to_le32(!!enable); 2555 2556 rc = mwl8k_post_cmd(hw, &cmd->header); 2557 kfree(cmd); 2558 2559 return rc; 2560} 2561 2562/* 2563 * CMD_SET_MAC_ADDR. 2564 */ 2565struct mwl8k_cmd_set_mac_addr { 2566 struct mwl8k_cmd_pkt header; 2567 union { 2568 struct { 2569 __le16 mac_type; 2570 __u8 mac_addr[ETH_ALEN]; 2571 } mbss; 2572 __u8 mac_addr[ETH_ALEN]; 2573 }; 2574} __attribute__((packed)); 2575 2576static int mwl8k_cmd_set_mac_addr(struct ieee80211_hw *hw, u8 *mac) 2577{ 2578 struct mwl8k_priv *priv = hw->priv; 2579 struct mwl8k_cmd_set_mac_addr *cmd; 2580 int rc; 2581 2582 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); 2583 if (cmd == NULL) 2584 return -ENOMEM; 2585 2586 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_MAC_ADDR); 2587 cmd->header.length = cpu_to_le16(sizeof(*cmd)); 2588 if (priv->ap_fw) { 2589 cmd->mbss.mac_type = 0; 2590 memcpy(cmd->mbss.mac_addr, mac, ETH_ALEN); 2591 } else { 2592 memcpy(cmd->mac_addr, mac, ETH_ALEN); 2593 } 2594 2595 rc = mwl8k_post_cmd(hw, &cmd->header); 2596 kfree(cmd); 2597 2598 return rc; 2599} 2600 2601/* 2602 * CMD_SET_RATEADAPT_MODE. 2603 */ 2604struct mwl8k_cmd_set_rate_adapt_mode { 2605 struct mwl8k_cmd_pkt header; 2606 __le16 action; 2607 __le16 mode; 2608} __attribute__((packed)); 2609 2610static int mwl8k_cmd_set_rateadapt_mode(struct ieee80211_hw *hw, __u16 mode) 2611{ 2612 struct mwl8k_cmd_set_rate_adapt_mode *cmd; 2613 int rc; 2614 2615 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); 2616 if (cmd == NULL) 2617 return -ENOMEM; 2618 2619 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE); 2620 cmd->header.length = cpu_to_le16(sizeof(*cmd)); 2621 cmd->action = cpu_to_le16(MWL8K_CMD_SET); 2622 cmd->mode = cpu_to_le16(mode); 2623 2624 rc = mwl8k_post_cmd(hw, &cmd->header); 2625 kfree(cmd); 2626 2627 return rc; 2628} 2629 2630/* 2631 * CMD_UPDATE_STADB. 2632 */ 2633struct mwl8k_cmd_update_stadb { 2634 struct mwl8k_cmd_pkt header; 2635 2636 /* See STADB_ACTION_TYPE */ 2637 __le32 action; 2638 2639 /* Peer MAC address */ 2640 __u8 peer_addr[ETH_ALEN]; 2641 2642 __le32 reserved; 2643 2644 /* Peer info - valid during add/update. */ 2645 struct peer_capability_info peer_info; 2646} __attribute__((packed)); 2647 2648static int mwl8k_cmd_update_stadb(struct ieee80211_hw *hw, 2649 struct ieee80211_vif *vif, __u32 action) 2650{ 2651 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif); 2652 struct mwl8k_cmd_update_stadb *cmd; 2653 struct peer_capability_info *peer_info; 2654 int rc; 2655 2656 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); 2657 if (cmd == NULL) 2658 return -ENOMEM; 2659 2660 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB); 2661 cmd->header.length = cpu_to_le16(sizeof(*cmd)); 2662 2663 cmd->action = cpu_to_le32(action); 2664 peer_info = &cmd->peer_info; 2665 memcpy(cmd->peer_addr, mv_vif->bssid, ETH_ALEN); 2666 2667 switch (action) { 2668 case MWL8K_STA_DB_ADD_ENTRY: 2669 case MWL8K_STA_DB_MODIFY_ENTRY: 2670 /* Build peer_info block */ 2671 peer_info->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT; 2672 peer_info->basic_caps = 2673 cpu_to_le16(vif->bss_conf.assoc_capability); 2674 memcpy(peer_info->legacy_rates, mwl8k_rateids, 2675 sizeof(mwl8k_rateids)); 2676 peer_info->interop = 1; 2677 peer_info->amsdu_enabled = 0; 2678 2679 rc = mwl8k_post_cmd(hw, &cmd->header); 2680 if (rc == 0) 2681 mv_vif->peer_id = peer_info->station_id; 2682 2683 break; 2684 2685 case MWL8K_STA_DB_DEL_ENTRY: 2686 case MWL8K_STA_DB_FLUSH: 2687 default: 2688 rc = mwl8k_post_cmd(hw, &cmd->header); 2689 if (rc == 0) 2690 mv_vif->peer_id = 0; 2691 break; 2692 } 2693 kfree(cmd); 2694 2695 return rc; 2696} 2697 2698 2699/* 2700 * Interrupt handling. 2701 */ 2702static irqreturn_t mwl8k_interrupt(int irq, void *dev_id) 2703{ 2704 struct ieee80211_hw *hw = dev_id; 2705 struct mwl8k_priv *priv = hw->priv; 2706 u32 status; 2707 2708 status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS); 2709 iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS); 2710 2711 if (!status) 2712 return IRQ_NONE; 2713 2714 if (status & MWL8K_A2H_INT_TX_DONE) 2715 tasklet_schedule(&priv->tx_reclaim_task); 2716 2717 if (status & MWL8K_A2H_INT_RX_READY) { 2718 while (rxq_process(hw, 0, 1)) 2719 rxq_refill(hw, 0, 1); 2720 } 2721 2722 if (status & MWL8K_A2H_INT_OPC_DONE) { 2723 if (priv->hostcmd_wait != NULL) 2724 complete(priv->hostcmd_wait); 2725 } 2726 2727 if (status & MWL8K_A2H_INT_QUEUE_EMPTY) { 2728 if (!mutex_is_locked(&priv->fw_mutex) && 2729 priv->radio_on && priv->pending_tx_pkts) 2730 mwl8k_tx_start(priv); 2731 } 2732 2733 return IRQ_HANDLED; 2734} 2735 2736 2737/* 2738 * Core driver operations. 2739 */ 2740static int mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb) 2741{ 2742 struct mwl8k_priv *priv = hw->priv; 2743 int index = skb_get_queue_mapping(skb); 2744 int rc; 2745 2746 if (priv->current_channel == NULL) { 2747 printk(KERN_DEBUG "%s: dropped TX frame since radio " 2748 "disabled\n", wiphy_name(hw->wiphy)); 2749 dev_kfree_skb(skb); 2750 return NETDEV_TX_OK; 2751 } 2752 2753 rc = mwl8k_txq_xmit(hw, index, skb); 2754 2755 return rc; 2756} 2757 2758static int mwl8k_start(struct ieee80211_hw *hw) 2759{ 2760 struct mwl8k_priv *priv = hw->priv; 2761 int rc; 2762 2763 rc = request_irq(priv->pdev->irq, mwl8k_interrupt, 2764 IRQF_SHARED, MWL8K_NAME, hw); 2765 if (rc) { 2766 printk(KERN_ERR "%s: failed to register IRQ handler\n", 2767 wiphy_name(hw->wiphy)); 2768 return -EIO; 2769 } 2770 2771 /* Enable tx reclaim tasklet */ 2772 tasklet_enable(&priv->tx_reclaim_task); 2773 2774 /* Enable interrupts */ 2775 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK); 2776 2777 rc = mwl8k_fw_lock(hw); 2778 if (!rc) { 2779 rc = mwl8k_cmd_radio_enable(hw); 2780 2781 if (!priv->ap_fw) { 2782 if (!rc) 2783 rc = mwl8k_cmd_enable_sniffer(hw, 0); 2784 2785 if (!rc) 2786 rc = mwl8k_cmd_set_pre_scan(hw); 2787 2788 if (!rc) 2789 rc = mwl8k_cmd_set_post_scan(hw, 2790 "\x00\x00\x00\x00\x00\x00"); 2791 } 2792 2793 if (!rc) 2794 rc = mwl8k_cmd_set_rateadapt_mode(hw, 0); 2795 2796 if (!rc) 2797 rc = mwl8k_cmd_set_wmm_mode(hw, 0); 2798 2799 mwl8k_fw_unlock(hw); 2800 } 2801 2802 if (rc) { 2803 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK); 2804 free_irq(priv->pdev->irq, hw); 2805 tasklet_disable(&priv->tx_reclaim_task); 2806 } 2807 2808 return rc; 2809} 2810 2811static void mwl8k_stop(struct ieee80211_hw *hw) 2812{ 2813 struct mwl8k_priv *priv = hw->priv; 2814 int i; 2815 2816 mwl8k_cmd_radio_disable(hw); 2817 2818 ieee80211_stop_queues(hw); 2819 2820 /* Disable interrupts */ 2821 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK); 2822 free_irq(priv->pdev->irq, hw); 2823 2824 /* Stop finalize join worker */ 2825 cancel_work_sync(&priv->finalize_join_worker); 2826 if (priv->beacon_skb != NULL) 2827 dev_kfree_skb(priv->beacon_skb); 2828 2829 /* Stop tx reclaim tasklet */ 2830 tasklet_disable(&priv->tx_reclaim_task); 2831 2832 /* Return all skbs to mac80211 */ 2833 for (i = 0; i < MWL8K_TX_QUEUES; i++) 2834 mwl8k_txq_reclaim(hw, i, 1); 2835} 2836 2837static int mwl8k_add_interface(struct ieee80211_hw *hw, 2838 struct ieee80211_if_init_conf *conf) 2839{ 2840 struct mwl8k_priv *priv = hw->priv; 2841 struct mwl8k_vif *mwl8k_vif; 2842 2843 /* 2844 * We only support one active interface at a time. 2845 */ 2846 if (priv->vif != NULL) 2847 return -EBUSY; 2848 2849 /* 2850 * We only support managed interfaces for now. 2851 */ 2852 if (conf->type != NL80211_IFTYPE_STATION) 2853 return -EINVAL; 2854 2855 /* 2856 * Reject interface creation if sniffer mode is active, as 2857 * STA operation is mutually exclusive with hardware sniffer 2858 * mode. 2859 */ 2860 if (priv->sniffer_enabled) { 2861 printk(KERN_INFO "%s: unable to create STA " 2862 "interface due to sniffer mode being enabled\n", 2863 wiphy_name(hw->wiphy)); 2864 return -EINVAL; 2865 } 2866 2867 /* Clean out driver private area */ 2868 mwl8k_vif = MWL8K_VIF(conf->vif); 2869 memset(mwl8k_vif, 0, sizeof(*mwl8k_vif)); 2870 2871 /* Set and save the mac address */ 2872 mwl8k_cmd_set_mac_addr(hw, conf->mac_addr); 2873 memcpy(mwl8k_vif->mac_addr, conf->mac_addr, ETH_ALEN); 2874 2875 /* Set Initial sequence number to zero */ 2876 mwl8k_vif->seqno = 0; 2877 2878 priv->vif = conf->vif; 2879 priv->current_channel = NULL; 2880 2881 return 0; 2882} 2883 2884static void mwl8k_remove_interface(struct ieee80211_hw *hw, 2885 struct ieee80211_if_init_conf *conf) 2886{ 2887 struct mwl8k_priv *priv = hw->priv; 2888 2889 if (priv->vif == NULL) 2890 return; 2891 2892 mwl8k_cmd_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00"); 2893 2894 priv->vif = NULL; 2895} 2896 2897static int mwl8k_config(struct ieee80211_hw *hw, u32 changed) 2898{ 2899 struct ieee80211_conf *conf = &hw->conf; 2900 struct mwl8k_priv *priv = hw->priv; 2901 int rc; 2902 2903 if (conf->flags & IEEE80211_CONF_IDLE) { 2904 mwl8k_cmd_radio_disable(hw); 2905 priv->current_channel = NULL; 2906 return 0; 2907 } 2908 2909 rc = mwl8k_fw_lock(hw); 2910 if (rc) 2911 return rc; 2912 2913 rc = mwl8k_cmd_radio_enable(hw); 2914 if (rc) 2915 goto out; 2916 2917 rc = mwl8k_cmd_set_rf_channel(hw, conf->channel); 2918 if (rc) 2919 goto out; 2920 2921 priv->current_channel = conf->channel; 2922 2923 if (conf->power_level > 18) 2924 conf->power_level = 18; 2925 rc = mwl8k_cmd_rf_tx_power(hw, conf->power_level); 2926 if (rc) 2927 goto out; 2928 2929 if (priv->ap_fw) { 2930 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_RX, 0x7); 2931 if (!rc) 2932 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_TX, 0x7); 2933 } else { 2934 rc = mwl8k_cmd_mimo_config(hw, 0x7, 0x7); 2935 } 2936 2937out: 2938 mwl8k_fw_unlock(hw); 2939 2940 return rc; 2941} 2942 2943static void mwl8k_bss_info_changed(struct ieee80211_hw *hw, 2944 struct ieee80211_vif *vif, 2945 struct ieee80211_bss_conf *info, 2946 u32 changed) 2947{ 2948 struct mwl8k_priv *priv = hw->priv; 2949 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif); 2950 int rc; 2951 2952 if ((changed & BSS_CHANGED_ASSOC) == 0) 2953 return; 2954 2955 priv->capture_beacon = false; 2956 2957 rc = mwl8k_fw_lock(hw); 2958 if (rc) 2959 return; 2960 2961 if (vif->bss_conf.assoc) { 2962 memcpy(mwl8k_vif->bssid, vif->bss_conf.bssid, ETH_ALEN); 2963 2964 /* Install rates */ 2965 rc = mwl8k_cmd_set_rate(hw, vif); 2966 if (rc) 2967 goto out; 2968 2969 /* Turn on rate adaptation */ 2970 rc = mwl8k_cmd_use_fixed_rate(hw, MWL8K_USE_AUTO_RATE, 2971 MWL8K_UCAST_RATE, NULL); 2972 if (rc) 2973 goto out; 2974 2975 /* Set radio preamble */ 2976 rc = mwl8k_set_radio_preamble(hw, 2977 vif->bss_conf.use_short_preamble); 2978 if (rc) 2979 goto out; 2980 2981 /* Set slot time */ 2982 rc = mwl8k_cmd_set_slot(hw, vif->bss_conf.use_short_slot); 2983 if (rc) 2984 goto out; 2985 2986 /* Update peer rate info */ 2987 rc = mwl8k_cmd_update_stadb(hw, vif, 2988 MWL8K_STA_DB_MODIFY_ENTRY); 2989 if (rc) 2990 goto out; 2991 2992 /* Set AID */ 2993 rc = mwl8k_cmd_set_aid(hw, vif); 2994 if (rc) 2995 goto out; 2996 2997 /* 2998 * Finalize the join. Tell rx handler to process 2999 * next beacon from our BSSID. 3000 */ 3001 memcpy(priv->capture_bssid, mwl8k_vif->bssid, ETH_ALEN); 3002 priv->capture_beacon = true; 3003 } else { 3004 rc = mwl8k_cmd_update_stadb(hw, vif, MWL8K_STA_DB_DEL_ENTRY); 3005 memset(mwl8k_vif->bssid, 0, ETH_ALEN); 3006 } 3007 3008out: 3009 mwl8k_fw_unlock(hw); 3010} 3011 3012static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw, 3013 int mc_count, struct dev_addr_list *mclist) 3014{ 3015 struct mwl8k_cmd_pkt *cmd; 3016 3017 /* 3018 * Synthesize and return a command packet that programs the 3019 * hardware multicast address filter. At this point we don't 3020 * know whether FIF_ALLMULTI is being requested, but if it is, 3021 * we'll end up throwing this packet away and creating a new 3022 * one in mwl8k_configure_filter(). 3023 */ 3024 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 0, mc_count, mclist); 3025 3026 return (unsigned long)cmd; 3027} 3028 3029static int 3030mwl8k_configure_filter_sniffer(struct ieee80211_hw *hw, 3031 unsigned int changed_flags, 3032 unsigned int *total_flags) 3033{ 3034 struct mwl8k_priv *priv = hw->priv; 3035 3036 /* 3037 * Hardware sniffer mode is mutually exclusive with STA 3038 * operation, so refuse to enable sniffer mode if a STA 3039 * interface is active. 3040 */ 3041 if (priv->vif != NULL) { 3042 if (net_ratelimit()) 3043 printk(KERN_INFO "%s: not enabling sniffer " 3044 "mode because STA interface is active\n", 3045 wiphy_name(hw->wiphy)); 3046 return 0; 3047 } 3048 3049 if (!priv->sniffer_enabled) { 3050 if (mwl8k_cmd_enable_sniffer(hw, 1)) 3051 return 0; 3052 priv->sniffer_enabled = true; 3053 } 3054 3055 *total_flags &= FIF_PROMISC_IN_BSS | FIF_ALLMULTI | 3056 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL | 3057 FIF_OTHER_BSS; 3058 3059 return 1; 3060} 3061 3062static void mwl8k_configure_filter(struct ieee80211_hw *hw, 3063 unsigned int changed_flags, 3064 unsigned int *total_flags, 3065 u64 multicast) 3066{ 3067 struct mwl8k_priv *priv = hw->priv; 3068 struct mwl8k_cmd_pkt *cmd = (void *)(unsigned long)multicast; 3069 3070 /* 3071 * AP firmware doesn't allow fine-grained control over 3072 * the receive filter. 3073 */ 3074 if (priv->ap_fw) { 3075 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC; 3076 kfree(cmd); 3077 return; 3078 } 3079 3080 /* 3081 * Enable hardware sniffer mode if FIF_CONTROL or 3082 * FIF_OTHER_BSS is requested. 3083 */ 3084 if (*total_flags & (FIF_CONTROL | FIF_OTHER_BSS) && 3085 mwl8k_configure_filter_sniffer(hw, changed_flags, total_flags)) { 3086 kfree(cmd); 3087 return; 3088 } 3089 3090 /* Clear unsupported feature flags */ 3091 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC; 3092 3093 if (mwl8k_fw_lock(hw)) 3094 return; 3095 3096 if (priv->sniffer_enabled) { 3097 mwl8k_cmd_enable_sniffer(hw, 0); 3098 priv->sniffer_enabled = false; 3099 } 3100 3101 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) { 3102 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) { 3103 /* 3104 * Disable the BSS filter. 3105 */ 3106 mwl8k_cmd_set_pre_scan(hw); 3107 } else { 3108 u8 *bssid; 3109 3110 /* 3111 * Enable the BSS filter. 3112 * 3113 * If there is an active STA interface, use that 3114 * interface's BSSID, otherwise use a dummy one 3115 * (where the OUI part needs to be nonzero for 3116 * the BSSID to be accepted by POST_SCAN). 3117 */ 3118 bssid = "\x01\x00\x00\x00\x00\x00"; 3119 if (priv->vif != NULL) 3120 bssid = MWL8K_VIF(priv->vif)->bssid; 3121 3122 mwl8k_cmd_set_post_scan(hw, bssid); 3123 } 3124 } 3125 3126 /* 3127 * If FIF_ALLMULTI is being requested, throw away the command 3128 * packet that ->prepare_multicast() built and replace it with 3129 * a command packet that enables reception of all multicast 3130 * packets. 3131 */ 3132 if (*total_flags & FIF_ALLMULTI) { 3133 kfree(cmd); 3134 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 1, 0, NULL); 3135 } 3136 3137 if (cmd != NULL) { 3138 mwl8k_post_cmd(hw, cmd); 3139 kfree(cmd); 3140 } 3141 3142 mwl8k_fw_unlock(hw); 3143} 3144 3145static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value) 3146{ 3147 return mwl8k_cmd_set_rts_threshold(hw, MWL8K_CMD_SET, value); 3148} 3149 3150static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue, 3151 const struct ieee80211_tx_queue_params *params) 3152{ 3153 struct mwl8k_priv *priv = hw->priv; 3154 int rc; 3155 3156 rc = mwl8k_fw_lock(hw); 3157 if (!rc) { 3158 if (!priv->wmm_enabled) 3159 rc = mwl8k_cmd_set_wmm_mode(hw, 1); 3160 3161 if (!rc) 3162 rc = mwl8k_cmd_set_edca_params(hw, queue, 3163 params->cw_min, 3164 params->cw_max, 3165 params->aifs, 3166 params->txop); 3167 3168 mwl8k_fw_unlock(hw); 3169 } 3170 3171 return rc; 3172} 3173 3174static int mwl8k_get_tx_stats(struct ieee80211_hw *hw, 3175 struct ieee80211_tx_queue_stats *stats) 3176{ 3177 struct mwl8k_priv *priv = hw->priv; 3178 struct mwl8k_tx_queue *txq; 3179 int index; 3180 3181 spin_lock_bh(&priv->tx_lock); 3182 for (index = 0; index < MWL8K_TX_QUEUES; index++) { 3183 txq = priv->txq + index; 3184 memcpy(&stats[index], &txq->stats, 3185 sizeof(struct ieee80211_tx_queue_stats)); 3186 } 3187 spin_unlock_bh(&priv->tx_lock); 3188 3189 return 0; 3190} 3191 3192static int mwl8k_get_stats(struct ieee80211_hw *hw, 3193 struct ieee80211_low_level_stats *stats) 3194{ 3195 return mwl8k_cmd_get_stat(hw, stats); 3196} 3197 3198static const struct ieee80211_ops mwl8k_ops = { 3199 .tx = mwl8k_tx, 3200 .start = mwl8k_start, 3201 .stop = mwl8k_stop, 3202 .add_interface = mwl8k_add_interface, 3203 .remove_interface = mwl8k_remove_interface, 3204 .config = mwl8k_config, 3205 .bss_info_changed = mwl8k_bss_info_changed, 3206 .prepare_multicast = mwl8k_prepare_multicast, 3207 .configure_filter = mwl8k_configure_filter, 3208 .set_rts_threshold = mwl8k_set_rts_threshold, 3209 .conf_tx = mwl8k_conf_tx, 3210 .get_tx_stats = mwl8k_get_tx_stats, 3211 .get_stats = mwl8k_get_stats, 3212}; 3213 3214static void mwl8k_tx_reclaim_handler(unsigned long data) 3215{ 3216 int i; 3217 struct ieee80211_hw *hw = (struct ieee80211_hw *) data; 3218 struct mwl8k_priv *priv = hw->priv; 3219 3220 spin_lock_bh(&priv->tx_lock); 3221 for (i = 0; i < MWL8K_TX_QUEUES; i++) 3222 mwl8k_txq_reclaim(hw, i, 0); 3223 3224 if (priv->tx_wait != NULL && !priv->pending_tx_pkts) { 3225 complete(priv->tx_wait); 3226 priv->tx_wait = NULL; 3227 } 3228 spin_unlock_bh(&priv->tx_lock); 3229} 3230 3231static void mwl8k_finalize_join_worker(struct work_struct *work) 3232{ 3233 struct mwl8k_priv *priv = 3234 container_of(work, struct mwl8k_priv, finalize_join_worker); 3235 struct sk_buff *skb = priv->beacon_skb; 3236 3237 mwl8k_cmd_finalize_join(priv->hw, skb->data, skb->len, 3238 priv->vif->bss_conf.dtim_period); 3239 dev_kfree_skb(skb); 3240 3241 priv->beacon_skb = NULL; 3242} 3243 3244enum { 3245 MWL8687 = 0, 3246 MWL8366, 3247}; 3248 3249static struct mwl8k_device_info mwl8k_info_tbl[] __devinitdata = { 3250 [MWL8687] = { 3251 .part_name = "88w8687", 3252 .helper_image = "mwl8k/helper_8687.fw", 3253 .fw_image = "mwl8k/fmimage_8687.fw", 3254 }, 3255 [MWL8366] = { 3256 .part_name = "88w8366", 3257 .helper_image = "mwl8k/helper_8366.fw", 3258 .fw_image = "mwl8k/fmimage_8366.fw", 3259 .ap_rxd_ops = &rxd_8366_ap_ops, 3260 }, 3261}; 3262 3263static DEFINE_PCI_DEVICE_TABLE(mwl8k_pci_id_table) = { 3264 { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = MWL8687, }, 3265 { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = MWL8687, }, 3266 { PCI_VDEVICE(MARVELL, 0x2a40), .driver_data = MWL8366, }, 3267 { }, 3268}; 3269MODULE_DEVICE_TABLE(pci, mwl8k_pci_id_table); 3270 3271static int __devinit mwl8k_probe(struct pci_dev *pdev, 3272 const struct pci_device_id *id) 3273{ 3274 static int printed_version = 0; 3275 struct ieee80211_hw *hw; 3276 struct mwl8k_priv *priv; 3277 int rc; 3278 int i; 3279 3280 if (!printed_version) { 3281 printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION); 3282 printed_version = 1; 3283 } 3284 3285 3286 rc = pci_enable_device(pdev); 3287 if (rc) { 3288 printk(KERN_ERR "%s: Cannot enable new PCI device\n", 3289 MWL8K_NAME); 3290 return rc; 3291 } 3292 3293 rc = pci_request_regions(pdev, MWL8K_NAME); 3294 if (rc) { 3295 printk(KERN_ERR "%s: Cannot obtain PCI resources\n", 3296 MWL8K_NAME); 3297 goto err_disable_device; 3298 } 3299 3300 pci_set_master(pdev); 3301 3302 3303 hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops); 3304 if (hw == NULL) { 3305 printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME); 3306 rc = -ENOMEM; 3307 goto err_free_reg; 3308 } 3309 3310 SET_IEEE80211_DEV(hw, &pdev->dev); 3311 pci_set_drvdata(pdev, hw); 3312 3313 priv = hw->priv; 3314 priv->hw = hw; 3315 priv->pdev = pdev; 3316 priv->device_info = &mwl8k_info_tbl[id->driver_data]; 3317 3318 3319 priv->sram = pci_iomap(pdev, 0, 0x10000); 3320 if (priv->sram == NULL) { 3321 printk(KERN_ERR "%s: Cannot map device SRAM\n", 3322 wiphy_name(hw->wiphy)); 3323 goto err_iounmap; 3324 } 3325 3326 /* 3327 * If BAR0 is a 32 bit BAR, the register BAR will be BAR1. 3328 * If BAR0 is a 64 bit BAR, the register BAR will be BAR2. 3329 */ 3330 priv->regs = pci_iomap(pdev, 1, 0x10000); 3331 if (priv->regs == NULL) { 3332 priv->regs = pci_iomap(pdev, 2, 0x10000); 3333 if (priv->regs == NULL) { 3334 printk(KERN_ERR "%s: Cannot map device registers\n", 3335 wiphy_name(hw->wiphy)); 3336 goto err_iounmap; 3337 } 3338 } 3339 3340 3341 /* Reset firmware and hardware */ 3342 mwl8k_hw_reset(priv); 3343 3344 /* Ask userland hotplug daemon for the device firmware */ 3345 rc = mwl8k_request_firmware(priv); 3346 if (rc) { 3347 printk(KERN_ERR "%s: Firmware files not found\n", 3348 wiphy_name(hw->wiphy)); 3349 goto err_stop_firmware; 3350 } 3351 3352 /* Load firmware into hardware */ 3353 rc = mwl8k_load_firmware(hw); 3354 if (rc) { 3355 printk(KERN_ERR "%s: Cannot start firmware\n", 3356 wiphy_name(hw->wiphy)); 3357 goto err_stop_firmware; 3358 } 3359 3360 /* Reclaim memory once firmware is successfully loaded */ 3361 mwl8k_release_firmware(priv); 3362 3363 3364 if (priv->ap_fw) 3365 priv->rxd_ops = priv->device_info->ap_rxd_ops; 3366 else 3367 priv->rxd_ops = &rxd_sta_ops; 3368 3369 priv->sniffer_enabled = false; 3370 priv->wmm_enabled = false; 3371 priv->pending_tx_pkts = 0; 3372 3373 3374 memcpy(priv->channels, mwl8k_channels, sizeof(mwl8k_channels)); 3375 priv->band.band = IEEE80211_BAND_2GHZ; 3376 priv->band.channels = priv->channels; 3377 priv->band.n_channels = ARRAY_SIZE(mwl8k_channels); 3378 priv->band.bitrates = priv->rates; 3379 priv->band.n_bitrates = ARRAY_SIZE(mwl8k_rates); 3380 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band; 3381 3382 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(mwl8k_rates)); 3383 memcpy(priv->rates, mwl8k_rates, sizeof(mwl8k_rates)); 3384 3385 /* 3386 * Extra headroom is the size of the required DMA header 3387 * minus the size of the smallest 802.11 frame (CTS frame). 3388 */ 3389 hw->extra_tx_headroom = 3390 sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts); 3391 3392 hw->channel_change_time = 10; 3393 3394 hw->queues = MWL8K_TX_QUEUES; 3395 3396 /* Set rssi and noise values to dBm */ 3397 hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_NOISE_DBM; 3398 hw->vif_data_size = sizeof(struct mwl8k_vif); 3399 priv->vif = NULL; 3400 3401 /* Set default radio state and preamble */ 3402 priv->radio_on = 0; 3403 priv->radio_short_preamble = 0; 3404 3405 /* Finalize join worker */ 3406 INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker); 3407 3408 /* TX reclaim tasklet */ 3409 tasklet_init(&priv->tx_reclaim_task, 3410 mwl8k_tx_reclaim_handler, (unsigned long)hw); 3411 tasklet_disable(&priv->tx_reclaim_task); 3412 3413 /* Power management cookie */ 3414 priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma); 3415 if (priv->cookie == NULL) 3416 goto err_stop_firmware; 3417 3418 rc = mwl8k_rxq_init(hw, 0); 3419 if (rc) 3420 goto err_free_cookie; 3421 rxq_refill(hw, 0, INT_MAX); 3422 3423 mutex_init(&priv->fw_mutex); 3424 priv->fw_mutex_owner = NULL; 3425 priv->fw_mutex_depth = 0; 3426 priv->hostcmd_wait = NULL; 3427 3428 spin_lock_init(&priv->tx_lock); 3429 3430 priv->tx_wait = NULL; 3431 3432 for (i = 0; i < MWL8K_TX_QUEUES; i++) { 3433 rc = mwl8k_txq_init(hw, i); 3434 if (rc) 3435 goto err_free_queues; 3436 } 3437 3438 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS); 3439 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK); 3440 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL); 3441 iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK); 3442 3443 rc = request_irq(priv->pdev->irq, mwl8k_interrupt, 3444 IRQF_SHARED, MWL8K_NAME, hw); 3445 if (rc) { 3446 printk(KERN_ERR "%s: failed to register IRQ handler\n", 3447 wiphy_name(hw->wiphy)); 3448 goto err_free_queues; 3449 } 3450 3451 /* 3452 * Temporarily enable interrupts. Initial firmware host 3453 * commands use interrupts and avoids polling. Disable 3454 * interrupts when done. 3455 */ 3456 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK); 3457 3458 /* Get config data, mac addrs etc */ 3459 if (priv->ap_fw) { 3460 rc = mwl8k_cmd_get_hw_spec_ap(hw); 3461 if (!rc) 3462 rc = mwl8k_cmd_set_hw_spec(hw); 3463 } else { 3464 rc = mwl8k_cmd_get_hw_spec_sta(hw); 3465 3466 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION); 3467 } 3468 if (rc) { 3469 printk(KERN_ERR "%s: Cannot initialise firmware\n", 3470 wiphy_name(hw->wiphy)); 3471 goto err_free_irq; 3472 } 3473 3474 /* Turn radio off */ 3475 rc = mwl8k_cmd_radio_disable(hw); 3476 if (rc) { 3477 printk(KERN_ERR "%s: Cannot disable\n", wiphy_name(hw->wiphy)); 3478 goto err_free_irq; 3479 } 3480 3481 /* Clear MAC address */ 3482 rc = mwl8k_cmd_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00"); 3483 if (rc) { 3484 printk(KERN_ERR "%s: Cannot clear MAC address\n", 3485 wiphy_name(hw->wiphy)); 3486 goto err_free_irq; 3487 } 3488 3489 /* Disable interrupts */ 3490 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK); 3491 free_irq(priv->pdev->irq, hw); 3492 3493 rc = ieee80211_register_hw(hw); 3494 if (rc) { 3495 printk(KERN_ERR "%s: Cannot register device\n", 3496 wiphy_name(hw->wiphy)); 3497 goto err_free_irq; 3498 } 3499 3500 printk(KERN_INFO "%s: %s v%d, %pM, %s firmware %u.%u.%u.%u\n", 3501 wiphy_name(hw->wiphy), priv->device_info->part_name, 3502 priv->hw_rev, hw->wiphy->perm_addr, 3503 priv->ap_fw ? "AP" : "STA", 3504 (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff, 3505 (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff); 3506 3507 return 0; 3508 3509err_free_irq: 3510 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK); 3511 free_irq(priv->pdev->irq, hw); 3512 3513err_free_queues: 3514 for (i = 0; i < MWL8K_TX_QUEUES; i++) 3515 mwl8k_txq_deinit(hw, i); 3516 mwl8k_rxq_deinit(hw, 0); 3517 3518err_free_cookie: 3519 if (priv->cookie != NULL) 3520 pci_free_consistent(priv->pdev, 4, 3521 priv->cookie, priv->cookie_dma); 3522 3523err_stop_firmware: 3524 mwl8k_hw_reset(priv); 3525 mwl8k_release_firmware(priv); 3526 3527err_iounmap: 3528 if (priv->regs != NULL) 3529 pci_iounmap(pdev, priv->regs); 3530 3531 if (priv->sram != NULL) 3532 pci_iounmap(pdev, priv->sram); 3533 3534 pci_set_drvdata(pdev, NULL); 3535 ieee80211_free_hw(hw); 3536 3537err_free_reg: 3538 pci_release_regions(pdev); 3539 3540err_disable_device: 3541 pci_disable_device(pdev); 3542 3543 return rc; 3544} 3545 3546static void __devexit mwl8k_shutdown(struct pci_dev *pdev) 3547{ 3548 printk(KERN_ERR "===>%s(%u)\n", __func__, __LINE__); 3549} 3550 3551static void __devexit mwl8k_remove(struct pci_dev *pdev) 3552{ 3553 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 3554 struct mwl8k_priv *priv; 3555 int i; 3556 3557 if (hw == NULL) 3558 return; 3559 priv = hw->priv; 3560 3561 ieee80211_stop_queues(hw); 3562 3563 ieee80211_unregister_hw(hw); 3564 3565 /* Remove tx reclaim tasklet */ 3566 tasklet_kill(&priv->tx_reclaim_task); 3567 3568 /* Stop hardware */ 3569 mwl8k_hw_reset(priv); 3570 3571 /* Return all skbs to mac80211 */ 3572 for (i = 0; i < MWL8K_TX_QUEUES; i++) 3573 mwl8k_txq_reclaim(hw, i, 1); 3574 3575 for (i = 0; i < MWL8K_TX_QUEUES; i++) 3576 mwl8k_txq_deinit(hw, i); 3577 3578 mwl8k_rxq_deinit(hw, 0); 3579 3580 pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma); 3581 3582 pci_iounmap(pdev, priv->regs); 3583 pci_iounmap(pdev, priv->sram); 3584 pci_set_drvdata(pdev, NULL); 3585 ieee80211_free_hw(hw); 3586 pci_release_regions(pdev); 3587 pci_disable_device(pdev); 3588} 3589 3590static struct pci_driver mwl8k_driver = { 3591 .name = MWL8K_NAME, 3592 .id_table = mwl8k_pci_id_table, 3593 .probe = mwl8k_probe, 3594 .remove = __devexit_p(mwl8k_remove), 3595 .shutdown = __devexit_p(mwl8k_shutdown), 3596}; 3597 3598static int __init mwl8k_init(void) 3599{ 3600 return pci_register_driver(&mwl8k_driver); 3601} 3602 3603static void __exit mwl8k_exit(void) 3604{ 3605 pci_unregister_driver(&mwl8k_driver); 3606} 3607 3608module_init(mwl8k_init); 3609module_exit(mwl8k_exit); 3610 3611MODULE_DESCRIPTION(MWL8K_DESC); 3612MODULE_VERSION(MWL8K_VERSION); 3613MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>"); 3614MODULE_LICENSE("GPL"); 3615