1eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu#ifndef NET2280_H 2eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu#define NET2280_H 3eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu/* 4eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu * NetChip 2280 high/full speed USB device controller. 5eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu * Unlike many such controllers, this one talks PCI. 6eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu */ 7eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu 8eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu/* 9eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu * Copyright (C) 2002 NetChip Technology, Inc. (http://www.netchip.com) 10eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu * Copyright (C) 2003 David Brownell 11eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu * 12eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu * This program is free software; you can redistribute it and/or modify 13eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu * it under the terms of the GNU General Public License as published by 14eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu * the Free Software Foundation; either version 2 of the License, or 15eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu * (at your option) any later version. 16eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu * 17eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu * This program is distributed in the hope that it will be useful, 18eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu * but WITHOUT ANY WARRANTY; without even the implied warranty of 19eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu * GNU General Public License for more details. 21eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu * 22eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu * You should have received a copy of the GNU General Public License 2336769159a99063ba4d3cb0a20ed0b3095a334c8cJeff Kirsher * along with this program; if not, see <http://www.gnu.org/licenses/>. 24eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu */ 25eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu 26eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu/*-------------------------------------------------------------------------*/ 27eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu 28eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu/* NET2280 MEMORY MAPPED REGISTERS 29eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu * 30eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu * The register layout came from the chip documentation, and the bit 31eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu * number definitions were extracted from chip specification. 32eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu * 33eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu * Use the shift operator ('<<') to build bit masks, with readl/writel 34eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu * to access the registers through PCI. 35eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu */ 36eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu 37eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu/* main registers, BAR0 + 0x0000 */ 38eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wustruct net2280_regs { 39cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter /* offset 0x0000 */ 40cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter __le32 devinit; 41cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define LOCAL_CLOCK_FREQUENCY 8 42cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define FORCE_PCI_RESET 7 43cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define PCI_ID 6 44cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define PCI_ENABLE 5 45cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define FIFO_SOFT_RESET 4 46cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define CFG_SOFT_RESET 3 47cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define PCI_SOFT_RESET 2 48cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define USB_SOFT_RESET 1 49cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define M8051_RESET 0 50cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter __le32 eectl; 51cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define EEPROM_ADDRESS_WIDTH 23 52cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define EEPROM_CHIP_SELECT_ACTIVE 22 53cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define EEPROM_PRESENT 21 54cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define EEPROM_VALID 20 55cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define EEPROM_BUSY 19 56cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define EEPROM_CHIP_SELECT_ENABLE 18 57cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define EEPROM_BYTE_READ_START 17 58cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define EEPROM_BYTE_WRITE_START 16 59cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define EEPROM_READ_DATA 8 60cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define EEPROM_WRITE_DATA 0 61cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter __le32 eeclkfreq; 62cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter u32 _unused0; 63cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter /* offset 0x0010 */ 64eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu 65cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter __le32 pciirqenb0; /* interrupt PCI master ... */ 66cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define SETUP_PACKET_INTERRUPT_ENABLE 7 67cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define ENDPOINT_F_INTERRUPT_ENABLE 6 68cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define ENDPOINT_E_INTERRUPT_ENABLE 5 69cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define ENDPOINT_D_INTERRUPT_ENABLE 4 70cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define ENDPOINT_C_INTERRUPT_ENABLE 3 71cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define ENDPOINT_B_INTERRUPT_ENABLE 2 72cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define ENDPOINT_A_INTERRUPT_ENABLE 1 73cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define ENDPOINT_0_INTERRUPT_ENABLE 0 74cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter __le32 pciirqenb1; 75cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define PCI_INTERRUPT_ENABLE 31 76cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define POWER_STATE_CHANGE_INTERRUPT_ENABLE 27 77cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define PCI_ARBITER_TIMEOUT_INTERRUPT_ENABLE 26 78cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define PCI_PARITY_ERROR_INTERRUPT_ENABLE 25 79cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define PCI_MASTER_ABORT_RECEIVED_INTERRUPT_ENABLE 20 80cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define PCI_TARGET_ABORT_RECEIVED_INTERRUPT_ENABLE 19 81cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define PCI_TARGET_ABORT_ASSERTED_INTERRUPT_ENABLE 18 82cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define PCI_RETRY_ABORT_INTERRUPT_ENABLE 17 83cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define PCI_MASTER_CYCLE_DONE_INTERRUPT_ENABLE 16 84cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define GPIO_INTERRUPT_ENABLE 13 85cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define DMA_D_INTERRUPT_ENABLE 12 86cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define DMA_C_INTERRUPT_ENABLE 11 87cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define DMA_B_INTERRUPT_ENABLE 10 88cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define DMA_A_INTERRUPT_ENABLE 9 89cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define EEPROM_DONE_INTERRUPT_ENABLE 8 90cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define VBUS_INTERRUPT_ENABLE 7 91cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define CONTROL_STATUS_INTERRUPT_ENABLE 6 92cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define ROOT_PORT_RESET_INTERRUPT_ENABLE 4 93cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define SUSPEND_REQUEST_INTERRUPT_ENABLE 3 94cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define SUSPEND_REQUEST_CHANGE_INTERRUPT_ENABLE 2 95cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define RESUME_INTERRUPT_ENABLE 1 96cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define SOF_INTERRUPT_ENABLE 0 97eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu __le32 cpu_irqenb0; /* ... or onboard 8051 */ 98cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define SETUP_PACKET_INTERRUPT_ENABLE 7 99cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define ENDPOINT_F_INTERRUPT_ENABLE 6 100cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define ENDPOINT_E_INTERRUPT_ENABLE 5 101cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define ENDPOINT_D_INTERRUPT_ENABLE 4 102cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define ENDPOINT_C_INTERRUPT_ENABLE 3 103cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define ENDPOINT_B_INTERRUPT_ENABLE 2 104cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define ENDPOINT_A_INTERRUPT_ENABLE 1 105cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define ENDPOINT_0_INTERRUPT_ENABLE 0 106eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu __le32 cpu_irqenb1; 107cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define CPU_INTERRUPT_ENABLE 31 108cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define POWER_STATE_CHANGE_INTERRUPT_ENABLE 27 109cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define PCI_ARBITER_TIMEOUT_INTERRUPT_ENABLE 26 110cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define PCI_PARITY_ERROR_INTERRUPT_ENABLE 25 111cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define PCI_INTA_INTERRUPT_ENABLE 24 112cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define PCI_PME_INTERRUPT_ENABLE 23 113cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define PCI_SERR_INTERRUPT_ENABLE 22 114cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define PCI_PERR_INTERRUPT_ENABLE 21 115cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define PCI_MASTER_ABORT_RECEIVED_INTERRUPT_ENABLE 20 116cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define PCI_TARGET_ABORT_RECEIVED_INTERRUPT_ENABLE 19 117cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define PCI_RETRY_ABORT_INTERRUPT_ENABLE 17 118cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define PCI_MASTER_CYCLE_DONE_INTERRUPT_ENABLE 16 119cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define GPIO_INTERRUPT_ENABLE 13 120cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define DMA_D_INTERRUPT_ENABLE 12 121cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define DMA_C_INTERRUPT_ENABLE 11 122cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define DMA_B_INTERRUPT_ENABLE 10 123cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define DMA_A_INTERRUPT_ENABLE 9 124cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define EEPROM_DONE_INTERRUPT_ENABLE 8 125cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define VBUS_INTERRUPT_ENABLE 7 126cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define CONTROL_STATUS_INTERRUPT_ENABLE 6 127cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define ROOT_PORT_RESET_INTERRUPT_ENABLE 4 128cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define SUSPEND_REQUEST_INTERRUPT_ENABLE 3 129cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define SUSPEND_REQUEST_CHANGE_INTERRUPT_ENABLE 2 130cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define RESUME_INTERRUPT_ENABLE 1 131cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define SOF_INTERRUPT_ENABLE 0 132eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu 133cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter /* offset 0x0020 */ 134cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter u32 _unused1; 135cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter __le32 usbirqenb1; 136cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define USB_INTERRUPT_ENABLE 31 137cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define POWER_STATE_CHANGE_INTERRUPT_ENABLE 27 138cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define PCI_ARBITER_TIMEOUT_INTERRUPT_ENABLE 26 139cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define PCI_PARITY_ERROR_INTERRUPT_ENABLE 25 140cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define PCI_INTA_INTERRUPT_ENABLE 24 141cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define PCI_PME_INTERRUPT_ENABLE 23 142cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define PCI_SERR_INTERRUPT_ENABLE 22 143cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define PCI_PERR_INTERRUPT_ENABLE 21 144cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define PCI_MASTER_ABORT_RECEIVED_INTERRUPT_ENABLE 20 145cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define PCI_TARGET_ABORT_RECEIVED_INTERRUPT_ENABLE 19 146cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define PCI_RETRY_ABORT_INTERRUPT_ENABLE 17 147cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define PCI_MASTER_CYCLE_DONE_INTERRUPT_ENABLE 16 148cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define GPIO_INTERRUPT_ENABLE 13 149cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define DMA_D_INTERRUPT_ENABLE 12 150cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define DMA_C_INTERRUPT_ENABLE 11 151cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define DMA_B_INTERRUPT_ENABLE 10 152cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define DMA_A_INTERRUPT_ENABLE 9 153cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define EEPROM_DONE_INTERRUPT_ENABLE 8 154cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define VBUS_INTERRUPT_ENABLE 7 155cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define CONTROL_STATUS_INTERRUPT_ENABLE 6 156cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define ROOT_PORT_RESET_INTERRUPT_ENABLE 4 157cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define SUSPEND_REQUEST_INTERRUPT_ENABLE 3 158cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define SUSPEND_REQUEST_CHANGE_INTERRUPT_ENABLE 2 159cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define RESUME_INTERRUPT_ENABLE 1 160cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define SOF_INTERRUPT_ENABLE 0 161cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter __le32 irqstat0; 162cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define INTA_ASSERTED 12 163cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define SETUP_PACKET_INTERRUPT 7 164cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define ENDPOINT_F_INTERRUPT 6 165cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define ENDPOINT_E_INTERRUPT 5 166cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define ENDPOINT_D_INTERRUPT 4 167cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define ENDPOINT_C_INTERRUPT 3 168cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define ENDPOINT_B_INTERRUPT 2 169cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define ENDPOINT_A_INTERRUPT 1 170cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define ENDPOINT_0_INTERRUPT 0 171cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter __le32 irqstat1; 172cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define POWER_STATE_CHANGE_INTERRUPT 27 173cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define PCI_ARBITER_TIMEOUT_INTERRUPT 26 174cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define PCI_PARITY_ERROR_INTERRUPT 25 175cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define PCI_INTA_INTERRUPT 24 176cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define PCI_PME_INTERRUPT 23 177cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define PCI_SERR_INTERRUPT 22 178cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define PCI_PERR_INTERRUPT 21 179cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define PCI_MASTER_ABORT_RECEIVED_INTERRUPT 20 180cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define PCI_TARGET_ABORT_RECEIVED_INTERRUPT 19 181cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define PCI_RETRY_ABORT_INTERRUPT 17 182cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define PCI_MASTER_CYCLE_DONE_INTERRUPT 16 183cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define GPIO_INTERRUPT 13 184cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define DMA_D_INTERRUPT 12 185cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define DMA_C_INTERRUPT 11 186cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define DMA_B_INTERRUPT 10 187cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define DMA_A_INTERRUPT 9 188cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define EEPROM_DONE_INTERRUPT 8 189cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define VBUS_INTERRUPT 7 190cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define CONTROL_STATUS_INTERRUPT 6 191cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define ROOT_PORT_RESET_INTERRUPT 4 192cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define SUSPEND_REQUEST_INTERRUPT 3 193cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define SUSPEND_REQUEST_CHANGE_INTERRUPT 2 194cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define RESUME_INTERRUPT 1 195cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define SOF_INTERRUPT 0 196cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter /* offset 0x0030 */ 197cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter __le32 idxaddr; 198cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter __le32 idxdata; 199cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter __le32 fifoctl; 200cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define PCI_BASE2_RANGE 16 201cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define IGNORE_FIFO_AVAILABILITY 3 202cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define PCI_BASE2_SELECT 2 203cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define FIFO_CONFIGURATION_SELECT 0 204cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter u32 _unused2; 205cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter /* offset 0x0040 */ 206cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter __le32 memaddr; 207cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define START 28 208cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define DIRECTION 27 209cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define FIFO_DIAGNOSTIC_SELECT 24 210cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define MEMORY_ADDRESS 0 211cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter __le32 memdata0; 212cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter __le32 memdata1; 213cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter u32 _unused3; 214cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter /* offset 0x0050 */ 215cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter __le32 gpioctl; 216cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define GPIO3_LED_SELECT 12 217cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define GPIO3_INTERRUPT_ENABLE 11 218cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define GPIO2_INTERRUPT_ENABLE 10 219cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define GPIO1_INTERRUPT_ENABLE 9 220cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define GPIO0_INTERRUPT_ENABLE 8 221cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define GPIO3_OUTPUT_ENABLE 7 222cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define GPIO2_OUTPUT_ENABLE 6 223cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define GPIO1_OUTPUT_ENABLE 5 224cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define GPIO0_OUTPUT_ENABLE 4 225cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define GPIO3_DATA 3 226cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define GPIO2_DATA 2 227cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define GPIO1_DATA 1 228cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define GPIO0_DATA 0 229cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter __le32 gpiostat; 230cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define GPIO3_INTERRUPT 3 231cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define GPIO2_INTERRUPT 2 232cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define GPIO1_INTERRUPT 1 233cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define GPIO0_INTERRUPT 0 234ba2d3587912f82d1ab4367975b1df460db60fb1eEric Dumazet} __packed; 235eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu 236eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu/* usb control, BAR0 + 0x0080 */ 237eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wustruct net2280_usb_regs { 238cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter /* offset 0x0080 */ 239cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter __le32 stdrsp; 240cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define STALL_UNSUPPORTED_REQUESTS 31 241cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define SET_TEST_MODE 16 242cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define GET_OTHER_SPEED_CONFIGURATION 15 243cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define GET_DEVICE_QUALIFIER 14 244cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define SET_ADDRESS 13 245cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define ENDPOINT_SET_CLEAR_HALT 12 246cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define DEVICE_SET_CLEAR_DEVICE_REMOTE_WAKEUP 11 247cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define GET_STRING_DESCRIPTOR_2 10 248cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define GET_STRING_DESCRIPTOR_1 9 249cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define GET_STRING_DESCRIPTOR_0 8 250cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define GET_SET_INTERFACE 6 251cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define GET_SET_CONFIGURATION 5 252cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define GET_CONFIGURATION_DESCRIPTOR 4 253cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define GET_DEVICE_DESCRIPTOR 3 254cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define GET_ENDPOINT_STATUS 2 255cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define GET_INTERFACE_STATUS 1 256cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define GET_DEVICE_STATUS 0 257cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter __le32 prodvendid; 258cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define PRODUCT_ID 16 259cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define VENDOR_ID 0 260cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter __le32 relnum; 261cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter __le32 usbctl; 262cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define SERIAL_NUMBER_INDEX 16 263cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define PRODUCT_ID_STRING_ENABLE 13 264cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define VENDOR_ID_STRING_ENABLE 12 265cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define USB_ROOT_PORT_WAKEUP_ENABLE 11 266cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define VBUS_PIN 10 267cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define TIMED_DISCONNECT 9 268cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define SUSPEND_IMMEDIATELY 7 269cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define SELF_POWERED_USB_DEVICE 6 270cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define REMOTE_WAKEUP_SUPPORT 5 271cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define PME_POLARITY 4 272cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define USB_DETECT_ENABLE 3 273cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define PME_WAKEUP_ENABLE 2 274cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define DEVICE_REMOTE_WAKEUP_ENABLE 1 275cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define SELF_POWERED_STATUS 0 276cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter /* offset 0x0090 */ 277cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter __le32 usbstat; 278cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define HIGH_SPEED 7 279cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define FULL_SPEED 6 280cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define GENERATE_RESUME 5 281cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define GENERATE_DEVICE_REMOTE_WAKEUP 4 282cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter __le32 xcvrdiag; 283cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define FORCE_HIGH_SPEED_MODE 31 284cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define FORCE_FULL_SPEED_MODE 30 285cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define USB_TEST_MODE 24 286cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define LINE_STATE 16 287cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define TRANSCEIVER_OPERATION_MODE 2 288cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define TRANSCEIVER_SELECT 1 289cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define TERMINATION_SELECT 0 290cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter __le32 setup0123; 291cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter __le32 setup4567; 292cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter /* offset 0x0090 */ 293cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter u32 _unused0; 294cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter __le32 ouraddr; 295cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define FORCE_IMMEDIATE 7 296cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define OUR_USB_ADDRESS 0 297cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter __le32 ourconfig; 298ba2d3587912f82d1ab4367975b1df460db60fb1eEric Dumazet} __packed; 299eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu 300eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu/* pci control, BAR0 + 0x0100 */ 301eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wustruct net2280_pci_regs { 302cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter /* offset 0x0100 */ 303cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter __le32 pcimstctl; 304cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define PCI_ARBITER_PARK_SELECT 13 305cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define PCI_MULTI LEVEL_ARBITER 12 306cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define PCI_RETRY_ABORT_ENABLE 11 307cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define DMA_MEMORY_WRITE_AND_INVALIDATE_ENABLE 10 308cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define DMA_READ_MULTIPLE_ENABLE 9 309cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define DMA_READ_LINE_ENABLE 8 310cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define PCI_MASTER_COMMAND_SELECT 6 311cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define MEM_READ_OR_WRITE 0 312cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define IO_READ_OR_WRITE 1 313cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define CFG_READ_OR_WRITE 2 314cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define PCI_MASTER_START 5 315cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define PCI_MASTER_READ_WRITE 4 316cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define PCI_MASTER_WRITE 0 317cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define PCI_MASTER_READ 1 318cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define PCI_MASTER_BYTE_WRITE_ENABLES 0 319cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter __le32 pcimstaddr; 320cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter __le32 pcimstdata; 321cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter __le32 pcimststat; 322cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define PCI_ARBITER_CLEAR 2 323cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define PCI_EXTERNAL_ARBITER 1 324cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define PCI_HOST_MODE 0 325ba2d3587912f82d1ab4367975b1df460db60fb1eEric Dumazet} __packed; 326eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu 327eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu/* dma control, BAR0 + 0x0180 ... array of four structs like this, 328eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu * for channels 0..3. see also struct net2280_dma: descriptor 329eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu * that can be loaded into some of these registers. 330eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu */ 331eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wustruct net2280_dma_regs { /* [11.7] */ 332cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter /* offset 0x0180, 0x01a0, 0x01c0, 0x01e0, */ 333cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter __le32 dmactl; 334cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define DMA_SCATTER_GATHER_DONE_INTERRUPT_ENABLE 25 335cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define DMA_CLEAR_COUNT_ENABLE 21 336cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define DESCRIPTOR_POLLING_RATE 19 337cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define POLL_CONTINUOUS 0 338cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define POLL_1_USEC 1 339cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define POLL_100_USEC 2 340cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define POLL_1_MSEC 3 341cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define DMA_VALID_BIT_POLLING_ENABLE 18 342cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define DMA_VALID_BIT_ENABLE 17 343cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define DMA_SCATTER_GATHER_ENABLE 16 344cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define DMA_OUT_AUTO_START_ENABLE 4 345cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define DMA_PREEMPT_ENABLE 3 346cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define DMA_FIFO_VALIDATE 2 347cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define DMA_ENABLE 1 348cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define DMA_ADDRESS_HOLD 0 349cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter __le32 dmastat; 350cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define DMA_SCATTER_GATHER_DONE_INTERRUPT 25 351cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define DMA_TRANSACTION_DONE_INTERRUPT 24 352cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define DMA_ABORT 1 353cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define DMA_START 0 354cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter u32 _unused0[2]; 355cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter /* offset 0x0190, 0x01b0, 0x01d0, 0x01f0, */ 356eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu __le32 dmacount; 357cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define VALID_BIT 31 358cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define DMA_DIRECTION 30 359cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define DMA_DONE_INTERRUPT_ENABLE 29 360cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define END_OF_CHAIN 28 361cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define DMA_BYTE_COUNT_MASK ((1<<24)-1) 362cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define DMA_BYTE_COUNT 0 363cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter __le32 dmaaddr; 364cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter __le32 dmadesc; 365cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter u32 _unused1; 366ba2d3587912f82d1ab4367975b1df460db60fb1eEric Dumazet} __packed; 367eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu 368eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu/* dedicated endpoint registers, BAR0 + 0x0200 */ 369eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu 370eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wustruct net2280_dep_regs { /* [11.8] */ 371cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter /* offset 0x0200, 0x0210, 0x220, 0x230, 0x240 */ 372cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter __le32 dep_cfg; 373cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter /* offset 0x0204, 0x0214, 0x224, 0x234, 0x244 */ 374cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter __le32 dep_rsp; 375cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter u32 _unused[2]; 376ba2d3587912f82d1ab4367975b1df460db60fb1eEric Dumazet} __packed; 377eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu 378eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu/* configurable endpoint registers, BAR0 + 0x0300 ... array of seven structs 379eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu * like this, for ep0 then the configurable endpoints A..F 380eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu * ep0 reserved for control; E and F have only 64 bytes of fifo 381eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu */ 382eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wustruct net2280_ep_regs { /* [11.9] */ 383cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter /* offset 0x0300, 0x0320, 0x0340, 0x0360, 0x0380, 0x03a0, 0x03c0 */ 384cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter __le32 ep_cfg; 385cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define ENDPOINT_BYTE_COUNT 16 386cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define ENDPOINT_ENABLE 10 387cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define ENDPOINT_TYPE 8 388cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define ENDPOINT_DIRECTION 7 389cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define ENDPOINT_NUMBER 0 390cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter __le32 ep_rsp; 391cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define SET_NAK_OUT_PACKETS 15 392cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define SET_EP_HIDE_STATUS_PHASE 14 393cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define SET_EP_FORCE_CRC_ERROR 13 394cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define SET_INTERRUPT_MODE 12 395cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define SET_CONTROL_STATUS_PHASE_HANDSHAKE 11 396cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define SET_NAK_OUT_PACKETS_MODE 10 397cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define SET_ENDPOINT_TOGGLE 9 398cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define SET_ENDPOINT_HALT 8 399cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define CLEAR_NAK_OUT_PACKETS 7 400cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define CLEAR_EP_HIDE_STATUS_PHASE 6 401cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define CLEAR_EP_FORCE_CRC_ERROR 5 402cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define CLEAR_INTERRUPT_MODE 4 403cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define CLEAR_CONTROL_STATUS_PHASE_HANDSHAKE 3 404cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define CLEAR_NAK_OUT_PACKETS_MODE 2 405cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define CLEAR_ENDPOINT_TOGGLE 1 406cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define CLEAR_ENDPOINT_HALT 0 407cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter __le32 ep_irqenb; 408cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define SHORT_PACKET_OUT_DONE_INTERRUPT_ENABLE 6 409cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define SHORT_PACKET_TRANSFERRED_INTERRUPT_ENABLE 5 410cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define DATA_PACKET_RECEIVED_INTERRUPT_ENABLE 3 411cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define DATA_PACKET_TRANSMITTED_INTERRUPT_ENABLE 2 412cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define DATA_OUT_PING_TOKEN_INTERRUPT_ENABLE 1 413cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define DATA_IN_TOKEN_INTERRUPT_ENABLE 0 414cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter __le32 ep_stat; 415cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define FIFO_VALID_COUNT 24 416cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define HIGH_BANDWIDTH_OUT_TRANSACTION_PID 22 417cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define TIMEOUT 21 418cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define USB_STALL_SENT 20 419cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define USB_IN_NAK_SENT 19 420cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define USB_IN_ACK_RCVD 18 421cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define USB_OUT_PING_NAK_SENT 17 422cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define USB_OUT_ACK_SENT 16 423cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define FIFO_OVERFLOW 13 424cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define FIFO_UNDERFLOW 12 425cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define FIFO_FULL 11 426cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define FIFO_EMPTY 10 427cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define FIFO_FLUSH 9 428cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define SHORT_PACKET_OUT_DONE_INTERRUPT 6 429cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define SHORT_PACKET_TRANSFERRED_INTERRUPT 5 430cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define NAK_OUT_PACKETS 4 431cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define DATA_PACKET_RECEIVED_INTERRUPT 3 432cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define DATA_PACKET_TRANSMITTED_INTERRUPT 2 433cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define DATA_OUT_PING_TOKEN_INTERRUPT 1 434cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter#define DATA_IN_TOKEN_INTERRUPT 0 435cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter /* offset 0x0310, 0x0330, 0x0350, 0x0370, 0x0390, 0x03b0, 0x03d0 */ 436cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter __le32 ep_avail; 437cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter __le32 ep_data; 438cfcdf40e52bdaa7622a9d1de62e5451d3427a5c6Christian Lamparter u32 _unused0[2]; 439ba2d3587912f82d1ab4367975b1df460db60fb1eEric Dumazet} __packed; 440eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu 441eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wustruct net2280_reg_write { 442eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu __le16 port; 443eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu __le32 addr; 444eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu __le32 val; 445ba2d3587912f82d1ab4367975b1df460db60fb1eEric Dumazet} __packed; 446eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu 447eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wustruct net2280_reg_read { 448eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu __le16 port; 449eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu __le32 addr; 450ba2d3587912f82d1ab4367975b1df460db60fb1eEric Dumazet} __packed; 451eff1a59c48e3c6a006eb4fe5f2e405a996f2259dMichael Wu#endif /* NET2280_H */ 452