rt2x00reg.h revision 61667d8d5bf3c3ee09474069eaf4b93a4755ff8b 
1/*
2	Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
3	<http://rt2x00.serialmonkey.com>
4
5	This program is free software; you can redistribute it and/or modify
6	it under the terms of the GNU General Public License as published by
7	the Free Software Foundation; either version 2 of the License, or
8	(at your option) any later version.
9
10	This program is distributed in the hope that it will be useful,
11	but WITHOUT ANY WARRANTY; without even the implied warranty of
12	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13	GNU General Public License for more details.
14
15	You should have received a copy of the GNU General Public License
16	along with this program; if not, write to the
17	Free Software Foundation, Inc.,
18	59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22	Module: rt2x00
23	Abstract: rt2x00 generic register information.
24 */
25
26#ifndef RT2X00REG_H
27#define RT2X00REG_H
28
29/*
30 * TX result flags.
31 */
32enum TX_STATUS {
33	TX_SUCCESS = 0,
34	TX_SUCCESS_RETRY = 1,
35	TX_FAIL_RETRY = 2,
36	TX_FAIL_INVALID = 3,
37	TX_FAIL_OTHER = 4,
38};
39
40/*
41 * Antenna values
42 */
43enum antenna {
44	ANTENNA_SW_DIVERSITY = 0,
45	ANTENNA_A = 1,
46	ANTENNA_B = 2,
47	ANTENNA_HW_DIVERSITY = 3,
48};
49
50/*
51 * Led mode values.
52 */
53enum led_mode {
54	LED_MODE_DEFAULT = 0,
55	LED_MODE_TXRX_ACTIVITY = 1,
56	LED_MODE_SIGNAL_STRENGTH = 2,
57	LED_MODE_ASUS = 3,
58	LED_MODE_ALPHA = 4,
59};
60
61/*
62 * TSF sync values
63 */
64enum tsf_sync {
65	TSF_SYNC_NONE = 0,
66	TSF_SYNC_INFRA = 1,
67	TSF_SYNC_BEACON = 2,
68};
69
70/*
71 * Device states
72 */
73enum dev_state {
74	STATE_DEEP_SLEEP = 0,
75	STATE_SLEEP = 1,
76	STATE_STANDBY = 2,
77	STATE_AWAKE = 3,
78
79/*
80 * Additional device states, these values are
81 * not strict since they are not directly passed
82 * into the device.
83 */
84	STATE_RADIO_ON,
85	STATE_RADIO_OFF,
86	STATE_RADIO_RX_ON,
87	STATE_RADIO_RX_OFF,
88	STATE_RADIO_RX_ON_LINK,
89	STATE_RADIO_RX_OFF_LINK,
90	STATE_RADIO_IRQ_ON,
91	STATE_RADIO_IRQ_OFF,
92};
93
94/*
95 * IFS backoff values
96 */
97enum ifs {
98	IFS_BACKOFF = 0,
99	IFS_SIFS = 1,
100	IFS_NEW_BACKOFF = 2,
101	IFS_NONE = 3,
102};
103
104/*
105 * Cipher types for hardware encryption
106 */
107enum cipher {
108	CIPHER_NONE = 0,
109	CIPHER_WEP64 = 1,
110	CIPHER_WEP128 = 2,
111	CIPHER_TKIP = 3,
112	CIPHER_AES = 4,
113/*
114 * The following fields were added by rt61pci and rt73usb.
115 */
116	CIPHER_CKIP64 = 5,
117	CIPHER_CKIP128 = 6,
118	CIPHER_TKIP_NO_MIC = 7,
119};
120
121/*
122 * Register handlers.
123 * We store the position of a register field inside a field structure,
124 * This will simplify the process of setting and reading a certain field
125 * inside the register while making sure the process remains byte order safe.
126 */
127struct rt2x00_field8 {
128	u8 bit_offset;
129	u8 bit_mask;
130};
131
132struct rt2x00_field16 {
133	u16 bit_offset;
134	u16 bit_mask;
135};
136
137struct rt2x00_field32 {
138	u32 bit_offset;
139	u32 bit_mask;
140};
141
142/*
143 * Power of two check, this will check
144 * if the mask that has been given contains
145 * and contiguous set of bits.
146 */
147#define is_power_of_two(x)	( !((x) & ((x)-1)) )
148#define low_bit_mask(x)		( ((x)-1) & ~(x) )
149#define is_valid_mask(x)	is_power_of_two(1 + (x) + low_bit_mask(x))
150
151#define FIELD8(__mask)				\
152({						\
153	BUILD_BUG_ON(!(__mask) ||		\
154		     !is_valid_mask(__mask) ||	\
155		     (__mask) != (u8)(__mask));	\
156	(struct rt2x00_field8) {		\
157		__ffs(__mask), (__mask)		\
158	};					\
159})
160
161#define FIELD16(__mask)				\
162({						\
163	BUILD_BUG_ON(!(__mask) ||		\
164		     !is_valid_mask(__mask) ||	\
165		     (__mask) != (u16)(__mask));\
166	(struct rt2x00_field16) {		\
167		__ffs(__mask), (__mask)		\
168	};					\
169})
170
171#define FIELD32(__mask)				\
172({						\
173	BUILD_BUG_ON(!(__mask) ||		\
174		     !is_valid_mask(__mask) ||	\
175		     (__mask) != (u32)(__mask));\
176	(struct rt2x00_field32) {		\
177		__ffs(__mask), (__mask)		\
178	};					\
179})
180
181static inline void rt2x00_set_field32(u32 *reg,
182				      const struct rt2x00_field32 field,
183				      const u32 value)
184{
185	*reg &= ~(field.bit_mask);
186	*reg |= (value << field.bit_offset) & field.bit_mask;
187}
188
189static inline u32 rt2x00_get_field32(const u32 reg,
190				     const struct rt2x00_field32 field)
191{
192	return (reg & field.bit_mask) >> field.bit_offset;
193}
194
195static inline void rt2x00_set_field16(u16 *reg,
196				      const struct rt2x00_field16 field,
197				      const u16 value)
198{
199	*reg &= ~(field.bit_mask);
200	*reg |= (value << field.bit_offset) & field.bit_mask;
201}
202
203static inline u16 rt2x00_get_field16(const u16 reg,
204				     const struct rt2x00_field16 field)
205{
206	return (reg & field.bit_mask) >> field.bit_offset;
207}
208
209static inline void rt2x00_set_field8(u8 *reg,
210				     const struct rt2x00_field8 field,
211				     const u8 value)
212{
213	*reg &= ~(field.bit_mask);
214	*reg |= (value << field.bit_offset) & field.bit_mask;
215}
216
217static inline u8 rt2x00_get_field8(const u8 reg,
218				   const struct rt2x00_field8 field)
219{
220	return (reg & field.bit_mask) >> field.bit_offset;
221}
222
223/*
224 * Device specific rate value.
225 * We will have to create the device specific rate value
226 * passed to the ieee80211 kernel. We need to make it a consist of
227 * multiple fields because we want to store more then 1 device specific
228 * values inside the value.
229 *	1 - rate, stored as 100 kbit/s.
230 *	2 - preamble, short_preamble enabled flag.
231 *	3 - MASK_RATE, which rates are enabled in this mode, this mask
232 *	corresponds with the TX register format for the current device.
233 *	4 - plcp, 802.11b rates are device specific,
234 *	802.11g rates are set according to the ieee802.11a-1999 p.14.
235 * The bit to enable preamble is set in a seperate define.
236 */
237#define DEV_RATE	FIELD32(0x000007ff)
238#define DEV_PREAMBLE	FIELD32(0x00000800)
239#define DEV_RATEMASK	FIELD32(0x00fff000)
240#define DEV_PLCP	FIELD32(0xff000000)
241
242/*
243 * Bitfields
244 */
245#define DEV_RATEBIT_1MB		( 1 << 0 )
246#define DEV_RATEBIT_2MB		( 1 << 1 )
247#define DEV_RATEBIT_5_5MB	( 1 << 2 )
248#define DEV_RATEBIT_11MB	( 1 << 3 )
249#define DEV_RATEBIT_6MB		( 1 << 4 )
250#define DEV_RATEBIT_9MB		( 1 << 5 )
251#define DEV_RATEBIT_12MB	( 1 << 6 )
252#define DEV_RATEBIT_18MB	( 1 << 7 )
253#define DEV_RATEBIT_24MB	( 1 << 8 )
254#define DEV_RATEBIT_36MB	( 1 << 9 )
255#define DEV_RATEBIT_48MB	( 1 << 10 )
256#define DEV_RATEBIT_54MB	( 1 << 11 )
257
258/*
259 * Bitmasks for DEV_RATEMASK
260 */
261#define DEV_RATEMASK_1MB	( (DEV_RATEBIT_1MB << 1) -1 )
262#define DEV_RATEMASK_2MB	( (DEV_RATEBIT_2MB << 1) -1 )
263#define DEV_RATEMASK_5_5MB	( (DEV_RATEBIT_5_5MB << 1) -1 )
264#define DEV_RATEMASK_11MB	( (DEV_RATEBIT_11MB << 1) -1 )
265#define DEV_RATEMASK_6MB	( (DEV_RATEBIT_6MB << 1) -1 )
266#define DEV_RATEMASK_9MB	( (DEV_RATEBIT_9MB << 1) -1 )
267#define DEV_RATEMASK_12MB	( (DEV_RATEBIT_12MB << 1) -1 )
268#define DEV_RATEMASK_18MB	( (DEV_RATEBIT_18MB << 1) -1 )
269#define DEV_RATEMASK_24MB	( (DEV_RATEBIT_24MB << 1) -1 )
270#define DEV_RATEMASK_36MB	( (DEV_RATEBIT_36MB << 1) -1 )
271#define DEV_RATEMASK_48MB	( (DEV_RATEBIT_48MB << 1) -1 )
272#define DEV_RATEMASK_54MB	( (DEV_RATEBIT_54MB << 1) -1 )
273
274/*
275 * Bitmask groups of bitrates
276 */
277#define DEV_BASIC_RATEMASK \
278	( DEV_RATEMASK_11MB | \
279	  DEV_RATEBIT_6MB | DEV_RATEBIT_12MB | DEV_RATEBIT_24MB )
280
281#define DEV_CCK_RATEMASK	( DEV_RATEMASK_11MB )
282#define DEV_OFDM_RATEMASK	( DEV_RATEMASK_54MB & ~DEV_CCK_RATEMASK )
283
284/*
285 * Macro's to set and get specific fields from the device specific val and val2
286 * fields inside the ieee80211_rate entry.
287 */
288#define DEVICE_SET_RATE_FIELD(__value, __mask) \
289	(int)( ((__value) << DEV_##__mask.bit_offset) & DEV_##__mask.bit_mask )
290
291#define DEVICE_GET_RATE_FIELD(__value, __mask) \
292	(int)( ((__value) & DEV_##__mask.bit_mask) >> DEV_##__mask.bit_offset )
293
294#endif /* RT2X00REG_H */
295