dm.c revision c151aed6aa146e9587590051aba9da68b9370f9b
1/****************************************************************************** 2 * 3 * Copyright(c) 2009-2013 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26#include "../wifi.h" 27#include "../base.h" 28#include "../pci.h" 29#include "reg.h" 30#include "def.h" 31#include "phy.h" 32#include "dm.h" 33#include "fw.h" 34#include "trx.h" 35 36static const u32 ofdmswing_table[OFDM_TABLE_SIZE] = { 37 0x7f8001fe, /* 0, +6.0dB */ 38 0x788001e2, /* 1, +5.5dB */ 39 0x71c001c7, /* 2, +5.0dB */ 40 0x6b8001ae, /* 3, +4.5dB */ 41 0x65400195, /* 4, +4.0dB */ 42 0x5fc0017f, /* 5, +3.5dB */ 43 0x5a400169, /* 6, +3.0dB */ 44 0x55400155, /* 7, +2.5dB */ 45 0x50800142, /* 8, +2.0dB */ 46 0x4c000130, /* 9, +1.5dB */ 47 0x47c0011f, /* 10, +1.0dB */ 48 0x43c0010f, /* 11, +0.5dB */ 49 0x40000100, /* 12, +0dB */ 50 0x3c8000f2, /* 13, -0.5dB */ 51 0x390000e4, /* 14, -1.0dB */ 52 0x35c000d7, /* 15, -1.5dB */ 53 0x32c000cb, /* 16, -2.0dB */ 54 0x300000c0, /* 17, -2.5dB */ 55 0x2d4000b5, /* 18, -3.0dB */ 56 0x2ac000ab, /* 19, -3.5dB */ 57 0x288000a2, /* 20, -4.0dB */ 58 0x26000098, /* 21, -4.5dB */ 59 0x24000090, /* 22, -5.0dB */ 60 0x22000088, /* 23, -5.5dB */ 61 0x20000080, /* 24, -6.0dB */ 62 0x1e400079, /* 25, -6.5dB */ 63 0x1c800072, /* 26, -7.0dB */ 64 0x1b00006c, /* 27. -7.5dB */ 65 0x19800066, /* 28, -8.0dB */ 66 0x18000060, /* 29, -8.5dB */ 67 0x16c0005b, /* 30, -9.0dB */ 68 0x15800056, /* 31, -9.5dB */ 69 0x14400051, /* 32, -10.0dB */ 70 0x1300004c, /* 33, -10.5dB */ 71 0x12000048, /* 34, -11.0dB */ 72 0x11000044, /* 35, -11.5dB */ 73 0x10000040, /* 36, -12.0dB */ 74 0x0f00003c, /* 37, -12.5dB */ 75 0x0e400039, /* 38, -13.0dB */ 76 0x0d800036, /* 39, -13.5dB */ 77 0x0cc00033, /* 40, -14.0dB */ 78 0x0c000030, /* 41, -14.5dB */ 79 0x0b40002d, /* 42, -15.0dB */ 80}; 81 82static const u8 cck_tbl_ch1_13[CCK_TABLE_SIZE][8] = { 83 {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /* 0, +0dB */ 84 {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 1, -0.5dB */ 85 {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 2, -1.0dB */ 86 {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 3, -1.5dB */ 87 {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 4, -2.0dB */ 88 {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 5, -2.5dB */ 89 {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 6, -3.0dB */ 90 {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 7, -3.5dB */ 91 {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 8, -4.0dB */ 92 {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 9, -4.5dB */ 93 {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 10, -5.0dB */ 94 {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 11, -5.5dB */ 95 {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 12, -6.0dB */ 96 {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 13, -6.5dB */ 97 {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 14, -7.0dB */ 98 {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 15, -7.5dB */ 99 {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */ 100 {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 17, -8.5dB */ 101 {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 18, -9.0dB */ 102 {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 19, -9.5dB */ 103 {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 20, -10.0dB*/ 104 {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 21, -10.5dB*/ 105 {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 22, -11.0dB*/ 106 {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 23, -11.5dB*/ 107 {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 24, -12.0dB*/ 108 {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 25, -12.5dB*/ 109 {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 26, -13.0dB*/ 110 {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 27, -13.5dB*/ 111 {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 28, -14.0dB*/ 112 {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 29, -14.5dB*/ 113 {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 30, -15.0dB*/ 114 {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 31, -15.5dB*/ 115 {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} /* 32, -16.0dB*/ 116}; 117 118static const u8 cck_tbl_ch14[CCK_TABLE_SIZE][8] = { 119 {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /* 0, +0dB */ 120 {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 1, -0.5dB */ 121 {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 2, -1.0dB */ 122 {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 3, -1.5dB */ 123 {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 4, -2.0dB */ 124 {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 5, -2.5dB */ 125 {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 6, -3.0dB */ 126 {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 7, -3.5dB */ 127 {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 8, -4.0dB */ 128 {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 9, -4.5dB */ 129 {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 10, -5.0dB */ 130 {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 11, -5.5dB */ 131 {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 12, -6.0dB */ 132 {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 13, -6.5dB */ 133 {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 14, -7.0dB */ 134 {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 15, -7.5dB */ 135 {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */ 136 {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 17, -8.5dB */ 137 {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 18, -9.0dB */ 138 {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 19, -9.5dB */ 139 {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 20, -10.0dB*/ 140 {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 21, -10.5dB*/ 141 {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 22, -11.0dB*/ 142 {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 23, -11.5dB*/ 143 {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 24, -12.0dB*/ 144 {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 25, -12.5dB*/ 145 {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 26, -13.0dB*/ 146 {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 27, -13.5dB*/ 147 {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 28, -14.0dB*/ 148 {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 29, -14.5dB*/ 149 {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 30, -15.0dB*/ 150 {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 31, -15.5dB*/ 151 {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} /* 32, -16.0dB*/ 152}; 153 154#define CAL_SWING_OFF(_off, _dir, _size, _del) \ 155 do { \ 156 for (_off = 0; _off < _size; _off++) { \ 157 if (_del < thermal_threshold[_dir][_off]) { \ 158 if (_off != 0) \ 159 _off--; \ 160 break; \ 161 } \ 162 } \ 163 if (_off >= _size) \ 164 _off = _size - 1; \ 165 } while (0) 166 167static void rtl88e_set_iqk_matrix(struct ieee80211_hw *hw, 168 u8 ofdm_index, u8 rfpath, 169 long iqk_result_x, long iqk_result_y) 170{ 171 long ele_a = 0, ele_d, ele_c = 0, value32; 172 173 ele_d = (ofdmswing_table[ofdm_index] & 0xFFC00000)>>22; 174 175 if (iqk_result_x != 0) { 176 if ((iqk_result_x & 0x00000200) != 0) 177 iqk_result_x = iqk_result_x | 0xFFFFFC00; 178 ele_a = ((iqk_result_x * ele_d)>>8)&0x000003FF; 179 180 if ((iqk_result_y & 0x00000200) != 0) 181 iqk_result_y = iqk_result_y | 0xFFFFFC00; 182 ele_c = ((iqk_result_y * ele_d)>>8)&0x000003FF; 183 184 switch (rfpath) { 185 case RF90_PATH_A: 186 value32 = (ele_d << 22)|((ele_c & 0x3F)<<16) | ele_a; 187 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 188 MASKDWORD, value32); 189 value32 = (ele_c & 0x000003C0) >> 6; 190 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS, 191 value32); 192 value32 = ((iqk_result_x * ele_d) >> 7) & 0x01; 193 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(24), 194 value32); 195 break; 196 case RF90_PATH_B: 197 value32 = (ele_d << 22)|((ele_c & 0x3F)<<16) | ele_a; 198 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, MASKDWORD, 199 value32); 200 value32 = (ele_c & 0x000003C0) >> 6; 201 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, MASKH4BITS, value32); 202 value32 = ((iqk_result_x * ele_d) >> 7) & 0x01; 203 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(28), 204 value32); 205 break; 206 default: 207 break; 208 } 209 } else { 210 switch (rfpath) { 211 case RF90_PATH_A: 212 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 213 MASKDWORD, ofdmswing_table[ofdm_index]); 214 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 215 MASKH4BITS, 0x00); 216 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, 217 BIT(24), 0x00); 218 break; 219 case RF90_PATH_B: 220 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 221 MASKDWORD, ofdmswing_table[ofdm_index]); 222 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 223 MASKH4BITS, 0x00); 224 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, 225 BIT(28), 0x00); 226 break; 227 default: 228 break; 229 } 230 } 231} 232 233void rtl88e_dm_txpower_track_adjust(struct ieee80211_hw *hw, 234 u8 type, u8 *pdirection, u32 *poutwrite_val) 235{ 236 struct rtl_priv *rtlpriv = rtl_priv(hw); 237 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw)); 238 u8 pwr_val = 0; 239 u8 cck_base = rtldm->swing_idx_cck_base; 240 u8 cck_val = rtldm->swing_idx_cck; 241 u8 ofdm_base = rtldm->swing_idx_ofdm_base[0]; 242 u8 ofdm_val = rtlpriv->dm.swing_idx_ofdm[RF90_PATH_A]; 243 244 if (type == 0) { 245 if (ofdm_val <= ofdm_base) { 246 *pdirection = 1; 247 pwr_val = ofdm_base - ofdm_val; 248 } else { 249 *pdirection = 2; 250 pwr_val = ofdm_base - ofdm_val; 251 } 252 } else if (type == 1) { 253 if (cck_val <= cck_base) { 254 *pdirection = 1; 255 pwr_val = cck_base - cck_val; 256 } else { 257 *pdirection = 2; 258 pwr_val = cck_val - cck_base; 259 } 260 } 261 262 if (pwr_val >= TXPWRTRACK_MAX_IDX && (*pdirection == 1)) 263 pwr_val = TXPWRTRACK_MAX_IDX; 264 265 *poutwrite_val = pwr_val | (pwr_val << 8) | (pwr_val << 16) | 266 (pwr_val << 24); 267} 268 269static void dm_tx_pwr_track_set_pwr(struct ieee80211_hw *hw, 270 enum pwr_track_control_method method, 271 u8 rfpath, u8 channel_mapped_index) 272{ 273 struct rtl_priv *rtlpriv = rtl_priv(hw); 274 struct rtl_phy *rtlphy = &rtlpriv->phy; 275 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw)); 276 277 if (method == TXAGC) { 278 if (rtldm->swing_flag_ofdm || 279 rtldm->swing_flag_cck) { 280 rtl88e_phy_set_txpower_level(hw, 281 rtlphy->current_channel); 282 rtldm->swing_flag_ofdm = false; 283 rtldm->swing_flag_cck = false; 284 } 285 } else if (method == BBSWING) { 286 if (!rtldm->cck_inch14) { 287 rtl_write_byte(rtlpriv, 0xa22, 288 cck_tbl_ch1_13[rtldm->swing_idx_cck][0]); 289 rtl_write_byte(rtlpriv, 0xa23, 290 cck_tbl_ch1_13[rtldm->swing_idx_cck][1]); 291 rtl_write_byte(rtlpriv, 0xa24, 292 cck_tbl_ch1_13[rtldm->swing_idx_cck][2]); 293 rtl_write_byte(rtlpriv, 0xa25, 294 cck_tbl_ch1_13[rtldm->swing_idx_cck][3]); 295 rtl_write_byte(rtlpriv, 0xa26, 296 cck_tbl_ch1_13[rtldm->swing_idx_cck][4]); 297 rtl_write_byte(rtlpriv, 0xa27, 298 cck_tbl_ch1_13[rtldm->swing_idx_cck][5]); 299 rtl_write_byte(rtlpriv, 0xa28, 300 cck_tbl_ch1_13[rtldm->swing_idx_cck][6]); 301 rtl_write_byte(rtlpriv, 0xa29, 302 cck_tbl_ch1_13[rtldm->swing_idx_cck][7]); 303 } else { 304 rtl_write_byte(rtlpriv, 0xa22, 305 cck_tbl_ch14[rtldm->swing_idx_cck][0]); 306 rtl_write_byte(rtlpriv, 0xa23, 307 cck_tbl_ch14[rtldm->swing_idx_cck][1]); 308 rtl_write_byte(rtlpriv, 0xa24, 309 cck_tbl_ch14[rtldm->swing_idx_cck][2]); 310 rtl_write_byte(rtlpriv, 0xa25, 311 cck_tbl_ch14[rtldm->swing_idx_cck][3]); 312 rtl_write_byte(rtlpriv, 0xa26, 313 cck_tbl_ch14[rtldm->swing_idx_cck][4]); 314 rtl_write_byte(rtlpriv, 0xa27, 315 cck_tbl_ch14[rtldm->swing_idx_cck][5]); 316 rtl_write_byte(rtlpriv, 0xa28, 317 cck_tbl_ch14[rtldm->swing_idx_cck][6]); 318 rtl_write_byte(rtlpriv, 0xa29, 319 cck_tbl_ch14[rtldm->swing_idx_cck][7]); 320 } 321 322 if (rfpath == RF90_PATH_A) { 323 rtl88e_set_iqk_matrix(hw, rtldm->swing_idx_ofdm[rfpath], 324 rfpath, rtlphy->iqk_matrix 325 [channel_mapped_index]. 326 value[0][0], 327 rtlphy->iqk_matrix 328 [channel_mapped_index]. 329 value[0][1]); 330 } else if (rfpath == RF90_PATH_B) { 331 rtl88e_set_iqk_matrix(hw, rtldm->swing_idx_ofdm[rfpath], 332 rfpath, rtlphy->iqk_matrix 333 [channel_mapped_index]. 334 value[0][4], 335 rtlphy->iqk_matrix 336 [channel_mapped_index]. 337 value[0][5]); 338 } 339 } else { 340 return; 341 } 342} 343 344static void rtl88e_dm_diginit(struct ieee80211_hw *hw) 345{ 346 struct rtl_priv *rtlpriv = rtl_priv(hw); 347 struct dig_t *dm_dig = &rtlpriv->dm_digtable; 348 349 dm_dig->dig_enable_flag = true; 350 dm_dig->cur_igvalue = rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f); 351 dm_dig->pre_igvalue = 0; 352 dm_dig->cur_sta_cstate = DIG_STA_DISCONNECT; 353 dm_dig->presta_cstate = DIG_STA_DISCONNECT; 354 dm_dig->curmultista_cstate = DIG_MULTISTA_DISCONNECT; 355 dm_dig->rssi_lowthresh = DM_DIG_THRESH_LOW; 356 dm_dig->rssi_highthresh = DM_DIG_THRESH_HIGH; 357 dm_dig->fa_lowthresh = DM_FALSEALARM_THRESH_LOW; 358 dm_dig->fa_highthresh = DM_FALSEALARM_THRESH_HIGH; 359 dm_dig->rx_gain_max = DM_DIG_MAX; 360 dm_dig->rx_gain_min = DM_DIG_MIN; 361 dm_dig->back_val = DM_DIG_BACKOFF_DEFAULT; 362 dm_dig->back_range_max = DM_DIG_BACKOFF_MAX; 363 dm_dig->back_range_min = DM_DIG_BACKOFF_MIN; 364 dm_dig->pre_cck_cca_thres = 0xff; 365 dm_dig->cur_cck_cca_thres = 0x83; 366 dm_dig->forbidden_igi = DM_DIG_MIN; 367 dm_dig->large_fa_hit = 0; 368 dm_dig->recover_cnt = 0; 369 dm_dig->dig_min_0 = 0x25; 370 dm_dig->dig_min_1 = 0x25; 371 dm_dig->media_connect_0 = false; 372 dm_dig->media_connect_1 = false; 373 rtlpriv->dm.dm_initialgain_enable = true; 374} 375 376static u8 rtl88e_dm_initial_gain_min_pwdb(struct ieee80211_hw *hw) 377{ 378 struct rtl_priv *rtlpriv = rtl_priv(hw); 379 struct dig_t *dm_dig = &rtlpriv->dm_digtable; 380 long rssi_val_min = 0; 381 382 if ((dm_dig->curmultista_cstate == DIG_MULTISTA_CONNECT) && 383 (dm_dig->cur_sta_cstate == DIG_STA_CONNECT)) { 384 if (rtlpriv->dm.entry_min_undec_sm_pwdb != 0) 385 rssi_val_min = 386 (rtlpriv->dm.entry_min_undec_sm_pwdb > 387 rtlpriv->dm.undec_sm_pwdb) ? 388 rtlpriv->dm.undec_sm_pwdb : 389 rtlpriv->dm.entry_min_undec_sm_pwdb; 390 else 391 rssi_val_min = rtlpriv->dm.undec_sm_pwdb; 392 } else if (dm_dig->cur_sta_cstate == DIG_STA_CONNECT || 393 dm_dig->cur_sta_cstate == DIG_STA_BEFORE_CONNECT) { 394 rssi_val_min = rtlpriv->dm.undec_sm_pwdb; 395 } else if (dm_dig->curmultista_cstate == 396 DIG_MULTISTA_CONNECT) { 397 rssi_val_min = rtlpriv->dm.entry_min_undec_sm_pwdb; 398 } 399 400 return (u8)rssi_val_min; 401} 402 403static void rtl88e_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw) 404{ 405 u32 ret_value; 406 struct rtl_priv *rtlpriv = rtl_priv(hw); 407 struct false_alarm_statistics *falsealm_cnt = &rtlpriv->falsealm_cnt; 408 409 rtl_set_bbreg(hw, ROFDM0_LSTF, BIT(31), 1); 410 rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(31), 1); 411 412 ret_value = rtl_get_bbreg(hw, ROFDM0_FRAMESYNC, MASKDWORD); 413 falsealm_cnt->cnt_fast_fsync_fail = (ret_value&0xffff); 414 falsealm_cnt->cnt_sb_search_fail = ((ret_value&0xffff0000)>>16); 415 416 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER1, MASKDWORD); 417 falsealm_cnt->cnt_ofdm_cca = (ret_value&0xffff); 418 falsealm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16); 419 420 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER2, MASKDWORD); 421 falsealm_cnt->cnt_rate_illegal = (ret_value & 0xffff); 422 falsealm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16); 423 424 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER3, MASKDWORD); 425 falsealm_cnt->cnt_mcs_fail = (ret_value & 0xffff); 426 falsealm_cnt->cnt_ofdm_fail = falsealm_cnt->cnt_parity_fail + 427 falsealm_cnt->cnt_rate_illegal + 428 falsealm_cnt->cnt_crc8_fail + 429 falsealm_cnt->cnt_mcs_fail + 430 falsealm_cnt->cnt_fast_fsync_fail + 431 falsealm_cnt->cnt_sb_search_fail; 432 433 ret_value = rtl_get_bbreg(hw, REG_SC_CNT, MASKDWORD); 434 falsealm_cnt->cnt_bw_lsc = (ret_value & 0xffff); 435 falsealm_cnt->cnt_bw_usc = ((ret_value & 0xffff0000) >> 16); 436 437 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(12), 1); 438 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(14), 1); 439 440 ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERLOWER, MASKBYTE0); 441 falsealm_cnt->cnt_cck_fail = ret_value; 442 443 ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERUPPER, MASKBYTE3); 444 falsealm_cnt->cnt_cck_fail += (ret_value & 0xff) << 8; 445 446 ret_value = rtl_get_bbreg(hw, RCCK0_CCA_CNT, MASKDWORD); 447 falsealm_cnt->cnt_cck_cca = ((ret_value & 0xff) << 8) | 448 ((ret_value&0xFF00)>>8); 449 450 falsealm_cnt->cnt_all = (falsealm_cnt->cnt_fast_fsync_fail + 451 falsealm_cnt->cnt_sb_search_fail + 452 falsealm_cnt->cnt_parity_fail + 453 falsealm_cnt->cnt_rate_illegal + 454 falsealm_cnt->cnt_crc8_fail + 455 falsealm_cnt->cnt_mcs_fail + 456 falsealm_cnt->cnt_cck_fail); 457 falsealm_cnt->cnt_cca_all = falsealm_cnt->cnt_ofdm_cca + 458 falsealm_cnt->cnt_cck_cca; 459 460 rtl_set_bbreg(hw, ROFDM0_TRSWISOLATION, BIT(31), 1); 461 rtl_set_bbreg(hw, ROFDM0_TRSWISOLATION, BIT(31), 0); 462 rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(27), 1); 463 rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(27), 0); 464 rtl_set_bbreg(hw, ROFDM0_LSTF, BIT(31), 0); 465 rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(31), 0); 466 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(13)|BIT(12), 0); 467 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(13)|BIT(12), 2); 468 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(15)|BIT(14), 0); 469 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(15)|BIT(14), 2); 470 471 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE, 472 "cnt_parity_fail = %d, cnt_rate_illegal = %d, cnt_crc8_fail = %d, cnt_mcs_fail = %d\n", 473 falsealm_cnt->cnt_parity_fail, 474 falsealm_cnt->cnt_rate_illegal, 475 falsealm_cnt->cnt_crc8_fail, falsealm_cnt->cnt_mcs_fail); 476 477 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE, 478 "cnt_ofdm_fail = %x, cnt_cck_fail = %x, cnt_all = %x\n", 479 falsealm_cnt->cnt_ofdm_fail, 480 falsealm_cnt->cnt_cck_fail, falsealm_cnt->cnt_all); 481} 482 483static void rtl88e_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw) 484{ 485 struct rtl_priv *rtlpriv = rtl_priv(hw); 486 struct dig_t *dm_dig = &rtlpriv->dm_digtable; 487 u8 cur_cck_cca_thresh; 488 489 if (dm_dig->cur_sta_cstate == DIG_STA_CONNECT) { 490 dm_dig->rssi_val_min = rtl88e_dm_initial_gain_min_pwdb(hw); 491 if (dm_dig->rssi_val_min > 25) { 492 cur_cck_cca_thresh = 0xcd; 493 } else if ((dm_dig->rssi_val_min <= 25) && 494 (dm_dig->rssi_val_min > 10)) { 495 cur_cck_cca_thresh = 0x83; 496 } else { 497 if (rtlpriv->falsealm_cnt.cnt_cck_fail > 1000) 498 cur_cck_cca_thresh = 0x83; 499 else 500 cur_cck_cca_thresh = 0x40; 501 } 502 503 } else { 504 if (rtlpriv->falsealm_cnt.cnt_cck_fail > 1000) 505 cur_cck_cca_thresh = 0x83; 506 else 507 cur_cck_cca_thresh = 0x40; 508 } 509 510 if (dm_dig->cur_cck_cca_thres != cur_cck_cca_thresh) 511 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, cur_cck_cca_thresh); 512 513 dm_dig->cur_cck_cca_thres = cur_cck_cca_thresh; 514 dm_dig->pre_cck_cca_thres = dm_dig->cur_cck_cca_thres; 515 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE, 516 "CCK cca thresh hold =%x\n", dm_dig->cur_cck_cca_thres); 517} 518 519static void rtl88e_dm_dig(struct ieee80211_hw *hw) 520{ 521 struct rtl_priv *rtlpriv = rtl_priv(hw); 522 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 523 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 524 struct dig_t *dm_dig = &rtlpriv->dm_digtable; 525 u8 dig_dynamic_min, dig_maxofmin; 526 bool bfirstconnect; 527 u8 dm_dig_max, dm_dig_min; 528 u8 current_igi = dm_dig->cur_igvalue; 529 530 if (rtlpriv->dm.dm_initialgain_enable == false) 531 return; 532 if (dm_dig->dig_enable_flag == false) 533 return; 534 if (mac->act_scanning == true) 535 return; 536 537 if (mac->link_state >= MAC80211_LINKED) 538 dm_dig->cur_sta_cstate = DIG_STA_CONNECT; 539 else 540 dm_dig->cur_sta_cstate = DIG_STA_DISCONNECT; 541 if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP || 542 rtlpriv->mac80211.opmode == NL80211_IFTYPE_ADHOC) 543 dm_dig->cur_sta_cstate = DIG_STA_DISCONNECT; 544 545 dm_dig_max = DM_DIG_MAX; 546 dm_dig_min = DM_DIG_MIN; 547 dig_maxofmin = DM_DIG_MAX_AP; 548 dig_dynamic_min = dm_dig->dig_min_0; 549 bfirstconnect = ((mac->link_state >= MAC80211_LINKED) ? true : false) && 550 !dm_dig->media_connect_0; 551 552 dm_dig->rssi_val_min = 553 rtl88e_dm_initial_gain_min_pwdb(hw); 554 555 if (mac->link_state >= MAC80211_LINKED) { 556 if ((dm_dig->rssi_val_min + 20) > dm_dig_max) 557 dm_dig->rx_gain_max = dm_dig_max; 558 else if ((dm_dig->rssi_val_min + 20) < dm_dig_min) 559 dm_dig->rx_gain_max = dm_dig_min; 560 else 561 dm_dig->rx_gain_max = dm_dig->rssi_val_min + 20; 562 563 if (rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV) { 564 dig_dynamic_min = dm_dig->antdiv_rssi_max; 565 } else { 566 if (dm_dig->rssi_val_min < dm_dig_min) 567 dig_dynamic_min = dm_dig_min; 568 else if (dm_dig->rssi_val_min < dig_maxofmin) 569 dig_dynamic_min = dig_maxofmin; 570 else 571 dig_dynamic_min = dm_dig->rssi_val_min; 572 } 573 } else { 574 dm_dig->rx_gain_max = dm_dig_max; 575 dig_dynamic_min = dm_dig_min; 576 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, "no link\n"); 577 } 578 579 if (rtlpriv->falsealm_cnt.cnt_all > 10000) { 580 dm_dig->large_fa_hit++; 581 if (dm_dig->forbidden_igi < current_igi) { 582 dm_dig->forbidden_igi = current_igi; 583 dm_dig->large_fa_hit = 1; 584 } 585 586 if (dm_dig->large_fa_hit >= 3) { 587 if ((dm_dig->forbidden_igi + 1) > 588 dm_dig->rx_gain_max) 589 dm_dig->rx_gain_min = 590 dm_dig->rx_gain_max; 591 else 592 dm_dig->rx_gain_min = 593 dm_dig->forbidden_igi + 1; 594 dm_dig->recover_cnt = 3600; 595 } 596 } else { 597 if (dm_dig->recover_cnt != 0) { 598 dm_dig->recover_cnt--; 599 } else { 600 if (dm_dig->large_fa_hit == 0) { 601 if ((dm_dig->forbidden_igi - 1) < 602 dig_dynamic_min) { 603 dm_dig->forbidden_igi = dig_dynamic_min; 604 dm_dig->rx_gain_min = dig_dynamic_min; 605 } else { 606 dm_dig->forbidden_igi--; 607 dm_dig->rx_gain_min = 608 dm_dig->forbidden_igi + 1; 609 } 610 } else if (dm_dig->large_fa_hit == 3) { 611 dm_dig->large_fa_hit = 0; 612 } 613 } 614 } 615 616 if (dm_dig->cur_sta_cstate == DIG_STA_CONNECT) { 617 if (bfirstconnect) { 618 current_igi = dm_dig->rssi_val_min; 619 } else { 620 if (rtlpriv->falsealm_cnt.cnt_all > DM_DIG_FA_TH2) 621 current_igi += 2; 622 else if (rtlpriv->falsealm_cnt.cnt_all > DM_DIG_FA_TH1) 623 current_igi++; 624 else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH0) 625 current_igi--; 626 } 627 } else { 628 if (rtlpriv->falsealm_cnt.cnt_all > 10000) 629 current_igi += 2; 630 else if (rtlpriv->falsealm_cnt.cnt_all > 8000) 631 current_igi++; 632 else if (rtlpriv->falsealm_cnt.cnt_all < 500) 633 current_igi--; 634 } 635 636 if (current_igi > DM_DIG_FA_UPPER) 637 current_igi = DM_DIG_FA_UPPER; 638 else if (current_igi < DM_DIG_FA_LOWER) 639 current_igi = DM_DIG_FA_LOWER; 640 641 if (rtlpriv->falsealm_cnt.cnt_all > 10000) 642 current_igi = DM_DIG_FA_UPPER; 643 644 dm_dig->cur_igvalue = current_igi; 645 rtl88e_dm_write_dig(hw); 646 dm_dig->media_connect_0 = 647 ((mac->link_state >= MAC80211_LINKED) ? true : false); 648 dm_dig->dig_min_0 = dig_dynamic_min; 649 650 rtl88e_dm_cck_packet_detection_thresh(hw); 651} 652 653static void rtl88e_dm_init_dynamic_txpower(struct ieee80211_hw *hw) 654{ 655 struct rtl_priv *rtlpriv = rtl_priv(hw); 656 657 rtlpriv->dm.dynamic_txpower_enable = false; 658 659 rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL; 660 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL; 661} 662 663static void rtl92c_dm_dynamic_txpower(struct ieee80211_hw *hw) 664{ 665 struct rtl_priv *rtlpriv = rtl_priv(hw); 666 struct rtl_phy *rtlphy = &rtlpriv->phy; 667 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 668 long undec_sm_pwdb; 669 670 if (!rtlpriv->dm.dynamic_txpower_enable) 671 return; 672 673 if (rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) { 674 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL; 675 return; 676 } 677 678 if ((mac->link_state < MAC80211_LINKED) && 679 (rtlpriv->dm.entry_min_undec_sm_pwdb == 0)) { 680 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE, 681 "Not connected to any\n"); 682 683 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL; 684 685 rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL; 686 return; 687 } 688 689 if (mac->link_state >= MAC80211_LINKED) { 690 if (mac->opmode == NL80211_IFTYPE_ADHOC) { 691 undec_sm_pwdb = 692 rtlpriv->dm.entry_min_undec_sm_pwdb; 693 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 694 "AP Client PWDB = 0x%lx\n", 695 undec_sm_pwdb); 696 } else { 697 undec_sm_pwdb = 698 rtlpriv->dm.undec_sm_pwdb; 699 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 700 "STA Default Port PWDB = 0x%lx\n", 701 undec_sm_pwdb); 702 } 703 } else { 704 undec_sm_pwdb = 705 rtlpriv->dm.entry_min_undec_sm_pwdb; 706 707 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 708 "AP Ext Port PWDB = 0x%lx\n", 709 undec_sm_pwdb); 710 } 711 712 if (undec_sm_pwdb >= TX_POWER_NEAR_FIELD_THRESH_LVL2) { 713 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1; 714 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 715 "TXHIGHPWRLEVEL_LEVEL1 (TxPwr = 0x0)\n"); 716 } else if ((undec_sm_pwdb < 717 (TX_POWER_NEAR_FIELD_THRESH_LVL2 - 3)) && 718 (undec_sm_pwdb >= 719 TX_POWER_NEAR_FIELD_THRESH_LVL1)) { 720 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1; 721 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 722 "TXHIGHPWRLEVEL_LEVEL1 (TxPwr = 0x10)\n"); 723 } else if (undec_sm_pwdb < 724 (TX_POWER_NEAR_FIELD_THRESH_LVL1 - 5)) { 725 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL; 726 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 727 "TXHIGHPWRLEVEL_NORMAL\n"); 728 } 729 730 if ((rtlpriv->dm.dynamic_txhighpower_lvl != 731 rtlpriv->dm.last_dtp_lvl)) { 732 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 733 "PHY_SetTxPowerLevel8192S() Channel = %d\n", 734 rtlphy->current_channel); 735 rtl88e_phy_set_txpower_level(hw, rtlphy->current_channel); 736 } 737 738 rtlpriv->dm.last_dtp_lvl = rtlpriv->dm.dynamic_txhighpower_lvl; 739} 740 741void rtl88e_dm_write_dig(struct ieee80211_hw *hw) 742{ 743 struct rtl_priv *rtlpriv = rtl_priv(hw); 744 struct dig_t *dm_dig = &rtlpriv->dm_digtable; 745 746 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, 747 "cur_igvalue = 0x%x, pre_igvalue = 0x%x, backoff_val = %d\n", 748 dm_dig->cur_igvalue, dm_dig->pre_igvalue, 749 dm_dig->back_val); 750 751 if (dm_dig->cur_igvalue > 0x3f) 752 dm_dig->cur_igvalue = 0x3f; 753 if (dm_dig->pre_igvalue != dm_dig->cur_igvalue) { 754 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f, 755 dm_dig->cur_igvalue); 756 757 dm_dig->pre_igvalue = dm_dig->cur_igvalue; 758 } 759} 760 761static void rtl88e_dm_pwdb_monitor(struct ieee80211_hw *hw) 762{ 763 struct rtl_priv *rtlpriv = rtl_priv(hw); 764 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 765 struct rtl_sta_info *drv_priv; 766 static u64 last_record_txok_cnt; 767 static u64 last_record_rxok_cnt; 768 long tmp_entry_max_pwdb = 0, tmp_entry_min_pwdb = 0xff; 769 770 if (rtlhal->oem_id == RT_CID_819X_HP) { 771 u64 cur_txok_cnt = 0; 772 u64 cur_rxok_cnt = 0; 773 cur_txok_cnt = rtlpriv->stats.txbytesunicast - 774 last_record_txok_cnt; 775 cur_rxok_cnt = rtlpriv->stats.rxbytesunicast - 776 last_record_rxok_cnt; 777 last_record_txok_cnt = cur_txok_cnt; 778 last_record_rxok_cnt = cur_rxok_cnt; 779 780 if (cur_rxok_cnt > (cur_txok_cnt * 6)) 781 rtl_write_dword(rtlpriv, REG_ARFR0, 0x8f015); 782 else 783 rtl_write_dword(rtlpriv, REG_ARFR0, 0xff015); 784 } 785 786 /* AP & ADHOC & MESH */ 787 spin_lock_bh(&rtlpriv->locks.entry_list_lock); 788 list_for_each_entry(drv_priv, &rtlpriv->entry_list, list) { 789 if (drv_priv->rssi_stat.undec_sm_pwdb < 790 tmp_entry_min_pwdb) 791 tmp_entry_min_pwdb = drv_priv->rssi_stat.undec_sm_pwdb; 792 if (drv_priv->rssi_stat.undec_sm_pwdb > 793 tmp_entry_max_pwdb) 794 tmp_entry_max_pwdb = drv_priv->rssi_stat.undec_sm_pwdb; 795 } 796 spin_unlock_bh(&rtlpriv->locks.entry_list_lock); 797 798 /* If associated entry is found */ 799 if (tmp_entry_max_pwdb != 0) { 800 rtlpriv->dm.entry_max_undec_sm_pwdb = tmp_entry_max_pwdb; 801 RTPRINT(rtlpriv, FDM, DM_PWDB, "EntryMaxPWDB = 0x%lx(%ld)\n", 802 tmp_entry_max_pwdb, tmp_entry_max_pwdb); 803 } else { 804 rtlpriv->dm.entry_max_undec_sm_pwdb = 0; 805 } 806 /* If associated entry is found */ 807 if (tmp_entry_min_pwdb != 0xff) { 808 rtlpriv->dm.entry_min_undec_sm_pwdb = tmp_entry_min_pwdb; 809 RTPRINT(rtlpriv, FDM, DM_PWDB, "EntryMinPWDB = 0x%lx(%ld)\n", 810 tmp_entry_min_pwdb, tmp_entry_min_pwdb); 811 } else { 812 rtlpriv->dm.entry_min_undec_sm_pwdb = 0; 813 } 814 /* Indicate Rx signal strength to FW. */ 815 if (rtlpriv->dm.useramask) { 816 u8 h2c_parameter[3] = { 0 }; 817 818 h2c_parameter[2] = (u8)(rtlpriv->dm.undec_sm_pwdb & 0xFF); 819 h2c_parameter[0] = 0x20; 820 } else { 821 rtl_write_byte(rtlpriv, 0x4fe, rtlpriv->dm.undec_sm_pwdb); 822 } 823} 824 825void rtl88e_dm_init_edca_turbo(struct ieee80211_hw *hw) 826{ 827 struct rtl_priv *rtlpriv = rtl_priv(hw); 828 829 rtlpriv->dm.current_turbo_edca = false; 830 rtlpriv->dm.is_any_nonbepkts = false; 831 rtlpriv->dm.is_cur_rdlstate = false; 832} 833 834static void rtl88e_dm_check_edca_turbo(struct ieee80211_hw *hw) 835{ 836 struct rtl_priv *rtlpriv = rtl_priv(hw); 837 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 838 static u64 last_txok_cnt; 839 static u64 last_rxok_cnt; 840 static u32 last_bt_edca_ul; 841 static u32 last_bt_edca_dl; 842 u64 cur_txok_cnt = 0; 843 u64 cur_rxok_cnt = 0; 844 u32 edca_be_ul = 0x5ea42b; 845 u32 edca_be_dl = 0x5ea42b; 846 bool bt_change_edca = false; 847 848 if ((last_bt_edca_ul != rtlpriv->btcoexist.bt_edca_ul) || 849 (last_bt_edca_dl != rtlpriv->btcoexist.bt_edca_dl)) { 850 rtlpriv->dm.current_turbo_edca = false; 851 last_bt_edca_ul = rtlpriv->btcoexist.bt_edca_ul; 852 last_bt_edca_dl = rtlpriv->btcoexist.bt_edca_dl; 853 } 854 855 if (rtlpriv->btcoexist.bt_edca_ul != 0) { 856 edca_be_ul = rtlpriv->btcoexist.bt_edca_ul; 857 bt_change_edca = true; 858 } 859 860 if (rtlpriv->btcoexist.bt_edca_dl != 0) { 861 edca_be_ul = rtlpriv->btcoexist.bt_edca_dl; 862 bt_change_edca = true; 863 } 864 865 if (mac->link_state != MAC80211_LINKED) { 866 rtlpriv->dm.current_turbo_edca = false; 867 return; 868 } 869 if ((bt_change_edca) || 870 ((!rtlpriv->dm.is_any_nonbepkts) && 871 (!rtlpriv->dm.disable_framebursting))) { 872 873 cur_txok_cnt = rtlpriv->stats.txbytesunicast - last_txok_cnt; 874 cur_rxok_cnt = rtlpriv->stats.rxbytesunicast - last_rxok_cnt; 875 876 if (cur_rxok_cnt > 4 * cur_txok_cnt) { 877 if (!rtlpriv->dm.is_cur_rdlstate || 878 !rtlpriv->dm.current_turbo_edca) { 879 rtl_write_dword(rtlpriv, 880 REG_EDCA_BE_PARAM, 881 edca_be_dl); 882 rtlpriv->dm.is_cur_rdlstate = true; 883 } 884 } else { 885 if (rtlpriv->dm.is_cur_rdlstate || 886 !rtlpriv->dm.current_turbo_edca) { 887 rtl_write_dword(rtlpriv, 888 REG_EDCA_BE_PARAM, 889 edca_be_ul); 890 rtlpriv->dm.is_cur_rdlstate = false; 891 } 892 } 893 rtlpriv->dm.current_turbo_edca = true; 894 } else { 895 if (rtlpriv->dm.current_turbo_edca) { 896 u8 tmp = AC0_BE; 897 898 rtlpriv->cfg->ops->set_hw_reg(hw, 899 HW_VAR_AC_PARAM, 900 &tmp); 901 rtlpriv->dm.current_turbo_edca = false; 902 } 903 } 904 905 rtlpriv->dm.is_any_nonbepkts = false; 906 last_txok_cnt = rtlpriv->stats.txbytesunicast; 907 last_rxok_cnt = rtlpriv->stats.rxbytesunicast; 908} 909 910static void dm_txpower_track_cb_therm(struct ieee80211_hw *hw) 911{ 912 struct rtl_priv *rtlpriv = rtl_priv(hw); 913 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 914 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw)); 915 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 916 u8 thermalvalue = 0, delta, delta_lck, delta_iqk, offset; 917 u8 thermalvalue_avg_count = 0; 918 u32 thermalvalue_avg = 0; 919 long ele_d, temp_cck; 920 char ofdm_index[2], cck_index = 0, 921 ofdm_index_old[2] = {0, 0}, cck_index_old = 0; 922 int i = 0; 923 /*bool is2t = false;*/ 924 925 u8 ofdm_min_index = 6, rf = 1; 926 /*u8 index_for_channel;*/ 927 enum _power_dec_inc {power_dec, power_inc}; 928 929 /*0.1 the following TWO tables decide the 930 *final index of OFDM/CCK swing table 931 */ 932 char delta_swing_table_idx[2][15] = { 933 {0, 0, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 10, 11}, 934 {0, 0, -1, -2, -3, -4, -4, -4, -4, -5, -7, -8, -9, -9, -10} 935 }; 936 u8 thermal_threshold[2][15] = { 937 {0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 27}, 938 {0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 25, 25, 25} 939 }; 940 941 /*Initilization (7 steps in total) */ 942 rtlpriv->dm.txpower_trackinginit = true; 943 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 944 "dm_txpower_track_cb_therm\n"); 945 946 thermalvalue = (u8)rtl_get_rfreg(hw, RF90_PATH_A, RF_T_METER, 947 0xfc00); 948 if (!thermalvalue) 949 return; 950 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 951 "Readback Thermal Meter = 0x%x pre thermal meter 0x%x eeprom_thermalmeter 0x%x\n", 952 thermalvalue, rtlpriv->dm.thermalvalue, 953 rtlefuse->eeprom_thermalmeter); 954 955 /*1. Query OFDM Default Setting: Path A*/ 956 ele_d = rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD) & 957 MASKOFDM_D; 958 for (i = 0; i < OFDM_TABLE_LENGTH; i++) { 959 if (ele_d == (ofdmswing_table[i] & MASKOFDM_D)) { 960 ofdm_index_old[0] = (u8)i; 961 rtldm->swing_idx_ofdm_base[RF90_PATH_A] = (u8)i; 962 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 963 "Initial pathA ele_d reg0x%x = 0x%lx, ofdm_index = 0x%x\n", 964 ROFDM0_XATXIQIMBALANCE, 965 ele_d, ofdm_index_old[0]); 966 break; 967 } 968 } 969 970 /*2.Query CCK default setting From 0xa24*/ 971 temp_cck = rtl_get_bbreg(hw, RCCK0_TXFILTER2, MASKDWORD) & MASKCCK; 972 for (i = 0; i < CCK_TABLE_LENGTH; i++) { 973 if (rtlpriv->dm.cck_inch14) { 974 if (memcmp(&temp_cck, &cck_tbl_ch14[i][2], 4) == 0) { 975 cck_index_old = (u8)i; 976 rtldm->swing_idx_cck_base = (u8)i; 977 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, 978 DBG_LOUD, 979 "Initial reg0x%x = 0x%lx, cck_index = 0x%x, ch 14 %d\n", 980 RCCK0_TXFILTER2, temp_cck, 981 cck_index_old, 982 rtlpriv->dm.cck_inch14); 983 break; 984 } 985 } else { 986 if (memcmp(&temp_cck, &cck_tbl_ch1_13[i][2], 4) == 0) { 987 cck_index_old = (u8)i; 988 rtldm->swing_idx_cck_base = (u8)i; 989 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, 990 DBG_LOUD, 991 "Initial reg0x%x = 0x%lx, cck_index = 0x%x, ch14 %d\n", 992 RCCK0_TXFILTER2, temp_cck, 993 cck_index_old, 994 rtlpriv->dm.cck_inch14); 995 break; 996 } 997 } 998 } 999 1000 /*3 Initialize ThermalValues of RFCalibrateInfo*/ 1001 if (!rtldm->thermalvalue) { 1002 rtlpriv->dm.thermalvalue = rtlefuse->eeprom_thermalmeter; 1003 rtlpriv->dm.thermalvalue_lck = thermalvalue; 1004 rtlpriv->dm.thermalvalue_iqk = thermalvalue; 1005 for (i = 0; i < rf; i++) 1006 rtlpriv->dm.ofdm_index[i] = ofdm_index_old[i]; 1007 rtlpriv->dm.cck_index = cck_index_old; 1008 } 1009 1010 /*4 Calculate average thermal meter*/ 1011 rtldm->thermalvalue_avg[rtldm->thermalvalue_avg_index] = thermalvalue; 1012 rtldm->thermalvalue_avg_index++; 1013 if (rtldm->thermalvalue_avg_index == AVG_THERMAL_NUM_88E) 1014 rtldm->thermalvalue_avg_index = 0; 1015 1016 for (i = 0; i < AVG_THERMAL_NUM_88E; i++) { 1017 if (rtldm->thermalvalue_avg[i]) { 1018 thermalvalue_avg += rtldm->thermalvalue_avg[i]; 1019 thermalvalue_avg_count++; 1020 } 1021 } 1022 1023 if (thermalvalue_avg_count) 1024 thermalvalue = (u8)(thermalvalue_avg / thermalvalue_avg_count); 1025 1026 /* 5 Calculate delta, delta_LCK, delta_IQK.*/ 1027 if (rtlhal->reloadtxpowerindex) { 1028 delta = (thermalvalue > rtlefuse->eeprom_thermalmeter) ? 1029 (thermalvalue - rtlefuse->eeprom_thermalmeter) : 1030 (rtlefuse->eeprom_thermalmeter - thermalvalue); 1031 rtlhal->reloadtxpowerindex = false; 1032 rtlpriv->dm.done_txpower = false; 1033 } else if (rtlpriv->dm.done_txpower) { 1034 delta = (thermalvalue > rtlpriv->dm.thermalvalue) ? 1035 (thermalvalue - rtlpriv->dm.thermalvalue) : 1036 (rtlpriv->dm.thermalvalue - thermalvalue); 1037 } else { 1038 delta = (thermalvalue > rtlefuse->eeprom_thermalmeter) ? 1039 (thermalvalue - rtlefuse->eeprom_thermalmeter) : 1040 (rtlefuse->eeprom_thermalmeter - thermalvalue); 1041 } 1042 delta_lck = (thermalvalue > rtlpriv->dm.thermalvalue_lck) ? 1043 (thermalvalue - rtlpriv->dm.thermalvalue_lck) : 1044 (rtlpriv->dm.thermalvalue_lck - thermalvalue); 1045 delta_iqk = (thermalvalue > rtlpriv->dm.thermalvalue_iqk) ? 1046 (thermalvalue - rtlpriv->dm.thermalvalue_iqk) : 1047 (rtlpriv->dm.thermalvalue_iqk - thermalvalue); 1048 1049 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 1050 "Readback Thermal Meter = 0x%x pre thermal meter 0x%x eeprom_thermalmeter 0x%x delta 0x%x delta_lck 0x%x delta_iqk 0x%x\n", 1051 thermalvalue, rtlpriv->dm.thermalvalue, 1052 rtlefuse->eeprom_thermalmeter, delta, delta_lck, 1053 delta_iqk); 1054 /* 6 If necessary, do LCK.*/ 1055 if (delta_lck >= 8) { 1056 rtlpriv->dm.thermalvalue_lck = thermalvalue; 1057 rtl88e_phy_lc_calibrate(hw); 1058 } 1059 1060 /* 7 If necessary, move the index of 1061 * swing table to adjust Tx power. 1062 */ 1063 if (delta > 0 && rtlpriv->dm.txpower_track_control) { 1064 delta = (thermalvalue > rtlefuse->eeprom_thermalmeter) ? 1065 (thermalvalue - rtlefuse->eeprom_thermalmeter) : 1066 (rtlefuse->eeprom_thermalmeter - thermalvalue); 1067 1068 /* 7.1 Get the final CCK_index and OFDM_index for each 1069 * swing table. 1070 */ 1071 if (thermalvalue > rtlefuse->eeprom_thermalmeter) { 1072 CAL_SWING_OFF(offset, power_inc, INDEX_MAPPING_NUM, 1073 delta); 1074 for (i = 0; i < rf; i++) 1075 ofdm_index[i] = 1076 rtldm->ofdm_index[i] + 1077 delta_swing_table_idx[power_inc][offset]; 1078 cck_index = rtldm->cck_index + 1079 delta_swing_table_idx[power_inc][offset]; 1080 } else { 1081 CAL_SWING_OFF(offset, power_dec, INDEX_MAPPING_NUM, 1082 delta); 1083 for (i = 0; i < rf; i++) 1084 ofdm_index[i] = 1085 rtldm->ofdm_index[i] + 1086 delta_swing_table_idx[power_dec][offset]; 1087 cck_index = rtldm->cck_index + 1088 delta_swing_table_idx[power_dec][offset]; 1089 } 1090 1091 /* 7.2 Handle boundary conditions of index.*/ 1092 for (i = 0; i < rf; i++) { 1093 if (ofdm_index[i] > OFDM_TABLE_SIZE-1) 1094 ofdm_index[i] = OFDM_TABLE_SIZE-1; 1095 else if (rtldm->ofdm_index[i] < ofdm_min_index) 1096 ofdm_index[i] = ofdm_min_index; 1097 } 1098 1099 if (cck_index > CCK_TABLE_SIZE-1) 1100 cck_index = CCK_TABLE_SIZE-1; 1101 else if (cck_index < 0) 1102 cck_index = 0; 1103 1104 /*7.3Configure the Swing Table to adjust Tx Power.*/ 1105 if (rtlpriv->dm.txpower_track_control) { 1106 rtldm->done_txpower = true; 1107 rtldm->swing_idx_ofdm[RF90_PATH_A] = 1108 (u8)ofdm_index[RF90_PATH_A]; 1109 rtldm->swing_idx_cck = cck_index; 1110 if (rtldm->swing_idx_ofdm_cur != 1111 rtldm->swing_idx_ofdm[0]) { 1112 rtldm->swing_idx_ofdm_cur = 1113 rtldm->swing_idx_ofdm[0]; 1114 rtldm->swing_flag_ofdm = true; 1115 } 1116 1117 if (rtldm->swing_idx_cck_cur != rtldm->swing_idx_cck) { 1118 rtldm->swing_idx_cck_cur = rtldm->swing_idx_cck; 1119 rtldm->swing_flag_cck = true; 1120 } 1121 1122 dm_tx_pwr_track_set_pwr(hw, TXAGC, 0, 0); 1123 } 1124 } 1125 1126 if (delta_iqk >= 8) { 1127 rtlpriv->dm.thermalvalue_iqk = thermalvalue; 1128 rtl88e_phy_iq_calibrate(hw, false); 1129 } 1130 1131 if (rtldm->txpower_track_control) 1132 rtldm->thermalvalue = thermalvalue; 1133 rtldm->txpowercount = 0; 1134 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, "end\n"); 1135} 1136 1137static void rtl88e_dm_init_txpower_tracking(struct ieee80211_hw *hw) 1138{ 1139 struct rtl_priv *rtlpriv = rtl_priv(hw); 1140 1141 rtlpriv->dm.txpower_tracking = true; 1142 rtlpriv->dm.txpower_trackinginit = false; 1143 rtlpriv->dm.txpowercount = 0; 1144 rtlpriv->dm.txpower_track_control = true; 1145 1146 rtlpriv->dm.swing_idx_ofdm[RF90_PATH_A] = 12; 1147 rtlpriv->dm.swing_idx_ofdm_cur = 12; 1148 rtlpriv->dm.swing_flag_ofdm = false; 1149 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 1150 "rtlpriv->dm.txpower_tracking = %d\n", 1151 rtlpriv->dm.txpower_tracking); 1152} 1153 1154void rtl88e_dm_check_txpower_tracking(struct ieee80211_hw *hw) 1155{ 1156 struct rtl_priv *rtlpriv = rtl_priv(hw); 1157 static u8 tm_trigger; 1158 1159 if (!rtlpriv->dm.txpower_tracking) 1160 return; 1161 1162 if (!tm_trigger) { 1163 rtl_set_rfreg(hw, RF90_PATH_A, RF_T_METER, BIT(17)|BIT(16), 1164 0x03); 1165 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 1166 "Trigger 88E Thermal Meter!!\n"); 1167 tm_trigger = 1; 1168 return; 1169 } else { 1170 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 1171 "Schedule TxPowerTracking !!\n"); 1172 dm_txpower_track_cb_therm(hw); 1173 tm_trigger = 0; 1174 } 1175} 1176 1177void rtl88e_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw) 1178{ 1179 struct rtl_priv *rtlpriv = rtl_priv(hw); 1180 struct rate_adaptive *p_ra = &rtlpriv->ra; 1181 1182 p_ra->ratr_state = DM_RATR_STA_INIT; 1183 p_ra->pre_ratr_state = DM_RATR_STA_INIT; 1184 1185 if (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER) 1186 rtlpriv->dm.useramask = true; 1187 else 1188 rtlpriv->dm.useramask = false; 1189} 1190 1191static void rtl88e_dm_refresh_rate_adaptive_mask(struct ieee80211_hw *hw) 1192{ 1193 struct rtl_priv *rtlpriv = rtl_priv(hw); 1194 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1195 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1196 struct rate_adaptive *p_ra = &rtlpriv->ra; 1197 u32 low_rssithresh_for_ra, high_rssithresh_for_ra; 1198 struct ieee80211_sta *sta = NULL; 1199 1200 if (is_hal_stop(rtlhal)) { 1201 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD, 1202 "driver is going to unload\n"); 1203 return; 1204 } 1205 1206 if (!rtlpriv->dm.useramask) { 1207 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD, 1208 "driver does not control rate adaptive mask\n"); 1209 return; 1210 } 1211 1212 if (mac->link_state == MAC80211_LINKED && 1213 mac->opmode == NL80211_IFTYPE_STATION) { 1214 switch (p_ra->pre_ratr_state) { 1215 case DM_RATR_STA_HIGH: 1216 high_rssithresh_for_ra = 50; 1217 low_rssithresh_for_ra = 20; 1218 break; 1219 case DM_RATR_STA_MIDDLE: 1220 high_rssithresh_for_ra = 55; 1221 low_rssithresh_for_ra = 20; 1222 break; 1223 case DM_RATR_STA_LOW: 1224 high_rssithresh_for_ra = 50; 1225 low_rssithresh_for_ra = 25; 1226 break; 1227 default: 1228 high_rssithresh_for_ra = 50; 1229 low_rssithresh_for_ra = 20; 1230 break; 1231 } 1232 1233 if (rtlpriv->dm.undec_sm_pwdb > 1234 (long)high_rssithresh_for_ra) 1235 p_ra->ratr_state = DM_RATR_STA_HIGH; 1236 else if (rtlpriv->dm.undec_sm_pwdb > 1237 (long)low_rssithresh_for_ra) 1238 p_ra->ratr_state = DM_RATR_STA_MIDDLE; 1239 else 1240 p_ra->ratr_state = DM_RATR_STA_LOW; 1241 1242 if (p_ra->pre_ratr_state != p_ra->ratr_state) { 1243 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD, 1244 "RSSI = %ld\n", 1245 rtlpriv->dm.undec_sm_pwdb); 1246 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD, 1247 "RSSI_LEVEL = %d\n", p_ra->ratr_state); 1248 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD, 1249 "PreState = %d, CurState = %d\n", 1250 p_ra->pre_ratr_state, p_ra->ratr_state); 1251 1252 rcu_read_lock(); 1253 sta = rtl_find_sta(hw, mac->bssid); 1254 if (sta) 1255 rtlpriv->cfg->ops->update_rate_tbl(hw, sta, 1256 p_ra->ratr_state); 1257 rcu_read_unlock(); 1258 1259 p_ra->pre_ratr_state = p_ra->ratr_state; 1260 } 1261 } 1262} 1263 1264static void rtl92c_dm_init_dynamic_bb_powersaving(struct ieee80211_hw *hw) 1265{ 1266 struct rtl_priv *rtlpriv = rtl_priv(hw); 1267 struct ps_t *dm_pstable = &rtlpriv->dm_pstable; 1268 1269 dm_pstable->pre_ccastate = CCA_MAX; 1270 dm_pstable->cur_ccasate = CCA_MAX; 1271 dm_pstable->pre_rfstate = RF_MAX; 1272 dm_pstable->cur_rfstate = RF_MAX; 1273 dm_pstable->rssi_val_min = 0; 1274} 1275 1276static void rtl88e_dm_update_rx_idle_ant(struct ieee80211_hw *hw, 1277 u8 ant) 1278{ 1279 struct rtl_priv *rtlpriv = rtl_priv(hw); 1280 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1281 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw)); 1282 struct fast_ant_training *pfat_table = &rtldm->fat_table; 1283 u32 default_ant, optional_ant; 1284 1285 if (pfat_table->rx_idle_ant != ant) { 1286 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1287 "need to update rx idle ant\n"); 1288 if (ant == MAIN_ANT) { 1289 default_ant = 1290 (pfat_table->rx_idle_ant == CG_TRX_HW_ANTDIV) ? 1291 MAIN_ANT_CG_TRX : MAIN_ANT_CGCS_RX; 1292 optional_ant = 1293 (pfat_table->rx_idle_ant == CG_TRX_HW_ANTDIV) ? 1294 AUX_ANT_CG_TRX : AUX_ANT_CGCS_RX; 1295 } else { 1296 default_ant = 1297 (pfat_table->rx_idle_ant == CG_TRX_HW_ANTDIV) ? 1298 AUX_ANT_CG_TRX : AUX_ANT_CGCS_RX; 1299 optional_ant = 1300 (pfat_table->rx_idle_ant == CG_TRX_HW_ANTDIV) ? 1301 MAIN_ANT_CG_TRX : MAIN_ANT_CGCS_RX; 1302 } 1303 1304 if (rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV) { 1305 rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N, 1306 BIT(5) | BIT(4) | BIT(3), default_ant); 1307 rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N, 1308 BIT(8) | BIT(7) | BIT(6), optional_ant); 1309 rtl_set_bbreg(hw, DM_REG_ANTSEL_CTRL_11N, 1310 BIT(14) | BIT(13) | BIT(12), 1311 default_ant); 1312 rtl_set_bbreg(hw, DM_REG_RESP_TX_11N, 1313 BIT(6) | BIT(7), default_ant); 1314 } else if (rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV) { 1315 rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N, 1316 BIT(5) | BIT(4) | BIT(3), default_ant); 1317 rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N, 1318 BIT(8) | BIT(7) | BIT(6), optional_ant); 1319 } 1320 } 1321 pfat_table->rx_idle_ant = ant; 1322 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "RxIdleAnt %s\n", 1323 (ant == MAIN_ANT) ? ("MAIN_ANT") : ("AUX_ANT")); 1324} 1325 1326static void rtl88e_dm_update_tx_ant(struct ieee80211_hw *hw, 1327 u8 ant, u32 mac_id) 1328{ 1329 struct rtl_priv *rtlpriv = rtl_priv(hw); 1330 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw)); 1331 struct fast_ant_training *pfat_table = &rtldm->fat_table; 1332 u8 target_ant; 1333 1334 if (ant == MAIN_ANT) 1335 target_ant = MAIN_ANT_CG_TRX; 1336 else 1337 target_ant = AUX_ANT_CG_TRX; 1338 1339 pfat_table->antsel_a[mac_id] = target_ant & BIT(0); 1340 pfat_table->antsel_b[mac_id] = (target_ant & BIT(1)) >> 1; 1341 pfat_table->antsel_c[mac_id] = (target_ant & BIT(2)) >> 2; 1342 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "txfrominfo target ant %s\n", 1343 (ant == MAIN_ANT) ? ("MAIN_ANT") : ("AUX_ANT")); 1344 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "antsel_tr_mux = 3'b%d%d%d\n", 1345 pfat_table->antsel_c[mac_id], 1346 pfat_table->antsel_b[mac_id], 1347 pfat_table->antsel_a[mac_id]); 1348} 1349 1350static void rtl88e_dm_rx_hw_antena_div_init(struct ieee80211_hw *hw) 1351{ 1352 u32 value32; 1353 1354 /*MAC Setting*/ 1355 value32 = rtl_get_bbreg(hw, DM_REG_ANTSEL_PIN_11N, MASKDWORD); 1356 rtl_set_bbreg(hw, DM_REG_ANTSEL_PIN_11N, 1357 MASKDWORD, value32 | (BIT(23) | BIT(25))); 1358 /*Pin Setting*/ 1359 rtl_set_bbreg(hw, DM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0); 1360 rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N, BIT(10), 0); 1361 rtl_set_bbreg(hw, DM_REG_LNA_SWITCH_11N, BIT(22), 1); 1362 rtl_set_bbreg(hw, DM_REG_LNA_SWITCH_11N, BIT(31), 1); 1363 /*OFDM Setting*/ 1364 rtl_set_bbreg(hw, DM_REG_ANTDIV_PARA1_11N, MASKDWORD, 0x000000a0); 1365 /*CCK Setting*/ 1366 rtl_set_bbreg(hw, DM_REG_BB_PWR_SAV4_11N, BIT(7), 1); 1367 rtl_set_bbreg(hw, DM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1); 1368 rtl88e_dm_update_rx_idle_ant(hw, MAIN_ANT); 1369 rtl_set_bbreg(hw, DM_REG_ANT_MAPPING1_11N, MASKLWORD, 0x0201); 1370} 1371 1372static void rtl88e_dm_trx_hw_antenna_div_init(struct ieee80211_hw *hw) 1373{ 1374 u32 value32; 1375 1376 /*MAC Setting*/ 1377 value32 = rtl_get_bbreg(hw, DM_REG_ANTSEL_PIN_11N, MASKDWORD); 1378 rtl_set_bbreg(hw, DM_REG_ANTSEL_PIN_11N, MASKDWORD, 1379 value32 | (BIT(23) | BIT(25))); 1380 /*Pin Setting*/ 1381 rtl_set_bbreg(hw, DM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0); 1382 rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N, BIT(10), 0); 1383 rtl_set_bbreg(hw, DM_REG_LNA_SWITCH_11N, BIT(22), 0); 1384 rtl_set_bbreg(hw, DM_REG_LNA_SWITCH_11N, BIT(31), 1); 1385 /*OFDM Setting*/ 1386 rtl_set_bbreg(hw, DM_REG_ANTDIV_PARA1_11N, MASKDWORD, 0x000000a0); 1387 /*CCK Setting*/ 1388 rtl_set_bbreg(hw, DM_REG_BB_PWR_SAV4_11N, BIT(7), 1); 1389 rtl_set_bbreg(hw, DM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1); 1390 /*TX Setting*/ 1391 rtl_set_bbreg(hw, DM_REG_TX_ANT_CTRL_11N, BIT(21), 0); 1392 rtl88e_dm_update_rx_idle_ant(hw, MAIN_ANT); 1393 rtl_set_bbreg(hw, DM_REG_ANT_MAPPING1_11N, MASKLWORD, 0x0201); 1394} 1395 1396static void rtl88e_dm_fast_training_init(struct ieee80211_hw *hw) 1397{ 1398 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw)); 1399 struct fast_ant_training *pfat_table = &rtldm->fat_table; 1400 u32 ant_combination = 2; 1401 u32 value32, i; 1402 1403 for (i = 0; i < 6; i++) { 1404 pfat_table->bssid[i] = 0; 1405 pfat_table->ant_sum[i] = 0; 1406 pfat_table->ant_cnt[i] = 0; 1407 pfat_table->ant_ave[i] = 0; 1408 } 1409 pfat_table->train_idx = 0; 1410 pfat_table->fat_state = FAT_NORMAL_STATE; 1411 1412 /*MAC Setting*/ 1413 value32 = rtl_get_bbreg(hw, DM_REG_ANTSEL_PIN_11N, MASKDWORD); 1414 rtl_set_bbreg(hw, DM_REG_ANTSEL_PIN_11N, 1415 MASKDWORD, value32 | (BIT(23) | BIT(25))); 1416 value32 = rtl_get_bbreg(hw, DM_REG_ANT_TRAIN_PARA2_11N, MASKDWORD); 1417 rtl_set_bbreg(hw, DM_REG_ANT_TRAIN_PARA2_11N, 1418 MASKDWORD, value32 | (BIT(16) | BIT(17))); 1419 rtl_set_bbreg(hw, DM_REG_ANT_TRAIN_PARA2_11N, 1420 MASKLWORD, 0); 1421 rtl_set_bbreg(hw, DM_REG_ANT_TRAIN_PARA1_11N, 1422 MASKDWORD, 0); 1423 1424 /*Pin Setting*/ 1425 rtl_set_bbreg(hw, DM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0); 1426 rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N, BIT(10), 0); 1427 rtl_set_bbreg(hw, DM_REG_LNA_SWITCH_11N, BIT(22), 0); 1428 rtl_set_bbreg(hw, DM_REG_LNA_SWITCH_11N, BIT(31), 1); 1429 1430 /*OFDM Setting*/ 1431 rtl_set_bbreg(hw, DM_REG_ANTDIV_PARA1_11N, MASKDWORD, 0x000000a0); 1432 /*antenna mapping table*/ 1433 rtl_set_bbreg(hw, DM_REG_ANT_MAPPING1_11N, MASKBYTE0, 1); 1434 rtl_set_bbreg(hw, DM_REG_ANT_MAPPING1_11N, MASKBYTE1, 2); 1435 1436 /*TX Setting*/ 1437 rtl_set_bbreg(hw, DM_REG_TX_ANT_CTRL_11N, BIT(21), 1); 1438 rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N, 1439 BIT(5) | BIT(4) | BIT(3), 0); 1440 rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N, 1441 BIT(8) | BIT(7) | BIT(6), 1); 1442 rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N, 1443 BIT(2) | BIT(1) | BIT(0), (ant_combination - 1)); 1444 1445 rtl_set_bbreg(hw, DM_REG_IGI_A_11N, BIT(7), 1); 1446} 1447 1448static void rtl88e_dm_antenna_div_init(struct ieee80211_hw *hw) 1449{ 1450 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1451 1452 if (rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV) 1453 rtl88e_dm_rx_hw_antena_div_init(hw); 1454 else if (rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV) 1455 rtl88e_dm_trx_hw_antenna_div_init(hw); 1456 else if (rtlefuse->antenna_div_type == CG_TRX_SMART_ANTDIV) 1457 rtl88e_dm_fast_training_init(hw); 1458 1459} 1460 1461void rtl88e_dm_set_tx_ant_by_tx_info(struct ieee80211_hw *hw, 1462 u8 *pdesc, u32 mac_id) 1463{ 1464 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1465 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw)); 1466 struct fast_ant_training *pfat_table = &rtldm->fat_table; 1467 1468 if ((rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV) || 1469 (rtlefuse->antenna_div_type == CG_TRX_SMART_ANTDIV)) { 1470 SET_TX_DESC_ANTSEL_A(pdesc, pfat_table->antsel_a[mac_id]); 1471 SET_TX_DESC_ANTSEL_B(pdesc, pfat_table->antsel_b[mac_id]); 1472 SET_TX_DESC_ANTSEL_C(pdesc, pfat_table->antsel_c[mac_id]); 1473 } 1474} 1475 1476void rtl88e_dm_ant_sel_statistics(struct ieee80211_hw *hw, 1477 u8 antsel_tr_mux, u32 mac_id, 1478 u32 rx_pwdb_all) 1479{ 1480 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1481 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw)); 1482 struct fast_ant_training *pfat_table = &rtldm->fat_table; 1483 1484 if (rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV) { 1485 if (antsel_tr_mux == MAIN_ANT_CG_TRX) { 1486 pfat_table->main_ant_sum[mac_id] += rx_pwdb_all; 1487 pfat_table->main_ant_cnt[mac_id]++; 1488 } else { 1489 pfat_table->aux_ant_sum[mac_id] += rx_pwdb_all; 1490 pfat_table->aux_ant_cnt[mac_id]++; 1491 } 1492 } else if (rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV) { 1493 if (antsel_tr_mux == MAIN_ANT_CGCS_RX) { 1494 pfat_table->main_ant_sum[mac_id] += rx_pwdb_all; 1495 pfat_table->main_ant_cnt[mac_id]++; 1496 } else { 1497 pfat_table->aux_ant_sum[mac_id] += rx_pwdb_all; 1498 pfat_table->aux_ant_cnt[mac_id]++; 1499 } 1500 } 1501} 1502 1503static void rtl88e_dm_hw_ant_div(struct ieee80211_hw *hw) 1504{ 1505 struct rtl_priv *rtlpriv = rtl_priv(hw); 1506 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1507 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw)); 1508 struct rtl_sta_info *drv_priv; 1509 struct fast_ant_training *pfat_table = &rtldm->fat_table; 1510 struct dig_t *dm_dig = &rtlpriv->dm_digtable; 1511 u32 i, min_rssi = 0xff, ant_div_max_rssi = 0; 1512 u32 max_rssi = 0, local_min_rssi, local_max_rssi; 1513 u32 main_rssi, aux_rssi; 1514 u8 rx_idle_ant = 0, target_ant = 7; 1515 1516 /*for sta its self*/ 1517 i = 0; 1518 main_rssi = (pfat_table->main_ant_cnt[i] != 0) ? 1519 (pfat_table->main_ant_sum[i] / pfat_table->main_ant_cnt[i]) : 0; 1520 aux_rssi = (pfat_table->aux_ant_cnt[i] != 0) ? 1521 (pfat_table->aux_ant_sum[i] / pfat_table->aux_ant_cnt[i]) : 0; 1522 target_ant = (main_rssi == aux_rssi) ? 1523 pfat_table->rx_idle_ant : ((main_rssi >= aux_rssi) ? 1524 MAIN_ANT : AUX_ANT); 1525 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1526 "main_ant_sum %d main_ant_cnt %d\n", 1527 pfat_table->main_ant_sum[i], 1528 pfat_table->main_ant_cnt[i]); 1529 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1530 "aux_ant_sum %d aux_ant_cnt %d\n", 1531 pfat_table->aux_ant_sum[i], pfat_table->aux_ant_cnt[i]); 1532 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "main_rssi %d aux_rssi%d\n", 1533 main_rssi, aux_rssi); 1534 local_max_rssi = (main_rssi > aux_rssi) ? main_rssi : aux_rssi; 1535 if ((local_max_rssi > ant_div_max_rssi) && (local_max_rssi < 40)) 1536 ant_div_max_rssi = local_max_rssi; 1537 if (local_max_rssi > max_rssi) 1538 max_rssi = local_max_rssi; 1539 1540 if ((pfat_table->rx_idle_ant == MAIN_ANT) && (main_rssi == 0)) 1541 main_rssi = aux_rssi; 1542 else if ((pfat_table->rx_idle_ant == AUX_ANT) && (aux_rssi == 0)) 1543 aux_rssi = main_rssi; 1544 1545 local_min_rssi = (main_rssi > aux_rssi) ? aux_rssi : main_rssi; 1546 if (local_min_rssi < min_rssi) { 1547 min_rssi = local_min_rssi; 1548 rx_idle_ant = target_ant; 1549 } 1550 if (rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV) 1551 rtl88e_dm_update_tx_ant(hw, target_ant, i); 1552 1553 if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP || 1554 rtlpriv->mac80211.opmode == NL80211_IFTYPE_ADHOC) { 1555 spin_lock_bh(&rtlpriv->locks.entry_list_lock); 1556 list_for_each_entry(drv_priv, &rtlpriv->entry_list, list) { 1557 i++; 1558 main_rssi = (pfat_table->main_ant_cnt[i] != 0) ? 1559 (pfat_table->main_ant_sum[i] / 1560 pfat_table->main_ant_cnt[i]) : 0; 1561 aux_rssi = (pfat_table->aux_ant_cnt[i] != 0) ? 1562 (pfat_table->aux_ant_sum[i] / 1563 pfat_table->aux_ant_cnt[i]) : 0; 1564 target_ant = (main_rssi == aux_rssi) ? 1565 pfat_table->rx_idle_ant : ((main_rssi >= 1566 aux_rssi) ? MAIN_ANT : AUX_ANT); 1567 1568 local_max_rssi = (main_rssi > aux_rssi) ? 1569 main_rssi : aux_rssi; 1570 if ((local_max_rssi > ant_div_max_rssi) && 1571 (local_max_rssi < 40)) 1572 ant_div_max_rssi = local_max_rssi; 1573 if (local_max_rssi > max_rssi) 1574 max_rssi = local_max_rssi; 1575 1576 if ((pfat_table->rx_idle_ant == MAIN_ANT) && 1577 (main_rssi == 0)) 1578 main_rssi = aux_rssi; 1579 else if ((pfat_table->rx_idle_ant == AUX_ANT) && 1580 (aux_rssi == 0)) 1581 aux_rssi = main_rssi; 1582 1583 local_min_rssi = (main_rssi > aux_rssi) ? 1584 aux_rssi : main_rssi; 1585 if (local_min_rssi < min_rssi) { 1586 min_rssi = local_min_rssi; 1587 rx_idle_ant = target_ant; 1588 } 1589 if (rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV) 1590 rtl88e_dm_update_tx_ant(hw, target_ant, i); 1591 } 1592 spin_unlock_bh(&rtlpriv->locks.entry_list_lock); 1593 } 1594 1595 for (i = 0; i < ASSOCIATE_ENTRY_NUM; i++) { 1596 pfat_table->main_ant_sum[i] = 0; 1597 pfat_table->aux_ant_sum[i] = 0; 1598 pfat_table->main_ant_cnt[i] = 0; 1599 pfat_table->aux_ant_cnt[i] = 0; 1600 } 1601 1602 rtl88e_dm_update_rx_idle_ant(hw, rx_idle_ant); 1603 1604 dm_dig->antdiv_rssi_max = ant_div_max_rssi; 1605 dm_dig->rssi_max = max_rssi; 1606} 1607 1608static void rtl88e_set_next_mac_address_target(struct ieee80211_hw *hw) 1609{ 1610 struct rtl_priv *rtlpriv = rtl_priv(hw); 1611 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1612 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw)); 1613 struct rtl_sta_info *drv_priv; 1614 struct fast_ant_training *pfat_table = &rtldm->fat_table; 1615 u32 value32, i, j = 0; 1616 1617 if (mac->link_state >= MAC80211_LINKED) { 1618 for (i = 0; i < ASSOCIATE_ENTRY_NUM; i++) { 1619 if ((pfat_table->train_idx + 1) == ASSOCIATE_ENTRY_NUM) 1620 pfat_table->train_idx = 0; 1621 else 1622 pfat_table->train_idx++; 1623 1624 if (pfat_table->train_idx == 0) { 1625 value32 = (mac->mac_addr[5] << 8) | 1626 mac->mac_addr[4]; 1627 rtl_set_bbreg(hw, DM_REG_ANT_TRAIN_PARA2_11N, 1628 MASKLWORD, value32); 1629 1630 value32 = (mac->mac_addr[3] << 24) | 1631 (mac->mac_addr[2] << 16) | 1632 (mac->mac_addr[1] << 8) | 1633 mac->mac_addr[0]; 1634 rtl_set_bbreg(hw, DM_REG_ANT_TRAIN_PARA1_11N, 1635 MASKDWORD, value32); 1636 break; 1637 } 1638 1639 if (rtlpriv->mac80211.opmode != 1640 NL80211_IFTYPE_STATION) { 1641 spin_lock_bh(&rtlpriv->locks.entry_list_lock); 1642 list_for_each_entry(drv_priv, 1643 &rtlpriv->entry_list, list) { 1644 j++; 1645 if (j != pfat_table->train_idx) 1646 continue; 1647 1648 value32 = (drv_priv->mac_addr[5] << 8) | 1649 drv_priv->mac_addr[4]; 1650 rtl_set_bbreg(hw, 1651 DM_REG_ANT_TRAIN_PARA2_11N, 1652 MASKLWORD, value32); 1653 1654 value32 = (drv_priv->mac_addr[3] << 24) | 1655 (drv_priv->mac_addr[2] << 16) | 1656 (drv_priv->mac_addr[1] << 8) | 1657 drv_priv->mac_addr[0]; 1658 rtl_set_bbreg(hw, 1659 DM_REG_ANT_TRAIN_PARA1_11N, 1660 MASKDWORD, value32); 1661 break; 1662 } 1663 spin_unlock_bh(&rtlpriv->locks.entry_list_lock); 1664 /*find entry, break*/ 1665 if (j == pfat_table->train_idx) 1666 break; 1667 } 1668 } 1669 } 1670} 1671 1672static void rtl88e_dm_fast_ant_training(struct ieee80211_hw *hw) 1673{ 1674 struct rtl_priv *rtlpriv = rtl_priv(hw); 1675 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw)); 1676 struct fast_ant_training *pfat_table = &rtldm->fat_table; 1677 u32 i, max_rssi = 0; 1678 u8 target_ant = 2; 1679 bool bpkt_filter_match = false; 1680 1681 if (pfat_table->fat_state == FAT_TRAINING_STATE) { 1682 for (i = 0; i < 7; i++) { 1683 if (pfat_table->ant_cnt[i] == 0) { 1684 pfat_table->ant_ave[i] = 0; 1685 } else { 1686 pfat_table->ant_ave[i] = 1687 pfat_table->ant_sum[i] / 1688 pfat_table->ant_cnt[i]; 1689 bpkt_filter_match = true; 1690 } 1691 1692 if (pfat_table->ant_ave[i] > max_rssi) { 1693 max_rssi = pfat_table->ant_ave[i]; 1694 target_ant = (u8) i; 1695 } 1696 } 1697 1698 if (bpkt_filter_match == false) { 1699 rtl_set_bbreg(hw, DM_REG_TXAGC_A_1_MCS32_11N, 1700 BIT(16), 0); 1701 rtl_set_bbreg(hw, DM_REG_IGI_A_11N, BIT(7), 0); 1702 } else { 1703 rtl_set_bbreg(hw, DM_REG_TXAGC_A_1_MCS32_11N, 1704 BIT(16), 0); 1705 rtl_set_bbreg(hw, DM_REG_RX_ANT_CTRL_11N, BIT(8) | 1706 BIT(7) | BIT(6), target_ant); 1707 rtl_set_bbreg(hw, DM_REG_TX_ANT_CTRL_11N, 1708 BIT(21), 1); 1709 1710 pfat_table->antsel_a[pfat_table->train_idx] = 1711 target_ant & BIT(0); 1712 pfat_table->antsel_b[pfat_table->train_idx] = 1713 (target_ant & BIT(1)) >> 1; 1714 pfat_table->antsel_c[pfat_table->train_idx] = 1715 (target_ant & BIT(2)) >> 2; 1716 1717 if (target_ant == 0) 1718 rtl_set_bbreg(hw, DM_REG_IGI_A_11N, BIT(7), 0); 1719 } 1720 1721 for (i = 0; i < 7; i++) { 1722 pfat_table->ant_sum[i] = 0; 1723 pfat_table->ant_cnt[i] = 0; 1724 } 1725 1726 pfat_table->fat_state = FAT_NORMAL_STATE; 1727 return; 1728 } 1729 1730 if (pfat_table->fat_state == FAT_NORMAL_STATE) { 1731 rtl88e_set_next_mac_address_target(hw); 1732 1733 pfat_table->fat_state = FAT_TRAINING_STATE; 1734 rtl_set_bbreg(hw, DM_REG_TXAGC_A_1_MCS32_11N, BIT(16), 1); 1735 rtl_set_bbreg(hw, DM_REG_IGI_A_11N, BIT(7), 1); 1736 1737 mod_timer(&rtlpriv->works.fast_antenna_training_timer, 1738 jiffies + MSECS(RTL_WATCH_DOG_TIME)); 1739 } 1740} 1741 1742void rtl88e_dm_fast_antenna_training_callback(unsigned long data) 1743{ 1744 struct ieee80211_hw *hw = (struct ieee80211_hw *)data; 1745 1746 rtl88e_dm_fast_ant_training(hw); 1747} 1748 1749static void rtl88e_dm_antenna_diversity(struct ieee80211_hw *hw) 1750{ 1751 struct rtl_priv *rtlpriv = rtl_priv(hw); 1752 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1753 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1754 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw)); 1755 struct fast_ant_training *pfat_table = &rtldm->fat_table; 1756 1757 if (mac->link_state < MAC80211_LINKED) { 1758 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, "No Link\n"); 1759 if (pfat_table->becomelinked) { 1760 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, 1761 "need to turn off HW AntDiv\n"); 1762 rtl_set_bbreg(hw, DM_REG_IGI_A_11N, BIT(7), 0); 1763 rtl_set_bbreg(hw, DM_REG_CCK_ANTDIV_PARA1_11N, 1764 BIT(15), 0); 1765 if (rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV) 1766 rtl_set_bbreg(hw, DM_REG_TX_ANT_CTRL_11N, 1767 BIT(21), 0); 1768 pfat_table->becomelinked = 1769 (mac->link_state == MAC80211_LINKED) ? 1770 true : false; 1771 } 1772 return; 1773 } else { 1774 if (!pfat_table->becomelinked) { 1775 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, 1776 "Need to turn on HW AntDiv\n"); 1777 rtl_set_bbreg(hw, DM_REG_IGI_A_11N, BIT(7), 1); 1778 rtl_set_bbreg(hw, DM_REG_CCK_ANTDIV_PARA1_11N, 1779 BIT(15), 1); 1780 if (rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV) 1781 rtl_set_bbreg(hw, DM_REG_TX_ANT_CTRL_11N, 1782 BIT(21), 1); 1783 pfat_table->becomelinked = 1784 (mac->link_state >= MAC80211_LINKED) ? 1785 true : false; 1786 } 1787 } 1788 1789 if ((rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV) || 1790 (rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV)) 1791 rtl88e_dm_hw_ant_div(hw); 1792 else if (rtlefuse->antenna_div_type == CG_TRX_SMART_ANTDIV) 1793 rtl88e_dm_fast_ant_training(hw); 1794} 1795 1796void rtl88e_dm_init(struct ieee80211_hw *hw) 1797{ 1798 struct rtl_priv *rtlpriv = rtl_priv(hw); 1799 1800 rtlpriv->dm.dm_type = DM_TYPE_BYDRIVER; 1801 rtl88e_dm_diginit(hw); 1802 rtl88e_dm_init_dynamic_txpower(hw); 1803 rtl88e_dm_init_edca_turbo(hw); 1804 rtl88e_dm_init_rate_adaptive_mask(hw); 1805 rtl88e_dm_init_txpower_tracking(hw); 1806 rtl92c_dm_init_dynamic_bb_powersaving(hw); 1807 rtl88e_dm_antenna_div_init(hw); 1808} 1809 1810void rtl88e_dm_watchdog(struct ieee80211_hw *hw) 1811{ 1812 struct rtl_priv *rtlpriv = rtl_priv(hw); 1813 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1814 bool fw_current_inpsmode = false; 1815 bool fw_ps_awake = true; 1816 1817 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, 1818 (u8 *)(&fw_current_inpsmode)); 1819 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FWLPS_RF_ON, 1820 (u8 *)(&fw_ps_awake)); 1821 if (ppsc->p2p_ps_info.p2p_ps_mode) 1822 fw_ps_awake = false; 1823 1824 if ((ppsc->rfpwr_state == ERFON) && 1825 ((!fw_current_inpsmode) && fw_ps_awake) && 1826 (!ppsc->rfchange_inprogress)) { 1827 rtl88e_dm_pwdb_monitor(hw); 1828 rtl88e_dm_dig(hw); 1829 rtl88e_dm_false_alarm_counter_statistics(hw); 1830 rtl92c_dm_dynamic_txpower(hw); 1831 rtl88e_dm_check_txpower_tracking(hw); 1832 rtl88e_dm_refresh_rate_adaptive_mask(hw); 1833 rtl88e_dm_check_edca_turbo(hw); 1834 rtl88e_dm_antenna_diversity(hw); 1835 } 1836} 1837