phy.c revision d41200ad5fc6c283c8c375f52e4f8699c0eeec61
1/****************************************************************************** 2 * 3 * Copyright(c) 2009-2013 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * The full GNU General Public License is included in this distribution in the 19 * file called LICENSE. 20 * 21 * Contact Information: 22 * wlanfae <wlanfae@realtek.com> 23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 24 * Hsinchu 300, Taiwan. 25 * 26 * Larry Finger <Larry.Finger@lwfinger.net> 27 * 28 *****************************************************************************/ 29 30#include "../wifi.h" 31#include "../pci.h" 32#include "../ps.h" 33#include "reg.h" 34#include "def.h" 35#include "phy.h" 36#include "rf.h" 37#include "dm.h" 38#include "table.h" 39 40static void set_baseband_phy_config(struct ieee80211_hw *hw); 41static void set_baseband_agc_config(struct ieee80211_hw *hw); 42static void store_pwrindex_offset(struct ieee80211_hw *hw, 43 u32 regaddr, u32 bitmask, 44 u32 data); 45static bool check_cond(struct ieee80211_hw *hw, const u32 condition); 46 47static u32 rf_serial_read(struct ieee80211_hw *hw, 48 enum radio_path rfpath, u32 offset) 49{ 50 struct rtl_priv *rtlpriv = rtl_priv(hw); 51 struct rtl_phy *rtlphy = &(rtlpriv->phy); 52 struct bb_reg_def *phreg = &rtlphy->phyreg_def[rfpath]; 53 u32 newoffset; 54 u32 tmplong, tmplong2; 55 u8 rfpi_enable = 0; 56 u32 ret; 57 int jj = RF90_PATH_A; 58 int kk = RF90_PATH_B; 59 60 offset &= 0xff; 61 newoffset = offset; 62 if (RT_CANNOT_IO(hw)) { 63 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "return all one\n"); 64 return 0xFFFFFFFF; 65 } 66 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD); 67 if (rfpath == jj) 68 tmplong2 = tmplong; 69 else 70 tmplong2 = rtl_get_bbreg(hw, phreg->rfhssi_para2, MASKDWORD); 71 tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) | 72 (newoffset << 23) | BLSSIREADEDGE; 73 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, 74 tmplong & (~BLSSIREADEDGE)); 75 mdelay(1); 76 rtl_set_bbreg(hw, phreg->rfhssi_para2, MASKDWORD, tmplong2); 77 mdelay(2); 78 if (rfpath == jj) 79 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1, 80 BIT(8)); 81 else if (rfpath == kk) 82 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1, 83 BIT(8)); 84 if (rfpi_enable) 85 ret = rtl_get_bbreg(hw, phreg->rf_rbpi, BLSSIREADBACKDATA); 86 else 87 ret = rtl_get_bbreg(hw, phreg->rf_rb, BLSSIREADBACKDATA); 88 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x]= 0x%x\n", 89 rfpath, phreg->rf_rb, ret); 90 return ret; 91} 92 93static void rf_serial_write(struct ieee80211_hw *hw, 94 enum radio_path rfpath, u32 offset, 95 u32 data) 96{ 97 u32 data_and_addr; 98 u32 newoffset; 99 struct rtl_priv *rtlpriv = rtl_priv(hw); 100 struct rtl_phy *rtlphy = &(rtlpriv->phy); 101 struct bb_reg_def *phreg = &rtlphy->phyreg_def[rfpath]; 102 103 if (RT_CANNOT_IO(hw)) { 104 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "stop\n"); 105 return; 106 } 107 offset &= 0xff; 108 newoffset = offset; 109 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff; 110 rtl_set_bbreg(hw, phreg->rf3wire_offset, MASKDWORD, data_and_addr); 111 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]= 0x%x\n", 112 rfpath, phreg->rf3wire_offset, data_and_addr); 113} 114 115static u32 cal_bit_shift(u32 bitmask) 116{ 117 u32 i; 118 119 for (i = 0; i <= 31; i++) { 120 if (((bitmask >> i) & 0x1) == 1) 121 break; 122 } 123 return i; 124} 125 126static bool config_bb_with_header(struct ieee80211_hw *hw, 127 u8 configtype) 128{ 129 if (configtype == BASEBAND_CONFIG_PHY_REG) 130 set_baseband_phy_config(hw); 131 else if (configtype == BASEBAND_CONFIG_AGC_TAB) 132 set_baseband_agc_config(hw); 133 return true; 134} 135 136static bool config_bb_with_pgheader(struct ieee80211_hw *hw, 137 u8 configtype) 138{ 139 struct rtl_priv *rtlpriv = rtl_priv(hw); 140 int i; 141 u32 *table_pg; 142 u16 tbl_page_len; 143 u32 v1 = 0, v2 = 0; 144 145 tbl_page_len = RTL8188EEPHY_REG_ARRAY_PGLEN; 146 table_pg = RTL8188EEPHY_REG_ARRAY_PG; 147 148 if (configtype == BASEBAND_CONFIG_PHY_REG) { 149 for (i = 0; i < tbl_page_len; i = i + 3) { 150 v1 = table_pg[i]; 151 v2 = table_pg[i + 1]; 152 153 if (v1 < 0xcdcdcdcd) { 154 if (table_pg[i] == 0xfe) 155 mdelay(50); 156 else if (table_pg[i] == 0xfd) 157 mdelay(5); 158 else if (table_pg[i] == 0xfc) 159 mdelay(1); 160 else if (table_pg[i] == 0xfb) 161 udelay(50); 162 else if (table_pg[i] == 0xfa) 163 udelay(5); 164 else if (table_pg[i] == 0xf9) 165 udelay(1); 166 167 store_pwrindex_offset(hw, table_pg[i], 168 table_pg[i + 1], 169 table_pg[i + 2]); 170 continue; 171 } else { 172 if (!check_cond(hw, table_pg[i])) { 173 /*don't need the hw_body*/ 174 i += 2; /* skip the pair of expression*/ 175 v1 = table_pg[i]; 176 v2 = table_pg[i + 1]; 177 while (v2 != 0xDEAD) { 178 i += 3; 179 v1 = table_pg[i]; 180 v2 = table_pg[i + 1]; 181 } 182 } 183 } 184 } 185 } else { 186 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE, 187 "configtype != BaseBand_Config_PHY_REG\n"); 188 } 189 return true; 190} 191 192static bool config_parafile(struct ieee80211_hw *hw) 193{ 194 struct rtl_priv *rtlpriv = rtl_priv(hw); 195 struct rtl_phy *rtlphy = &(rtlpriv->phy); 196 struct rtl_efuse *fuse = rtl_efuse(rtl_priv(hw)); 197 bool rtstatus; 198 199 rtstatus = config_bb_with_header(hw, BASEBAND_CONFIG_PHY_REG); 200 if (rtstatus != true) { 201 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Write BB Reg Fail!!"); 202 return false; 203 } 204 205 if (fuse->autoload_failflag == false) { 206 rtlphy->pwrgroup_cnt = 0; 207 rtstatus = config_bb_with_pgheader(hw, BASEBAND_CONFIG_PHY_REG); 208 } 209 if (rtstatus != true) { 210 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "BB_PG Reg Fail!!"); 211 return false; 212 } 213 rtstatus = config_bb_with_header(hw, BASEBAND_CONFIG_AGC_TAB); 214 if (rtstatus != true) { 215 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "AGC Table Fail\n"); 216 return false; 217 } 218 rtlphy->cck_high_power = (bool) (rtl_get_bbreg(hw, 219 RFPGA0_XA_HSSIPARAMETER2, 0x200)); 220 221 return true; 222} 223 224static void rtl88e_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw) 225{ 226 struct rtl_priv *rtlpriv = rtl_priv(hw); 227 struct rtl_phy *rtlphy = &(rtlpriv->phy); 228 int jj = RF90_PATH_A; 229 int kk = RF90_PATH_B; 230 231 rtlphy->phyreg_def[jj].rfintfs = RFPGA0_XAB_RFINTERFACESW; 232 rtlphy->phyreg_def[kk].rfintfs = RFPGA0_XAB_RFINTERFACESW; 233 rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW; 234 rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW; 235 236 rtlphy->phyreg_def[jj].rfintfi = RFPGA0_XAB_RFINTERFACERB; 237 rtlphy->phyreg_def[kk].rfintfi = RFPGA0_XAB_RFINTERFACERB; 238 rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB; 239 rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB; 240 241 rtlphy->phyreg_def[jj].rfintfo = RFPGA0_XA_RFINTERFACEOE; 242 rtlphy->phyreg_def[kk].rfintfo = RFPGA0_XB_RFINTERFACEOE; 243 244 rtlphy->phyreg_def[jj].rfintfe = RFPGA0_XA_RFINTERFACEOE; 245 rtlphy->phyreg_def[kk].rfintfe = RFPGA0_XB_RFINTERFACEOE; 246 247 rtlphy->phyreg_def[jj].rf3wire_offset = RFPGA0_XA_LSSIPARAMETER; 248 rtlphy->phyreg_def[kk].rf3wire_offset = RFPGA0_XB_LSSIPARAMETER; 249 250 rtlphy->phyreg_def[jj].rflssi_select = rFPGA0_XAB_RFPARAMETER; 251 rtlphy->phyreg_def[kk].rflssi_select = rFPGA0_XAB_RFPARAMETER; 252 rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = rFPGA0_XCD_RFPARAMETER; 253 rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = rFPGA0_XCD_RFPARAMETER; 254 255 rtlphy->phyreg_def[jj].rftxgain_stage = RFPGA0_TXGAINSTAGE; 256 rtlphy->phyreg_def[kk].rftxgain_stage = RFPGA0_TXGAINSTAGE; 257 rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE; 258 rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE; 259 260 rtlphy->phyreg_def[jj].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1; 261 rtlphy->phyreg_def[kk].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1; 262 263 rtlphy->phyreg_def[jj].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2; 264 rtlphy->phyreg_def[kk].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2; 265 266 rtlphy->phyreg_def[jj].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL; 267 rtlphy->phyreg_def[kk].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL; 268 rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL; 269 rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL; 270 271 rtlphy->phyreg_def[jj].rfagc_control1 = ROFDM0_XAAGCCORE1; 272 rtlphy->phyreg_def[kk].rfagc_control1 = ROFDM0_XBAGCCORE1; 273 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1; 274 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1; 275 276 rtlphy->phyreg_def[jj].rfagc_control2 = ROFDM0_XAAGCCORE2; 277 rtlphy->phyreg_def[kk].rfagc_control2 = ROFDM0_XBAGCCORE2; 278 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2; 279 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2; 280 281 rtlphy->phyreg_def[jj].rfrxiq_imbal = ROFDM0_XARXIQIMBAL; 282 rtlphy->phyreg_def[kk].rfrxiq_imbal = ROFDM0_XBRXIQIMBAL; 283 rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBAL; 284 rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBAL; 285 286 rtlphy->phyreg_def[jj].rfrx_afe = ROFDM0_XARXAFE; 287 rtlphy->phyreg_def[kk].rfrx_afe = ROFDM0_XBRXAFE; 288 rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE; 289 rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE; 290 291 rtlphy->phyreg_def[jj].rftxiq_imbal = ROFDM0_XATXIQIMBAL; 292 rtlphy->phyreg_def[kk].rftxiq_imbal = ROFDM0_XBTXIQIMBAL; 293 rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTXIQIMBAL; 294 rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTXIQIMBAL; 295 296 rtlphy->phyreg_def[jj].rftx_afe = ROFDM0_XATXAFE; 297 rtlphy->phyreg_def[kk].rftx_afe = ROFDM0_XBTXAFE; 298 299 rtlphy->phyreg_def[jj].rf_rb = RFPGA0_XA_LSSIREADBACK; 300 rtlphy->phyreg_def[kk].rf_rb = RFPGA0_XB_LSSIREADBACK; 301 302 rtlphy->phyreg_def[jj].rf_rbpi = TRANSCEIVEA_HSPI_READBACK; 303 rtlphy->phyreg_def[kk].rf_rbpi = TRANSCEIVEB_HSPI_READBACK; 304} 305 306static bool rtl88e_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable, 307 u32 cmdtableidx, u32 cmdtablesz, 308 enum swchnlcmd_id cmdid, 309 u32 para1, u32 para2, u32 msdelay) 310{ 311 struct swchnlcmd *pcmd; 312 313 if (cmdtable == NULL) { 314 RT_ASSERT(false, "cmdtable cannot be NULL.\n"); 315 return false; 316 } 317 318 if (cmdtableidx >= cmdtablesz) 319 return false; 320 321 pcmd = cmdtable + cmdtableidx; 322 pcmd->cmdid = cmdid; 323 pcmd->para1 = para1; 324 pcmd->para2 = para2; 325 pcmd->msdelay = msdelay; 326 return true; 327} 328 329static bool chnl_step_by_step(struct ieee80211_hw *hw, 330 u8 channel, u8 *stage, u8 *step, 331 u32 *delay) 332{ 333 struct rtl_priv *rtlpriv = rtl_priv(hw); 334 struct rtl_phy *rtlphy = &(rtlpriv->phy); 335 struct swchnlcmd precommoncmd[MAX_PRECMD_CNT]; 336 u32 precommoncmdcnt; 337 struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT]; 338 u32 postcommoncmdcnt; 339 struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT]; 340 u32 rfdependcmdcnt; 341 struct swchnlcmd *currentcmd = NULL; 342 u8 rfpath; 343 u8 num_total_rfpath = rtlphy->num_total_rfpath; 344 345 precommoncmdcnt = 0; 346 rtl88e_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++, 347 MAX_PRECMD_CNT, 348 CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0); 349 rtl88e_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++, 350 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0); 351 352 postcommoncmdcnt = 0; 353 354 rtl88e_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++, 355 MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0); 356 357 rfdependcmdcnt = 0; 358 359 RT_ASSERT((channel >= 1 && channel <= 14), 360 "illegal channel for Zebra: %d\n", channel); 361 362 rtl88e_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++, 363 MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG, 364 RF_CHNLBW, channel, 10); 365 366 rtl88e_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++, 367 MAX_RFDEPENDCMD_CNT, CMDID_END, 0, 0, 368 0); 369 370 do { 371 switch (*stage) { 372 case 0: 373 currentcmd = &precommoncmd[*step]; 374 break; 375 case 1: 376 currentcmd = &rfdependcmd[*step]; 377 break; 378 case 2: 379 currentcmd = &postcommoncmd[*step]; 380 break; 381 } 382 383 if (currentcmd->cmdid == CMDID_END) { 384 if ((*stage) == 2) { 385 return true; 386 } else { 387 (*stage)++; 388 (*step) = 0; 389 continue; 390 } 391 } 392 393 switch (currentcmd->cmdid) { 394 case CMDID_SET_TXPOWEROWER_LEVEL: 395 rtl88e_phy_set_txpower_level(hw, channel); 396 break; 397 case CMDID_WRITEPORT_ULONG: 398 rtl_write_dword(rtlpriv, currentcmd->para1, 399 currentcmd->para2); 400 break; 401 case CMDID_WRITEPORT_USHORT: 402 rtl_write_word(rtlpriv, currentcmd->para1, 403 (u16) currentcmd->para2); 404 break; 405 case CMDID_WRITEPORT_UCHAR: 406 rtl_write_byte(rtlpriv, currentcmd->para1, 407 (u8) currentcmd->para2); 408 break; 409 case CMDID_RF_WRITEREG: 410 for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) { 411 rtlphy->rfreg_chnlval[rfpath] = 412 ((rtlphy->rfreg_chnlval[rfpath] & 413 0xfffffc00) | currentcmd->para2); 414 415 rtl_set_rfreg(hw, (enum radio_path)rfpath, 416 currentcmd->para1, 417 RFREG_OFFSET_MASK, 418 rtlphy->rfreg_chnlval[rfpath]); 419 } 420 break; 421 default: 422 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 423 "switch case not processed\n"); 424 break; 425 } 426 427 break; 428 } while (true); 429 430 (*delay) = currentcmd->msdelay; 431 (*step)++; 432 return false; 433} 434 435static long rtl88e_pwr_idx_dbm(struct ieee80211_hw *hw, 436 enum wireless_mode wirelessmode, 437 u8 txpwridx) 438{ 439 long offset; 440 long pwrout_dbm; 441 442 switch (wirelessmode) { 443 case WIRELESS_MODE_B: 444 offset = -7; 445 break; 446 case WIRELESS_MODE_G: 447 case WIRELESS_MODE_N_24G: 448 offset = -8; 449 break; 450 default: 451 offset = -8; 452 break; 453 } 454 pwrout_dbm = txpwridx / 2 + offset; 455 return pwrout_dbm; 456} 457 458static void rtl88e_phy_set_io(struct ieee80211_hw *hw) 459{ 460 struct rtl_priv *rtlpriv = rtl_priv(hw); 461 struct rtl_phy *rtlphy = &(rtlpriv->phy); 462 struct dig_t *dm_digtable = &rtlpriv->dm_digtable; 463 464 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, 465 "--->Cmd(%#x), set_io_inprogress(%d)\n", 466 rtlphy->current_io_type, rtlphy->set_io_inprogress); 467 switch (rtlphy->current_io_type) { 468 case IO_CMD_RESUME_DM_BY_SCAN: 469 dm_digtable->cur_igvalue = rtlphy->initgain_backup.xaagccore1; 470 /*rtl92c_dm_write_dig(hw);*/ 471 rtl88e_phy_set_txpower_level(hw, rtlphy->current_channel); 472 rtl_set_bbreg(hw, RCCK0_CCA, 0xff0000, 0x83); 473 break; 474 case IO_CMD_PAUSE_DM_BY_SCAN: 475 rtlphy->initgain_backup.xaagccore1 = dm_digtable->cur_igvalue; 476 dm_digtable->cur_igvalue = 0x17; 477 rtl_set_bbreg(hw, RCCK0_CCA, 0xff0000, 0x40); 478 break; 479 default: 480 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 481 "switch case not processed\n"); 482 break; 483 } 484 rtlphy->set_io_inprogress = false; 485 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, 486 "(%#x)\n", rtlphy->current_io_type); 487} 488 489u32 rtl88e_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask) 490{ 491 struct rtl_priv *rtlpriv = rtl_priv(hw); 492 u32 returnvalue, originalvalue, bitshift; 493 494 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 495 "regaddr(%#x), bitmask(%#x)\n", regaddr, bitmask); 496 originalvalue = rtl_read_dword(rtlpriv, regaddr); 497 bitshift = cal_bit_shift(bitmask); 498 returnvalue = (originalvalue & bitmask) >> bitshift; 499 500 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 501 "BBR MASK = 0x%x Addr[0x%x]= 0x%x\n", bitmask, 502 regaddr, originalvalue); 503 504 return returnvalue; 505} 506 507void rtl88e_phy_set_bb_reg(struct ieee80211_hw *hw, 508 u32 regaddr, u32 bitmask, u32 data) 509{ 510 struct rtl_priv *rtlpriv = rtl_priv(hw); 511 u32 originalvalue, bitshift; 512 513 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 514 "regaddr(%#x), bitmask(%#x),data(%#x)\n", 515 regaddr, bitmask, data); 516 517 if (bitmask != MASKDWORD) { 518 originalvalue = rtl_read_dword(rtlpriv, regaddr); 519 bitshift = cal_bit_shift(bitmask); 520 data = ((originalvalue & (~bitmask)) | (data << bitshift)); 521 } 522 523 rtl_write_dword(rtlpriv, regaddr, data); 524 525 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 526 "regaddr(%#x), bitmask(%#x), data(%#x)\n", 527 regaddr, bitmask, data); 528} 529 530u32 rtl88e_phy_query_rf_reg(struct ieee80211_hw *hw, 531 enum radio_path rfpath, u32 regaddr, u32 bitmask) 532{ 533 struct rtl_priv *rtlpriv = rtl_priv(hw); 534 u32 original_value, readback_value, bitshift; 535 unsigned long flags; 536 537 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 538 "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n", 539 regaddr, rfpath, bitmask); 540 541 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags); 542 543 544 original_value = rf_serial_read(hw, rfpath, regaddr); 545 bitshift = cal_bit_shift(bitmask); 546 readback_value = (original_value & bitmask) >> bitshift; 547 548 spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags); 549 550 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 551 "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n", 552 regaddr, rfpath, bitmask, original_value); 553 554 return readback_value; 555} 556 557void rtl88e_phy_set_rf_reg(struct ieee80211_hw *hw, 558 enum radio_path rfpath, 559 u32 regaddr, u32 bitmask, u32 data) 560{ 561 struct rtl_priv *rtlpriv = rtl_priv(hw); 562 u32 original_value, bitshift; 563 unsigned long flags; 564 565 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 566 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n", 567 regaddr, bitmask, data, rfpath); 568 569 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags); 570 571 if (bitmask != RFREG_OFFSET_MASK) { 572 original_value = rf_serial_read(hw, rfpath, regaddr); 573 bitshift = cal_bit_shift(bitmask); 574 data = ((original_value & (~bitmask)) | 575 (data << bitshift)); 576 } 577 578 rf_serial_write(hw, rfpath, regaddr, data); 579 580 581 spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags); 582 583 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 584 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n", 585 regaddr, bitmask, data, rfpath); 586} 587 588static bool config_mac_with_header(struct ieee80211_hw *hw) 589{ 590 struct rtl_priv *rtlpriv = rtl_priv(hw); 591 u32 i; 592 u32 arraylength; 593 u32 *ptrarray; 594 595 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Read Rtl8188EMACPHY_Array\n"); 596 arraylength = RTL8188EEMAC_1T_ARRAYLEN; 597 ptrarray = RTL8188EEMAC_1T_ARRAY; 598 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 599 "Img:RTL8188EEMAC_1T_ARRAY LEN %d\n", arraylength); 600 for (i = 0; i < arraylength; i = i + 2) 601 rtl_write_byte(rtlpriv, ptrarray[i], (u8) ptrarray[i + 1]); 602 return true; 603} 604 605bool rtl88e_phy_mac_config(struct ieee80211_hw *hw) 606{ 607 struct rtl_priv *rtlpriv = rtl_priv(hw); 608 bool rtstatus = config_mac_with_header(hw); 609 610 rtl_write_byte(rtlpriv, 0x04CA, 0x0B); 611 return rtstatus; 612} 613 614bool rtl88e_phy_bb_config(struct ieee80211_hw *hw) 615{ 616 bool rtstatus = true; 617 struct rtl_priv *rtlpriv = rtl_priv(hw); 618 u16 regval; 619 u8 reg_hwparafile = 1; 620 u32 tmp; 621 rtl88e_phy_init_bb_rf_register_definition(hw); 622 regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); 623 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, 624 regval | BIT(13) | BIT(0) | BIT(1)); 625 626 rtl_write_byte(rtlpriv, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB); 627 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 628 FEN_PPLL | FEN_PCIEA | FEN_DIO_PCIE | 629 FEN_BB_GLB_RSTN | FEN_BBRSTB); 630 tmp = rtl_read_dword(rtlpriv, 0x4c); 631 rtl_write_dword(rtlpriv, 0x4c, tmp | BIT(23)); 632 if (reg_hwparafile == 1) 633 rtstatus = config_parafile(hw); 634 return rtstatus; 635} 636 637bool rtl88e_phy_rf_config(struct ieee80211_hw *hw) 638{ 639 return rtl88e_phy_rf6052_config(hw); 640} 641 642static bool check_cond(struct ieee80211_hw *hw, 643 const u32 condition) 644{ 645 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 646 struct rtl_efuse *fuse = rtl_efuse(rtl_priv(hw)); 647 u32 _board = fuse->board_type; /*need efuse define*/ 648 u32 _interface = rtlhal->interface; 649 u32 _platform = 0x08;/*SupportPlatform */ 650 u32 cond = condition; 651 652 if (condition == 0xCDCDCDCD) 653 return true; 654 655 cond = condition & 0xFF; 656 if ((_board & cond) == 0 && cond != 0x1F) 657 return false; 658 659 cond = condition & 0xFF00; 660 cond = cond >> 8; 661 if ((_interface & cond) == 0 && cond != 0x07) 662 return false; 663 664 cond = condition & 0xFF0000; 665 cond = cond >> 16; 666 if ((_platform & cond) == 0 && cond != 0x0F) 667 return false; 668 return true; 669} 670 671static void _rtl8188e_config_rf_reg(struct ieee80211_hw *hw, 672 u32 addr, u32 data, enum radio_path rfpath, 673 u32 regaddr) 674{ 675 if (addr == 0xffe) { 676 mdelay(50); 677 } else if (addr == 0xfd) { 678 mdelay(5); 679 } else if (addr == 0xfc) { 680 mdelay(1); 681 } else if (addr == 0xfb) { 682 udelay(50); 683 } else if (addr == 0xfa) { 684 udelay(5); 685 } else if (addr == 0xf9) { 686 udelay(1); 687 } else { 688 rtl_set_rfreg(hw, rfpath, regaddr, 689 RFREG_OFFSET_MASK, 690 data); 691 udelay(1); 692 } 693} 694 695static void rtl88_config_s(struct ieee80211_hw *hw, 696 u32 addr, u32 data) 697{ 698 u32 content = 0x1000; /*RF Content: radio_a_txt*/ 699 u32 maskforphyset = (u32)(content & 0xE000); 700 701 _rtl8188e_config_rf_reg(hw, addr, data, RF90_PATH_A, 702 addr | maskforphyset); 703} 704 705static void _rtl8188e_config_bb_reg(struct ieee80211_hw *hw, 706 u32 addr, u32 data) 707{ 708 if (addr == 0xfe) { 709 mdelay(50); 710 } else if (addr == 0xfd) { 711 mdelay(5); 712 } else if (addr == 0xfc) { 713 mdelay(1); 714 } else if (addr == 0xfb) { 715 udelay(50); 716 } else if (addr == 0xfa) { 717 udelay(5); 718 } else if (addr == 0xf9) { 719 udelay(1); 720 } else { 721 rtl_set_bbreg(hw, addr, MASKDWORD, data); 722 udelay(1); 723 } 724} 725 726 727#define NEXT_PAIR(v1, v2, i) \ 728 do { \ 729 i += 2; v1 = array_table[i]; \ 730 v2 = array_table[i + 1]; \ 731 } while (0) 732 733static void set_baseband_agc_config(struct ieee80211_hw *hw) 734{ 735 int i; 736 u32 *array_table; 737 u16 arraylen; 738 struct rtl_priv *rtlpriv = rtl_priv(hw); 739 u32 v1 = 0, v2 = 0; 740 741 arraylen = RTL8188EEAGCTAB_1TARRAYLEN; 742 array_table = RTL8188EEAGCTAB_1TARRAY; 743 744 for (i = 0; i < arraylen; i += 2) { 745 v1 = array_table[i]; 746 v2 = array_table[i + 1]; 747 if (v1 < 0xCDCDCDCD) { 748 rtl_set_bbreg(hw, array_table[i], MASKDWORD, 749 array_table[i + 1]); 750 udelay(1); 751 continue; 752 } else {/*This line is the start line of branch.*/ 753 if (!check_cond(hw, array_table[i])) { 754 /*Discard the following (offset, data) pairs*/ 755 NEXT_PAIR(v1, v2, i); 756 while (v2 != 0xDEAD && v2 != 0xCDEF && 757 v2 != 0xCDCD && i < arraylen - 2) { 758 NEXT_PAIR(v1, v2, i); 759 } 760 i -= 2; /* compensate for loop's += 2*/ 761 } else { 762 /* Configure matched pairs and skip to end */ 763 NEXT_PAIR(v1, v2, i); 764 while (v2 != 0xDEAD && v2 != 0xCDEF && 765 v2 != 0xCDCD && i < arraylen - 2) { 766 rtl_set_bbreg(hw, array_table[i], 767 MASKDWORD, 768 array_table[i + 1]); 769 udelay(1); 770 NEXT_PAIR(v1, v2, i); 771 } 772 773 while (v2 != 0xDEAD && i < arraylen - 2) 774 NEXT_PAIR(v1, v2, i); 775 } 776 } 777 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 778 "The agctab_array_table[0] is %x Rtl818EEPHY_REGArray[1] is %x\n", 779 array_table[i], 780 array_table[i + 1]); 781 } 782} 783 784static void set_baseband_phy_config(struct ieee80211_hw *hw) 785{ 786 int i; 787 u32 *array_table; 788 u16 arraylen; 789 u32 v1 = 0, v2 = 0; 790 791 arraylen = RTL8188EEPHY_REG_1TARRAYLEN; 792 array_table = RTL8188EEPHY_REG_1TARRAY; 793 794 for (i = 0; i < arraylen; i += 2) { 795 v1 = array_table[i]; 796 v2 = array_table[i + 1]; 797 if (v1 < 0xcdcdcdcd) { 798 _rtl8188e_config_bb_reg(hw, v1, v2); 799 } else {/*This line is the start line of branch.*/ 800 if (!check_cond(hw, array_table[i])) { 801 /*Discard the following (offset, data) pairs*/ 802 NEXT_PAIR(v1, v2, i); 803 while (v2 != 0xDEAD && 804 v2 != 0xCDEF && 805 v2 != 0xCDCD && i < arraylen - 2) 806 NEXT_PAIR(v1, v2, i); 807 i -= 2; /* prevent from for-loop += 2*/ 808 } else { 809 /* Configure matched pairs and skip to end */ 810 NEXT_PAIR(v1, v2, i); 811 while (v2 != 0xDEAD && 812 v2 != 0xCDEF && 813 v2 != 0xCDCD && i < arraylen - 2) { 814 _rtl8188e_config_bb_reg(hw, v1, v2); 815 NEXT_PAIR(v1, v2, i); 816 } 817 818 while (v2 != 0xDEAD && i < arraylen - 2) 819 NEXT_PAIR(v1, v2, i); 820 } 821 } 822 } 823} 824 825static void store_pwrindex_offset(struct ieee80211_hw *hw, 826 u32 regaddr, u32 bitmask, 827 u32 data) 828{ 829 struct rtl_priv *rtlpriv = rtl_priv(hw); 830 struct rtl_phy *rtlphy = &(rtlpriv->phy); 831 832 if (regaddr == RTXAGC_A_RATE18_06) { 833 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][0] = data; 834 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 835 "MCSTxPowerLevelOriginalOffset[%d][0] = 0x%x\n", 836 rtlphy->pwrgroup_cnt, 837 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][0]); 838 } 839 if (regaddr == RTXAGC_A_RATE54_24) { 840 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][1] = data; 841 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 842 "MCSTxPowerLevelOriginalOffset[%d][1] = 0x%x\n", 843 rtlphy->pwrgroup_cnt, 844 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][1]); 845 } 846 if (regaddr == RTXAGC_A_CCK1_MCS32) { 847 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][6] = data; 848 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 849 "MCSTxPowerLevelOriginalOffset[%d][6] = 0x%x\n", 850 rtlphy->pwrgroup_cnt, 851 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][6]); 852 } 853 if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00) { 854 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][7] = data; 855 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 856 "MCSTxPowerLevelOriginalOffset[%d][7] = 0x%x\n", 857 rtlphy->pwrgroup_cnt, 858 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][7]); 859 } 860 if (regaddr == RTXAGC_A_MCS03_MCS00) { 861 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][2] = data; 862 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 863 "MCSTxPowerLevelOriginalOffset[%d][2] = 0x%x\n", 864 rtlphy->pwrgroup_cnt, 865 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][2]); 866 } 867 if (regaddr == RTXAGC_A_MCS07_MCS04) { 868 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][3] = data; 869 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 870 "MCSTxPowerLevelOriginalOffset[%d][3] = 0x%x\n", 871 rtlphy->pwrgroup_cnt, 872 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][3]); 873 } 874 if (regaddr == RTXAGC_A_MCS11_MCS08) { 875 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][4] = data; 876 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 877 "MCSTxPowerLevelOriginalOffset[%d][4] = 0x%x\n", 878 rtlphy->pwrgroup_cnt, 879 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][4]); 880 } 881 if (regaddr == RTXAGC_A_MCS15_MCS12) { 882 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][5] = data; 883 if (get_rf_type(rtlphy) == RF_1T1R) 884 rtlphy->pwrgroup_cnt++; 885 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 886 "MCSTxPowerLevelOriginalOffset[%d][5] = 0x%x\n", 887 rtlphy->pwrgroup_cnt, 888 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][5]); 889 } 890 if (regaddr == RTXAGC_B_RATE18_06) { 891 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][8] = data; 892 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 893 "MCSTxPowerLevelOriginalOffset[%d][8] = 0x%x\n", 894 rtlphy->pwrgroup_cnt, 895 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][8]); 896 } 897 if (regaddr == RTXAGC_B_RATE54_24) { 898 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][9] = data; 899 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 900 "MCSTxPowerLevelOriginalOffset[%d][9] = 0x%x\n", 901 rtlphy->pwrgroup_cnt, 902 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][9]); 903 } 904 if (regaddr == RTXAGC_B_CCK1_55_MCS32) { 905 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][14] = data; 906 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 907 "MCSTxPowerLevelOriginalOffset[%d][14] = 0x%x\n", 908 rtlphy->pwrgroup_cnt, 909 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][14]); 910 } 911 if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff) { 912 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][15] = data; 913 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 914 "MCSTxPowerLevelOriginalOffset[%d][15] = 0x%x\n", 915 rtlphy->pwrgroup_cnt, 916 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][15]); 917 } 918 if (regaddr == RTXAGC_B_MCS03_MCS00) { 919 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][10] = data; 920 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 921 "MCSTxPowerLevelOriginalOffset[%d][10] = 0x%x\n", 922 rtlphy->pwrgroup_cnt, 923 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][10]); 924 } 925 if (regaddr == RTXAGC_B_MCS07_MCS04) { 926 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][11] = data; 927 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 928 "MCSTxPowerLevelOriginalOffset[%d][11] = 0x%x\n", 929 rtlphy->pwrgroup_cnt, 930 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][11]); 931 } 932 if (regaddr == RTXAGC_B_MCS11_MCS08) { 933 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][12] = data; 934 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 935 "MCSTxPowerLevelOriginalOffset[%d][12] = 0x%x\n", 936 rtlphy->pwrgroup_cnt, 937 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][12]); 938 } 939 if (regaddr == RTXAGC_B_MCS15_MCS12) { 940 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][13] = data; 941 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 942 "MCSTxPowerLevelOriginalOffset[%d][13] = 0x%x\n", 943 rtlphy->pwrgroup_cnt, 944 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][13]); 945 if (get_rf_type(rtlphy) != RF_1T1R) 946 rtlphy->pwrgroup_cnt++; 947 } 948} 949 950#define READ_NEXT_RF_PAIR(v1, v2, i) \ 951 do { \ 952 i += 2; v1 = a_table[i]; \ 953 v2 = a_table[i + 1]; \ 954 } while (0) 955 956bool rtl88e_phy_config_rf_with_headerfile(struct ieee80211_hw *hw, 957 enum radio_path rfpath) 958{ 959 int i; 960 u32 *a_table; 961 u16 a_len; 962 struct rtl_priv *rtlpriv = rtl_priv(hw); 963 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 964 u32 v1 = 0, v2 = 0; 965 966 a_len = RTL8188EE_RADIOA_1TARRAYLEN; 967 a_table = RTL8188EE_RADIOA_1TARRAY; 968 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 969 "Radio_A:RTL8188EE_RADIOA_1TARRAY %d\n", a_len); 970 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Radio No %x\n", rfpath); 971 switch (rfpath) { 972 case RF90_PATH_A: 973 for (i = 0; i < a_len; i = i + 2) { 974 v1 = a_table[i]; 975 v2 = a_table[i + 1]; 976 if (v1 < 0xcdcdcdcd) { 977 rtl88_config_s(hw, v1, v2); 978 } else {/*This line is the start line of branch.*/ 979 if (!check_cond(hw, a_table[i])) { 980 /* Discard the following (offset, data) 981 * pairs 982 */ 983 READ_NEXT_RF_PAIR(v1, v2, i); 984 while (v2 != 0xDEAD && v2 != 0xCDEF && 985 v2 != 0xCDCD && i < a_len - 2) 986 READ_NEXT_RF_PAIR(v1, v2, i); 987 i -= 2; /* prevent from for-loop += 2*/ 988 } else { 989 /* Configure matched pairs and skip to 990 * end of if-else. 991 */ 992 READ_NEXT_RF_PAIR(v1, v2, i); 993 while (v2 != 0xDEAD && v2 != 0xCDEF && 994 v2 != 0xCDCD && i < a_len - 2) { 995 rtl88_config_s(hw, v1, v2); 996 READ_NEXT_RF_PAIR(v1, v2, i); 997 } 998 999 while (v2 != 0xDEAD && i < a_len - 2) 1000 READ_NEXT_RF_PAIR(v1, v2, i); 1001 } 1002 } 1003 } 1004 1005 if (rtlhal->oem_id == RT_CID_819x_HP) 1006 rtl88_config_s(hw, 0x52, 0x7E4BD); 1007 1008 break; 1009 1010 case RF90_PATH_B: 1011 case RF90_PATH_C: 1012 case RF90_PATH_D: 1013 default: 1014 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 1015 "switch case not processed\n"); 1016 break; 1017 } 1018 return true; 1019} 1020 1021void rtl88e_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw) 1022{ 1023 struct rtl_priv *rtlpriv = rtl_priv(hw); 1024 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1025 1026 rtlphy->default_initialgain[0] = rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, 1027 MASKBYTE0); 1028 rtlphy->default_initialgain[1] = rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, 1029 MASKBYTE0); 1030 rtlphy->default_initialgain[2] = rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, 1031 MASKBYTE0); 1032 rtlphy->default_initialgain[3] = rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, 1033 MASKBYTE0); 1034 1035 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1036 "Default initial gain (c50 = 0x%x, c58 = 0x%x, c60 = 0x%x, c68 = 0x%x\n", 1037 rtlphy->default_initialgain[0], 1038 rtlphy->default_initialgain[1], 1039 rtlphy->default_initialgain[2], 1040 rtlphy->default_initialgain[3]); 1041 1042 rtlphy->framesync = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3, 1043 MASKBYTE0); 1044 rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2, 1045 MASKDWORD); 1046 1047 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1048 "Default framesync (0x%x) = 0x%x\n", 1049 ROFDM0_RXDETECTOR3, rtlphy->framesync); 1050} 1051 1052void rtl88e_phy_get_txpower_level(struct ieee80211_hw *hw, long *powerlevel) 1053{ 1054 struct rtl_priv *rtlpriv = rtl_priv(hw); 1055 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1056 u8 level; 1057 long dbm; 1058 1059 level = rtlphy->cur_cck_txpwridx; 1060 dbm = rtl88e_pwr_idx_dbm(hw, WIRELESS_MODE_B, level); 1061 level = rtlphy->cur_ofdm24g_txpwridx; 1062 if (rtl88e_pwr_idx_dbm(hw, WIRELESS_MODE_G, level) > dbm) 1063 dbm = rtl88e_pwr_idx_dbm(hw, WIRELESS_MODE_G, level); 1064 level = rtlphy->cur_ofdm24g_txpwridx; 1065 if (rtl88e_pwr_idx_dbm(hw, WIRELESS_MODE_N_24G, level) > dbm) 1066 dbm = rtl88e_pwr_idx_dbm(hw, WIRELESS_MODE_N_24G, level); 1067 *powerlevel = dbm; 1068} 1069 1070static void _rtl88e_get_txpower_index(struct ieee80211_hw *hw, u8 channel, 1071 u8 *cckpower, u8 *ofdm, u8 *bw20_pwr, 1072 u8 *bw40_pwr) 1073{ 1074 struct rtl_efuse *fuse = rtl_efuse(rtl_priv(hw)); 1075 u8 i = (channel - 1); 1076 u8 rf_path = 0; 1077 int jj = RF90_PATH_A; 1078 int kk = RF90_PATH_B; 1079 1080 for (rf_path = 0; rf_path < 2; rf_path++) { 1081 if (rf_path == jj) { 1082 cckpower[jj] = fuse->txpwrlevel_cck[jj][i]; 1083 if (fuse->txpwr_ht20diff[jj][i] > 0x0f) /*-8~7 */ 1084 bw20_pwr[jj] = fuse->txpwrlevel_ht40_1s[jj][i] - 1085 (~(fuse->txpwr_ht20diff[jj][i]) + 1); 1086 else 1087 bw20_pwr[jj] = fuse->txpwrlevel_ht40_1s[jj][i] + 1088 fuse->txpwr_ht20diff[jj][i]; 1089 if (fuse->txpwr_legacyhtdiff[jj][i] > 0xf) 1090 ofdm[jj] = fuse->txpwrlevel_ht40_1s[jj][i] - 1091 (~(fuse->txpwr_legacyhtdiff[jj][i])+1); 1092 else 1093 ofdm[jj] = fuse->txpwrlevel_ht40_1s[jj][i] + 1094 fuse->txpwr_legacyhtdiff[jj][i]; 1095 bw40_pwr[jj] = fuse->txpwrlevel_ht40_1s[jj][i]; 1096 1097 } else if (rf_path == kk) { 1098 cckpower[kk] = fuse->txpwrlevel_cck[kk][i]; 1099 bw20_pwr[kk] = fuse->txpwrlevel_ht40_1s[kk][i] + 1100 fuse->txpwr_ht20diff[kk][i]; 1101 ofdm[kk] = fuse->txpwrlevel_ht40_1s[kk][i] + 1102 fuse->txpwr_legacyhtdiff[kk][i]; 1103 bw40_pwr[kk] = fuse->txpwrlevel_ht40_1s[kk][i]; 1104 } 1105 } 1106} 1107 1108static void _rtl88e_ccxpower_index_check(struct ieee80211_hw *hw, 1109 u8 channel, u8 *cckpower, 1110 u8 *ofdm, u8 *bw20_pwr, 1111 u8 *bw40_pwr) 1112{ 1113 struct rtl_priv *rtlpriv = rtl_priv(hw); 1114 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1115 1116 rtlphy->cur_cck_txpwridx = cckpower[0]; 1117 rtlphy->cur_ofdm24g_txpwridx = ofdm[0]; 1118 rtlphy->cur_bw20_txpwridx = bw20_pwr[0]; 1119 rtlphy->cur_bw40_txpwridx = bw40_pwr[0]; 1120} 1121 1122void rtl88e_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel) 1123{ 1124 struct rtl_efuse *fuse = rtl_efuse(rtl_priv(hw)); 1125 u8 cckpower[MAX_TX_COUNT] = {0}, ofdm[MAX_TX_COUNT] = {0}; 1126 u8 bw20_pwr[MAX_TX_COUNT] = {0}, bw40_pwr[MAX_TX_COUNT] = {0}; 1127 1128 if (fuse->txpwr_fromeprom == false) 1129 return; 1130 _rtl88e_get_txpower_index(hw, channel, &cckpower[0], &ofdm[0], 1131 &bw20_pwr[0], &bw40_pwr[0]); 1132 _rtl88e_ccxpower_index_check(hw, channel, &cckpower[0], &ofdm[0], 1133 &bw20_pwr[0], &bw40_pwr[0]); 1134 rtl88e_phy_rf6052_set_cck_txpower(hw, &cckpower[0]); 1135 rtl88e_phy_rf6052_set_ofdm_txpower(hw, &ofdm[0], &bw20_pwr[0], 1136 &bw40_pwr[0], channel); 1137} 1138 1139void rtl88e_phy_set_bw_mode_callback(struct ieee80211_hw *hw) 1140{ 1141 struct rtl_priv *rtlpriv = rtl_priv(hw); 1142 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1143 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1144 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1145 u8 reg_bw_opmode; 1146 u8 reg_prsr_rsc; 1147 1148 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, 1149 "Switch to %s bandwidth\n", 1150 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ? 1151 "20MHz" : "40MHz"); 1152 1153 if (is_hal_stop(rtlhal)) { 1154 rtlphy->set_bwmode_inprogress = false; 1155 return; 1156 } 1157 1158 reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE); 1159 reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2); 1160 1161 switch (rtlphy->current_chan_bw) { 1162 case HT_CHANNEL_WIDTH_20: 1163 reg_bw_opmode |= BW_OPMODE_20MHZ; 1164 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode); 1165 break; 1166 case HT_CHANNEL_WIDTH_20_40: 1167 reg_bw_opmode &= ~BW_OPMODE_20MHZ; 1168 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode); 1169 reg_prsr_rsc = 1170 (reg_prsr_rsc & 0x90) | (mac->cur_40_prime_sc << 5); 1171 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc); 1172 break; 1173 default: 1174 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 1175 "unknown bandwidth: %#X\n", rtlphy->current_chan_bw); 1176 break; 1177 } 1178 1179 switch (rtlphy->current_chan_bw) { 1180 case HT_CHANNEL_WIDTH_20: 1181 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0); 1182 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0); 1183 /* rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);*/ 1184 break; 1185 case HT_CHANNEL_WIDTH_20_40: 1186 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1); 1187 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1); 1188 1189 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND, 1190 (mac->cur_40_prime_sc >> 1)); 1191 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc); 1192 /*rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 0);*/ 1193 1194 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)), 1195 (mac->cur_40_prime_sc == 1196 HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1); 1197 break; 1198 default: 1199 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 1200 "unknown bandwidth: %#X\n", rtlphy->current_chan_bw); 1201 break; 1202 } 1203 rtl88e_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw); 1204 rtlphy->set_bwmode_inprogress = false; 1205 RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD, "\n"); 1206} 1207 1208void rtl88e_phy_set_bw_mode(struct ieee80211_hw *hw, 1209 enum nl80211_channel_type ch_type) 1210{ 1211 struct rtl_priv *rtlpriv = rtl_priv(hw); 1212 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1213 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1214 u8 tmp_bw = rtlphy->current_chan_bw; 1215 1216 if (rtlphy->set_bwmode_inprogress) 1217 return; 1218 rtlphy->set_bwmode_inprogress = true; 1219 if ((!is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) { 1220 rtl88e_phy_set_bw_mode_callback(hw); 1221 } else { 1222 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1223 "FALSE driver sleep or unload\n"); 1224 rtlphy->set_bwmode_inprogress = false; 1225 rtlphy->current_chan_bw = tmp_bw; 1226 } 1227} 1228 1229void rtl88e_phy_sw_chnl_callback(struct ieee80211_hw *hw) 1230{ 1231 struct rtl_priv *rtlpriv = rtl_priv(hw); 1232 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1233 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1234 u32 delay; 1235 1236 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, 1237 "switch to channel%d\n", rtlphy->current_channel); 1238 if (is_hal_stop(rtlhal)) 1239 return; 1240 do { 1241 if (!rtlphy->sw_chnl_inprogress) 1242 break; 1243 if (!chnl_step_by_step(hw, rtlphy->current_channel, 1244 &rtlphy->sw_chnl_stage, 1245 &rtlphy->sw_chnl_step, &delay)) { 1246 if (delay > 0) 1247 mdelay(delay); 1248 else 1249 continue; 1250 } else { 1251 rtlphy->sw_chnl_inprogress = false; 1252 } 1253 break; 1254 } while (true); 1255 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "\n"); 1256} 1257 1258u8 rtl88e_phy_sw_chnl(struct ieee80211_hw *hw) 1259{ 1260 struct rtl_priv *rtlpriv = rtl_priv(hw); 1261 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1262 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1263 1264 if (rtlphy->sw_chnl_inprogress) 1265 return 0; 1266 if (rtlphy->set_bwmode_inprogress) 1267 return 0; 1268 RT_ASSERT((rtlphy->current_channel <= 14), 1269 "WIRELESS_MODE_G but channel>14"); 1270 rtlphy->sw_chnl_inprogress = true; 1271 rtlphy->sw_chnl_stage = 0; 1272 rtlphy->sw_chnl_step = 0; 1273 if (!(is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) { 1274 rtl88e_phy_sw_chnl_callback(hw); 1275 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD, 1276 "sw_chnl_inprogress false schdule workitem current channel %d\n", 1277 rtlphy->current_channel); 1278 rtlphy->sw_chnl_inprogress = false; 1279 } else { 1280 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD, 1281 "sw_chnl_inprogress false driver sleep or unload\n"); 1282 rtlphy->sw_chnl_inprogress = false; 1283 } 1284 return 1; 1285} 1286 1287static u8 _rtl88e_phy_path_a_iqk(struct ieee80211_hw *hw, bool config_pathb) 1288{ 1289 u32 reg_eac, reg_e94, reg_e9c; 1290 u8 result = 0x00; 1291 1292 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1c); 1293 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x30008c1c); 1294 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x8214032a); 1295 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x28160000); 1296 1297 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911); 1298 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000); 1299 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); 1300 1301 mdelay(IQK_DELAY_TIME); 1302 1303 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); 1304 reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD); 1305 reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD); 1306 1307 if (!(reg_eac & BIT(28)) && 1308 (((reg_e94 & 0x03FF0000) >> 16) != 0x142) && 1309 (((reg_e9c & 0x03FF0000) >> 16) != 0x42)) 1310 result |= 0x01; 1311 return result; 1312} 1313 1314static u8 _rtl88e_phy_path_b_iqk(struct ieee80211_hw *hw) 1315{ 1316 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc; 1317 u8 result = 0x00; 1318 1319 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002); 1320 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000); 1321 mdelay(IQK_DELAY_TIME); 1322 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); 1323 reg_eb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD); 1324 reg_ebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD); 1325 reg_ec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD); 1326 reg_ecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD); 1327 1328 if (!(reg_eac & BIT(31)) && 1329 (((reg_eb4 & 0x03FF0000) >> 16) != 0x142) && 1330 (((reg_ebc & 0x03FF0000) >> 16) != 0x42)) 1331 result |= 0x01; 1332 else 1333 return result; 1334 if (!(reg_eac & BIT(30)) && 1335 (((reg_ec4 & 0x03FF0000) >> 16) != 0x132) && 1336 (((reg_ecc & 0x03FF0000) >> 16) != 0x36)) 1337 result |= 0x02; 1338 return result; 1339} 1340 1341static u8 _rtl88e_phy_path_a_rx_iqk(struct ieee80211_hw *hw, bool config_pathb) 1342{ 1343 u32 reg_eac, reg_e94, reg_e9c, reg_ea4, u32temp; 1344 u8 result = 0x00; 1345 int jj = RF90_PATH_A; 1346 1347 /*Get TXIMR Setting*/ 1348 /*Modify RX IQK mode table*/ 1349 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); 1350 rtl_set_rfreg(hw, jj, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0); 1351 rtl_set_rfreg(hw, jj, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000); 1352 rtl_set_rfreg(hw, jj, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f); 1353 rtl_set_rfreg(hw, jj, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf117b); 1354 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); 1355 1356 /*IQK Setting*/ 1357 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); 1358 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x81004800); 1359 1360 /*path a IQK setting*/ 1361 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x10008c1c); 1362 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x30008c1c); 1363 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160804); 1364 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28160000); 1365 1366 /*LO calibration Setting*/ 1367 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911); 1368 /*one shot, path A LOK & iqk*/ 1369 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000); 1370 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); 1371 1372 mdelay(IQK_DELAY_TIME); 1373 1374 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD); 1375 reg_e94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD); 1376 reg_e9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD); 1377 1378 1379 if (!(reg_eac & BIT(28)) && 1380 (((reg_e94 & 0x03FF0000) >> 16) != 0x142) && 1381 (((reg_e9c & 0x03FF0000) >> 16) != 0x42)) 1382 result |= 0x01; 1383 else 1384 return result; 1385 1386 u32temp = 0x80007C00 | (reg_e94&0x3FF0000) | 1387 ((reg_e9c&0x3FF0000) >> 16); 1388 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, u32temp); 1389 /*RX IQK*/ 1390 /*Modify RX IQK mode table*/ 1391 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); 1392 rtl_set_rfreg(hw, jj, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0); 1393 rtl_set_rfreg(hw, jj, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000); 1394 rtl_set_rfreg(hw, jj, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f); 1395 rtl_set_rfreg(hw, jj, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf7ffa); 1396 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); 1397 1398 /*IQK Setting*/ 1399 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); 1400 1401 /*path a IQK setting*/ 1402 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x30008c1c); 1403 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x10008c1c); 1404 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160c05); 1405 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28160c05); 1406 1407 /*LO calibration Setting*/ 1408 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911); 1409 /*one shot, path A LOK & iqk*/ 1410 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000); 1411 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); 1412 1413 mdelay(IQK_DELAY_TIME); 1414 1415 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD); 1416 reg_e94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD); 1417 reg_e9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD); 1418 reg_ea4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_A_2, MASKDWORD); 1419 1420 if (!(reg_eac & BIT(27)) && 1421 (((reg_ea4 & 0x03FF0000) >> 16) != 0x132) && 1422 (((reg_eac & 0x03FF0000) >> 16) != 0x36)) 1423 result |= 0x02; 1424 return result; 1425} 1426 1427static void fill_iqk(struct ieee80211_hw *hw, bool iqk_ok, long result[][8], 1428 u8 final, bool btxonly) 1429{ 1430 u32 oldval_0, x, tx0_a, reg; 1431 long y, tx0_c; 1432 1433 if (final == 0xFF) { 1434 return; 1435 } else if (iqk_ok) { 1436 oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBAL, 1437 MASKDWORD) >> 22) & 0x3FF; 1438 x = result[final][0]; 1439 if ((x & 0x00000200) != 0) 1440 x = x | 0xFFFFFC00; 1441 tx0_a = (x * oldval_0) >> 8; 1442 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBAL, 0x3FF, tx0_a); 1443 rtl_set_bbreg(hw, ROFDM0_ECCATHRES, BIT(31), 1444 ((x * oldval_0 >> 7) & 0x1)); 1445 y = result[final][1]; 1446 if ((y & 0x00000200) != 0) 1447 y |= 0xFFFFFC00; 1448 tx0_c = (y * oldval_0) >> 8; 1449 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000, 1450 ((tx0_c & 0x3C0) >> 6)); 1451 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBAL, 0x003F0000, 1452 (tx0_c & 0x3F)); 1453 rtl_set_bbreg(hw, ROFDM0_ECCATHRES, BIT(29), 1454 ((y * oldval_0 >> 7) & 0x1)); 1455 if (btxonly) 1456 return; 1457 reg = result[final][2]; 1458 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBAL, 0x3FF, reg); 1459 reg = result[final][3] & 0x3F; 1460 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBAL, 0xFC00, reg); 1461 reg = (result[final][3] >> 6) & 0xF; 1462 rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg); 1463 } 1464} 1465 1466static void save_adda_reg(struct ieee80211_hw *hw, 1467 const u32 *addareg, u32 *backup, 1468 u32 registernum) 1469{ 1470 u32 i; 1471 1472 for (i = 0; i < registernum; i++) 1473 backup[i] = rtl_get_bbreg(hw, addareg[i], MASKDWORD); 1474} 1475 1476static void save_mac_reg(struct ieee80211_hw *hw, const u32 *macreg, 1477 u32 *macbackup) 1478{ 1479 struct rtl_priv *rtlpriv = rtl_priv(hw); 1480 u32 i; 1481 1482 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++) 1483 macbackup[i] = rtl_read_byte(rtlpriv, macreg[i]); 1484 macbackup[i] = rtl_read_dword(rtlpriv, macreg[i]); 1485} 1486 1487static void reload_adda(struct ieee80211_hw *hw, const u32 *addareg, 1488 u32 *backup, u32 reg_num) 1489{ 1490 u32 i; 1491 1492 for (i = 0; i < reg_num; i++) 1493 rtl_set_bbreg(hw, addareg[i], MASKDWORD, backup[i]); 1494} 1495 1496static void reload_mac(struct ieee80211_hw *hw, const u32 *macreg, 1497 u32 *macbackup) 1498{ 1499 struct rtl_priv *rtlpriv = rtl_priv(hw); 1500 u32 i; 1501 1502 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++) 1503 rtl_write_byte(rtlpriv, macreg[i], (u8) macbackup[i]); 1504 rtl_write_dword(rtlpriv, macreg[i], macbackup[i]); 1505} 1506 1507static void _rtl88e_phy_path_adda_on(struct ieee80211_hw *hw, 1508 const u32 *addareg, bool is_patha_on, 1509 bool is2t) 1510{ 1511 u32 pathon; 1512 u32 i; 1513 1514 pathon = is_patha_on ? 0x04db25a4 : 0x0b1b25a4; 1515 if (false == is2t) { 1516 pathon = 0x0bdb25a0; 1517 rtl_set_bbreg(hw, addareg[0], MASKDWORD, 0x0b1b25a0); 1518 } else { 1519 rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathon); 1520 } 1521 1522 for (i = 1; i < IQK_ADDA_REG_NUM; i++) 1523 rtl_set_bbreg(hw, addareg[i], MASKDWORD, pathon); 1524} 1525 1526static void _rtl88e_phy_mac_setting_calibration(struct ieee80211_hw *hw, 1527 const u32 *macreg, 1528 u32 *macbackup) 1529{ 1530 struct rtl_priv *rtlpriv = rtl_priv(hw); 1531 u32 i = 0; 1532 1533 rtl_write_byte(rtlpriv, macreg[i], 0x3F); 1534 1535 for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++) 1536 rtl_write_byte(rtlpriv, macreg[i], 1537 (u8) (macbackup[i] & (~BIT(3)))); 1538 rtl_write_byte(rtlpriv, macreg[i], (u8) (macbackup[i] & (~BIT(5)))); 1539} 1540 1541static void _rtl88e_phy_path_a_standby(struct ieee80211_hw *hw) 1542{ 1543 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0); 1544 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000); 1545 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); 1546} 1547 1548static void _rtl88e_phy_pi_mode_switch(struct ieee80211_hw *hw, bool pi_mode) 1549{ 1550 u32 mode; 1551 1552 mode = pi_mode ? 0x01000100 : 0x01000000; 1553 rtl_set_bbreg(hw, 0x820, MASKDWORD, mode); 1554 rtl_set_bbreg(hw, 0x828, MASKDWORD, mode); 1555} 1556 1557static bool sim_comp(struct ieee80211_hw *hw, long result[][8], u8 c1, u8 c2) 1558{ 1559 u32 i, j, diff, bitmap, bound; 1560 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1561 1562 u8 final[2] = {0xFF, 0xFF}; 1563 bool bresult = true, is2t = IS_92C_SERIAL(rtlhal->version); 1564 1565 if (is2t) 1566 bound = 8; 1567 else 1568 bound = 4; 1569 1570 bitmap = 0; 1571 1572 for (i = 0; i < bound; i++) { 1573 diff = (result[c1][i] > result[c2][i]) ? 1574 (result[c1][i] - result[c2][i]) : 1575 (result[c2][i] - result[c1][i]); 1576 1577 if (diff > MAX_TOLERANCE) { 1578 if ((i == 2 || i == 6) && !bitmap) { 1579 if (result[c1][i] + result[c1][i + 1] == 0) 1580 final[(i / 4)] = c2; 1581 else if (result[c2][i] + result[c2][i + 1] == 0) 1582 final[(i / 4)] = c1; 1583 else 1584 bitmap = bitmap | (1 << i); 1585 } else { 1586 bitmap = bitmap | (1 << i); 1587 } 1588 } 1589 } 1590 1591 if (bitmap == 0) { 1592 for (i = 0; i < (bound / 4); i++) { 1593 if (final[i] != 0xFF) { 1594 for (j = i * 4; j < (i + 1) * 4 - 2; j++) 1595 result[3][j] = result[final[i]][j]; 1596 bresult = false; 1597 } 1598 } 1599 return bresult; 1600 } else if (!(bitmap & 0x0F)) { 1601 for (i = 0; i < 4; i++) 1602 result[3][i] = result[c1][i]; 1603 return false; 1604 } else if (!(bitmap & 0xF0) && is2t) { 1605 for (i = 4; i < 8; i++) 1606 result[3][i] = result[c1][i]; 1607 return false; 1608 } else { 1609 return false; 1610 } 1611} 1612 1613static void _rtl88e_phy_iq_calibrate(struct ieee80211_hw *hw, 1614 long result[][8], u8 t, bool is2t) 1615{ 1616 struct rtl_priv *rtlpriv = rtl_priv(hw); 1617 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1618 u32 i; 1619 u8 patha_ok, pathb_ok; 1620 const u32 adda_reg[IQK_ADDA_REG_NUM] = { 1621 0x85c, 0xe6c, 0xe70, 0xe74, 1622 0xe78, 0xe7c, 0xe80, 0xe84, 1623 0xe88, 0xe8c, 0xed0, 0xed4, 1624 0xed8, 0xedc, 0xee0, 0xeec 1625 }; 1626 const u32 iqk_mac_reg[IQK_MAC_REG_NUM] = { 1627 0x522, 0x550, 0x551, 0x040 1628 }; 1629 const u32 iqk_bb_reg[IQK_BB_REG_NUM] = { 1630 ROFDM0_TRXPATHENABLE, ROFDM0_TRMUXPAR, RFPGA0_XCD_RFINTERFACESW, 1631 0xb68, 0xb6c, 0x870, 0x860, 0x864, 0x800 1632 }; 1633 const u32 retrycount = 2; 1634 1635 if (t == 0) { 1636 save_adda_reg(hw, adda_reg, rtlphy->adda_backup, 16); 1637 save_mac_reg(hw, iqk_mac_reg, rtlphy->iqk_mac_backup); 1638 save_adda_reg(hw, iqk_bb_reg, rtlphy->iqk_bb_backup, 1639 IQK_BB_REG_NUM); 1640 } 1641 _rtl88e_phy_path_adda_on(hw, adda_reg, true, is2t); 1642 if (t == 0) { 1643 rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw, 1644 RFPGA0_XA_HSSIPARAMETER1, BIT(8)); 1645 } 1646 1647 if (!rtlphy->rfpi_enable) 1648 _rtl88e_phy_pi_mode_switch(hw, true); 1649 /*BB Setting*/ 1650 rtl_set_bbreg(hw, 0x800, BIT(24), 0x00); 1651 rtl_set_bbreg(hw, 0xc04, MASKDWORD, 0x03a05600); 1652 rtl_set_bbreg(hw, 0xc08, MASKDWORD, 0x000800e4); 1653 rtl_set_bbreg(hw, 0x874, MASKDWORD, 0x22204000); 1654 1655 rtl_set_bbreg(hw, 0x870, BIT(10), 0x01); 1656 rtl_set_bbreg(hw, 0x870, BIT(26), 0x01); 1657 rtl_set_bbreg(hw, 0x860, BIT(10), 0x00); 1658 rtl_set_bbreg(hw, 0x864, BIT(10), 0x00); 1659 1660 if (is2t) { 1661 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000); 1662 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00010000); 1663 } 1664 _rtl88e_phy_mac_setting_calibration(hw, iqk_mac_reg, 1665 rtlphy->iqk_mac_backup); 1666 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000); 1667 if (is2t) 1668 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000); 1669 1670 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); 1671 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00); 1672 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x81004800); 1673 for (i = 0; i < retrycount; i++) { 1674 patha_ok = _rtl88e_phy_path_a_iqk(hw, is2t); 1675 if (patha_ok == 0x01) { 1676 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1677 "Path A Tx IQK Success!!\n"); 1678 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & 1679 0x3FF0000) >> 16; 1680 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & 1681 0x3FF0000) >> 16; 1682 break; 1683 } 1684 } 1685 1686 for (i = 0; i < retrycount; i++) { 1687 patha_ok = _rtl88e_phy_path_a_rx_iqk(hw, is2t); 1688 if (patha_ok == 0x03) { 1689 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1690 "Path A Rx IQK Success!!\n"); 1691 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) & 1692 0x3FF0000) >> 16; 1693 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) & 1694 0x3FF0000) >> 16; 1695 break; 1696 } else { 1697 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1698 "Path a RX iqk fail!!!\n"); 1699 } 1700 } 1701 1702 if (0 == patha_ok) { 1703 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1704 "Path A IQK Success!!\n"); 1705 } 1706 if (is2t) { 1707 _rtl88e_phy_path_a_standby(hw); 1708 _rtl88e_phy_path_adda_on(hw, adda_reg, false, is2t); 1709 for (i = 0; i < retrycount; i++) { 1710 pathb_ok = _rtl88e_phy_path_b_iqk(hw); 1711 if (pathb_ok == 0x03) { 1712 result[t][4] = (rtl_get_bbreg(hw, 1713 0xeb4, MASKDWORD) & 1714 0x3FF0000) >> 16; 1715 result[t][5] = 1716 (rtl_get_bbreg(hw, 0xebc, MASKDWORD) & 1717 0x3FF0000) >> 16; 1718 result[t][6] = 1719 (rtl_get_bbreg(hw, 0xec4, MASKDWORD) & 1720 0x3FF0000) >> 16; 1721 result[t][7] = 1722 (rtl_get_bbreg(hw, 0xecc, MASKDWORD) & 1723 0x3FF0000) >> 16; 1724 break; 1725 } else if (i == (retrycount - 1) && pathb_ok == 0x01) { 1726 result[t][4] = (rtl_get_bbreg(hw, 1727 0xeb4, MASKDWORD) & 1728 0x3FF0000) >> 16; 1729 } 1730 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) & 1731 0x3FF0000) >> 16; 1732 } 1733 } 1734 1735 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0); 1736 1737 if (t != 0) { 1738 if (!rtlphy->rfpi_enable) 1739 _rtl88e_phy_pi_mode_switch(hw, false); 1740 reload_adda(hw, adda_reg, rtlphy->adda_backup, 16); 1741 reload_mac(hw, iqk_mac_reg, rtlphy->iqk_mac_backup); 1742 reload_adda(hw, iqk_bb_reg, rtlphy->iqk_bb_backup, 1743 IQK_BB_REG_NUM); 1744 1745 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00032ed3); 1746 if (is2t) 1747 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00032ed3); 1748 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x01008c00); 1749 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x01008c00); 1750 } 1751 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "88ee IQK Finish!!\n"); 1752} 1753 1754static void _rtl88e_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t) 1755{ 1756 u8 tmpreg; 1757 u32 rf_a_mode = 0, rf_b_mode = 0, lc_cal; 1758 struct rtl_priv *rtlpriv = rtl_priv(hw); 1759 int jj = RF90_PATH_A; 1760 int kk = RF90_PATH_B; 1761 1762 tmpreg = rtl_read_byte(rtlpriv, 0xd03); 1763 1764 if ((tmpreg & 0x70) != 0) 1765 rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F); 1766 else 1767 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); 1768 1769 if ((tmpreg & 0x70) != 0) { 1770 rf_a_mode = rtl_get_rfreg(hw, jj, 0x00, MASK12BITS); 1771 1772 if (is2t) 1773 rf_b_mode = rtl_get_rfreg(hw, kk, 0x00, 1774 MASK12BITS); 1775 1776 rtl_set_rfreg(hw, jj, 0x00, MASK12BITS, 1777 (rf_a_mode & 0x8FFFF) | 0x10000); 1778 1779 if (is2t) 1780 rtl_set_rfreg(hw, kk, 0x00, MASK12BITS, 1781 (rf_b_mode & 0x8FFFF) | 0x10000); 1782 } 1783 lc_cal = rtl_get_rfreg(hw, jj, 0x18, MASK12BITS); 1784 1785 rtl_set_rfreg(hw, jj, 0x18, MASK12BITS, lc_cal | 0x08000); 1786 1787 mdelay(100); 1788 1789 if ((tmpreg & 0x70) != 0) { 1790 rtl_write_byte(rtlpriv, 0xd03, tmpreg); 1791 rtl_set_rfreg(hw, jj, 0x00, MASK12BITS, rf_a_mode); 1792 1793 if (is2t) 1794 rtl_set_rfreg(hw, kk, 0x00, MASK12BITS, 1795 rf_b_mode); 1796 } else { 1797 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); 1798 } 1799 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "\n"); 1800} 1801 1802static void rfpath_switch(struct ieee80211_hw *hw, 1803 bool bmain, bool is2t) 1804{ 1805 struct rtl_priv *rtlpriv = rtl_priv(hw); 1806 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1807 struct rtl_efuse *fuse = rtl_efuse(rtl_priv(hw)); 1808 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "\n"); 1809 1810 if (is_hal_stop(rtlhal)) { 1811 u8 u1btmp; 1812 u1btmp = rtl_read_byte(rtlpriv, REG_LEDCFG0); 1813 rtl_write_byte(rtlpriv, REG_LEDCFG0, u1btmp | BIT(7)); 1814 rtl_set_bbreg(hw, rFPGA0_XAB_RFPARAMETER, BIT(13), 0x01); 1815 } 1816 if (is2t) { 1817 if (bmain) 1818 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, 1819 BIT(5) | BIT(6), 0x1); 1820 else 1821 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, 1822 BIT(5) | BIT(6), 0x2); 1823 } else { 1824 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BIT(8) | BIT(9), 0); 1825 rtl_set_bbreg(hw, 0x914, MASKLWORD, 0x0201); 1826 1827 /* We use the RF definition of MAIN and AUX, left antenna and 1828 * right antenna repectively. 1829 * Default output at AUX. 1830 */ 1831 if (bmain) { 1832 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(14) | 1833 BIT(13) | BIT(12), 0); 1834 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, BIT(5) | 1835 BIT(4) | BIT(3), 0); 1836 if (fuse->antenna_div_type == CGCS_RX_HW_ANTDIV) 1837 rtl_set_bbreg(hw, RCONFIG_RAM64X16, BIT(31), 0); 1838 } else { 1839 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(14) | 1840 BIT(13) | BIT(12), 1); 1841 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, BIT(5) | 1842 BIT(4) | BIT(3), 1); 1843 if (fuse->antenna_div_type == CGCS_RX_HW_ANTDIV) 1844 rtl_set_bbreg(hw, RCONFIG_RAM64X16, BIT(31), 1); 1845 } 1846 } 1847} 1848 1849#undef IQK_ADDA_REG_NUM 1850#undef IQK_DELAY_TIME 1851 1852void rtl88e_phy_iq_calibrate(struct ieee80211_hw *hw, bool recovery) 1853{ 1854 struct rtl_priv *rtlpriv = rtl_priv(hw); 1855 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1856 long result[4][8]; 1857 u8 i, final; 1858 bool patha_ok; 1859 long reg_e94, reg_e9c, reg_ea4, reg_eb4, reg_ebc, reg_tmp = 0; 1860 bool is12simular, is13simular, is23simular; 1861 u32 iqk_bb_reg[9] = { 1862 ROFDM0_XARXIQIMBAL, 1863 ROFDM0_XBRXIQIMBAL, 1864 ROFDM0_ECCATHRES, 1865 ROFDM0_AGCRSSITABLE, 1866 ROFDM0_XATXIQIMBAL, 1867 ROFDM0_XBTXIQIMBAL, 1868 ROFDM0_XCTXAFE, 1869 ROFDM0_XDTXAFE, 1870 ROFDM0_RXIQEXTANTA 1871 }; 1872 1873 if (recovery) { 1874 reload_adda(hw, iqk_bb_reg, rtlphy->iqk_bb_backup, 9); 1875 return; 1876 } 1877 1878 memset(result, 0, 32 * sizeof(long)); 1879 final = 0xff; 1880 patha_ok = false; 1881 is12simular = false; 1882 is23simular = false; 1883 is13simular = false; 1884 for (i = 0; i < 3; i++) { 1885 if (get_rf_type(rtlphy) == RF_2T2R) 1886 _rtl88e_phy_iq_calibrate(hw, result, i, true); 1887 else 1888 _rtl88e_phy_iq_calibrate(hw, result, i, false); 1889 if (i == 1) { 1890 is12simular = sim_comp(hw, result, 0, 1); 1891 if (is12simular) { 1892 final = 0; 1893 break; 1894 } 1895 } 1896 if (i == 2) { 1897 is13simular = sim_comp(hw, result, 0, 2); 1898 if (is13simular) { 1899 final = 0; 1900 break; 1901 } 1902 is23simular = sim_comp(hw, result, 1, 2); 1903 if (is23simular) { 1904 final = 1; 1905 } else { 1906 for (i = 0; i < 8; i++) 1907 reg_tmp += result[3][i]; 1908 1909 if (reg_tmp != 0) 1910 final = 3; 1911 else 1912 final = 0xFF; 1913 } 1914 } 1915 } 1916 for (i = 0; i < 4; i++) { 1917 reg_e94 = result[i][0]; 1918 reg_e9c = result[i][1]; 1919 reg_ea4 = result[i][2]; 1920 reg_eb4 = result[i][4]; 1921 reg_ebc = result[i][5]; 1922 } 1923 if (final != 0xff) { 1924 reg_e94 = result[final][0]; 1925 rtlphy->reg_e94 = reg_e94; 1926 reg_e9c = result[final][1]; 1927 rtlphy->reg_e9c = reg_e9c; 1928 reg_ea4 = result[final][2]; 1929 reg_eb4 = result[final][4]; 1930 rtlphy->reg_eb4 = reg_eb4; 1931 reg_ebc = result[final][5]; 1932 rtlphy->reg_ebc = reg_ebc; 1933 patha_ok = true; 1934 } else { 1935 rtlphy->reg_e94 = 0x100; 1936 rtlphy->reg_eb4 = 0x100; 1937 rtlphy->reg_ebc = 0x0; 1938 rtlphy->reg_e9c = 0x0; 1939 } 1940 if (reg_e94 != 0) /*&&(reg_ea4 != 0) */ 1941 fill_iqk(hw, patha_ok, result, final, (reg_ea4 == 0)); 1942 if (final != 0xFF) { 1943 for (i = 0; i < IQK_MATRIX_REG_NUM; i++) 1944 rtlphy->iqk_matrix[0].value[0][i] = result[final][i]; 1945 rtlphy->iqk_matrix[0].iqk_done = true; 1946 } 1947 save_adda_reg(hw, iqk_bb_reg, rtlphy->iqk_bb_backup, 9); 1948} 1949 1950void rtl88e_phy_lc_calibrate(struct ieee80211_hw *hw) 1951{ 1952 struct rtl_priv *rtlpriv = rtl_priv(hw); 1953 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1954 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal); 1955 bool start_conttx = false, singletone = false; 1956 u32 timeout = 2000, timecount = 0; 1957 1958 if (start_conttx || singletone) 1959 return; 1960 1961 while (rtlpriv->mac80211.act_scanning && timecount < timeout) { 1962 udelay(50); 1963 timecount += 50; 1964 } 1965 1966 rtlphy->lck_inprogress = true; 1967 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1968 "LCK:Start!!! currentband %x delay %d ms\n", 1969 rtlhal->current_bandtype, timecount); 1970 1971 _rtl88e_phy_lc_calibrate(hw, false); 1972 1973 rtlphy->lck_inprogress = false; 1974} 1975 1976void rtl88e_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain) 1977{ 1978 rfpath_switch(hw, bmain, false); 1979} 1980 1981bool rtl88e_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype) 1982{ 1983 struct rtl_priv *rtlpriv = rtl_priv(hw); 1984 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1985 bool postprocessing = false; 1986 1987 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, 1988 "-->IO Cmd(%#x), set_io_inprogress(%d)\n", 1989 iotype, rtlphy->set_io_inprogress); 1990 do { 1991 switch (iotype) { 1992 case IO_CMD_RESUME_DM_BY_SCAN: 1993 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, 1994 "[IO CMD] Resume DM after scan.\n"); 1995 postprocessing = true; 1996 break; 1997 case IO_CMD_PAUSE_DM_BY_SCAN: 1998 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, 1999 "[IO CMD] Pause DM before scan.\n"); 2000 postprocessing = true; 2001 break; 2002 default: 2003 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 2004 "switch case not processed\n"); 2005 break; 2006 } 2007 } while (false); 2008 if (postprocessing && !rtlphy->set_io_inprogress) { 2009 rtlphy->set_io_inprogress = true; 2010 rtlphy->current_io_type = iotype; 2011 } else { 2012 return false; 2013 } 2014 rtl88e_phy_set_io(hw); 2015 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, "IO Type(%#x)\n", iotype); 2016 return true; 2017} 2018 2019static void rtl88ee_phy_set_rf_on(struct ieee80211_hw *hw) 2020{ 2021 struct rtl_priv *rtlpriv = rtl_priv(hw); 2022 2023 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b); 2024 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); 2025 /*rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);*/ 2026 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); 2027 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); 2028 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); 2029} 2030 2031static void _rtl88ee_phy_set_rf_sleep(struct ieee80211_hw *hw) 2032{ 2033 struct rtl_priv *rtlpriv = rtl_priv(hw); 2034 int jj = RF90_PATH_A; 2035 2036 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); 2037 rtl_set_rfreg(hw, jj, 0x00, RFREG_OFFSET_MASK, 0x00); 2038 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); 2039 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22); 2040} 2041 2042static bool _rtl88ee_phy_set_rf_power_state(struct ieee80211_hw *hw, 2043 enum rf_pwrstate rfpwr_state) 2044{ 2045 struct rtl_priv *rtlpriv = rtl_priv(hw); 2046 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 2047 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2048 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 2049 struct rtl8192_tx_ring *ring = NULL; 2050 bool bresult = true; 2051 u8 i, queue_id; 2052 2053 switch (rfpwr_state) { 2054 case ERFON:{ 2055 if ((ppsc->rfpwr_state == ERFOFF) && 2056 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) { 2057 bool rtstatus; 2058 u32 init = 0; 2059 do { 2060 init++; 2061 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 2062 "IPS Set eRf nic enable\n"); 2063 rtstatus = rtl_ps_enable_nic(hw); 2064 } while ((rtstatus != true) && (init < 10)); 2065 RT_CLEAR_PS_LEVEL(ppsc, 2066 RT_RF_OFF_LEVL_HALT_NIC); 2067 } else { 2068 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 2069 "Set ERFON sleeped:%d ms\n", 2070 jiffies_to_msecs(jiffies - ppsc-> 2071 last_sleep_jiffies)); 2072 ppsc->last_awake_jiffies = jiffies; 2073 rtl88ee_phy_set_rf_on(hw); 2074 } 2075 if (mac->link_state == MAC80211_LINKED) 2076 rtlpriv->cfg->ops->led_control(hw, LED_CTL_LINK); 2077 else 2078 rtlpriv->cfg->ops->led_control(hw, LED_CTL_NO_LINK); 2079 break; } 2080 case ERFOFF:{ 2081 for (queue_id = 0, i = 0; 2082 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) { 2083 ring = &pcipriv->dev.tx_ring[queue_id]; 2084 if (skb_queue_len(&ring->queue) == 0) { 2085 queue_id++; 2086 continue; 2087 } else { 2088 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 2089 "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n", 2090 (i + 1), queue_id, 2091 skb_queue_len(&ring->queue)); 2092 2093 udelay(10); 2094 i++; 2095 } 2096 if (i >= MAX_DOZE_WAITING_TIMES_9x) { 2097 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 2098 "\n ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n", 2099 MAX_DOZE_WAITING_TIMES_9x, 2100 queue_id, 2101 skb_queue_len(&ring->queue)); 2102 break; 2103 } 2104 } 2105 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) { 2106 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 2107 "IPS Set eRf nic disable\n"); 2108 rtl_ps_disable_nic(hw); 2109 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 2110 } else { 2111 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) { 2112 rtlpriv->cfg->ops->led_control(hw, 2113 LED_CTL_NO_LINK); 2114 } else { 2115 rtlpriv->cfg->ops->led_control(hw, 2116 LED_CTL_POWER_OFF); 2117 } 2118 } 2119 break; } 2120 case ERFSLEEP:{ 2121 if (ppsc->rfpwr_state == ERFOFF) 2122 break; 2123 for (queue_id = 0, i = 0; 2124 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) { 2125 ring = &pcipriv->dev.tx_ring[queue_id]; 2126 if (skb_queue_len(&ring->queue) == 0) { 2127 queue_id++; 2128 continue; 2129 } else { 2130 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 2131 "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n", 2132 (i + 1), queue_id, 2133 skb_queue_len(&ring->queue)); 2134 2135 udelay(10); 2136 i++; 2137 } 2138 if (i >= MAX_DOZE_WAITING_TIMES_9x) { 2139 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 2140 "\n ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n", 2141 MAX_DOZE_WAITING_TIMES_9x, 2142 queue_id, 2143 skb_queue_len(&ring->queue)); 2144 break; 2145 } 2146 } 2147 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 2148 "Set ERFSLEEP awaked:%d ms\n", 2149 jiffies_to_msecs(jiffies - ppsc->last_awake_jiffies)); 2150 ppsc->last_sleep_jiffies = jiffies; 2151 _rtl88ee_phy_set_rf_sleep(hw); 2152 break; } 2153 default: 2154 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 2155 "switch case not processed\n"); 2156 bresult = false; 2157 break; 2158 } 2159 if (bresult) 2160 ppsc->rfpwr_state = rfpwr_state; 2161 return bresult; 2162} 2163 2164bool rtl88e_phy_set_rf_power_state(struct ieee80211_hw *hw, 2165 enum rf_pwrstate rfpwr_state) 2166{ 2167 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 2168 bool bresult; 2169 2170 if (rfpwr_state == ppsc->rfpwr_state) 2171 return false; 2172 bresult = _rtl88ee_phy_set_rf_power_state(hw, rfpwr_state); 2173 return bresult; 2174} 2175