reg.h revision 25b13dbc38a74b76da5746d75867e306b70035bd
1/****************************************************************************** 2 * 3 * Copyright(c) 2009-2013 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * The full GNU General Public License is included in this distribution in the 19 * file called LICENSE. 20 * 21 * Contact Information: 22 * wlanfae <wlanfae@realtek.com> 23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 24 * Hsinchu 300, Taiwan. 25 * 26 * Larry Finger <Larry.Finger@lwfinger.net> 27 * 28 *****************************************************************************/ 29 30#ifndef __RTL92C_REG_H__ 31#define __RTL92C_REG_H__ 32 33#define TXPKT_BUF_SELECT 0x69 34#define RXPKT_BUF_SELECT 0xA5 35#define DISABLE_TRXPKT_BUF_ACCESS 0x0 36 37#define REG_SYS_ISO_CTRL 0x0000 38#define REG_SYS_FUNC_EN 0x0002 39#define REG_APS_FSMCO 0x0004 40#define REG_SYS_CLKR 0x0008 41#define REG_9346CR 0x000A 42#define REG_EE_VPD 0x000C 43#define REG_AFE_MISC 0x0010 44#define REG_SPS0_CTRL 0x0011 45#define REG_SPS_OCP_CFG 0x0018 46#define REG_RSV_CTRL 0x001C 47#define REG_RF_CTRL 0x001F 48#define REG_LDOA15_CTRL 0x0020 49#define REG_LDOV12D_CTRL 0x0021 50#define REG_LDOHCI12_CTRL 0x0022 51#define REG_LPLDO_CTRL 0x0023 52#define REG_AFE_XTAL_CTRL 0x0024 53#define REG_AFE_LDO_CTRL 0x0027 /* 1.5v for 8188EE test 54 * chip, 1.4v for MP chip 55 */ 56#define REG_AFE_PLL_CTRL 0x0028 57#define REG_EFUSE_CTRL 0x0030 58#define REG_EFUSE_TEST 0x0034 59#define REG_PWR_DATA 0x0038 60#define REG_CAL_TIMER 0x003C 61#define REG_ACLK_MON 0x003E 62#define REG_GPIO_MUXCFG 0x0040 63#define REG_GPIO_IO_SEL 0x0042 64#define REG_MAC_PINMUX_CFG 0x0043 65#define REG_GPIO_PIN_CTRL 0x0044 66#define REG_GPIO_INTM 0x0048 67#define REG_LEDCFG0 0x004C 68#define REG_LEDCFG1 0x004D 69#define REG_LEDCFG2 0x004E 70#define REG_LEDCFG3 0x004F 71#define REG_FSIMR 0x0050 72#define REG_FSISR 0x0054 73#define REG_HSIMR 0x0058 74#define REG_HSISR 0x005c 75#define REG_GPIO_PIN_CTRL_2 0x0060 76#define REG_GPIO_IO_SEL_2 0x0062 77#define REG_GPIO_OUTPUT 0x006c 78#define REG_AFE_XTAL_CTRL_EXT 0x0078 79#define REG_XCK_OUT_CTRL 0x007c 80#define REG_MCUFWDL 0x0080 81#define REG_WOL_EVENT 0x0081 82#define REG_MCUTSTCFG 0x0084 83 84 85#define REG_HIMR 0x00B0 86#define REG_HISR 0x00B4 87#define REG_HIMRE 0x00B8 88#define REG_HISRE 0x00BC 89 90#define REG_EFUSE_ACCESS 0x00CF 91 92#define REG_BIST_SCAN 0x00D0 93#define REG_BIST_RPT 0x00D4 94#define REG_BIST_ROM_RPT 0x00D8 95#define REG_USB_SIE_INTF 0x00E0 96#define REG_PCIE_MIO_INTF 0x00E4 97#define REG_PCIE_MIO_INTD 0x00E8 98#define REG_HPON_FSM 0x00EC 99#define REG_SYS_CFG 0x00F0 100 101#define REG_CR 0x0100 102#define REG_PBP 0x0104 103#define REG_PKT_BUFF_ACCESS_CTRL 0x0106 104#define REG_TRXDMA_CTRL 0x010C 105#define REG_TRXFF_BNDY 0x0114 106#define REG_TRXFF_STATUS 0x0118 107#define REG_RXFF_PTR 0x011C 108 109#define REG_CPWM 0x012F 110#define REG_FWIMR 0x0130 111#define REG_FWISR 0x0134 112#define REG_PKTBUF_DBG_CTRL 0x0140 113#define REG_PKTBUF_DBG_DATA_L 0x0144 114#define REG_PKTBUF_DBG_DATA_H 0x0148 115#define REG_RXPKTBUF_CTRL (REG_PKTBUF_DBG_CTRL+2) 116 117#define REG_TC0_CTRL 0x0150 118#define REG_TC1_CTRL 0x0154 119#define REG_TC2_CTRL 0x0158 120#define REG_TC3_CTRL 0x015C 121#define REG_TC4_CTRL 0x0160 122#define REG_TCUNIT_BASE 0x0164 123#define REG_MBIST_START 0x0174 124#define REG_MBIST_DONE 0x0178 125#define REG_MBIST_FAIL 0x017C 126#define REG_32K_CTRL 0x0194 127#define REG_C2HEVT_MSG_NORMAL 0x01A0 128#define REG_C2HEVT_CLEAR 0x01AF 129#define REG_C2HEVT_MSG_TEST 0x01B8 130#define REG_MCUTST_1 0x01c0 131#define REG_FMETHR 0x01C8 132#define REG_HMETFR 0x01CC 133#define REG_HMEBOX_0 0x01D0 134#define REG_HMEBOX_1 0x01D4 135#define REG_HMEBOX_2 0x01D8 136#define REG_HMEBOX_3 0x01DC 137 138#define REG_LLT_INIT 0x01E0 139#define REG_BB_ACCEESS_CTRL 0x01E8 140#define REG_BB_ACCESS_DATA 0x01EC 141 142#define REG_HMEBOX_EXT_0 0x01F0 143#define REG_HMEBOX_EXT_1 0x01F4 144#define REG_HMEBOX_EXT_2 0x01F8 145#define REG_HMEBOX_EXT_3 0x01FC 146 147#define REG_RQPN 0x0200 148#define REG_FIFOPAGE 0x0204 149#define REG_TDECTRL 0x0208 150#define REG_TXDMA_OFFSET_CHK 0x020C 151#define REG_TXDMA_STATUS 0x0210 152#define REG_RQPN_NPQ 0x0214 153 154#define REG_RXDMA_AGG_PG_TH 0x0280 155#define REG_FW_UPD_RDPTR 0x0284 /* FW shall update this 156 * register before FW * write 157 * RXPKT_RELEASE_POLL to 1 158 */ 159#define REG_RXDMA_CONTROL 0x0286 /* Control the RX DMA.*/ 160#define REG_RXPKT_NUM 0x0287 /* The number of packets 161 * in RXPKTBUF. 162 */ 163#define REG_PCIE_CTRL_REG 0x0300 164#define REG_INT_MIG 0x0304 165#define REG_BCNQ_DESA 0x0308 166#define REG_HQ_DESA 0x0310 167#define REG_MGQ_DESA 0x0318 168#define REG_VOQ_DESA 0x0320 169#define REG_VIQ_DESA 0x0328 170#define REG_BEQ_DESA 0x0330 171#define REG_BKQ_DESA 0x0338 172#define REG_RX_DESA 0x0340 173 174#define REG_DBI 0x0348 175#define REG_MDIO 0x0354 176#define REG_DBG_SEL 0x0360 177#define REG_PCIE_HRPWM 0x0361 178#define REG_PCIE_HCPWM 0x0363 179#define REG_UART_CTRL 0x0364 180#define REG_WATCH_DOG 0x0368 181#define REG_UART_TX_DESA 0x0370 182#define REG_UART_RX_DESA 0x0378 183 184 185#define REG_HDAQ_DESA_NODEF 0x0000 186#define REG_CMDQ_DESA_NODEF 0x0000 187 188#define REG_VOQ_INFORMATION 0x0400 189#define REG_VIQ_INFORMATION 0x0404 190#define REG_BEQ_INFORMATION 0x0408 191#define REG_BKQ_INFORMATION 0x040C 192#define REG_MGQ_INFORMATION 0x0410 193#define REG_HGQ_INFORMATION 0x0414 194#define REG_BCNQ_INFORMATION 0x0418 195#define REG_TXPKT_EMPTY 0x041A 196 197 198#define REG_CPU_MGQ_INFORMATION 0x041C 199#define REG_FWHW_TXQ_CTRL 0x0420 200#define REG_HWSEQ_CTRL 0x0423 201#define REG_TXPKTBUF_BCNQ_BDNY 0x0424 202#define REG_TXPKTBUF_MGQ_BDNY 0x0425 203#define REG_MULTI_BCNQ_EN 0x0426 204#define REG_MULTI_BCNQ_OFFSET 0x0427 205#define REG_SPEC_SIFS 0x0428 206#define REG_RL 0x042A 207#define REG_DARFRC 0x0430 208#define REG_RARFRC 0x0438 209#define REG_RRSR 0x0440 210#define REG_ARFR0 0x0444 211#define REG_ARFR1 0x0448 212#define REG_ARFR2 0x044C 213#define REG_ARFR3 0x0450 214#define REG_AGGLEN_LMT 0x0458 215#define REG_AMPDU_MIN_SPACE 0x045C 216#define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045D 217#define REG_FAST_EDCA_CTRL 0x0460 218#define REG_RD_RESP_PKT_TH 0x0463 219#define REG_INIRTS_RATE_SEL 0x0480 220#define REG_INIDATA_RATE_SEL 0x0484 221#define REG_POWER_STATUS 0x04A4 222#define REG_POWER_STAGE1 0x04B4 223#define REG_POWER_STAGE2 0x04B8 224#define REG_PKT_LIFE_TIME 0x04C0 225#define REG_STBC_SETTING 0x04C4 226#define REG_PROT_MODE_CTRL 0x04C8 227#define REG_BAR_MODE_CTRL 0x04CC 228#define REG_RA_TRY_RATE_AGG_LMT 0x04CF 229#define REG_EARLY_MODE_CONTROL 0x04D0 230#define REG_NQOS_SEQ 0x04DC 231#define REG_QOS_SEQ 0x04DE 232#define REG_NEED_CPU_HANDLE 0x04E0 233#define REG_PKT_LOSE_RPT 0x04E1 234#define REG_PTCL_ERR_STATUS 0x04E2 235#define REG_TX_RPT_CTRL 0x04EC 236#define REG_TX_RPT_TIME 0x04F0 237#define REG_DUMMY 0x04FC 238 239#define REG_EDCA_VO_PARAM 0x0500 240#define REG_EDCA_VI_PARAM 0x0504 241#define REG_EDCA_BE_PARAM 0x0508 242#define REG_EDCA_BK_PARAM 0x050C 243#define REG_BCNTCFG 0x0510 244#define REG_PIFS 0x0512 245#define REG_RDG_PIFS 0x0513 246#define REG_SIFS_CTX 0x0514 247#define REG_SIFS_TRX 0x0516 248#define REG_AGGR_BREAK_TIME 0x051A 249#define REG_SLOT 0x051B 250#define REG_TX_PTCL_CTRL 0x0520 251#define REG_TXPAUSE 0x0522 252#define REG_DIS_TXREQ_CLR 0x0523 253#define REG_RD_CTRL 0x0524 254#define REG_TBTT_PROHIBIT 0x0540 255#define REG_RD_NAV_NXT 0x0544 256#define REG_NAV_PROT_LEN 0x0546 257#define REG_BCN_CTRL 0x0550 258#define REG_USTIME_TSF 0x0551 259#define REG_MBID_NUM 0x0552 260#define REG_DUAL_TSF_RST 0x0553 261#define REG_BCN_INTERVAL 0x0554 262#define REG_MBSSID_BCN_SPACE 0x0554 263#define REG_DRVERLYINT 0x0558 264#define REG_BCNDMATIM 0x0559 265#define REG_ATIMWND 0x055A 266#define REG_BCN_MAX_ERR 0x055D 267#define REG_RXTSF_OFFSET_CCK 0x055E 268#define REG_RXTSF_OFFSET_OFDM 0x055F 269#define REG_TSFTR 0x0560 270#define REG_INIT_TSFTR 0x0564 271#define REG_PSTIMER 0x0580 272#define REG_TIMER0 0x0584 273#define REG_TIMER1 0x0588 274#define REG_ACMHWCTRL 0x05C0 275#define REG_ACMRSTCTRL 0x05C1 276#define REG_ACMAVG 0x05C2 277#define REG_VO_ADMTIME 0x05C4 278#define REG_VI_ADMTIME 0x05C6 279#define REG_BE_ADMTIME 0x05C8 280#define REG_EDCA_RANDOM_GEN 0x05CC 281#define REG_SCH_TXCMD 0x05D0 282 283#define REG_APSD_CTRL 0x0600 284#define REG_BWOPMODE 0x0603 285#define REG_TCR 0x0604 286#define REG_RCR 0x0608 287#define REG_RX_PKT_LIMIT 0x060C 288#define REG_RX_DLK_TIME 0x060D 289#define REG_RX_DRVINFO_SZ 0x060F 290 291#define REG_MACID 0x0610 292#define REG_BSSID 0x0618 293#define REG_MAR 0x0620 294#define REG_MBIDCAMCFG 0x0628 295 296#define REG_USTIME_EDCA 0x0638 297#define REG_MAC_SPEC_SIFS 0x063A 298#define REG_RESP_SIFS_CCK 0x063C 299#define REG_RESP_SIFS_OFDM 0x063E 300#define REG_ACKTO 0x0640 301#define REG_CTS2TO 0x0641 302#define REG_EIFS 0x0642 303 304#define REG_NAV_CTRL 0x0650 305#define REG_BACAMCMD 0x0654 306#define REG_BACAMCONTENT 0x0658 307#define REG_LBDLY 0x0660 308#define REG_FWDLY 0x0661 309#define REG_RXERR_RPT 0x0664 310#define REG_TRXPTCL_CTL 0x0668 311 312#define REG_CAMCMD 0x0670 313#define REG_CAMWRITE 0x0674 314#define REG_CAMREAD 0x0678 315#define REG_CAMDBG 0x067C 316#define REG_SECCFG 0x0680 317 318#define REG_WOW_CTRL 0x0690 319#define REG_PSSTATUS 0x0691 320#define REG_PS_RX_INFO 0x0692 321#define REG_UAPSD_TID 0x0693 322#define REG_LPNAV_CTRL 0x0694 323#define REG_WKFMCAM_NUM 0x0698 324#define REG_WKFMCAM_RWD 0x069C 325#define REG_RXFLTMAP0 0x06A0 326#define REG_RXFLTMAP1 0x06A2 327#define REG_RXFLTMAP2 0x06A4 328#define REG_BCN_PSR_RPT 0x06A8 329#define REG_CALB32K_CTRL 0x06AC 330#define REG_PKT_MON_CTRL 0x06B4 331#define REG_BT_COEX_TABLE 0x06C0 332#define REG_WMAC_RESP_TXINFO 0x06D8 333 334#define REG_USB_INFO 0xFE17 335#define REG_USB_SPECIAL_OPTION 0xFE55 336#define REG_USB_DMA_AGG_TO 0xFE5B 337#define REG_USB_AGG_TO 0xFE5C 338#define REG_USB_AGG_TH 0xFE5D 339 340#define REG_TEST_USB_TXQS 0xFE48 341#define REG_TEST_SIE_VID 0xFE60 342#define REG_TEST_SIE_PID 0xFE62 343#define REG_TEST_SIE_OPTIONAL 0xFE64 344#define REG_TEST_SIE_CHIRP_K 0xFE65 345#define REG_TEST_SIE_PHY 0xFE66 346#define REG_TEST_SIE_MAC_ADDR 0xFE70 347#define REG_TEST_SIE_STRING 0xFE80 348 349#define REG_NORMAL_SIE_VID 0xFE60 350#define REG_NORMAL_SIE_PID 0xFE62 351#define REG_NORMAL_SIE_OPTIONAL 0xFE64 352#define REG_NORMAL_SIE_EP 0xFE65 353#define REG_NORMAL_SIE_PHY 0xFE68 354#define REG_NORMAL_SIE_MAC_ADDR 0xFE70 355#define REG_NORMAL_SIE_STRING 0xFE80 356 357#define CR9346 REG_9346CR 358#define MSR (REG_CR + 2) 359#define ISR REG_HISR 360#define TSFR REG_TSFTR 361 362#define MACIDR0 REG_MACID 363#define MACIDR4 (REG_MACID + 4) 364 365#define PBP REG_PBP 366 367#define IDR0 MACIDR0 368#define IDR4 MACIDR4 369 370#define UNUSED_REGISTER 0x1BF 371#define DCAM UNUSED_REGISTER 372#define PSR UNUSED_REGISTER 373#define BBADDR UNUSED_REGISTER 374#define PHYDATAR UNUSED_REGISTER 375 376#define INVALID_BBRF_VALUE 0x12345678 377 378#define MAX_MSS_DENSITY_2T 0x13 379#define MAX_MSS_DENSITY_1T 0x0A 380 381#define CMDEEPROM_EN BIT(5) 382#define CMDEEPROM_SEL BIT(4) 383#define CMD9346CR_9356SEL BIT(4) 384#define AUTOLOAD_EEPROM (CMDEEPROM_EN|CMDEEPROM_SEL) 385#define AUTOLOAD_EFUSE CMDEEPROM_EN 386 387#define GPIOSEL_GPIO 0 388#define GPIOSEL_ENBT BIT(5) 389 390#define GPIO_IN REG_GPIO_PIN_CTRL 391#define GPIO_OUT (REG_GPIO_PIN_CTRL+1) 392#define GPIO_IO_SEL (REG_GPIO_PIN_CTRL+2) 393#define GPIO_MOD (REG_GPIO_PIN_CTRL+3) 394 395/* 8723/8188E Host System Interrupt Mask Register (offset 0x58, 32 byte) */ 396#define HSIMR_GPIO12_0_INT_EN BIT(0) 397#define HSIMR_SPS_OCP_INT_EN BIT(5) 398#define HSIMR_RON_INT_EN BIT(6) 399#define HSIMR_PDN_INT_EN BIT(7) 400#define HSIMR_GPIO9_INT_EN BIT(25) 401 402 403/* 8723/8188E Host System Interrupt Status Register (offset 0x5C, 32 byte) */ 404#define HSISR_GPIO12_0_INT BIT(0) 405#define HSISR_SPS_OCP_INT BIT(5) 406#define HSISR_RON_INT_EN BIT(6) 407#define HSISR_PDNINT BIT(7) 408#define HSISR_GPIO9_INT BIT(25) 409 410#define MSR_NOLINK 0x00 411#define MSR_ADHOC 0x01 412#define MSR_INFRA 0x02 413#define MSR_AP 0x03 414 415#define RRSR_RSC_OFFSET 21 416#define RRSR_SHORT_OFFSET 23 417#define RRSR_RSC_BW_40M 0x600000 418#define RRSR_RSC_UPSUBCHNL 0x400000 419#define RRSR_RSC_LOWSUBCHNL 0x200000 420#define RRSR_SHORT 0x800000 421#define RRSR_1M BIT(0) 422#define RRSR_2M BIT(1) 423#define RRSR_5_5M BIT(2) 424#define RRSR_11M BIT(3) 425#define RRSR_6M BIT(4) 426#define RRSR_9M BIT(5) 427#define RRSR_12M BIT(6) 428#define RRSR_18M BIT(7) 429#define RRSR_24M BIT(8) 430#define RRSR_36M BIT(9) 431#define RRSR_48M BIT(10) 432#define RRSR_54M BIT(11) 433#define RRSR_MCS0 BIT(12) 434#define RRSR_MCS1 BIT(13) 435#define RRSR_MCS2 BIT(14) 436#define RRSR_MCS3 BIT(15) 437#define RRSR_MCS4 BIT(16) 438#define RRSR_MCS5 BIT(17) 439#define RRSR_MCS6 BIT(18) 440#define RRSR_MCS7 BIT(19) 441#define BRSR_ACKSHORTPMB BIT(23) 442 443#define RATR_1M 0x00000001 444#define RATR_2M 0x00000002 445#define RATR_55M 0x00000004 446#define RATR_11M 0x00000008 447#define RATR_6M 0x00000010 448#define RATR_9M 0x00000020 449#define RATR_12M 0x00000040 450#define RATR_18M 0x00000080 451#define RATR_24M 0x00000100 452#define RATR_36M 0x00000200 453#define RATR_48M 0x00000400 454#define RATR_54M 0x00000800 455#define RATR_MCS0 0x00001000 456#define RATR_MCS1 0x00002000 457#define RATR_MCS2 0x00004000 458#define RATR_MCS3 0x00008000 459#define RATR_MCS4 0x00010000 460#define RATR_MCS5 0x00020000 461#define RATR_MCS6 0x00040000 462#define RATR_MCS7 0x00080000 463#define RATR_MCS8 0x00100000 464#define RATR_MCS9 0x00200000 465#define RATR_MCS10 0x00400000 466#define RATR_MCS11 0x00800000 467#define RATR_MCS12 0x01000000 468#define RATR_MCS13 0x02000000 469#define RATR_MCS14 0x04000000 470#define RATR_MCS15 0x08000000 471 472#define RATE_1M BIT(0) 473#define RATE_2M BIT(1) 474#define RATE_5_5M BIT(2) 475#define RATE_11M BIT(3) 476#define RATE_6M BIT(4) 477#define RATE_9M BIT(5) 478#define RATE_12M BIT(6) 479#define RATE_18M BIT(7) 480#define RATE_24M BIT(8) 481#define RATE_36M BIT(9) 482#define RATE_48M BIT(10) 483#define RATE_54M BIT(11) 484#define RATE_MCS0 BIT(12) 485#define RATE_MCS1 BIT(13) 486#define RATE_MCS2 BIT(14) 487#define RATE_MCS3 BIT(15) 488#define RATE_MCS4 BIT(16) 489#define RATE_MCS5 BIT(17) 490#define RATE_MCS6 BIT(18) 491#define RATE_MCS7 BIT(19) 492#define RATE_MCS8 BIT(20) 493#define RATE_MCS9 BIT(21) 494#define RATE_MCS10 BIT(22) 495#define RATE_MCS11 BIT(23) 496#define RATE_MCS12 BIT(24) 497#define RATE_MCS13 BIT(25) 498#define RATE_MCS14 BIT(26) 499#define RATE_MCS15 BIT(27) 500 501#define RATE_ALL_CCK (RATR_1M | RATR_2M | RATR_55M | RATR_11M) 502#define RATE_ALL_OFDM_AG (RATR_6M | RATR_9M | RATR_12M | RATR_18M | \ 503 RATR_24M | RATR_36M | RATR_48M | RATR_54M) 504#define RATE_ALL_OFDM_1SS (RATR_MCS0 | RATR_MCS1 | RATR_MCS2 | \ 505 RATR_MCS3 | RATR_MCS4 | RATR_MCS5 | \ 506 RATR_MCS6 | RATR_MCS7) 507#define RATE_ALL_OFDM_2SS (RATR_MCS8 | RATR_MCS9 | RATR_MCS10 | \ 508 RATR_MCS11 | RATR_MCS12 | RATR_MCS13 | \ 509 RATR_MCS14 | RATR_MCS15) 510 511#define BW_OPMODE_20MHZ BIT(2) 512#define BW_OPMODE_5G BIT(1) 513#define BW_OPMODE_11J BIT(0) 514 515#define CAM_VALID BIT(15) 516#define CAM_NOTVALID 0x0000 517#define CAM_USEDK BIT(5) 518 519#define CAM_NONE 0x0 520#define CAM_WEP40 0x01 521#define CAM_TKIP 0x02 522#define CAM_AES 0x04 523#define CAM_WEP104 0x05 524 525#define TOTAL_CAM_ENTRY 32 526#define HALF_CAM_ENTRY 16 527 528#define CAM_WRITE BIT(16) 529#define CAM_READ 0x00000000 530#define CAM_POLLINIG BIT(31) 531 532#define SCR_USEDK 0x01 533#define SCR_TXSEC_ENABLE 0x02 534#define SCR_RXSEC_ENABLE 0x04 535 536#define WOW_PMEN BIT(0) 537#define WOW_WOMEN BIT(1) 538#define WOW_MAGIC BIT(2) 539#define WOW_UWF BIT(3) 540 541/********************************************* 542* 8188 IMR/ISR bits 543**********************************************/ 544#define IMR_DISABLED 0x0 545/* IMR DW0(0x0060-0063) Bit 0-31 */ 546#define IMR_TXCCK BIT(30) /* TXRPT interrupt when CCX bit of 547 * the packet is set 548 */ 549#define IMR_PSTIMEOUT BIT(29) /* Power Save Time Out Interrupt */ 550#define IMR_GTINT4 BIT(28) /* When GTIMER4 expires, 551 * this bit is set to 1 552 */ 553#define IMR_GTINT3 BIT(27) /* When GTIMER3 expires, 554 * this bit is set to 1 555 */ 556#define IMR_TBDER BIT(26) /* Transmit Beacon0 Error */ 557#define IMR_TBDOK BIT(25) /* Transmit Beacon0 OK */ 558#define IMR_TSF_BIT32_TOGGLE BIT(24) /* TSF Timer BIT32 toggle ind int */ 559#define IMR_BCNDMAINT0 BIT(20) /* Beacon DMA Interrupt 0 */ 560#define IMR_BCNDOK0 BIT(16) /* Beacon Queue DMA OK0 */ 561#define IMR_HSISR_IND_ON_INT BIT(15) /* HSISR Indicator (HSIMR & HSISR is 562 * true, this bit is set to 1) 563 */ 564#define IMR_BCNDMAINT_E BIT(14) /* Beacon DMA Int Extension for Win7 */ 565#define IMR_ATIMEND BIT(12) /* CTWidnow End or ATIM Window End */ 566#define IMR_HISR1_IND_INT BIT(11) /* HISR1 Indicator (HISR1 & HIMR1 is 567 * true, this bit is set to 1) 568 */ 569#define IMR_C2HCMD BIT(10) /* CPU to Host Command INT Status, 570 * Write 1 clear 571 */ 572#define IMR_CPWM2 BIT(9) /* CPU power Mode exchange INT Status, 573 * Write 1 clear 574 */ 575#define IMR_CPWM BIT(8) /* CPU power Mode exchange INT Status, 576 * Write 1 clear 577 */ 578#define IMR_HIGHDOK BIT(7) /* High Queue DMA OK */ 579#define IMR_MGNTDOK BIT(6) /* Management Queue DMA OK */ 580#define IMR_BKDOK BIT(5) /* AC_BK DMA OK */ 581#define IMR_BEDOK BIT(4) /* AC_BE DMA OK */ 582#define IMR_VIDOK BIT(3) /* AC_VI DMA OK */ 583#define IMR_VODOK BIT(2) /* AC_VO DMA OK */ 584#define IMR_RDU BIT(1) /* Rx Descriptor Unavailable */ 585#define IMR_ROK BIT(0) /* Receive DMA OK */ 586 587/* IMR DW1(0x00B4-00B7) Bit 0-31 */ 588#define IMR_BCNDMAINT7 BIT(27) /* Beacon DMA Interrupt 7 */ 589#define IMR_BCNDMAINT6 BIT(26) /* Beacon DMA Interrupt 6 */ 590#define IMR_BCNDMAINT5 BIT(25) /* Beacon DMA Interrupt 5 */ 591#define IMR_BCNDMAINT4 BIT(24) /* Beacon DMA Interrupt 4 */ 592#define IMR_BCNDMAINT3 BIT(23) /* Beacon DMA Interrupt 3 */ 593#define IMR_BCNDMAINT2 BIT(22) /* Beacon DMA Interrupt 2 */ 594#define IMR_BCNDMAINT1 BIT(21) /* Beacon DMA Interrupt 1 */ 595#define IMR_BCNDOK7 BIT(20) /* Beacon Queue DMA OK Interrup 7 */ 596#define IMR_BCNDOK6 BIT(19) /* Beacon Queue DMA OK Interrup 6 */ 597#define IMR_BCNDOK5 BIT(18) /* Beacon Queue DMA OK Interrup 5 */ 598#define IMR_BCNDOK4 BIT(17) /* Beacon Queue DMA OK Interrup 4 */ 599#define IMR_BCNDOK3 BIT(16) /* Beacon Queue DMA OK Interrup 3 */ 600#define IMR_BCNDOK2 BIT(15) /* Beacon Queue DMA OK Interrup 2 */ 601#define IMR_BCNDOK1 BIT(14) /* Beacon Queue DMA OK Interrup 1 */ 602#define IMR_ATIMEND_E BIT(13) /* ATIM Window End Extension for Win7 */ 603#define IMR_TXERR BIT(11) /* Tx Err Flag Int Status, 604 * write 1 clear. 605 */ 606#define IMR_RXERR BIT(10) /* Rx Err Flag INT Status, 607 * Write 1 clear 608 */ 609#define IMR_TXFOVW BIT(9) /* Transmit FIFO Overflow */ 610#define IMR_RXFOVW BIT(8) /* Receive FIFO Overflow */ 611 612 613#define HWSET_MAX_SIZE 512 614#define EFUSE_MAX_SECTION 64 615#define EFUSE_REAL_CONTENT_LEN 256 616#define EFUSE_OOB_PROTECT_BYTES 18 /* PG data exclude header, 617 * dummy 7 bytes frome CP 618 * test and reserved 1byte. 619 */ 620 621#define EEPROM_DEFAULT_TSSI 0x0 622#define EEPROM_DEFAULT_TXPOWERDIFF 0x0 623#define EEPROM_DEFAULT_CRYSTALCAP 0x5 624#define EEPROM_DEFAULT_BOARDTYPE 0x02 625#define EEPROM_DEFAULT_TXPOWER 0x1010 626#define EEPROM_DEFAULT_HT2T_TXPWR 0x10 627 628#define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x3 629#define EEPROM_DEFAULT_THERMALMETER 0x18 630#define EEPROM_DEFAULT_ANTTXPOWERDIFF 0x0 631#define EEPROM_DEFAULT_TXPWDIFF_CRYSTALCAP 0x5 632#define EEPROM_DEFAULT_TXPOWERLEVEL 0x22 633#define EEPROM_DEFAULT_HT40_2SDIFF 0x0 634#define EEPROM_DEFAULT_HT20_DIFF 2 635#define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x3 636#define EEPROM_DEFAULT_HT40_PWRMAXOFFSET 0 637#define EEPROM_DEFAULT_HT20_PWRMAXOFFSET 0 638 639#define RF_OPTION1 0x79 640#define RF_OPTION2 0x7A 641#define RF_OPTION3 0x7B 642#define RF_OPTION4 0x7C 643 644#define EEPROM_DEFAULT_PID 0x1234 645#define EEPROM_DEFAULT_VID 0x5678 646#define EEPROM_DEFAULT_CUSTOMERID 0xAB 647#define EEPROM_DEFAULT_SUBCUSTOMERID 0xCD 648#define EEPROM_DEFAULT_VERSION 0 649 650#define EEPROM_CHANNEL_PLAN_FCC 0x0 651#define EEPROM_CHANNEL_PLAN_IC 0x1 652#define EEPROM_CHANNEL_PLAN_ETSI 0x2 653#define EEPROM_CHANNEL_PLAN_SPAIN 0x3 654#define EEPROM_CHANNEL_PLAN_FRANCE 0x4 655#define EEPROM_CHANNEL_PLAN_MKK 0x5 656#define EEPROM_CHANNEL_PLAN_MKK1 0x6 657#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7 658#define EEPROM_CHANNEL_PLAN_TELEC 0x8 659#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9 660#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA 661#define EEPROM_CHANNEL_PLAN_NCC 0xB 662#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80 663 664#define EEPROM_CID_DEFAULT 0x0 665#define EEPROM_CID_TOSHIBA 0x4 666#define EEPROM_CID_CCX 0x10 667#define EEPROM_CID_QMI 0x0D 668#define EEPROM_CID_WHQL 0xFE 669 670#define RTL8188E_EEPROM_ID 0x8129 671 672#define EEPROM_HPON 0x02 673#define EEPROM_CLK 0x06 674#define EEPROM_TESTR 0x08 675 676#define EEPROM_TXPOWERCCK 0x10 677#define EEPROM_TXPOWERHT40_1S 0x16 678#define EEPROM_TXPOWERHT20DIFF 0x1B 679#define EEPROM_TXPOWER_OFDMDIFF 0x1B 680 681#define EEPROM_TX_PWR_INX 0x10 682 683#define EEPROM_CHANNELPLAN 0xB8 684#define EEPROM_XTAL_88E 0xB9 685#define EEPROM_THERMAL_METER_88E 0xBA 686#define EEPROM_IQK_LCK_88E 0xBB 687 688#define EEPROM_RF_BOARD_OPTION_88E 0xC1 689#define EEPROM_RF_FEATURE_OPTION_88E 0xC2 690#define EEPROM_RF_BT_SETTING_88E 0xC3 691#define EEPROM_VERSION 0xC4 692#define EEPROM_CUSTOMER_ID 0xC5 693#define EEPROM_RF_ANTENNA_OPT_88E 0xC9 694 695#define EEPROM_MAC_ADDR 0xD0 696#define EEPROM_VID 0xD6 697#define EEPROM_DID 0xD8 698#define EEPROM_SVID 0xDA 699#define EEPROM_SMID 0xDC 700 701#define STOPBECON BIT(6) 702#define STOPHIGHT BIT(5) 703#define STOPMGT BIT(4) 704#define STOPVO BIT(3) 705#define STOPVI BIT(2) 706#define STOPBE BIT(1) 707#define STOPBK BIT(0) 708 709#define RCR_APPFCS BIT(31) 710#define RCR_APP_MIC BIT(30) 711#define RCR_APP_ICV BIT(29) 712#define RCR_APP_PHYST_RXFF BIT(28) 713#define RCR_APP_BA_SSN BIT(27) 714#define RCR_ENMBID BIT(24) 715#define RCR_LSIGEN BIT(23) 716#define RCR_MFBEN BIT(22) 717#define RCR_HTC_LOC_CTRL BIT(14) 718#define RCR_AMF BIT(13) 719#define RCR_ACF BIT(12) 720#define RCR_ADF BIT(11) 721#define RCR_AICV BIT(9) 722#define RCR_ACRC32 BIT(8) 723#define RCR_CBSSID_BCN BIT(7) 724#define RCR_CBSSID_DATA BIT(6) 725#define RCR_CBSSID RCR_CBSSID_DATA 726#define RCR_APWRMGT BIT(5) 727#define RCR_ADD3 BIT(4) 728#define RCR_AB BIT(3) 729#define RCR_AM BIT(2) 730#define RCR_APM BIT(1) 731#define RCR_AAP BIT(0) 732#define RCR_MXDMA_OFFSET 8 733#define RCR_FIFO_OFFSET 13 734 735#define RSV_CTRL 0x001C 736#define RD_CTRL 0x0524 737 738#define REG_USB_INFO 0xFE17 739#define REG_USB_SPECIAL_OPTION 0xFE55 740#define REG_USB_DMA_AGG_TO 0xFE5B 741#define REG_USB_AGG_TO 0xFE5C 742#define REG_USB_AGG_TH 0xFE5D 743 744#define REG_USB_VID 0xFE60 745#define REG_USB_PID 0xFE62 746#define REG_USB_OPTIONAL 0xFE64 747#define REG_USB_CHIRP_K 0xFE65 748#define REG_USB_PHY 0xFE66 749#define REG_USB_MAC_ADDR 0xFE70 750#define REG_USB_HRPWM 0xFE58 751#define REG_USB_HCPWM 0xFE57 752 753#define SW18_FPWM BIT(3) 754 755#define ISO_MD2PP BIT(0) 756#define ISO_UA2USB BIT(1) 757#define ISO_UD2CORE BIT(2) 758#define ISO_PA2PCIE BIT(3) 759#define ISO_PD2CORE BIT(4) 760#define ISO_IP2MAC BIT(5) 761#define ISO_DIOP BIT(6) 762#define ISO_DIOE BIT(7) 763#define ISO_EB2CORE BIT(8) 764#define ISO_DIOR BIT(9) 765 766#define PWC_EV25V BIT(14) 767#define PWC_EV12V BIT(15) 768 769#define FEN_BBRSTB BIT(0) 770#define FEN_BB_GLB_RSTN BIT(1) 771#define FEN_USBA BIT(2) 772#define FEN_UPLL BIT(3) 773#define FEN_USBD BIT(4) 774#define FEN_DIO_PCIE BIT(5) 775#define FEN_PCIEA BIT(6) 776#define FEN_PPLL BIT(7) 777#define FEN_PCIED BIT(8) 778#define FEN_DIOE BIT(9) 779#define FEN_CPUEN BIT(10) 780#define FEN_DCORE BIT(11) 781#define FEN_ELDR BIT(12) 782#define FEN_DIO_RF BIT(13) 783#define FEN_HWPDN BIT(14) 784#define FEN_MREGEN BIT(15) 785 786#define PFM_LDALL BIT(0) 787#define PFM_ALDN BIT(1) 788#define PFM_LDKP BIT(2) 789#define PFM_WOWL BIT(3) 790#define ENPDN BIT(4) 791#define PDN_PL BIT(5) 792#define APFM_ONMAC BIT(8) 793#define APFM_OFF BIT(9) 794#define APFM_RSM BIT(10) 795#define AFSM_HSUS BIT(11) 796#define AFSM_PCIE BIT(12) 797#define APDM_MAC BIT(13) 798#define APDM_HOST BIT(14) 799#define APDM_HPDN BIT(15) 800#define RDY_MACON BIT(16) 801#define SUS_HOST BIT(17) 802#define ROP_ALD BIT(20) 803#define ROP_PWR BIT(21) 804#define ROP_SPS BIT(22) 805#define SOP_MRST BIT(25) 806#define SOP_FUSE BIT(26) 807#define SOP_ABG BIT(27) 808#define SOP_AMB BIT(28) 809#define SOP_RCK BIT(29) 810#define SOP_A8M BIT(30) 811#define XOP_BTCK BIT(31) 812 813#define ANAD16V_EN BIT(0) 814#define ANA8M BIT(1) 815#define MACSLP BIT(4) 816#define LOADER_CLK_EN BIT(5) 817#define _80M_SSC_DIS BIT(7) 818#define _80M_SSC_EN_HO BIT(8) 819#define PHY_SSC_RSTB BIT(9) 820#define SEC_CLK_EN BIT(10) 821#define MAC_CLK_EN BIT(11) 822#define SYS_CLK_EN BIT(12) 823#define RING_CLK_EN BIT(13) 824 825#define BOOT_FROM_EEPROM BIT(4) 826#define EEPROM_EN BIT(5) 827 828#define AFE_BGEN BIT(0) 829#define AFE_MBEN BIT(1) 830#define MAC_ID_EN BIT(7) 831 832#define WLOCK_ALL BIT(0) 833#define WLOCK_00 BIT(1) 834#define WLOCK_04 BIT(2) 835#define WLOCK_08 BIT(3) 836#define WLOCK_40 BIT(4) 837#define R_DIS_PRST_0 BIT(5) 838#define R_DIS_PRST_1 BIT(6) 839#define LOCK_ALL_EN BIT(7) 840 841#define RF_EN BIT(0) 842#define RF_RSTB BIT(1) 843#define RF_SDMRSTB BIT(2) 844 845#define LDA15_EN BIT(0) 846#define LDA15_STBY BIT(1) 847#define LDA15_OBUF BIT(2) 848#define LDA15_REG_VOS BIT(3) 849#define _LDA15_VOADJ(x) (((x) & 0x7) << 4) 850 851#define LDV12_EN BIT(0) 852#define LDV12_SDBY BIT(1) 853#define LPLDO_HSM BIT(2) 854#define LPLDO_LSM_DIS BIT(3) 855#define _LDV12_VADJ(x) (((x) & 0xF) << 4) 856 857#define XTAL_EN BIT(0) 858#define XTAL_BSEL BIT(1) 859#define _XTAL_BOSC(x) (((x) & 0x3) << 2) 860#define _XTAL_CADJ(x) (((x) & 0xF) << 4) 861#define XTAL_GATE_USB BIT(8) 862#define _XTAL_USB_DRV(x) (((x) & 0x3) << 9) 863#define XTAL_GATE_AFE BIT(11) 864#define _XTAL_AFE_DRV(x) (((x) & 0x3) << 12) 865#define XTAL_RF_GATE BIT(14) 866#define _XTAL_RF_DRV(x) (((x) & 0x3) << 15) 867#define XTAL_GATE_DIG BIT(17) 868#define _XTAL_DIG_DRV(x) (((x) & 0x3) << 18) 869#define XTAL_BT_GATE BIT(20) 870#define _XTAL_BT_DRV(x) (((x) & 0x3) << 21) 871#define _XTAL_GPIO(x) (((x) & 0x7) << 23) 872 873#define CKDLY_AFE BIT(26) 874#define CKDLY_USB BIT(27) 875#define CKDLY_DIG BIT(28) 876#define CKDLY_BT BIT(29) 877 878#define APLL_EN BIT(0) 879#define APLL_320_EN BIT(1) 880#define APLL_FREF_SEL BIT(2) 881#define APLL_EDGE_SEL BIT(3) 882#define APLL_WDOGB BIT(4) 883#define APLL_LPFEN BIT(5) 884 885#define APLL_REF_CLK_13MHZ 0x1 886#define APLL_REF_CLK_19_2MHZ 0x2 887#define APLL_REF_CLK_20MHZ 0x3 888#define APLL_REF_CLK_25MHZ 0x4 889#define APLL_REF_CLK_26MHZ 0x5 890#define APLL_REF_CLK_38_4MHZ 0x6 891#define APLL_REF_CLK_40MHZ 0x7 892 893#define APLL_320EN BIT(14) 894#define APLL_80EN BIT(15) 895#define APLL_1MEN BIT(24) 896 897#define ALD_EN BIT(18) 898#define EF_PD BIT(19) 899#define EF_FLAG BIT(31) 900 901#define EF_TRPT BIT(7) 902#define LDOE25_EN BIT(31) 903 904#define RSM_EN BIT(0) 905#define TIMER_EN BIT(4) 906 907#define TRSW0EN BIT(2) 908#define TRSW1EN BIT(3) 909#define EROM_EN BIT(4) 910#define ENBT BIT(5) 911#define ENUART BIT(8) 912#define UART_910 BIT(9) 913#define ENPMAC BIT(10) 914#define SIC_SWRST BIT(11) 915#define ENSIC BIT(12) 916#define SIC_23 BIT(13) 917#define ENHDP BIT(14) 918#define SIC_LBK BIT(15) 919 920#define LED0PL BIT(4) 921#define LED1PL BIT(12) 922#define LED0DIS BIT(7) 923 924#define MCUFWDL_EN BIT(0) 925#define MCUFWDL_RDY BIT(1) 926#define FWDL_CHKSUM_RPT BIT(2) 927#define MACINI_RDY BIT(3) 928#define BBINI_RDY BIT(4) 929#define RFINI_RDY BIT(5) 930#define WINTINI_RDY BIT(6) 931#define CPRST BIT(23) 932 933#define XCLK_VLD BIT(0) 934#define ACLK_VLD BIT(1) 935#define UCLK_VLD BIT(2) 936#define PCLK_VLD BIT(3) 937#define PCIRSTB BIT(4) 938#define V15_VLD BIT(5) 939#define TRP_B15V_EN BIT(7) 940#define SIC_IDLE BIT(8) 941#define BD_MAC2 BIT(9) 942#define BD_MAC1 BIT(10) 943#define IC_MACPHY_MODE BIT(11) 944#define VENDOR_ID BIT(19) 945#define PAD_HWPD_IDN BIT(22) 946#define TRP_VAUX_EN BIT(23) 947#define TRP_BT_EN BIT(24) 948#define BD_PKG_SEL BIT(25) 949#define BD_HCI_SEL BIT(26) 950#define TYPE_ID BIT(27) 951 952#define CHIP_VER_RTL_MASK 0xF000 953#define CHIP_VER_RTL_SHIFT 12 954 955#define REG_LBMODE (REG_CR + 3) 956 957#define HCI_TXDMA_EN BIT(0) 958#define HCI_RXDMA_EN BIT(1) 959#define TXDMA_EN BIT(2) 960#define RXDMA_EN BIT(3) 961#define PROTOCOL_EN BIT(4) 962#define SCHEDULE_EN BIT(5) 963#define MACTXEN BIT(6) 964#define MACRXEN BIT(7) 965#define ENSWBCN BIT(8) 966#define ENSEC BIT(9) 967 968#define _NETTYPE(x) (((x) & 0x3) << 16) 969#define MASK_NETTYPE 0x30000 970#define NT_NO_LINK 0x0 971#define NT_LINK_AD_HOC 0x1 972#define NT_LINK_AP 0x2 973#define NT_AS_AP 0x3 974 975#define _LBMODE(x) (((x) & 0xF) << 24) 976#define MASK_LBMODE 0xF000000 977#define LOOPBACK_NORMAL 0x0 978#define LOOPBACK_IMMEDIATELY 0xB 979#define LOOPBACK_MAC_DELAY 0x3 980#define LOOPBACK_PHY 0x1 981#define LOOPBACK_DMA 0x7 982 983#define GET_RX_PAGE_SIZE(value) ((value) & 0xF) 984#define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4) 985#define _PSRX_MASK 0xF 986#define _PSTX_MASK 0xF0 987#define _PSRX(x) (x) 988#define _PSTX(x) ((x) << 4) 989 990#define PBP_64 0x0 991#define PBP_128 0x1 992#define PBP_256 0x2 993#define PBP_512 0x3 994#define PBP_1024 0x4 995 996#define RXDMA_ARBBW_EN BIT(0) 997#define RXSHFT_EN BIT(1) 998#define RXDMA_AGG_EN BIT(2) 999#define QS_VO_QUEUE BIT(8) 1000#define QS_VI_QUEUE BIT(9) 1001#define QS_BE_QUEUE BIT(10) 1002#define QS_BK_QUEUE BIT(11) 1003#define QS_MANAGER_QUEUE BIT(12) 1004#define QS_HIGH_QUEUE BIT(13) 1005 1006#define HQSEL_VOQ BIT(0) 1007#define HQSEL_VIQ BIT(1) 1008#define HQSEL_BEQ BIT(2) 1009#define HQSEL_BKQ BIT(3) 1010#define HQSEL_MGTQ BIT(4) 1011#define HQSEL_HIQ BIT(5) 1012 1013#define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14) 1014#define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12) 1015#define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10) 1016#define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8) 1017#define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6) 1018#define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4) 1019 1020#define QUEUE_LOW 1 1021#define QUEUE_NORMAL 2 1022#define QUEUE_HIGH 3 1023 1024#define _LLT_NO_ACTIVE 0x0 1025#define _LLT_WRITE_ACCESS 0x1 1026#define _LLT_READ_ACCESS 0x2 1027 1028#define _LLT_INIT_DATA(x) ((x) & 0xFF) 1029#define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8) 1030#define _LLT_OP(x) (((x) & 0x3) << 30) 1031#define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3) 1032 1033#define BB_WRITE_READ_MASK (BIT(31) | BIT(30)) 1034#define BB_WRITE_EN BIT(30) 1035#define BB_READ_EN BIT(31) 1036 1037#define _HPQ(x) ((x) & 0xFF) 1038#define _LPQ(x) (((x) & 0xFF) << 8) 1039#define _PUBQ(x) (((x) & 0xFF) << 16) 1040#define _NPQ(x) ((x) & 0xFF) 1041 1042#define HPQ_PUBLIC_DIS BIT(24) 1043#define LPQ_PUBLIC_DIS BIT(25) 1044#define LD_RQPN BIT(31) 1045 1046#define BCN_VALID BIT(16) 1047#define BCN_HEAD(x) (((x) & 0xFF) << 8) 1048#define BCN_HEAD_MASK 0xFF00 1049 1050#define BLK_DESC_NUM_SHIFT 4 1051#define BLK_DESC_NUM_MASK 0xF 1052 1053#define DROP_DATA_EN BIT(9) 1054 1055#define EN_AMPDU_RTY_NEW BIT(7) 1056 1057#define _INIRTSMCS_SEL(x) ((x) & 0x3F) 1058 1059#define _SPEC_SIFS_CCK(x) ((x) & 0xFF) 1060#define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8) 1061 1062#define RATE_REG_BITMAP_ALL 0xFFFFF 1063 1064#define _RRSC_BITMAP(x) ((x) & 0xFFFFF) 1065 1066#define _RRSR_RSC(x) (((x) & 0x3) << 21) 1067#define RRSR_RSC_RESERVED 0x0 1068#define RRSR_RSC_UPPER_SUBCHANNEL 0x1 1069#define RRSR_RSC_LOWER_SUBCHANNEL 0x2 1070#define RRSR_RSC_DUPLICATE_MODE 0x3 1071 1072#define USE_SHORT_G1 BIT(20) 1073 1074#define _AGGLMT_MCS0(x) ((x) & 0xF) 1075#define _AGGLMT_MCS1(x) (((x) & 0xF) << 4) 1076#define _AGGLMT_MCS2(x) (((x) & 0xF) << 8) 1077#define _AGGLMT_MCS3(x) (((x) & 0xF) << 12) 1078#define _AGGLMT_MCS4(x) (((x) & 0xF) << 16) 1079#define _AGGLMT_MCS5(x) (((x) & 0xF) << 20) 1080#define _AGGLMT_MCS6(x) (((x) & 0xF) << 24) 1081#define _AGGLMT_MCS7(x) (((x) & 0xF) << 28) 1082 1083#define RETRY_LIMIT_SHORT_SHIFT 8 1084#define RETRY_LIMIT_LONG_SHIFT 0 1085 1086#define _DARF_RC1(x) ((x) & 0x1F) 1087#define _DARF_RC2(x) (((x) & 0x1F) << 8) 1088#define _DARF_RC3(x) (((x) & 0x1F) << 16) 1089#define _DARF_RC4(x) (((x) & 0x1F) << 24) 1090#define _DARF_RC5(x) ((x) & 0x1F) 1091#define _DARF_RC6(x) (((x) & 0x1F) << 8) 1092#define _DARF_RC7(x) (((x) & 0x1F) << 16) 1093#define _DARF_RC8(x) (((x) & 0x1F) << 24) 1094 1095#define _RARF_RC1(x) ((x) & 0x1F) 1096#define _RARF_RC2(x) (((x) & 0x1F) << 8) 1097#define _RARF_RC3(x) (((x) & 0x1F) << 16) 1098#define _RARF_RC4(x) (((x) & 0x1F) << 24) 1099#define _RARF_RC5(x) ((x) & 0x1F) 1100#define _RARF_RC6(x) (((x) & 0x1F) << 8) 1101#define _RARF_RC7(x) (((x) & 0x1F) << 16) 1102#define _RARF_RC8(x) (((x) & 0x1F) << 24) 1103 1104#define AC_PARAM_TXOP_LIMIT_OFFSET 16 1105#define AC_PARAM_ECW_MAX_OFFSET 12 1106#define AC_PARAM_ECW_MIN_OFFSET 8 1107#define AC_PARAM_AIFS_OFFSET 0 1108 1109#define _AIFS(x) (x) 1110#define _ECW_MAX_MIN(x) ((x) << 8) 1111#define _TXOP_LIMIT(x) ((x) << 16) 1112 1113#define _BCNIFS(x) ((x) & 0xFF) 1114#define _BCNECW(x) ((((x) & 0xF)) << 8) 1115 1116#define _LRL(x) ((x) & 0x3F) 1117#define _SRL(x) (((x) & 0x3F) << 8) 1118 1119#define _SIFS_CCK_CTX(x) ((x) & 0xFF) 1120#define _SIFS_CCK_TRX(x) (((x) & 0xFF) << 8); 1121 1122#define _SIFS_OFDM_CTX(x) ((x) & 0xFF) 1123#define _SIFS_OFDM_TRX(x) (((x) & 0xFF) << 8); 1124 1125#define _TBTT_PROHIBIT_HOLD(x) (((x) & 0xFF) << 8) 1126 1127#define DIS_EDCA_CNT_DWN BIT(11) 1128 1129#define EN_MBSSID BIT(1) 1130#define EN_TXBCN_RPT BIT(2) 1131#define EN_BCN_FUNCTION BIT(3) 1132 1133#define TSFTR_RST BIT(0) 1134#define TSFTR1_RST BIT(1) 1135 1136#define STOP_BCNQ BIT(6) 1137 1138#define DIS_TSF_UDT0_NORMAL_CHIP BIT(4) 1139#define DIS_TSF_UDT0_TEST_CHIP BIT(5) 1140 1141#define ACMHW_HWEN BIT(0) 1142#define ACMHW_BEQEN BIT(1) 1143#define ACMHW_VIQEN BIT(2) 1144#define ACMHW_VOQEN BIT(3) 1145#define ACMHW_BEQSTATUS BIT(4) 1146#define ACMHW_VIQSTATUS BIT(5) 1147#define ACMHW_VOQSTATUS BIT(6) 1148 1149#define APSDOFF BIT(6) 1150#define APSDOFF_STATUS BIT(7) 1151 1152#define BW_20MHZ BIT(2) 1153 1154#define RATE_BITMAP_ALL 0xFFFFF 1155 1156#define RATE_RRSR_CCK_ONLY_1M 0xFFFF1 1157 1158#define TSFRST BIT(0) 1159#define DIS_GCLK BIT(1) 1160#define PAD_SEL BIT(2) 1161#define PWR_ST BIT(6) 1162#define PWRBIT_OW_EN BIT(7) 1163#define ACRC BIT(8) 1164#define CFENDFORM BIT(9) 1165#define ICV BIT(10) 1166 1167#define AAP BIT(0) 1168#define APM BIT(1) 1169#define AM BIT(2) 1170#define AB BIT(3) 1171#define ADD3 BIT(4) 1172#define APWRMGT BIT(5) 1173#define CBSSID BIT(6) 1174#define CBSSID_DATA BIT(6) 1175#define CBSSID_BCN BIT(7) 1176#define ACRC32 BIT(8) 1177#define AICV BIT(9) 1178#define ADF BIT(11) 1179#define ACF BIT(12) 1180#define AMF BIT(13) 1181#define HTC_LOC_CTRL BIT(14) 1182#define UC_DATA_EN BIT(16) 1183#define BM_DATA_EN BIT(17) 1184#define MFBEN BIT(22) 1185#define LSIGEN BIT(23) 1186#define ENMBID BIT(24) 1187#define APP_BASSN BIT(27) 1188#define APP_PHYSTS BIT(28) 1189#define APP_ICV BIT(29) 1190#define APP_MIC BIT(30) 1191#define APP_FCS BIT(31) 1192 1193#define _MIN_SPACE(x) ((x) & 0x7) 1194#define _SHORT_GI_PADDING(x) (((x) & 0x1F) << 3) 1195 1196#define RXERR_TYPE_OFDM_PPDU 0 1197#define RXERR_TYPE_OFDM_FALSE_ALARM 1 1198#define RXERR_TYPE_OFDM_MPDU_OK 2 1199#define RXERR_TYPE_OFDM_MPDU_FAIL 3 1200#define RXERR_TYPE_CCK_PPDU 4 1201#define RXERR_TYPE_CCK_FALSE_ALARM 5 1202#define RXERR_TYPE_CCK_MPDU_OK 6 1203#define RXERR_TYPE_CCK_MPDU_FAIL 7 1204#define RXERR_TYPE_HT_PPDU 8 1205#define RXERR_TYPE_HT_FALSE_ALARM 9 1206#define RXERR_TYPE_HT_MPDU_TOTAL 10 1207#define RXERR_TYPE_HT_MPDU_OK 11 1208#define RXERR_TYPE_HT_MPDU_FAIL 12 1209#define RXERR_TYPE_RX_FULL_DROP 15 1210 1211#define RXERR_COUNTER_MASK 0xFFFFF 1212#define RXERR_RPT_RST BIT(27) 1213#define _RXERR_RPT_SEL(type) ((type) << 28) 1214 1215#define SCR_TXUSEDK BIT(0) 1216#define SCR_RXUSEDK BIT(1) 1217#define SCR_TXENCENABLE BIT(2) 1218#define SCR_RXDECENABLE BIT(3) 1219#define SCR_SKBYA2 BIT(4) 1220#define SCR_NOSKMC BIT(5) 1221#define SCR_TXBCUSEDK BIT(6) 1222#define SCR_RXBCUSEDK BIT(7) 1223 1224#define USB_IS_HIGH_SPEED 0 1225#define USB_IS_FULL_SPEED 1 1226#define USB_SPEED_MASK BIT(5) 1227 1228#define USB_NORMAL_SIE_EP_MASK 0xF 1229#define USB_NORMAL_SIE_EP_SHIFT 4 1230 1231#define USB_TEST_EP_MASK 0x30 1232#define USB_TEST_EP_SHIFT 4 1233 1234#define USB_AGG_EN BIT(3) 1235 1236#define MAC_ADDR_LEN 6 1237#define LAST_ENTRY_OF_TX_PKT_BUFFER 175/*255 88e*/ 1238 1239#define POLLING_LLT_THRESHOLD 20 1240#define POLLING_READY_TIMEOUT_COUNT 3000 1241 1242#define MAX_MSS_DENSITY_2T 0x13 1243#define MAX_MSS_DENSITY_1T 0x0A 1244 1245#define EPROM_CMD_OPERATING_MODE_MASK ((1<<7)|(1<<6)) 1246#define EPROM_CMD_CONFIG 0x3 1247#define EPROM_CMD_LOAD 1 1248 1249#define HWSET_MAX_SIZE_92S HWSET_MAX_SIZE 1250 1251#define HAL_8192C_HW_GPIO_WPS_BIT BIT(2) 1252 1253#define RPMAC_RESET 0x100 1254#define RPMAC_TXSTART 0x104 1255#define RPMAC_TXLEGACYSIG 0x108 1256#define RPMAC_TXHTSIG1 0x10c 1257#define RPMAC_TXHTSIG2 0x110 1258#define RPMAC_PHYDEBUG 0x114 1259#define RPMAC_TXPACKETNUM 0x118 1260#define RPMAC_TXIDLE 0x11c 1261#define RPMAC_TXMACHEADER0 0x120 1262#define RPMAC_TXMACHEADER1 0x124 1263#define RPMAC_TXMACHEADER2 0x128 1264#define RPMAC_TXMACHEADER3 0x12c 1265#define RPMAC_TXMACHEADER4 0x130 1266#define RPMAC_TXMACHEADER5 0x134 1267#define RPMAC_TXDADATYPE 0x138 1268#define RPMAC_TXRANDOMSEED 0x13c 1269#define RPMAC_CCKPLCPPREAMBLE 0x140 1270#define RPMAC_CCKPLCPHEADER 0x144 1271#define RPMAC_CCKCRC16 0x148 1272#define RPMAC_OFDMRXCRC32OK 0x170 1273#define RPMAC_OFDMRXCRC32Er 0x174 1274#define RPMAC_OFDMRXPARITYER 0x178 1275#define RPMAC_OFDMRXCRC8ER 0x17c 1276#define RPMAC_CCKCRXRC16ER 0x180 1277#define RPMAC_CCKCRXRC32ER 0x184 1278#define RPMAC_CCKCRXRC32OK 0x188 1279#define RPMAC_TXSTATUS 0x18c 1280 1281#define RFPGA0_RFMOD 0x800 1282 1283#define RFPGA0_TXINFO 0x804 1284#define RFPGA0_PSDFUNCTION 0x808 1285 1286#define RFPGA0_TXGAINSTAGE 0x80c 1287 1288#define RFPGA0_RFTIMING1 0x810 1289#define RFPGA0_RFTIMING2 0x814 1290 1291#define RFPGA0_XA_HSSIPARAMETER1 0x820 1292#define RFPGA0_XA_HSSIPARAMETER2 0x824 1293#define RFPGA0_XB_HSSIPARAMETER1 0x828 1294#define RFPGA0_XB_HSSIPARAMETER2 0x82c 1295 1296#define RFPGA0_XA_LSSIPARAMETER 0x840 1297#define RFPGA0_XB_LSSIPARAMETER 0x844 1298 1299#define RFPGA0_RFWAKEUPPARAMETER 0x850 1300#define RFPGA0_RFSLEEPUPPARAMETER 0x854 1301 1302#define RFPGA0_XAB_SWITCHCONTROL 0x858 1303#define RFPGA0_XCD_SWITCHCONTROL 0x85c 1304 1305#define RFPGA0_XA_RFINTERFACEOE 0x860 1306#define RFPGA0_XB_RFINTERFACEOE 0x864 1307 1308#define RFPGA0_XAB_RFINTERFACESW 0x870 1309#define RFPGA0_XCD_RFINTERFACESW 0x874 1310 1311#define rFPGA0_XAB_RFPARAMETER 0x878 1312#define rFPGA0_XCD_RFPARAMETER 0x87c 1313 1314#define RFPGA0_ANALOGPARAMETER1 0x880 1315#define RFPGA0_ANALOGPARAMETER2 0x884 1316#define RFPGA0_ANALOGPARAMETER3 0x888 1317#define RFPGA0_ANALOGPARAMETER4 0x88c 1318 1319#define RFPGA0_XA_LSSIREADBACK 0x8a0 1320#define RFPGA0_XB_LSSIREADBACK 0x8a4 1321#define RFPGA0_XC_LSSIREADBACK 0x8a8 1322#define RFPGA0_XD_LSSIREADBACK 0x8ac 1323 1324#define RFPGA0_PSDREPORT 0x8b4 1325#define TRANSCEIVEA_HSPI_READBACK 0x8b8 1326#define TRANSCEIVEB_HSPI_READBACK 0x8bc 1327#define REG_SC_CNT 0x8c4 1328#define RFPGA0_XAB_RFINTERFACERB 0x8e0 1329#define RFPGA0_XCD_RFINTERFACERB 0x8e4 1330 1331#define RFPGA1_RFMOD 0x900 1332 1333#define RFPGA1_TXBLOCK 0x904 1334#define RFPGA1_DEBUGSELECT 0x908 1335#define RFPGA1_TXINFO 0x90c 1336 1337#define RCCK0_SYSTEM 0xa00 1338 1339#define RCCK0_AFESETTING 0xa04 1340#define RCCK0_CCA 0xa08 1341 1342#define RCCK0_RXAGC1 0xa0c 1343#define RCCK0_RXAGC2 0xa10 1344 1345#define RCCK0_RXHP 0xa14 1346 1347#define RCCK0_DSPPARAMETER1 0xa18 1348#define RCCK0_DSPPARAMETER2 0xa1c 1349 1350#define RCCK0_TXFILTER1 0xa20 1351#define RCCK0_TXFILTER2 0xa24 1352#define RCCK0_DEBUGPORT 0xa28 1353#define RCCK0_FALSEALARMREPORT 0xa2c 1354#define RCCK0_TRSSIREPORT 0xa50 1355#define RCCK0_RXREPORT 0xa54 1356#define RCCK0_FACOUNTERLOWER 0xa5c 1357#define RCCK0_FACOUNTERUPPER 0xa58 1358#define RCCK0_CCA_CNT 0xa60 1359 1360 1361/* PageB(0xB00) */ 1362#define RPDP_ANTA 0xb00 1363#define RPDP_ANTA_4 0xb04 1364#define RPDP_ANTA_8 0xb08 1365#define RPDP_ANTA_C 0xb0c 1366#define RPDP_ANTA_10 0xb10 1367#define RPDP_ANTA_14 0xb14 1368#define RPDP_ANTA_18 0xb18 1369#define RPDP_ANTA_1C 0xb1c 1370#define RPDP_ANTA_20 0xb20 1371#define RPDP_ANTA_24 0xb24 1372 1373#define RCONFIG_PMPD_ANTA 0xb28 1374#define RCONFIG_RAM64X16 0xb2c 1375 1376#define RBNDA 0xb30 1377#define RHSSIPAR 0xb34 1378 1379#define RCONFIG_ANTA 0xb68 1380#define RCONFIG_ANTB 0xb6c 1381 1382#define RPDP_ANTB 0xb70 1383#define RPDP_ANTB_4 0xb74 1384#define RPDP_ANTB_8 0xb78 1385#define RPDP_ANTB_C 0xb7c 1386#define RPDP_ANTB_10 0xb80 1387#define RPDP_ANTB_14 0xb84 1388#define RPDP_ANTB_18 0xb88 1389#define RPDP_ANTB_1C 0xb8c 1390#define RPDP_ANTB_20 0xb90 1391#define RPDP_ANTB_24 0xb94 1392 1393#define RCONFIG_PMPD_ANTB 0xb98 1394 1395#define RBNDB 0xba0 1396 1397#define RAPK 0xbd8 1398#define rPm_Rx0_AntA 0xbdc 1399#define rPm_Rx1_AntA 0xbe0 1400#define rPm_Rx2_AntA 0xbe4 1401#define rPm_Rx3_AntA 0xbe8 1402#define rPm_Rx0_AntB 0xbec 1403#define rPm_Rx1_AntB 0xbf0 1404#define rPm_Rx2_AntB 0xbf4 1405#define rPm_Rx3_AntB 0xbf8 1406 1407/*Page C*/ 1408#define ROFDM0_LSTF 0xc00 1409 1410#define ROFDM0_TRXPATHENABLE 0xc04 1411#define ROFDM0_TRMUXPAR 0xc08 1412#define ROFDM0_TRSWISOLATION 0xc0c 1413 1414#define ROFDM0_XARXAFE 0xc10 1415#define ROFDM0_XARXIQIMBAL 0xc14 1416#define ROFDM0_XBRXAFE 0xc18 1417#define ROFDM0_XBRXIQIMBAL 0xc1c 1418#define ROFDM0_XCRXAFE 0xc20 1419#define ROFDM0_XCRXIQIMBAL 0xc24 1420#define ROFDM0_XDRXAFE 0xc28 1421#define ROFDM0_XDRXIQIMBAL 0xc2c 1422 1423#define ROFDM0_RXDETECTOR1 0xc30 1424#define ROFDM0_RXDETECTOR2 0xc34 1425#define ROFDM0_RXDETECTOR3 0xc38 1426#define ROFDM0_RXDETECTOR4 0xc3c 1427 1428#define ROFDM0_RXDSP 0xc40 1429#define ROFDM0_CFOANDDAGC 0xc44 1430#define ROFDM0_CCADROPTHRES 0xc48 1431#define ROFDM0_ECCATHRES 0xc4c 1432 1433#define ROFDM0_XAAGCCORE1 0xc50 1434#define ROFDM0_XAAGCCORE2 0xc54 1435#define ROFDM0_XBAGCCORE1 0xc58 1436#define ROFDM0_XBAGCCORE2 0xc5c 1437#define ROFDM0_XCAGCCORE1 0xc60 1438#define ROFDM0_XCAGCCORE2 0xc64 1439#define ROFDM0_XDAGCCORE1 0xc68 1440#define ROFDM0_XDAGCCORE2 0xc6c 1441 1442#define ROFDM0_AGCPARAMETER1 0xc70 1443#define ROFDM0_AGCPARAMETER2 0xc74 1444#define ROFDM0_AGCRSSITABLE 0xc78 1445#define ROFDM0_HTSTFAGC 0xc7c 1446 1447#define ROFDM0_XATXIQIMBAL 0xc80 1448#define ROFDM0_XATXAFE 0xc84 1449#define ROFDM0_XBTXIQIMBAL 0xc88 1450#define ROFDM0_XBTXAFE 0xc8c 1451#define ROFDM0_XCTXIQIMBAL 0xc90 1452#define ROFDM0_XCTXAFE 0xc94 1453#define ROFDM0_XDTXIQIMBAL 0xc98 1454#define ROFDM0_XDTXAFE 0xc9c 1455 1456#define ROFDM0_RXIQEXTANTA 0xca0 1457#define ROFDM0_TXCOEFF1 0xca4 1458#define ROFDM0_TXCOEFF2 0xca8 1459#define ROFDM0_TXCOEFF3 0xcac 1460#define ROFDM0_TXCOEFF4 0xcb0 1461#define ROFDM0_TXCOEFF5 0xcb4 1462#define ROFDM0_TXCOEFF6 0xcb8 1463 1464#define ROFDM0_RXHPPARAMETER 0xce0 1465#define ROFDM0_TXPSEUDONOISEWGT 0xce4 1466#define ROFDM0_FRAMESYNC 0xcf0 1467#define ROFDM0_DFSREPORT 0xcf4 1468 1469 1470#define ROFDM1_LSTF 0xd00 1471#define ROFDM1_TRXPATHENABLE 0xd04 1472 1473#define ROFDM1_CF0 0xd08 1474#define ROFDM1_CSI1 0xd10 1475#define ROFDM1_SBD 0xd14 1476#define ROFDM1_CSI2 0xd18 1477#define ROFDM1_CFOTRACKING 0xd2c 1478#define ROFDM1_TRXMESAURE1 0xd34 1479#define ROFDM1_INTFDET 0xd3c 1480#define ROFDM1_PSEUDONOISESTATEAB 0xd50 1481#define ROFDM1_PSEUDONOISESTATECD 0xd54 1482#define ROFDM1_RXPSEUDONOISEWGT 0xd58 1483 1484#define ROFDM_PHYCOUNTER1 0xda0 1485#define ROFDM_PHYCOUNTER2 0xda4 1486#define ROFDM_PHYCOUNTER3 0xda8 1487 1488#define ROFDM_SHORTCFOAB 0xdac 1489#define ROFDM_SHORTCFOCD 0xdb0 1490#define ROFDM_LONGCFOAB 0xdb4 1491#define ROFDM_LONGCFOCD 0xdb8 1492#define ROFDM_TAILCF0AB 0xdbc 1493#define ROFDM_TAILCF0CD 0xdc0 1494#define ROFDM_PWMEASURE1 0xdc4 1495#define ROFDM_PWMEASURE2 0xdc8 1496#define ROFDM_BWREPORT 0xdcc 1497#define ROFDM_AGCREPORT 0xdd0 1498#define ROFDM_RXSNR 0xdd4 1499#define ROFDM_RXEVMCSI 0xdd8 1500#define ROFDM_SIGREPORT 0xddc 1501 1502#define RTXAGC_A_RATE18_06 0xe00 1503#define RTXAGC_A_RATE54_24 0xe04 1504#define RTXAGC_A_CCK1_MCS32 0xe08 1505#define RTXAGC_A_MCS03_MCS00 0xe10 1506#define RTXAGC_A_MCS07_MCS04 0xe14 1507#define RTXAGC_A_MCS11_MCS08 0xe18 1508#define RTXAGC_A_MCS15_MCS12 0xe1c 1509 1510#define RTXAGC_B_RATE18_06 0x830 1511#define RTXAGC_B_RATE54_24 0x834 1512#define RTXAGC_B_CCK1_55_MCS32 0x838 1513#define RTXAGC_B_MCS03_MCS00 0x83c 1514#define RTXAGC_B_MCS07_MCS04 0x848 1515#define RTXAGC_B_MCS11_MCS08 0x84c 1516#define RTXAGC_B_MCS15_MCS12 0x868 1517#define RTXAGC_B_CCK11_A_CCK2_11 0x86c 1518 1519#define RFPGA0_IQK 0xe28 1520#define RTX_IQK_TONE_A 0xe30 1521#define RRX_IQK_TONE_A 0xe34 1522#define RTX_IQK_PI_A 0xe38 1523#define RRX_IQK_PI_A 0xe3c 1524 1525#define RTX_IQK 0xe40 1526#define RRX_IQK 0xe44 1527#define RIQK_AGC_PTS 0xe48 1528#define RIQK_AGC_RSP 0xe4c 1529#define RTX_IQK_TONE_B 0xe50 1530#define RRX_IQK_TONE_B 0xe54 1531#define RTX_IQK_PI_B 0xe58 1532#define RRX_IQK_PI_B 0xe5c 1533#define RIQK_AGC_CONT 0xe60 1534 1535#define RBLUE_TOOTH 0xe6c 1536#define RRX_WAIT_CCA 0xe70 1537#define RTX_CCK_RFON 0xe74 1538#define RTX_CCK_BBON 0xe78 1539#define RTX_OFDM_RFON 0xe7c 1540#define RTX_OFDM_BBON 0xe80 1541#define RTX_TO_RX 0xe84 1542#define RTX_TO_TX 0xe88 1543#define RRX_CCK 0xe8c 1544 1545#define RTX_POWER_BEFORE_IQK_A 0xe94 1546#define RTX_POWER_AFTER_IQK_A 0xe9c 1547 1548#define RRX_POWER_BEFORE_IQK_A 0xea0 1549#define RRX_POWER_BEFORE_IQK_A_2 0xea4 1550#define RRX_POWER_AFTER_IQK_A 0xea8 1551#define RRX_POWER_AFTER_IQK_A_2 0xeac 1552 1553#define RTX_POWER_BEFORE_IQK_B 0xeb4 1554#define RTX_POWER_AFTER_IQK_B 0xebc 1555 1556#define RRX_POWER_BEFORE_IQK_B 0xec0 1557#define RRX_POWER_BEFORE_IQK_B_2 0xec4 1558#define RRX_POWER_AFTER_IQK_B 0xec8 1559#define RRX_POWER_AFTER_IQK_B_2 0xecc 1560 1561#define RRX_OFDM 0xed0 1562#define RRX_WAIT_RIFS 0xed4 1563#define RRX_TO_RX 0xed8 1564#define RSTANDBY 0xedc 1565#define RSLEEP 0xee0 1566#define RPMPD_ANAEN 0xeec 1567 1568#define RZEBRA1_HSSIENABLE 0x0 1569#define RZEBRA1_TRXENABLE1 0x1 1570#define RZEBRA1_TRXENABLE2 0x2 1571#define RZEBRA1_AGC 0x4 1572#define RZEBRA1_CHARGEPUMP 0x5 1573#define RZEBRA1_CHANNEL 0x7 1574 1575#define RZEBRA1_TXGAIN 0x8 1576#define RZEBRA1_TXLPF 0x9 1577#define RZEBRA1_RXLPF 0xb 1578#define RZEBRA1_RXHPFCORNER 0xc 1579 1580#define RGLOBALCTRL 0 1581#define RRTL8256_TXLPF 19 1582#define RRTL8256_RXLPF 11 1583#define RRTL8258_TXLPF 0x11 1584#define RRTL8258_RXLPF 0x13 1585#define RRTL8258_RSSILPF 0xa 1586 1587#define RF_AC 0x00 1588 1589#define RF_IQADJ_G1 0x01 1590#define RF_IQADJ_G2 0x02 1591#define RF_POW_TRSW 0x05 1592 1593#define RF_GAIN_RX 0x06 1594#define RF_GAIN_TX 0x07 1595 1596#define RF_TXM_IDAC 0x08 1597#define RF_BS_IQGEN 0x0F 1598 1599#define RF_MODE1 0x10 1600#define RF_MODE2 0x11 1601 1602#define RF_RX_AGC_HP 0x12 1603#define RF_TX_AGC 0x13 1604#define RF_BIAS 0x14 1605#define RF_IPA 0x15 1606#define RF_POW_ABILITY 0x17 1607#define RF_MODE_AG 0x18 1608#define RRFCHANNEL 0x18 1609#define RF_CHNLBW 0x18 1610#define RF_TOP 0x19 1611 1612#define RF_RX_G1 0x1A 1613#define RF_RX_G2 0x1B 1614 1615#define RF_RX_BB2 0x1C 1616#define RF_RX_BB1 0x1D 1617 1618#define RF_RCK1 0x1E 1619#define RF_RCK2 0x1F 1620 1621#define RF_TX_G1 0x20 1622#define RF_TX_G2 0x21 1623#define RF_TX_G3 0x22 1624 1625#define RF_TX_BB1 0x23 1626#define RF_T_METER 0x42 1627 1628#define RF_SYN_G1 0x25 1629#define RF_SYN_G2 0x26 1630#define RF_SYN_G3 0x27 1631#define RF_SYN_G4 0x28 1632#define RF_SYN_G5 0x29 1633#define RF_SYN_G6 0x2A 1634#define RF_SYN_G7 0x2B 1635#define RF_SYN_G8 0x2C 1636 1637#define RF_RCK_OS 0x30 1638#define RF_TXPA_G1 0x31 1639#define RF_TXPA_G2 0x32 1640#define RF_TXPA_G3 0x33 1641 1642#define RF_TX_BIAS_A 0x35 1643#define RF_TX_BIAS_D 0x36 1644#define RF_LOBF_9 0x38 1645#define RF_RXRF_A3 0x3C 1646#define RF_TRSW 0x3F 1647 1648#define RF_TXRF_A2 0x41 1649#define RF_TXPA_G4 0x46 1650#define RF_TXPA_A4 0x4B 1651 1652#define RF_WE_LUT 0xEF 1653 1654#define BBBRESETB 0x100 1655#define BGLOBALRESETB 0x200 1656#define BOFDMTXSTART 0x4 1657#define BCCKTXSTART 0x8 1658#define BCRC32DEBUG 0x100 1659#define BPMACLOOPBACK 0x10 1660#define BTXLSIG 0xffffff 1661#define BOFDMTXRATE 0xf 1662#define BOFDMTXRESERVED 0x10 1663#define BOFDMTXLENGTH 0x1ffe0 1664#define BOFDMTXPARITY 0x20000 1665#define BTXHTSIG1 0xffffff 1666#define BTXHTMCSRATE 0x7f 1667#define BTXHTBW 0x80 1668#define BTXHTLENGTH 0xffff00 1669#define BTXHTSIG2 0xffffff 1670#define BTXHTSMOOTHING 0x1 1671#define BTXHTSOUNDING 0x2 1672#define BTXHTRESERVED 0x4 1673#define BTXHTAGGREATION 0x8 1674#define BTXHTSTBC 0x30 1675#define BTXHTADVANCECODING 0x40 1676#define BTXHTSHORTGI 0x80 1677#define BTXHTNUMBERHT_LTF 0x300 1678#define BTXHTCRC8 0x3fc00 1679#define BCOUNTERRESET 0x10000 1680#define BNUMOFOFDMTX 0xffff 1681#define BNUMOFCCKTX 0xffff0000 1682#define BTXIDLEINTERVAL 0xffff 1683#define BOFDMSERVICE 0xffff0000 1684#define BTXMACHEADER 0xffffffff 1685#define BTXDATAINIT 0xff 1686#define BTXHTMODE 0x100 1687#define BTXDATATYPE 0x30000 1688#define BTXRANDOMSEED 0xffffffff 1689#define BCCKTXPREAMBLE 0x1 1690#define BCCKTXSFD 0xffff0000 1691#define BCCKTXSIG 0xff 1692#define BCCKTXSERVICE 0xff00 1693#define BCCKLENGTHEXT 0x8000 1694#define BCCKTXLENGHT 0xffff0000 1695#define BCCKTXCRC16 0xffff 1696#define BCCKTXSTATUS 0x1 1697#define BOFDMTXSTATUS 0x2 1698#define IS_BB_REG_OFFSET_92S(_offset) \ 1699 ((_offset >= 0x800) && (_offset <= 0xfff)) 1700 1701#define BRFMOD 0x1 1702#define BJAPANMODE 0x2 1703#define BCCKTXSC 0x30 1704#define BCCKEN 0x1000000 1705#define BOFDMEN 0x2000000 1706 1707#define BOFDMRXADCPHASE 0x10000 1708#define BOFDMTXDACPHASE 0x40000 1709#define BXATXAGC 0x3f 1710 1711#define BXBTXAGC 0xf00 1712#define BXCTXAGC 0xf000 1713#define BXDTXAGC 0xf0000 1714 1715#define BPASTART 0xf0000000 1716#define BTRSTART 0x00f00000 1717#define BRFSTART 0x0000f000 1718#define BBBSTART 0x000000f0 1719#define BBBCCKSTART 0x0000000f 1720#define BPAEND 0xf 1721#define BTREND 0x0f000000 1722#define BRFEND 0x000f0000 1723#define BCCAMASK 0x000000f0 1724#define BR2RCCAMASK 0x00000f00 1725#define BHSSI_R2TDELAY 0xf8000000 1726#define BHSSI_T2RDELAY 0xf80000 1727#define BCONTXHSSI 0x400 1728#define BIGFROMCCK 0x200 1729#define BAGCADDRESS 0x3f 1730#define BRXHPTX 0x7000 1731#define BRXHP2RX 0x38000 1732#define BRXHPCCKINI 0xc0000 1733#define BAGCTXCODE 0xc00000 1734#define BAGCRXCODE 0x300000 1735 1736#define B3WIREDATALENGTH 0x800 1737#define B3WIREADDREAALENGTH 0x400 1738 1739#define B3WIRERFPOWERDOWN 0x1 1740#define B5GPAPEPOLARITY 0x40000000 1741#define B2GPAPEPOLARITY 0x80000000 1742#define BRFSW_TXDEFAULTANT 0x3 1743#define BRFSW_TXOPTIONANT 0x30 1744#define BRFSW_RXDEFAULTANT 0x300 1745#define BRFSW_RXOPTIONANT 0x3000 1746#define BRFSI_3WIREDATA 0x1 1747#define BRFSI_3WIRECLOCK 0x2 1748#define BRFSI_3WIRELOAD 0x4 1749#define BRFSI_3WIRERW 0x8 1750#define BRFSI_3WIRE 0xf 1751 1752#define BRFSI_RFENV 0x10 1753 1754#define BRFSI_TRSW 0x20 1755#define BRFSI_TRSWB 0x40 1756#define BRFSI_ANTSW 0x100 1757#define BRFSI_ANTSWB 0x200 1758#define BRFSI_PAPE 0x400 1759#define BRFSI_PAPE5G 0x800 1760#define BBANDSELECT 0x1 1761#define BHTSIG2_GI 0x80 1762#define BHTSIG2_SMOOTHING 0x01 1763#define BHTSIG2_SOUNDING 0x02 1764#define BHTSIG2_AGGREATON 0x08 1765#define BHTSIG2_STBC 0x30 1766#define BHTSIG2_ADVCODING 0x40 1767#define BHTSIG2_NUMOFHTLTF 0x300 1768#define BHTSIG2_CRC8 0x3fc 1769#define BHTSIG1_MCS 0x7f 1770#define BHTSIG1_BANDWIDTH 0x80 1771#define BHTSIG1_HTLENGTH 0xffff 1772#define BLSIG_RATE 0xf 1773#define BLSIG_RESERVED 0x10 1774#define BLSIG_LENGTH 0x1fffe 1775#define BLSIG_PARITY 0x20 1776#define BCCKRXPHASE 0x4 1777 1778#define BLSSIREADADDRESS 0x7f800000 1779#define BLSSIREADEDGE 0x80000000 1780 1781#define BLSSIREADBACKDATA 0xfffff 1782 1783#define BLSSIREADOKFLAG 0x1000 1784#define BCCKSAMPLERATE 0x8 1785#define BREGULATOR0STANDBY 0x1 1786#define BREGULATORPLLSTANDBY 0x2 1787#define BREGULATOR1STANDBY 0x4 1788#define BPLLPOWERUP 0x8 1789#define BDPLLPOWERUP 0x10 1790#define BDA10POWERUP 0x20 1791#define BAD7POWERUP 0x200 1792#define BDA6POWERUP 0x2000 1793#define BXTALPOWERUP 0x4000 1794#define B40MDCLKPOWERUP 0x8000 1795#define BDA6DEBUGMODE 0x20000 1796#define BDA6SWING 0x380000 1797 1798#define BADCLKPHASE 0x4000000 1799#define B80MCLKDELAY 0x18000000 1800#define BAFEWATCHDOGENABLE 0x20000000 1801 1802#define BXTALCAP01 0xc0000000 1803#define BXTALCAP23 0x3 1804#define BXTALCAP92X 0x0f000000 1805#define BXTALCAP 0x0f000000 1806 1807#define BINTDIFCLKENABLE 0x400 1808#define BEXTSIGCLKENABLE 0x800 1809#define BBANDGAP_MBIAS_POWERUP 0x10000 1810#define BAD11SH_GAIN 0xc0000 1811#define BAD11NPUT_RANGE 0x700000 1812#define BAD110P_CURRENT 0x3800000 1813#define BLPATH_LOOPBACK 0x4000000 1814#define BQPATH_LOOPBACK 0x8000000 1815#define BAFE_LOOPBACK 0x10000000 1816#define BDA10_SWING 0x7e0 1817#define BDA10_REVERSE 0x800 1818#define BDA_CLK_SOURCE 0x1000 1819#define BDA7INPUT_RANGE 0x6000 1820#define BDA7_GAIN 0x38000 1821#define BDA7OUTPUT_CM_MODE 0x40000 1822#define BDA7INPUT_CM_MODE 0x380000 1823#define BDA7CURRENT 0xc00000 1824#define BREGULATOR_ADJUST 0x7000000 1825#define BAD11POWERUP_ATTX 0x1 1826#define BDA10PS_ATTX 0x10 1827#define BAD11POWERUP_ATRX 0x100 1828#define BDA10PS_ATRX 0x1000 1829#define BCCKRX_AGC_FORMAT 0x200 1830#define BPSDFFT_SAMPLE_POINT 0xc000 1831#define BPSD_AVERAGE_NUM 0x3000 1832#define BIQPATH_CONTROL 0xc00 1833#define BPSD_FREQ 0x3ff 1834#define BPSD_ANTENNA_PATH 0x30 1835#define BPSD_IQ_SWITCH 0x40 1836#define BPSD_RX_TRIGGER 0x400000 1837#define BPSD_TX_TRIGGERCW 0x80000000 1838#define BPSD_SINE_TONE_SCALE 0x7f000000 1839#define BPSD_REPORT 0xffff 1840 1841#define BOFDM_TXSC 0x30000000 1842#define BCCK_TXON 0x1 1843#define BOFDM_TXON 0x2 1844#define BDEBUG_PAGE 0xfff 1845#define BDEBUG_ITEM 0xff 1846#define BANTL 0x10 1847#define BANT_NONHT 0x100 1848#define BANT_HT1 0x1000 1849#define BANT_HT2 0x10000 1850#define BANT_HT1S1 0x100000 1851#define BANT_NONHTS1 0x1000000 1852 1853#define BCCK_BBMODE 0x3 1854#define BCCK_TXPOWERSAVING 0x80 1855#define BCCK_RXPOWERSAVING 0x40 1856 1857#define BCCK_SIDEBAND 0x10 1858 1859#define BCCK_SCRAMBLE 0x8 1860#define BCCK_ANTDIVERSITY 0x8000 1861#define BCCK_CARRIER_RECOVERY 0x4000 1862#define BCCK_TXRATE 0x3000 1863#define BCCK_DCCANCEL 0x0800 1864#define BCCK_ISICANCEL 0x0400 1865#define BCCK_MATCH_FILTER 0x0200 1866#define BCCK_EQUALIZER 0x0100 1867#define BCCK_PREAMBLE_DETECT 0x800000 1868#define BCCK_FAST_FALSECCA 0x400000 1869#define BCCK_CH_ESTSTART 0x300000 1870#define BCCK_CCA_COUNT 0x080000 1871#define BCCK_CS_LIM 0x070000 1872#define BCCK_BIST_MODE 0x80000000 1873#define BCCK_CCAMASK 0x40000000 1874#define BCCK_TX_DAC_PHASE 0x4 1875#define BCCK_RX_ADC_PHASE 0x20000000 1876#define BCCKR_CP_MODE 0x0100 1877#define BCCK_TXDC_OFFSET 0xf0 1878#define BCCK_RXDC_OFFSET 0xf 1879#define BCCK_CCA_MODE 0xc000 1880#define BCCK_FALSECS_LIM 0x3f00 1881#define BCCK_CS_RATIO 0xc00000 1882#define BCCK_CORGBIT_SEL 0x300000 1883#define BCCK_PD_LIM 0x0f0000 1884#define BCCK_NEWCCA 0x80000000 1885#define BCCK_RXHP_OF_IG 0x8000 1886#define BCCK_RXIG 0x7f00 1887#define BCCK_LNA_POLARITY 0x800000 1888#define BCCK_RX1ST_BAIN 0x7f0000 1889#define BCCK_RF_EXTEND 0x20000000 1890#define BCCK_RXAGC_SATLEVEL 0x1f000000 1891#define BCCK_RXAGC_SATCOUNT 0xe0 1892#define BCCKRXRFSETTLE 0x1f 1893#define BCCK_FIXED_RXAGC 0x8000 1894#define BCCK_ANTENNA_POLARITY 0x2000 1895#define BCCK_TXFILTER_TYPE 0x0c00 1896#define BCCK_RXAGC_REPORTTYPE 0x0300 1897#define BCCK_RXDAGC_EN 0x80000000 1898#define BCCK_RXDAGC_PERIOD 0x20000000 1899#define BCCK_RXDAGC_SATLEVEL 0x1f000000 1900#define BCCK_TIMING_RECOVERY 0x800000 1901#define BCCK_TXC0 0x3f0000 1902#define BCCK_TXC1 0x3f000000 1903#define BCCK_TXC2 0x3f 1904#define BCCK_TXC3 0x3f00 1905#define BCCK_TXC4 0x3f0000 1906#define BCCK_TXC5 0x3f000000 1907#define BCCK_TXC6 0x3f 1908#define BCCK_TXC7 0x3f00 1909#define BCCK_DEBUGPORT 0xff0000 1910#define BCCK_DAC_DEBUG 0x0f000000 1911#define BCCK_FALSEALARM_ENABLE 0x8000 1912#define BCCK_FALSEALARM_READ 0x4000 1913#define BCCK_TRSSI 0x7f 1914#define BCCK_RXAGC_REPORT 0xfe 1915#define BCCK_RXREPORT_ANTSEL 0x80000000 1916#define BCCK_RXREPORT_MFOFF 0x40000000 1917#define BCCK_RXREPORT_SQLOSS 0x20000000 1918#define BCCK_RXREPORT_PKTLOSS 0x10000000 1919#define BCCK_RXREPORT_LOCKEDBIT 0x08000000 1920#define BCCK_RXREPORT_RATEERROR 0x04000000 1921#define BCCK_RXREPORT_RXRATE 0x03000000 1922#define BCCK_RXFA_COUNTER_LOWER 0xff 1923#define BCCK_RXFA_COUNTER_UPPER 0xff000000 1924#define BCCK_RXHPAGC_START 0xe000 1925#define BCCK_RXHPAGC_FINAL 0x1c00 1926#define BCCK_RXFALSEALARM_ENABLE 0x8000 1927#define BCCK_FACOUNTER_FREEZE 0x4000 1928#define BCCK_TXPATH_SEL 0x10000000 1929#define BCCK_DEFAULT_RXPATH 0xc000000 1930#define BCCK_OPTION_RXPATH 0x3000000 1931 1932#define BNUM_OFSTF 0x3 1933#define BSHIFT_L 0xc0 1934#define BGI_TH 0xc 1935#define BRXPATH_A 0x1 1936#define BRXPATH_B 0x2 1937#define BRXPATH_C 0x4 1938#define BRXPATH_D 0x8 1939#define BTXPATH_A 0x1 1940#define BTXPATH_B 0x2 1941#define BTXPATH_C 0x4 1942#define BTXPATH_D 0x8 1943#define BTRSSI_FREQ 0x200 1944#define BADC_BACKOFF 0x3000 1945#define BDFIR_BACKOFF 0xc000 1946#define BTRSSI_LATCH_PHASE 0x10000 1947#define BRX_LDC_OFFSET 0xff 1948#define BRX_QDC_OFFSET 0xff00 1949#define BRX_DFIR_MODE 0x1800000 1950#define BRX_DCNF_TYPE 0xe000000 1951#define BRXIQIMB_A 0x3ff 1952#define BRXIQIMB_B 0xfc00 1953#define BRXIQIMB_C 0x3f0000 1954#define BRXIQIMB_D 0xffc00000 1955#define BDC_DC_NOTCH 0x60000 1956#define BRXNB_NOTCH 0x1f000000 1957#define BPD_TH 0xf 1958#define BPD_TH_OPT2 0xc000 1959#define BPWED_TH 0x700 1960#define BIFMF_WIN_L 0x800 1961#define BPD_OPTION 0x1000 1962#define BMF_WIN_L 0xe000 1963#define BBW_SEARCH_L 0x30000 1964#define BWIN_ENH_L 0xc0000 1965#define BBW_TH 0x700000 1966#define BED_TH2 0x3800000 1967#define BBW_OPTION 0x4000000 1968#define BRADIO_TH 0x18000000 1969#define BWINDOW_L 0xe0000000 1970#define BSBD_OPTION 0x1 1971#define BFRAME_TH 0x1c 1972#define BFS_OPTION 0x60 1973#define BDC_SLOPE_CHECK 0x80 1974#define BFGUARD_COUNTER_DC_L 0xe00 1975#define BFRAME_WEIGHT_SHORT 0x7000 1976#define BSUB_TUNE 0xe00000 1977#define BFRAME_DC_LENGTH 0xe000000 1978#define BSBD_START_OFFSET 0x30000000 1979#define BFRAME_TH_2 0x7 1980#define BFRAME_GI2_TH 0x38 1981#define BGI2_SYNC_EN 0x40 1982#define BSARCH_SHORT_EARLY 0x300 1983#define BSARCH_SHORT_LATE 0xc00 1984#define BSARCH_GI2_LATE 0x70000 1985#define BCFOANTSUM 0x1 1986#define BCFOACC 0x2 1987#define BCFOSTARTOFFSET 0xc 1988#define BCFOLOOPBACK 0x70 1989#define BCFOSUMWEIGHT 0x80 1990#define BDAGCENABLE 0x10000 1991#define BTXIQIMB_A 0x3ff 1992#define BTXIQIMB_B 0xfc00 1993#define BTXIQIMB_C 0x3f0000 1994#define BTXIQIMB_D 0xffc00000 1995#define BTXIDCOFFSET 0xff 1996#define BTXIQDCOFFSET 0xff00 1997#define BTXDFIRMODE 0x10000 1998#define BTXPESUDO_NOISEON 0x4000000 1999#define BTXPESUDO_NOISE_A 0xff 2000#define BTXPESUDO_NOISE_B 0xff00 2001#define BTXPESUDO_NOISE_C 0xff0000 2002#define BTXPESUDO_NOISE_D 0xff000000 2003#define BCCA_DROPOPTION 0x20000 2004#define BCCA_DROPTHRES 0xfff00000 2005#define BEDCCA_H 0xf 2006#define BEDCCA_L 0xf0 2007#define BLAMBDA_ED 0x300 2008#define BRX_INITIALGAIN 0x7f 2009#define BRX_ANTDIV_EN 0x80 2010#define BRX_AGC_ADDRESS_FOR_LNA 0x7f00 2011#define BRX_HIGHPOWER_FLOW 0x8000 2012#define BRX_AGC_FREEZE_THRES 0xc0000 2013#define BRX_FREEZESTEP_AGC1 0x300000 2014#define BRX_FREEZESTEP_AGC2 0xc00000 2015#define BRX_FREEZESTEP_AGC3 0x3000000 2016#define BRX_FREEZESTEP_AGC0 0xc000000 2017#define BRXRSSI_CMP_EN 0x10000000 2018#define BRXQUICK_AGCEN 0x20000000 2019#define BRXAGC_FREEZE_THRES_MODE 0x40000000 2020#define BRX_OVERFLOW_CHECKTYPE 0x80000000 2021#define BRX_AGCSHIFT 0x7f 2022#define BTRSW_TRI_ONLY 0x80 2023#define BPOWER_THRES 0x300 2024#define BRXAGC_EN 0x1 2025#define BRXAGC_TOGETHER_EN 0x2 2026#define BRXAGC_MIN 0x4 2027#define BRXHP_INI 0x7 2028#define BRXHP_TRLNA 0x70 2029#define BRXHP_RSSI 0x700 2030#define BRXHP_BBP1 0x7000 2031#define BRXHP_BBP2 0x70000 2032#define BRXHP_BBP3 0x700000 2033#define BRSSI_H 0x7f0000 2034#define BRSSI_GEN 0x7f000000 2035#define BRXSETTLE_TRSW 0x7 2036#define BRXSETTLE_LNA 0x38 2037#define BRXSETTLE_RSSI 0x1c0 2038#define BRXSETTLE_BBP 0xe00 2039#define BRXSETTLE_RXHP 0x7000 2040#define BRXSETTLE_ANTSW_RSSI 0x38000 2041#define BRXSETTLE_ANTSW 0xc0000 2042#define BRXPROCESS_TIME_DAGC 0x300000 2043#define BRXSETTLE_HSSI 0x400000 2044#define BRXPROCESS_TIME_BBPPW 0x800000 2045#define BRXANTENNA_POWER_SHIFT 0x3000000 2046#define BRSSI_TABLE_SELECT 0xc000000 2047#define BRXHP_FINAL 0x7000000 2048#define BRXHPSETTLE_BBP 0x7 2049#define BRXHTSETTLE_HSSI 0x8 2050#define BRXHTSETTLE_RXHP 0x70 2051#define BRXHTSETTLE_BBPPW 0x80 2052#define BRXHTSETTLE_IDLE 0x300 2053#define BRXHTSETTLE_RESERVED 0x1c00 2054#define BRXHT_RXHP_EN 0x8000 2055#define BRXAGC_FREEZE_THRES 0x30000 2056#define BRXAGC_TOGETHEREN 0x40000 2057#define BRXHTAGC_MIN 0x80000 2058#define BRXHTAGC_EN 0x100000 2059#define BRXHTDAGC_EN 0x200000 2060#define BRXHT_RXHP_BBP 0x1c00000 2061#define BRXHT_RXHP_FINAL 0xe0000000 2062#define BRXPW_RADIO_TH 0x3 2063#define BRXPW_RADIO_EN 0x4 2064#define BRXMF_HOLD 0x3800 2065#define BRXPD_DELAY_TH1 0x38 2066#define BRXPD_DELAY_TH2 0x1c0 2067#define BRXPD_DC_COUNT_MAX 0x600 2068#define BRXPD_DELAY_TH 0x8000 2069#define BRXPROCESS_DELAY 0xf0000 2070#define BRXSEARCHRANGE_GI2_EARLY 0x700000 2071#define BRXFRAME_FUARD_COUNTER_L 0x3800000 2072#define BRXSGI_GUARD_L 0xc000000 2073#define BRXSGI_SEARCH_L 0x30000000 2074#define BRXSGI_TH 0xc0000000 2075#define BDFSCNT0 0xff 2076#define BDFSCNT1 0xff00 2077#define BDFSFLAG 0xf0000 2078#define BMF_WEIGHT_SUM 0x300000 2079#define BMINIDX_TH 0x7f000000 2080#define BDAFORMAT 0x40000 2081#define BTXCH_EMU_ENABLE 0x01000000 2082#define BTRSW_ISOLATION_A 0x7f 2083#define BTRSW_ISOLATION_B 0x7f00 2084#define BTRSW_ISOLATION_C 0x7f0000 2085#define BTRSW_ISOLATION_D 0x7f000000 2086#define BEXT_LNA_GAIN 0x7c00 2087 2088#define BSTBC_EN 0x4 2089#define BANTENNA_MAPPING 0x10 2090#define BNSS 0x20 2091#define BCFO_ANTSUM_ID 0x200 2092#define BPHY_COUNTER_RESET 0x8000000 2093#define BCFO_REPORT_GET 0x4000000 2094#define BOFDM_CONTINUE_TX 0x10000000 2095#define BOFDM_SINGLE_CARRIER 0x20000000 2096#define BOFDM_SINGLE_TONE 0x40000000 2097#define BHT_DETECT 0x100 2098#define BCFOEN 0x10000 2099#define BCFOVALUE 0xfff00000 2100#define BSIGTONE_RE 0x3f 2101#define BSIGTONE_IM 0x7f00 2102#define BCOUNTER_CCA 0xffff 2103#define BCOUNTER_PARITYFAIL 0xffff0000 2104#define BCOUNTER_RATEILLEGAL 0xffff 2105#define BCOUNTER_CRC8FAIL 0xffff0000 2106#define BCOUNTER_MCSNOSUPPORT 0xffff 2107#define BCOUNTER_FASTSYNC 0xffff 2108#define BSHORTCFO 0xfff 2109#define BSHORTCFOT_LENGTH 12 2110#define BSHORTCFOF_LENGTH 11 2111#define BLONGCFO 0x7ff 2112#define BLONGCFOT_LENGTH 11 2113#define BLONGCFOF_LENGTH 11 2114#define BTAILCFO 0x1fff 2115#define BTAILCFOT_LENGTH 13 2116#define BTAILCFOF_LENGTH 12 2117#define BNOISE_EN_PWDB 0xffff 2118#define BCC_POWER_DB 0xffff0000 2119#define BMOISE_PWDB 0xffff 2120#define BPOWERMEAST_LENGTH 10 2121#define BPOWERMEASF_LENGTH 3 2122#define BRX_HT_BW 0x1 2123#define BRXSC 0x6 2124#define BRX_HT 0x8 2125#define BNB_INTF_DET_ON 0x1 2126#define BINTF_WIN_LEN_CFG 0x30 2127#define BNB_INTF_TH_CFG 0x1c0 2128#define BRFGAIN 0x3f 2129#define BTABLESEL 0x40 2130#define BTRSW 0x80 2131#define BRXSNR_A 0xff 2132#define BRXSNR_B 0xff00 2133#define BRXSNR_C 0xff0000 2134#define BRXSNR_D 0xff000000 2135#define BSNR_EVMT_LENGTH 8 2136#define BSNR_EVMF_LENGTH 1 2137#define BCSI1ST 0xff 2138#define BCSI2ND 0xff00 2139#define BRXEVM1ST 0xff0000 2140#define BRXEVM2ND 0xff000000 2141#define BSIGEVM 0xff 2142#define BPWDB 0xff00 2143#define BSGIEN 0x10000 2144 2145#define BSFACTOR_QMA1 0xf 2146#define BSFACTOR_QMA2 0xf0 2147#define BSFACTOR_QMA3 0xf00 2148#define BSFACTOR_QMA4 0xf000 2149#define BSFACTOR_QMA5 0xf0000 2150#define BSFACTOR_QMA6 0xf0000 2151#define BSFACTOR_QMA7 0xf00000 2152#define BSFACTOR_QMA8 0xf000000 2153#define BSFACTOR_QMA9 0xf0000000 2154#define BCSI_SCHEME 0x100000 2155 2156#define BNOISE_LVL_TOP_SET 0x3 2157#define BCHSMOOTH 0x4 2158#define BCHSMOOTH_CFG1 0x38 2159#define BCHSMOOTH_CFG2 0x1c0 2160#define BCHSMOOTH_CFG3 0xe00 2161#define BCHSMOOTH_CFG4 0x7000 2162#define BMRCMODE 0x800000 2163#define BTHEVMCFG 0x7000000 2164 2165#define BLOOP_FIT_TYPE 0x1 2166#define BUPD_CFO 0x40 2167#define BUPD_CFO_OFFDATA 0x80 2168#define BADV_UPD_CFO 0x100 2169#define BADV_TIME_CTRL 0x800 2170#define BUPD_CLKO 0x1000 2171#define BFC 0x6000 2172#define BTRACKING_MODE 0x8000 2173#define BPHCMP_ENABLE 0x10000 2174#define BUPD_CLKO_LTF 0x20000 2175#define BCOM_CH_CFO 0x40000 2176#define BCSI_ESTI_MODE 0x80000 2177#define BADV_UPD_EQZ 0x100000 2178#define BUCHCFG 0x7000000 2179#define BUPDEQZ 0x8000000 2180 2181#define BRX_PESUDO_NOISE_ON 0x20000000 2182#define BRX_PESUDO_NOISE_A 0xff 2183#define BRX_PESUDO_NOISE_B 0xff00 2184#define BRX_PESUDO_NOISE_C 0xff0000 2185#define BRX_PESUDO_NOISE_D 0xff000000 2186#define BRX_PESUDO_NOISESTATE_A 0xffff 2187#define BRX_PESUDO_NOISESTATE_B 0xffff0000 2188#define BRX_PESUDO_NOISESTATE_C 0xffff 2189#define BRX_PESUDO_NOISESTATE_D 0xffff0000 2190 2191#define BZEBRA1_HSSIENABLE 0x8 2192#define BZEBRA1_TRXCONTROL 0xc00 2193#define BZEBRA1_TRXGAINSETTING 0x07f 2194#define BZEBRA1_RXCOUNTER 0xc00 2195#define BZEBRA1_TXCHANGEPUMP 0x38 2196#define BZEBRA1_RXCHANGEPUMP 0x7 2197#define BZEBRA1_CHANNEL_NUM 0xf80 2198#define BZEBRA1_TXLPFBW 0x400 2199#define BZEBRA1_RXLPFBW 0x600 2200 2201#define BRTL8256REG_MODE_CTRL1 0x100 2202#define BRTL8256REG_MODE_CTRL0 0x40 2203#define BRTL8256REG_TXLPFBW 0x18 2204#define BRTL8256REG_RXLPFBW 0x600 2205 2206#define BRTL8258_TXLPFBW 0xc 2207#define BRTL8258_RXLPFBW 0xc00 2208#define BRTL8258_RSSILPFBW 0xc0 2209 2210#define BBYTE0 0x1 2211#define BBYTE1 0x2 2212#define BBYTE2 0x4 2213#define BBYTE3 0x8 2214#define BWORD0 0x3 2215#define BWORD1 0xc 2216#define BWORD 0xf 2217 2218#define BENABLE 0x1 2219#define BDISABLE 0x0 2220 2221#define LEFT_ANTENNA 0x0 2222#define RIGHT_ANTENNA 0x1 2223 2224#define TCHECK_TXSTATUS 500 2225#define TUPDATE_RXCOUNTER 100 2226 2227#define REG_UN_USED_REGISTER 0x01bf 2228 2229/* WOL bit information */ 2230#define HAL92C_WOL_PTK_UPDATE_EVENT BIT(0) 2231#define HAL92C_WOL_GTK_UPDATE_EVENT BIT(1) 2232#define HAL92C_WOL_DISASSOC_EVENT BIT(2) 2233#define HAL92C_WOL_DEAUTH_EVENT BIT(3) 2234#define HAL92C_WOL_FW_DISCONNECT_EVENT BIT(4) 2235 2236#define WOL_REASON_PTK_UPDATE BIT(0) 2237#define WOL_REASON_GTK_UPDATE BIT(1) 2238#define WOL_REASON_DISASSOC BIT(2) 2239#define WOL_REASON_DEAUTH BIT(3) 2240#define WOL_REASON_FW_DISCONNECT BIT(4) 2241 2242#endif 2243