reg.h revision 17c9ac62812b58aacefc7336215aecbb522f6547
1/****************************************************************************** 2 * 3 * Copyright(c) 2009-2010 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * The full GNU General Public License is included in this distribution in the 19 * file called LICENSE. 20 * 21 * Contact Information: 22 * wlanfae <wlanfae@realtek.com> 23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 24 * Hsinchu 300, Taiwan. 25 * 26 * Larry Finger <Larry.Finger@lwfinger.net> 27 * 28 *****************************************************************************/ 29 30#ifndef __RTL92C_REG_H__ 31#define __RTL92C_REG_H__ 32 33#define REG_SYS_ISO_CTRL 0x0000 34#define REG_SYS_FUNC_EN 0x0002 35#define REG_APS_FSMCO 0x0004 36#define REG_SYS_CLKR 0x0008 37#define REG_9346CR 0x000A 38#define REG_EE_VPD 0x000C 39#define REG_AFE_MISC 0x0010 40#define REG_SPS0_CTRL 0x0011 41#define REG_SPS_OCP_CFG 0x0018 42#define REG_RSV_CTRL 0x001C 43#define REG_RF_CTRL 0x001F 44#define REG_LDOA15_CTRL 0x0020 45#define REG_LDOV12D_CTRL 0x0021 46#define REG_LDOHCI12_CTRL 0x0022 47#define REG_LPLDO_CTRL 0x0023 48#define REG_AFE_XTAL_CTRL 0x0024 49#define REG_AFE_PLL_CTRL 0x0028 50#define REG_EFUSE_CTRL 0x0030 51#define REG_EFUSE_TEST 0x0034 52#define REG_PWR_DATA 0x0038 53#define REG_CAL_TIMER 0x003C 54#define REG_ACLK_MON 0x003E 55#define REG_GPIO_MUXCFG 0x0040 56#define REG_GPIO_IO_SEL 0x0042 57#define REG_MAC_PINMUX_CFG 0x0043 58#define REG_GPIO_PIN_CTRL 0x0044 59#define REG_GPIO_INTM 0x0048 60#define REG_LEDCFG0 0x004C 61#define REG_LEDCFG1 0x004D 62#define REG_LEDCFG2 0x004E 63#define REG_LEDCFG3 0x004F 64#define REG_FSIMR 0x0050 65#define REG_FSISR 0x0054 66#define REG_HSIMR 0x0058 67#define REG_HSISR 0x005c 68 69/* RTL8723 WIFI/BT/GPS Multi-Function GPIO Pin Control. */ 70#define REG_GPIO_PIN_CTRL_2 0x0060 71/* RTL8723 WIFI/BT/GPS Multi-Function GPIO Select. */ 72#define REG_GPIO_IO_SEL_2 0x0062 73/* RTL8723 WIFI/BT/GPS Multi-Function control source. */ 74#define REG_MULTI_FUNC_CTRL 0x0068 75#define REG_MCUFWDL 0x0080 76 77#define REG_HMEBOX_EXT_0 0x0088 78#define REG_HMEBOX_EXT_1 0x008A 79#define REG_HMEBOX_EXT_2 0x008C 80#define REG_HMEBOX_EXT_3 0x008E 81 82#define REG_BIST_SCAN 0x00D0 83#define REG_BIST_RPT 0x00D4 84#define REG_BIST_ROM_RPT 0x00D8 85#define REG_USB_SIE_INTF 0x00E0 86#define REG_PCIE_MIO_INTF 0x00E4 87#define REG_PCIE_MIO_INTD 0x00E8 88#define REG_HPON_FSM 0x00EC 89#define REG_SYS_CFG 0x00F0 90#define REG_GPIO_OUTSTS 0x00F4 /* For RTL8723 only.*/ 91 92#define REG_CR 0x0100 93#define REG_PBP 0x0104 94#define REG_TRXDMA_CTRL 0x010C 95#define REG_TRXFF_BNDY 0x0114 96#define REG_TRXFF_STATUS 0x0118 97#define REG_RXFF_PTR 0x011C 98#define REG_HIMR 0x0120 99#define REG_HISR 0x0124 100#define REG_HIMRE 0x0128 101#define REG_HISRE 0x012C 102#define REG_CPWM 0x012F 103#define REG_FWIMR 0x0130 104#define REG_FWISR 0x0134 105#define REG_PKTBUF_DBG_CTRL 0x0140 106#define REG_PKTBUF_DBG_DATA_L 0x0144 107#define REG_PKTBUF_DBG_DATA_H 0x0148 108 109#define REG_TC0_CTRL 0x0150 110#define REG_TC1_CTRL 0x0154 111#define REG_TC2_CTRL 0x0158 112#define REG_TC3_CTRL 0x015C 113#define REG_TC4_CTRL 0x0160 114#define REG_TCUNIT_BASE 0x0164 115#define REG_MBIST_START 0x0174 116#define REG_MBIST_DONE 0x0178 117#define REG_MBIST_FAIL 0x017C 118#define REG_C2HEVT_MSG_NORMAL 0x01A0 119#define REG_C2HEVT_MSG_TEST 0x01B8 120#define REG_C2HEVT_CLEAR 0x01BF 121#define REG_MCUTST_1 0x01c0 122#define REG_FMETHR 0x01C8 123#define REG_HMETFR 0x01CC 124#define REG_HMEBOX_0 0x01D0 125#define REG_HMEBOX_1 0x01D4 126#define REG_HMEBOX_2 0x01D8 127#define REG_HMEBOX_3 0x01DC 128 129#define REG_LLT_INIT 0x01E0 130#define REG_BB_ACCEESS_CTRL 0x01E8 131#define REG_BB_ACCESS_DATA 0x01EC 132 133#define REG_RQPN 0x0200 134#define REG_FIFOPAGE 0x0204 135#define REG_TDECTRL 0x0208 136#define REG_TXDMA_OFFSET_CHK 0x020C 137#define REG_TXDMA_STATUS 0x0210 138#define REG_RQPN_NPQ 0x0214 139 140#define REG_RXDMA_AGG_PG_TH 0x0280 141#define REG_RXPKT_NUM 0x0284 142#define REG_RXDMA_STATUS 0x0288 143 144#define REG_PCIE_CTRL_REG 0x0300 145#define REG_INT_MIG 0x0304 146#define REG_BCNQ_DESA 0x0308 147#define REG_HQ_DESA 0x0310 148#define REG_MGQ_DESA 0x0318 149#define REG_VOQ_DESA 0x0320 150#define REG_VIQ_DESA 0x0328 151#define REG_BEQ_DESA 0x0330 152#define REG_BKQ_DESA 0x0338 153#define REG_RX_DESA 0x0340 154#define REG_DBI 0x0348 155#define REG_MDIO 0x0354 156#define REG_DBG_SEL 0x0360 157#define REG_PCIE_HRPWM 0x0361 158#define REG_PCIE_HCPWM 0x0363 159#define REG_UART_CTRL 0x0364 160#define REG_UART_TX_DESA 0x0370 161#define REG_UART_RX_DESA 0x0378 162 163#define REG_HDAQ_DESA_NODEF 0x0000 164#define REG_CMDQ_DESA_NODEF 0x0000 165 166#define REG_VOQ_INFORMATION 0x0400 167#define REG_VIQ_INFORMATION 0x0404 168#define REG_BEQ_INFORMATION 0x0408 169#define REG_BKQ_INFORMATION 0x040C 170#define REG_MGQ_INFORMATION 0x0410 171#define REG_HGQ_INFORMATION 0x0414 172#define REG_BCNQ_INFORMATION 0x0418 173 174#define REG_CPU_MGQ_INFORMATION 0x041C 175#define REG_FWHW_TXQ_CTRL 0x0420 176#define REG_HWSEQ_CTRL 0x0423 177#define REG_TXPKTBUF_BCNQ_BDNY 0x0424 178#define REG_TXPKTBUF_MGQ_BDNY 0x0425 179#define REG_MULTI_BCNQ_EN 0x0426 180#define REG_MULTI_BCNQ_OFFSET 0x0427 181#define REG_SPEC_SIFS 0x0428 182#define REG_RL 0x042A 183#define REG_DARFRC 0x0430 184#define REG_RARFRC 0x0438 185#define REG_RRSR 0x0440 186#define REG_ARFR0 0x0444 187#define REG_ARFR1 0x0448 188#define REG_ARFR2 0x044C 189#define REG_ARFR3 0x0450 190#define REG_AGGLEN_LMT 0x0458 191#define REG_AMPDU_MIN_SPACE 0x045C 192#define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045D 193#define REG_FAST_EDCA_CTRL 0x0460 194#define REG_RD_RESP_PKT_TH 0x0463 195#define REG_INIRTS_RATE_SEL 0x0480 196#define REG_INIDATA_RATE_SEL 0x0484 197#define REG_POWER_STATUS 0x04A4 198#define REG_POWER_STAGE1 0x04B4 199#define REG_POWER_STAGE2 0x04B8 200#define REG_PKT_LIFE_TIME 0x04C0 201#define REG_STBC_SETTING 0x04C4 202#define REG_PROT_MODE_CTRL 0x04C8 203#define REG_BAR_MODE_CTRL 0x04CC 204#define REG_RA_TRY_RATE_AGG_LMT 0x04CF 205#define REG_NQOS_SEQ 0x04DC 206#define REG_QOS_SEQ 0x04DE 207#define REG_NEED_CPU_HANDLE 0x04E0 208#define REG_PKT_LOSE_RPT 0x04E1 209#define REG_PTCL_ERR_STATUS 0x04E2 210#define REG_DUMMY 0x04FC 211 212#define REG_EDCA_VO_PARAM 0x0500 213#define REG_EDCA_VI_PARAM 0x0504 214#define REG_EDCA_BE_PARAM 0x0508 215#define REG_EDCA_BK_PARAM 0x050C 216#define REG_BCNTCFG 0x0510 217#define REG_PIFS 0x0512 218#define REG_RDG_PIFS 0x0513 219#define REG_SIFS_CTX 0x0514 220#define REG_SIFS_TRX 0x0516 221#define REG_SIFS_CCK 0x0514 222#define REG_SIFS_OFDM 0x0516 223#define REG_AGGR_BREAK_TIME 0x051A 224#define REG_SLOT 0x051B 225#define REG_TX_PTCL_CTRL 0x0520 226#define REG_TXPAUSE 0x0522 227#define REG_DIS_TXREQ_CLR 0x0523 228#define REG_RD_CTRL 0x0524 229#define REG_TBTT_PROHIBIT 0x0540 230#define REG_RD_NAV_NXT 0x0544 231#define REG_NAV_PROT_LEN 0x0546 232#define REG_BCN_CTRL 0x0550 233#define REG_USTIME_TSF 0x0551 234#define REG_MBID_NUM 0x0552 235#define REG_DUAL_TSF_RST 0x0553 236#define REG_BCN_INTERVAL 0x0554 237#define REG_MBSSID_BCN_SPACE 0x0554 238#define REG_DRVERLYINT 0x0558 239#define REG_BCNDMATIM 0x0559 240#define REG_ATIMWND 0x055A 241#define REG_BCN_MAX_ERR 0x055D 242#define REG_RXTSF_OFFSET_CCK 0x055E 243#define REG_RXTSF_OFFSET_OFDM 0x055F 244#define REG_TSFTR 0x0560 245#define REG_INIT_TSFTR 0x0564 246#define REG_PSTIMER 0x0580 247#define REG_TIMER0 0x0584 248#define REG_TIMER1 0x0588 249#define REG_ACMHWCTRL 0x05C0 250#define REG_ACMRSTCTRL 0x05C1 251#define REG_ACMAVG 0x05C2 252#define REG_VO_ADMTIME 0x05C4 253#define REG_VI_ADMTIME 0x05C6 254#define REG_BE_ADMTIME 0x05C8 255#define REG_EDCA_RANDOM_GEN 0x05CC 256#define REG_SCH_TXCMD 0x05D0 257 258#define REG_APSD_CTRL 0x0600 259#define REG_BWOPMODE 0x0603 260#define REG_TCR 0x0604 261#define REG_RCR 0x0608 262#define REG_RX_PKT_LIMIT 0x060C 263#define REG_RX_DLK_TIME 0x060D 264#define REG_RX_DRVINFO_SZ 0x060F 265 266#define REG_MACID 0x0610 267#define REG_BSSID 0x0618 268#define REG_MAR 0x0620 269#define REG_MBIDCAMCFG 0x0628 270 271#define REG_USTIME_EDCA 0x0638 272#define REG_MAC_SPEC_SIFS 0x063A 273#define REG_RESP_SIFS_CCK 0x063C 274#define REG_RESP_SIFS_OFDM 0x063E 275/* [15:8]SIFS_R2T_OFDM, [7:0]SIFS_R2T_CCK */ 276#define REG_R2T_SIFS 0x063C 277/* [15:8]SIFS_T2T_OFDM, [7:0]SIFS_T2T_CCK */ 278#define REG_T2T_SIFS 0x063E 279#define REG_ACKTO 0x0640 280#define REG_CTS2TO 0x0641 281#define REG_EIFS 0x0642 282 283#define REG_NAV_CTRL 0x0650 284#define REG_BACAMCMD 0x0654 285#define REG_BACAMCONTENT 0x0658 286#define REG_LBDLY 0x0660 287#define REG_FWDLY 0x0661 288#define REG_RXERR_RPT 0x0664 289#define REG_WMAC_TRXPTCL_CTL 0x0668 290 291#define REG_CAMCMD 0x0670 292#define REG_CAMWRITE 0x0674 293#define REG_CAMREAD 0x0678 294#define REG_CAMDBG 0x067C 295#define REG_SECCFG 0x0680 296 297#define REG_WOW_CTRL 0x0690 298#define REG_PSSTATUS 0x0691 299#define REG_PS_RX_INFO 0x0692 300#define REG_LPNAV_CTRL 0x0694 301#define REG_WKFMCAM_CMD 0x0698 302#define REG_WKFMCAM_RWD 0x069C 303#define REG_RXFLTMAP0 0x06A0 304#define REG_RXFLTMAP1 0x06A2 305#define REG_RXFLTMAP2 0x06A4 306#define REG_BCN_PSR_RPT 0x06A8 307#define REG_CALB32K_CTRL 0x06AC 308#define REG_PKT_MON_CTRL 0x06B4 309#define REG_BT_COEX_TABLE 0x06C0 310#define REG_WMAC_RESP_TXINFO 0x06D8 311 312#define REG_USB_INFO 0xFE17 313#define REG_USB_SPECIAL_OPTION 0xFE55 314#define REG_USB_DMA_AGG_TO 0xFE5B 315#define REG_USB_AGG_TO 0xFE5C 316#define REG_USB_AGG_TH 0xFE5D 317 318#define REG_TEST_USB_TXQS 0xFE48 319#define REG_TEST_SIE_VID 0xFE60 320#define REG_TEST_SIE_PID 0xFE62 321#define REG_TEST_SIE_OPTIONAL 0xFE64 322#define REG_TEST_SIE_CHIRP_K 0xFE65 323#define REG_TEST_SIE_PHY 0xFE66 324#define REG_TEST_SIE_MAC_ADDR 0xFE70 325#define REG_TEST_SIE_STRING 0xFE80 326 327#define REG_NORMAL_SIE_VID 0xFE60 328#define REG_NORMAL_SIE_PID 0xFE62 329#define REG_NORMAL_SIE_OPTIONAL 0xFE64 330#define REG_NORMAL_SIE_EP 0xFE65 331#define REG_NORMAL_SIE_PHY 0xFE68 332#define REG_NORMAL_SIE_MAC_ADDR 0xFE70 333#define REG_NORMAL_SIE_STRING 0xFE80 334 335#define CR9346 REG_9346CR 336#define MSR (REG_CR + 2) 337#define ISR REG_HISR 338#define TSFR REG_TSFTR 339 340#define MACIDR0 REG_MACID 341#define MACIDR4 (REG_MACID + 4) 342 343#define PBP REG_PBP 344 345#define IDR0 MACIDR0 346#define IDR4 MACIDR4 347 348#define UNUSED_REGISTER 0x1BF 349#define DCAM UNUSED_REGISTER 350#define PSR UNUSED_REGISTER 351#define BBADDR UNUSED_REGISTER 352#define PHYDATAR UNUSED_REGISTER 353 354#define INVALID_BBRF_VALUE 0x12345678 355 356#define MAX_MSS_DENSITY_2T 0x13 357#define MAX_MSS_DENSITY_1T 0x0A 358 359#define CMDEEPROM_EN BIT(5) 360#define CMDEEPROM_SEL BIT(4) 361#define CMD9346CR_9356SEL BIT(4) 362#define AUTOLOAD_EEPROM (CMDEEPROM_EN|CMDEEPROM_SEL) 363#define AUTOLOAD_EFUSE CMDEEPROM_EN 364 365#define GPIOSEL_GPIO 0 366#define GPIOSEL_ENBT BIT(5) 367 368#define GPIO_IN REG_GPIO_PIN_CTRL 369#define GPIO_OUT (REG_GPIO_PIN_CTRL+1) 370#define GPIO_IO_SEL (REG_GPIO_PIN_CTRL+2) 371#define GPIO_MOD (REG_GPIO_PIN_CTRL+3) 372 373#define MSR_NOLINK 0x00 374#define MSR_ADHOC 0x01 375#define MSR_INFRA 0x02 376#define MSR_AP 0x03 377 378#define RRSR_RSC_OFFSET 21 379#define RRSR_SHORT_OFFSET 23 380#define RRSR_RSC_BW_40M 0x600000 381#define RRSR_RSC_UPSUBCHNL 0x400000 382#define RRSR_RSC_LOWSUBCHNL 0x200000 383#define RRSR_SHORT 0x800000 384#define RRSR_1M BIT(0) 385#define RRSR_2M BIT(1) 386#define RRSR_5_5M BIT(2) 387#define RRSR_11M BIT(3) 388#define RRSR_6M BIT(4) 389#define RRSR_9M BIT(5) 390#define RRSR_12M BIT(6) 391#define RRSR_18M BIT(7) 392#define RRSR_24M BIT(8) 393#define RRSR_36M BIT(9) 394#define RRSR_48M BIT(10) 395#define RRSR_54M BIT(11) 396#define RRSR_MCS0 BIT(12) 397#define RRSR_MCS1 BIT(13) 398#define RRSR_MCS2 BIT(14) 399#define RRSR_MCS3 BIT(15) 400#define RRSR_MCS4 BIT(16) 401#define RRSR_MCS5 BIT(17) 402#define RRSR_MCS6 BIT(18) 403#define RRSR_MCS7 BIT(19) 404#define BRSR_ACKSHORTPMB BIT(23) 405 406#define RATR_1M 0x00000001 407#define RATR_2M 0x00000002 408#define RATR_55M 0x00000004 409#define RATR_11M 0x00000008 410#define RATR_6M 0x00000010 411#define RATR_9M 0x00000020 412#define RATR_12M 0x00000040 413#define RATR_18M 0x00000080 414#define RATR_24M 0x00000100 415#define RATR_36M 0x00000200 416#define RATR_48M 0x00000400 417#define RATR_54M 0x00000800 418#define RATR_MCS0 0x00001000 419#define RATR_MCS1 0x00002000 420#define RATR_MCS2 0x00004000 421#define RATR_MCS3 0x00008000 422#define RATR_MCS4 0x00010000 423#define RATR_MCS5 0x00020000 424#define RATR_MCS6 0x00040000 425#define RATR_MCS7 0x00080000 426#define RATR_MCS8 0x00100000 427#define RATR_MCS9 0x00200000 428#define RATR_MCS10 0x00400000 429#define RATR_MCS11 0x00800000 430#define RATR_MCS12 0x01000000 431#define RATR_MCS13 0x02000000 432#define RATR_MCS14 0x04000000 433#define RATR_MCS15 0x08000000 434 435#define RATE_1M BIT(0) 436#define RATE_2M BIT(1) 437#define RATE_5_5M BIT(2) 438#define RATE_11M BIT(3) 439#define RATE_6M BIT(4) 440#define RATE_9M BIT(5) 441#define RATE_12M BIT(6) 442#define RATE_18M BIT(7) 443#define RATE_24M BIT(8) 444#define RATE_36M BIT(9) 445#define RATE_48M BIT(10) 446#define RATE_54M BIT(11) 447#define RATE_MCS0 BIT(12) 448#define RATE_MCS1 BIT(13) 449#define RATE_MCS2 BIT(14) 450#define RATE_MCS3 BIT(15) 451#define RATE_MCS4 BIT(16) 452#define RATE_MCS5 BIT(17) 453#define RATE_MCS6 BIT(18) 454#define RATE_MCS7 BIT(19) 455#define RATE_MCS8 BIT(20) 456#define RATE_MCS9 BIT(21) 457#define RATE_MCS10 BIT(22) 458#define RATE_MCS11 BIT(23) 459#define RATE_MCS12 BIT(24) 460#define RATE_MCS13 BIT(25) 461#define RATE_MCS14 BIT(26) 462#define RATE_MCS15 BIT(27) 463 464#define RATE_ALL_CCK (RATR_1M | RATR_2M | RATR_55M | RATR_11M) 465#define RATE_ALL_OFDM_AG (RATR_6M | RATR_9M | RATR_12M | RATR_18M \ 466 | RATR_24M | RATR_36M | RATR_48M | RATR_54M) 467#define RATE_ALL_OFDM_1SS (RATR_MCS0 | RATR_MCS1 | RATR_MCS2 | \ 468 RATR_MCS3 | RATR_MCS4 | RATR_MCS5 | \ 469 RATR_MCS6 | RATR_MCS7) 470#define RATE_ALL_OFDM_2SS (RATR_MCS8 | RATR_MCS9 | RATR_MCS10 | \ 471 RATR_MCS11 | RATR_MCS12 | RATR_MCS13 | \ 472 RATR_MCS14 | RATR_MCS15) 473 474#define BW_OPMODE_20MHZ BIT(2) 475#define BW_OPMODE_5G BIT(1) 476#define BW_OPMODE_11J BIT(0) 477 478#define CAM_VALID BIT(15) 479#define CAM_NOTVALID 0x0000 480#define CAM_USEDK BIT(5) 481 482#define CAM_NONE 0x0 483#define CAM_WEP40 0x01 484#define CAM_TKIP 0x02 485#define CAM_AES 0x04 486#define CAM_WEP104 0x05 487 488#define TOTAL_CAM_ENTRY 32 489#define HALF_CAM_ENTRY 16 490 491#define CAM_WRITE BIT(16) 492#define CAM_READ 0x00000000 493#define CAM_POLLINIG BIT(31) 494 495#define SCR_USEDK 0x01 496#define SCR_TXSEC_ENABLE 0x02 497#define SCR_RXSEC_ENABLE 0x04 498 499#define WOW_PMEN BIT(0) 500#define WOW_WOMEN BIT(1) 501#define WOW_MAGIC BIT(2) 502#define WOW_UWF BIT(3) 503 504#define IMR8190_DISABLED 0x0 505#define IMR_BCNDMAINT6 BIT(31) 506#define IMR_BCNDMAINT5 BIT(30) 507#define IMR_BCNDMAINT4 BIT(29) 508#define IMR_BCNDMAINT3 BIT(28) 509#define IMR_BCNDMAINT2 BIT(27) 510#define IMR_BCNDMAINT1 BIT(26) 511#define IMR_BCNDOK8 BIT(25) 512#define IMR_BCNDOK7 BIT(24) 513#define IMR_BCNDOK6 BIT(23) 514#define IMR_BCNDOK5 BIT(22) 515#define IMR_BCNDOK4 BIT(21) 516#define IMR_BCNDOK3 BIT(20) 517#define IMR_BCNDOK2 BIT(19) 518#define IMR_BCNDOK1 BIT(18) 519#define IMR_TIMEOUT2 BIT(17) 520#define IMR_TIMEOUT1 BIT(16) 521#define IMR_TXFOVW BIT(15) 522#define IMR_PSTIMEOUT BIT(14) 523#define IMR_BCNINT BIT(13) 524#define IMR_RXFOVW BIT(12) 525#define IMR_RDU BIT(11) 526#define IMR_ATIMEND BIT(10) 527#define IMR_BDOK BIT(9) 528#define IMR_HIGHDOK BIT(8) 529#define IMR_TBDOK BIT(7) 530#define IMR_MGNTDOK BIT(6) 531#define IMR_TBDER BIT(5) 532#define IMR_BKDOK BIT(4) 533#define IMR_BEDOK BIT(3) 534#define IMR_VIDOK BIT(2) 535#define IMR_VODOK BIT(1) 536#define IMR_ROK BIT(0) 537 538#define IMR_TXERR BIT(11) 539#define IMR_RXERR BIT(10) 540#define IMR_C2HCMD BIT(9) 541#define IMR_CPWM BIT(8) 542#define IMR_OCPINT BIT(1) 543#define IMR_WLANOFF BIT(0) 544 545#define HWSET_MAX_SIZE 128 546 547#define EEPROM_DEFAULT_TSSI 0x0 548#define EEPROM_DEFAULT_TXPOWERDIFF 0x0 549#define EEPROM_DEFAULT_CRYSTALCAP 0x5 550#define EEPROM_DEFAULT_BOARDTYPE 0x02 551#define EEPROM_DEFAULT_TXPOWER 0x1010 552#define EEPROM_DEFAULT_HT2T_TXPWR 0x10 553 554#define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x3 555#define EEPROM_DEFAULT_THERMALMETER 0x12 556#define EEPROM_DEFAULT_ANTTXPOWERDIFF 0x0 557#define EEPROM_DEFAULT_TXPWDIFF_CRYSTALCAP 0x5 558#define EEPROM_DEFAULT_TXPOWERLEVEL 0x22 559#define EEPROM_DEFAULT_HT40_2SDIFF 0x0 560#define EEPROM_DEFAULT_HT20_DIFF 2 561#define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x3 562#define EEPROM_DEFAULT_HT40_PWRMAXOFFSET 0 563#define EEPROM_DEFAULT_HT20_PWRMAXOFFSET 0 564 565#define RF_OPTION1 0x79 566#define RF_OPTION2 0x7A 567#define RF_OPTION3 0x7B 568#define RF_OPTION4 0x7C 569 570#define EEPROM_DEFAULT_PID 0x1234 571#define EEPROM_DEFAULT_VID 0x5678 572#define EEPROM_DEFAULT_CUSTOMERID 0xAB 573#define EEPROM_DEFAULT_SUBCUSTOMERID 0xCD 574#define EEPROM_DEFAULT_VERSION 0 575 576#define EEPROM_CHANNEL_PLAN_FCC 0x0 577#define EEPROM_CHANNEL_PLAN_IC 0x1 578#define EEPROM_CHANNEL_PLAN_ETSI 0x2 579#define EEPROM_CHANNEL_PLAN_SPAIN 0x3 580#define EEPROM_CHANNEL_PLAN_FRANCE 0x4 581#define EEPROM_CHANNEL_PLAN_MKK 0x5 582#define EEPROM_CHANNEL_PLAN_MKK1 0x6 583#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7 584#define EEPROM_CHANNEL_PLAN_TELEC 0x8 585#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9 586#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA 587#define EEPROM_CHANNEL_PLAN_NCC 0xB 588#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80 589 590#define EEPROM_CID_DEFAULT 0x0 591#define EEPROM_CID_TOSHIBA 0x4 592#define EEPROM_CID_CCX 0x10 593#define EEPROM_CID_QMI 0x0D 594#define EEPROM_CID_WHQL 0xFE 595 596#define RTL8192_EEPROM_ID 0x8129 597 598#define RTL8190_EEPROM_ID 0x8129 599#define EEPROM_HPON 0x02 600#define EEPROM_CLK 0x06 601#define EEPROM_TESTR 0x08 602 603#define EEPROM_VID 0x0A 604#define EEPROM_DID 0x0C 605#define EEPROM_SVID 0x0E 606#define EEPROM_SMID 0x10 607 608#define EEPROM_MAC_ADDR 0x16 609 610#define EEPROM_CCK_TX_PWR_INX 0x5A 611#define EEPROM_HT40_1S_TX_PWR_INX 0x60 612#define EEPROM_HT40_2S_TX_PWR_INX_DIFF 0x66 613#define EEPROM_HT20_TX_PWR_INX_DIFF 0x69 614#define EEPROM_OFDM_TX_PWR_INX_DIFF 0x6C 615#define EEPROM_HT40_MAX_PWR_OFFSET 0x6F 616#define EEPROM_HT20_MAX_PWR_OFFSET 0x72 617 618#define EEPROM_TSSI_A 0x76 619#define EEPROM_TSSI_B 0x77 620#define EEPROM_THERMAL_METER 0x78 621#define EEPROM_XTAL_K 0x78 622#define EEPROM_RF_OPT1 0x79 623#define EEPROM_RF_OPT2 0x7A 624#define EEPROM_RF_OPT3 0x7B 625#define EEPROM_RF_OPT4 0x7C 626#define EEPROM_CHANNEL_PLAN 0x7D 627#define EEPROM_VERSION 0x7E 628#define EEPROM_CUSTOMER_ID 0x7F 629 630#define EEPROM_PWRDIFF 0x54 631 632#define EEPROM_TXPOWERCCK 0x5A 633#define EEPROM_TXPOWERHT40_1S 0x60 634#define EEPROM_TXPOWERHT40_2SDIFF 0x66 635#define EEPROM_TXPOWERHT20DIFF 0x69 636#define EEPROM_TXPOWER_OFDMDIFF 0x6C 637 638#define EEPROM_TXPWR_GROUP 0x6F 639 640#define EEPROM_TSSI_A 0x76 641#define EEPROM_TSSI_B 0x77 642#define EEPROM_THERMAL_METER 0x78 643 644#define EEPROM_CHANNELPLAN 0x75 645 646#define RF_OPTION1 0x79 647#define RF_OPTION2 0x7A 648#define RF_OPTION3 0x7B 649#define RF_OPTION4 0x7C 650 651#define STOPBECON BIT(6) 652#define STOPHIGHT BIT(5) 653#define STOPMGT BIT(4) 654#define STOPVO BIT(3) 655#define STOPVI BIT(2) 656#define STOPBE BIT(1) 657#define STOPBK BIT(0) 658 659#define RCR_APP_FCS BIT(31) 660#define RCR_APP_MIC BIT(30) 661#define RCR_APP_ICV BIT(29) 662#define RCR_APP_PHYSTS BIT(28) 663#define RCR_APP_PHYST_RXFF BIT(28) 664#define RCR_APP_BA_SSN BIT(27) 665#define RCR_ENMBID BIT(24) 666#define RCR_LSIGEN BIT(23) 667#define RCR_MFBEN BIT(22) 668#define RCR_HTC_LOC_CTRL BIT(14) 669#define RCR_AMF BIT(13) 670#define RCR_ACF BIT(12) 671#define RCR_ADF BIT(11) 672#define RCR_AICV BIT(9) 673#define RCR_ACRC32 BIT(8) 674#define RCR_CBSSID_BCN BIT(7) 675#define RCR_CBSSID_DATA BIT(6) 676#define RCR_CBSSID RCR_CBSSID_DATA 677#define RCR_APWRMGT BIT(5) 678#define RCR_ADD3 BIT(4) 679#define RCR_AB BIT(3) 680#define RCR_AM BIT(2) 681#define RCR_APM BIT(1) 682#define RCR_AAP BIT(0) 683#define RCR_MXDMA_OFFSET 8 684#define RCR_FIFO_OFFSET 13 685 686#define RSV_CTRL 0x001C 687#define RD_CTRL 0x0524 688 689#define REG_USB_INFO 0xFE17 690#define REG_USB_SPECIAL_OPTION 0xFE55 691#define REG_USB_DMA_AGG_TO 0xFE5B 692#define REG_USB_AGG_TO 0xFE5C 693#define REG_USB_AGG_TH 0xFE5D 694 695#define REG_USB_VID 0xFE60 696#define REG_USB_PID 0xFE62 697#define REG_USB_OPTIONAL 0xFE64 698#define REG_USB_CHIRP_K 0xFE65 699#define REG_USB_PHY 0xFE66 700#define REG_USB_MAC_ADDR 0xFE70 701#define REG_USB_HRPWM 0xFE58 702#define REG_USB_HCPWM 0xFE57 703 704#define SW18_FPWM BIT(3) 705 706#define ISO_MD2PP BIT(0) 707#define ISO_UA2USB BIT(1) 708#define ISO_UD2CORE BIT(2) 709#define ISO_PA2PCIE BIT(3) 710#define ISO_PD2CORE BIT(4) 711#define ISO_IP2MAC BIT(5) 712#define ISO_DIOP BIT(6) 713#define ISO_DIOE BIT(7) 714#define ISO_EB2CORE BIT(8) 715#define ISO_DIOR BIT(9) 716 717#define PWC_EV25V BIT(14) 718#define PWC_EV12V BIT(15) 719 720#define FEN_BBRSTB BIT(0) 721#define FEN_BB_GLB_RSTn BIT(1) 722#define FEN_USBA BIT(2) 723#define FEN_UPLL BIT(3) 724#define FEN_USBD BIT(4) 725#define FEN_DIO_PCIE BIT(5) 726#define FEN_PCIEA BIT(6) 727#define FEN_PPLL BIT(7) 728#define FEN_PCIED BIT(8) 729#define FEN_DIOE BIT(9) 730#define FEN_CPUEN BIT(10) 731#define FEN_DCORE BIT(11) 732#define FEN_ELDR BIT(12) 733#define FEN_DIO_RF BIT(13) 734#define FEN_HWPDN BIT(14) 735#define FEN_MREGEN BIT(15) 736 737#define PFM_LDALL BIT(0) 738#define PFM_ALDN BIT(1) 739#define PFM_LDKP BIT(2) 740#define PFM_WOWL BIT(3) 741#define EnPDN BIT(4) 742#define PDN_PL BIT(5) 743#define APFM_ONMAC BIT(8) 744#define APFM_OFF BIT(9) 745#define APFM_RSM BIT(10) 746#define AFSM_HSUS BIT(11) 747#define AFSM_PCIE BIT(12) 748#define APDM_MAC BIT(13) 749#define APDM_HOST BIT(14) 750#define APDM_HPDN BIT(15) 751#define RDY_MACON BIT(16) 752#define SUS_HOST BIT(17) 753#define ROP_ALD BIT(20) 754#define ROP_PWR BIT(21) 755#define ROP_SPS BIT(22) 756#define SOP_MRST BIT(25) 757#define SOP_FUSE BIT(26) 758#define SOP_ABG BIT(27) 759#define SOP_AMB BIT(28) 760#define SOP_RCK BIT(29) 761#define SOP_A8M BIT(30) 762#define XOP_BTCK BIT(31) 763 764#define ANAD16V_EN BIT(0) 765#define ANA8M BIT(1) 766#define MACSLP BIT(4) 767#define LOADER_CLK_EN BIT(5) 768#define _80M_SSC_DIS BIT(7) 769#define _80M_SSC_EN_HO BIT(8) 770#define PHY_SSC_RSTB BIT(9) 771#define SEC_CLK_EN BIT(10) 772#define MAC_CLK_EN BIT(11) 773#define SYS_CLK_EN BIT(12) 774#define RING_CLK_EN BIT(13) 775 776#define BOOT_FROM_EEPROM BIT(4) 777#define EEPROM_EN BIT(5) 778#define EEPROMSEL BOOT_FROM_EEPROM 779 780#define AFE_BGEN BIT(0) 781#define AFE_MBEN BIT(1) 782#define MAC_ID_EN BIT(7) 783 784#define WLOCK_ALL BIT(0) 785#define WLOCK_00 BIT(1) 786#define WLOCK_04 BIT(2) 787#define WLOCK_08 BIT(3) 788#define WLOCK_40 BIT(4) 789#define R_DIS_PRST_0 BIT(5) 790#define R_DIS_PRST_1 BIT(6) 791#define LOCK_ALL_EN BIT(7) 792 793#define RF_EN BIT(0) 794#define RF_RSTB BIT(1) 795#define RF_SDMRSTB BIT(2) 796 797#define LDA15_EN BIT(0) 798#define LDA15_STBY BIT(1) 799#define LDA15_OBUF BIT(2) 800#define LDA15_REG_VOS BIT(3) 801#define _LDA15_VOADJ(x) (((x) & 0x7) << 4) 802 803#define LDV12_EN BIT(0) 804#define LDV12_SDBY BIT(1) 805#define LPLDO_HSM BIT(2) 806#define LPLDO_LSM_DIS BIT(3) 807#define _LDV12_VADJ(x) (((x) & 0xF) << 4) 808 809#define XTAL_EN BIT(0) 810#define XTAL_BSEL BIT(1) 811#define _XTAL_BOSC(x) (((x) & 0x3) << 2) 812#define _XTAL_CADJ(x) (((x) & 0xF) << 4) 813#define XTAL_GATE_USB BIT(8) 814#define _XTAL_USB_DRV(x) (((x) & 0x3) << 9) 815#define XTAL_GATE_AFE BIT(11) 816#define _XTAL_AFE_DRV(x) (((x) & 0x3) << 12) 817#define XTAL_RF_GATE BIT(14) 818#define _XTAL_RF_DRV(x) (((x) & 0x3) << 15) 819#define XTAL_GATE_DIG BIT(17) 820#define _XTAL_DIG_DRV(x) (((x) & 0x3) << 18) 821#define XTAL_BT_GATE BIT(20) 822#define _XTAL_BT_DRV(x) (((x) & 0x3) << 21) 823#define _XTAL_GPIO(x) (((x) & 0x7) << 23) 824 825#define CKDLY_AFE BIT(26) 826#define CKDLY_USB BIT(27) 827#define CKDLY_DIG BIT(28) 828#define CKDLY_BT BIT(29) 829 830#define APLL_EN BIT(0) 831#define APLL_320_EN BIT(1) 832#define APLL_FREF_SEL BIT(2) 833#define APLL_EDGE_SEL BIT(3) 834#define APLL_WDOGB BIT(4) 835#define APLL_LPFEN BIT(5) 836 837#define APLL_REF_CLK_13MHZ 0x1 838#define APLL_REF_CLK_19_2MHZ 0x2 839#define APLL_REF_CLK_20MHZ 0x3 840#define APLL_REF_CLK_25MHZ 0x4 841#define APLL_REF_CLK_26MHZ 0x5 842#define APLL_REF_CLK_38_4MHZ 0x6 843#define APLL_REF_CLK_40MHZ 0x7 844 845#define APLL_320EN BIT(14) 846#define APLL_80EN BIT(15) 847#define APLL_1MEN BIT(24) 848 849#define ALD_EN BIT(18) 850#define EF_PD BIT(19) 851#define EF_FLAG BIT(31) 852 853#define EF_TRPT BIT(7) 854#define LDOE25_EN BIT(31) 855 856#define RSM_EN BIT(0) 857#define Timer_EN BIT(4) 858 859#define TRSW0EN BIT(2) 860#define TRSW1EN BIT(3) 861#define EROM_EN BIT(4) 862#define EnBT BIT(5) 863#define EnUart BIT(8) 864#define Uart_910 BIT(9) 865#define EnPMAC BIT(10) 866#define SIC_SWRST BIT(11) 867#define EnSIC BIT(12) 868#define SIC_23 BIT(13) 869#define EnHDP BIT(14) 870#define SIC_LBK BIT(15) 871 872#define LED0PL BIT(4) 873#define LED1PL BIT(12) 874#define LED0DIS BIT(7) 875 876#define MCUFWDL_EN BIT(0) 877#define MCUFWDL_RDY BIT(1) 878#define FWDL_ChkSum_rpt BIT(2) 879#define MACINI_RDY BIT(3) 880#define BBINI_RDY BIT(4) 881#define RFINI_RDY BIT(5) 882#define WINTINI_RDY BIT(6) 883#define CPRST BIT(23) 884 885#define XCLK_VLD BIT(0) 886#define ACLK_VLD BIT(1) 887#define UCLK_VLD BIT(2) 888#define PCLK_VLD BIT(3) 889#define PCIRSTB BIT(4) 890#define V15_VLD BIT(5) 891#define TRP_B15V_EN BIT(7) 892#define SIC_IDLE BIT(8) 893#define BD_MAC2 BIT(9) 894#define BD_MAC1 BIT(10) 895#define IC_MACPHY_MODE BIT(11) 896#define BT_FUNC BIT(16) 897#define VENDOR_ID BIT(19) 898#define PAD_HWPD_IDN BIT(22) 899#define TRP_VAUX_EN BIT(23) 900#define TRP_BT_EN BIT(24) 901#define BD_PKG_SEL BIT(25) 902#define BD_HCI_SEL BIT(26) 903#define TYPE_ID BIT(27) 904 905/* REG_GPIO_OUTSTS (For RTL8723 only) */ 906#define EFS_HCI_SEL (BIT(0)|BIT(1)) 907#define PAD_HCI_SEL (BIT(2)|BIT(3)) 908#define HCI_SEL (BIT(4)|BIT(5)) 909#define PKG_SEL_HCI BIT(6) 910#define FEN_GPS BIT(7) 911#define FEN_BT BIT(8) 912#define FEN_WL BIT(9) 913#define FEN_PCI BIT(10) 914#define FEN_USB BIT(11) 915#define BTRF_HWPDN_N BIT(12) 916#define WLRF_HWPDN_N BIT(13) 917#define PDN_BT_N BIT(14) 918#define PDN_GPS_N BIT(15) 919#define BT_CTL_HWPDN BIT(16) 920#define GPS_CTL_HWPDN BIT(17) 921#define PPHY_SUSB BIT(20) 922#define UPHY_SUSB BIT(21) 923#define PCI_SUSEN BIT(22) 924#define USB_SUSEN BIT(23) 925#define RF_RL_ID (BIT(31) | BIT(30) | BIT(29) | BIT(28)) 926 927#define CHIP_VER_RTL_MASK 0xF000 928#define CHIP_VER_RTL_SHIFT 12 929 930#define REG_LBMODE (REG_CR + 3) 931 932#define HCI_TXDMA_EN BIT(0) 933#define HCI_RXDMA_EN BIT(1) 934#define TXDMA_EN BIT(2) 935#define RXDMA_EN BIT(3) 936#define PROTOCOL_EN BIT(4) 937#define SCHEDULE_EN BIT(5) 938#define MACTXEN BIT(6) 939#define MACRXEN BIT(7) 940#define ENSWBCN BIT(8) 941#define ENSEC BIT(9) 942 943#define _NETTYPE(x) (((x) & 0x3) << 16) 944#define MASK_NETTYPE 0x30000 945#define NT_NO_LINK 0x0 946#define NT_LINK_AD_HOC 0x1 947#define NT_LINK_AP 0x2 948#define NT_AS_AP 0x3 949 950#define _LBMODE(x) (((x) & 0xF) << 24) 951#define MASK_LBMODE 0xF000000 952#define LOOPBACK_NORMAL 0x0 953#define LOOPBACK_IMMEDIATELY 0xB 954#define LOOPBACK_MAC_DELAY 0x3 955#define LOOPBACK_PHY 0x1 956#define LOOPBACK_DMA 0x7 957 958#define GET_RX_PAGE_SIZE(value) ((value) & 0xF) 959#define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4) 960#define _PSRX_MASK 0xF 961#define _PSTX_MASK 0xF0 962#define _PSRX(x) (x) 963#define _PSTX(x) ((x) << 4) 964 965#define PBP_64 0x0 966#define PBP_128 0x1 967#define PBP_256 0x2 968#define PBP_512 0x3 969#define PBP_1024 0x4 970 971#define RXDMA_ARBBW_EN BIT(0) 972#define RXSHFT_EN BIT(1) 973#define RXDMA_AGG_EN BIT(2) 974#define QS_VO_QUEUE BIT(8) 975#define QS_VI_QUEUE BIT(9) 976#define QS_BE_QUEUE BIT(10) 977#define QS_BK_QUEUE BIT(11) 978#define QS_MANAGER_QUEUE BIT(12) 979#define QS_HIGH_QUEUE BIT(13) 980 981#define HQSEL_VOQ BIT(0) 982#define HQSEL_VIQ BIT(1) 983#define HQSEL_BEQ BIT(2) 984#define HQSEL_BKQ BIT(3) 985#define HQSEL_MGTQ BIT(4) 986#define HQSEL_HIQ BIT(5) 987 988#define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14) 989#define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12) 990#define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10) 991#define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8) 992#define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6) 993#define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4) 994 995#define QUEUE_LOW 1 996#define QUEUE_NORMAL 2 997#define QUEUE_HIGH 3 998 999#define _LLT_NO_ACTIVE 0x0 1000#define _LLT_WRITE_ACCESS 0x1 1001#define _LLT_READ_ACCESS 0x2 1002 1003#define _LLT_INIT_DATA(x) ((x) & 0xFF) 1004#define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8) 1005#define _LLT_OP(x) (((x) & 0x3) << 30) 1006#define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3) 1007 1008#define BB_WRITE_READ_MASK (BIT(31) | BIT(30)) 1009#define BB_WRITE_EN BIT(30) 1010#define BB_READ_EN BIT(31) 1011 1012#define _HPQ(x) ((x) & 0xFF) 1013#define _LPQ(x) (((x) & 0xFF) << 8) 1014#define _PUBQ(x) (((x) & 0xFF) << 16) 1015#define _NPQ(x) ((x) & 0xFF) 1016 1017#define HPQ_PUBLIC_DIS BIT(24) 1018#define LPQ_PUBLIC_DIS BIT(25) 1019#define LD_RQPN BIT(31) 1020 1021#define BCN_VALID BIT(16) 1022#define BCN_HEAD(x) (((x) & 0xFF) << 8) 1023#define BCN_HEAD_MASK 0xFF00 1024 1025#define BLK_DESC_NUM_SHIFT 4 1026#define BLK_DESC_NUM_MASK 0xF 1027 1028#define DROP_DATA_EN BIT(9) 1029 1030#define EN_AMPDU_RTY_NEW BIT(7) 1031 1032#define _INIRTSMCS_SEL(x) ((x) & 0x3F) 1033 1034#define _SPEC_SIFS_CCK(x) ((x) & 0xFF) 1035#define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8) 1036 1037#define RATE_REG_BITMAP_ALL 0xFFFFF 1038 1039#define _RRSC_BITMAP(x) ((x) & 0xFFFFF) 1040 1041#define _RRSR_RSC(x) (((x) & 0x3) << 21) 1042#define RRSR_RSC_RESERVED 0x0 1043#define RRSR_RSC_UPPER_SUBCHANNEL 0x1 1044#define RRSR_RSC_LOWER_SUBCHANNEL 0x2 1045#define RRSR_RSC_DUPLICATE_MODE 0x3 1046 1047#define USE_SHORT_G1 BIT(20) 1048 1049#define _AGGLMT_MCS0(x) ((x) & 0xF) 1050#define _AGGLMT_MCS1(x) (((x) & 0xF) << 4) 1051#define _AGGLMT_MCS2(x) (((x) & 0xF) << 8) 1052#define _AGGLMT_MCS3(x) (((x) & 0xF) << 12) 1053#define _AGGLMT_MCS4(x) (((x) & 0xF) << 16) 1054#define _AGGLMT_MCS5(x) (((x) & 0xF) << 20) 1055#define _AGGLMT_MCS6(x) (((x) & 0xF) << 24) 1056#define _AGGLMT_MCS7(x) (((x) & 0xF) << 28) 1057 1058#define RETRY_LIMIT_SHORT_SHIFT 8 1059#define RETRY_LIMIT_LONG_SHIFT 0 1060 1061#define _DARF_RC1(x) ((x) & 0x1F) 1062#define _DARF_RC2(x) (((x) & 0x1F) << 8) 1063#define _DARF_RC3(x) (((x) & 0x1F) << 16) 1064#define _DARF_RC4(x) (((x) & 0x1F) << 24) 1065#define _DARF_RC5(x) ((x) & 0x1F) 1066#define _DARF_RC6(x) (((x) & 0x1F) << 8) 1067#define _DARF_RC7(x) (((x) & 0x1F) << 16) 1068#define _DARF_RC8(x) (((x) & 0x1F) << 24) 1069 1070#define _RARF_RC1(x) ((x) & 0x1F) 1071#define _RARF_RC2(x) (((x) & 0x1F) << 8) 1072#define _RARF_RC3(x) (((x) & 0x1F) << 16) 1073#define _RARF_RC4(x) (((x) & 0x1F) << 24) 1074#define _RARF_RC5(x) ((x) & 0x1F) 1075#define _RARF_RC6(x) (((x) & 0x1F) << 8) 1076#define _RARF_RC7(x) (((x) & 0x1F) << 16) 1077#define _RARF_RC8(x) (((x) & 0x1F) << 24) 1078 1079#define AC_PARAM_TXOP_OFFSET 16 1080#define AC_PARAM_ECW_MAX_OFFSET 12 1081#define AC_PARAM_ECW_MIN_OFFSET 8 1082#define AC_PARAM_AIFS_OFFSET 0 1083 1084#define _AIFS(x) (x) 1085#define _ECW_MAX_MIN(x) ((x) << 8) 1086#define _TXOP_LIMIT(x) ((x) << 16) 1087 1088#define _BCNIFS(x) ((x) & 0xFF) 1089#define _BCNECW(x) ((((x) & 0xF)) << 8) 1090 1091#define _LRL(x) ((x) & 0x3F) 1092#define _SRL(x) (((x) & 0x3F) << 8) 1093 1094#define _SIFS_CCK_CTX(x) ((x) & 0xFF) 1095#define _SIFS_CCK_TRX(x) (((x) & 0xFF) << 8); 1096 1097#define _SIFS_OFDM_CTX(x) ((x) & 0xFF) 1098#define _SIFS_OFDM_TRX(x) (((x) & 0xFF) << 8); 1099 1100#define _TBTT_PROHIBIT_HOLD(x) (((x) & 0xFF) << 8) 1101 1102#define DIS_EDCA_CNT_DWN BIT(11) 1103 1104#define EN_MBSSID BIT(1) 1105#define EN_TXBCN_RPT BIT(2) 1106#define EN_BCN_FUNCTION BIT(3) 1107 1108#define TSFTR_RST BIT(0) 1109#define TSFTR1_RST BIT(1) 1110 1111#define STOP_BCNQ BIT(6) 1112 1113#define DIS_TSF_UDT0_NORMAL_CHIP BIT(4) 1114#define DIS_TSF_UDT0_TEST_CHIP BIT(5) 1115 1116#define AcmHw_HwEn BIT(0) 1117#define AcmHw_BeqEn BIT(1) 1118#define AcmHw_ViqEn BIT(2) 1119#define AcmHw_VoqEn BIT(3) 1120#define AcmHw_BeqStatus BIT(4) 1121#define AcmHw_ViqStatus BIT(5) 1122#define AcmHw_VoqStatus BIT(6) 1123 1124#define APSDOFF BIT(6) 1125#define APSDOFF_STATUS BIT(7) 1126 1127#define BW_20MHZ BIT(2) 1128 1129#define RATE_BITMAP_ALL 0xFFFFF 1130 1131#define RATE_RRSR_CCK_ONLY_1M 0xFFFF1 1132 1133#define TSFRST BIT(0) 1134#define DIS_GCLK BIT(1) 1135#define PAD_SEL BIT(2) 1136#define PWR_ST BIT(6) 1137#define PWRBIT_OW_EN BIT(7) 1138#define ACRC BIT(8) 1139#define CFENDFORM BIT(9) 1140#define ICV BIT(10) 1141 1142#define AAP BIT(0) 1143#define APM BIT(1) 1144#define AM BIT(2) 1145#define AB BIT(3) 1146#define ADD3 BIT(4) 1147#define APWRMGT BIT(5) 1148#define CBSSID BIT(6) 1149#define CBSSID_DATA BIT(6) 1150#define CBSSID_BCN BIT(7) 1151#define ACRC32 BIT(8) 1152#define AICV BIT(9) 1153#define ADF BIT(11) 1154#define ACF BIT(12) 1155#define AMF BIT(13) 1156#define HTC_LOC_CTRL BIT(14) 1157#define UC_DATA_EN BIT(16) 1158#define BM_DATA_EN BIT(17) 1159#define MFBEN BIT(22) 1160#define LSIGEN BIT(23) 1161#define EnMBID BIT(24) 1162#define APP_BASSN BIT(27) 1163#define APP_PHYSTS BIT(28) 1164#define APP_ICV BIT(29) 1165#define APP_MIC BIT(30) 1166#define APP_FCS BIT(31) 1167 1168#define _MIN_SPACE(x) ((x) & 0x7) 1169#define _SHORT_GI_PADDING(x) (((x) & 0x1F) << 3) 1170 1171#define RXERR_TYPE_OFDM_PPDU 0 1172#define RXERR_TYPE_OFDM_FALSE_ALARM 1 1173#define RXERR_TYPE_OFDM_MPDU_OK 2 1174#define RXERR_TYPE_OFDM_MPDU_FAIL 3 1175#define RXERR_TYPE_CCK_PPDU 4 1176#define RXERR_TYPE_CCK_FALSE_ALARM 5 1177#define RXERR_TYPE_CCK_MPDU_OK 6 1178#define RXERR_TYPE_CCK_MPDU_FAIL 7 1179#define RXERR_TYPE_HT_PPDU 8 1180#define RXERR_TYPE_HT_FALSE_ALARM 9 1181#define RXERR_TYPE_HT_MPDU_TOTAL 10 1182#define RXERR_TYPE_HT_MPDU_OK 11 1183#define RXERR_TYPE_HT_MPDU_FAIL 12 1184#define RXERR_TYPE_RX_FULL_DROP 15 1185 1186#define RXERR_COUNTER_MASK 0xFFFFF 1187#define RXERR_RPT_RST BIT(27) 1188#define _RXERR_RPT_SEL(type) ((type) << 28) 1189 1190#define SCR_TxUseDK BIT(0) 1191#define SCR_RxUseDK BIT(1) 1192#define SCR_TxEncEnable BIT(2) 1193#define SCR_RxDecEnable BIT(3) 1194#define SCR_SKByA2 BIT(4) 1195#define SCR_NoSKMC BIT(5) 1196#define SCR_TXBCUSEDK BIT(6) 1197#define SCR_RXBCUSEDK BIT(7) 1198 1199#define USB_IS_HIGH_SPEED 0 1200#define USB_IS_FULL_SPEED 1 1201#define USB_SPEED_MASK BIT(5) 1202 1203#define USB_NORMAL_SIE_EP_MASK 0xF 1204#define USB_NORMAL_SIE_EP_SHIFT 4 1205 1206#define USB_TEST_EP_MASK 0x30 1207#define USB_TEST_EP_SHIFT 4 1208 1209#define USB_AGG_EN BIT(3) 1210 1211#define MAC_ADDR_LEN 6 1212#define LAST_ENTRY_OF_TX_PKT_BUFFER 255 1213 1214#define POLLING_LLT_THRESHOLD 20 1215#define POLLING_READY_TIMEOUT_COUNT 1000 1216 1217#define MAX_MSS_DENSITY_2T 0x13 1218#define MAX_MSS_DENSITY_1T 0x0A 1219 1220#define EPROM_CMD_OPERATING_MODE_MASK ((1<<7)|(1<<6)) 1221#define EPROM_CMD_CONFIG 0x3 1222#define EPROM_CMD_LOAD 1 1223 1224#define HWSET_MAX_SIZE_92S HWSET_MAX_SIZE 1225 1226#define HAL_8192C_HW_GPIO_WPS_BIT BIT(2) 1227 1228/* REG_MULTI_FUNC_CTRL(For RTL8723 Only) */ 1229/* Enable GPIO[9] as WiFi HW PDn source */ 1230#define WL_HWPDN_EN BIT(0) 1231/* WiFi HW PDn polarity control */ 1232#define WL_HWPDN_SL BIT(1) 1233/* WiFi function enable */ 1234#define WL_FUNC_EN BIT(2) 1235/* Enable GPIO[9] as WiFi RF HW PDn source */ 1236#define WL_HWROF_EN BIT(3) 1237/* Enable GPIO[11] as BT HW PDn source */ 1238#define BT_HWPDN_EN BIT(16) 1239/* BT HW PDn polarity control */ 1240#define BT_HWPDN_SL BIT(17) 1241/* BT function enable */ 1242#define BT_FUNC_EN BIT(18) 1243/* Enable GPIO[11] as BT/GPS RF HW PDn source */ 1244#define BT_HWROF_EN BIT(19) 1245/* Enable GPIO[10] as GPS HW PDn source */ 1246#define GPS_HWPDN_EN BIT(20) 1247/* GPS HW PDn polarity control */ 1248#define GPS_HWPDN_SL BIT(21) 1249/* GPS function enable */ 1250#define GPS_FUNC_EN BIT(22) 1251 1252#define RPMAC_RESET 0x100 1253#define RPMAC_TXSTART 0x104 1254#define RPMAC_TXLEGACYSIG 0x108 1255#define RPMAC_TXHTSIG1 0x10c 1256#define RPMAC_TXHTSIG2 0x110 1257#define RPMAC_PHYDEBUG 0x114 1258#define RPMAC_TXPACKETNUM 0x118 1259#define RPMAC_TXIDLE 0x11c 1260#define RPMAC_TXMACHEADER0 0x120 1261#define RPMAC_TXMACHEADER1 0x124 1262#define RPMAC_TXMACHEADER2 0x128 1263#define RPMAC_TXMACHEADER3 0x12c 1264#define RPMAC_TXMACHEADER4 0x130 1265#define RPMAC_TXMACHEADER5 0x134 1266#define RPMAC_TXDADATYPE 0x138 1267#define RPMAC_TXRANDOMSEED 0x13c 1268#define RPMAC_CCKPLCPPREAMBLE 0x140 1269#define RPMAC_CCKPLCPHEADER 0x144 1270#define RPMAC_CCKCRC16 0x148 1271#define RPMAC_OFDMRXCRC32OK 0x170 1272#define RPMAC_OFDMRXCRC32Er 0x174 1273#define RPMAC_OFDMRXPARITYER 0x178 1274#define RPMAC_OFDMRXCRC8ER 0x17c 1275#define RPMAC_CCKCRXRC16ER 0x180 1276#define RPMAC_CCKCRXRC32ER 0x184 1277#define RPMAC_CCKCRXRC32OK 0x188 1278#define RPMAC_TXSTATUS 0x18c 1279 1280#define RFPGA0_RFMOD 0x800 1281 1282#define RFPGA0_TXINFO 0x804 1283#define RFPGA0_PSDFUNCTION 0x808 1284 1285#define RFPGA0_TXGAINSTAGE 0x80c 1286 1287#define RFPGA0_RFTIMING1 0x810 1288#define RFPGA0_RFTIMING2 0x814 1289 1290#define RFPGA0_XA_HSSIPARAMETER1 0x820 1291#define RFPGA0_XA_HSSIPARAMETER2 0x824 1292#define RFPGA0_XB_HSSIPARAMETER1 0x828 1293#define RFPGA0_XB_HSSIPARAMETER2 0x82c 1294 1295#define RFPGA0_XA_LSSIPARAMETER 0x840 1296#define RFPGA0_XB_LSSIPARAMETER 0x844 1297 1298#define RFPGA0_RFWAKEUPPARAMETER 0x850 1299#define RFPGA0_RFSLEEPUPPARAMETER 0x854 1300 1301#define RFPGA0_XAB_SWITCHCONTROL 0x858 1302#define RFPGA0_XCD_SWITCHCONTROL 0x85c 1303 1304#define RFPGA0_XA_RFINTERFACEOE 0x860 1305#define RFPGA0_XB_RFINTERFACEOE 0x864 1306 1307#define RFPGA0_XAB_RFINTERFACESW 0x870 1308#define RFPGA0_XCD_RFINTERFACESW 0x874 1309 1310#define rFPGA0_XAB_RFPARAMETER 0x878 1311#define rFPGA0_XCD_RFPARAMETER 0x87c 1312 1313#define RFPGA0_ANALOGPARAMETER1 0x880 1314#define RFPGA0_ANALOGPARAMETER2 0x884 1315#define RFPGA0_ANALOGPARAMETER3 0x888 1316#define RFPGA0_ANALOGPARAMETER4 0x88c 1317 1318#define RFPGA0_XA_LSSIREADBACK 0x8a0 1319#define RFPGA0_XB_LSSIREADBACK 0x8a4 1320#define RFPGA0_XC_LSSIREADBACK 0x8a8 1321#define RFPGA0_XD_LSSIREADBACK 0x8ac 1322 1323#define RFPGA0_PSDREPORT 0x8b4 1324#define TRANSCEIVEA_HSPI_READBACK 0x8b8 1325#define TRANSCEIVEB_HSPI_READBACK 0x8bc 1326#define RFPGA0_XAB_RFINTERFACERB 0x8e0 1327#define RFPGA0_XCD_RFINTERFACERB 0x8e4 1328 1329#define RFPGA1_RFMOD 0x900 1330 1331#define RFPGA1_TXBLOCK 0x904 1332#define RFPGA1_DEBUGSELECT 0x908 1333#define RFPGA1_TXINFO 0x90c 1334 1335#define RCCK0_SYSTEM 0xa00 1336 1337#define RCCK0_AFESETTING 0xa04 1338#define RCCK0_CCA 0xa08 1339 1340#define RCCK0_RXAGC1 0xa0c 1341#define RCCK0_RXAGC2 0xa10 1342 1343#define RCCK0_RXHP 0xa14 1344 1345#define RCCK0_DSPPARAMETER1 0xa18 1346#define RCCK0_DSPPARAMETER2 0xa1c 1347 1348#define RCCK0_TXFILTER1 0xa20 1349#define RCCK0_TXFILTER2 0xa24 1350#define RCCK0_DEBUGPORT 0xa28 1351#define RCCK0_FALSEALARMREPORT 0xa2c 1352#define RCCK0_TRSSIREPORT 0xa50 1353#define RCCK0_RXREPORT 0xa54 1354#define RCCK0_FACOUNTERLOWER 0xa5c 1355#define RCCK0_FACOUNTERUPPER 0xa58 1356 1357#define ROFDM0_LSTF 0xc00 1358 1359#define ROFDM0_TRXPATHENABLE 0xc04 1360#define ROFDM0_TRMUXPAR 0xc08 1361#define ROFDM0_TRSWISOLATION 0xc0c 1362 1363#define ROFDM0_XARXAFE 0xc10 1364#define ROFDM0_XARXIQIMBALANCE 0xc14 1365#define ROFDM0_XBRXAFE 0xc18 1366#define ROFDM0_XBRXIQIMBALANCE 0xc1c 1367#define ROFDM0_XCRXAFE 0xc20 1368#define ROFDM0_XCRXIQIMBANLANCE 0xc24 1369#define ROFDM0_XDRXAFE 0xc28 1370#define ROFDM0_XDRXIQIMBALANCE 0xc2c 1371 1372#define ROFDM0_RXDETECTOR1 0xc30 1373#define ROFDM0_RXDETECTOR2 0xc34 1374#define ROFDM0_RXDETECTOR3 0xc38 1375#define ROFDM0_RXDETECTOR4 0xc3c 1376 1377#define ROFDM0_RXDSP 0xc40 1378#define ROFDM0_CFOANDDAGC 0xc44 1379#define ROFDM0_CCADROPTHRESHOLD 0xc48 1380#define ROFDM0_ECCATHRESHOLD 0xc4c 1381 1382#define ROFDM0_XAAGCCORE1 0xc50 1383#define ROFDM0_XAAGCCORE2 0xc54 1384#define ROFDM0_XBAGCCORE1 0xc58 1385#define ROFDM0_XBAGCCORE2 0xc5c 1386#define ROFDM0_XCAGCCORE1 0xc60 1387#define ROFDM0_XCAGCCORE2 0xc64 1388#define ROFDM0_XDAGCCORE1 0xc68 1389#define ROFDM0_XDAGCCORE2 0xc6c 1390 1391#define ROFDM0_AGCPARAMETER1 0xc70 1392#define ROFDM0_AGCPARAMETER2 0xc74 1393#define ROFDM0_AGCRSSITABLE 0xc78 1394#define ROFDM0_HTSTFAGC 0xc7c 1395 1396#define ROFDM0_XATXIQIMBALANCE 0xc80 1397#define ROFDM0_XATXAFE 0xc84 1398#define ROFDM0_XBTXIQIMBALANCE 0xc88 1399#define ROFDM0_XBTXAFE 0xc8c 1400#define ROFDM0_XCTXIQIMBALANCE 0xc90 1401#define ROFDM0_XCTXAFE 0xc94 1402#define ROFDM0_XDTXIQIMBALANCE 0xc98 1403#define ROFDM0_XDTXAFE 0xc9c 1404 1405#define ROFDM0_RXIQEXTANTA 0xca0 1406 1407#define ROFDM0_RXHPPARAMETER 0xce0 1408#define ROFDM0_TXPSEUDONOISEWGT 0xce4 1409#define ROFDM0_FRAMESYNC 0xcf0 1410#define ROFDM0_DFSREPORT 0xcf4 1411#define ROFDM0_TXCOEFF1 0xca4 1412#define ROFDM0_TXCOEFF2 0xca8 1413#define ROFDM0_TXCOEFF3 0xcac 1414#define ROFDM0_TXCOEFF4 0xcb0 1415#define ROFDM0_TXCOEFF5 0xcb4 1416#define ROFDM0_TXCOEFF6 0xcb8 1417 1418#define ROFDM1_LSTF 0xd00 1419#define ROFDM1_TRXPATHENABLE 0xd04 1420 1421#define ROFDM1_CF0 0xd08 1422#define ROFDM1_CSI1 0xd10 1423#define ROFDM1_SBD 0xd14 1424#define ROFDM1_CSI2 0xd18 1425#define ROFDM1_CFOTRACKING 0xd2c 1426#define ROFDM1_TRXMESAURE1 0xd34 1427#define ROFDM1_INTFDET 0xd3c 1428#define ROFDM1_PSEUDONOISESTATEAB 0xd50 1429#define ROFDM1_PSEUDONOISESTATECD 0xd54 1430#define ROFDM1_RXPSEUDONOISEWGT 0xd58 1431 1432#define ROFDM_PHYCOUNTER1 0xda0 1433#define ROFDM_PHYCOUNTER2 0xda4 1434#define ROFDM_PHYCOUNTER3 0xda8 1435 1436#define ROFDM_SHORTCFOAB 0xdac 1437#define ROFDM_SHORTCFOCD 0xdb0 1438#define ROFDM_LONGCFOAB 0xdb4 1439#define ROFDM_LONGCFOCD 0xdb8 1440#define ROFDM_TAILCF0AB 0xdbc 1441#define ROFDM_TAILCF0CD 0xdc0 1442#define ROFDM_PWMEASURE1 0xdc4 1443#define ROFDM_PWMEASURE2 0xdc8 1444#define ROFDM_BWREPORT 0xdcc 1445#define ROFDM_AGCREPORT 0xdd0 1446#define ROFDM_RXSNR 0xdd4 1447#define ROFDM_RXEVMCSI 0xdd8 1448#define ROFDM_SIGREPORT 0xddc 1449 1450#define RTXAGC_A_RATE18_06 0xe00 1451#define RTXAGC_A_RATE54_24 0xe04 1452#define RTXAGC_A_CCK1_MCS32 0xe08 1453#define RTXAGC_A_MCS03_MCS00 0xe10 1454#define RTXAGC_A_MCS07_MCS04 0xe14 1455#define RTXAGC_A_MCS11_MCS08 0xe18 1456#define RTXAGC_A_MCS15_MCS12 0xe1c 1457 1458#define RTXAGC_B_RATE18_06 0x830 1459#define RTXAGC_B_RATE54_24 0x834 1460#define RTXAGC_B_CCK1_55_MCS32 0x838 1461#define RTXAGC_B_MCS03_MCS00 0x83c 1462#define RTXAGC_B_MCS07_MCS04 0x848 1463#define RTXAGC_B_MCS11_MCS08 0x84c 1464#define RTXAGC_B_MCS15_MCS12 0x868 1465#define RTXAGC_B_CCK11_A_CCK2_11 0x86c 1466 1467#define RZEBRA1_HSSIENABLE 0x0 1468#define RZEBRA1_TRXENABLE1 0x1 1469#define RZEBRA1_TRXENABLE2 0x2 1470#define RZEBRA1_AGC 0x4 1471#define RZEBRA1_CHARGEPUMP 0x5 1472#define RZEBRA1_CHANNEL 0x7 1473 1474#define RZEBRA1_TXGAIN 0x8 1475#define RZEBRA1_TXLPF 0x9 1476#define RZEBRA1_RXLPF 0xb 1477#define RZEBRA1_RXHPFCORNER 0xc 1478 1479#define RGLOBALCTRL 0 1480#define RRTL8256_TXLPF 19 1481#define RRTL8256_RXLPF 11 1482#define RRTL8258_TXLPF 0x11 1483#define RRTL8258_RXLPF 0x13 1484#define RRTL8258_RSSILPF 0xa 1485 1486#define RF_AC 0x00 1487 1488#define RF_IQADJ_G1 0x01 1489#define RF_IQADJ_G2 0x02 1490#define RF_POW_TRSW 0x05 1491 1492#define RF_GAIN_RX 0x06 1493#define RF_GAIN_TX 0x07 1494 1495#define RF_TXM_IDAC 0x08 1496#define RF_BS_IQGEN 0x0F 1497 1498#define RF_MODE1 0x10 1499#define RF_MODE2 0x11 1500 1501#define RF_RX_AGC_HP 0x12 1502#define RF_TX_AGC 0x13 1503#define RF_BIAS 0x14 1504#define RF_IPA 0x15 1505#define RF_POW_ABILITY 0x17 1506#define RF_MODE_AG 0x18 1507#define RRFCHANNEL 0x18 1508#define RF_CHNLBW 0x18 1509#define RF_TOP 0x19 1510 1511#define RF_RX_G1 0x1A 1512#define RF_RX_G2 0x1B 1513 1514#define RF_RX_BB2 0x1C 1515#define RF_RX_BB1 0x1D 1516 1517#define RF_RCK1 0x1E 1518#define RF_RCK2 0x1F 1519 1520#define RF_TX_G1 0x20 1521#define RF_TX_G2 0x21 1522#define RF_TX_G3 0x22 1523 1524#define RF_TX_BB1 0x23 1525#define RF_T_METER 0x24 1526 1527#define RF_SYN_G1 0x25 1528#define RF_SYN_G2 0x26 1529#define RF_SYN_G3 0x27 1530#define RF_SYN_G4 0x28 1531#define RF_SYN_G5 0x29 1532#define RF_SYN_G6 0x2A 1533#define RF_SYN_G7 0x2B 1534#define RF_SYN_G8 0x2C 1535 1536#define RF_RCK_OS 0x30 1537#define RF_TXPA_G1 0x31 1538#define RF_TXPA_G2 0x32 1539#define RF_TXPA_G3 0x33 1540 1541#define BBBRESETB 0x100 1542#define BGLOBALRESETB 0x200 1543#define BOFDMTXSTART 0x4 1544#define BCCKTXSTART 0x8 1545#define BCRC32DEBUG 0x100 1546#define BPMACLOOPBACK 0x10 1547#define BTXLSIG 0xffffff 1548#define BOFDMTXRATE 0xf 1549#define BOFDMTXRESERVED 0x10 1550#define BOFDMTXLENGTH 0x1ffe0 1551#define BOFDMTXPARITY 0x20000 1552#define BTXHTSIG1 0xffffff 1553#define BTXHTMCSRATE 0x7f 1554#define BTXHTBW 0x80 1555#define BTXHTLENGTH 0xffff00 1556#define BTXHTSIG2 0xffffff 1557#define BTXHTSMOOTHING 0x1 1558#define BTXHTSOUNDING 0x2 1559#define BTXHTRESERVED 0x4 1560#define BTXHTAGGREATION 0x8 1561#define BTXHTSTBC 0x30 1562#define BTXHTADVANCECODING 0x40 1563#define BTXHTSHORTGI 0x80 1564#define BTXHTNUMBERHT_LTF 0x300 1565#define BTXHTCRC8 0x3fc00 1566#define BCOUNTERRESET 0x10000 1567#define BNUMOFOFDMTX 0xffff 1568#define BNUMOFCCKTX 0xffff0000 1569#define BTXIDLEINTERVAL 0xffff 1570#define BOFDMSERVICE 0xffff0000 1571#define BTXMACHEADER 0xffffffff 1572#define BTXDATAINIT 0xff 1573#define BTXHTMODE 0x100 1574#define BTXDATATYPE 0x30000 1575#define BTXRANDOMSEED 0xffffffff 1576#define BCCKTXPREAMBLE 0x1 1577#define BCCKTXSFD 0xffff0000 1578#define BCCKTXSIG 0xff 1579#define BCCKTXSERVICE 0xff00 1580#define BCCKLENGTHEXT 0x8000 1581#define BCCKTXLENGHT 0xffff0000 1582#define BCCKTXCRC16 0xffff 1583#define BCCKTXSTATUS 0x1 1584#define BOFDMTXSTATUS 0x2 1585#define IS_BB_REG_OFFSET_92S(_Offset) \ 1586 ((_Offset >= 0x800) && (_Offset <= 0xfff)) 1587 1588#define BRFMOD 0x1 1589#define BJAPANMODE 0x2 1590#define BCCKTXSC 0x30 1591#define BCCKEN 0x1000000 1592#define BOFDMEN 0x2000000 1593 1594#define BOFDMRXADCPHASE 0x10000 1595#define BOFDMTXDACPHASE 0x40000 1596#define BXATXAGC 0x3f 1597 1598#define BXBTXAGC 0xf00 1599#define BXCTXAGC 0xf000 1600#define BXDTXAGC 0xf0000 1601 1602#define BPASTART 0xf0000000 1603#define BTRSTART 0x00f00000 1604#define BRFSTART 0x0000f000 1605#define BBBSTART 0x000000f0 1606#define BBBCCKSTART 0x0000000f 1607#define BPAEND 0xf 1608#define BTREND 0x0f000000 1609#define BRFEND 0x000f0000 1610#define BCCAMASK 0x000000f0 1611#define BR2RCCAMASK 0x00000f00 1612#define BHSSI_R2TDELAY 0xf8000000 1613#define BHSSI_T2RDELAY 0xf80000 1614#define BCONTXHSSI 0x400 1615#define BIGFROMCCK 0x200 1616#define BAGCADDRESS 0x3f 1617#define BRXHPTX 0x7000 1618#define BRXHP2RX 0x38000 1619#define BRXHPCCKINI 0xc0000 1620#define BAGCTXCODE 0xc00000 1621#define BAGCRXCODE 0x300000 1622 1623#define B3WIREDATALENGTH 0x800 1624#define B3WIREADDREAALENGTH 0x400 1625 1626#define B3WIRERFPOWERDOWN 0x1 1627#define B5GPAPEPOLARITY 0x40000000 1628#define B2GPAPEPOLARITY 0x80000000 1629#define BRFSW_TXDEFAULTANT 0x3 1630#define BRFSW_TXOPTIONANT 0x30 1631#define BRFSW_RXDEFAULTANT 0x300 1632#define BRFSW_RXOPTIONANT 0x3000 1633#define BRFSI_3WIREDATA 0x1 1634#define BRFSI_3WIRECLOCK 0x2 1635#define BRFSI_3WIRELOAD 0x4 1636#define BRFSI_3WIRERW 0x8 1637#define BRFSI_3WIRE 0xf 1638 1639#define BRFSI_RFENV 0x10 1640 1641#define BRFSI_TRSW 0x20 1642#define BRFSI_TRSWB 0x40 1643#define BRFSI_ANTSW 0x100 1644#define BRFSI_ANTSWB 0x200 1645#define BRFSI_PAPE 0x400 1646#define BRFSI_PAPE5G 0x800 1647#define BBANDSELECT 0x1 1648#define BHTSIG2_GI 0x80 1649#define BHTSIG2_SMOOTHING 0x01 1650#define BHTSIG2_SOUNDING 0x02 1651#define BHTSIG2_AGGREATON 0x08 1652#define BHTSIG2_STBC 0x30 1653#define BHTSIG2_ADVCODING 0x40 1654#define BHTSIG2_NUMOFHTLTF 0x300 1655#define BHTSIG2_CRC8 0x3fc 1656#define BHTSIG1_MCS 0x7f 1657#define BHTSIG1_BANDWIDTH 0x80 1658#define BHTSIG1_HTLENGTH 0xffff 1659#define BLSIG_RATE 0xf 1660#define BLSIG_RESERVED 0x10 1661#define BLSIG_LENGTH 0x1fffe 1662#define BLSIG_PARITY 0x20 1663#define BCCKRXPHASE 0x4 1664 1665#define BLSSIREADADDRESS 0x7f800000 1666#define BLSSIREADEDGE 0x80000000 1667 1668#define BLSSIREADBACKDATA 0xfffff 1669 1670#define BLSSIREADOKFLAG 0x1000 1671#define BCCKSAMPLERATE 0x8 1672#define BREGULATOR0STANDBY 0x1 1673#define BREGULATORPLLSTANDBY 0x2 1674#define BREGULATOR1STANDBY 0x4 1675#define BPLLPOWERUP 0x8 1676#define BDPLLPOWERUP 0x10 1677#define BDA10POWERUP 0x20 1678#define BAD7POWERUP 0x200 1679#define BDA6POWERUP 0x2000 1680#define BXTALPOWERUP 0x4000 1681#define B40MDCLKPOWERUP 0x8000 1682#define BDA6DEBUGMODE 0x20000 1683#define BDA6SWING 0x380000 1684 1685#define BADCLKPHASE 0x4000000 1686#define B80MCLKDELAY 0x18000000 1687#define BAFEWATCHDOGENABLE 0x20000000 1688 1689#define BXTALCAP01 0xc0000000 1690#define BXTALCAP23 0x3 1691#define BXTALCAP92X 0x0f000000 1692#define BXTALCAP 0x0f000000 1693 1694#define BINTDIFCLKENABLE 0x400 1695#define BEXTSIGCLKENABLE 0x800 1696#define BBANDGAP_MBIAS_POWERUP 0x10000 1697#define BAD11SH_GAIN 0xc0000 1698#define BAD11NPUT_RANGE 0x700000 1699#define BAD110P_CURRENT 0x3800000 1700#define BLPATH_LOOPBACK 0x4000000 1701#define BQPATH_LOOPBACK 0x8000000 1702#define BAFE_LOOPBACK 0x10000000 1703#define BDA10_SWING 0x7e0 1704#define BDA10_REVERSE 0x800 1705#define BDA_CLK_SOURCE 0x1000 1706#define BDA7INPUT_RANGE 0x6000 1707#define BDA7_GAIN 0x38000 1708#define BDA7OUTPUT_CM_MODE 0x40000 1709#define BDA7INPUT_CM_MODE 0x380000 1710#define BDA7CURRENT 0xc00000 1711#define BREGULATOR_ADJUST 0x7000000 1712#define BAD11POWERUP_ATTX 0x1 1713#define BDA10PS_ATTX 0x10 1714#define BAD11POWERUP_ATRX 0x100 1715#define BDA10PS_ATRX 0x1000 1716#define BCCKRX_AGC_FORMAT 0x200 1717#define BPSDFFT_SAMPLE_POINT 0xc000 1718#define BPSD_AVERAGE_NUM 0x3000 1719#define BIQPATH_CONTROL 0xc00 1720#define BPSD_FREQ 0x3ff 1721#define BPSD_ANTENNA_PATH 0x30 1722#define BPSD_IQ_SWITCH 0x40 1723#define BPSD_RX_TRIGGER 0x400000 1724#define BPSD_TX_TRIGGER 0x80000000 1725#define BPSD_SINE_TONE_SCALE 0x7f000000 1726#define BPSD_REPORT 0xffff 1727 1728#define BOFDM_TXSC 0x30000000 1729#define BCCK_TXON 0x1 1730#define BOFDM_TXON 0x2 1731#define BDEBUG_PAGE 0xfff 1732#define BDEBUG_ITEM 0xff 1733#define BANTL 0x10 1734#define BANT_NONHT 0x100 1735#define BANT_HT1 0x1000 1736#define BANT_HT2 0x10000 1737#define BANT_HT1S1 0x100000 1738#define BANT_NONHTS1 0x1000000 1739 1740#define BCCK_BBMODE 0x3 1741#define BCCK_TXPOWERSAVING 0x80 1742#define BCCK_RXPOWERSAVING 0x40 1743 1744#define BCCK_SIDEBAND 0x10 1745 1746#define BCCK_SCRAMBLE 0x8 1747#define BCCK_ANTDIVERSITY 0x8000 1748#define BCCK_CARRIER_RECOVERY 0x4000 1749#define BCCK_TXRATE 0x3000 1750#define BCCK_DCCANCEL 0x0800 1751#define BCCK_ISICANCEL 0x0400 1752#define BCCK_MATCH_FILTER 0x0200 1753#define BCCK_EQUALIZER 0x0100 1754#define BCCK_PREAMBLE_DETECT 0x800000 1755#define BCCK_FAST_FALSECCA 0x400000 1756#define BCCK_CH_ESTSTART 0x300000 1757#define BCCK_CCA_COUNT 0x080000 1758#define BCCK_CS_LIM 0x070000 1759#define BCCK_BIST_MODE 0x80000000 1760#define BCCK_CCAMASK 0x40000000 1761#define BCCK_TX_DAC_PHASE 0x4 1762#define BCCK_RX_ADC_PHASE 0x20000000 1763#define BCCKR_CP_MODE 0x0100 1764#define BCCK_TXDC_OFFSET 0xf0 1765#define BCCK_RXDC_OFFSET 0xf 1766#define BCCK_CCA_MODE 0xc000 1767#define BCCK_FALSECS_LIM 0x3f00 1768#define BCCK_CS_RATIO 0xc00000 1769#define BCCK_CORGBIT_SEL 0x300000 1770#define BCCK_PD_LIM 0x0f0000 1771#define BCCK_NEWCCA 0x80000000 1772#define BCCK_RXHP_OF_IG 0x8000 1773#define BCCK_RXIG 0x7f00 1774#define BCCK_LNA_POLARITY 0x800000 1775#define BCCK_RX1ST_BAIN 0x7f0000 1776#define BCCK_RF_EXTEND 0x20000000 1777#define BCCK_RXAGC_SATLEVEL 0x1f000000 1778#define BCCK_RXAGC_SATCOUNT 0xe0 1779#define bCCKRxRFSettle 0x1f 1780#define BCCK_FIXED_RXAGC 0x8000 1781#define BCCK_ANTENNA_POLARITY 0x2000 1782#define BCCK_TXFILTER_TYPE 0x0c00 1783#define BCCK_RXAGC_REPORTTYPE 0x0300 1784#define BCCK_RXDAGC_EN 0x80000000 1785#define BCCK_RXDAGC_PERIOD 0x20000000 1786#define BCCK_RXDAGC_SATLEVEL 0x1f000000 1787#define BCCK_TIMING_RECOVERY 0x800000 1788#define BCCK_TXC0 0x3f0000 1789#define BCCK_TXC1 0x3f000000 1790#define BCCK_TXC2 0x3f 1791#define BCCK_TXC3 0x3f00 1792#define BCCK_TXC4 0x3f0000 1793#define BCCK_TXC5 0x3f000000 1794#define BCCK_TXC6 0x3f 1795#define BCCK_TXC7 0x3f00 1796#define BCCK_DEBUGPORT 0xff0000 1797#define BCCK_DAC_DEBUG 0x0f000000 1798#define BCCK_FALSEALARM_ENABLE 0x8000 1799#define BCCK_FALSEALARM_READ 0x4000 1800#define BCCK_TRSSI 0x7f 1801#define BCCK_RXAGC_REPORT 0xfe 1802#define BCCK_RXREPORT_ANTSEL 0x80000000 1803#define BCCK_RXREPORT_MFOFF 0x40000000 1804#define BCCK_RXREPORT_SQLOSS 0x20000000 1805#define BCCK_RXREPORT_PKTLOSS 0x10000000 1806#define BCCK_RXREPORT_LOCKEDBIT 0x08000000 1807#define BCCK_RXREPORT_RATEERROR 0x04000000 1808#define BCCK_RXREPORT_RXRATE 0x03000000 1809#define BCCK_RXFA_COUNTER_LOWER 0xff 1810#define BCCK_RXFA_COUNTER_UPPER 0xff000000 1811#define BCCK_RXHPAGC_START 0xe000 1812#define BCCK_RXHPAGC_FINAL 0x1c00 1813#define BCCK_RXFALSEALARM_ENABLE 0x8000 1814#define BCCK_FACOUNTER_FREEZE 0x4000 1815#define BCCK_TXPATH_SEL 0x10000000 1816#define BCCK_DEFAULT_RXPATH 0xc000000 1817#define BCCK_OPTION_RXPATH 0x3000000 1818 1819#define BNUM_OFSTF 0x3 1820#define BSHIFT_L 0xc0 1821#define BGI_TH 0xc 1822#define BRXPATH_A 0x1 1823#define BRXPATH_B 0x2 1824#define BRXPATH_C 0x4 1825#define BRXPATH_D 0x8 1826#define BTXPATH_A 0x1 1827#define BTXPATH_B 0x2 1828#define BTXPATH_C 0x4 1829#define BTXPATH_D 0x8 1830#define BTRSSI_FREQ 0x200 1831#define BADC_BACKOFF 0x3000 1832#define BDFIR_BACKOFF 0xc000 1833#define BTRSSI_LATCH_PHASE 0x10000 1834#define BRX_LDC_OFFSET 0xff 1835#define BRX_QDC_OFFSET 0xff00 1836#define BRX_DFIR_MODE 0x1800000 1837#define BRX_DCNF_TYPE 0xe000000 1838#define BRXIQIMB_A 0x3ff 1839#define BRXIQIMB_B 0xfc00 1840#define BRXIQIMB_C 0x3f0000 1841#define BRXIQIMB_D 0xffc00000 1842#define BDC_DC_NOTCH 0x60000 1843#define BRXNB_NOTCH 0x1f000000 1844#define BPD_TH 0xf 1845#define BPD_TH_OPT2 0xc000 1846#define BPWED_TH 0x700 1847#define BIFMF_WIN_L 0x800 1848#define BPD_OPTION 0x1000 1849#define BMF_WIN_L 0xe000 1850#define BBW_SEARCH_L 0x30000 1851#define BWIN_ENH_L 0xc0000 1852#define BBW_TH 0x700000 1853#define BED_TH2 0x3800000 1854#define BBW_OPTION 0x4000000 1855#define BRADIO_TH 0x18000000 1856#define BWINDOW_L 0xe0000000 1857#define BSBD_OPTION 0x1 1858#define BFRAME_TH 0x1c 1859#define BFS_OPTION 0x60 1860#define BDC_SLOPE_CHECK 0x80 1861#define BFGUARD_COUNTER_DC_L 0xe00 1862#define BFRAME_WEIGHT_SHORT 0x7000 1863#define BSUB_TUNE 0xe00000 1864#define BFRAME_DC_LENGTH 0xe000000 1865#define BSBD_START_OFFSET 0x30000000 1866#define BFRAME_TH_2 0x7 1867#define BFRAME_GI2_TH 0x38 1868#define BGI2_SYNC_EN 0x40 1869#define BSARCH_SHORT_EARLY 0x300 1870#define BSARCH_SHORT_LATE 0xc00 1871#define BSARCH_GI2_LATE 0x70000 1872#define BCFOANTSUM 0x1 1873#define BCFOACC 0x2 1874#define BCFOSTARTOFFSET 0xc 1875#define BCFOLOOPBACK 0x70 1876#define BCFOSUMWEIGHT 0x80 1877#define BDAGCENABLE 0x10000 1878#define BTXIQIMB_A 0x3ff 1879#define BTXIQIMB_b 0xfc00 1880#define BTXIQIMB_C 0x3f0000 1881#define BTXIQIMB_D 0xffc00000 1882#define BTXIDCOFFSET 0xff 1883#define BTXIQDCOFFSET 0xff00 1884#define BTXDFIRMODE 0x10000 1885#define BTXPESUDO_NOISEON 0x4000000 1886#define BTXPESUDO_NOISE_A 0xff 1887#define BTXPESUDO_NOISE_B 0xff00 1888#define BTXPESUDO_NOISE_C 0xff0000 1889#define BTXPESUDO_NOISE_D 0xff000000 1890#define BCCA_DROPOPTION 0x20000 1891#define BCCA_DROPTHRES 0xfff00000 1892#define BEDCCA_H 0xf 1893#define BEDCCA_L 0xf0 1894#define BLAMBDA_ED 0x300 1895#define BRX_INITIALGAIN 0x7f 1896#define BRX_ANTDIV_EN 0x80 1897#define BRX_AGC_ADDRESS_FOR_LNA 0x7f00 1898#define BRX_HIGHPOWER_FLOW 0x8000 1899#define BRX_AGC_FREEZE_THRES 0xc0000 1900#define BRX_FREEZESTEP_AGC1 0x300000 1901#define BRX_FREEZESTEP_AGC2 0xc00000 1902#define BRX_FREEZESTEP_AGC3 0x3000000 1903#define BRX_FREEZESTEP_AGC0 0xc000000 1904#define BRXRSSI_CMP_EN 0x10000000 1905#define BRXQUICK_AGCEN 0x20000000 1906#define BRXAGC_FREEZE_THRES_MODE 0x40000000 1907#define BRX_OVERFLOW_CHECKTYPE 0x80000000 1908#define BRX_AGCSHIFT 0x7f 1909#define BTRSW_TRI_ONLY 0x80 1910#define BPOWER_THRES 0x300 1911#define BRXAGC_EN 0x1 1912#define BRXAGC_TOGETHER_EN 0x2 1913#define BRXAGC_MIN 0x4 1914#define BRXHP_INI 0x7 1915#define BRXHP_TRLNA 0x70 1916#define BRXHP_RSSI 0x700 1917#define BRXHP_BBP1 0x7000 1918#define BRXHP_BBP2 0x70000 1919#define BRXHP_BBP3 0x700000 1920#define BRSSI_H 0x7f0000 1921#define BRSSI_GEN 0x7f000000 1922#define BRXSETTLE_TRSW 0x7 1923#define BRXSETTLE_LNA 0x38 1924#define BRXSETTLE_RSSI 0x1c0 1925#define BRXSETTLE_BBP 0xe00 1926#define BRXSETTLE_RXHP 0x7000 1927#define BRXSETTLE_ANTSW_RSSI 0x38000 1928#define BRXSETTLE_ANTSW 0xc0000 1929#define BRXPROCESS_TIME_DAGC 0x300000 1930#define BRXSETTLE_HSSI 0x400000 1931#define BRXPROCESS_TIME_BBPPW 0x800000 1932#define BRXANTENNA_POWER_SHIFT 0x3000000 1933#define BRSSI_TABLE_SELECT 0xc000000 1934#define BRXHP_FINAL 0x7000000 1935#define BRXHPSETTLE_BBP 0x7 1936#define BRXHTSETTLE_HSSI 0x8 1937#define BRXHTSETTLE_RXHP 0x70 1938#define BRXHTSETTLE_BBPPW 0x80 1939#define BRXHTSETTLE_IDLE 0x300 1940#define BRXHTSETTLE_RESERVED 0x1c00 1941#define BRXHT_RXHP_EN 0x8000 1942#define BRXAGC_FREEZE_THRES 0x30000 1943#define BRXAGC_TOGETHEREN 0x40000 1944#define BRXHTAGC_MIN 0x80000 1945#define BRXHTAGC_EN 0x100000 1946#define BRXHTDAGC_EN 0x200000 1947#define BRXHT_RXHP_BBP 0x1c00000 1948#define BRXHT_RXHP_FINAL 0xe0000000 1949#define BRXPW_RADIO_TH 0x3 1950#define BRXPW_RADIO_EN 0x4 1951#define BRXMF_HOLD 0x3800 1952#define BRXPD_DELAY_TH1 0x38 1953#define BRXPD_DELAY_TH2 0x1c0 1954#define BRXPD_DC_COUNT_MAX 0x600 1955#define BRXPD_DELAY_TH 0x8000 1956#define BRXPROCESS_DELAY 0xf0000 1957#define BRXSEARCHRANGE_GI2_EARLY 0x700000 1958#define BRXFRAME_FUARD_COUNTER_L 0x3800000 1959#define BRXSGI_GUARD_L 0xc000000 1960#define BRXSGI_SEARCH_L 0x30000000 1961#define BRXSGI_TH 0xc0000000 1962#define BDFSCNT0 0xff 1963#define BDFSCNT1 0xff00 1964#define BDFSFLAG 0xf0000 1965#define BMF_WEIGHT_SUM 0x300000 1966#define BMINIDX_TH 0x7f000000 1967#define BDAFORMAT 0x40000 1968#define BTXCH_EMU_ENABLE 0x01000000 1969#define BTRSW_ISOLATION_A 0x7f 1970#define BTRSW_ISOLATION_B 0x7f00 1971#define BTRSW_ISOLATION_C 0x7f0000 1972#define BTRSW_ISOLATION_D 0x7f000000 1973#define BEXT_LNA_GAIN 0x7c00 1974 1975#define BSTBC_EN 0x4 1976#define BANTENNA_MAPPING 0x10 1977#define BNSS 0x20 1978#define BCFO_ANTSUM_ID 0x200 1979#define BPHY_COUNTER_RESET 0x8000000 1980#define BCFO_REPORT_GET 0x4000000 1981#define BOFDM_CONTINUE_TX 0x10000000 1982#define BOFDM_SINGLE_CARRIER 0x20000000 1983#define BOFDM_SINGLE_TONE 0x40000000 1984#define BHT_DETECT 0x100 1985#define BCFOEN 0x10000 1986#define BCFOVALUE 0xfff00000 1987#define BSIGTONE_RE 0x3f 1988#define BSIGTONE_IM 0x7f00 1989#define BCOUNTER_CCA 0xffff 1990#define BCOUNTER_PARITYFAIL 0xffff0000 1991#define BCOUNTER_RATEILLEGAL 0xffff 1992#define BCOUNTER_CRC8FAIL 0xffff0000 1993#define BCOUNTER_MCSNOSUPPORT 0xffff 1994#define BCOUNTER_FASTSYNC 0xffff 1995#define BSHORTCFO 0xfff 1996#define BSHORTCFOT_LENGTH 12 1997#define BSHORTCFOF_LENGTH 11 1998#define BLONGCFO 0x7ff 1999#define BLONGCFOT_LENGTH 11 2000#define BLONGCFOF_LENGTH 11 2001#define BTAILCFO 0x1fff 2002#define BTAILCFOT_LENGTH 13 2003#define BTAILCFOF_LENGTH 12 2004#define BNOISE_EN_PWDB 0xffff 2005#define BCC_POWER_DB 0xffff0000 2006#define BMOISE_PWDB 0xffff 2007#define BPOWERMEAST_LENGTH 10 2008#define BPOWERMEASF_LENGTH 3 2009#define BRX_HT_BW 0x1 2010#define BRXSC 0x6 2011#define BRX_HT 0x8 2012#define BNB_INTF_DET_ON 0x1 2013#define BINTF_WIN_LEN_CFG 0x30 2014#define BNB_INTF_TH_CFG 0x1c0 2015#define BRFGAIN 0x3f 2016#define BTABLESEL 0x40 2017#define BTRSW 0x80 2018#define BRXSNR_A 0xff 2019#define BRXSNR_B 0xff00 2020#define BRXSNR_C 0xff0000 2021#define BRXSNR_D 0xff000000 2022#define BSNR_EVMT_LENGTH 8 2023#define BSNR_EVMF_LENGTH 1 2024#define BCSI1ST 0xff 2025#define BCSI2ND 0xff00 2026#define BRXEVM1ST 0xff0000 2027#define BRXEVM2ND 0xff000000 2028#define BSIGEVM 0xff 2029#define BPWDB 0xff00 2030#define BSGIEN 0x10000 2031 2032#define BSFACTOR_QMA1 0xf 2033#define BSFACTOR_QMA2 0xf0 2034#define BSFACTOR_QMA3 0xf00 2035#define BSFACTOR_QMA4 0xf000 2036#define BSFACTOR_QMA5 0xf0000 2037#define BSFACTOR_QMA6 0xf0000 2038#define BSFACTOR_QMA7 0xf00000 2039#define BSFACTOR_QMA8 0xf000000 2040#define BSFACTOR_QMA9 0xf0000000 2041#define BCSI_SCHEME 0x100000 2042 2043#define BNOISE_LVL_TOP_SET 0x3 2044#define BCHSMOOTH 0x4 2045#define BCHSMOOTH_CFG1 0x38 2046#define BCHSMOOTH_CFG2 0x1c0 2047#define BCHSMOOTH_CFG3 0xe00 2048#define BCHSMOOTH_CFG4 0x7000 2049#define BMRCMODE 0x800000 2050#define BTHEVMCFG 0x7000000 2051 2052#define BLOOP_FIT_TYPE 0x1 2053#define BUPD_CFO 0x40 2054#define BUPD_CFO_OFFDATA 0x80 2055#define BADV_UPD_CFO 0x100 2056#define BADV_TIME_CTRL 0x800 2057#define BUPD_CLKO 0x1000 2058#define BFC 0x6000 2059#define BTRACKING_MODE 0x8000 2060#define BPHCMP_ENABLE 0x10000 2061#define BUPD_CLKO_LTF 0x20000 2062#define BCOM_CH_CFO 0x40000 2063#define BCSI_ESTI_MODE 0x80000 2064#define BADV_UPD_EQZ 0x100000 2065#define BUCHCFG 0x7000000 2066#define BUPDEQZ 0x8000000 2067 2068#define BRX_PESUDO_NOISE_ON 0x20000000 2069#define BRX_PESUDO_NOISE_A 0xff 2070#define BRX_PESUDO_NOISE_B 0xff00 2071#define BRX_PESUDO_NOISE_C 0xff0000 2072#define BRX_PESUDO_NOISE_D 0xff000000 2073#define BRX_PESUDO_NOISESTATE_A 0xffff 2074#define BRX_PESUDO_NOISESTATE_B 0xffff0000 2075#define BRX_PESUDO_NOISESTATE_C 0xffff 2076#define BRX_PESUDO_NOISESTATE_D 0xffff0000 2077 2078#define BZEBRA1_HSSIENABLE 0x8 2079#define BZEBRA1_TRXCONTROL 0xc00 2080#define BZEBRA1_TRXGAINSETTING 0x07f 2081#define BZEBRA1_RXCOUNTER 0xc00 2082#define BZEBRA1_TXCHANGEPUMP 0x38 2083#define BZEBRA1_RXCHANGEPUMP 0x7 2084#define BZEBRA1_CHANNEL_NUM 0xf80 2085#define BZEBRA1_TXLPFBW 0x400 2086#define BZEBRA1_RXLPFBW 0x600 2087 2088#define BRTL8256REG_MODE_CTRL1 0x100 2089#define BRTL8256REG_MODE_CTRL0 0x40 2090#define BRTL8256REG_TXLPFBW 0x18 2091#define BRTL8256REG_RXLPFBW 0x600 2092 2093#define BRTL8258_TXLPFBW 0xc 2094#define BRTL8258_RXLPFBW 0xc00 2095#define BRTL8258_RSSILPFBW 0xc0 2096 2097#define BBYTE0 0x1 2098#define BBYTE1 0x2 2099#define BBYTE2 0x4 2100#define BBYTE3 0x8 2101#define BWORD0 0x3 2102#define BWORD1 0xc 2103#define BWORD 0xf 2104 2105#define MASKBYTE0 0xff 2106#define MASKBYTE1 0xff00 2107#define MASKBYTE2 0xff0000 2108#define MASKBYTE3 0xff000000 2109#define MASKHWORD 0xffff0000 2110#define MASKLWORD 0x0000ffff 2111#define MASKDWORD 0xffffffff 2112#define MASK12BITS 0xfff 2113#define MASKH4BITS 0xf0000000 2114#define MASKOFDM_D 0xffc00000 2115#define MASKCCK 0x3f3f3f3f 2116 2117#define MASK4BITS 0x0f 2118#define MASK20BITS 0xfffff 2119#define RFREG_OFFSET_MASK 0xfffff 2120 2121#define BENABLE 0x1 2122#define BDISABLE 0x0 2123 2124#define LEFT_ANTENNA 0x0 2125#define RIGHT_ANTENNA 0x1 2126 2127#define TCHECK_TXSTATUS 500 2128#define TUPDATE_RXCOUNTER 100 2129 2130#endif 2131