sw.c revision 603be3885b9d518ff4822b357e2687b6ff02f1ac
1/****************************************************************************** 2 * 3 * Copyright(c) 2009-2010 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * The full GNU General Public License is included in this distribution in the 19 * file called LICENSE. 20 * 21 * Contact Information: 22 * wlanfae <wlanfae@realtek.com> 23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 24 * Hsinchu 300, Taiwan. 25 * 26 * Larry Finger <Larry.Finger@lwfinger.net> 27 * 28 *****************************************************************************/ 29 30#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 31 32#include <linux/vmalloc.h> 33 34#include "../wifi.h" 35#include "../core.h" 36#include "../pci.h" 37#include "reg.h" 38#include "def.h" 39#include "phy.h" 40#include "dm.h" 41#include "hw.h" 42#include "sw.h" 43#include "trx.h" 44#include "led.h" 45 46static void rtl92d_init_aspm_vars(struct ieee80211_hw *hw) 47{ 48 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 49 50 /*close ASPM for AMD defaultly */ 51 rtlpci->const_amdpci_aspm = 0; 52 53 /* 54 * ASPM PS mode. 55 * 0 - Disable ASPM, 56 * 1 - Enable ASPM without Clock Req, 57 * 2 - Enable ASPM with Clock Req, 58 * 3 - Alwyas Enable ASPM with Clock Req, 59 * 4 - Always Enable ASPM without Clock Req. 60 * set defult to RTL8192CE:3 RTL8192E:2 61 * */ 62 rtlpci->const_pci_aspm = 3; 63 64 /*Setting for PCI-E device */ 65 rtlpci->const_devicepci_aspm_setting = 0x03; 66 67 /*Setting for PCI-E bridge */ 68 rtlpci->const_hostpci_aspm_setting = 0x02; 69 70 /* 71 * In Hw/Sw Radio Off situation. 72 * 0 - Default, 73 * 1 - From ASPM setting without low Mac Pwr, 74 * 2 - From ASPM setting with low Mac Pwr, 75 * 3 - Bus D3 76 * set default to RTL8192CE:0 RTL8192SE:2 77 */ 78 rtlpci->const_hwsw_rfoff_d3 = 0; 79 80 /* 81 * This setting works for those device with 82 * backdoor ASPM setting such as EPHY setting. 83 * 0 - Not support ASPM, 84 * 1 - Support ASPM, 85 * 2 - According to chipset. 86 */ 87 rtlpci->const_support_pciaspm = 1; 88} 89 90static int rtl92d_init_sw_vars(struct ieee80211_hw *hw) 91{ 92 int err; 93 u8 tid; 94 struct rtl_priv *rtlpriv = rtl_priv(hw); 95 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 96 const struct firmware *firmware; 97 static int header_print; 98 99 rtlpriv->dm.dm_initialgain_enable = true; 100 rtlpriv->dm.dm_flag = 0; 101 rtlpriv->dm.disable_framebursting = 0; 102 rtlpriv->dm.thermalvalue = 0; 103 rtlpriv->dm.useramask = 1; 104 105 /* dual mac */ 106 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) 107 rtlpriv->phy.current_channel = 36; 108 else 109 rtlpriv->phy.current_channel = 1; 110 111 if (rtlpriv->rtlhal.macphymode != SINGLEMAC_SINGLEPHY) { 112 rtlpriv->rtlhal.disable_amsdu_8k = true; 113 /* No long RX - reduce fragmentation */ 114 rtlpci->rxbuffersize = 4096; 115 } 116 117 rtlpci->transmit_config = CFENDFORM | BIT(12) | BIT(13); 118 119 rtlpci->receive_config = ( 120 RCR_APPFCS 121 | RCR_AMF 122 | RCR_ADF 123 | RCR_APP_MIC 124 | RCR_APP_ICV 125 | RCR_AICV 126 | RCR_ACRC32 127 | RCR_AB 128 | RCR_AM 129 | RCR_APM 130 | RCR_APP_PHYST_RXFF 131 | RCR_HTC_LOC_CTRL 132 ); 133 134 rtlpci->irq_mask[0] = (u32) ( 135 IMR_ROK 136 | IMR_VODOK 137 | IMR_VIDOK 138 | IMR_BEDOK 139 | IMR_BKDOK 140 | IMR_MGNTDOK 141 | IMR_HIGHDOK 142 | IMR_BDOK 143 | IMR_RDU 144 | IMR_RXFOVW 145 ); 146 147 rtlpci->irq_mask[1] = (u32) (IMR_CPWM | IMR_C2HCMD); 148 149 /* for debug level */ 150 rtlpriv->dbg.global_debuglevel = rtlpriv->cfg->mod_params->debug; 151 /* for LPS & IPS */ 152 rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps; 153 rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps; 154 rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps; 155 if (!rtlpriv->psc.inactiveps) 156 pr_info("rtl8192ce: Power Save off (module option)\n"); 157 if (!rtlpriv->psc.fwctrl_lps) 158 pr_info("rtl8192ce: FW Power Save off (module option)\n"); 159 rtlpriv->psc.reg_fwctrl_lps = 3; 160 rtlpriv->psc.reg_max_lps_awakeintvl = 5; 161 /* for ASPM, you can close aspm through 162 * set const_support_pciaspm = 0 */ 163 rtl92d_init_aspm_vars(hw); 164 165 if (rtlpriv->psc.reg_fwctrl_lps == 1) 166 rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE; 167 else if (rtlpriv->psc.reg_fwctrl_lps == 2) 168 rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE; 169 else if (rtlpriv->psc.reg_fwctrl_lps == 3) 170 rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE; 171 172 /* for firmware buf */ 173 rtlpriv->rtlhal.pfirmware = vzalloc(0x8000); 174 if (!rtlpriv->rtlhal.pfirmware) { 175 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 176 ("Can't alloc buffer for fw.\n")); 177 return 1; 178 } 179 180 if (!header_print) { 181 pr_info("Driver for Realtek RTL8192DE WLAN interface\n"); 182 pr_info("Loading firmware file %s\n", rtlpriv->cfg->fw_name); 183 header_print++; 184 } 185 /* request fw */ 186 err = request_firmware(&firmware, rtlpriv->cfg->fw_name, 187 rtlpriv->io.dev); 188 if (err) { 189 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 190 ("Failed to request firmware!\n")); 191 return 1; 192 } 193 if (firmware->size > 0x8000) { 194 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 195 ("Firmware is too big!\n")); 196 release_firmware(firmware); 197 return 1; 198 } 199 memcpy(rtlpriv->rtlhal.pfirmware, firmware->data, firmware->size); 200 rtlpriv->rtlhal.fwsize = firmware->size; 201 release_firmware(firmware); 202 203 /* for early mode */ 204 rtlpriv->rtlhal.earlymode_enable = true; 205 for (tid = 0; tid < 8; tid++) 206 skb_queue_head_init(&rtlpriv->mac80211.skb_waitq[tid]); 207 return 0; 208} 209 210static void rtl92d_deinit_sw_vars(struct ieee80211_hw *hw) 211{ 212 struct rtl_priv *rtlpriv = rtl_priv(hw); 213 u8 tid; 214 215 if (rtlpriv->rtlhal.pfirmware) { 216 vfree(rtlpriv->rtlhal.pfirmware); 217 rtlpriv->rtlhal.pfirmware = NULL; 218 } 219 for (tid = 0; tid < 8; tid++) 220 skb_queue_purge(&rtlpriv->mac80211.skb_waitq[tid]); 221} 222 223static struct rtl_hal_ops rtl8192de_hal_ops = { 224 .init_sw_vars = rtl92d_init_sw_vars, 225 .deinit_sw_vars = rtl92d_deinit_sw_vars, 226 .read_eeprom_info = rtl92de_read_eeprom_info, 227 .interrupt_recognized = rtl92de_interrupt_recognized, 228 .hw_init = rtl92de_hw_init, 229 .hw_disable = rtl92de_card_disable, 230 .hw_suspend = rtl92de_suspend, 231 .hw_resume = rtl92de_resume, 232 .enable_interrupt = rtl92de_enable_interrupt, 233 .disable_interrupt = rtl92de_disable_interrupt, 234 .set_network_type = rtl92de_set_network_type, 235 .set_chk_bssid = rtl92de_set_check_bssid, 236 .set_qos = rtl92de_set_qos, 237 .set_bcn_reg = rtl92de_set_beacon_related_registers, 238 .set_bcn_intv = rtl92de_set_beacon_interval, 239 .update_interrupt_mask = rtl92de_update_interrupt_mask, 240 .get_hw_reg = rtl92de_get_hw_reg, 241 .set_hw_reg = rtl92de_set_hw_reg, 242 .update_rate_tbl = rtl92de_update_hal_rate_tbl, 243 .fill_tx_desc = rtl92de_tx_fill_desc, 244 .fill_tx_cmddesc = rtl92de_tx_fill_cmddesc, 245 .query_rx_desc = rtl92de_rx_query_desc, 246 .set_channel_access = rtl92de_update_channel_access_setting, 247 .radio_onoff_checking = rtl92de_gpio_radio_on_off_checking, 248 .set_bw_mode = rtl92d_phy_set_bw_mode, 249 .switch_channel = rtl92d_phy_sw_chnl, 250 .dm_watchdog = rtl92d_dm_watchdog, 251 .scan_operation_backup = rtl92d_phy_scan_operation_backup, 252 .set_rf_power_state = rtl92d_phy_set_rf_power_state, 253 .led_control = rtl92de_led_control, 254 .set_desc = rtl92de_set_desc, 255 .get_desc = rtl92de_get_desc, 256 .tx_polling = rtl92de_tx_polling, 257 .enable_hw_sec = rtl92de_enable_hw_security_config, 258 .set_key = rtl92de_set_key, 259 .init_sw_leds = rtl92de_init_sw_leds, 260 .get_bbreg = rtl92d_phy_query_bb_reg, 261 .set_bbreg = rtl92d_phy_set_bb_reg, 262 .get_rfreg = rtl92d_phy_query_rf_reg, 263 .set_rfreg = rtl92d_phy_set_rf_reg, 264 .linked_set_reg = rtl92d_linked_set_reg, 265}; 266 267static struct rtl_mod_params rtl92de_mod_params = { 268 .sw_crypto = false, 269 .inactiveps = true, 270 .swctrl_lps = true, 271 .fwctrl_lps = false, 272 .debug = DBG_EMERG, 273}; 274 275static struct rtl_hal_cfg rtl92de_hal_cfg = { 276 .bar_id = 2, 277 .write_readback = true, 278 .name = "rtl8192de", 279 .fw_name = "rtlwifi/rtl8192defw.bin", 280 .ops = &rtl8192de_hal_ops, 281 .mod_params = &rtl92de_mod_params, 282 283 .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL, 284 .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN, 285 .maps[SYS_CLK] = REG_SYS_CLKR, 286 .maps[MAC_RCR_AM] = RCR_AM, 287 .maps[MAC_RCR_AB] = RCR_AB, 288 .maps[MAC_RCR_ACRC32] = RCR_ACRC32, 289 .maps[MAC_RCR_ACF] = RCR_ACF, 290 .maps[MAC_RCR_AAP] = RCR_AAP, 291 292 .maps[EFUSE_TEST] = REG_EFUSE_TEST, 293 .maps[EFUSE_CTRL] = REG_EFUSE_CTRL, 294 .maps[EFUSE_CLK] = 0, /* just for 92se */ 295 .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL, 296 .maps[EFUSE_PWC_EV12V] = PWC_EV12V, 297 .maps[EFUSE_FEN_ELDR] = FEN_ELDR, 298 .maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN, 299 .maps[EFUSE_ANA8M] = 0, /* just for 92se */ 300 .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE, 301 .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION, 302 .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN, 303 304 .maps[RWCAM] = REG_CAMCMD, 305 .maps[WCAMI] = REG_CAMWRITE, 306 .maps[RCAMO] = REG_CAMREAD, 307 .maps[CAMDBG] = REG_CAMDBG, 308 .maps[SECR] = REG_SECCFG, 309 .maps[SEC_CAM_NONE] = CAM_NONE, 310 .maps[SEC_CAM_WEP40] = CAM_WEP40, 311 .maps[SEC_CAM_TKIP] = CAM_TKIP, 312 .maps[SEC_CAM_AES] = CAM_AES, 313 .maps[SEC_CAM_WEP104] = CAM_WEP104, 314 315 .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6, 316 .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5, 317 .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4, 318 .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3, 319 .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2, 320 .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1, 321 .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8, 322 .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7, 323 .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6, 324 .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5, 325 .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4, 326 .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3, 327 .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2, 328 .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1, 329 .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2, 330 .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1, 331 332 .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW, 333 .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT, 334 .maps[RTL_IMR_BcnInt] = IMR_BcnInt, 335 .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW, 336 .maps[RTL_IMR_RDU] = IMR_RDU, 337 .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND, 338 .maps[RTL_IMR_BDOK] = IMR_BDOK, 339 .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK, 340 .maps[RTL_IMR_TBDER] = IMR_TBDER, 341 .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK, 342 .maps[RTL_IMR_TBDOK] = IMR_TBDOK, 343 .maps[RTL_IMR_BKDOK] = IMR_BKDOK, 344 .maps[RTL_IMR_BEDOK] = IMR_BEDOK, 345 .maps[RTL_IMR_VIDOK] = IMR_VIDOK, 346 .maps[RTL_IMR_VODOK] = IMR_VODOK, 347 .maps[RTL_IMR_ROK] = IMR_ROK, 348 .maps[RTL_IBSS_INT_MASKS] = (IMR_BcnInt | IMR_TBDOK | IMR_TBDER), 349 350 .maps[RTL_RC_CCK_RATE1M] = DESC92_RATE1M, 351 .maps[RTL_RC_CCK_RATE2M] = DESC92_RATE2M, 352 .maps[RTL_RC_CCK_RATE5_5M] = DESC92_RATE5_5M, 353 .maps[RTL_RC_CCK_RATE11M] = DESC92_RATE11M, 354 .maps[RTL_RC_OFDM_RATE6M] = DESC92_RATE6M, 355 .maps[RTL_RC_OFDM_RATE9M] = DESC92_RATE9M, 356 .maps[RTL_RC_OFDM_RATE12M] = DESC92_RATE12M, 357 .maps[RTL_RC_OFDM_RATE18M] = DESC92_RATE18M, 358 .maps[RTL_RC_OFDM_RATE24M] = DESC92_RATE24M, 359 .maps[RTL_RC_OFDM_RATE36M] = DESC92_RATE36M, 360 .maps[RTL_RC_OFDM_RATE48M] = DESC92_RATE48M, 361 .maps[RTL_RC_OFDM_RATE54M] = DESC92_RATE54M, 362 363 .maps[RTL_RC_HT_RATEMCS7] = DESC92_RATEMCS7, 364 .maps[RTL_RC_HT_RATEMCS15] = DESC92_RATEMCS15, 365}; 366 367static struct pci_device_id rtl92de_pci_ids[] __devinitdata = { 368 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8193, rtl92de_hal_cfg)}, 369 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x002B, rtl92de_hal_cfg)}, 370 {}, 371}; 372 373MODULE_DEVICE_TABLE(pci, rtl92de_pci_ids); 374 375MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>"); 376MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>"); 377MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>"); 378MODULE_LICENSE("GPL"); 379MODULE_DESCRIPTION("Realtek 8192DE 802.11n Dual Mac PCI wireless"); 380MODULE_FIRMWARE("rtlwifi/rtl8192defw.bin"); 381 382module_param_named(swenc, rtl92de_mod_params.sw_crypto, bool, 0444); 383module_param_named(debug, rtl92de_mod_params.debug, int, 0444); 384module_param_named(ips, rtl92de_mod_params.inactiveps, bool, 0444); 385module_param_named(swlps, rtl92de_mod_params.swctrl_lps, bool, 0444); 386module_param_named(fwlps, rtl92de_mod_params.fwctrl_lps, bool, 0444); 387MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n"); 388MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n"); 389MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n"); 390MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 1)\n"); 391MODULE_PARM_DESC(debug, "Set debug level (0-5) (default 0)"); 392 393static const struct dev_pm_ops rtlwifi_pm_ops = { 394 .suspend = rtl_pci_suspend, 395 .resume = rtl_pci_resume, 396 .freeze = rtl_pci_suspend, 397 .thaw = rtl_pci_resume, 398 .poweroff = rtl_pci_suspend, 399 .restore = rtl_pci_resume, 400}; 401 402static struct pci_driver rtl92de_driver = { 403 .name = KBUILD_MODNAME, 404 .id_table = rtl92de_pci_ids, 405 .probe = rtl_pci_probe, 406 .remove = rtl_pci_disconnect, 407 .driver.pm = &rtlwifi_pm_ops, 408}; 409 410/* add global spin lock to solve the problem that 411 * Dul mac register operation on the same time */ 412spinlock_t globalmutex_power; 413spinlock_t globalmutex_for_fwdownload; 414spinlock_t globalmutex_for_power_and_efuse; 415 416static int __init rtl92de_module_init(void) 417{ 418 int ret = 0; 419 420 spin_lock_init(&globalmutex_power); 421 spin_lock_init(&globalmutex_for_fwdownload); 422 spin_lock_init(&globalmutex_for_power_and_efuse); 423 424 ret = pci_register_driver(&rtl92de_driver); 425 if (ret) 426 RT_ASSERT(false, (": No device found\n")); 427 return ret; 428} 429 430static void __exit rtl92de_module_exit(void) 431{ 432 pci_unregister_driver(&rtl92de_driver); 433} 434 435module_init(rtl92de_module_init); 436module_exit(rtl92de_module_exit); 437