sw.c revision c0386f1584127442d0f2aea41bc948056d6b1337
1/****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * The full GNU General Public License is included in this distribution in the 19 * file called LICENSE. 20 * 21 * Contact Information: 22 * wlanfae <wlanfae@realtek.com> 23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 24 * Hsinchu 300, Taiwan. 25 * 26 * Larry Finger <Larry.Finger@lwfinger.net> 27 * 28 *****************************************************************************/ 29 30#include "../wifi.h" 31#include "../core.h" 32#include "../pci.h" 33#include "../base.h" 34#include "reg.h" 35#include "def.h" 36#include "phy.h" 37#include "dm.h" 38#include "hw.h" 39#include "sw.h" 40#include "trx.h" 41#include "led.h" 42 43#include <linux/module.h> 44 45static void rtl92d_init_aspm_vars(struct ieee80211_hw *hw) 46{ 47 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 48 49 /*close ASPM for AMD defaultly */ 50 rtlpci->const_amdpci_aspm = 0; 51 52 /* 53 * ASPM PS mode. 54 * 0 - Disable ASPM, 55 * 1 - Enable ASPM without Clock Req, 56 * 2 - Enable ASPM with Clock Req, 57 * 3 - Alwyas Enable ASPM with Clock Req, 58 * 4 - Always Enable ASPM without Clock Req. 59 * set defult to RTL8192CE:3 RTL8192E:2 60 * */ 61 rtlpci->const_pci_aspm = 3; 62 63 /*Setting for PCI-E device */ 64 rtlpci->const_devicepci_aspm_setting = 0x03; 65 66 /*Setting for PCI-E bridge */ 67 rtlpci->const_hostpci_aspm_setting = 0x02; 68 69 /* 70 * In Hw/Sw Radio Off situation. 71 * 0 - Default, 72 * 1 - From ASPM setting without low Mac Pwr, 73 * 2 - From ASPM setting with low Mac Pwr, 74 * 3 - Bus D3 75 * set default to RTL8192CE:0 RTL8192SE:2 76 */ 77 rtlpci->const_hwsw_rfoff_d3 = 0; 78 79 /* 80 * This setting works for those device with 81 * backdoor ASPM setting such as EPHY setting. 82 * 0 - Not support ASPM, 83 * 1 - Support ASPM, 84 * 2 - According to chipset. 85 */ 86 rtlpci->const_support_pciaspm = 1; 87} 88 89static int rtl92d_init_sw_vars(struct ieee80211_hw *hw) 90{ 91 int err; 92 u8 tid; 93 struct rtl_priv *rtlpriv = rtl_priv(hw); 94 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 95 96 rtlpriv->dm.dm_initialgain_enable = true; 97 rtlpriv->dm.dm_flag = 0; 98 rtlpriv->dm.disable_framebursting = false; 99 rtlpriv->dm.thermalvalue = 0; 100 rtlpriv->dm.useramask = true; 101 102 /* dual mac */ 103 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) 104 rtlpriv->phy.current_channel = 36; 105 else 106 rtlpriv->phy.current_channel = 1; 107 108 if (rtlpriv->rtlhal.macphymode != SINGLEMAC_SINGLEPHY) { 109 rtlpriv->rtlhal.disable_amsdu_8k = true; 110 /* No long RX - reduce fragmentation */ 111 rtlpci->rxbuffersize = 4096; 112 } 113 114 rtlpci->transmit_config = CFENDFORM | BIT(12) | BIT(13); 115 116 rtlpci->receive_config = ( 117 RCR_APPFCS 118 | RCR_AMF 119 | RCR_ADF 120 | RCR_APP_MIC 121 | RCR_APP_ICV 122 | RCR_AICV 123 | RCR_ACRC32 124 | RCR_AB 125 | RCR_AM 126 | RCR_APM 127 | RCR_APP_PHYST_RXFF 128 | RCR_HTC_LOC_CTRL 129 ); 130 131 rtlpci->irq_mask[0] = (u32) ( 132 IMR_ROK 133 | IMR_VODOK 134 | IMR_VIDOK 135 | IMR_BEDOK 136 | IMR_BKDOK 137 | IMR_MGNTDOK 138 | IMR_HIGHDOK 139 | IMR_BDOK 140 | IMR_RDU 141 | IMR_RXFOVW 142 ); 143 144 rtlpci->irq_mask[1] = (u32) (IMR_CPWM | IMR_C2HCMD); 145 146 /* for debug level */ 147 rtlpriv->dbg.global_debuglevel = rtlpriv->cfg->mod_params->debug; 148 /* for LPS & IPS */ 149 rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps; 150 rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps; 151 rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps; 152 if (!rtlpriv->psc.inactiveps) 153 pr_info("Power Save off (module option)\n"); 154 if (!rtlpriv->psc.fwctrl_lps) 155 pr_info("FW Power Save off (module option)\n"); 156 rtlpriv->psc.reg_fwctrl_lps = 3; 157 rtlpriv->psc.reg_max_lps_awakeintvl = 5; 158 /* for ASPM, you can close aspm through 159 * set const_support_pciaspm = 0 */ 160 rtl92d_init_aspm_vars(hw); 161 162 if (rtlpriv->psc.reg_fwctrl_lps == 1) 163 rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE; 164 else if (rtlpriv->psc.reg_fwctrl_lps == 2) 165 rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE; 166 else if (rtlpriv->psc.reg_fwctrl_lps == 3) 167 rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE; 168 169 /* for early mode */ 170 rtlpriv->rtlhal.earlymode_enable = false; 171 for (tid = 0; tid < 8; tid++) 172 skb_queue_head_init(&rtlpriv->mac80211.skb_waitq[tid]); 173 174 /* for firmware buf */ 175 rtlpriv->rtlhal.pfirmware = vzalloc(0x8000); 176 if (!rtlpriv->rtlhal.pfirmware) { 177 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 178 "Can't alloc buffer for fw\n"); 179 return 1; 180 } 181 182 rtlpriv->max_fw_size = 0x8000; 183 pr_info("Driver for Realtek RTL8192DE WLAN interface\n"); 184 pr_info("Loading firmware file %s\n", rtlpriv->cfg->fw_name); 185 186 /* request fw */ 187 err = request_firmware_nowait(THIS_MODULE, 1, rtlpriv->cfg->fw_name, 188 rtlpriv->io.dev, GFP_KERNEL, hw, 189 rtl_fw_cb); 190 if (err) { 191 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 192 "Failed to request firmware!\n"); 193 return 1; 194 } 195 196 return 0; 197} 198 199static void rtl92d_deinit_sw_vars(struct ieee80211_hw *hw) 200{ 201 struct rtl_priv *rtlpriv = rtl_priv(hw); 202 u8 tid; 203 204 if (rtlpriv->rtlhal.pfirmware) { 205 vfree(rtlpriv->rtlhal.pfirmware); 206 rtlpriv->rtlhal.pfirmware = NULL; 207 } 208 for (tid = 0; tid < 8; tid++) 209 skb_queue_purge(&rtlpriv->mac80211.skb_waitq[tid]); 210} 211 212static struct rtl_hal_ops rtl8192de_hal_ops = { 213 .init_sw_vars = rtl92d_init_sw_vars, 214 .deinit_sw_vars = rtl92d_deinit_sw_vars, 215 .read_eeprom_info = rtl92de_read_eeprom_info, 216 .interrupt_recognized = rtl92de_interrupt_recognized, 217 .hw_init = rtl92de_hw_init, 218 .hw_disable = rtl92de_card_disable, 219 .hw_suspend = rtl92de_suspend, 220 .hw_resume = rtl92de_resume, 221 .enable_interrupt = rtl92de_enable_interrupt, 222 .disable_interrupt = rtl92de_disable_interrupt, 223 .set_network_type = rtl92de_set_network_type, 224 .set_chk_bssid = rtl92de_set_check_bssid, 225 .set_qos = rtl92de_set_qos, 226 .set_bcn_reg = rtl92de_set_beacon_related_registers, 227 .set_bcn_intv = rtl92de_set_beacon_interval, 228 .update_interrupt_mask = rtl92de_update_interrupt_mask, 229 .get_hw_reg = rtl92de_get_hw_reg, 230 .set_hw_reg = rtl92de_set_hw_reg, 231 .update_rate_tbl = rtl92de_update_hal_rate_tbl, 232 .fill_tx_desc = rtl92de_tx_fill_desc, 233 .fill_tx_cmddesc = rtl92de_tx_fill_cmddesc, 234 .query_rx_desc = rtl92de_rx_query_desc, 235 .set_channel_access = rtl92de_update_channel_access_setting, 236 .radio_onoff_checking = rtl92de_gpio_radio_on_off_checking, 237 .set_bw_mode = rtl92d_phy_set_bw_mode, 238 .switch_channel = rtl92d_phy_sw_chnl, 239 .dm_watchdog = rtl92d_dm_watchdog, 240 .scan_operation_backup = rtl_phy_scan_operation_backup, 241 .set_rf_power_state = rtl92d_phy_set_rf_power_state, 242 .led_control = rtl92de_led_control, 243 .set_desc = rtl92de_set_desc, 244 .get_desc = rtl92de_get_desc, 245 .tx_polling = rtl92de_tx_polling, 246 .enable_hw_sec = rtl92de_enable_hw_security_config, 247 .set_key = rtl92de_set_key, 248 .init_sw_leds = rtl92de_init_sw_leds, 249 .get_bbreg = rtl92d_phy_query_bb_reg, 250 .set_bbreg = rtl92d_phy_set_bb_reg, 251 .get_rfreg = rtl92d_phy_query_rf_reg, 252 .set_rfreg = rtl92d_phy_set_rf_reg, 253 .linked_set_reg = rtl92d_linked_set_reg, 254 .get_btc_status = rtl_btc_status_false, 255}; 256 257static struct rtl_mod_params rtl92de_mod_params = { 258 .sw_crypto = false, 259 .inactiveps = true, 260 .swctrl_lps = true, 261 .fwctrl_lps = false, 262 .debug = DBG_EMERG, 263}; 264 265static struct rtl_hal_cfg rtl92de_hal_cfg = { 266 .bar_id = 2, 267 .write_readback = true, 268 .name = "rtl8192de", 269 .fw_name = "rtlwifi/rtl8192defw.bin", 270 .ops = &rtl8192de_hal_ops, 271 .mod_params = &rtl92de_mod_params, 272 273 .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL, 274 .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN, 275 .maps[SYS_CLK] = REG_SYS_CLKR, 276 .maps[MAC_RCR_AM] = RCR_AM, 277 .maps[MAC_RCR_AB] = RCR_AB, 278 .maps[MAC_RCR_ACRC32] = RCR_ACRC32, 279 .maps[MAC_RCR_ACF] = RCR_ACF, 280 .maps[MAC_RCR_AAP] = RCR_AAP, 281 282 .maps[EFUSE_TEST] = REG_EFUSE_TEST, 283 .maps[EFUSE_CTRL] = REG_EFUSE_CTRL, 284 .maps[EFUSE_CLK] = 0, /* just for 92se */ 285 .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL, 286 .maps[EFUSE_PWC_EV12V] = PWC_EV12V, 287 .maps[EFUSE_FEN_ELDR] = FEN_ELDR, 288 .maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN, 289 .maps[EFUSE_ANA8M] = 0, /* just for 92se */ 290 .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE, 291 .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION, 292 .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN, 293 294 .maps[RWCAM] = REG_CAMCMD, 295 .maps[WCAMI] = REG_CAMWRITE, 296 .maps[RCAMO] = REG_CAMREAD, 297 .maps[CAMDBG] = REG_CAMDBG, 298 .maps[SECR] = REG_SECCFG, 299 .maps[SEC_CAM_NONE] = CAM_NONE, 300 .maps[SEC_CAM_WEP40] = CAM_WEP40, 301 .maps[SEC_CAM_TKIP] = CAM_TKIP, 302 .maps[SEC_CAM_AES] = CAM_AES, 303 .maps[SEC_CAM_WEP104] = CAM_WEP104, 304 305 .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6, 306 .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5, 307 .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4, 308 .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3, 309 .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2, 310 .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1, 311 .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8, 312 .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7, 313 .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6, 314 .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5, 315 .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4, 316 .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3, 317 .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2, 318 .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1, 319 .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2, 320 .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1, 321 322 .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW, 323 .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT, 324 .maps[RTL_IMR_BCNINT] = IMR_BCNINT, 325 .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW, 326 .maps[RTL_IMR_RDU] = IMR_RDU, 327 .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND, 328 .maps[RTL_IMR_BDOK] = IMR_BDOK, 329 .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK, 330 .maps[RTL_IMR_TBDER] = IMR_TBDER, 331 .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK, 332 .maps[RTL_IMR_TBDOK] = IMR_TBDOK, 333 .maps[RTL_IMR_BKDOK] = IMR_BKDOK, 334 .maps[RTL_IMR_BEDOK] = IMR_BEDOK, 335 .maps[RTL_IMR_VIDOK] = IMR_VIDOK, 336 .maps[RTL_IMR_VODOK] = IMR_VODOK, 337 .maps[RTL_IMR_ROK] = IMR_ROK, 338 .maps[RTL_IBSS_INT_MASKS] = (IMR_BCNINT | IMR_TBDOK | IMR_TBDER), 339 340 .maps[RTL_RC_CCK_RATE1M] = DESC92_RATE1M, 341 .maps[RTL_RC_CCK_RATE2M] = DESC92_RATE2M, 342 .maps[RTL_RC_CCK_RATE5_5M] = DESC92_RATE5_5M, 343 .maps[RTL_RC_CCK_RATE11M] = DESC92_RATE11M, 344 .maps[RTL_RC_OFDM_RATE6M] = DESC92_RATE6M, 345 .maps[RTL_RC_OFDM_RATE9M] = DESC92_RATE9M, 346 .maps[RTL_RC_OFDM_RATE12M] = DESC92_RATE12M, 347 .maps[RTL_RC_OFDM_RATE18M] = DESC92_RATE18M, 348 .maps[RTL_RC_OFDM_RATE24M] = DESC92_RATE24M, 349 .maps[RTL_RC_OFDM_RATE36M] = DESC92_RATE36M, 350 .maps[RTL_RC_OFDM_RATE48M] = DESC92_RATE48M, 351 .maps[RTL_RC_OFDM_RATE54M] = DESC92_RATE54M, 352 353 .maps[RTL_RC_HT_RATEMCS7] = DESC92_RATEMCS7, 354 .maps[RTL_RC_HT_RATEMCS15] = DESC92_RATEMCS15, 355}; 356 357static struct pci_device_id rtl92de_pci_ids[] = { 358 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8193, rtl92de_hal_cfg)}, 359 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x002B, rtl92de_hal_cfg)}, 360 {}, 361}; 362 363MODULE_DEVICE_TABLE(pci, rtl92de_pci_ids); 364 365MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>"); 366MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>"); 367MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>"); 368MODULE_LICENSE("GPL"); 369MODULE_DESCRIPTION("Realtek 8192DE 802.11n Dual Mac PCI wireless"); 370MODULE_FIRMWARE("rtlwifi/rtl8192defw.bin"); 371 372module_param_named(swenc, rtl92de_mod_params.sw_crypto, bool, 0444); 373module_param_named(debug, rtl92de_mod_params.debug, int, 0444); 374module_param_named(ips, rtl92de_mod_params.inactiveps, bool, 0444); 375module_param_named(swlps, rtl92de_mod_params.swctrl_lps, bool, 0444); 376module_param_named(fwlps, rtl92de_mod_params.fwctrl_lps, bool, 0444); 377MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n"); 378MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n"); 379MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n"); 380MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 1)\n"); 381MODULE_PARM_DESC(debug, "Set debug level (0-5) (default 0)"); 382 383static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume); 384 385static struct pci_driver rtl92de_driver = { 386 .name = KBUILD_MODNAME, 387 .id_table = rtl92de_pci_ids, 388 .probe = rtl_pci_probe, 389 .remove = rtl_pci_disconnect, 390 .driver.pm = &rtlwifi_pm_ops, 391}; 392 393/* add global spin lock to solve the problem that 394 * Dul mac register operation on the same time */ 395spinlock_t globalmutex_power; 396spinlock_t globalmutex_for_fwdownload; 397spinlock_t globalmutex_for_power_and_efuse; 398 399static int __init rtl92de_module_init(void) 400{ 401 int ret = 0; 402 403 spin_lock_init(&globalmutex_power); 404 spin_lock_init(&globalmutex_for_fwdownload); 405 spin_lock_init(&globalmutex_for_power_and_efuse); 406 407 ret = pci_register_driver(&rtl92de_driver); 408 if (ret) 409 RT_ASSERT(false, "No device found\n"); 410 return ret; 411} 412 413static void __exit rtl92de_module_exit(void) 414{ 415 pci_unregister_driver(&rtl92de_driver); 416} 417 418module_init(rtl92de_module_init); 419module_exit(rtl92de_module_exit); 420