def.h revision dac67975f3dc8565e4254b1d7a49618494f1a2f1
1e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li/****************************************************************************** 2e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li * 3ca742cd9766ff519b0e927a9296e29541ee13c7bLarry Finger * Copyright(c) 2009-2012 Realtek Corporation. 4e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li * 5e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li * This program is free software; you can redistribute it and/or modify it 6e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li * under the terms of version 2 of the GNU General Public License as 7e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li * published by the Free Software Foundation. 8e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li * 9e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li * This program is distributed in the hope that it will be useful, but WITHOUT 10e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li * more details. 13e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li * 14e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li * You should have received a copy of the GNU General Public License along with 15e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li * this program; if not, write to the Free Software Foundation, Inc., 16e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li * 18e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li * The full GNU General Public License is included in this distribution in the 19e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li * file called LICENSE. 20e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li * 21e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li * Contact Information: 22e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li * wlanfae <wlanfae@realtek.com> 23e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 24e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li * Hsinchu 300, Taiwan. 25e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li * 26e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li * Larry Finger <Larry.Finger@lwfinger.net> 27e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li * 28e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li *****************************************************************************/ 29e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#ifndef __REALTEK_92S_DEF_H__ 30e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define __REALTEK_92S_DEF_H__ 31e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li 32e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define RX_MPDU_QUEUE 0 33e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define RX_CMD_QUEUE 1 34e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define RX_MAX_QUEUE 2 35e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li 36e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SHORT_SLOT_TIME 9 37e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define NON_SHORT_SLOT_TIME 20 38e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li 39e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li/* Rx smooth factor */ 40e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define RX_SMOOTH_FACTOR 20 41e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li 42e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li/* Queue Select Value in TxDesc */ 43e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define QSLT_BK 0x2 44e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define QSLT_BE 0x0 45e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define QSLT_VI 0x5 46e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define QSLT_VO 0x6 47e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define QSLT_BEACON 0x10 48e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define QSLT_HIGH 0x11 49e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define QSLT_MGNT 0x12 50e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define QSLT_CMD 0x13 51e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li 52e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define PHY_RSSI_SLID_WIN_MAX 100 53e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define PHY_LINKQUALITY_SLID_WIN_MAX 20 54e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define PHY_BEACON_RSSI_SLID_WIN_MAX 10 55e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li 56e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li/* Tx Desc */ 57e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define TX_DESC_SIZE_RTL8192S (16 * 4) 58e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define TX_CMDDESC_SIZE_RTL8192S (16 * 4) 59e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li 60e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li/* Define a macro that takes a le32 word, converts it to host ordering, 61e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li * right shifts by a specified count, creates a mask of the specified 62e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li * bit count, and extracts that number of bits. 63e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li */ 64e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li 65e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SHIFT_AND_MASK_LE(__pdesc, __shift, __mask) \ 66e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li ((le32_to_cpu(*(((__le32 *)(__pdesc)))) >> (__shift)) & \ 67e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li BIT_LEN_MASK_32(__mask)) 68e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li 69e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li/* Define a macro that clears a bit field in an le32 word and 70e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li * sets the specified value into that bit field. The resulting 71e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li * value remains in le32 ordering; however, it is properly converted 72e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li * to host ordering for the clear and set operations before conversion 73e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li * back to le32. 74e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li */ 75e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li 76e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_BITS_OFFSET_LE(__pdesc, __shift, __len, __val) \ 77e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li (*(__le32 *)(__pdesc) = \ 78e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li (cpu_to_le32((le32_to_cpu(*((__le32 *)(__pdesc))) & \ 79e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li (~(BIT_OFFSET_LEN_MASK_32((__shift), __len)))) | \ 80e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li (((u32)(__val) & BIT_LEN_MASK_32(__len)) << (__shift))))); 81e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li 82e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li/* macros to read/write various fields in RX or TX descriptors */ 83e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li 84e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li/* Dword 0 */ 85e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_PKT_SIZE(__pdesc, __val) \ 86e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc, 0, 16, __val) 87e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_OFFSET(__pdesc, __val) \ 88e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc, 16, 8, __val) 89e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_TYPE(__pdesc, __val) \ 90e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc, 24, 2, __val) 91e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_LAST_SEG(__pdesc, __val) \ 92e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc, 26, 1, __val) 93e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_FIRST_SEG(__pdesc, __val) \ 94e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc, 27, 1, __val) 95e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_LINIP(__pdesc, __val) \ 96e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc, 28, 1, __val) 97e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_AMSDU(__pdesc, __val) \ 98e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc, 29, 1, __val) 99e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_GREEN_FIELD(__pdesc, __val) \ 100e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc, 30, 1, __val) 101e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_OWN(__pdesc, __val) \ 102e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc, 31, 1, __val) 103e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li 104e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define GET_TX_DESC_OWN(__pdesc) \ 105e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SHIFT_AND_MASK_LE(__pdesc, 31, 1) 106e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li 107e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li/* Dword 1 */ 108e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_MACID(__pdesc, __val) \ 109e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 4, 0, 5, __val) 110e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_MORE_DATA(__pdesc, __val) \ 111e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 4, 5, 1, __val) 112e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_MORE_FRAG(__pdesc, __val) \ 113e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 4, 6, 1, __val) 114e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_PIFS(__pdesc, __val) \ 115e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 4, 7, 1, __val) 116e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_QUEUE_SEL(__pdesc, __val) \ 117e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 4, 8, 5, __val) 118e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_ACK_POLICY(__pdesc, __val) \ 119e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 4, 13, 2, __val) 120e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_NO_ACM(__pdesc, __val) \ 121e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 4, 15, 1, __val) 122e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_NON_QOS(__pdesc, __val) \ 123e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 4, 16, 1, __val) 124e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_KEY_ID(__pdesc, __val) \ 125e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 4, 17, 2, __val) 126e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_OUI(__pdesc, __val) \ 127e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 4, 19, 1, __val) 128e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_PKT_TYPE(__pdesc, __val) \ 129e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 4, 20, 1, __val) 130e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_EN_DESC_ID(__pdesc, __val) \ 131e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 4, 21, 1, __val) 132e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_SEC_TYPE(__pdesc, __val) \ 133e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 4, 22, 2, __val) 134e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_WDS(__pdesc, __val) \ 135e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 4, 24, 1, __val) 136e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_HTC(__pdesc, __val) \ 137e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 4, 25, 1, __val) 138e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_PKT_OFFSET(__pdesc, __val) \ 139e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 4, 26, 5, __val) 140e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_HWPC(__pdesc, __val) \ 141e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 4, 27, 1, __val) 142e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li 143e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li/* Dword 2 */ 144e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_DATA_RETRY_LIMIT(__pdesc, __val) \ 145e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 8, 0, 6, __val) 146e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_RETRY_LIMIT_ENABLE(__pdesc, __val) \ 147e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 8, 6, 1, __val) 148e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_TSFL(__pdesc, __val) \ 149e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 8, 7, 5, __val) 150e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_RTS_RETRY_COUNT(__pdesc, __val) \ 151e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 8, 12, 6, __val) 152e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_DATA_RETRY_COUNT(__pdesc, __val) \ 153e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 8, 18, 6, __val) 154e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_RSVD_MACID(__pdesc, __val) \ 155e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(((__pdesc) + 8), 24, 5, __val) 156e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_AGG_ENABLE(__pdesc, __val) \ 157e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 8, 29, 1, __val) 158e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_AGG_BREAK(__pdesc, __val) \ 159e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 8, 30, 1, __val) 160e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_OWN_MAC(__pdesc, __val) \ 161e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 8, 31, 1, __val) 162e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li 163e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li/* Dword 3 */ 164e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_NEXT_HEAP_PAGE(__pdesc, __val) \ 165e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 12, 0, 8, __val) 166e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_TAIL_PAGE(__pdesc, __val) \ 167e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 12, 8, 8, __val) 168e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_SEQ(__pdesc, __val) \ 169e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 12, 16, 12, __val) 170e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_FRAG(__pdesc, __val) \ 171e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 12, 28, 4, __val) 172e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li 173e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li/* Dword 4 */ 174e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_RTS_RATE(__pdesc, __val) \ 175e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 16, 0, 6, __val) 176e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_DISABLE_RTS_FB(__pdesc, __val) \ 177e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 16, 6, 1, __val) 178e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_RTS_RATE_FB_LIMIT(__pdesc, __val) \ 179e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 16, 7, 4, __val) 180e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_CTS_ENABLE(__pdesc, __val) \ 181e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 16, 11, 1, __val) 182e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_RTS_ENABLE(__pdesc, __val) \ 183e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 16, 12, 1, __val) 184e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_RA_BRSR_ID(__pdesc, __val) \ 185e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 16, 13, 3, __val) 186e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_TXHT(__pdesc, __val) \ 187e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 16, 16, 1, __val) 188e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_TX_SHORT(__pdesc, __val) \ 189e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 16, 17, 1, __val) 190e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_TX_BANDWIDTH(__pdesc, __val) \ 191e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 16, 18, 1, __val) 192e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_TX_SUB_CARRIER(__pdesc, __val) \ 193e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 16, 19, 2, __val) 194e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_TX_STBC(__pdesc, __val) \ 195e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 16, 21, 2, __val) 196e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_TX_REVERSE_DIRECTION(__pdesc, __val) \ 197e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 16, 23, 1, __val) 198e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_RTS_HT(__pdesc, __val) \ 199e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 16, 24, 1, __val) 200e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_RTS_SHORT(__pdesc, __val) \ 201e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 16, 25, 1, __val) 202e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_RTS_BANDWIDTH(__pdesc, __val) \ 203e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 16, 26, 1, __val) 204e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_RTS_SUB_CARRIER(__pdesc, __val) \ 205e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 16, 27, 2, __val) 206e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_RTS_STBC(__pdesc, __val) \ 207e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 16, 29, 2, __val) 208e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_USER_RATE(__pdesc, __val) \ 209e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 16, 31, 1, __val) 210e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li 211e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li/* Dword 5 */ 212e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_PACKET_ID(__pdesc, __val) \ 213e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 20, 0, 9, __val) 214e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_TX_RATE(__pdesc, __val) \ 215e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 20, 9, 6, __val) 216e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_DISABLE_FB(__pdesc, __val) \ 217e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 20, 15, 1, __val) 218e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_DATA_RATE_FB_LIMIT(__pdesc, __val) \ 219e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 20, 16, 5, __val) 220e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_TX_AGC(__pdesc, __val) \ 221e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 20, 21, 11, __val) 222e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li 223e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li/* Dword 6 */ 224e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_IP_CHECK_SUM(__pdesc, __val) \ 225e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 24, 0, 16, __val) 226e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_TCP_CHECK_SUM(__pdesc, __val) \ 227e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 24, 16, 16, __val) 228e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li 229e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li/* Dword 7 */ 230e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_TX_BUFFER_SIZE(__pdesc, __val) \ 231e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 28, 0, 16, __val) 232e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_IP_HEADER_OFFSET(__pdesc, __val) \ 233e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 28, 16, 8, __val) 234e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_TCP_ENABLE(__pdesc, __val) \ 235e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 28, 31, 1, __val) 236e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li 237e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li/* Dword 8 */ 238e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc, __val) \ 239e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 32, 0, 32, __val) 240e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define GET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc) \ 241e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SHIFT_AND_MASK_LE(__pdesc + 32, 0, 32) 242e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li 243e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li/* Dword 9 */ 244e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_TX_DESC_NEXT_DESC_ADDRESS(__pdesc, __val) \ 245e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 36, 0, 32, __val) 246e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li 247e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li/* Because the PCI Tx descriptors are chaied at the 248e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li * initialization and all the NextDescAddresses in 249e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li * these descriptors cannot not be cleared (,or 250e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li * driver/HW cannot find the next descriptor), the 251e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li * offset 36 (NextDescAddresses) is reserved when 252e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li * the desc is cleared. */ 253e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define TX_DESC_NEXT_DESC_OFFSET 36 254e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define CLEAR_PCI_TX_DESC_CONTENT(__pdesc, _size) \ 255da951c2417ec1020d0d00813da36f38e395994e9Joe Perches memset(__pdesc, 0, min_t(size_t, _size, TX_DESC_NEXT_DESC_OFFSET)) 256e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li 257e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li/* Rx Desc */ 258e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define RX_STATUS_DESC_SIZE 24 259e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define RX_DRV_INFO_SIZE_UNIT 8 260e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li 261e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li/* DWORD 0 */ 262e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_RX_STATUS_DESC_PKT_LEN(__pdesc, __val) \ 263e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc, 0, 14, __val) 264e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_RX_STATUS_DESC_CRC32(__pdesc, __val) \ 265e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc, 14, 1, __val) 266e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_RX_STATUS_DESC_ICV(__pdesc, __val) \ 267e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc, 15, 1, __val) 268e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_RX_STATUS_DESC_DRVINFO_SIZE(__pdesc, __val) \ 269e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc, 16, 4, __val) 270e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_RX_STATUS_DESC_SECURITY(__pdesc, __val) \ 271e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc, 20, 3, __val) 272e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_RX_STATUS_DESC_QOS(__pdesc, __val) \ 273e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc, 23, 1, __val) 274e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_RX_STATUS_DESC_SHIFT(__pdesc, __val) \ 275e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc, 24, 2, __val) 276e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_RX_STATUS_DESC_PHY_STATUS(__pdesc, __val) \ 277e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc, 26, 1, __val) 278e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_RX_STATUS_DESC_SWDEC(__pdesc, __val) \ 279e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc, 27, 1, __val) 280e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_RX_STATUS_DESC_LAST_SEG(__pdesc, __val) \ 281e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc, 28, 1, __val) 282e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_RX_STATUS_DESC_FIRST_SEG(__pdesc, __val) \ 283e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc, 29, 1, __val) 284e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_RX_STATUS_DESC_EOR(__pdesc, __val) \ 285e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc, 30, 1, __val) 286e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_RX_STATUS_DESC_OWN(__pdesc, __val) \ 287e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc, 31, 1, __val) 288e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li 289e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define GET_RX_STATUS_DESC_PKT_LEN(__pdesc) \ 290e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SHIFT_AND_MASK_LE(__pdesc, 0, 14) 291e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define GET_RX_STATUS_DESC_CRC32(__pdesc) \ 292e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SHIFT_AND_MASK_LE(__pdesc, 14, 1) 293e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define GET_RX_STATUS_DESC_ICV(__pdesc) \ 294e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SHIFT_AND_MASK_LE(__pdesc, 15, 1) 295e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define GET_RX_STATUS_DESC_DRVINFO_SIZE(__pdesc) \ 296e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SHIFT_AND_MASK_LE(__pdesc, 16, 4) 297e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define GET_RX_STATUS_DESC_SECURITY(__pdesc) \ 298e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SHIFT_AND_MASK_LE(__pdesc, 20, 3) 299e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define GET_RX_STATUS_DESC_QOS(__pdesc) \ 300e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SHIFT_AND_MASK_LE(__pdesc, 23, 1) 301e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define GET_RX_STATUS_DESC_SHIFT(__pdesc) \ 302e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SHIFT_AND_MASK_LE(__pdesc, 24, 2) 303e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define GET_RX_STATUS_DESC_PHY_STATUS(__pdesc) \ 304e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SHIFT_AND_MASK_LE(__pdesc, 26, 1) 305e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define GET_RX_STATUS_DESC_SWDEC(__pdesc) \ 306e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SHIFT_AND_MASK_LE(__pdesc, 27, 1) 307e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define GET_RX_STATUS_DESC_LAST_SEG(__pdesc) \ 308e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SHIFT_AND_MASK_LE(__pdesc, 28, 1) 309e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define GET_RX_STATUS_DESC_FIRST_SEG(__pdesc) \ 310e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SHIFT_AND_MASK_LE(__pdesc, 29, 1) 311e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define GET_RX_STATUS_DESC_EOR(__pdesc) \ 312e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SHIFT_AND_MASK_LE(__pdesc, 30, 1) 313e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define GET_RX_STATUS_DESC_OWN(__pdesc) \ 314e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SHIFT_AND_MASK_LE(__pdesc, 31, 1) 315e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li 316e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li/* DWORD 1 */ 317e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_RX_STATUS_DESC_MACID(__pdesc, __val) \ 318e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 4, 0, 5, __val) 319e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_RX_STATUS_DESC_TID(__pdesc, __val) \ 320e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 4, 5, 4, __val) 321e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_RX_STATUS_DESC_PAGGR(__pdesc, __val) \ 322e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 4, 14, 1, __val) 323e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_RX_STATUS_DESC_FAGGR(__pdesc, __val) \ 324e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 4, 15, 1, __val) 325e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_RX_STATUS_DESC_A1_FIT(__pdesc, __val) \ 326e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 4, 16, 4, __val) 327e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_RX_STATUS_DESC_A2_FIT(__pdesc, __val) \ 328e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 4, 20, 4, __val) 329e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_RX_STATUS_DESC_PAM(__pdesc, __val) \ 330e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 4, 24, 1, __val) 331e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_RX_STATUS_DESC_PWR(__pdesc, __val) \ 332e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 4, 25, 1, __val) 333e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_RX_STATUS_DESC_MOREDATA(__pdesc, __val) \ 334e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 4, 26, 1, __val) 335e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_RX_STATUS_DESC_MOREFRAG(__pdesc, __val) \ 336e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 4, 27, 1, __val) 337e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_RX_STATUS_DESC_TYPE(__pdesc, __val) \ 338e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 4, 28, 2, __val) 339e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_RX_STATUS_DESC_MC(__pdesc, __val) \ 340e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 4, 30, 1, __val) 341e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_RX_STATUS_DESC_BC(__pdesc, __val) \ 342e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 4, 31, 1, __val) 343e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li 344e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define GET_RX_STATUS_DEC_MACID(__pdesc) \ 345e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SHIFT_AND_MASK_LE(__pdesc + 4, 0, 5) 346e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define GET_RX_STATUS_DESC_TID(__pdesc) \ 347e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SHIFT_AND_MASK_LE(__pdesc + 4, 5, 4) 348e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define GET_RX_STATUS_DESC_PAGGR(__pdesc) \ 349e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SHIFT_AND_MASK_LE(__pdesc + 4, 14, 1) 350e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define GET_RX_STATUS_DESC_FAGGR(__pdesc) \ 351e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SHIFT_AND_MASK_LE(__pdesc + 4, 15, 1) 352e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define GET_RX_STATUS_DESC_A1_FIT(__pdesc) \ 353e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SHIFT_AND_MASK_LE(__pdesc + 4, 16, 4) 354e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define GET_RX_STATUS_DESC_A2_FIT(__pdesc) \ 355e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SHIFT_AND_MASK_LE(__pdesc + 4, 20, 4) 356e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define GET_RX_STATUS_DESC_PAM(__pdesc) \ 357e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SHIFT_AND_MASK_LE(__pdesc + 4, 24, 1) 358e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define GET_RX_STATUS_DESC_PWR(__pdesc) \ 359e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SHIFT_AND_MASK_LE(__pdesc + 4, 25, 1) 360e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define GET_RX_STATUS_DESC_MORE_DATA(__pdesc) \ 361e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SHIFT_AND_MASK_LE(__pdesc + 4, 26, 1) 362e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define GET_RX_STATUS_DESC_MORE_FRAG(__pdesc) \ 363e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SHIFT_AND_MASK_LE(__pdesc + 4, 27, 1) 364e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define GET_RX_STATUS_DESC_TYPE(__pdesc) \ 365e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SHIFT_AND_MASK_LE(__pdesc + 4, 28, 2) 366e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define GET_RX_STATUS_DESC_MC(__pdesc) \ 367e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SHIFT_AND_MASK_LE(__pdesc + 4, 30, 1) 368e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define GET_RX_STATUS_DESC_BC(__pdesc) \ 369e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SHIFT_AND_MASK_LE(__pdesc + 4, 31, 1) 370e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li 371e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li/* DWORD 2 */ 372e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_RX_STATUS_DESC_SEQ(__pdesc, __val) \ 373e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 8, 0, 12, __val) 374e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_RX_STATUS_DESC_FRAG(__pdesc, __val) \ 375e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 8, 12, 4, __val) 376e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_RX_STATUS_DESC_NEXT_PKTLEN(__pdesc, __val) \ 377e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 8, 16, 8, __val) 378e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_RX_STATUS_DESC_NEXT_IND(__pdesc, __val) \ 379e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 8, 30, 1, __val) 380e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li 381e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define GET_RX_STATUS_DESC_SEQ(__pdesc) \ 382e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SHIFT_AND_MASK_LE(__pdesc + 8, 0, 12) 383e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define GET_RX_STATUS_DESC_FRAG(__pdesc) \ 384e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SHIFT_AND_MASK_LE(__pdesc + 8, 12, 4) 385e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define GET_RX_STATUS_DESC_NEXT_PKTLEN(__pdesc) \ 386e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SHIFT_AND_MASK_LE(__pdesc + 8, 16, 8) 387e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define GET_RX_STATUS_DESC_NEXT_IND(__pdesc) \ 388e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SHIFT_AND_MASK_LE(__pdesc + 8, 30, 1) 389e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li 390e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li/* DWORD 3 */ 391e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_RX_STATUS_DESC_RX_MCS(__pdesc, __val) \ 392e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 12, 0, 6, __val) 393e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_RX_STATUS_DESC_RX_HT(__pdesc, __val) \ 394e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 12, 6, 1, __val) 395e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_RX_STATUS_DESC_AMSDU(__pdesc, __val) \ 396e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 12, 7, 1, __val) 397e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_RX_STATUS_DESC_SPLCP(__pdesc, __val) \ 398e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 12, 8, 1, __val) 399e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_RX_STATUS_DESC_BW(__pdesc, __val) \ 400e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 12, 9, 1, __val) 401e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_RX_STATUS_DESC_HTC(__pdesc, __val) \ 402e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 12, 10, 1, __val) 403e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_RX_STATUS_DESC_TCP_CHK_RPT(__pdesc, __val) \ 404e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 12, 11, 1, __val) 405e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_RX_STATUS_DESC_IP_CHK_RPT(__pdesc, __val) \ 406e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 12, 12, 1, __val) 407e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_RX_STATUS_DESC_TCP_CHK_VALID(__pdesc, __val) \ 408e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 12, 13, 1, __val) 409e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_RX_STATUS_DESC_HWPC_ERR(__pdesc, __val) \ 410e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 12, 14, 1, __val) 411e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_RX_STATUS_DESC_HWPC_IND(__pdesc, __val) \ 412e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 12, 15, 1, __val) 413e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_RX_STATUS_DESC_IV0(__pdesc, __val) \ 414e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 12, 16, 16, __val) 415e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li 416e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define GET_RX_STATUS_DESC_RX_MCS(__pdesc) \ 417e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SHIFT_AND_MASK_LE(__pdesc + 12, 0, 6) 418e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define GET_RX_STATUS_DESC_RX_HT(__pdesc) \ 419e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SHIFT_AND_MASK_LE(__pdesc + 12, 6, 1) 420e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define GET_RX_STATUS_DESC_AMSDU(__pdesc) \ 421e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SHIFT_AND_MASK_LE(__pdesc + 12, 7, 1) 422e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define GET_RX_STATUS_DESC_SPLCP(__pdesc) \ 423e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SHIFT_AND_MASK_LE(__pdesc + 12, 8, 1) 424e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define GET_RX_STATUS_DESC_BW(__pdesc) \ 425e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SHIFT_AND_MASK_LE(__pdesc + 12, 9, 1) 426e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define GET_RX_STATUS_DESC_HTC(__pdesc) \ 427e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SHIFT_AND_MASK_LE(__pdesc + 12, 10, 1) 428e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define GET_RX_STATUS_DESC_TCP_CHK_RPT(__pdesc) \ 429e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SHIFT_AND_MASK_LE(__pdesc + 12, 11, 1) 430e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define GET_RX_STATUS_DESC_IP_CHK_RPT(__pdesc) \ 431e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SHIFT_AND_MASK_LE(__pdesc + 12, 12, 1) 432e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define GET_RX_STATUS_DESC_TCP_CHK_VALID(__pdesc) \ 433e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SHIFT_AND_MASK_LE(__pdesc + 12, 13, 1) 434e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define GET_RX_STATUS_DESC_HWPC_ERR(__pdesc) \ 435e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SHIFT_AND_MASK_LE(__pdesc + 12, 14, 1) 436e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define GET_RX_STATUS_DESC_HWPC_IND(__pdesc) \ 437e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SHIFT_AND_MASK_LE(__pdesc + 12, 15, 1) 438e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define GET_RX_STATUS_DESC_IV0(__pdesc) \ 439e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SHIFT_AND_MASK_LE(__pdesc + 12, 16, 16) 440e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li 441e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li/* DWORD 4 */ 442e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_RX_STATUS_DESC_IV1(__pdesc, __val) \ 443e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 16, 0, 32, __val) 444e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define GET_RX_STATUS_DESC_IV1(__pdesc) \ 445e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SHIFT_AND_MASK_LE(__pdesc + 16, 0, 32) 446e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li 447e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li/* DWORD 5 */ 448e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_RX_STATUS_DESC_TSFL(__pdesc, __val) \ 449e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 20, 0, 32, __val) 450e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define GET_RX_STATUS_DESC_TSFL(__pdesc) \ 451e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SHIFT_AND_MASK_LE(__pdesc + 20, 0, 32) 452e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li 453e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li/* DWORD 6 */ 454e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#define SET_RX_STATUS__DESC_BUFF_ADDR(__pdesc, __val) \ 455e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li SET_BITS_OFFSET_LE(__pdesc + 24, 0, 32, __val) 456e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li 457da3ba88a9996cd64c6768bed5727e02da81e2c8dLarry Finger#define SE_RX_HAL_IS_CCK_RATE(_pdesc)\ 4588e35337731abb901f3ae20ebc3f44a50ba6953e9Larry Finger (GET_RX_STATUS_DESC_RX_MCS(_pdesc) == DESC92_RATE1M || \ 4598e35337731abb901f3ae20ebc3f44a50ba6953e9Larry Finger GET_RX_STATUS_DESC_RX_MCS(_pdesc) == DESC92_RATE2M || \ 4608e35337731abb901f3ae20ebc3f44a50ba6953e9Larry Finger GET_RX_STATUS_DESC_RX_MCS(_pdesc) == DESC92_RATE5_5M ||\ 4618e35337731abb901f3ae20ebc3f44a50ba6953e9Larry Finger GET_RX_STATUS_DESC_RX_MCS(_pdesc) == DESC92_RATE11M) 462e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li 463e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Lienum rf_optype { 464e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li RF_OP_BY_SW_3WIRE = 0, 465e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li RF_OP_BY_FW, 466e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li RF_OP_MAX 467e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li}; 468e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li 469e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Lienum ic_inferiority { 470e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li IC_INFERIORITY_A = 0, 471e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li IC_INFERIORITY_B = 1, 472e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li}; 473e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li 474e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Lienum fwcmd_iotype { 475e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li /* For DIG DM */ 476e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li FW_CMD_DIG_ENABLE = 0, 477e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li FW_CMD_DIG_DISABLE = 1, 478e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li FW_CMD_DIG_HALT = 2, 479e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li FW_CMD_DIG_RESUME = 3, 480e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li /* For High Power DM */ 481e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li FW_CMD_HIGH_PWR_ENABLE = 4, 482e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li FW_CMD_HIGH_PWR_DISABLE = 5, 483e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li /* For Rate adaptive DM */ 484e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li FW_CMD_RA_RESET = 6, 485e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li FW_CMD_RA_ACTIVE = 7, 486e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li FW_CMD_RA_REFRESH_N = 8, 487e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li FW_CMD_RA_REFRESH_BG = 9, 488e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li FW_CMD_RA_INIT = 10, 489e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li /* For FW supported IQK */ 490e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li FW_CMD_IQK_INIT = 11, 491e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li /* Tx power tracking switch, 492e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li * MP driver only */ 493e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li FW_CMD_TXPWR_TRACK_ENABLE = 12, 494e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li /* Tx power tracking switch, 495e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li * MP driver only */ 496e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li FW_CMD_TXPWR_TRACK_DISABLE = 13, 497e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li /* Tx power tracking with thermal 498e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li * indication, for Normal driver */ 499e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li FW_CMD_TXPWR_TRACK_THERMAL = 14, 500e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li FW_CMD_PAUSE_DM_BY_SCAN = 15, 501e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li FW_CMD_RESUME_DM_BY_SCAN = 16, 502e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li FW_CMD_RA_REFRESH_N_COMB = 17, 503e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li FW_CMD_RA_REFRESH_BG_COMB = 18, 504e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li FW_CMD_ANTENNA_SW_ENABLE = 19, 505e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li FW_CMD_ANTENNA_SW_DISABLE = 20, 506e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li /* Tx Status report for CCX from FW */ 507e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li FW_CMD_TX_FEEDBACK_CCX_ENABLE = 21, 508e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li /* Indifate firmware that driver 509e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li * enters LPS, For PS-Poll issue */ 510e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li FW_CMD_LPS_ENTER = 22, 511e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li /* Indicate firmware that driver 512e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li * leave LPS*/ 513e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li FW_CMD_LPS_LEAVE = 23, 514e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li /* Set DIG mode to signal strength */ 515e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li FW_CMD_DIG_MODE_SS = 24, 516e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li /* Set DIG mode to false alarm. */ 517e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li FW_CMD_DIG_MODE_FA = 25, 518e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li FW_CMD_ADD_A2_ENTRY = 26, 519e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li FW_CMD_CTRL_DM_BY_DRIVER = 27, 520e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li FW_CMD_CTRL_DM_BY_DRIVER_NEW = 28, 521e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li FW_CMD_PAPE_CONTROL = 29, 522e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li FW_CMD_IQK_ENABLE = 30, 523e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li}; 524e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li 525dac67975f3dc8565e4254b1d7a49618494f1a2f1Daniel Stamer/* Driver info contain PHY status 526e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li * and other variabel size info 527e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li * PHY Status content as below 528e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li */ 529e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Listruct rx_fwinfo { 530e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li /* DWORD 0 */ 531e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li u8 gain_trsw[4]; 532e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li /* DWORD 1 */ 533e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li u8 pwdb_all; 534e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li u8 cfosho[4]; 535e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li /* DWORD 2 */ 536e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li u8 cfotail[4]; 537e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li /* DWORD 3 */ 538e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li s8 rxevm[2]; 539e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li s8 rxsnr[4]; 540e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li /* DWORD 4 */ 541e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li u8 pdsnr[2]; 542e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li /* DWORD 5 */ 543e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li u8 csi_current[2]; 544e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li u8 csi_target[2]; 545e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li /* DWORD 6 */ 546e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li u8 sigevm; 547e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li u8 max_ex_pwr; 548e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li u8 ex_intf_flag:1; 549e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li u8 sgi_en:1; 550e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li u8 rxsc:2; 551e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li u8 reserve:4; 552e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li}; 553e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li 554e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Listruct phy_sts_cck_8192s_t { 555e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li u8 adc_pwdb_x[4]; 556e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li u8 sq_rpt; 557e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li u8 cck_agc_rpt; 558e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li}; 559e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li 560e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li#endif 561e52dadb341c9c5ac25d6abd9216dd62752784f03Chaoming Li 562