1/*
2 * This file is part of wl1251
3 *
4 * Copyright (c) 1998-2007 Texas Instruments Incorporated
5 * Copyright (C) 2008 Nokia Corporation
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
19 * 02110-1301 USA
20 *
21 */
22
23#ifndef __WL1251_TX_H__
24#define __WL1251_TX_H__
25
26#include <linux/bitops.h>
27#include "acx.h"
28
29/*
30 *
31 * TX PATH
32 *
33 * The Tx path uses a double buffer and a tx_control structure, each located
34 * at a fixed address in the device's memory. On startup, the host retrieves
35 * the pointers to these addresses. A double buffer allows for continuous data
36 * flow towards the device. The host keeps track of which buffer is available
37 * and alternates between these two buffers on a per packet basis.
38 *
39 * The size of each of the two buffers is large enough to hold the longest
40 * 802.3 packet - maximum size Ethernet packet + header + descriptor.
41 * TX complete indication will be received a-synchronously in a TX done cyclic
42 * buffer which is composed of 16 tx_result descriptors structures and is used
43 * in a cyclic manner.
44 *
45 * The TX (HOST) procedure is as follows:
46 * 1. Read the Tx path status, that will give the data_out_count.
47 * 2. goto 1, if not possible.
48 *    i.e. if data_in_count - data_out_count >= HwBuffer size (2 for double
49 *    buffer).
50 * 3. Copy the packet (preceded by double_buffer_desc), if possible.
51 *    i.e. if data_in_count - data_out_count < HwBuffer size (2 for double
52 *    buffer).
53 * 4. increment data_in_count.
54 * 5. Inform the firmware by generating a firmware internal interrupt.
55 * 6. FW will increment data_out_count after it reads the buffer.
56 *
57 * The TX Complete procedure:
58 * 1. To get a TX complete indication the host enables the tx_complete flag in
59 *    the TX descriptor Structure.
60 * 2. For each packet with a Tx Complete field set, the firmware adds the
61 *    transmit results to the cyclic buffer (txDoneRing) and sets both done_1
62 *    and done_2 to 1 to indicate driver ownership.
63 * 3. The firmware sends a Tx Complete interrupt to the host to trigger the
64 *    host to process the new data. Note: interrupt will be send per packet if
65 *    TX complete indication was requested in tx_control or per crossing
66 *    aggregation threshold.
67 * 4. After receiving the Tx Complete interrupt, the host reads the
68 *    TxDescriptorDone information in a cyclic manner and clears both done_1
69 *    and done_2 fields.
70 *
71 */
72
73#define TX_COMPLETE_REQUIRED_BIT	0x80
74#define TX_STATUS_DATA_OUT_COUNT_MASK   0xf
75
76#define WL1251_TX_ALIGN_TO 4
77#define WL1251_TX_ALIGN(len) (((len) + WL1251_TX_ALIGN_TO - 1) & \
78			     ~(WL1251_TX_ALIGN_TO - 1))
79#define WL1251_TKIP_IV_SPACE 4
80
81struct tx_control {
82	/* Rate Policy (class) index */
83	unsigned rate_policy:3;
84
85	/* When set, no ack policy is expected */
86	unsigned ack_policy:1;
87
88	/*
89	 * Packet type:
90	 * 0 -> 802.11
91	 * 1 -> 802.3
92	 * 2 -> IP
93	 * 3 -> raw codec
94	 */
95	unsigned packet_type:2;
96
97	/* If set, this is a QoS-Null or QoS-Data frame */
98	unsigned qos:1;
99
100	/*
101	 * If set, the target triggers the tx complete INT
102	 * upon frame sending completion.
103	 */
104	unsigned tx_complete:1;
105
106	/* 2 bytes padding before packet header */
107	unsigned xfer_pad:1;
108
109	unsigned reserved:7;
110} __packed;
111
112
113struct tx_double_buffer_desc {
114	/* Length of payload, including headers. */
115	__le16 length;
116
117	/*
118	 * A bit mask that specifies the initial rate to be used
119	 * Possible values are:
120	 * 0x0001 - 1Mbits
121	 * 0x0002 - 2Mbits
122	 * 0x0004 - 5.5Mbits
123	 * 0x0008 - 6Mbits
124	 * 0x0010 - 9Mbits
125	 * 0x0020 - 11Mbits
126	 * 0x0040 - 12Mbits
127	 * 0x0080 - 18Mbits
128	 * 0x0100 - 22Mbits
129	 * 0x0200 - 24Mbits
130	 * 0x0400 - 36Mbits
131	 * 0x0800 - 48Mbits
132	 * 0x1000 - 54Mbits
133	 */
134	__le16 rate;
135
136	/* Time in us that a packet can spend in the target */
137	__le32 expiry_time;
138
139	/* index of the TX queue used for this packet */
140	u8 xmit_queue;
141
142	/* Used to identify a packet */
143	u8 id;
144
145	struct tx_control control;
146
147	/*
148	 * The FW should cut the packet into fragments
149	 * of this size.
150	 */
151	__le16 frag_threshold;
152
153	/* Numbers of HW queue blocks to be allocated */
154	u8 num_mem_blocks;
155
156	u8 reserved;
157} __packed;
158
159enum {
160	TX_SUCCESS              = 0,
161	TX_DMA_ERROR            = BIT(7),
162	TX_DISABLED             = BIT(6),
163	TX_RETRY_EXCEEDED       = BIT(5),
164	TX_TIMEOUT              = BIT(4),
165	TX_KEY_NOT_FOUND        = BIT(3),
166	TX_ENCRYPT_FAIL         = BIT(2),
167	TX_UNAVAILABLE_PRIORITY = BIT(1),
168};
169
170struct tx_result {
171	/*
172	 * Ownership synchronization between the host and
173	 * the firmware. If done_1 and done_2 are cleared,
174	 * owned by the FW (no info ready).
175	 */
176	u8 done_1;
177
178	/* same as double_buffer_desc->id */
179	u8 id;
180
181	/*
182	 * Total air access duration consumed by this
183	 * packet, including all retries and overheads.
184	 */
185	u16 medium_usage;
186
187	/* Total media delay (from 1st EDCA AIFS counter until TX Complete). */
188	u32 medium_delay;
189
190	/* Time between host xfer and tx complete */
191	u32 fw_hnadling_time;
192
193	/* The LS-byte of the last TKIP sequence number. */
194	u8 lsb_seq_num;
195
196	/* Retry count */
197	u8 ack_failures;
198
199	/* At which rate we got a ACK */
200	u16 rate;
201
202	u16 reserved;
203
204	/* TX_* */
205	u8 status;
206
207	/* See done_1 */
208	u8 done_2;
209} __packed;
210
211static inline int wl1251_tx_get_queue(int queue)
212{
213	switch (queue) {
214	case 0:
215		return QOS_AC_VO;
216	case 1:
217		return QOS_AC_VI;
218	case 2:
219		return QOS_AC_BE;
220	case 3:
221		return QOS_AC_BK;
222	default:
223		return QOS_AC_BE;
224	}
225}
226
227void wl1251_tx_work(struct work_struct *work);
228void wl1251_tx_complete(struct wl1251 *wl);
229void wl1251_tx_flush(struct wl1251 *wl);
230
231#endif
232