1f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho/* 2f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho * This file is part of wl12xx 3f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho * 4f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho * Copyright (C) 1998-2009 Texas Instruments. All rights reserved. 5f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho * Copyright (C) 2009 Nokia Corporation 6f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho * 7f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho * Contact: Luciano Coelho <luciano.coelho@nokia.com> 8f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho * 9f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho * This program is free software; you can redistribute it and/or 10f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho * modify it under the terms of the GNU General Public License 11f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho * version 2 as published by the Free Software Foundation. 12f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho * 13f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho * This program is distributed in the hope that it will be useful, but 14f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho * WITHOUT ANY WARRANTY; without even the implied warranty of 15f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho * General Public License for more details. 17f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho * 18f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho * You should have received a copy of the GNU General Public License 19f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho * along with this program; if not, write to the Free Software 20f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 21f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho * 02110-1301 USA 22f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho * 23f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho */ 24f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 25f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho#ifndef __REG_H__ 26f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho#define __REG_H__ 27f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 28f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho#include <linux/bitops.h> 29f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 30f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho#define REGISTERS_BASE 0x00300000 31f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho#define DRPW_BASE 0x00310000 32f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 33f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho#define REGISTERS_DOWN_SIZE 0x00008800 34f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho#define REGISTERS_WORK_SIZE 0x0000b000 35f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 36c15f63bffabb996f90b9c24c62fb0614c5a4f676Juuso Oikarinen#define FW_STATUS_ADDR (0x14FC0 + 0xA000) 37f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 38f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho/*=============================================== 39f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho Host Software Reset - 32bit RW 40f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho ------------------------------------------ 41f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho [31:1] Reserved 42f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 0 SOFT_RESET Soft Reset - When this bit is set, 43f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho it holds the Wlan hardware in a soft reset state. 44f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho This reset disables all MAC and baseband processor 45f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho clocks except the CardBus/PCI interface clock. 46f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho It also initializes all MAC state machines except 47f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho the host interface. It does not reload the 48f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho contents of the EEPROM. When this bit is cleared 49f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho (not self-clearing), the Wlan hardware 50f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho exits the software reset state. 51f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho===============================================*/ 5200782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL12XX_SLV_SOFT_RESET (REGISTERS_BASE + 0x0000) 53f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 54f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho#define WL1271_SLV_REG_DATA (REGISTERS_BASE + 0x0008) 55f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho#define WL1271_SLV_REG_ADATA (REGISTERS_BASE + 0x000c) 56f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho#define WL1271_SLV_MEM_DATA (REGISTERS_BASE + 0x0018) 57f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 5800782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL12XX_REG_INTERRUPT_TRIG (REGISTERS_BASE + 0x0474) 5900782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL12XX_REG_INTERRUPT_TRIG_H (REGISTERS_BASE + 0x0478) 60f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 61f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho/*============================================= 62f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho Host Interrupt Mask Register - 32bit (RW) 63f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho ------------------------------------------ 64f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho Setting a bit in this register masks the 65f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho corresponding interrupt to the host. 66f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 0 - RX0 - Rx first dubble buffer Data Interrupt 67f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 1 - TXD - Tx Data Interrupt 68f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 2 - TXXFR - Tx Transfer Interrupt 69f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 3 - RX1 - Rx second dubble buffer Data Interrupt 70f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 4 - RXXFR - Rx Transfer Interrupt 71f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 5 - EVENT_A - Event Mailbox interrupt 72f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 6 - EVENT_B - Event Mailbox interrupt 73f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 7 - WNONHST - Wake On Host Interrupt 74f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 8 - TRACE_A - Debug Trace interrupt 75f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 9 - TRACE_B - Debug Trace interrupt 76f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 10 - CDCMP - Command Complete Interrupt 77f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 11 - 78f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 12 - 79f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 13 - 80f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 14 - ICOMP - Initialization Complete Interrupt 81f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 16 - SG SE - Soft Gemini - Sense enable interrupt 82f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 17 - SG SD - Soft Gemini - Sense disable interrupt 83f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 18 - - 84f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 19 - - 85f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 20 - - 86f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 21- - 87f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho Default: 0x0001 88f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho*==============================================*/ 8900782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL12XX_REG_INTERRUPT_MASK (REGISTERS_BASE + 0x04DC) 90f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 91f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho/*============================================= 92f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho Host Interrupt Mask Set 16bit, (Write only) 93f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho ------------------------------------------ 94f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho Setting a bit in this register sets 95f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho the corresponding bin in ACX_HINT_MASK register 96f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho without effecting the mask 97f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho state of other bits (0 = no effect). 98f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho==============================================*/ 99f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho#define ACX_REG_HINT_MASK_SET (REGISTERS_BASE + 0x04E0) 100f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 101f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho/*============================================= 102f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho Host Interrupt Mask Clear 16bit,(Write only) 103f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho ------------------------------------------ 104f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho Setting a bit in this register clears 105f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho the corresponding bin in ACX_HINT_MASK register 106f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho without effecting the mask 107f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho state of other bits (0 = no effect). 108f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho=============================================*/ 109f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho#define ACX_REG_HINT_MASK_CLR (REGISTERS_BASE + 0x04E4) 110f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 111f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho/*============================================= 112f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho Host Interrupt Status Nondestructive Read 113f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 16bit,(Read only) 114f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho ------------------------------------------ 115f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho The host can read this register to determine 116f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho which interrupts are active. 117f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho Reading this register doesn't 118f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho effect its content. 119f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho=============================================*/ 12000782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL12XX_REG_INTERRUPT_NO_CLEAR (REGISTERS_BASE + 0x04E8) 121f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 122f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho/*============================================= 123f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho Host Interrupt Status Clear on Read Register 124f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 16bit,(Read only) 125f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho ------------------------------------------ 126f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho The host can read this register to determine 127f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho which interrupts are active. 128f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho Reading this register clears it, 129f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho thus making all interrupts inactive. 130f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho==============================================*/ 131f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho#define ACX_REG_INTERRUPT_CLEAR (REGISTERS_BASE + 0x04F8) 132f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 133f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho/*============================================= 134f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho Host Interrupt Acknowledge Register 135f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 16bit,(Write only) 136f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho ------------------------------------------ 137f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho The host can set individual bits in this 138f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho register to clear (acknowledge) the corresp. 139f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho interrupt status bits in the HINT_STS_CLR and 140f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho HINT_STS_ND registers, thus making the 141f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho assotiated interrupt inactive. (0-no effect) 142f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho==============================================*/ 14300782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL12XX_REG_INTERRUPT_ACK (REGISTERS_BASE + 0x04F0) 144f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 14500782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL12XX_REG_RX_DRIVER_COUNTER (REGISTERS_BASE + 0x0538) 146f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 147f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho/* Device Configuration registers*/ 148f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho#define SOR_CFG (REGISTERS_BASE + 0x0800) 149f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 150f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho/* Embedded ARM CPU Control */ 151f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 152f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho/*=============================================== 153f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho Halt eCPU - 32bit RW 154f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho ------------------------------------------ 155f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 0 HALT_ECPU Halt Embedded CPU - This bit is the 156f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho compliment of bit 1 (MDATA2) in the SOR_CFG register. 157f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho During a hardware reset, this bit holds 158f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho the inverse of MDATA2. 159f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho When downloading firmware from the host, 160f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho set this bit (pull down MDATA2). 161f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho The host clears this bit after downloading the firmware into 162f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho zero-wait-state SSRAM. 163f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho When loading firmware from Flash, clear this bit (pull up MDATA2) 164f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho so that the eCPU can run the bootloader code in Flash 165f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho HALT_ECPU eCPU State 166f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho -------------------- 167f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 1 halt eCPU 168f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 0 enable eCPU 169f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho ===============================================*/ 17000782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL12XX_REG_ECPU_CONTROL (REGISTERS_BASE + 0x0804) 171f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 17200782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL12XX_HI_CFG (REGISTERS_BASE + 0x0808) 173f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 174f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho/*=============================================== 175f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho EEPROM Burst Read Start - 32bit RW 176f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho ------------------------------------------ 177f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho [31:1] Reserved 178f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 0 ACX_EE_START - EEPROM Burst Read Start 0 179f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho Setting this bit starts a burst read from 180f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho the external EEPROM. 181f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho If this bit is set (after reset) before an EEPROM read/write, 182f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho the burst read starts at EEPROM address 0. 183f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho Otherwise, it starts at the address 184f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho following the address of the previous access. 185f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho TheWlan hardware hardware clears this bit automatically. 186f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 187f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho Default: 0x00000000 188f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho*================================================*/ 189f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho#define ACX_REG_EE_START (REGISTERS_BASE + 0x080C) 190f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 19100782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL12XX_OCP_POR_CTR (REGISTERS_BASE + 0x09B4) 19200782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL12XX_OCP_DATA_WRITE (REGISTERS_BASE + 0x09B8) 19300782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL12XX_OCP_DATA_READ (REGISTERS_BASE + 0x09BC) 19400782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL12XX_OCP_CMD (REGISTERS_BASE + 0x09C0) 195f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 19600782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL12XX_HOST_WR_ACCESS (REGISTERS_BASE + 0x09F8) 197f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 19800782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL12XX_CHIP_ID_B (REGISTERS_BASE + 0x5674) 199f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 20000782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL12XX_ENABLE (REGISTERS_BASE + 0x5450) 201f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 202f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho/* Power Management registers */ 20300782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL12XX_ELP_CFG_MODE (REGISTERS_BASE + 0x5804) 20400782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL12XX_ELP_CMD (REGISTERS_BASE + 0x5808) 20500782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL12XX_PLL_CAL_TIME (REGISTERS_BASE + 0x5810) 20600782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL12XX_CLK_REQ_TIME (REGISTERS_BASE + 0x5814) 20700782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL12XX_CLK_BUF_TIME (REGISTERS_BASE + 0x5818) 208f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 20900782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL12XX_CFG_PLL_SYNC_CNT (REGISTERS_BASE + 0x5820) 210f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 211f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho/* Scratch Pad registers*/ 21200782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL12XX_SCR_PAD0 (REGISTERS_BASE + 0x5608) 21300782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL12XX_SCR_PAD1 (REGISTERS_BASE + 0x560C) 21400782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL12XX_SCR_PAD2 (REGISTERS_BASE + 0x5610) 21500782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL12XX_SCR_PAD3 (REGISTERS_BASE + 0x5614) 21600782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL12XX_SCR_PAD4 (REGISTERS_BASE + 0x5618) 21700782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL12XX_SCR_PAD4_SET (REGISTERS_BASE + 0x561C) 21800782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL12XX_SCR_PAD4_CLR (REGISTERS_BASE + 0x5620) 21900782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL12XX_SCR_PAD5 (REGISTERS_BASE + 0x5624) 22000782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL12XX_SCR_PAD5_SET (REGISTERS_BASE + 0x5628) 22100782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL12XX_SCR_PAD5_CLR (REGISTERS_BASE + 0x562C) 22200782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL12XX_SCR_PAD6 (REGISTERS_BASE + 0x5630) 22300782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL12XX_SCR_PAD7 (REGISTERS_BASE + 0x5634) 22400782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL12XX_SCR_PAD8 (REGISTERS_BASE + 0x5638) 22500782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL12XX_SCR_PAD9 (REGISTERS_BASE + 0x563C) 226f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 227f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho/* Spare registers*/ 22800782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL12XX_SPARE_A1 (REGISTERS_BASE + 0x0994) 22900782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL12XX_SPARE_A2 (REGISTERS_BASE + 0x0998) 23000782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL12XX_SPARE_A3 (REGISTERS_BASE + 0x099C) 23100782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL12XX_SPARE_A4 (REGISTERS_BASE + 0x09A0) 23200782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL12XX_SPARE_A5 (REGISTERS_BASE + 0x09A4) 23300782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL12XX_SPARE_A6 (REGISTERS_BASE + 0x09A8) 23400782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL12XX_SPARE_A7 (REGISTERS_BASE + 0x09AC) 23500782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL12XX_SPARE_A8 (REGISTERS_BASE + 0x09B0) 23600782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL12XX_SPARE_B1 (REGISTERS_BASE + 0x5420) 23700782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL12XX_SPARE_B2 (REGISTERS_BASE + 0x5424) 23800782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL12XX_SPARE_B3 (REGISTERS_BASE + 0x5428) 23900782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL12XX_SPARE_B4 (REGISTERS_BASE + 0x542C) 24000782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL12XX_SPARE_B5 (REGISTERS_BASE + 0x5430) 24100782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL12XX_SPARE_B6 (REGISTERS_BASE + 0x5434) 24200782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL12XX_SPARE_B7 (REGISTERS_BASE + 0x5438) 24300782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL12XX_SPARE_B8 (REGISTERS_BASE + 0x543C) 24400782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho 24500782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL12XX_PLL_PARAMETERS (REGISTERS_BASE + 0x6040) 24600782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL12XX_WU_COUNTER_PAUSE (REGISTERS_BASE + 0x6008) 24700782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL12XX_WELP_ARM_COMMAND (REGISTERS_BASE + 0x6100) 24800782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL12XX_DRPW_SCRATCH_START (DRPW_BASE + 0x002C) 24900782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho 25000782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL12XX_CMD_MBOX_ADDRESS 0x407B4 25100782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho 252f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho#define ACX_REG_EEPROM_START_BIT BIT(1) 253f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 254f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho/* Command/Information Mailbox Pointers */ 255f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 256f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho/*=============================================== 257f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho Command Mailbox Pointer - 32bit RW 258f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho ------------------------------------------ 259f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho This register holds the start address of 260f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho the command mailbox located in the Wlan hardware memory. 261f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho The host must read this pointer after a reset to 262f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho find the location of the command mailbox. 263f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho The Wlan hardware initializes the command mailbox 264f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho pointer with the default address of the command mailbox. 265f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho The command mailbox pointer is not valid until after 266f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho the host receives the Init Complete interrupt from 267f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho the Wlan hardware. 268f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho ===============================================*/ 26900782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL12XX_REG_COMMAND_MAILBOX_PTR (WL12XX_SCR_PAD0) 270f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 271f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho/*=============================================== 272f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho Information Mailbox Pointer - 32bit RW 273f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho ------------------------------------------ 274f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho This register holds the start address of 275f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho the information mailbox located in the Wlan hardware memory. 276f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho The host must read this pointer after a reset to find 277f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho the location of the information mailbox. 278f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho The Wlan hardware initializes the information mailbox pointer 279f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho with the default address of the information mailbox. 280f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho The information mailbox pointer is not valid 281f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho until after the host receives the Init Complete interrupt from 282f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho the Wlan hardware. 283f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho ===============================================*/ 28400782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL12XX_REG_EVENT_MAILBOX_PTR (WL12XX_SCR_PAD1) 285f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 286f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho/*=============================================== 287f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho EEPROM Read/Write Request 32bit RW 288f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho ------------------------------------------ 289f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 1 EE_READ - EEPROM Read Request 1 - Setting this bit 290f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho loads a single byte of data into the EE_DATA 291f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho register from the EEPROM location specified in 292f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho the EE_ADDR register. 293f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho The Wlan hardware hardware clears this bit automatically. 294f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho EE_DATA is valid when this bit is cleared. 295f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 296f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 0 EE_WRITE - EEPROM Write Request - Setting this bit 297f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho writes a single byte of data from the EE_DATA register into the 298f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho EEPROM location specified in the EE_ADDR register. 299f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho The Wlan hardware hardware clears this bit automatically. 300f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho*===============================================*/ 301f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho#define ACX_EE_CTL_REG EE_CTL 302f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho#define EE_WRITE 0x00000001ul 303f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho#define EE_READ 0x00000002ul 304f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 305f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho/*=============================================== 306f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho EEPROM Address - 32bit RW 307f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho ------------------------------------------ 308f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho This register specifies the address 309f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho within the EEPROM from/to which to read/write data. 310f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho ===============================================*/ 311f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho#define ACX_EE_ADDR_REG EE_ADDR 312f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 313f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho/*=============================================== 314f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho EEPROM Data - 32bit RW 315f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho ------------------------------------------ 316f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho This register either holds the read 8 bits of 317f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho data from the EEPROM or the write data 318f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho to be written to the EEPROM. 319f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho ===============================================*/ 320f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho#define ACX_EE_DATA_REG EE_DATA 321f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 322f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho/*=============================================== 323f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho EEPROM Base Address - 32bit RW 324f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho ------------------------------------------ 325f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho This register holds the upper nine bits 326f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho [23:15] of the 24-bit Wlan hardware memory 327f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho address for burst reads from EEPROM accesses. 328f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho The EEPROM provides the lower 15 bits of this address. 329f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho The MSB of the address from the EEPROM is ignored. 330f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho ===============================================*/ 331f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho#define ACX_EE_CFG EE_CFG 332f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 333f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho/*=============================================== 334f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho GPIO Output Values -32bit, RW 335f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho ------------------------------------------ 336f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho [31:16] Reserved 337f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho [15: 0] Specify the output values (at the output driver inputs) for 338f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho GPIO[15:0], respectively. 339f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho ===============================================*/ 340f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho#define ACX_GPIO_OUT_REG GPIO_OUT 341f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho#define ACX_MAX_GPIO_LINES 15 342f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 343f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho/*=============================================== 344f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho Contention window -32bit, RW 345f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho ------------------------------------------ 346f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho [31:26] Reserved 347f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho [25:16] Max (0x3ff) 348f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho [15:07] Reserved 349f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho [06:00] Current contention window value - default is 0x1F 350f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho ===============================================*/ 351f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho#define ACX_CONT_WIND_CFG_REG CONT_WIND_CFG 352f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho#define ACX_CONT_WIND_MIN_MASK 0x0000007f 353f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho#define ACX_CONT_WIND_MAX 0x03ff0000 354f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 355f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho#define REF_FREQ_19_2 0 356f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho#define REF_FREQ_26_0 1 357f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho#define REF_FREQ_38_4 2 358f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho#define REF_FREQ_40_0 3 359f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho#define REF_FREQ_33_6 4 360f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho#define REF_FREQ_NUM 5 361f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 362f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho#define LUT_PARAM_INTEGER_DIVIDER 0 363f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho#define LUT_PARAM_FRACTIONAL_DIVIDER 1 364f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho#define LUT_PARAM_ATTN_BB 2 365f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho#define LUT_PARAM_ALPHA_BB 3 366f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho#define LUT_PARAM_STOP_TIME_BB 4 367f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho#define LUT_PARAM_BB_PLL_LOOP_FILTER 5 368f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho#define LUT_PARAM_NUM 6 369f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 37000782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL12XX_EEPROMLESS_IND (WL12XX_SCR_PAD4) 371f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho#define USE_EEPROM 0 372f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho#define NVS_DATA_BUNDARY_ALIGNMENT 4 373f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 374f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho/* Firmware image header size */ 375f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho#define FW_HDR_SIZE 8 376f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 377f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho/****************************************************************************** 378f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 379f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho CHANNELS, BAND & REG DOMAINS definitions 380f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 381f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho******************************************************************************/ 382f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 383f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho#define SHORT_PREAMBLE_BIT BIT(0) /* CCK or Barker depending on the rate */ 384f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho#define OFDM_RATE_BIT BIT(6) 385f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho#define PBCC_RATE_BIT BIT(7) 386f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 387f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelhoenum { 388f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho CCK_LONG = 0, 389f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho CCK_SHORT = SHORT_PREAMBLE_BIT, 390f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho PBCC_LONG = PBCC_RATE_BIT, 391f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho PBCC_SHORT = PBCC_RATE_BIT | SHORT_PREAMBLE_BIT, 392f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho OFDM = OFDM_RATE_BIT 393f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho}; 394f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 395f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho/****************************************************************************** 396f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 397f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano CoelhoTransmit-Descriptor RATE-SET field definitions... 398f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 399f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano CoelhoDefine a new "Rate-Set" for TX path that incorporates the 400f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano CoelhoRate & Modulation info into a single 16-bit field. 401f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 402f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano CoelhoTxdRateSet_t: 403f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelhob15 - Indicates Preamble type (1=SHORT, 0=LONG). 404f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho Notes: 405f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho Must be LONG (0) for 1Mbps rate. 406f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho Does not apply (set to 0) for RevG-OFDM rates. 407f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelhob14 - Indicates PBCC encoding (1=PBCC, 0=not). 408f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho Notes: 409f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho Does not apply (set to 0) for rates 1 and 2 Mbps. 410f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho Does not apply (set to 0) for RevG-OFDM rates. 411f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelhob13 - Unused (set to 0). 412f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelhob12-b0 - Supported Rate indicator bits as defined below. 413f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 414f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho******************************************************************************/ 415f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 41600782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define OCP_CMD_LOOP 32 41700782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define OCP_CMD_WRITE 0x1 41800782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define OCP_CMD_READ 0x2 41900782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define OCP_READY_MASK BIT(18) 42000782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define OCP_STATUS_MASK (BIT(16) | BIT(17)) 42100782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define OCP_STATUS_NO_RESP 0x00000 42200782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define OCP_STATUS_OK 0x10000 42300782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define OCP_STATUS_REQ_FAILED 0x20000 42400782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define OCP_STATUS_RESP_ERROR 0x30000 42500782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho 42600782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define OCP_REG_POLARITY 0x0064 42700782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define OCP_REG_CLK_TYPE 0x0448 42800782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define OCP_REG_CLK_POLARITY 0x0cb2 42900782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define OCP_REG_CLK_PULL 0x0cb4 43000782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho 43100782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define POLARITY_LOW BIT(1) 43200782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define NO_PULL (BIT(14) | BIT(15)) 43300782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho 43400782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define FREF_CLK_TYPE_BITS 0xfffffe7f 43500782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define CLK_REQ_PRCM 0x100 43600782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define FREF_CLK_POLARITY_BITS 0xfffff8ff 43700782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define CLK_REQ_OUTN_SEL 0x700 43800782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho 43900782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WU_COUNTER_PAUSE_VAL 0x3FF 44000782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho 44100782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho/* PLL configuration algorithm for wl128x */ 44200782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define SYS_CLK_CFG_REG 0x2200 44300782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho/* Bit[0] - 0-TCXO, 1-FREF */ 44400782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define MCS_PLL_CLK_SEL_FREF BIT(0) 44500782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho/* Bit[3:2] - 01-TCXO, 10-FREF */ 44600782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL_CLK_REQ_TYPE_FREF BIT(3) 44700782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL_CLK_REQ_TYPE_PG2 (BIT(3) | BIT(2)) 44800782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho/* Bit[4] - 0-TCXO, 1-FREF */ 44900782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define PRCM_CM_EN_MUX_WLAN_FREF BIT(4) 45000782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho 45100782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define TCXO_ILOAD_INT_REG 0x2264 45200782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define TCXO_CLK_DETECT_REG 0x2266 45300782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho 45400782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define TCXO_DET_FAILED BIT(4) 45500782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho 45600782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define FREF_ILOAD_INT_REG 0x2084 45700782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define FREF_CLK_DETECT_REG 0x2086 45800782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define FREF_CLK_DETECT_FAIL BIT(4) 45900782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho 46000782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho/* Use this reg for masking during driver access */ 46100782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL_SPARE_REG 0x2320 46200782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL_SPARE_VAL BIT(2) 46300782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho/* Bit[6:5:3] - mask wl write SYS_CLK_CFG[8:5:2:4] */ 46400782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define WL_SPARE_MASK_8526 (BIT(6) | BIT(5) | BIT(3)) 46500782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho 46600782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define PLL_LOCK_COUNTERS_REG 0xD8C 46700782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define PLL_LOCK_COUNTERS_COEX 0x0F 46800782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define PLL_LOCK_COUNTERS_MCS 0xF0 46900782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define MCS_PLL_OVERRIDE_REG 0xD90 47000782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define MCS_PLL_CONFIG_REG 0xD92 47100782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define MCS_SEL_IN_FREQ_MASK 0x0070 47200782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define MCS_SEL_IN_FREQ_SHIFT 4 47300782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define MCS_PLL_CONFIG_REG_VAL 0x73 47400782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define MCS_PLL_ENABLE_HP (BIT(0) | BIT(1)) 47500782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho 47600782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define MCS_PLL_M_REG 0xD94 47700782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define MCS_PLL_N_REG 0xD96 47800782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define MCS_PLL_M_REG_VAL 0xC8 47900782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define MCS_PLL_N_REG_VAL 0x07 48000782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho 48100782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define SDIO_IO_DS 0xd14 48200782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho 48300782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho/* SDIO/wSPI DS configuration values */ 48400782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelhoenum { 48500782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho HCI_IO_DS_8MA = 0, 48600782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho HCI_IO_DS_4MA = 1, /* default */ 48700782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho HCI_IO_DS_6MA = 2, 48800782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho HCI_IO_DS_2MA = 3, 48900782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho}; 490f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 49100782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho/* end PLL configuration algorithm for wl128x */ 492f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 493f16ff75872b04fa6c779367ae24146c8a1729f2eLuciano Coelho/* 494f16ff75872b04fa6c779367ae24146c8a1729f2eLuciano Coelho * Host Command Interrupt. Setting this bit masks 495f16ff75872b04fa6c779367ae24146c8a1729f2eLuciano Coelho * the interrupt that the host issues to inform 496f16ff75872b04fa6c779367ae24146c8a1729f2eLuciano Coelho * the FW that it has sent a command 497f16ff75872b04fa6c779367ae24146c8a1729f2eLuciano Coelho * to the Wlan hardware Command Mailbox. 498f16ff75872b04fa6c779367ae24146c8a1729f2eLuciano Coelho */ 499f16ff75872b04fa6c779367ae24146c8a1729f2eLuciano Coelho#define WL12XX_INTR_TRIG_CMD BIT(0) 500f16ff75872b04fa6c779367ae24146c8a1729f2eLuciano Coelho 501f16ff75872b04fa6c779367ae24146c8a1729f2eLuciano Coelho/* 502f16ff75872b04fa6c779367ae24146c8a1729f2eLuciano Coelho * Host Event Acknowlegde Interrupt. The host 503f16ff75872b04fa6c779367ae24146c8a1729f2eLuciano Coelho * sets this bit to acknowledge that it received 504f16ff75872b04fa6c779367ae24146c8a1729f2eLuciano Coelho * the unsolicited information from the event 505f16ff75872b04fa6c779367ae24146c8a1729f2eLuciano Coelho * mailbox. 506f16ff75872b04fa6c779367ae24146c8a1729f2eLuciano Coelho */ 507f16ff75872b04fa6c779367ae24146c8a1729f2eLuciano Coelho#define WL12XX_INTR_TRIG_EVENT_ACK BIT(1) 508f16ff75872b04fa6c779367ae24146c8a1729f2eLuciano Coelho 50900782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho/*=============================================== 51000782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho HI_CFG Interface Configuration Register Values 51100782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho ------------------------------------------ 51200782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho ===============================================*/ 51300782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define HI_CFG_UART_ENABLE 0x00000004 51400782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define HI_CFG_RST232_ENABLE 0x00000008 51500782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define HI_CFG_CLOCK_REQ_SELECT 0x00000010 51600782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define HI_CFG_HOST_INT_ENABLE 0x00000020 51700782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define HI_CFG_VLYNQ_OUTPUT_ENABLE 0x00000040 51800782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define HI_CFG_HOST_INT_ACTIVE_LOW 0x00000080 51900782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define HI_CFG_UART_TX_OUT_GPIO_15 0x00000100 52000782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define HI_CFG_UART_TX_OUT_GPIO_14 0x00000200 52100782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define HI_CFG_UART_TX_OUT_GPIO_7 0x00000400 522f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 52300782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho#define HI_CFG_DEF_VAL \ 52400782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho (HI_CFG_UART_ENABLE | \ 52500782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho HI_CFG_RST232_ENABLE | \ 52600782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho HI_CFG_CLOCK_REQ_SELECT | \ 52700782136b4d6e2316e0a2a55f3b1fba160e9576eLuciano Coelho HI_CFG_HOST_INT_ENABLE) 528f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho 5295e037e74802a10a71dddbb05585753b2fcbd8ad7Luciano Coelho#define WL127X_REG_FUSE_DATA_2_1 0x050a 5305e037e74802a10a71dddbb05585753b2fcbd8ad7Luciano Coelho#define WL128X_REG_FUSE_DATA_2_1 0x2152 5315e037e74802a10a71dddbb05585753b2fcbd8ad7Luciano Coelho#define PG_VER_MASK 0x3c 5325e037e74802a10a71dddbb05585753b2fcbd8ad7Luciano Coelho#define PG_VER_OFFSET 2 5335e037e74802a10a71dddbb05585753b2fcbd8ad7Luciano Coelho 5345e037e74802a10a71dddbb05585753b2fcbd8ad7Luciano Coelho#define WL127X_PG_MAJOR_VER_MASK 0x3 5355e037e74802a10a71dddbb05585753b2fcbd8ad7Luciano Coelho#define WL127X_PG_MAJOR_VER_OFFSET 0x0 5365e037e74802a10a71dddbb05585753b2fcbd8ad7Luciano Coelho#define WL127X_PG_MINOR_VER_MASK 0xc 5375e037e74802a10a71dddbb05585753b2fcbd8ad7Luciano Coelho#define WL127X_PG_MINOR_VER_OFFSET 0x2 5385e037e74802a10a71dddbb05585753b2fcbd8ad7Luciano Coelho 5395e037e74802a10a71dddbb05585753b2fcbd8ad7Luciano Coelho#define WL128X_PG_MAJOR_VER_MASK 0xc 5405e037e74802a10a71dddbb05585753b2fcbd8ad7Luciano Coelho#define WL128X_PG_MAJOR_VER_OFFSET 0x2 5415e037e74802a10a71dddbb05585753b2fcbd8ad7Luciano Coelho#define WL128X_PG_MINOR_VER_MASK 0x3 5425e037e74802a10a71dddbb05585753b2fcbd8ad7Luciano Coelho#define WL128X_PG_MINOR_VER_OFFSET 0x0 5435e037e74802a10a71dddbb05585753b2fcbd8ad7Luciano Coelho 5445e037e74802a10a71dddbb05585753b2fcbd8ad7Luciano Coelho#define WL127X_PG_GET_MAJOR(pg_ver) ((pg_ver & WL127X_PG_MAJOR_VER_MASK) >> \ 5455e037e74802a10a71dddbb05585753b2fcbd8ad7Luciano Coelho WL127X_PG_MAJOR_VER_OFFSET) 5465e037e74802a10a71dddbb05585753b2fcbd8ad7Luciano Coelho#define WL127X_PG_GET_MINOR(pg_ver) ((pg_ver & WL127X_PG_MINOR_VER_MASK) >> \ 5475e037e74802a10a71dddbb05585753b2fcbd8ad7Luciano Coelho WL127X_PG_MINOR_VER_OFFSET) 5485e037e74802a10a71dddbb05585753b2fcbd8ad7Luciano Coelho#define WL128X_PG_GET_MAJOR(pg_ver) ((pg_ver & WL128X_PG_MAJOR_VER_MASK) >> \ 5495e037e74802a10a71dddbb05585753b2fcbd8ad7Luciano Coelho WL128X_PG_MAJOR_VER_OFFSET) 5505e037e74802a10a71dddbb05585753b2fcbd8ad7Luciano Coelho#define WL128X_PG_GET_MINOR(pg_ver) ((pg_ver & WL128X_PG_MINOR_VER_MASK) >> \ 5515e037e74802a10a71dddbb05585753b2fcbd8ad7Luciano Coelho WL128X_PG_MINOR_VER_OFFSET) 5525e037e74802a10a71dddbb05585753b2fcbd8ad7Luciano Coelho 5535e037e74802a10a71dddbb05585753b2fcbd8ad7Luciano Coelho#define WL12XX_REG_FUSE_BD_ADDR_1 0x00310eb4 5545e037e74802a10a71dddbb05585753b2fcbd8ad7Luciano Coelho#define WL12XX_REG_FUSE_BD_ADDR_2 0x00310eb8 5555e037e74802a10a71dddbb05585753b2fcbd8ad7Luciano Coelho 556f5fc0f86b02afef1119b523623b4cde41475bc8cLuciano Coelho#endif 557