io.h revision 6134323f42b0dbae8e8206414d26cb167b9bedfc
1/*
2 * This file is part of wl1271
3 *
4 * Copyright (C) 1998-2009 Texas Instruments. All rights reserved.
5 * Copyright (C) 2008-2010 Nokia Corporation
6 *
7 * Contact: Luciano Coelho <luciano.coelho@nokia.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
21 * 02110-1301 USA
22 *
23 */
24
25#ifndef __IO_H__
26#define __IO_H__
27
28#include <linux/irqreturn.h>
29
30#define HW_ACCESS_MEMORY_MAX_RANGE	0x1FFC0
31
32#define HW_PARTITION_REGISTERS_ADDR     0x1FFC0
33#define HW_PART0_SIZE_ADDR              (HW_PARTITION_REGISTERS_ADDR)
34#define HW_PART0_START_ADDR             (HW_PARTITION_REGISTERS_ADDR + 4)
35#define HW_PART1_SIZE_ADDR              (HW_PARTITION_REGISTERS_ADDR + 8)
36#define HW_PART1_START_ADDR             (HW_PARTITION_REGISTERS_ADDR + 12)
37#define HW_PART2_SIZE_ADDR              (HW_PARTITION_REGISTERS_ADDR + 16)
38#define HW_PART2_START_ADDR             (HW_PARTITION_REGISTERS_ADDR + 20)
39#define HW_PART3_START_ADDR             (HW_PARTITION_REGISTERS_ADDR + 24)
40
41#define HW_ACCESS_REGISTER_SIZE         4
42
43#define HW_ACCESS_PRAM_MAX_RANGE	0x3c000
44
45struct wl1271;
46
47void wlcore_disable_interrupts(struct wl1271 *wl);
48void wlcore_disable_interrupts_nosync(struct wl1271 *wl);
49void wlcore_enable_interrupts(struct wl1271 *wl);
50
51void wl1271_io_reset(struct wl1271 *wl);
52void wl1271_io_init(struct wl1271 *wl);
53int wlcore_translate_addr(struct wl1271 *wl, int addr);
54
55/* Raw target IO, address is not translated */
56static inline int wlcore_raw_write(struct wl1271 *wl, int addr, void *buf,
57				   size_t len, bool fixed)
58{
59	return wl->if_ops->write(wl->dev, addr, buf, len, fixed);
60}
61
62static inline int wlcore_raw_read(struct wl1271 *wl, int addr, void *buf,
63				  size_t len, bool fixed)
64{
65	return wl->if_ops->read(wl->dev, addr, buf, len, fixed);
66}
67
68static inline int wlcore_raw_read_data(struct wl1271 *wl, int reg, void *buf,
69				       size_t len, bool fixed)
70{
71	return wlcore_raw_read(wl, wl->rtable[reg], buf, len, fixed);
72}
73
74static inline int wlcore_raw_write_data(struct wl1271 *wl, int reg, void *buf,
75					size_t len, bool fixed)
76{
77	return wlcore_raw_write(wl, wl->rtable[reg], buf, len, fixed);
78}
79
80static inline int wlcore_raw_read32(struct wl1271 *wl, int addr, u32 *val)
81{
82	int ret;
83
84	ret = wlcore_raw_read(wl, addr, &wl->buffer_32,
85			      sizeof(wl->buffer_32), false);
86	if (ret < 0)
87		return ret;
88
89	if (val)
90		*val = le32_to_cpu(wl->buffer_32);
91
92	return 0;
93}
94
95static inline void wl1271_raw_write32(struct wl1271 *wl, int addr, u32 val)
96{
97	wl->buffer_32 = cpu_to_le32(val);
98	wlcore_raw_write(wl, addr, &wl->buffer_32,
99			     sizeof(wl->buffer_32), false);
100}
101
102static inline int wlcore_read(struct wl1271 *wl, int addr, void *buf,
103			      size_t len, bool fixed)
104{
105	int physical;
106
107	physical = wlcore_translate_addr(wl, addr);
108
109	return wlcore_raw_read(wl, physical, buf, len, fixed);
110}
111
112static inline int wlcore_write(struct wl1271 *wl, int addr, void *buf,
113			       size_t len, bool fixed)
114{
115	int physical;
116
117	physical = wlcore_translate_addr(wl, addr);
118
119	return wlcore_raw_write(wl, physical, buf, len, fixed);
120}
121
122static inline int wlcore_write_data(struct wl1271 *wl, int reg, void *buf,
123				    size_t len, bool fixed)
124{
125	return wlcore_write(wl, wl->rtable[reg], buf, len, fixed);
126}
127
128static inline int wlcore_read_data(struct wl1271 *wl, int reg, void *buf,
129				    size_t len, bool fixed)
130{
131	return wlcore_read(wl, wl->rtable[reg], buf, len, fixed);
132}
133
134static inline void wl1271_read_hwaddr(struct wl1271 *wl, int hwaddr,
135				      void *buf, size_t len, bool fixed)
136{
137	int physical;
138	int addr;
139
140	/* Addresses are stored internally as addresses to 32 bytes blocks */
141	addr = hwaddr << 5;
142
143	physical = wlcore_translate_addr(wl, addr);
144
145	wlcore_raw_read(wl, physical, buf, len, fixed);
146}
147
148static inline int wlcore_read32(struct wl1271 *wl, int addr, u32 *val)
149{
150	return wlcore_raw_read32(wl, wlcore_translate_addr(wl, addr), val);
151}
152
153static inline void wl1271_write32(struct wl1271 *wl, int addr, u32 val)
154{
155	wl1271_raw_write32(wl, wlcore_translate_addr(wl, addr), val);
156}
157
158static inline int wlcore_read_reg(struct wl1271 *wl, int reg, u32 *val)
159{
160	return wlcore_raw_read32(wl,
161				 wlcore_translate_addr(wl, wl->rtable[reg]),
162				 val);
163}
164
165static inline void wlcore_write_reg(struct wl1271 *wl, int reg, u32 val)
166{
167	wl1271_raw_write32(wl, wlcore_translate_addr(wl, wl->rtable[reg]), val);
168}
169
170static inline void wl1271_power_off(struct wl1271 *wl)
171{
172	int ret;
173
174	if (!test_bit(WL1271_FLAG_GPIO_POWER, &wl->flags))
175		return;
176
177	ret = wl->if_ops->power(wl->dev, false);
178	if (!ret)
179		clear_bit(WL1271_FLAG_GPIO_POWER, &wl->flags);
180}
181
182static inline int wl1271_power_on(struct wl1271 *wl)
183{
184	int ret = wl->if_ops->power(wl->dev, true);
185	if (ret == 0)
186		set_bit(WL1271_FLAG_GPIO_POWER, &wl->flags);
187
188	return ret;
189}
190
191void wlcore_set_partition(struct wl1271 *wl,
192			  const struct wlcore_partition_set *p);
193
194bool wl1271_set_block_size(struct wl1271 *wl);
195
196/* Functions from wl1271_main.c */
197
198int wl1271_tx_dummy_packet(struct wl1271 *wl);
199
200void wlcore_select_partition(struct wl1271 *wl, u8 part);
201
202#endif
203