wlcore.h revision 187e52cc3c9f5ee64136f8b5c4edcb4cf94693e7
1/* 2 * This file is part of wlcore 3 * 4 * Copyright (C) 2011 Texas Instruments Inc. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * version 2 as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 18 * 02110-1301 USA 19 * 20 */ 21 22#ifndef __WLCORE_H__ 23#define __WLCORE_H__ 24 25#include <linux/platform_device.h> 26 27#include "wlcore_i.h" 28#include "event.h" 29#include "boot.h" 30 31/* The maximum number of Tx descriptors in all chip families */ 32#define WLCORE_MAX_TX_DESCRIPTORS 32 33 34/* 35 * We always allocate this number of mac addresses. If we don't 36 * have enough allocated addresses, the LAA bit is used 37 */ 38#define WLCORE_NUM_MAC_ADDRESSES 3 39 40/* wl12xx/wl18xx maximum transmission power (in dBm) */ 41#define WLCORE_MAX_TXPWR 25 42 43/* forward declaration */ 44struct wl1271_tx_hw_descr; 45enum wl_rx_buf_align; 46struct wl1271_rx_descriptor; 47 48struct wlcore_ops { 49 int (*setup)(struct wl1271 *wl); 50 int (*identify_chip)(struct wl1271 *wl); 51 int (*identify_fw)(struct wl1271 *wl); 52 int (*boot)(struct wl1271 *wl); 53 int (*plt_init)(struct wl1271 *wl); 54 int (*trigger_cmd)(struct wl1271 *wl, int cmd_box_addr, 55 void *buf, size_t len); 56 int (*ack_event)(struct wl1271 *wl); 57 int (*wait_for_event)(struct wl1271 *wl, enum wlcore_wait_event event, 58 bool *timeout); 59 int (*process_mailbox_events)(struct wl1271 *wl); 60 u32 (*calc_tx_blocks)(struct wl1271 *wl, u32 len, u32 spare_blks); 61 void (*set_tx_desc_blocks)(struct wl1271 *wl, 62 struct wl1271_tx_hw_descr *desc, 63 u32 blks, u32 spare_blks); 64 void (*set_tx_desc_data_len)(struct wl1271 *wl, 65 struct wl1271_tx_hw_descr *desc, 66 struct sk_buff *skb); 67 enum wl_rx_buf_align (*get_rx_buf_align)(struct wl1271 *wl, 68 u32 rx_desc); 69 int (*prepare_read)(struct wl1271 *wl, u32 rx_desc, u32 len); 70 u32 (*get_rx_packet_len)(struct wl1271 *wl, void *rx_data, 71 u32 data_len); 72 int (*tx_delayed_compl)(struct wl1271 *wl); 73 void (*tx_immediate_compl)(struct wl1271 *wl); 74 int (*hw_init)(struct wl1271 *wl); 75 int (*init_vif)(struct wl1271 *wl, struct wl12xx_vif *wlvif); 76 u32 (*sta_get_ap_rate_mask)(struct wl1271 *wl, 77 struct wl12xx_vif *wlvif); 78 int (*get_pg_ver)(struct wl1271 *wl, s8 *ver); 79 int (*get_mac)(struct wl1271 *wl); 80 void (*set_tx_desc_csum)(struct wl1271 *wl, 81 struct wl1271_tx_hw_descr *desc, 82 struct sk_buff *skb); 83 void (*set_rx_csum)(struct wl1271 *wl, 84 struct wl1271_rx_descriptor *desc, 85 struct sk_buff *skb); 86 u32 (*ap_get_mimo_wide_rate_mask)(struct wl1271 *wl, 87 struct wl12xx_vif *wlvif); 88 int (*debugfs_init)(struct wl1271 *wl, struct dentry *rootdir); 89 int (*handle_static_data)(struct wl1271 *wl, 90 struct wl1271_static_data *static_data); 91 int (*scan_start)(struct wl1271 *wl, struct wl12xx_vif *wlvif, 92 struct cfg80211_scan_request *req); 93 int (*scan_stop)(struct wl1271 *wl, struct wl12xx_vif *wlvif); 94 int (*sched_scan_start)(struct wl1271 *wl, struct wl12xx_vif *wlvif, 95 struct cfg80211_sched_scan_request *req, 96 struct ieee80211_sched_scan_ies *ies); 97 void (*sched_scan_stop)(struct wl1271 *wl, struct wl12xx_vif *wlvif); 98 int (*get_spare_blocks)(struct wl1271 *wl, bool is_gem); 99 int (*set_key)(struct wl1271 *wl, enum set_key_cmd cmd, 100 struct ieee80211_vif *vif, 101 struct ieee80211_sta *sta, 102 struct ieee80211_key_conf *key_conf); 103 int (*channel_switch)(struct wl1271 *wl, 104 struct wl12xx_vif *wlvif, 105 struct ieee80211_channel_switch *ch_switch); 106 u32 (*pre_pkt_send)(struct wl1271 *wl, u32 buf_offset, u32 last_len); 107 void (*sta_rc_update)(struct wl1271 *wl, struct wl12xx_vif *wlvif, 108 struct ieee80211_sta *sta, u32 changed); 109 int (*set_peer_cap)(struct wl1271 *wl, 110 struct ieee80211_sta_ht_cap *ht_cap, 111 bool allow_ht_operation, 112 u32 rate_set, u8 hlid); 113 bool (*lnk_high_prio)(struct wl1271 *wl, u8 hlid, 114 struct wl1271_link *lnk); 115 bool (*lnk_low_prio)(struct wl1271 *wl, u8 hlid, 116 struct wl1271_link *lnk); 117}; 118 119enum wlcore_partitions { 120 PART_DOWN, 121 PART_WORK, 122 PART_BOOT, 123 PART_DRPW, 124 PART_TOP_PRCM_ELP_SOC, 125 PART_PHY_INIT, 126 127 PART_TABLE_LEN, 128}; 129 130struct wlcore_partition { 131 u32 size; 132 u32 start; 133}; 134 135struct wlcore_partition_set { 136 struct wlcore_partition mem; 137 struct wlcore_partition reg; 138 struct wlcore_partition mem2; 139 struct wlcore_partition mem3; 140}; 141 142enum wlcore_registers { 143 /* register addresses, used with partition translation */ 144 REG_ECPU_CONTROL, 145 REG_INTERRUPT_NO_CLEAR, 146 REG_INTERRUPT_ACK, 147 REG_COMMAND_MAILBOX_PTR, 148 REG_EVENT_MAILBOX_PTR, 149 REG_INTERRUPT_TRIG, 150 REG_INTERRUPT_MASK, 151 REG_PC_ON_RECOVERY, 152 REG_CHIP_ID_B, 153 REG_CMD_MBOX_ADDRESS, 154 155 /* data access memory addresses, used with partition translation */ 156 REG_SLV_MEM_DATA, 157 REG_SLV_REG_DATA, 158 159 /* raw data access memory addresses */ 160 REG_RAW_FW_STATUS_ADDR, 161 162 REG_TABLE_LEN, 163}; 164 165struct wl1271_stats { 166 void *fw_stats; 167 unsigned long fw_stats_update; 168 size_t fw_stats_len; 169 170 unsigned int retry_count; 171 unsigned int excessive_retries; 172}; 173 174struct wl1271 { 175 bool initialized; 176 struct ieee80211_hw *hw; 177 bool mac80211_registered; 178 179 struct device *dev; 180 struct platform_device *pdev; 181 182 void *if_priv; 183 184 struct wl1271_if_operations *if_ops; 185 186 int irq; 187 188 spinlock_t wl_lock; 189 190 enum wlcore_state state; 191 enum wl12xx_fw_type fw_type; 192 bool plt; 193 enum plt_mode plt_mode; 194 u8 fem_manuf; 195 u8 last_vif_count; 196 struct mutex mutex; 197 198 unsigned long flags; 199 200 struct wlcore_partition_set curr_part; 201 202 struct wl1271_chip chip; 203 204 int cmd_box_addr; 205 206 u8 *fw; 207 size_t fw_len; 208 void *nvs; 209 size_t nvs_len; 210 211 s8 hw_pg_ver; 212 213 /* address read from the fuse ROM */ 214 u32 fuse_oui_addr; 215 u32 fuse_nic_addr; 216 217 /* we have up to 2 MAC addresses */ 218 struct mac_address addresses[WLCORE_NUM_MAC_ADDRESSES]; 219 int channel; 220 u8 system_hlid; 221 222 unsigned long links_map[BITS_TO_LONGS(WL12XX_MAX_LINKS)]; 223 unsigned long roles_map[BITS_TO_LONGS(WL12XX_MAX_ROLES)]; 224 unsigned long roc_map[BITS_TO_LONGS(WL12XX_MAX_ROLES)]; 225 unsigned long rate_policies_map[ 226 BITS_TO_LONGS(WL12XX_MAX_RATE_POLICIES)]; 227 unsigned long klv_templates_map[ 228 BITS_TO_LONGS(WLCORE_MAX_KLV_TEMPLATES)]; 229 230 u8 session_ids[WL12XX_MAX_LINKS]; 231 232 struct list_head wlvif_list; 233 234 u8 sta_count; 235 u8 ap_count; 236 237 struct wl1271_acx_mem_map *target_mem_map; 238 239 /* Accounting for allocated / available TX blocks on HW */ 240 u32 tx_blocks_freed; 241 u32 tx_blocks_available; 242 u32 tx_allocated_blocks; 243 u32 tx_results_count; 244 245 /* Accounting for allocated / available Tx packets in HW */ 246 u32 tx_pkts_freed[NUM_TX_QUEUES]; 247 u32 tx_allocated_pkts[NUM_TX_QUEUES]; 248 249 /* Transmitted TX packets counter for chipset interface */ 250 u32 tx_packets_count; 251 252 /* Time-offset between host and chipset clocks */ 253 s64 time_offset; 254 255 /* Frames scheduled for transmission, not handled yet */ 256 int tx_queue_count[NUM_TX_QUEUES]; 257 unsigned long queue_stop_reasons[ 258 NUM_TX_QUEUES * WLCORE_NUM_MAC_ADDRESSES]; 259 260 /* Frames received, not handled yet by mac80211 */ 261 struct sk_buff_head deferred_rx_queue; 262 263 /* Frames sent, not returned yet to mac80211 */ 264 struct sk_buff_head deferred_tx_queue; 265 266 struct work_struct tx_work; 267 struct workqueue_struct *freezable_wq; 268 269 /* Pending TX frames */ 270 unsigned long tx_frames_map[BITS_TO_LONGS(WLCORE_MAX_TX_DESCRIPTORS)]; 271 struct sk_buff *tx_frames[WLCORE_MAX_TX_DESCRIPTORS]; 272 int tx_frames_cnt; 273 274 /* FW Rx counter */ 275 u32 rx_counter; 276 277 /* Intermediate buffer, used for packet aggregation */ 278 u8 *aggr_buf; 279 u32 aggr_buf_size; 280 281 /* Reusable dummy packet template */ 282 struct sk_buff *dummy_packet; 283 284 /* Network stack work */ 285 struct work_struct netstack_work; 286 287 /* FW log buffer */ 288 u8 *fwlog; 289 290 /* Number of valid bytes in the FW log buffer */ 291 ssize_t fwlog_size; 292 293 /* Sysfs FW log entry readers wait queue */ 294 wait_queue_head_t fwlog_waitq; 295 296 /* Hardware recovery work */ 297 struct work_struct recovery_work; 298 bool watchdog_recovery; 299 300 /* Reg domain last configuration */ 301 u32 reg_ch_conf_last[2]; 302 /* Reg domain pending configuration */ 303 u32 reg_ch_conf_pending[2]; 304 305 /* Pointer that holds DMA-friendly block for the mailbox */ 306 void *mbox; 307 308 /* The mbox event mask */ 309 u32 event_mask; 310 311 /* Mailbox pointers */ 312 u32 mbox_size; 313 u32 mbox_ptr[2]; 314 315 /* Are we currently scanning */ 316 struct wl12xx_vif *scan_wlvif; 317 struct wl1271_scan scan; 318 struct delayed_work scan_complete_work; 319 320 struct ieee80211_vif *roc_vif; 321 struct delayed_work roc_complete_work; 322 323 struct wl12xx_vif *sched_vif; 324 325 /* The current band */ 326 enum ieee80211_band band; 327 328 struct completion *elp_compl; 329 struct delayed_work elp_work; 330 331 /* in dBm */ 332 int power_level; 333 334 struct wl1271_stats stats; 335 336 __le32 *buffer_32; 337 u32 buffer_cmd; 338 u32 buffer_busyword[WL1271_BUSY_WORD_CNT]; 339 340 struct wl_fw_status_1 *fw_status_1; 341 struct wl_fw_status_2 *fw_status_2; 342 struct wl1271_tx_hw_res_if *tx_res_if; 343 344 /* Current chipset configuration */ 345 struct wlcore_conf conf; 346 347 bool sg_enabled; 348 349 bool enable_11a; 350 351 int recovery_count; 352 353 /* Most recently reported noise in dBm */ 354 s8 noise; 355 356 /* bands supported by this instance of wl12xx */ 357 struct ieee80211_supported_band bands[WLCORE_NUM_BANDS]; 358 359 /* 360 * wowlan trigger was configured during suspend. 361 * (currently, only "ANY" trigger is supported) 362 */ 363 bool wow_enabled; 364 bool irq_wake_enabled; 365 366 /* 367 * AP-mode - links indexed by HLID. The global and broadcast links 368 * are always active. 369 */ 370 struct wl1271_link links[WL12XX_MAX_LINKS]; 371 372 /* number of currently active links */ 373 int active_link_count; 374 375 /* Fast/slow links bitmap according to FW */ 376 u32 fw_fast_lnk_map; 377 378 /* AP-mode - a bitmap of links currently in PS mode according to FW */ 379 u32 ap_fw_ps_map; 380 381 /* AP-mode - a bitmap of links currently in PS mode in mac80211 */ 382 unsigned long ap_ps_map; 383 384 /* Quirks of specific hardware revisions */ 385 unsigned int quirks; 386 387 /* Platform limitations */ 388 unsigned int platform_quirks; 389 390 /* number of currently active RX BA sessions */ 391 int ba_rx_session_count; 392 393 /* Maximum number of supported RX BA sessions */ 394 int ba_rx_session_count_max; 395 396 /* AP-mode - number of currently connected stations */ 397 int active_sta_count; 398 399 /* last wlvif we transmitted from */ 400 struct wl12xx_vif *last_wlvif; 401 402 /* work to fire when Tx is stuck */ 403 struct delayed_work tx_watchdog_work; 404 405 struct wlcore_ops *ops; 406 /* pointer to the lower driver partition table */ 407 const struct wlcore_partition_set *ptable; 408 /* pointer to the lower driver register table */ 409 const int *rtable; 410 /* name of the firmwares to load - for PLT, single role, multi-role */ 411 const char *plt_fw_name; 412 const char *sr_fw_name; 413 const char *mr_fw_name; 414 415 u8 scan_templ_id_2_4; 416 u8 scan_templ_id_5; 417 u8 sched_scan_templ_id_2_4; 418 u8 sched_scan_templ_id_5; 419 u8 max_channels_5; 420 421 /* per-chip-family private structure */ 422 void *priv; 423 424 /* number of TX descriptors the HW supports. */ 425 u32 num_tx_desc; 426 /* number of RX descriptors the HW supports. */ 427 u32 num_rx_desc; 428 429 /* translate HW Tx rates to standard rate-indices */ 430 const u8 **band_rate_to_idx; 431 432 /* size of table for HW rates that can be received from chip */ 433 u8 hw_tx_rate_tbl_size; 434 435 /* this HW rate and below are considered HT rates for this chip */ 436 u8 hw_min_ht_rate; 437 438 /* HW HT (11n) capabilities */ 439 struct ieee80211_sta_ht_cap ht_cap[WLCORE_NUM_BANDS]; 440 441 /* size of the private FW status data */ 442 size_t fw_status_priv_len; 443 444 /* RX Data filter rule state - enabled/disabled */ 445 bool rx_filter_enabled[WL1271_MAX_RX_FILTERS]; 446 447 /* size of the private static data */ 448 size_t static_data_priv_len; 449 450 /* the current channel type */ 451 enum nl80211_channel_type channel_type; 452 453 /* mutex for protecting the tx_flush function */ 454 struct mutex flush_mutex; 455 456 /* sleep auth value currently configured to FW */ 457 int sleep_auth; 458 459 /* the number of allocated MAC addresses in this chip */ 460 int num_mac_addr; 461 462 /* minimum FW version required for the driver to work in single-role */ 463 unsigned int min_sr_fw_ver[NUM_FW_VER]; 464 465 /* minimum FW version required for the driver to work in multi-role */ 466 unsigned int min_mr_fw_ver[NUM_FW_VER]; 467 468 struct completion nvs_loading_complete; 469 470 /* number of concurrent channels the HW supports */ 471 u32 num_channels; 472}; 473 474int wlcore_probe(struct wl1271 *wl, struct platform_device *pdev); 475int wlcore_remove(struct platform_device *pdev); 476struct ieee80211_hw *wlcore_alloc_hw(size_t priv_size, u32 aggr_buf_size, 477 u32 mbox_size); 478int wlcore_free_hw(struct wl1271 *wl); 479int wlcore_set_key(struct wl1271 *wl, enum set_key_cmd cmd, 480 struct ieee80211_vif *vif, 481 struct ieee80211_sta *sta, 482 struct ieee80211_key_conf *key_conf); 483void wlcore_regdomain_config(struct wl1271 *wl); 484void wlcore_update_inconn_sta(struct wl1271 *wl, struct wl12xx_vif *wlvif, 485 struct wl1271_station *wl_sta, bool in_conn); 486 487static inline void 488wlcore_set_ht_cap(struct wl1271 *wl, enum ieee80211_band band, 489 struct ieee80211_sta_ht_cap *ht_cap) 490{ 491 memcpy(&wl->ht_cap[band], ht_cap, sizeof(*ht_cap)); 492} 493 494/* Tell wlcore not to care about this element when checking the version */ 495#define WLCORE_FW_VER_IGNORE -1 496 497static inline void 498wlcore_set_min_fw_ver(struct wl1271 *wl, unsigned int chip, 499 unsigned int iftype_sr, unsigned int major_sr, 500 unsigned int subtype_sr, unsigned int minor_sr, 501 unsigned int iftype_mr, unsigned int major_mr, 502 unsigned int subtype_mr, unsigned int minor_mr) 503{ 504 wl->min_sr_fw_ver[FW_VER_CHIP] = chip; 505 wl->min_sr_fw_ver[FW_VER_IF_TYPE] = iftype_sr; 506 wl->min_sr_fw_ver[FW_VER_MAJOR] = major_sr; 507 wl->min_sr_fw_ver[FW_VER_SUBTYPE] = subtype_sr; 508 wl->min_sr_fw_ver[FW_VER_MINOR] = minor_sr; 509 510 wl->min_mr_fw_ver[FW_VER_CHIP] = chip; 511 wl->min_mr_fw_ver[FW_VER_IF_TYPE] = iftype_mr; 512 wl->min_mr_fw_ver[FW_VER_MAJOR] = major_mr; 513 wl->min_mr_fw_ver[FW_VER_SUBTYPE] = subtype_mr; 514 wl->min_mr_fw_ver[FW_VER_MINOR] = minor_mr; 515} 516 517/* Firmware image load chunk size */ 518#define CHUNK_SIZE 16384 519 520/* Quirks */ 521 522/* Each RX/TX transaction requires an end-of-transaction transfer */ 523#define WLCORE_QUIRK_END_OF_TRANSACTION BIT(0) 524 525/* the first start_role(sta) sometimes doesn't work on wl12xx */ 526#define WLCORE_QUIRK_START_STA_FAILS BIT(1) 527 528/* wl127x and SPI don't support SDIO block size alignment */ 529#define WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN BIT(2) 530 531/* means aggregated Rx packets are aligned to a SDIO block */ 532#define WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN BIT(3) 533 534/* Older firmwares did not implement the FW logger over bus feature */ 535#define WLCORE_QUIRK_FWLOG_NOT_IMPLEMENTED BIT(4) 536 537/* Older firmwares use an old NVS format */ 538#define WLCORE_QUIRK_LEGACY_NVS BIT(5) 539 540/* pad only the last frame in the aggregate buffer */ 541#define WLCORE_QUIRK_TX_PAD_LAST_FRAME BIT(7) 542 543/* extra header space is required for TKIP */ 544#define WLCORE_QUIRK_TKIP_HEADER_SPACE BIT(8) 545 546/* Some firmwares not support sched scans while connected */ 547#define WLCORE_QUIRK_NO_SCHED_SCAN_WHILE_CONN BIT(9) 548 549/* separate probe response templates for one-shot and sched scans */ 550#define WLCORE_QUIRK_DUAL_PROBE_TMPL BIT(10) 551 552/* Firmware requires reg domain configuration for active calibration */ 553#define WLCORE_QUIRK_REGDOMAIN_CONF BIT(11) 554 555/* The FW only support a zero session id for AP */ 556#define WLCORE_QUIRK_AP_ZERO_SESSION_ID BIT(12) 557 558/* TODO: move all these common registers and values elsewhere */ 559#define HW_ACCESS_ELP_CTRL_REG 0x1FFFC 560 561/* ELP register commands */ 562#define ELPCTRL_WAKE_UP 0x1 563#define ELPCTRL_WAKE_UP_WLAN_READY 0x5 564#define ELPCTRL_SLEEP 0x0 565/* ELP WLAN_READY bit */ 566#define ELPCTRL_WLAN_READY 0x2 567 568/************************************************************************* 569 570 Interrupt Trigger Register (Host -> WiLink) 571 572**************************************************************************/ 573 574/* Hardware to Embedded CPU Interrupts - first 32-bit register set */ 575 576/* 577 * The host sets this bit to inform the Wlan 578 * FW that a TX packet is in the XFER 579 * Buffer #0. 580 */ 581#define INTR_TRIG_TX_PROC0 BIT(2) 582 583/* 584 * The host sets this bit to inform the FW 585 * that it read a packet from RX XFER 586 * Buffer #0. 587 */ 588#define INTR_TRIG_RX_PROC0 BIT(3) 589 590#define INTR_TRIG_DEBUG_ACK BIT(4) 591 592#define INTR_TRIG_STATE_CHANGED BIT(5) 593 594/* Hardware to Embedded CPU Interrupts - second 32-bit register set */ 595 596/* 597 * The host sets this bit to inform the FW 598 * that it read a packet from RX XFER 599 * Buffer #1. 600 */ 601#define INTR_TRIG_RX_PROC1 BIT(17) 602 603/* 604 * The host sets this bit to inform the Wlan 605 * hardware that a TX packet is in the XFER 606 * Buffer #1. 607 */ 608#define INTR_TRIG_TX_PROC1 BIT(18) 609 610#define ACX_SLV_SOFT_RESET_BIT BIT(1) 611#define SOFT_RESET_MAX_TIME 1000000 612#define SOFT_RESET_STALL_TIME 1000 613 614#define ECPU_CONTROL_HALT 0x00000101 615 616#define WELP_ARM_COMMAND_VAL 0x4 617 618#endif /* __WLCORE_H__ */ 619