wlcore.h revision ebc7e57ddd01ffa4c996dde7095746259693755d 
1/*
2 * This file is part of wlcore
3 *
4 * Copyright (C) 2011 Texas Instruments Inc.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22#ifndef __WLCORE_H__
23#define __WLCORE_H__
24
25#include <linux/platform_device.h>
26
27#include "wl12xx.h"
28#include "event.h"
29
30/* The maximum number of Tx descriptors in all chip families */
31#define WLCORE_MAX_TX_DESCRIPTORS 32
32
33/* forward declaration */
34struct wl1271_tx_hw_descr;
35enum wl_rx_buf_align;
36struct wl1271_rx_descriptor;
37
38struct wlcore_ops {
39	int (*identify_chip)(struct wl1271 *wl);
40	int (*identify_fw)(struct wl1271 *wl);
41	int (*boot)(struct wl1271 *wl);
42	void (*trigger_cmd)(struct wl1271 *wl, int cmd_box_addr,
43			    void *buf, size_t len);
44	void (*ack_event)(struct wl1271 *wl);
45	u32 (*calc_tx_blocks)(struct wl1271 *wl, u32 len, u32 spare_blks);
46	void (*set_tx_desc_blocks)(struct wl1271 *wl,
47				   struct wl1271_tx_hw_descr *desc,
48				   u32 blks, u32 spare_blks);
49	void (*set_tx_desc_data_len)(struct wl1271 *wl,
50				     struct wl1271_tx_hw_descr *desc,
51				     struct sk_buff *skb);
52	enum wl_rx_buf_align (*get_rx_buf_align)(struct wl1271 *wl,
53						 u32 rx_desc);
54	void (*prepare_read)(struct wl1271 *wl, u32 rx_desc, u32 len);
55	u32 (*get_rx_packet_len)(struct wl1271 *wl, void *rx_data,
56				 u32 data_len);
57	void (*tx_delayed_compl)(struct wl1271 *wl);
58	void (*tx_immediate_compl)(struct wl1271 *wl);
59	int (*hw_init)(struct wl1271 *wl);
60	int (*init_vif)(struct wl1271 *wl, struct wl12xx_vif *wlvif);
61	u32 (*sta_get_ap_rate_mask)(struct wl1271 *wl,
62				    struct wl12xx_vif *wlvif);
63	s8 (*get_pg_ver)(struct wl1271 *wl);
64	void (*get_mac)(struct wl1271 *wl);
65	void (*set_tx_desc_csum)(struct wl1271 *wl,
66				 struct wl1271_tx_hw_descr *desc,
67				 struct sk_buff *skb);
68	void (*set_rx_csum)(struct wl1271 *wl,
69			    struct wl1271_rx_descriptor *desc,
70			    struct sk_buff *skb);
71	u32 (*ap_get_mimo_wide_rate_mask)(struct wl1271 *wl,
72					  struct wl12xx_vif *wlvif);
73};
74
75enum wlcore_partitions {
76	PART_DOWN,
77	PART_WORK,
78	PART_BOOT,
79	PART_DRPW,
80	PART_TOP_PRCM_ELP_SOC,
81	PART_PHY_INIT,
82
83	PART_TABLE_LEN,
84};
85
86struct wlcore_partition {
87	u32 size;
88	u32 start;
89};
90
91struct wlcore_partition_set {
92	struct wlcore_partition mem;
93	struct wlcore_partition reg;
94	struct wlcore_partition mem2;
95	struct wlcore_partition mem3;
96};
97
98enum wlcore_registers {
99	/* register addresses, used with partition translation */
100	REG_ECPU_CONTROL,
101	REG_INTERRUPT_NO_CLEAR,
102	REG_INTERRUPT_ACK,
103	REG_COMMAND_MAILBOX_PTR,
104	REG_EVENT_MAILBOX_PTR,
105	REG_INTERRUPT_TRIG,
106	REG_INTERRUPT_MASK,
107	REG_PC_ON_RECOVERY,
108	REG_CHIP_ID_B,
109	REG_CMD_MBOX_ADDRESS,
110
111	/* data access memory addresses, used with partition translation */
112	REG_SLV_MEM_DATA,
113	REG_SLV_REG_DATA,
114
115	/* raw data access memory addresses */
116	REG_RAW_FW_STATUS_ADDR,
117
118	REG_TABLE_LEN,
119};
120
121struct wl1271 {
122	struct ieee80211_hw *hw;
123	bool mac80211_registered;
124
125	struct device *dev;
126
127	void *if_priv;
128
129	struct wl1271_if_operations *if_ops;
130
131	void (*set_power)(bool enable);
132	int irq;
133	int ref_clock;
134
135	spinlock_t wl_lock;
136
137	enum wl1271_state state;
138	enum wl12xx_fw_type fw_type;
139	bool plt;
140	u8 last_vif_count;
141	struct mutex mutex;
142
143	unsigned long flags;
144
145	struct wlcore_partition_set curr_part;
146
147	struct wl1271_chip chip;
148
149	int cmd_box_addr;
150
151	u8 *fw;
152	size_t fw_len;
153	void *nvs;
154	size_t nvs_len;
155
156	s8 hw_pg_ver;
157
158	/* address read from the fuse ROM */
159	u32 fuse_oui_addr;
160	u32 fuse_nic_addr;
161
162	/* we have up to 2 MAC addresses */
163	struct mac_address addresses[2];
164	int channel;
165	u8 system_hlid;
166
167	unsigned long links_map[BITS_TO_LONGS(WL12XX_MAX_LINKS)];
168	unsigned long roles_map[BITS_TO_LONGS(WL12XX_MAX_ROLES)];
169	unsigned long roc_map[BITS_TO_LONGS(WL12XX_MAX_ROLES)];
170	unsigned long rate_policies_map[
171			BITS_TO_LONGS(WL12XX_MAX_RATE_POLICIES)];
172
173	struct list_head wlvif_list;
174
175	u8 sta_count;
176	u8 ap_count;
177
178	struct wl1271_acx_mem_map *target_mem_map;
179
180	/* Accounting for allocated / available TX blocks on HW */
181	u32 tx_blocks_freed;
182	u32 tx_blocks_available;
183	u32 tx_allocated_blocks;
184	u32 tx_results_count;
185
186	/* Accounting for allocated / available Tx packets in HW */
187	u32 tx_pkts_freed[NUM_TX_QUEUES];
188	u32 tx_allocated_pkts[NUM_TX_QUEUES];
189
190	/* Transmitted TX packets counter for chipset interface */
191	u32 tx_packets_count;
192
193	/* Time-offset between host and chipset clocks */
194	s64 time_offset;
195
196	/* Frames scheduled for transmission, not handled yet */
197	int tx_queue_count[NUM_TX_QUEUES];
198	long stopped_queues_map;
199
200	/* Frames received, not handled yet by mac80211 */
201	struct sk_buff_head deferred_rx_queue;
202
203	/* Frames sent, not returned yet to mac80211 */
204	struct sk_buff_head deferred_tx_queue;
205
206	struct work_struct tx_work;
207	struct workqueue_struct *freezable_wq;
208
209	/* Pending TX frames */
210	unsigned long tx_frames_map[BITS_TO_LONGS(WLCORE_MAX_TX_DESCRIPTORS)];
211	struct sk_buff *tx_frames[WLCORE_MAX_TX_DESCRIPTORS];
212	int tx_frames_cnt;
213
214	/* FW Rx counter */
215	u32 rx_counter;
216
217	/* Rx memory pool address */
218	struct wl1271_rx_mem_pool_addr rx_mem_pool_addr;
219
220	/* Intermediate buffer, used for packet aggregation */
221	u8 *aggr_buf;
222
223	/* Reusable dummy packet template */
224	struct sk_buff *dummy_packet;
225
226	/* Network stack work  */
227	struct work_struct netstack_work;
228
229	/* FW log buffer */
230	u8 *fwlog;
231
232	/* Number of valid bytes in the FW log buffer */
233	ssize_t fwlog_size;
234
235	/* Sysfs FW log entry readers wait queue */
236	wait_queue_head_t fwlog_waitq;
237
238	/* Hardware recovery work */
239	struct work_struct recovery_work;
240
241	/* Pointer that holds DMA-friendly block for the mailbox */
242	struct event_mailbox *mbox;
243
244	/* The mbox event mask */
245	u32 event_mask;
246
247	/* Mailbox pointers */
248	u32 mbox_ptr[2];
249
250	/* Are we currently scanning */
251	struct ieee80211_vif *scan_vif;
252	struct wl1271_scan scan;
253	struct delayed_work scan_complete_work;
254
255	/* Connection loss work */
256	struct delayed_work connection_loss_work;
257
258	bool sched_scanning;
259
260	/* The current band */
261	enum ieee80211_band band;
262
263	struct completion *elp_compl;
264	struct delayed_work elp_work;
265
266	/* in dBm */
267	int power_level;
268
269	struct wl1271_stats stats;
270
271	__le32 buffer_32;
272	u32 buffer_cmd;
273	u32 buffer_busyword[WL1271_BUSY_WORD_CNT];
274
275	struct wl_fw_status *fw_status;
276	struct wl1271_tx_hw_res_if *tx_res_if;
277
278	/* Current chipset configuration */
279	struct wlcore_conf conf;
280
281	bool sg_enabled;
282
283	bool enable_11a;
284
285	/* Most recently reported noise in dBm */
286	s8 noise;
287
288	/* bands supported by this instance of wl12xx */
289	struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
290
291	int tcxo_clock;
292
293	/*
294	 * wowlan trigger was configured during suspend.
295	 * (currently, only "ANY" trigger is supported)
296	 */
297	bool wow_enabled;
298	bool irq_wake_enabled;
299
300	/*
301	 * AP-mode - links indexed by HLID. The global and broadcast links
302	 * are always active.
303	 */
304	struct wl1271_link links[WL12XX_MAX_LINKS];
305
306	/* AP-mode - a bitmap of links currently in PS mode according to FW */
307	u32 ap_fw_ps_map;
308
309	/* AP-mode - a bitmap of links currently in PS mode in mac80211 */
310	unsigned long ap_ps_map;
311
312	/* Quirks of specific hardware revisions */
313	unsigned int quirks;
314
315	/* Platform limitations */
316	unsigned int platform_quirks;
317
318	/* number of currently active RX BA sessions */
319	int ba_rx_session_count;
320
321	/* AP-mode - number of currently connected stations */
322	int active_sta_count;
323
324	/* last wlvif we transmitted from */
325	struct wl12xx_vif *last_wlvif;
326
327	/* work to fire when Tx is stuck */
328	struct delayed_work tx_watchdog_work;
329
330	struct wlcore_ops *ops;
331	/* pointer to the lower driver partition table */
332	const struct wlcore_partition_set *ptable;
333	/* pointer to the lower driver register table */
334	const int *rtable;
335	/* name of the firmwares to load - for PLT, single role, multi-role */
336	const char *plt_fw_name;
337	const char *sr_fw_name;
338	const char *mr_fw_name;
339
340	/* per-chip-family private structure */
341	void *priv;
342
343	/* number of TX descriptors the HW supports. */
344	u32 num_tx_desc;
345
346	/* spare Tx blocks for normal/GEM operating modes */
347	u32 normal_tx_spare;
348	u32 gem_tx_spare;
349
350	/* translate HW Tx rates to standard rate-indices */
351	const u8 **band_rate_to_idx;
352
353	/* size of table for HW rates that can be received from chip */
354	u8 hw_tx_rate_tbl_size;
355
356	/* this HW rate and below are considered HT rates for this chip */
357	u8 hw_min_ht_rate;
358
359	/* HW HT (11n) capabilities */
360	struct ieee80211_sta_ht_cap ht_cap;
361
362	/* size of the private FW status data */
363	size_t fw_status_priv_len;
364
365	/* RX Data filter rule state - enabled/disabled */
366	bool rx_filter_enabled[WL1271_MAX_RX_FILTERS];
367
368	/* the current channel type */
369	enum nl80211_channel_type channel_type;
370};
371
372int __devinit wlcore_probe(struct wl1271 *wl, struct platform_device *pdev);
373int __devexit wlcore_remove(struct platform_device *pdev);
374struct ieee80211_hw *wlcore_alloc_hw(size_t priv_size);
375int wlcore_free_hw(struct wl1271 *wl);
376
377/* Firmware image load chunk size */
378#define CHUNK_SIZE	16384
379
380/* Quirks */
381
382/* Each RX/TX transaction requires an end-of-transaction transfer */
383#define WLCORE_QUIRK_END_OF_TRANSACTION		BIT(0)
384
385/* wl127x and SPI don't support SDIO block size alignment */
386#define WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN		BIT(2)
387
388/* means aggregated Rx packets are aligned to a SDIO block */
389#define WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN		BIT(3)
390
391/* Older firmwares did not implement the FW logger over bus feature */
392#define WLCORE_QUIRK_FWLOG_NOT_IMPLEMENTED	BIT(4)
393
394/* Older firmwares use an old NVS format */
395#define WLCORE_QUIRK_LEGACY_NVS			BIT(5)
396
397/* Some firmwares may not support ELP */
398#define WLCORE_QUIRK_NO_ELP			BIT(6)
399
400/* TODO: move to the lower drivers when all usages are abstracted */
401#define CHIP_ID_1271_PG10              (0x4030101)
402#define CHIP_ID_1271_PG20              (0x4030111)
403#define CHIP_ID_1283_PG10              (0x05030101)
404#define CHIP_ID_1283_PG20              (0x05030111)
405
406/* TODO: move all these common registers and values elsewhere */
407#define HW_ACCESS_ELP_CTRL_REG		0x1FFFC
408
409/* ELP register commands */
410#define ELPCTRL_WAKE_UP             0x1
411#define ELPCTRL_WAKE_UP_WLAN_READY  0x5
412#define ELPCTRL_SLEEP               0x0
413/* ELP WLAN_READY bit */
414#define ELPCTRL_WLAN_READY          0x2
415
416/*************************************************************************
417
418    Interrupt Trigger Register (Host -> WiLink)
419
420**************************************************************************/
421
422/* Hardware to Embedded CPU Interrupts - first 32-bit register set */
423
424/*
425 * The host sets this bit to inform the Wlan
426 * FW that a TX packet is in the XFER
427 * Buffer #0.
428 */
429#define INTR_TRIG_TX_PROC0 BIT(2)
430
431/*
432 * The host sets this bit to inform the FW
433 * that it read a packet from RX XFER
434 * Buffer #0.
435 */
436#define INTR_TRIG_RX_PROC0 BIT(3)
437
438#define INTR_TRIG_DEBUG_ACK BIT(4)
439
440#define INTR_TRIG_STATE_CHANGED BIT(5)
441
442/* Hardware to Embedded CPU Interrupts - second 32-bit register set */
443
444/*
445 * The host sets this bit to inform the FW
446 * that it read a packet from RX XFER
447 * Buffer #1.
448 */
449#define INTR_TRIG_RX_PROC1 BIT(17)
450
451/*
452 * The host sets this bit to inform the Wlan
453 * hardware that a TX packet is in the XFER
454 * Buffer #1.
455 */
456#define INTR_TRIG_TX_PROC1 BIT(18)
457
458#define ACX_SLV_SOFT_RESET_BIT	BIT(1)
459#define SOFT_RESET_MAX_TIME	1000000
460#define SOFT_RESET_STALL_TIME	1000
461
462#define ECPU_CONTROL_HALT	0x00000101
463
464#define WELP_ARM_COMMAND_VAL	0x4
465
466#endif /* __WLCORE_H__ */
467