1b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li/* 2b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li * Freescale FlexTimer Module (FTM) PWM Driver 3b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li * 4b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li * Copyright 2012-2013 Freescale Semiconductor, Inc. 5b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li * 6b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li * This program is free software; you can redistribute it and/or modify 7b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li * it under the terms of the GNU General Public License as published by 8b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li * the Free Software Foundation; either version 2 of the License, or 9b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li * (at your option) any later version. 10b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li */ 11b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 12b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li#include <linux/clk.h> 13b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li#include <linux/err.h> 14b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li#include <linux/io.h> 15b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li#include <linux/kernel.h> 16b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li#include <linux/module.h> 17b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li#include <linux/mutex.h> 18b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li#include <linux/of_address.h> 19b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li#include <linux/platform_device.h> 20b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li#include <linux/pwm.h> 2142fa98a9c3609c1aff466cb847e421c611cc9157Xiubo Li#include <linux/regmap.h> 22b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li#include <linux/slab.h> 23b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 24b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li#define FTM_SC 0x00 25cd6d92d2aa1556b22cd05acbc5f2cc8e5caafcc4Xiubo Li#define FTM_SC_CLK_MASK_SHIFT 3 26cd6d92d2aa1556b22cd05acbc5f2cc8e5caafcc4Xiubo Li#define FTM_SC_CLK_MASK (3 << FTM_SC_CLK_MASK_SHIFT) 27cd6d92d2aa1556b22cd05acbc5f2cc8e5caafcc4Xiubo Li#define FTM_SC_CLK(c) (((c) + 1) << FTM_SC_CLK_MASK_SHIFT) 28b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li#define FTM_SC_PS_MASK 0x7 29b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 30b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li#define FTM_CNT 0x04 31b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li#define FTM_MOD 0x08 32b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 33b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li#define FTM_CSC_BASE 0x0C 34b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li#define FTM_CSC_MSB BIT(5) 35b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li#define FTM_CSC_MSA BIT(4) 36b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li#define FTM_CSC_ELSB BIT(3) 37b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li#define FTM_CSC_ELSA BIT(2) 38b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li#define FTM_CSC(_channel) (FTM_CSC_BASE + ((_channel) * 8)) 39b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 40b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li#define FTM_CV_BASE 0x10 41b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li#define FTM_CV(_channel) (FTM_CV_BASE + ((_channel) * 8)) 42b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 43b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li#define FTM_CNTIN 0x4C 44b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li#define FTM_STATUS 0x50 45b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 46b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li#define FTM_MODE 0x54 47b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li#define FTM_MODE_FTMEN BIT(0) 48b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li#define FTM_MODE_INIT BIT(2) 49b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li#define FTM_MODE_PWMSYNC BIT(3) 50b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 51b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li#define FTM_SYNC 0x58 52b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li#define FTM_OUTINIT 0x5C 53b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li#define FTM_OUTMASK 0x60 54b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li#define FTM_COMBINE 0x64 55b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li#define FTM_DEADTIME 0x68 56b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li#define FTM_EXTTRIG 0x6C 57b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li#define FTM_POL 0x70 58b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li#define FTM_FMS 0x74 59b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li#define FTM_FILTER 0x78 60b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li#define FTM_FLTCTRL 0x7C 61b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li#define FTM_QDCTRL 0x80 62b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li#define FTM_CONF 0x84 63b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li#define FTM_FLTPOL 0x88 64b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li#define FTM_SYNCONF 0x8C 65b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li#define FTM_INVCTRL 0x90 66b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li#define FTM_SWOCTRL 0x94 67b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li#define FTM_PWMLOAD 0x98 68b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 69b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Lienum fsl_pwm_clk { 70b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li FSL_PWM_CLK_SYS, 71b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li FSL_PWM_CLK_FIX, 72b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li FSL_PWM_CLK_EXT, 73b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li FSL_PWM_CLK_CNTEN, 74b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li FSL_PWM_CLK_MAX 75b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li}; 76b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 77b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Listruct fsl_pwm_chip { 78b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li struct pwm_chip chip; 79b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 80b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li struct mutex lock; 81b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 82b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li unsigned int use_count; 83b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li unsigned int cnt_select; 84b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li unsigned int clk_ps; 85b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 8642fa98a9c3609c1aff466cb847e421c611cc9157Xiubo Li struct regmap *regmap; 87b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 88b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li int period_ns; 89b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 90b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li struct clk *clk[FSL_PWM_CLK_MAX]; 91b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li}; 92b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 93b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Listatic inline struct fsl_pwm_chip *to_fsl_chip(struct pwm_chip *chip) 94b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li{ 95b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li return container_of(chip, struct fsl_pwm_chip, chip); 96b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li} 97b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 98b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Listatic int fsl_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) 99b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li{ 100b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li struct fsl_pwm_chip *fpc = to_fsl_chip(chip); 101b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 102b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li return clk_prepare_enable(fpc->clk[FSL_PWM_CLK_SYS]); 103b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li} 104b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 105b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Listatic void fsl_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) 106b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li{ 107b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li struct fsl_pwm_chip *fpc = to_fsl_chip(chip); 108b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 109b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_SYS]); 110b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li} 111b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 112b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Listatic int fsl_pwm_calculate_default_ps(struct fsl_pwm_chip *fpc, 113b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li enum fsl_pwm_clk index) 114b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li{ 115b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li unsigned long sys_rate, cnt_rate; 116b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li unsigned long long ratio; 117b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 118b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li sys_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_SYS]); 119b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li if (!sys_rate) 120b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li return -EINVAL; 121b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 122b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li cnt_rate = clk_get_rate(fpc->clk[fpc->cnt_select]); 123b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li if (!cnt_rate) 124b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li return -EINVAL; 125b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 126b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li switch (index) { 127b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li case FSL_PWM_CLK_SYS: 128b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li fpc->clk_ps = 1; 129b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li break; 130b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li case FSL_PWM_CLK_FIX: 131b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li ratio = 2 * cnt_rate - 1; 132b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li do_div(ratio, sys_rate); 133b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li fpc->clk_ps = ratio; 134b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li break; 135b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li case FSL_PWM_CLK_EXT: 136b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li ratio = 4 * cnt_rate - 1; 137b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li do_div(ratio, sys_rate); 138b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li fpc->clk_ps = ratio; 139b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li break; 140b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li default: 141b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li return -EINVAL; 142b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li } 143b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 144b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li return 0; 145b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li} 146b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 147b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Listatic unsigned long fsl_pwm_calculate_cycles(struct fsl_pwm_chip *fpc, 148b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li unsigned long period_ns) 149b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li{ 150b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li unsigned long long c, c0; 151b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 152b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li c = clk_get_rate(fpc->clk[fpc->cnt_select]); 153b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li c = c * period_ns; 154b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li do_div(c, 1000000000UL); 155b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 156b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li do { 157b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li c0 = c; 158b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li do_div(c0, (1 << fpc->clk_ps)); 159b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li if (c0 <= 0xFFFF) 160b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li return (unsigned long)c0; 161b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li } while (++fpc->clk_ps < 8); 162b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 163b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li return 0; 164b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li} 165b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 166b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Listatic unsigned long fsl_pwm_calculate_period_cycles(struct fsl_pwm_chip *fpc, 167b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li unsigned long period_ns, 168b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li enum fsl_pwm_clk index) 169b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li{ 170b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li int ret; 171b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 172b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li ret = fsl_pwm_calculate_default_ps(fpc, index); 173b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li if (ret) { 174b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li dev_err(fpc->chip.dev, 175b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li "failed to calculate default prescaler: %d\n", 176b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li ret); 177b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li return 0; 178b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li } 179b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 180b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li return fsl_pwm_calculate_cycles(fpc, period_ns); 181b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li} 182b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 183b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Listatic unsigned long fsl_pwm_calculate_period(struct fsl_pwm_chip *fpc, 184b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li unsigned long period_ns) 185b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li{ 186b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li enum fsl_pwm_clk m0, m1; 187b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li unsigned long fix_rate, ext_rate, cycles; 188b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 189b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li cycles = fsl_pwm_calculate_period_cycles(fpc, period_ns, 190b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li FSL_PWM_CLK_SYS); 191b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li if (cycles) { 192b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li fpc->cnt_select = FSL_PWM_CLK_SYS; 193b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li return cycles; 194b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li } 195b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 196b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li fix_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_FIX]); 197b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li ext_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_EXT]); 198b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 199b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li if (fix_rate > ext_rate) { 200b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li m0 = FSL_PWM_CLK_FIX; 201b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li m1 = FSL_PWM_CLK_EXT; 202b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li } else { 203b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li m0 = FSL_PWM_CLK_EXT; 204b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li m1 = FSL_PWM_CLK_FIX; 205b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li } 206b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 207b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li cycles = fsl_pwm_calculate_period_cycles(fpc, period_ns, m0); 208b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li if (cycles) { 209b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li fpc->cnt_select = m0; 210b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li return cycles; 211b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li } 212b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 213b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li fpc->cnt_select = m1; 214b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 215b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li return fsl_pwm_calculate_period_cycles(fpc, period_ns, m1); 216b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li} 217b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 218b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Listatic unsigned long fsl_pwm_calculate_duty(struct fsl_pwm_chip *fpc, 219b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li unsigned long period_ns, 220b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li unsigned long duty_ns) 221b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li{ 22242fa98a9c3609c1aff466cb847e421c611cc9157Xiubo Li unsigned long long duty; 22342fa98a9c3609c1aff466cb847e421c611cc9157Xiubo Li u32 val; 224b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 22542fa98a9c3609c1aff466cb847e421c611cc9157Xiubo Li regmap_read(fpc->regmap, FTM_MOD, &val); 22642fa98a9c3609c1aff466cb847e421c611cc9157Xiubo Li duty = (unsigned long long)duty_ns * (val + 1); 227b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li do_div(duty, period_ns); 228b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 229b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li return (unsigned long)duty; 230b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li} 231b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 232b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Listatic int fsl_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, 233b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li int duty_ns, int period_ns) 234b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li{ 235b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li struct fsl_pwm_chip *fpc = to_fsl_chip(chip); 23642fa98a9c3609c1aff466cb847e421c611cc9157Xiubo Li u32 period, duty; 237b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 238b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li mutex_lock(&fpc->lock); 239b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 240b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li /* 241b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li * The Freescale FTM controller supports only a single period for 242b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li * all PWM channels, therefore incompatible changes need to be 243b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li * refused. 244b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li */ 245b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li if (fpc->period_ns && fpc->period_ns != period_ns) { 246b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li dev_err(fpc->chip.dev, 247b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li "conflicting period requested for PWM %u\n", 248b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li pwm->hwpwm); 249b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li mutex_unlock(&fpc->lock); 250b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li return -EBUSY; 251b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li } 252b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 253b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li if (!fpc->period_ns && duty_ns) { 254b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li period = fsl_pwm_calculate_period(fpc, period_ns); 255b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li if (!period) { 256b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li dev_err(fpc->chip.dev, "failed to calculate period\n"); 257b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li mutex_unlock(&fpc->lock); 258b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li return -EINVAL; 259b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li } 260b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 26142fa98a9c3609c1aff466cb847e421c611cc9157Xiubo Li regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_PS_MASK, 26242fa98a9c3609c1aff466cb847e421c611cc9157Xiubo Li fpc->clk_ps); 26342fa98a9c3609c1aff466cb847e421c611cc9157Xiubo Li regmap_write(fpc->regmap, FTM_MOD, period - 1); 264b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 265b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li fpc->period_ns = period_ns; 266b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li } 267b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 268b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li mutex_unlock(&fpc->lock); 269b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 270b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li duty = fsl_pwm_calculate_duty(fpc, period_ns, duty_ns); 271b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 27242fa98a9c3609c1aff466cb847e421c611cc9157Xiubo Li regmap_write(fpc->regmap, FTM_CSC(pwm->hwpwm), 27342fa98a9c3609c1aff466cb847e421c611cc9157Xiubo Li FTM_CSC_MSB | FTM_CSC_ELSB); 27442fa98a9c3609c1aff466cb847e421c611cc9157Xiubo Li regmap_write(fpc->regmap, FTM_CV(pwm->hwpwm), duty); 275b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 276b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li return 0; 277b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li} 278b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 279b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Listatic int fsl_pwm_set_polarity(struct pwm_chip *chip, 280b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li struct pwm_device *pwm, 281b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li enum pwm_polarity polarity) 282b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li{ 283b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li struct fsl_pwm_chip *fpc = to_fsl_chip(chip); 284b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li u32 val; 285b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 28642fa98a9c3609c1aff466cb847e421c611cc9157Xiubo Li regmap_read(fpc->regmap, FTM_POL, &val); 287b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 288b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li if (polarity == PWM_POLARITY_INVERSED) 289b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li val |= BIT(pwm->hwpwm); 290b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li else 291b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li val &= ~BIT(pwm->hwpwm); 292b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 29342fa98a9c3609c1aff466cb847e421c611cc9157Xiubo Li regmap_write(fpc->regmap, FTM_POL, val); 294b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 295b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li return 0; 296b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li} 297b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 298b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Listatic int fsl_counter_clock_enable(struct fsl_pwm_chip *fpc) 299b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li{ 300b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li int ret; 301b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 302b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li if (fpc->use_count != 0) 303b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li return 0; 304b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 305b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li /* select counter clock source */ 30642fa98a9c3609c1aff466cb847e421c611cc9157Xiubo Li regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_CLK_MASK, 30742fa98a9c3609c1aff466cb847e421c611cc9157Xiubo Li FTM_SC_CLK(fpc->cnt_select)); 308b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 309b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li ret = clk_prepare_enable(fpc->clk[fpc->cnt_select]); 310b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li if (ret) 311b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li return ret; 312b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 313b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li ret = clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]); 314b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li if (ret) { 315b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li clk_disable_unprepare(fpc->clk[fpc->cnt_select]); 316b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li return ret; 317b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li } 318b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 319b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li fpc->use_count++; 320b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 321b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li return 0; 322b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li} 323b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 324b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Listatic int fsl_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) 325b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li{ 326b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li struct fsl_pwm_chip *fpc = to_fsl_chip(chip); 327b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li int ret; 328b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 329b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li mutex_lock(&fpc->lock); 33042fa98a9c3609c1aff466cb847e421c611cc9157Xiubo Li regmap_update_bits(fpc->regmap, FTM_OUTMASK, BIT(pwm->hwpwm), 0); 331b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 332b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li ret = fsl_counter_clock_enable(fpc); 333b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li mutex_unlock(&fpc->lock); 334b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 335b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li return ret; 336b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li} 337b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 338b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Listatic void fsl_counter_clock_disable(struct fsl_pwm_chip *fpc) 339b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li{ 340b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li /* 341b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li * already disabled, do nothing 342b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li */ 343b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li if (fpc->use_count == 0) 344b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li return; 345b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 346b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li /* there are still users, so can't disable yet */ 347b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li if (--fpc->use_count > 0) 348b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li return; 349b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 350b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li /* no users left, disable PWM counter clock */ 35142fa98a9c3609c1aff466cb847e421c611cc9157Xiubo Li regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_CLK_MASK, 0); 352b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 353b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]); 354b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li clk_disable_unprepare(fpc->clk[fpc->cnt_select]); 355b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li} 356b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 357b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Listatic void fsl_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) 358b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li{ 359b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li struct fsl_pwm_chip *fpc = to_fsl_chip(chip); 360b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li u32 val; 361b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 362b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li mutex_lock(&fpc->lock); 36342fa98a9c3609c1aff466cb847e421c611cc9157Xiubo Li regmap_update_bits(fpc->regmap, FTM_OUTMASK, BIT(pwm->hwpwm), 36442fa98a9c3609c1aff466cb847e421c611cc9157Xiubo Li BIT(pwm->hwpwm)); 365b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 366b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li fsl_counter_clock_disable(fpc); 367b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 36842fa98a9c3609c1aff466cb847e421c611cc9157Xiubo Li regmap_read(fpc->regmap, FTM_OUTMASK, &val); 369b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li if ((val & 0xFF) == 0xFF) 370b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li fpc->period_ns = 0; 371b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 372b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li mutex_unlock(&fpc->lock); 373b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li} 374b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 375b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Listatic const struct pwm_ops fsl_pwm_ops = { 376b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li .request = fsl_pwm_request, 377b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li .free = fsl_pwm_free, 378b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li .config = fsl_pwm_config, 379b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li .set_polarity = fsl_pwm_set_polarity, 380b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li .enable = fsl_pwm_enable, 381b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li .disable = fsl_pwm_disable, 382b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li .owner = THIS_MODULE, 383b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li}; 384b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 385b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Listatic int fsl_pwm_init(struct fsl_pwm_chip *fpc) 386b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li{ 387b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li int ret; 388b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 389b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li ret = clk_prepare_enable(fpc->clk[FSL_PWM_CLK_SYS]); 390b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li if (ret) 391b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li return ret; 392b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 39342fa98a9c3609c1aff466cb847e421c611cc9157Xiubo Li regmap_write(fpc->regmap, FTM_CNTIN, 0x00); 39442fa98a9c3609c1aff466cb847e421c611cc9157Xiubo Li regmap_write(fpc->regmap, FTM_OUTINIT, 0x00); 39542fa98a9c3609c1aff466cb847e421c611cc9157Xiubo Li regmap_write(fpc->regmap, FTM_OUTMASK, 0xFF); 396b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 397b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_SYS]); 398b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 399b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li return 0; 400b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li} 401b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 40242fa98a9c3609c1aff466cb847e421c611cc9157Xiubo Listatic const struct regmap_config fsl_pwm_regmap_config = { 40342fa98a9c3609c1aff466cb847e421c611cc9157Xiubo Li .reg_bits = 32, 40442fa98a9c3609c1aff466cb847e421c611cc9157Xiubo Li .reg_stride = 4, 40542fa98a9c3609c1aff466cb847e421c611cc9157Xiubo Li .val_bits = 32, 40642fa98a9c3609c1aff466cb847e421c611cc9157Xiubo Li 40742fa98a9c3609c1aff466cb847e421c611cc9157Xiubo Li .max_register = FTM_PWMLOAD, 40842fa98a9c3609c1aff466cb847e421c611cc9157Xiubo Li}; 40942fa98a9c3609c1aff466cb847e421c611cc9157Xiubo Li 410b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Listatic int fsl_pwm_probe(struct platform_device *pdev) 411b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li{ 412b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li struct fsl_pwm_chip *fpc; 413b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li struct resource *res; 41442fa98a9c3609c1aff466cb847e421c611cc9157Xiubo Li void __iomem *base; 415b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li int ret; 416b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 417b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li fpc = devm_kzalloc(&pdev->dev, sizeof(*fpc), GFP_KERNEL); 418b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li if (!fpc) 419b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li return -ENOMEM; 420b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 421b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li mutex_init(&fpc->lock); 422b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 423b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li fpc->chip.dev = &pdev->dev; 424b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 425b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 42642fa98a9c3609c1aff466cb847e421c611cc9157Xiubo Li base = devm_ioremap_resource(&pdev->dev, res); 42742fa98a9c3609c1aff466cb847e421c611cc9157Xiubo Li if (IS_ERR(base)) 42842fa98a9c3609c1aff466cb847e421c611cc9157Xiubo Li return PTR_ERR(base); 42942fa98a9c3609c1aff466cb847e421c611cc9157Xiubo Li 43042fa98a9c3609c1aff466cb847e421c611cc9157Xiubo Li fpc->regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL, base, 43142fa98a9c3609c1aff466cb847e421c611cc9157Xiubo Li &fsl_pwm_regmap_config); 43242fa98a9c3609c1aff466cb847e421c611cc9157Xiubo Li if (IS_ERR(fpc->regmap)) { 43342fa98a9c3609c1aff466cb847e421c611cc9157Xiubo Li dev_err(&pdev->dev, "regmap init failed\n"); 43442fa98a9c3609c1aff466cb847e421c611cc9157Xiubo Li return PTR_ERR(fpc->regmap); 43542fa98a9c3609c1aff466cb847e421c611cc9157Xiubo Li } 436b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 437b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li fpc->clk[FSL_PWM_CLK_SYS] = devm_clk_get(&pdev->dev, "ftm_sys"); 438b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li if (IS_ERR(fpc->clk[FSL_PWM_CLK_SYS])) { 439b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li dev_err(&pdev->dev, "failed to get \"ftm_sys\" clock\n"); 440b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li return PTR_ERR(fpc->clk[FSL_PWM_CLK_SYS]); 441b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li } 442b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 443b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li fpc->clk[FSL_PWM_CLK_FIX] = devm_clk_get(fpc->chip.dev, "ftm_fix"); 444b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li if (IS_ERR(fpc->clk[FSL_PWM_CLK_FIX])) 445b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li return PTR_ERR(fpc->clk[FSL_PWM_CLK_FIX]); 446b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 447b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li fpc->clk[FSL_PWM_CLK_EXT] = devm_clk_get(fpc->chip.dev, "ftm_ext"); 448b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li if (IS_ERR(fpc->clk[FSL_PWM_CLK_EXT])) 449b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li return PTR_ERR(fpc->clk[FSL_PWM_CLK_EXT]); 450b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 451b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li fpc->clk[FSL_PWM_CLK_CNTEN] = 452b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li devm_clk_get(fpc->chip.dev, "ftm_cnt_clk_en"); 453b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li if (IS_ERR(fpc->clk[FSL_PWM_CLK_CNTEN])) 454b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li return PTR_ERR(fpc->clk[FSL_PWM_CLK_CNTEN]); 455b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 456b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li fpc->chip.ops = &fsl_pwm_ops; 457b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li fpc->chip.of_xlate = of_pwm_xlate_with_flags; 458b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li fpc->chip.of_pwm_n_cells = 3; 459b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li fpc->chip.base = -1; 460b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li fpc->chip.npwm = 8; 46139fd3f99aba3f7683fc9b62e916e4c886a1cb6b0Axel Lin fpc->chip.can_sleep = true; 462b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 463b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li ret = pwmchip_add(&fpc->chip); 464b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li if (ret < 0) { 465b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret); 466b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li return ret; 467b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li } 468b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 469b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li platform_set_drvdata(pdev, fpc); 470b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 471b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li return fsl_pwm_init(fpc); 472b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li} 473b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 474b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Listatic int fsl_pwm_remove(struct platform_device *pdev) 475b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li{ 476b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li struct fsl_pwm_chip *fpc = platform_get_drvdata(pdev); 477b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 478b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li return pwmchip_remove(&fpc->chip); 479b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li} 480b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 481b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Listatic const struct of_device_id fsl_pwm_dt_ids[] = { 482b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li { .compatible = "fsl,vf610-ftm-pwm", }, 483b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li { /* sentinel */ } 484b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li}; 485b505183b5117ce149c65ae62f8c00e889acafa69Xiubo LiMODULE_DEVICE_TABLE(of, fsl_pwm_dt_ids); 486b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 487b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Listatic struct platform_driver fsl_pwm_driver = { 488b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li .driver = { 489b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li .name = "fsl-ftm-pwm", 490b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li .of_match_table = fsl_pwm_dt_ids, 491b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li }, 492b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li .probe = fsl_pwm_probe, 493b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li .remove = fsl_pwm_remove, 494b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li}; 495b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Limodule_platform_driver(fsl_pwm_driver); 496b505183b5117ce149c65ae62f8c00e889acafa69Xiubo Li 497b505183b5117ce149c65ae62f8c00e889acafa69Xiubo LiMODULE_DESCRIPTION("Freescale FlexTimer Module PWM Driver"); 498b505183b5117ce149c65ae62f8c00e889acafa69Xiubo LiMODULE_AUTHOR("Xiubo Li <Li.Xiubo@freescale.com>"); 499b505183b5117ce149c65ae62f8c00e889acafa69Xiubo LiMODULE_ALIAS("platform:fsl-ftm-pwm"); 500b505183b5117ce149c65ae62f8c00e889acafa69Xiubo LiMODULE_LICENSE("GPL"); 501