11237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu/*
21237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu * Aic94xx SAS/SATA driver hardware interface header file.
31237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu *
41237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu * Copyright (C) 2005 Adaptec, Inc.  All rights reserved.
51237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu * Copyright (C) 2005 Gilbert Wu <gilbert_wu@adaptec.com>
61237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu *
71237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu * This file is licensed under GPLv2.
81237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu *
91237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu * This file is part of the aic94xx driver.
101237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu *
111237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu * The aic94xx driver is free software; you can redistribute it and/or
121237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu * modify it under the terms of the GNU General Public License as
131237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu * published by the Free Software Foundation; version 2 of the
141237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu * License.
151237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu *
161237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu * The aic94xx driver is distributed in the hope that it will be useful,
171237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu * but WITHOUT ANY WARRANTY; without even the implied warranty of
181237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
191237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu * General Public License for more details.
201237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu *
211237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu * You should have received a copy of the GNU General Public License
221237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu * along with the aic94xx driver; if not, write to the Free Software
231237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
241237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu *
251237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu */
261237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu#ifndef _AIC94XX_SDS_H_
271237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu#define _AIC94XX_SDS_H_
281237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu
291237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wuenum {
301237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu	FLASH_METHOD_UNKNOWN,
311237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu	FLASH_METHOD_A,
321237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu	FLASH_METHOD_B
331237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu};
341237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu
351237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu#define FLASH_MANUF_ID_AMD              0x01
361237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu#define FLASH_MANUF_ID_ST               0x20
371237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu#define FLASH_MANUF_ID_FUJITSU          0x04
381237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu#define FLASH_MANUF_ID_MACRONIX         0xC2
391237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu#define FLASH_MANUF_ID_INTEL            0x89
401237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu#define FLASH_MANUF_ID_UNKNOWN          0xFF
411237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu
421237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu#define FLASH_DEV_ID_AM29LV008BT        0x3E
431237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu#define FLASH_DEV_ID_AM29LV800DT        0xDA
441237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu#define FLASH_DEV_ID_STM29W800DT        0xD7
451237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu#define FLASH_DEV_ID_STM29LV640         0xDE
461237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu#define FLASH_DEV_ID_STM29008           0xEA
471237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu#define FLASH_DEV_ID_MBM29LV800TE       0xDA
481237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu#define FLASH_DEV_ID_MBM29DL800TA       0x4A
491237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu#define FLASH_DEV_ID_MBM29LV008TA       0x3E
501237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu#define FLASH_DEV_ID_AM29LV640MT        0x7E
511237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu#define FLASH_DEV_ID_AM29F800B          0xD6
521237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu#define FLASH_DEV_ID_MX29LV800BT        0xDA
531237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu#define FLASH_DEV_ID_MX29LV008CT        0xDA
541237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu#define FLASH_DEV_ID_I28LV00TAT         0x3E
551237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu#define FLASH_DEV_ID_UNKNOWN            0xFF
561237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu
571237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu/* status bit mask values */
581237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu#define FLASH_STATUS_BIT_MASK_DQ6       0x40
591237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu#define FLASH_STATUS_BIT_MASK_DQ5       0x20
601237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu#define FLASH_STATUS_BIT_MASK_DQ2       0x04
611237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu
621237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu/* minimum value in micro seconds needed for checking status */
631237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu#define FLASH_STATUS_ERASE_DELAY_COUNT  50
641237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu#define FLASH_STATUS_WRITE_DELAY_COUNT  25
651237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu
661237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu#define FLASH_SECTOR_SIZE               0x010000
671237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu#define FLASH_SECTOR_SIZE_MASK          0xffff0000
681237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu
691237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu#define FLASH_OK                        0x000000
701237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu#define FAIL_OPEN_BIOS_FILE             0x000100
711237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu#define FAIL_CHECK_PCI_ID               0x000200
721237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu#define FAIL_CHECK_SUM                  0x000300
731237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu#define FAIL_UNKNOWN                    0x000400
741237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu#define FAIL_VERIFY                     0x000500
751237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu#define FAIL_RESET_FLASH                0x000600
761237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu#define FAIL_FIND_FLASH_ID              0x000700
771237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu#define FAIL_ERASE_FLASH                0x000800
781237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu#define FAIL_WRITE_FLASH                0x000900
791237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu#define FAIL_FILE_SIZE                  0x000a00
801237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu#define FAIL_PARAMETERS                 0x000b00
811237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu#define FAIL_OUT_MEMORY                 0x000c00
821237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu#define FLASH_IN_PROGRESS               0x001000
831237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu
841237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wustruct controller_id {
851237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu	u32 vendor;     /* PCI Vendor ID */
861237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu	u32 device;     /* PCI Device ID */
871237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu	u32 sub_vendor; /* PCI Subvendor ID */
881237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu	u32 sub_device; /* PCI Subdevice ID */
891237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu};
901237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu
911237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wustruct image_info {
921237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu	u32 ImageId;       /* Identifies the image */
931237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu	u32 ImageOffset;   /* Offset the beginning of the file */
941237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu	u32 ImageLength;   /* length of the image */
951237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu	u32 ImageChecksum; /* Image checksum */
961237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu	u32 ImageVersion;  /* Version of the image, could be build number */
971237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu};
981237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu
991237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wustruct bios_file_header {
1001237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu	u8 signature[32]; /* Signature/Cookie to identify the file */
1011237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu	u32 checksum;	  /*Entire file checksum with this field zero */
1021237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu	u32 antidote;	  /* Entire file checksum with this field 0xFFFFFFFF */
1031237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu	struct controller_id contrl_id; /*PCI id to identify the controller */
1041237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu	u32 filelen;      /*Length of the entire file*/
1051237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu	u32 chunk_num;	  /*The chunk/part number for multiple Image files */
1061237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu	u32 total_chunks; /*Total number of chunks/parts in the image file */
1071237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu	u32 num_images;   /* Number of images in the file */
1081237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu	u32 build_num;    /* Build number of this image */
1091237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu	struct image_info image_header;
1101237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu};
1111237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu
1121237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wuint asd_verify_flash_seg(struct asd_ha_struct *asd_ha,
1130bc202e0fd84b8c8d042bdf9f0995e1e47bdbf59David Woodhouse		const void *src, u32 dest_offset, u32 bytes_to_verify);
1141237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wuint asd_write_flash_seg(struct asd_ha_struct *asd_ha,
1150bc202e0fd84b8c8d042bdf9f0995e1e47bdbf59David Woodhouse		const void *src, u32 dest_offset, u32 bytes_to_write);
1161237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wuint asd_chk_write_status(struct asd_ha_struct *asd_ha,
1171237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu		u32 sector_addr, u8 erase_flag);
1181237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wuint asd_check_flash_type(struct asd_ha_struct *asd_ha);
1191237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wuint asd_erase_nv_sector(struct asd_ha_struct *asd_ha,
1201237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu		u32 flash_addr, u32 size);
1211237c98db2aa94b42dbb9fb1df062b7d3733dc83Gilbert Wu#endif
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