14a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan/* 24a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * This file is part of the Chelsio FCoE driver for Linux. 34a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * 44a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * Copyright (c) 2008-2013 Chelsio Communications, Inc. All rights reserved. 54a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * 64a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * This software is available to you under a choice of one of two 74a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * licenses. You may choose to be licensed under the terms of the GNU 84a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * General Public License (GPL) Version 2, available from the file 94a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * OpenIB.org BSD license below: 104a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * 114a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * Redistribution and use in source and binary forms, with or 124a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * without modification, are permitted provided that the following 134a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * conditions are met: 144a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * 154a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * - Redistributions of source code must retain the above 164a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * copyright notice, this list of conditions and the following 174a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * disclaimer. 184a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * 194a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * - Redistributions in binary form must reproduce the above 204a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * copyright notice, this list of conditions and the following 214a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * disclaimer in the documentation and/or other materials 224a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * provided with the distribution. 234a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * 244a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 254a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 264a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 274a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 284a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 294a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 304a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 314a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * SOFTWARE. 324a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan */ 334a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan 344a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan#include "csio_hw.h" 354a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan#include "csio_init.h" 364a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan 374a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushanstatic int 384a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushancsio_t5_set_mem_win(struct csio_hw *hw, uint32_t win) 394a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan{ 404a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan u32 mem_win_base; 414a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan /* 424a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * Truncation intentional: we only read the bottom 32-bits of the 434a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * 64-bit BAR0/BAR1 ... We use the hardware backdoor mechanism to 444a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * read BAR0 instead of using pci_resource_start() because we could be 454a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * operating from within a Virtual Machine which is trapping our 464a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * accesses to our Configuration Space and we need to set up the PCI-E 474a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * Memory Window decoders with the actual addresses which will be 484a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * coming across the PCI-E link. 494a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan */ 504a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan 514a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan /* For T5, only relative offset inside the PCIe BAR is passed */ 524a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan mem_win_base = MEMWIN_BASE; 534a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan 544a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan /* 554a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * Set up memory window for accessing adapter memory ranges. (Read 564a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * back MA register to ensure that changes propagate before we attempt 574a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * to use the new values.) 584a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan */ 594a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan csio_wr_reg32(hw, mem_win_base | BIR(0) | 604a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan WINDOW(ilog2(MEMWIN_APERTURE) - 10), 614a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, win)); 624a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan csio_rd_reg32(hw, 634a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, win)); 644a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan 654a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan return 0; 664a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan} 674a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan 684a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan/* 694a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * Interrupt handler for the PCIE module. 704a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan */ 714a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushanstatic void 724a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushancsio_t5_pcie_intr_handler(struct csio_hw *hw) 734a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan{ 744a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan static struct intr_info sysbus_intr_info[] = { 754a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan { RNPP, "RXNP array parity error", -1, 1 }, 764a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan { RPCP, "RXPC array parity error", -1, 1 }, 774a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan { RCIP, "RXCIF array parity error", -1, 1 }, 784a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan { RCCP, "Rx completions control array parity error", -1, 1 }, 794a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan { RFTP, "RXFT array parity error", -1, 1 }, 804a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan { 0, NULL, 0, 0 } 814a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan }; 824a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan static struct intr_info pcie_port_intr_info[] = { 834a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan { TPCP, "TXPC array parity error", -1, 1 }, 844a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan { TNPP, "TXNP array parity error", -1, 1 }, 854a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan { TFTP, "TXFT array parity error", -1, 1 }, 864a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan { TCAP, "TXCA array parity error", -1, 1 }, 874a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan { TCIP, "TXCIF array parity error", -1, 1 }, 884a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan { RCAP, "RXCA array parity error", -1, 1 }, 894a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan { OTDD, "outbound request TLP discarded", -1, 1 }, 904a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan { RDPE, "Rx data parity error", -1, 1 }, 914a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan { TDUE, "Tx uncorrectable data error", -1, 1 }, 924a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan { 0, NULL, 0, 0 } 934a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan }; 944a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan 954a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan static struct intr_info pcie_intr_info[] = { 964a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan { MSTGRPPERR, "Master Response Read Queue parity error", 974a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan -1, 1 }, 984a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan { MSTTIMEOUTPERR, "Master Timeout FIFO parity error", -1, 1 }, 994a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan { MSIXSTIPERR, "MSI-X STI SRAM parity error", -1, 1 }, 1004a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan { MSIXADDRLPERR, "MSI-X AddrL parity error", -1, 1 }, 1014a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan { MSIXADDRHPERR, "MSI-X AddrH parity error", -1, 1 }, 1024a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan { MSIXDATAPERR, "MSI-X data parity error", -1, 1 }, 1034a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan { MSIXDIPERR, "MSI-X DI parity error", -1, 1 }, 1044a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan { PIOCPLGRPPERR, "PCI PIO completion Group FIFO parity error", 1054a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan -1, 1 }, 1064a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan { PIOREQGRPPERR, "PCI PIO request Group FIFO parity error", 1074a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan -1, 1 }, 1084a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan { TARTAGPERR, "PCI PCI target tag FIFO parity error", -1, 1 }, 1094a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan { MSTTAGQPERR, "PCI master tag queue parity error", -1, 1 }, 1104a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan { CREQPERR, "PCI CMD channel request parity error", -1, 1 }, 1114a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan { CRSPPERR, "PCI CMD channel response parity error", -1, 1 }, 1124a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan { DREQWRPERR, "PCI DMA channel write request parity error", 1134a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan -1, 1 }, 1144a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan { DREQPERR, "PCI DMA channel request parity error", -1, 1 }, 1154a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan { DRSPPERR, "PCI DMA channel response parity error", -1, 1 }, 1164a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan { HREQWRPERR, "PCI HMA channel count parity error", -1, 1 }, 1174a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan { HREQPERR, "PCI HMA channel request parity error", -1, 1 }, 1184a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan { HRSPPERR, "PCI HMA channel response parity error", -1, 1 }, 1194a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan { CFGSNPPERR, "PCI config snoop FIFO parity error", -1, 1 }, 1204a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan { FIDPERR, "PCI FID parity error", -1, 1 }, 1214a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan { VFIDPERR, "PCI INTx clear parity error", -1, 1 }, 1224a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan { MAGRPPERR, "PCI MA group FIFO parity error", -1, 1 }, 1234a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan { PIOTAGPERR, "PCI PIO tag parity error", -1, 1 }, 1244a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan { IPRXHDRGRPPERR, "PCI IP Rx header group parity error", 1254a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan -1, 1 }, 1264a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan { IPRXDATAGRPPERR, "PCI IP Rx data group parity error", 1274a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan -1, 1 }, 1284a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan { RPLPERR, "PCI IP replay buffer parity error", -1, 1 }, 1294a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan { IPSOTPERR, "PCI IP SOT buffer parity error", -1, 1 }, 1304a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan { TRGT1GRPPERR, "PCI TRGT1 group FIFOs parity error", -1, 1 }, 1314a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan { READRSPERR, "Outbound read error", -1, 0 }, 1324a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan { 0, NULL, 0, 0 } 1334a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan }; 1344a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan 1354a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan int fat; 1364a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan fat = csio_handle_intr_status(hw, 1374a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS, 1384a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan sysbus_intr_info) + 1394a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan csio_handle_intr_status(hw, 1404a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS, 1414a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan pcie_port_intr_info) + 1424a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan csio_handle_intr_status(hw, PCIE_INT_CAUSE, pcie_intr_info); 1434a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan if (fat) 1444a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan csio_hw_fatal_err(hw); 1454a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan} 1464a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan 1474a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan/* 1484a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * csio_t5_flash_cfg_addr - return the address of the flash configuration file 1494a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * @hw: the HW module 1504a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * 1514a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * Return the address within the flash where the Firmware Configuration 1524a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * File is stored. 1534a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan */ 1544a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushanstatic unsigned int 1554a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushancsio_t5_flash_cfg_addr(struct csio_hw *hw) 1564a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan{ 1574a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan return FLASH_CFG_START; 1584a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan} 1594a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan 1604a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan/* 1614a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * csio_t5_mc_read - read from MC through backdoor accesses 1624a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * @hw: the hw module 1634a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * @idx: index to the register 1644a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * @addr: address of first byte requested 1654a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * @data: 64 bytes of data containing the requested address 1664a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * @ecc: where to store the corresponding 64-bit ECC word 1674a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * 1684a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * Read 64 bytes of data from MC starting at a 64-byte-aligned address 1694a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * that covers the requested address @addr. If @parity is not %NULL it 1704a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * is assigned the 64-bit ECC word for the read data. 1714a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan */ 1724a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushanstatic int 1734a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushancsio_t5_mc_read(struct csio_hw *hw, int idx, uint32_t addr, __be32 *data, 1744a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan uint64_t *ecc) 1754a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan{ 1764a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan int i; 1774a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan uint32_t mc_bist_cmd_reg, mc_bist_cmd_addr_reg, mc_bist_cmd_len_reg; 1784a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan uint32_t mc_bist_status_rdata_reg, mc_bist_data_pattern_reg; 1794a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan 1804a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan mc_bist_cmd_reg = MC_REG(MC_P_BIST_CMD, idx); 1814a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan mc_bist_cmd_addr_reg = MC_REG(MC_P_BIST_CMD_ADDR, idx); 1824a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan mc_bist_cmd_len_reg = MC_REG(MC_P_BIST_CMD_LEN, idx); 1834a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan mc_bist_status_rdata_reg = MC_REG(MC_P_BIST_STATUS_RDATA, idx); 1844a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan mc_bist_data_pattern_reg = MC_REG(MC_P_BIST_DATA_PATTERN, idx); 1854a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan 1864a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan if (csio_rd_reg32(hw, mc_bist_cmd_reg) & START_BIST) 1874a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan return -EBUSY; 1884a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan csio_wr_reg32(hw, addr & ~0x3fU, mc_bist_cmd_addr_reg); 1894a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan csio_wr_reg32(hw, 64, mc_bist_cmd_len_reg); 1904a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan csio_wr_reg32(hw, 0xc, mc_bist_data_pattern_reg); 1914a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan csio_wr_reg32(hw, BIST_OPCODE(1) | START_BIST | BIST_CMD_GAP(1), 1924a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan mc_bist_cmd_reg); 1934a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan i = csio_hw_wait_op_done_val(hw, mc_bist_cmd_reg, START_BIST, 1944a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan 0, 10, 1, NULL); 1954a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan if (i) 1964a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan return i; 1974a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan 1984a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan#define MC_DATA(i) MC_BIST_STATUS_REG(MC_BIST_STATUS_RDATA, i) 1994a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan 2004a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan for (i = 15; i >= 0; i--) 2014a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan *data++ = htonl(csio_rd_reg32(hw, MC_DATA(i))); 2024a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan if (ecc) 2034a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan *ecc = csio_rd_reg64(hw, MC_DATA(16)); 2044a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan#undef MC_DATA 2054a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan return 0; 2064a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan} 2074a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan 2084a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan/* 2094a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * csio_t5_edc_read - read from EDC through backdoor accesses 2104a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * @hw: the hw module 2114a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * @idx: which EDC to access 2124a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * @addr: address of first byte requested 2134a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * @data: 64 bytes of data containing the requested address 2144a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * @ecc: where to store the corresponding 64-bit ECC word 2154a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * 2164a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * Read 64 bytes of data from EDC starting at a 64-byte-aligned address 2174a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * that covers the requested address @addr. If @parity is not %NULL it 2184a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * is assigned the 64-bit ECC word for the read data. 2194a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan */ 2204a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushanstatic int 2214a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushancsio_t5_edc_read(struct csio_hw *hw, int idx, uint32_t addr, __be32 *data, 2224a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan uint64_t *ecc) 2234a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan{ 2244a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan int i; 2254a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan uint32_t edc_bist_cmd_reg, edc_bist_cmd_addr_reg, edc_bist_cmd_len_reg; 2264a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan uint32_t edc_bist_cmd_data_pattern, edc_bist_status_rdata_reg; 2274a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan 2284a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan/* 2294a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * These macro are missing in t4_regs.h file. 2304a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan */ 2314a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan#define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR) 2324a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan#define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx) 2334a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan 2344a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan edc_bist_cmd_reg = EDC_REG_T5(EDC_H_BIST_CMD, idx); 2354a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan edc_bist_cmd_addr_reg = EDC_REG_T5(EDC_H_BIST_CMD_ADDR, idx); 2364a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan edc_bist_cmd_len_reg = EDC_REG_T5(EDC_H_BIST_CMD_LEN, idx); 2374a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan edc_bist_cmd_data_pattern = EDC_REG_T5(EDC_H_BIST_DATA_PATTERN, idx); 2384a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan edc_bist_status_rdata_reg = EDC_REG_T5(EDC_H_BIST_STATUS_RDATA, idx); 2394a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan#undef EDC_REG_T5 2404a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan#undef EDC_STRIDE_T5 2414a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan 2424a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan if (csio_rd_reg32(hw, edc_bist_cmd_reg) & START_BIST) 2434a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan return -EBUSY; 2444a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan csio_wr_reg32(hw, addr & ~0x3fU, edc_bist_cmd_addr_reg); 2454a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan csio_wr_reg32(hw, 64, edc_bist_cmd_len_reg); 2464a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan csio_wr_reg32(hw, 0xc, edc_bist_cmd_data_pattern); 2474a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan csio_wr_reg32(hw, BIST_OPCODE(1) | START_BIST | BIST_CMD_GAP(1), 2484a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan edc_bist_cmd_reg); 2494a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan i = csio_hw_wait_op_done_val(hw, edc_bist_cmd_reg, START_BIST, 2504a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan 0, 10, 1, NULL); 2514a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan if (i) 2524a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan return i; 2534a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan 2544a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan#define EDC_DATA(i) (EDC_BIST_STATUS_REG(EDC_BIST_STATUS_RDATA, i) + idx) 2554a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan 2564a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan for (i = 15; i >= 0; i--) 2574a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan *data++ = htonl(csio_rd_reg32(hw, EDC_DATA(i))); 2584a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan if (ecc) 2594a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan *ecc = csio_rd_reg64(hw, EDC_DATA(16)); 2604a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan#undef EDC_DATA 2614a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan return 0; 2624a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan} 2634a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan 2644a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan/* 2654a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * csio_t5_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window 2664a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * @hw: the csio_hw 2674a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * @win: PCI-E memory Window to use 2684a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * @mtype: memory type: MEM_EDC0, MEM_EDC1, MEM_MC0 (or MEM_MC) or MEM_MC1 2694a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * @addr: address within indicated memory type 2704a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * @len: amount of memory to transfer 2714a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * @buf: host memory buffer 2724a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * @dir: direction of transfer 1 => read, 0 => write 2734a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * 2744a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * Reads/writes an [almost] arbitrary memory region in the firmware: the 2754a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * firmware memory address, length and host buffer must be aligned on 2764a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * 32-bit boudaries. The memory is transferred as a raw byte sequence 2774a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * from/to the firmware's memory. If this memory contains data 2784a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * structures which contain multi-byte integers, it's the callers 2794a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * responsibility to perform appropriate byte order conversions. 2804a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan */ 2814a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushanstatic int 2824a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushancsio_t5_memory_rw(struct csio_hw *hw, u32 win, int mtype, u32 addr, 2834a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan u32 len, uint32_t *buf, int dir) 2844a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan{ 2854a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan u32 pos, start, offset, memoffset; 2864a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan u32 edc_size, mc_size, win_pf, mem_reg, mem_aperture, mem_base; 2874a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan 2884a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan /* 2894a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * Argument sanity checks ... 2904a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan */ 2914a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan if ((addr & 0x3) || (len & 0x3)) 2924a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan return -EINVAL; 2934a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan 2944a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan /* Offset into the region of memory which is being accessed 2954a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * MEM_EDC0 = 0 2964a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * MEM_EDC1 = 1 2974a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * MEM_MC = 2 -- T4 2984a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * MEM_MC0 = 2 -- For T5 2994a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * MEM_MC1 = 3 -- For T5 3004a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan */ 3014a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan edc_size = EDRAM_SIZE_GET(csio_rd_reg32(hw, MA_EDRAM0_BAR)); 3024a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan if (mtype != MEM_MC1) 3034a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan memoffset = (mtype * (edc_size * 1024 * 1024)); 3044a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan else { 3054a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan mc_size = EXT_MEM_SIZE_GET(csio_rd_reg32(hw, 3064a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan MA_EXT_MEMORY_BAR)); 3074a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan memoffset = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024; 3084a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan } 3094a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan 3104a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan /* Determine the PCIE_MEM_ACCESS_OFFSET */ 3114a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan addr = addr + memoffset; 3124a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan 3134a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan /* 3144a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * Each PCI-E Memory Window is programmed with a window size -- or 3154a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * "aperture" -- which controls the granularity of its mapping onto 3164a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * adapter memory. We need to grab that aperture in order to know 3174a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * how to use the specified window. The window is also programmed 3184a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * with the base address of the Memory Window in BAR0's address 3194a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * space. For T4 this is an absolute PCI-E Bus Address. For T5 3204a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * the address is relative to BAR0. 3214a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan */ 3224a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan mem_reg = csio_rd_reg32(hw, 3234a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, win)); 3244a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan mem_aperture = 1 << (WINDOW(mem_reg) + 10); 3254a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan mem_base = GET_PCIEOFST(mem_reg) << 10; 3264a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan 3274a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan start = addr & ~(mem_aperture-1); 3284a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan offset = addr - start; 3294a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan win_pf = V_PFNUM(hw->pfn); 3304a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan 3314a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan csio_dbg(hw, "csio_t5_memory_rw: mem_reg: 0x%x, mem_aperture: 0x%x\n", 3324a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan mem_reg, mem_aperture); 3334a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan csio_dbg(hw, "csio_t5_memory_rw: mem_base: 0x%x, mem_offset: 0x%x\n", 3344a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan mem_base, memoffset); 3354a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan csio_dbg(hw, "csio_t5_memory_rw: start:0x%x, offset:0x%x, win_pf:%d\n", 3364a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan start, offset, win_pf); 3374a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan csio_dbg(hw, "csio_t5_memory_rw: mtype: %d, addr: 0x%x, len: %d\n", 3384a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan mtype, addr, len); 3394a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan 3404a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan for (pos = start; len > 0; pos += mem_aperture, offset = 0) { 3414a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan /* 3424a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * Move PCI-E Memory Window to our current transfer 3434a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * position. Read it back to ensure that changes propagate 3444a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * before we attempt to use the new value. 3454a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan */ 3464a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan csio_wr_reg32(hw, pos | win_pf, 3474a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, win)); 3484a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan csio_rd_reg32(hw, 3494a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, win)); 3504a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan 3514a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan while (offset < mem_aperture && len > 0) { 3524a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan if (dir) 3534a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan *buf++ = csio_rd_reg32(hw, mem_base + offset); 3544a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan else 3554a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan csio_wr_reg32(hw, *buf++, mem_base + offset); 3564a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan 3574a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan offset += sizeof(__be32); 3584a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan len -= sizeof(__be32); 3594a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan } 3604a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan } 3614a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan return 0; 3624a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan} 3634a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan 3644a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan/* 3654a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * csio_t5_dfs_create_ext_mem - setup debugfs for MC0 or MC1 to read the values 3664a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * @hw: the csio_hw 3674a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * 3684a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * This function creates files in the debugfs with external memory region 3694a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan * MC0 & MC1. 3704a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan */ 3714a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushanstatic void 3724a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushancsio_t5_dfs_create_ext_mem(struct csio_hw *hw) 3734a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan{ 3744a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan u32 size; 3754a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan int i = csio_rd_reg32(hw, MA_TARGET_MEM_ENABLE); 3764a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan if (i & EXT_MEM_ENABLE) { 3774a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan size = csio_rd_reg32(hw, MA_EXT_MEMORY_BAR); 3784a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan csio_add_debugfs_mem(hw, "mc0", MEM_MC0, 3794a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan EXT_MEM_SIZE_GET(size)); 3804a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan } 3814a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan if (i & EXT_MEM1_ENABLE) { 3824a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan size = csio_rd_reg32(hw, MA_EXT_MEMORY1_BAR); 3834a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan csio_add_debugfs_mem(hw, "mc1", MEM_MC1, 3844a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan EXT_MEM_SIZE_GET(size)); 3854a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan } 3864a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan} 3874a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan 3884a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan/* T5 adapter specific function */ 3894a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushanstruct csio_hw_chip_ops t5_ops = { 3904a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan .chip_set_mem_win = csio_t5_set_mem_win, 3914a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan .chip_pcie_intr_handler = csio_t5_pcie_intr_handler, 3924a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan .chip_flash_cfg_addr = csio_t5_flash_cfg_addr, 3934a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan .chip_mc_read = csio_t5_mc_read, 3944a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan .chip_edc_read = csio_t5_edc_read, 3954a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan .chip_memory_rw = csio_t5_memory_rw, 3964a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan .chip_dfs_create_ext_mem = csio_t5_dfs_create_ext_mem, 3974a22edb593012041ee656a88ea7f9889837cb0d1Arvind Bhushan}; 398