qla_dbg.c revision 754d1243915d0fda6874fa0f1a926d85eb09e0b4
1/* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2013 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 8/* 9 * Table for showing the current message id in use for particular level 10 * Change this table for addition of log/debug messages. 11 * ---------------------------------------------------------------------- 12 * | Level | Last Value Used | Holes | 13 * ---------------------------------------------------------------------- 14 * | Module Init and Probe | 0x014f | 0x4b,0xba,0xfa | 15 * | Mailbox commands | 0x117a | 0x111a-0x111b | 16 * | | | 0x1155-0x1158 | 17 * | Device Discovery | 0x2095 | 0x2020-0x2022, | 18 * | | | 0x2016 | 19 * | Queue Command and IO tracing | 0x3058 | 0x3006-0x300b | 20 * | | | 0x3027-0x3028 | 21 * | | | 0x303d-0x3041 | 22 * | | | 0x302d,0x3033 | 23 * | | | 0x3036,0x3038 | 24 * | | | 0x303a | 25 * | DPC Thread | 0x4022 | 0x4002,0x4013 | 26 * | Async Events | 0x5081 | 0x502b-0x502f | 27 * | | | 0x5047,0x5052 | 28 * | | | 0x5040,0x5075 | 29 * | Timer Routines | 0x6011 | | 30 * | User Space Interactions | 0x70dd | 0x7018,0x702e, | 31 * | | | 0x7020,0x7024, | 32 * | | | 0x7039,0x7045, | 33 * | | | 0x7073-0x7075, | 34 * | | | 0x707b,0x708c, | 35 * | | | 0x70a5,0x70a6, | 36 * | | | 0x70a8,0x70ab, | 37 * | | | 0x70ad-0x70ae, | 38 * | | | 0x70d1-0x70da | 39 * | Task Management | 0x803c | 0x8025-0x8026 | 40 * | | | 0x800b,0x8039 | 41 * | AER/EEH | 0x9011 | | 42 * | Virtual Port | 0xa007 | | 43 * | ISP82XX Specific | 0xb086 | 0xb002,0xb024 | 44 * | MultiQ | 0xc00c | | 45 * | Misc | 0xd010 | | 46 * | Target Mode | 0xe070 | | 47 * | Target Mode Management | 0xf072 | | 48 * | Target Mode Task Management | 0x1000b | | 49 * ---------------------------------------------------------------------- 50 */ 51 52#include "qla_def.h" 53 54#include <linux/delay.h> 55 56static uint32_t ql_dbg_offset = 0x800; 57 58static inline void 59qla2xxx_prep_dump(struct qla_hw_data *ha, struct qla2xxx_fw_dump *fw_dump) 60{ 61 fw_dump->fw_major_version = htonl(ha->fw_major_version); 62 fw_dump->fw_minor_version = htonl(ha->fw_minor_version); 63 fw_dump->fw_subminor_version = htonl(ha->fw_subminor_version); 64 fw_dump->fw_attributes = htonl(ha->fw_attributes); 65 66 fw_dump->vendor = htonl(ha->pdev->vendor); 67 fw_dump->device = htonl(ha->pdev->device); 68 fw_dump->subsystem_vendor = htonl(ha->pdev->subsystem_vendor); 69 fw_dump->subsystem_device = htonl(ha->pdev->subsystem_device); 70} 71 72static inline void * 73qla2xxx_copy_queues(struct qla_hw_data *ha, void *ptr) 74{ 75 struct req_que *req = ha->req_q_map[0]; 76 struct rsp_que *rsp = ha->rsp_q_map[0]; 77 /* Request queue. */ 78 memcpy(ptr, req->ring, req->length * 79 sizeof(request_t)); 80 81 /* Response queue. */ 82 ptr += req->length * sizeof(request_t); 83 memcpy(ptr, rsp->ring, rsp->length * 84 sizeof(response_t)); 85 86 return ptr + (rsp->length * sizeof(response_t)); 87} 88 89static int 90qla24xx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint32_t *ram, 91 uint32_t ram_dwords, void **nxt) 92{ 93 int rval; 94 uint32_t cnt, stat, timer, dwords, idx; 95 uint16_t mb0; 96 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 97 dma_addr_t dump_dma = ha->gid_list_dma; 98 uint32_t *dump = (uint32_t *)ha->gid_list; 99 100 rval = QLA_SUCCESS; 101 mb0 = 0; 102 103 WRT_REG_WORD(®->mailbox0, MBC_DUMP_RISC_RAM_EXTENDED); 104 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 105 106 dwords = qla2x00_gid_list_size(ha) / 4; 107 for (cnt = 0; cnt < ram_dwords && rval == QLA_SUCCESS; 108 cnt += dwords, addr += dwords) { 109 if (cnt + dwords > ram_dwords) 110 dwords = ram_dwords - cnt; 111 112 WRT_REG_WORD(®->mailbox1, LSW(addr)); 113 WRT_REG_WORD(®->mailbox8, MSW(addr)); 114 115 WRT_REG_WORD(®->mailbox2, MSW(dump_dma)); 116 WRT_REG_WORD(®->mailbox3, LSW(dump_dma)); 117 WRT_REG_WORD(®->mailbox6, MSW(MSD(dump_dma))); 118 WRT_REG_WORD(®->mailbox7, LSW(MSD(dump_dma))); 119 120 WRT_REG_WORD(®->mailbox4, MSW(dwords)); 121 WRT_REG_WORD(®->mailbox5, LSW(dwords)); 122 WRT_REG_DWORD(®->hccr, HCCRX_SET_HOST_INT); 123 124 for (timer = 6000000; timer; timer--) { 125 /* Check for pending interrupts. */ 126 stat = RD_REG_DWORD(®->host_status); 127 if (stat & HSRX_RISC_INT) { 128 stat &= 0xff; 129 130 if (stat == 0x1 || stat == 0x2 || 131 stat == 0x10 || stat == 0x11) { 132 set_bit(MBX_INTERRUPT, 133 &ha->mbx_cmd_flags); 134 135 mb0 = RD_REG_WORD(®->mailbox0); 136 137 WRT_REG_DWORD(®->hccr, 138 HCCRX_CLR_RISC_INT); 139 RD_REG_DWORD(®->hccr); 140 break; 141 } 142 143 /* Clear this intr; it wasn't a mailbox intr */ 144 WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_INT); 145 RD_REG_DWORD(®->hccr); 146 } 147 udelay(5); 148 } 149 150 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { 151 rval = mb0 & MBS_MASK; 152 for (idx = 0; idx < dwords; idx++) 153 ram[cnt + idx] = swab32(dump[idx]); 154 } else { 155 rval = QLA_FUNCTION_FAILED; 156 } 157 } 158 159 *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL; 160 return rval; 161} 162 163static int 164qla24xx_dump_memory(struct qla_hw_data *ha, uint32_t *code_ram, 165 uint32_t cram_size, void **nxt) 166{ 167 int rval; 168 169 /* Code RAM. */ 170 rval = qla24xx_dump_ram(ha, 0x20000, code_ram, cram_size / 4, nxt); 171 if (rval != QLA_SUCCESS) 172 return rval; 173 174 /* External Memory. */ 175 return qla24xx_dump_ram(ha, 0x100000, *nxt, 176 ha->fw_memory_size - 0x100000 + 1, nxt); 177} 178 179static uint32_t * 180qla24xx_read_window(struct device_reg_24xx __iomem *reg, uint32_t iobase, 181 uint32_t count, uint32_t *buf) 182{ 183 uint32_t __iomem *dmp_reg; 184 185 WRT_REG_DWORD(®->iobase_addr, iobase); 186 dmp_reg = ®->iobase_window; 187 while (count--) 188 *buf++ = htonl(RD_REG_DWORD(dmp_reg++)); 189 190 return buf; 191} 192 193static inline int 194qla24xx_pause_risc(struct device_reg_24xx __iomem *reg) 195{ 196 int rval = QLA_SUCCESS; 197 uint32_t cnt; 198 199 WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_PAUSE); 200 for (cnt = 30000; 201 ((RD_REG_DWORD(®->host_status) & HSRX_RISC_PAUSED) == 0) && 202 rval == QLA_SUCCESS; cnt--) { 203 if (cnt) 204 udelay(100); 205 else 206 rval = QLA_FUNCTION_TIMEOUT; 207 } 208 209 return rval; 210} 211 212static int 213qla24xx_soft_reset(struct qla_hw_data *ha) 214{ 215 int rval = QLA_SUCCESS; 216 uint32_t cnt; 217 uint16_t mb0, wd; 218 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 219 220 /* Reset RISC. */ 221 WRT_REG_DWORD(®->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); 222 for (cnt = 0; cnt < 30000; cnt++) { 223 if ((RD_REG_DWORD(®->ctrl_status) & CSRX_DMA_ACTIVE) == 0) 224 break; 225 226 udelay(10); 227 } 228 229 WRT_REG_DWORD(®->ctrl_status, 230 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); 231 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd); 232 233 udelay(100); 234 /* Wait for firmware to complete NVRAM accesses. */ 235 mb0 = (uint32_t) RD_REG_WORD(®->mailbox0); 236 for (cnt = 10000 ; cnt && mb0; cnt--) { 237 udelay(5); 238 mb0 = (uint32_t) RD_REG_WORD(®->mailbox0); 239 barrier(); 240 } 241 242 /* Wait for soft-reset to complete. */ 243 for (cnt = 0; cnt < 30000; cnt++) { 244 if ((RD_REG_DWORD(®->ctrl_status) & 245 CSRX_ISP_SOFT_RESET) == 0) 246 break; 247 248 udelay(10); 249 } 250 WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_RESET); 251 RD_REG_DWORD(®->hccr); /* PCI Posting. */ 252 253 for (cnt = 30000; RD_REG_WORD(®->mailbox0) != 0 && 254 rval == QLA_SUCCESS; cnt--) { 255 if (cnt) 256 udelay(100); 257 else 258 rval = QLA_FUNCTION_TIMEOUT; 259 } 260 261 return rval; 262} 263 264static int 265qla2xxx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint16_t *ram, 266 uint32_t ram_words, void **nxt) 267{ 268 int rval; 269 uint32_t cnt, stat, timer, words, idx; 270 uint16_t mb0; 271 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 272 dma_addr_t dump_dma = ha->gid_list_dma; 273 uint16_t *dump = (uint16_t *)ha->gid_list; 274 275 rval = QLA_SUCCESS; 276 mb0 = 0; 277 278 WRT_MAILBOX_REG(ha, reg, 0, MBC_DUMP_RISC_RAM_EXTENDED); 279 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 280 281 words = qla2x00_gid_list_size(ha) / 2; 282 for (cnt = 0; cnt < ram_words && rval == QLA_SUCCESS; 283 cnt += words, addr += words) { 284 if (cnt + words > ram_words) 285 words = ram_words - cnt; 286 287 WRT_MAILBOX_REG(ha, reg, 1, LSW(addr)); 288 WRT_MAILBOX_REG(ha, reg, 8, MSW(addr)); 289 290 WRT_MAILBOX_REG(ha, reg, 2, MSW(dump_dma)); 291 WRT_MAILBOX_REG(ha, reg, 3, LSW(dump_dma)); 292 WRT_MAILBOX_REG(ha, reg, 6, MSW(MSD(dump_dma))); 293 WRT_MAILBOX_REG(ha, reg, 7, LSW(MSD(dump_dma))); 294 295 WRT_MAILBOX_REG(ha, reg, 4, words); 296 WRT_REG_WORD(®->hccr, HCCR_SET_HOST_INT); 297 298 for (timer = 6000000; timer; timer--) { 299 /* Check for pending interrupts. */ 300 stat = RD_REG_DWORD(®->u.isp2300.host_status); 301 if (stat & HSR_RISC_INT) { 302 stat &= 0xff; 303 304 if (stat == 0x1 || stat == 0x2) { 305 set_bit(MBX_INTERRUPT, 306 &ha->mbx_cmd_flags); 307 308 mb0 = RD_MAILBOX_REG(ha, reg, 0); 309 310 /* Release mailbox registers. */ 311 WRT_REG_WORD(®->semaphore, 0); 312 WRT_REG_WORD(®->hccr, 313 HCCR_CLR_RISC_INT); 314 RD_REG_WORD(®->hccr); 315 break; 316 } else if (stat == 0x10 || stat == 0x11) { 317 set_bit(MBX_INTERRUPT, 318 &ha->mbx_cmd_flags); 319 320 mb0 = RD_MAILBOX_REG(ha, reg, 0); 321 322 WRT_REG_WORD(®->hccr, 323 HCCR_CLR_RISC_INT); 324 RD_REG_WORD(®->hccr); 325 break; 326 } 327 328 /* clear this intr; it wasn't a mailbox intr */ 329 WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT); 330 RD_REG_WORD(®->hccr); 331 } 332 udelay(5); 333 } 334 335 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { 336 rval = mb0 & MBS_MASK; 337 for (idx = 0; idx < words; idx++) 338 ram[cnt + idx] = swab16(dump[idx]); 339 } else { 340 rval = QLA_FUNCTION_FAILED; 341 } 342 } 343 344 *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL; 345 return rval; 346} 347 348static inline void 349qla2xxx_read_window(struct device_reg_2xxx __iomem *reg, uint32_t count, 350 uint16_t *buf) 351{ 352 uint16_t __iomem *dmp_reg = ®->u.isp2300.fb_cmd; 353 354 while (count--) 355 *buf++ = htons(RD_REG_WORD(dmp_reg++)); 356} 357 358static inline void * 359qla24xx_copy_eft(struct qla_hw_data *ha, void *ptr) 360{ 361 if (!ha->eft) 362 return ptr; 363 364 memcpy(ptr, ha->eft, ntohl(ha->fw_dump->eft_size)); 365 return ptr + ntohl(ha->fw_dump->eft_size); 366} 367 368static inline void * 369qla25xx_copy_fce(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain) 370{ 371 uint32_t cnt; 372 uint32_t *iter_reg; 373 struct qla2xxx_fce_chain *fcec = ptr; 374 375 if (!ha->fce) 376 return ptr; 377 378 *last_chain = &fcec->type; 379 fcec->type = __constant_htonl(DUMP_CHAIN_FCE); 380 fcec->chain_size = htonl(sizeof(struct qla2xxx_fce_chain) + 381 fce_calc_size(ha->fce_bufs)); 382 fcec->size = htonl(fce_calc_size(ha->fce_bufs)); 383 fcec->addr_l = htonl(LSD(ha->fce_dma)); 384 fcec->addr_h = htonl(MSD(ha->fce_dma)); 385 386 iter_reg = fcec->eregs; 387 for (cnt = 0; cnt < 8; cnt++) 388 *iter_reg++ = htonl(ha->fce_mb[cnt]); 389 390 memcpy(iter_reg, ha->fce, ntohl(fcec->size)); 391 392 return (char *)iter_reg + ntohl(fcec->size); 393} 394 395static inline void * 396qla2xxx_copy_atioqueues(struct qla_hw_data *ha, void *ptr, 397 uint32_t **last_chain) 398{ 399 struct qla2xxx_mqueue_chain *q; 400 struct qla2xxx_mqueue_header *qh; 401 uint32_t num_queues; 402 int que; 403 struct { 404 int length; 405 void *ring; 406 } aq, *aqp; 407 408 if (!ha->tgt.atio_ring) 409 return ptr; 410 411 num_queues = 1; 412 aqp = &aq; 413 aqp->length = ha->tgt.atio_q_length; 414 aqp->ring = ha->tgt.atio_ring; 415 416 for (que = 0; que < num_queues; que++) { 417 /* aqp = ha->atio_q_map[que]; */ 418 q = ptr; 419 *last_chain = &q->type; 420 q->type = __constant_htonl(DUMP_CHAIN_QUEUE); 421 q->chain_size = htonl( 422 sizeof(struct qla2xxx_mqueue_chain) + 423 sizeof(struct qla2xxx_mqueue_header) + 424 (aqp->length * sizeof(request_t))); 425 ptr += sizeof(struct qla2xxx_mqueue_chain); 426 427 /* Add header. */ 428 qh = ptr; 429 qh->queue = __constant_htonl(TYPE_ATIO_QUEUE); 430 qh->number = htonl(que); 431 qh->size = htonl(aqp->length * sizeof(request_t)); 432 ptr += sizeof(struct qla2xxx_mqueue_header); 433 434 /* Add data. */ 435 memcpy(ptr, aqp->ring, aqp->length * sizeof(request_t)); 436 437 ptr += aqp->length * sizeof(request_t); 438 } 439 440 return ptr; 441} 442 443static inline void * 444qla25xx_copy_mqueues(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain) 445{ 446 struct qla2xxx_mqueue_chain *q; 447 struct qla2xxx_mqueue_header *qh; 448 struct req_que *req; 449 struct rsp_que *rsp; 450 int que; 451 452 if (!ha->mqenable) 453 return ptr; 454 455 /* Request queues */ 456 for (que = 1; que < ha->max_req_queues; que++) { 457 req = ha->req_q_map[que]; 458 if (!req) 459 break; 460 461 /* Add chain. */ 462 q = ptr; 463 *last_chain = &q->type; 464 q->type = __constant_htonl(DUMP_CHAIN_QUEUE); 465 q->chain_size = htonl( 466 sizeof(struct qla2xxx_mqueue_chain) + 467 sizeof(struct qla2xxx_mqueue_header) + 468 (req->length * sizeof(request_t))); 469 ptr += sizeof(struct qla2xxx_mqueue_chain); 470 471 /* Add header. */ 472 qh = ptr; 473 qh->queue = __constant_htonl(TYPE_REQUEST_QUEUE); 474 qh->number = htonl(que); 475 qh->size = htonl(req->length * sizeof(request_t)); 476 ptr += sizeof(struct qla2xxx_mqueue_header); 477 478 /* Add data. */ 479 memcpy(ptr, req->ring, req->length * sizeof(request_t)); 480 ptr += req->length * sizeof(request_t); 481 } 482 483 /* Response queues */ 484 for (que = 1; que < ha->max_rsp_queues; que++) { 485 rsp = ha->rsp_q_map[que]; 486 if (!rsp) 487 break; 488 489 /* Add chain. */ 490 q = ptr; 491 *last_chain = &q->type; 492 q->type = __constant_htonl(DUMP_CHAIN_QUEUE); 493 q->chain_size = htonl( 494 sizeof(struct qla2xxx_mqueue_chain) + 495 sizeof(struct qla2xxx_mqueue_header) + 496 (rsp->length * sizeof(response_t))); 497 ptr += sizeof(struct qla2xxx_mqueue_chain); 498 499 /* Add header. */ 500 qh = ptr; 501 qh->queue = __constant_htonl(TYPE_RESPONSE_QUEUE); 502 qh->number = htonl(que); 503 qh->size = htonl(rsp->length * sizeof(response_t)); 504 ptr += sizeof(struct qla2xxx_mqueue_header); 505 506 /* Add data. */ 507 memcpy(ptr, rsp->ring, rsp->length * sizeof(response_t)); 508 ptr += rsp->length * sizeof(response_t); 509 } 510 511 return ptr; 512} 513 514static inline void * 515qla25xx_copy_mq(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain) 516{ 517 uint32_t cnt, que_idx; 518 uint8_t que_cnt; 519 struct qla2xxx_mq_chain *mq = ptr; 520 struct device_reg_25xxmq __iomem *reg; 521 522 if (!ha->mqenable || IS_QLA83XX(ha)) 523 return ptr; 524 525 mq = ptr; 526 *last_chain = &mq->type; 527 mq->type = __constant_htonl(DUMP_CHAIN_MQ); 528 mq->chain_size = __constant_htonl(sizeof(struct qla2xxx_mq_chain)); 529 530 que_cnt = ha->max_req_queues > ha->max_rsp_queues ? 531 ha->max_req_queues : ha->max_rsp_queues; 532 mq->count = htonl(que_cnt); 533 for (cnt = 0; cnt < que_cnt; cnt++) { 534 reg = (struct device_reg_25xxmq __iomem *) 535 (ha->mqiobase + cnt * QLA_QUE_PAGE); 536 que_idx = cnt * 4; 537 mq->qregs[que_idx] = htonl(RD_REG_DWORD(®->req_q_in)); 538 mq->qregs[que_idx+1] = htonl(RD_REG_DWORD(®->req_q_out)); 539 mq->qregs[que_idx+2] = htonl(RD_REG_DWORD(®->rsp_q_in)); 540 mq->qregs[que_idx+3] = htonl(RD_REG_DWORD(®->rsp_q_out)); 541 } 542 543 return ptr + sizeof(struct qla2xxx_mq_chain); 544} 545 546void 547qla2xxx_dump_post_process(scsi_qla_host_t *vha, int rval) 548{ 549 struct qla_hw_data *ha = vha->hw; 550 551 if (rval != QLA_SUCCESS) { 552 ql_log(ql_log_warn, vha, 0xd000, 553 "Failed to dump firmware (%x).\n", rval); 554 ha->fw_dumped = 0; 555 } else { 556 ql_log(ql_log_info, vha, 0xd001, 557 "Firmware dump saved to temp buffer (%ld/%p).\n", 558 vha->host_no, ha->fw_dump); 559 ha->fw_dumped = 1; 560 qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP); 561 } 562} 563 564/** 565 * qla2300_fw_dump() - Dumps binary data from the 2300 firmware. 566 * @ha: HA context 567 * @hardware_locked: Called with the hardware_lock 568 */ 569void 570qla2300_fw_dump(scsi_qla_host_t *vha, int hardware_locked) 571{ 572 int rval; 573 uint32_t cnt; 574 struct qla_hw_data *ha = vha->hw; 575 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 576 uint16_t __iomem *dmp_reg; 577 unsigned long flags; 578 struct qla2300_fw_dump *fw; 579 void *nxt; 580 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 581 582 flags = 0; 583 584 if (!hardware_locked) 585 spin_lock_irqsave(&ha->hardware_lock, flags); 586 587 if (!ha->fw_dump) { 588 ql_log(ql_log_warn, vha, 0xd002, 589 "No buffer available for dump.\n"); 590 goto qla2300_fw_dump_failed; 591 } 592 593 if (ha->fw_dumped) { 594 ql_log(ql_log_warn, vha, 0xd003, 595 "Firmware has been previously dumped (%p) " 596 "-- ignoring request.\n", 597 ha->fw_dump); 598 goto qla2300_fw_dump_failed; 599 } 600 fw = &ha->fw_dump->isp.isp23; 601 qla2xxx_prep_dump(ha, ha->fw_dump); 602 603 rval = QLA_SUCCESS; 604 fw->hccr = htons(RD_REG_WORD(®->hccr)); 605 606 /* Pause RISC. */ 607 WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); 608 if (IS_QLA2300(ha)) { 609 for (cnt = 30000; 610 (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 && 611 rval == QLA_SUCCESS; cnt--) { 612 if (cnt) 613 udelay(100); 614 else 615 rval = QLA_FUNCTION_TIMEOUT; 616 } 617 } else { 618 RD_REG_WORD(®->hccr); /* PCI Posting. */ 619 udelay(10); 620 } 621 622 if (rval == QLA_SUCCESS) { 623 dmp_reg = ®->flash_address; 624 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++) 625 fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); 626 627 dmp_reg = ®->u.isp2300.req_q_in; 628 for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; cnt++) 629 fw->risc_host_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); 630 631 dmp_reg = ®->u.isp2300.mailbox0; 632 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) 633 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); 634 635 WRT_REG_WORD(®->ctrl_status, 0x40); 636 qla2xxx_read_window(reg, 32, fw->resp_dma_reg); 637 638 WRT_REG_WORD(®->ctrl_status, 0x50); 639 qla2xxx_read_window(reg, 48, fw->dma_reg); 640 641 WRT_REG_WORD(®->ctrl_status, 0x00); 642 dmp_reg = ®->risc_hw; 643 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++) 644 fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); 645 646 WRT_REG_WORD(®->pcr, 0x2000); 647 qla2xxx_read_window(reg, 16, fw->risc_gp0_reg); 648 649 WRT_REG_WORD(®->pcr, 0x2200); 650 qla2xxx_read_window(reg, 16, fw->risc_gp1_reg); 651 652 WRT_REG_WORD(®->pcr, 0x2400); 653 qla2xxx_read_window(reg, 16, fw->risc_gp2_reg); 654 655 WRT_REG_WORD(®->pcr, 0x2600); 656 qla2xxx_read_window(reg, 16, fw->risc_gp3_reg); 657 658 WRT_REG_WORD(®->pcr, 0x2800); 659 qla2xxx_read_window(reg, 16, fw->risc_gp4_reg); 660 661 WRT_REG_WORD(®->pcr, 0x2A00); 662 qla2xxx_read_window(reg, 16, fw->risc_gp5_reg); 663 664 WRT_REG_WORD(®->pcr, 0x2C00); 665 qla2xxx_read_window(reg, 16, fw->risc_gp6_reg); 666 667 WRT_REG_WORD(®->pcr, 0x2E00); 668 qla2xxx_read_window(reg, 16, fw->risc_gp7_reg); 669 670 WRT_REG_WORD(®->ctrl_status, 0x10); 671 qla2xxx_read_window(reg, 64, fw->frame_buf_hdw_reg); 672 673 WRT_REG_WORD(®->ctrl_status, 0x20); 674 qla2xxx_read_window(reg, 64, fw->fpm_b0_reg); 675 676 WRT_REG_WORD(®->ctrl_status, 0x30); 677 qla2xxx_read_window(reg, 64, fw->fpm_b1_reg); 678 679 /* Reset RISC. */ 680 WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET); 681 for (cnt = 0; cnt < 30000; cnt++) { 682 if ((RD_REG_WORD(®->ctrl_status) & 683 CSR_ISP_SOFT_RESET) == 0) 684 break; 685 686 udelay(10); 687 } 688 } 689 690 if (!IS_QLA2300(ha)) { 691 for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 && 692 rval == QLA_SUCCESS; cnt--) { 693 if (cnt) 694 udelay(100); 695 else 696 rval = QLA_FUNCTION_TIMEOUT; 697 } 698 } 699 700 /* Get RISC SRAM. */ 701 if (rval == QLA_SUCCESS) 702 rval = qla2xxx_dump_ram(ha, 0x800, fw->risc_ram, 703 sizeof(fw->risc_ram) / 2, &nxt); 704 705 /* Get stack SRAM. */ 706 if (rval == QLA_SUCCESS) 707 rval = qla2xxx_dump_ram(ha, 0x10000, fw->stack_ram, 708 sizeof(fw->stack_ram) / 2, &nxt); 709 710 /* Get data SRAM. */ 711 if (rval == QLA_SUCCESS) 712 rval = qla2xxx_dump_ram(ha, 0x11000, fw->data_ram, 713 ha->fw_memory_size - 0x11000 + 1, &nxt); 714 715 if (rval == QLA_SUCCESS) 716 qla2xxx_copy_queues(ha, nxt); 717 718 qla2xxx_dump_post_process(base_vha, rval); 719 720qla2300_fw_dump_failed: 721 if (!hardware_locked) 722 spin_unlock_irqrestore(&ha->hardware_lock, flags); 723} 724 725/** 726 * qla2100_fw_dump() - Dumps binary data from the 2100/2200 firmware. 727 * @ha: HA context 728 * @hardware_locked: Called with the hardware_lock 729 */ 730void 731qla2100_fw_dump(scsi_qla_host_t *vha, int hardware_locked) 732{ 733 int rval; 734 uint32_t cnt, timer; 735 uint16_t risc_address; 736 uint16_t mb0, mb2; 737 struct qla_hw_data *ha = vha->hw; 738 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 739 uint16_t __iomem *dmp_reg; 740 unsigned long flags; 741 struct qla2100_fw_dump *fw; 742 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 743 744 risc_address = 0; 745 mb0 = mb2 = 0; 746 flags = 0; 747 748 if (!hardware_locked) 749 spin_lock_irqsave(&ha->hardware_lock, flags); 750 751 if (!ha->fw_dump) { 752 ql_log(ql_log_warn, vha, 0xd004, 753 "No buffer available for dump.\n"); 754 goto qla2100_fw_dump_failed; 755 } 756 757 if (ha->fw_dumped) { 758 ql_log(ql_log_warn, vha, 0xd005, 759 "Firmware has been previously dumped (%p) " 760 "-- ignoring request.\n", 761 ha->fw_dump); 762 goto qla2100_fw_dump_failed; 763 } 764 fw = &ha->fw_dump->isp.isp21; 765 qla2xxx_prep_dump(ha, ha->fw_dump); 766 767 rval = QLA_SUCCESS; 768 fw->hccr = htons(RD_REG_WORD(®->hccr)); 769 770 /* Pause RISC. */ 771 WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); 772 for (cnt = 30000; (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 && 773 rval == QLA_SUCCESS; cnt--) { 774 if (cnt) 775 udelay(100); 776 else 777 rval = QLA_FUNCTION_TIMEOUT; 778 } 779 if (rval == QLA_SUCCESS) { 780 dmp_reg = ®->flash_address; 781 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++) 782 fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); 783 784 dmp_reg = ®->u.isp2100.mailbox0; 785 for (cnt = 0; cnt < ha->mbx_count; cnt++) { 786 if (cnt == 8) 787 dmp_reg = ®->u_end.isp2200.mailbox8; 788 789 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); 790 } 791 792 dmp_reg = ®->u.isp2100.unused_2[0]; 793 for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++) 794 fw->dma_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); 795 796 WRT_REG_WORD(®->ctrl_status, 0x00); 797 dmp_reg = ®->risc_hw; 798 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++) 799 fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); 800 801 WRT_REG_WORD(®->pcr, 0x2000); 802 qla2xxx_read_window(reg, 16, fw->risc_gp0_reg); 803 804 WRT_REG_WORD(®->pcr, 0x2100); 805 qla2xxx_read_window(reg, 16, fw->risc_gp1_reg); 806 807 WRT_REG_WORD(®->pcr, 0x2200); 808 qla2xxx_read_window(reg, 16, fw->risc_gp2_reg); 809 810 WRT_REG_WORD(®->pcr, 0x2300); 811 qla2xxx_read_window(reg, 16, fw->risc_gp3_reg); 812 813 WRT_REG_WORD(®->pcr, 0x2400); 814 qla2xxx_read_window(reg, 16, fw->risc_gp4_reg); 815 816 WRT_REG_WORD(®->pcr, 0x2500); 817 qla2xxx_read_window(reg, 16, fw->risc_gp5_reg); 818 819 WRT_REG_WORD(®->pcr, 0x2600); 820 qla2xxx_read_window(reg, 16, fw->risc_gp6_reg); 821 822 WRT_REG_WORD(®->pcr, 0x2700); 823 qla2xxx_read_window(reg, 16, fw->risc_gp7_reg); 824 825 WRT_REG_WORD(®->ctrl_status, 0x10); 826 qla2xxx_read_window(reg, 16, fw->frame_buf_hdw_reg); 827 828 WRT_REG_WORD(®->ctrl_status, 0x20); 829 qla2xxx_read_window(reg, 64, fw->fpm_b0_reg); 830 831 WRT_REG_WORD(®->ctrl_status, 0x30); 832 qla2xxx_read_window(reg, 64, fw->fpm_b1_reg); 833 834 /* Reset the ISP. */ 835 WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET); 836 } 837 838 for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 && 839 rval == QLA_SUCCESS; cnt--) { 840 if (cnt) 841 udelay(100); 842 else 843 rval = QLA_FUNCTION_TIMEOUT; 844 } 845 846 /* Pause RISC. */ 847 if (rval == QLA_SUCCESS && (IS_QLA2200(ha) || (IS_QLA2100(ha) && 848 (RD_REG_WORD(®->mctr) & (BIT_1 | BIT_0)) != 0))) { 849 850 WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); 851 for (cnt = 30000; 852 (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 && 853 rval == QLA_SUCCESS; cnt--) { 854 if (cnt) 855 udelay(100); 856 else 857 rval = QLA_FUNCTION_TIMEOUT; 858 } 859 if (rval == QLA_SUCCESS) { 860 /* Set memory configuration and timing. */ 861 if (IS_QLA2100(ha)) 862 WRT_REG_WORD(®->mctr, 0xf1); 863 else 864 WRT_REG_WORD(®->mctr, 0xf2); 865 RD_REG_WORD(®->mctr); /* PCI Posting. */ 866 867 /* Release RISC. */ 868 WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC); 869 } 870 } 871 872 if (rval == QLA_SUCCESS) { 873 /* Get RISC SRAM. */ 874 risc_address = 0x1000; 875 WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD); 876 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 877 } 878 for (cnt = 0; cnt < sizeof(fw->risc_ram) / 2 && rval == QLA_SUCCESS; 879 cnt++, risc_address++) { 880 WRT_MAILBOX_REG(ha, reg, 1, risc_address); 881 WRT_REG_WORD(®->hccr, HCCR_SET_HOST_INT); 882 883 for (timer = 6000000; timer != 0; timer--) { 884 /* Check for pending interrupts. */ 885 if (RD_REG_WORD(®->istatus) & ISR_RISC_INT) { 886 if (RD_REG_WORD(®->semaphore) & BIT_0) { 887 set_bit(MBX_INTERRUPT, 888 &ha->mbx_cmd_flags); 889 890 mb0 = RD_MAILBOX_REG(ha, reg, 0); 891 mb2 = RD_MAILBOX_REG(ha, reg, 2); 892 893 WRT_REG_WORD(®->semaphore, 0); 894 WRT_REG_WORD(®->hccr, 895 HCCR_CLR_RISC_INT); 896 RD_REG_WORD(®->hccr); 897 break; 898 } 899 WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT); 900 RD_REG_WORD(®->hccr); 901 } 902 udelay(5); 903 } 904 905 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { 906 rval = mb0 & MBS_MASK; 907 fw->risc_ram[cnt] = htons(mb2); 908 } else { 909 rval = QLA_FUNCTION_FAILED; 910 } 911 } 912 913 if (rval == QLA_SUCCESS) 914 qla2xxx_copy_queues(ha, &fw->risc_ram[cnt]); 915 916 qla2xxx_dump_post_process(base_vha, rval); 917 918qla2100_fw_dump_failed: 919 if (!hardware_locked) 920 spin_unlock_irqrestore(&ha->hardware_lock, flags); 921} 922 923void 924qla24xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) 925{ 926 int rval; 927 uint32_t cnt; 928 uint32_t risc_address; 929 struct qla_hw_data *ha = vha->hw; 930 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 931 uint32_t __iomem *dmp_reg; 932 uint32_t *iter_reg; 933 uint16_t __iomem *mbx_reg; 934 unsigned long flags; 935 struct qla24xx_fw_dump *fw; 936 uint32_t ext_mem_cnt; 937 void *nxt; 938 void *nxt_chain; 939 uint32_t *last_chain = NULL; 940 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 941 942 if (IS_QLA82XX(ha)) 943 return; 944 945 risc_address = ext_mem_cnt = 0; 946 flags = 0; 947 948 if (!hardware_locked) 949 spin_lock_irqsave(&ha->hardware_lock, flags); 950 951 if (!ha->fw_dump) { 952 ql_log(ql_log_warn, vha, 0xd006, 953 "No buffer available for dump.\n"); 954 goto qla24xx_fw_dump_failed; 955 } 956 957 if (ha->fw_dumped) { 958 ql_log(ql_log_warn, vha, 0xd007, 959 "Firmware has been previously dumped (%p) " 960 "-- ignoring request.\n", 961 ha->fw_dump); 962 goto qla24xx_fw_dump_failed; 963 } 964 fw = &ha->fw_dump->isp.isp24; 965 qla2xxx_prep_dump(ha, ha->fw_dump); 966 967 fw->host_status = htonl(RD_REG_DWORD(®->host_status)); 968 969 /* Pause RISC. */ 970 rval = qla24xx_pause_risc(reg); 971 if (rval != QLA_SUCCESS) 972 goto qla24xx_fw_dump_failed_0; 973 974 /* Host interface registers. */ 975 dmp_reg = ®->flash_addr; 976 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) 977 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); 978 979 /* Disable interrupts. */ 980 WRT_REG_DWORD(®->ictrl, 0); 981 RD_REG_DWORD(®->ictrl); 982 983 /* Shadow registers. */ 984 WRT_REG_DWORD(®->iobase_addr, 0x0F70); 985 RD_REG_DWORD(®->iobase_addr); 986 WRT_REG_DWORD(®->iobase_select, 0xB0000000); 987 fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata)); 988 989 WRT_REG_DWORD(®->iobase_select, 0xB0100000); 990 fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata)); 991 992 WRT_REG_DWORD(®->iobase_select, 0xB0200000); 993 fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata)); 994 995 WRT_REG_DWORD(®->iobase_select, 0xB0300000); 996 fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata)); 997 998 WRT_REG_DWORD(®->iobase_select, 0xB0400000); 999 fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1000 1001 WRT_REG_DWORD(®->iobase_select, 0xB0500000); 1002 fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1003 1004 WRT_REG_DWORD(®->iobase_select, 0xB0600000); 1005 fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1006 1007 /* Mailbox registers. */ 1008 mbx_reg = ®->mailbox0; 1009 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) 1010 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++)); 1011 1012 /* Transfer sequence registers. */ 1013 iter_reg = fw->xseq_gp_reg; 1014 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg); 1015 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg); 1016 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg); 1017 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg); 1018 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg); 1019 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg); 1020 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg); 1021 qla24xx_read_window(reg, 0xBF70, 16, iter_reg); 1022 1023 qla24xx_read_window(reg, 0xBFE0, 16, fw->xseq_0_reg); 1024 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg); 1025 1026 /* Receive sequence registers. */ 1027 iter_reg = fw->rseq_gp_reg; 1028 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg); 1029 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg); 1030 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg); 1031 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg); 1032 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg); 1033 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg); 1034 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg); 1035 qla24xx_read_window(reg, 0xFF70, 16, iter_reg); 1036 1037 qla24xx_read_window(reg, 0xFFD0, 16, fw->rseq_0_reg); 1038 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg); 1039 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg); 1040 1041 /* Command DMA registers. */ 1042 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg); 1043 1044 /* Queues. */ 1045 iter_reg = fw->req0_dma_reg; 1046 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg); 1047 dmp_reg = ®->iobase_q; 1048 for (cnt = 0; cnt < 7; cnt++) 1049 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1050 1051 iter_reg = fw->resp0_dma_reg; 1052 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg); 1053 dmp_reg = ®->iobase_q; 1054 for (cnt = 0; cnt < 7; cnt++) 1055 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1056 1057 iter_reg = fw->req1_dma_reg; 1058 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg); 1059 dmp_reg = ®->iobase_q; 1060 for (cnt = 0; cnt < 7; cnt++) 1061 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1062 1063 /* Transmit DMA registers. */ 1064 iter_reg = fw->xmt0_dma_reg; 1065 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg); 1066 qla24xx_read_window(reg, 0x7610, 16, iter_reg); 1067 1068 iter_reg = fw->xmt1_dma_reg; 1069 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg); 1070 qla24xx_read_window(reg, 0x7630, 16, iter_reg); 1071 1072 iter_reg = fw->xmt2_dma_reg; 1073 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg); 1074 qla24xx_read_window(reg, 0x7650, 16, iter_reg); 1075 1076 iter_reg = fw->xmt3_dma_reg; 1077 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg); 1078 qla24xx_read_window(reg, 0x7670, 16, iter_reg); 1079 1080 iter_reg = fw->xmt4_dma_reg; 1081 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg); 1082 qla24xx_read_window(reg, 0x7690, 16, iter_reg); 1083 1084 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg); 1085 1086 /* Receive DMA registers. */ 1087 iter_reg = fw->rcvt0_data_dma_reg; 1088 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg); 1089 qla24xx_read_window(reg, 0x7710, 16, iter_reg); 1090 1091 iter_reg = fw->rcvt1_data_dma_reg; 1092 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg); 1093 qla24xx_read_window(reg, 0x7730, 16, iter_reg); 1094 1095 /* RISC registers. */ 1096 iter_reg = fw->risc_gp_reg; 1097 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg); 1098 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg); 1099 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg); 1100 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg); 1101 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg); 1102 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg); 1103 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg); 1104 qla24xx_read_window(reg, 0x0F70, 16, iter_reg); 1105 1106 /* Local memory controller registers. */ 1107 iter_reg = fw->lmc_reg; 1108 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg); 1109 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg); 1110 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg); 1111 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg); 1112 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg); 1113 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg); 1114 qla24xx_read_window(reg, 0x3060, 16, iter_reg); 1115 1116 /* Fibre Protocol Module registers. */ 1117 iter_reg = fw->fpm_hdw_reg; 1118 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg); 1119 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg); 1120 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg); 1121 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg); 1122 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg); 1123 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg); 1124 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg); 1125 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg); 1126 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg); 1127 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg); 1128 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg); 1129 qla24xx_read_window(reg, 0x40B0, 16, iter_reg); 1130 1131 /* Frame Buffer registers. */ 1132 iter_reg = fw->fb_hdw_reg; 1133 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg); 1134 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg); 1135 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg); 1136 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg); 1137 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg); 1138 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg); 1139 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg); 1140 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg); 1141 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg); 1142 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg); 1143 qla24xx_read_window(reg, 0x61B0, 16, iter_reg); 1144 1145 rval = qla24xx_soft_reset(ha); 1146 if (rval != QLA_SUCCESS) 1147 goto qla24xx_fw_dump_failed_0; 1148 1149 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram), 1150 &nxt); 1151 if (rval != QLA_SUCCESS) 1152 goto qla24xx_fw_dump_failed_0; 1153 1154 nxt = qla2xxx_copy_queues(ha, nxt); 1155 1156 qla24xx_copy_eft(ha, nxt); 1157 1158 nxt_chain = (void *)ha->fw_dump + ha->chain_offset; 1159 nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain); 1160 if (last_chain) { 1161 ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT); 1162 *last_chain |= __constant_htonl(DUMP_CHAIN_LAST); 1163 } 1164 1165 /* Adjust valid length. */ 1166 ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump); 1167 1168qla24xx_fw_dump_failed_0: 1169 qla2xxx_dump_post_process(base_vha, rval); 1170 1171qla24xx_fw_dump_failed: 1172 if (!hardware_locked) 1173 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1174} 1175 1176void 1177qla25xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) 1178{ 1179 int rval; 1180 uint32_t cnt; 1181 uint32_t risc_address; 1182 struct qla_hw_data *ha = vha->hw; 1183 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1184 uint32_t __iomem *dmp_reg; 1185 uint32_t *iter_reg; 1186 uint16_t __iomem *mbx_reg; 1187 unsigned long flags; 1188 struct qla25xx_fw_dump *fw; 1189 uint32_t ext_mem_cnt; 1190 void *nxt, *nxt_chain; 1191 uint32_t *last_chain = NULL; 1192 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 1193 1194 risc_address = ext_mem_cnt = 0; 1195 flags = 0; 1196 1197 if (!hardware_locked) 1198 spin_lock_irqsave(&ha->hardware_lock, flags); 1199 1200 if (!ha->fw_dump) { 1201 ql_log(ql_log_warn, vha, 0xd008, 1202 "No buffer available for dump.\n"); 1203 goto qla25xx_fw_dump_failed; 1204 } 1205 1206 if (ha->fw_dumped) { 1207 ql_log(ql_log_warn, vha, 0xd009, 1208 "Firmware has been previously dumped (%p) " 1209 "-- ignoring request.\n", 1210 ha->fw_dump); 1211 goto qla25xx_fw_dump_failed; 1212 } 1213 fw = &ha->fw_dump->isp.isp25; 1214 qla2xxx_prep_dump(ha, ha->fw_dump); 1215 ha->fw_dump->version = __constant_htonl(2); 1216 1217 fw->host_status = htonl(RD_REG_DWORD(®->host_status)); 1218 1219 /* Pause RISC. */ 1220 rval = qla24xx_pause_risc(reg); 1221 if (rval != QLA_SUCCESS) 1222 goto qla25xx_fw_dump_failed_0; 1223 1224 /* Host/Risc registers. */ 1225 iter_reg = fw->host_risc_reg; 1226 iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg); 1227 qla24xx_read_window(reg, 0x7010, 16, iter_reg); 1228 1229 /* PCIe registers. */ 1230 WRT_REG_DWORD(®->iobase_addr, 0x7C00); 1231 RD_REG_DWORD(®->iobase_addr); 1232 WRT_REG_DWORD(®->iobase_window, 0x01); 1233 dmp_reg = ®->iobase_c4; 1234 fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++)); 1235 fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++)); 1236 fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg)); 1237 fw->pcie_regs[3] = htonl(RD_REG_DWORD(®->iobase_window)); 1238 1239 WRT_REG_DWORD(®->iobase_window, 0x00); 1240 RD_REG_DWORD(®->iobase_window); 1241 1242 /* Host interface registers. */ 1243 dmp_reg = ®->flash_addr; 1244 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) 1245 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); 1246 1247 /* Disable interrupts. */ 1248 WRT_REG_DWORD(®->ictrl, 0); 1249 RD_REG_DWORD(®->ictrl); 1250 1251 /* Shadow registers. */ 1252 WRT_REG_DWORD(®->iobase_addr, 0x0F70); 1253 RD_REG_DWORD(®->iobase_addr); 1254 WRT_REG_DWORD(®->iobase_select, 0xB0000000); 1255 fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1256 1257 WRT_REG_DWORD(®->iobase_select, 0xB0100000); 1258 fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1259 1260 WRT_REG_DWORD(®->iobase_select, 0xB0200000); 1261 fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1262 1263 WRT_REG_DWORD(®->iobase_select, 0xB0300000); 1264 fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1265 1266 WRT_REG_DWORD(®->iobase_select, 0xB0400000); 1267 fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1268 1269 WRT_REG_DWORD(®->iobase_select, 0xB0500000); 1270 fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1271 1272 WRT_REG_DWORD(®->iobase_select, 0xB0600000); 1273 fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1274 1275 WRT_REG_DWORD(®->iobase_select, 0xB0700000); 1276 fw->shadow_reg[7] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1277 1278 WRT_REG_DWORD(®->iobase_select, 0xB0800000); 1279 fw->shadow_reg[8] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1280 1281 WRT_REG_DWORD(®->iobase_select, 0xB0900000); 1282 fw->shadow_reg[9] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1283 1284 WRT_REG_DWORD(®->iobase_select, 0xB0A00000); 1285 fw->shadow_reg[10] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1286 1287 /* RISC I/O register. */ 1288 WRT_REG_DWORD(®->iobase_addr, 0x0010); 1289 fw->risc_io_reg = htonl(RD_REG_DWORD(®->iobase_window)); 1290 1291 /* Mailbox registers. */ 1292 mbx_reg = ®->mailbox0; 1293 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) 1294 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++)); 1295 1296 /* Transfer sequence registers. */ 1297 iter_reg = fw->xseq_gp_reg; 1298 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg); 1299 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg); 1300 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg); 1301 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg); 1302 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg); 1303 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg); 1304 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg); 1305 qla24xx_read_window(reg, 0xBF70, 16, iter_reg); 1306 1307 iter_reg = fw->xseq_0_reg; 1308 iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg); 1309 iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg); 1310 qla24xx_read_window(reg, 0xBFE0, 16, iter_reg); 1311 1312 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg); 1313 1314 /* Receive sequence registers. */ 1315 iter_reg = fw->rseq_gp_reg; 1316 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg); 1317 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg); 1318 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg); 1319 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg); 1320 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg); 1321 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg); 1322 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg); 1323 qla24xx_read_window(reg, 0xFF70, 16, iter_reg); 1324 1325 iter_reg = fw->rseq_0_reg; 1326 iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg); 1327 qla24xx_read_window(reg, 0xFFD0, 16, iter_reg); 1328 1329 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg); 1330 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg); 1331 1332 /* Auxiliary sequence registers. */ 1333 iter_reg = fw->aseq_gp_reg; 1334 iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg); 1335 iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg); 1336 iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg); 1337 iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg); 1338 iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg); 1339 iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg); 1340 iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg); 1341 qla24xx_read_window(reg, 0xB070, 16, iter_reg); 1342 1343 iter_reg = fw->aseq_0_reg; 1344 iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg); 1345 qla24xx_read_window(reg, 0xB0D0, 16, iter_reg); 1346 1347 qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg); 1348 qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg); 1349 1350 /* Command DMA registers. */ 1351 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg); 1352 1353 /* Queues. */ 1354 iter_reg = fw->req0_dma_reg; 1355 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg); 1356 dmp_reg = ®->iobase_q; 1357 for (cnt = 0; cnt < 7; cnt++) 1358 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1359 1360 iter_reg = fw->resp0_dma_reg; 1361 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg); 1362 dmp_reg = ®->iobase_q; 1363 for (cnt = 0; cnt < 7; cnt++) 1364 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1365 1366 iter_reg = fw->req1_dma_reg; 1367 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg); 1368 dmp_reg = ®->iobase_q; 1369 for (cnt = 0; cnt < 7; cnt++) 1370 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1371 1372 /* Transmit DMA registers. */ 1373 iter_reg = fw->xmt0_dma_reg; 1374 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg); 1375 qla24xx_read_window(reg, 0x7610, 16, iter_reg); 1376 1377 iter_reg = fw->xmt1_dma_reg; 1378 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg); 1379 qla24xx_read_window(reg, 0x7630, 16, iter_reg); 1380 1381 iter_reg = fw->xmt2_dma_reg; 1382 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg); 1383 qla24xx_read_window(reg, 0x7650, 16, iter_reg); 1384 1385 iter_reg = fw->xmt3_dma_reg; 1386 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg); 1387 qla24xx_read_window(reg, 0x7670, 16, iter_reg); 1388 1389 iter_reg = fw->xmt4_dma_reg; 1390 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg); 1391 qla24xx_read_window(reg, 0x7690, 16, iter_reg); 1392 1393 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg); 1394 1395 /* Receive DMA registers. */ 1396 iter_reg = fw->rcvt0_data_dma_reg; 1397 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg); 1398 qla24xx_read_window(reg, 0x7710, 16, iter_reg); 1399 1400 iter_reg = fw->rcvt1_data_dma_reg; 1401 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg); 1402 qla24xx_read_window(reg, 0x7730, 16, iter_reg); 1403 1404 /* RISC registers. */ 1405 iter_reg = fw->risc_gp_reg; 1406 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg); 1407 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg); 1408 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg); 1409 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg); 1410 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg); 1411 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg); 1412 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg); 1413 qla24xx_read_window(reg, 0x0F70, 16, iter_reg); 1414 1415 /* Local memory controller registers. */ 1416 iter_reg = fw->lmc_reg; 1417 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg); 1418 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg); 1419 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg); 1420 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg); 1421 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg); 1422 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg); 1423 iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg); 1424 qla24xx_read_window(reg, 0x3070, 16, iter_reg); 1425 1426 /* Fibre Protocol Module registers. */ 1427 iter_reg = fw->fpm_hdw_reg; 1428 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg); 1429 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg); 1430 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg); 1431 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg); 1432 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg); 1433 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg); 1434 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg); 1435 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg); 1436 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg); 1437 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg); 1438 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg); 1439 qla24xx_read_window(reg, 0x40B0, 16, iter_reg); 1440 1441 /* Frame Buffer registers. */ 1442 iter_reg = fw->fb_hdw_reg; 1443 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg); 1444 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg); 1445 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg); 1446 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg); 1447 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg); 1448 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg); 1449 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg); 1450 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg); 1451 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg); 1452 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg); 1453 iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg); 1454 qla24xx_read_window(reg, 0x6F00, 16, iter_reg); 1455 1456 /* Multi queue registers */ 1457 nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset, 1458 &last_chain); 1459 1460 rval = qla24xx_soft_reset(ha); 1461 if (rval != QLA_SUCCESS) 1462 goto qla25xx_fw_dump_failed_0; 1463 1464 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram), 1465 &nxt); 1466 if (rval != QLA_SUCCESS) 1467 goto qla25xx_fw_dump_failed_0; 1468 1469 nxt = qla2xxx_copy_queues(ha, nxt); 1470 1471 nxt = qla24xx_copy_eft(ha, nxt); 1472 1473 /* Chain entries -- started with MQ. */ 1474 nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain); 1475 nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain); 1476 nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain); 1477 if (last_chain) { 1478 ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT); 1479 *last_chain |= __constant_htonl(DUMP_CHAIN_LAST); 1480 } 1481 1482 /* Adjust valid length. */ 1483 ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump); 1484 1485qla25xx_fw_dump_failed_0: 1486 qla2xxx_dump_post_process(base_vha, rval); 1487 1488qla25xx_fw_dump_failed: 1489 if (!hardware_locked) 1490 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1491} 1492 1493void 1494qla81xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) 1495{ 1496 int rval; 1497 uint32_t cnt; 1498 uint32_t risc_address; 1499 struct qla_hw_data *ha = vha->hw; 1500 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1501 uint32_t __iomem *dmp_reg; 1502 uint32_t *iter_reg; 1503 uint16_t __iomem *mbx_reg; 1504 unsigned long flags; 1505 struct qla81xx_fw_dump *fw; 1506 uint32_t ext_mem_cnt; 1507 void *nxt, *nxt_chain; 1508 uint32_t *last_chain = NULL; 1509 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 1510 1511 risc_address = ext_mem_cnt = 0; 1512 flags = 0; 1513 1514 if (!hardware_locked) 1515 spin_lock_irqsave(&ha->hardware_lock, flags); 1516 1517 if (!ha->fw_dump) { 1518 ql_log(ql_log_warn, vha, 0xd00a, 1519 "No buffer available for dump.\n"); 1520 goto qla81xx_fw_dump_failed; 1521 } 1522 1523 if (ha->fw_dumped) { 1524 ql_log(ql_log_warn, vha, 0xd00b, 1525 "Firmware has been previously dumped (%p) " 1526 "-- ignoring request.\n", 1527 ha->fw_dump); 1528 goto qla81xx_fw_dump_failed; 1529 } 1530 fw = &ha->fw_dump->isp.isp81; 1531 qla2xxx_prep_dump(ha, ha->fw_dump); 1532 1533 fw->host_status = htonl(RD_REG_DWORD(®->host_status)); 1534 1535 /* Pause RISC. */ 1536 rval = qla24xx_pause_risc(reg); 1537 if (rval != QLA_SUCCESS) 1538 goto qla81xx_fw_dump_failed_0; 1539 1540 /* Host/Risc registers. */ 1541 iter_reg = fw->host_risc_reg; 1542 iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg); 1543 qla24xx_read_window(reg, 0x7010, 16, iter_reg); 1544 1545 /* PCIe registers. */ 1546 WRT_REG_DWORD(®->iobase_addr, 0x7C00); 1547 RD_REG_DWORD(®->iobase_addr); 1548 WRT_REG_DWORD(®->iobase_window, 0x01); 1549 dmp_reg = ®->iobase_c4; 1550 fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++)); 1551 fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++)); 1552 fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg)); 1553 fw->pcie_regs[3] = htonl(RD_REG_DWORD(®->iobase_window)); 1554 1555 WRT_REG_DWORD(®->iobase_window, 0x00); 1556 RD_REG_DWORD(®->iobase_window); 1557 1558 /* Host interface registers. */ 1559 dmp_reg = ®->flash_addr; 1560 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) 1561 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); 1562 1563 /* Disable interrupts. */ 1564 WRT_REG_DWORD(®->ictrl, 0); 1565 RD_REG_DWORD(®->ictrl); 1566 1567 /* Shadow registers. */ 1568 WRT_REG_DWORD(®->iobase_addr, 0x0F70); 1569 RD_REG_DWORD(®->iobase_addr); 1570 WRT_REG_DWORD(®->iobase_select, 0xB0000000); 1571 fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1572 1573 WRT_REG_DWORD(®->iobase_select, 0xB0100000); 1574 fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1575 1576 WRT_REG_DWORD(®->iobase_select, 0xB0200000); 1577 fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1578 1579 WRT_REG_DWORD(®->iobase_select, 0xB0300000); 1580 fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1581 1582 WRT_REG_DWORD(®->iobase_select, 0xB0400000); 1583 fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1584 1585 WRT_REG_DWORD(®->iobase_select, 0xB0500000); 1586 fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1587 1588 WRT_REG_DWORD(®->iobase_select, 0xB0600000); 1589 fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1590 1591 WRT_REG_DWORD(®->iobase_select, 0xB0700000); 1592 fw->shadow_reg[7] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1593 1594 WRT_REG_DWORD(®->iobase_select, 0xB0800000); 1595 fw->shadow_reg[8] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1596 1597 WRT_REG_DWORD(®->iobase_select, 0xB0900000); 1598 fw->shadow_reg[9] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1599 1600 WRT_REG_DWORD(®->iobase_select, 0xB0A00000); 1601 fw->shadow_reg[10] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1602 1603 /* RISC I/O register. */ 1604 WRT_REG_DWORD(®->iobase_addr, 0x0010); 1605 fw->risc_io_reg = htonl(RD_REG_DWORD(®->iobase_window)); 1606 1607 /* Mailbox registers. */ 1608 mbx_reg = ®->mailbox0; 1609 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) 1610 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++)); 1611 1612 /* Transfer sequence registers. */ 1613 iter_reg = fw->xseq_gp_reg; 1614 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg); 1615 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg); 1616 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg); 1617 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg); 1618 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg); 1619 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg); 1620 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg); 1621 qla24xx_read_window(reg, 0xBF70, 16, iter_reg); 1622 1623 iter_reg = fw->xseq_0_reg; 1624 iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg); 1625 iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg); 1626 qla24xx_read_window(reg, 0xBFE0, 16, iter_reg); 1627 1628 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg); 1629 1630 /* Receive sequence registers. */ 1631 iter_reg = fw->rseq_gp_reg; 1632 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg); 1633 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg); 1634 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg); 1635 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg); 1636 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg); 1637 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg); 1638 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg); 1639 qla24xx_read_window(reg, 0xFF70, 16, iter_reg); 1640 1641 iter_reg = fw->rseq_0_reg; 1642 iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg); 1643 qla24xx_read_window(reg, 0xFFD0, 16, iter_reg); 1644 1645 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg); 1646 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg); 1647 1648 /* Auxiliary sequence registers. */ 1649 iter_reg = fw->aseq_gp_reg; 1650 iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg); 1651 iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg); 1652 iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg); 1653 iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg); 1654 iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg); 1655 iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg); 1656 iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg); 1657 qla24xx_read_window(reg, 0xB070, 16, iter_reg); 1658 1659 iter_reg = fw->aseq_0_reg; 1660 iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg); 1661 qla24xx_read_window(reg, 0xB0D0, 16, iter_reg); 1662 1663 qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg); 1664 qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg); 1665 1666 /* Command DMA registers. */ 1667 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg); 1668 1669 /* Queues. */ 1670 iter_reg = fw->req0_dma_reg; 1671 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg); 1672 dmp_reg = ®->iobase_q; 1673 for (cnt = 0; cnt < 7; cnt++) 1674 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1675 1676 iter_reg = fw->resp0_dma_reg; 1677 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg); 1678 dmp_reg = ®->iobase_q; 1679 for (cnt = 0; cnt < 7; cnt++) 1680 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1681 1682 iter_reg = fw->req1_dma_reg; 1683 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg); 1684 dmp_reg = ®->iobase_q; 1685 for (cnt = 0; cnt < 7; cnt++) 1686 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 1687 1688 /* Transmit DMA registers. */ 1689 iter_reg = fw->xmt0_dma_reg; 1690 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg); 1691 qla24xx_read_window(reg, 0x7610, 16, iter_reg); 1692 1693 iter_reg = fw->xmt1_dma_reg; 1694 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg); 1695 qla24xx_read_window(reg, 0x7630, 16, iter_reg); 1696 1697 iter_reg = fw->xmt2_dma_reg; 1698 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg); 1699 qla24xx_read_window(reg, 0x7650, 16, iter_reg); 1700 1701 iter_reg = fw->xmt3_dma_reg; 1702 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg); 1703 qla24xx_read_window(reg, 0x7670, 16, iter_reg); 1704 1705 iter_reg = fw->xmt4_dma_reg; 1706 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg); 1707 qla24xx_read_window(reg, 0x7690, 16, iter_reg); 1708 1709 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg); 1710 1711 /* Receive DMA registers. */ 1712 iter_reg = fw->rcvt0_data_dma_reg; 1713 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg); 1714 qla24xx_read_window(reg, 0x7710, 16, iter_reg); 1715 1716 iter_reg = fw->rcvt1_data_dma_reg; 1717 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg); 1718 qla24xx_read_window(reg, 0x7730, 16, iter_reg); 1719 1720 /* RISC registers. */ 1721 iter_reg = fw->risc_gp_reg; 1722 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg); 1723 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg); 1724 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg); 1725 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg); 1726 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg); 1727 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg); 1728 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg); 1729 qla24xx_read_window(reg, 0x0F70, 16, iter_reg); 1730 1731 /* Local memory controller registers. */ 1732 iter_reg = fw->lmc_reg; 1733 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg); 1734 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg); 1735 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg); 1736 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg); 1737 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg); 1738 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg); 1739 iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg); 1740 qla24xx_read_window(reg, 0x3070, 16, iter_reg); 1741 1742 /* Fibre Protocol Module registers. */ 1743 iter_reg = fw->fpm_hdw_reg; 1744 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg); 1745 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg); 1746 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg); 1747 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg); 1748 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg); 1749 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg); 1750 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg); 1751 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg); 1752 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg); 1753 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg); 1754 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg); 1755 iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg); 1756 iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg); 1757 qla24xx_read_window(reg, 0x40D0, 16, iter_reg); 1758 1759 /* Frame Buffer registers. */ 1760 iter_reg = fw->fb_hdw_reg; 1761 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg); 1762 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg); 1763 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg); 1764 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg); 1765 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg); 1766 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg); 1767 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg); 1768 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg); 1769 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg); 1770 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg); 1771 iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg); 1772 iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg); 1773 qla24xx_read_window(reg, 0x6F00, 16, iter_reg); 1774 1775 /* Multi queue registers */ 1776 nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset, 1777 &last_chain); 1778 1779 rval = qla24xx_soft_reset(ha); 1780 if (rval != QLA_SUCCESS) 1781 goto qla81xx_fw_dump_failed_0; 1782 1783 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram), 1784 &nxt); 1785 if (rval != QLA_SUCCESS) 1786 goto qla81xx_fw_dump_failed_0; 1787 1788 nxt = qla2xxx_copy_queues(ha, nxt); 1789 1790 nxt = qla24xx_copy_eft(ha, nxt); 1791 1792 /* Chain entries -- started with MQ. */ 1793 nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain); 1794 nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain); 1795 nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain); 1796 if (last_chain) { 1797 ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT); 1798 *last_chain |= __constant_htonl(DUMP_CHAIN_LAST); 1799 } 1800 1801 /* Adjust valid length. */ 1802 ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump); 1803 1804qla81xx_fw_dump_failed_0: 1805 qla2xxx_dump_post_process(base_vha, rval); 1806 1807qla81xx_fw_dump_failed: 1808 if (!hardware_locked) 1809 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1810} 1811 1812void 1813qla83xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) 1814{ 1815 int rval; 1816 uint32_t cnt, reg_data; 1817 uint32_t risc_address; 1818 struct qla_hw_data *ha = vha->hw; 1819 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1820 uint32_t __iomem *dmp_reg; 1821 uint32_t *iter_reg; 1822 uint16_t __iomem *mbx_reg; 1823 unsigned long flags; 1824 struct qla83xx_fw_dump *fw; 1825 uint32_t ext_mem_cnt; 1826 void *nxt, *nxt_chain; 1827 uint32_t *last_chain = NULL; 1828 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 1829 1830 risc_address = ext_mem_cnt = 0; 1831 flags = 0; 1832 1833 if (!hardware_locked) 1834 spin_lock_irqsave(&ha->hardware_lock, flags); 1835 1836 if (!ha->fw_dump) { 1837 ql_log(ql_log_warn, vha, 0xd00c, 1838 "No buffer available for dump!!!\n"); 1839 goto qla83xx_fw_dump_failed; 1840 } 1841 1842 if (ha->fw_dumped) { 1843 ql_log(ql_log_warn, vha, 0xd00d, 1844 "Firmware has been previously dumped (%p) -- ignoring " 1845 "request...\n", ha->fw_dump); 1846 goto qla83xx_fw_dump_failed; 1847 } 1848 fw = &ha->fw_dump->isp.isp83; 1849 qla2xxx_prep_dump(ha, ha->fw_dump); 1850 1851 fw->host_status = htonl(RD_REG_DWORD(®->host_status)); 1852 1853 /* Pause RISC. */ 1854 rval = qla24xx_pause_risc(reg); 1855 if (rval != QLA_SUCCESS) 1856 goto qla83xx_fw_dump_failed_0; 1857 1858 WRT_REG_DWORD(®->iobase_addr, 0x6000); 1859 dmp_reg = ®->iobase_window; 1860 reg_data = RD_REG_DWORD(dmp_reg); 1861 WRT_REG_DWORD(dmp_reg, 0); 1862 1863 dmp_reg = ®->unused_4_1[0]; 1864 reg_data = RD_REG_DWORD(dmp_reg); 1865 WRT_REG_DWORD(dmp_reg, 0); 1866 1867 WRT_REG_DWORD(®->iobase_addr, 0x6010); 1868 dmp_reg = ®->unused_4_1[2]; 1869 reg_data = RD_REG_DWORD(dmp_reg); 1870 WRT_REG_DWORD(dmp_reg, 0); 1871 1872 /* select PCR and disable ecc checking and correction */ 1873 WRT_REG_DWORD(®->iobase_addr, 0x0F70); 1874 RD_REG_DWORD(®->iobase_addr); 1875 WRT_REG_DWORD(®->iobase_select, 0x60000000); /* write to F0h = PCR */ 1876 1877 /* Host/Risc registers. */ 1878 iter_reg = fw->host_risc_reg; 1879 iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg); 1880 iter_reg = qla24xx_read_window(reg, 0x7010, 16, iter_reg); 1881 qla24xx_read_window(reg, 0x7040, 16, iter_reg); 1882 1883 /* PCIe registers. */ 1884 WRT_REG_DWORD(®->iobase_addr, 0x7C00); 1885 RD_REG_DWORD(®->iobase_addr); 1886 WRT_REG_DWORD(®->iobase_window, 0x01); 1887 dmp_reg = ®->iobase_c4; 1888 fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++)); 1889 fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++)); 1890 fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg)); 1891 fw->pcie_regs[3] = htonl(RD_REG_DWORD(®->iobase_window)); 1892 1893 WRT_REG_DWORD(®->iobase_window, 0x00); 1894 RD_REG_DWORD(®->iobase_window); 1895 1896 /* Host interface registers. */ 1897 dmp_reg = ®->flash_addr; 1898 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) 1899 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); 1900 1901 /* Disable interrupts. */ 1902 WRT_REG_DWORD(®->ictrl, 0); 1903 RD_REG_DWORD(®->ictrl); 1904 1905 /* Shadow registers. */ 1906 WRT_REG_DWORD(®->iobase_addr, 0x0F70); 1907 RD_REG_DWORD(®->iobase_addr); 1908 WRT_REG_DWORD(®->iobase_select, 0xB0000000); 1909 fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1910 1911 WRT_REG_DWORD(®->iobase_select, 0xB0100000); 1912 fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1913 1914 WRT_REG_DWORD(®->iobase_select, 0xB0200000); 1915 fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1916 1917 WRT_REG_DWORD(®->iobase_select, 0xB0300000); 1918 fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1919 1920 WRT_REG_DWORD(®->iobase_select, 0xB0400000); 1921 fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1922 1923 WRT_REG_DWORD(®->iobase_select, 0xB0500000); 1924 fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1925 1926 WRT_REG_DWORD(®->iobase_select, 0xB0600000); 1927 fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1928 1929 WRT_REG_DWORD(®->iobase_select, 0xB0700000); 1930 fw->shadow_reg[7] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1931 1932 WRT_REG_DWORD(®->iobase_select, 0xB0800000); 1933 fw->shadow_reg[8] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1934 1935 WRT_REG_DWORD(®->iobase_select, 0xB0900000); 1936 fw->shadow_reg[9] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1937 1938 WRT_REG_DWORD(®->iobase_select, 0xB0A00000); 1939 fw->shadow_reg[10] = htonl(RD_REG_DWORD(®->iobase_sdata)); 1940 1941 /* RISC I/O register. */ 1942 WRT_REG_DWORD(®->iobase_addr, 0x0010); 1943 fw->risc_io_reg = htonl(RD_REG_DWORD(®->iobase_window)); 1944 1945 /* Mailbox registers. */ 1946 mbx_reg = ®->mailbox0; 1947 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) 1948 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++)); 1949 1950 /* Transfer sequence registers. */ 1951 iter_reg = fw->xseq_gp_reg; 1952 iter_reg = qla24xx_read_window(reg, 0xBE00, 16, iter_reg); 1953 iter_reg = qla24xx_read_window(reg, 0xBE10, 16, iter_reg); 1954 iter_reg = qla24xx_read_window(reg, 0xBE20, 16, iter_reg); 1955 iter_reg = qla24xx_read_window(reg, 0xBE30, 16, iter_reg); 1956 iter_reg = qla24xx_read_window(reg, 0xBE40, 16, iter_reg); 1957 iter_reg = qla24xx_read_window(reg, 0xBE50, 16, iter_reg); 1958 iter_reg = qla24xx_read_window(reg, 0xBE60, 16, iter_reg); 1959 iter_reg = qla24xx_read_window(reg, 0xBE70, 16, iter_reg); 1960 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg); 1961 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg); 1962 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg); 1963 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg); 1964 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg); 1965 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg); 1966 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg); 1967 qla24xx_read_window(reg, 0xBF70, 16, iter_reg); 1968 1969 iter_reg = fw->xseq_0_reg; 1970 iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg); 1971 iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg); 1972 qla24xx_read_window(reg, 0xBFE0, 16, iter_reg); 1973 1974 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg); 1975 1976 qla24xx_read_window(reg, 0xBEF0, 16, fw->xseq_2_reg); 1977 1978 /* Receive sequence registers. */ 1979 iter_reg = fw->rseq_gp_reg; 1980 iter_reg = qla24xx_read_window(reg, 0xFE00, 16, iter_reg); 1981 iter_reg = qla24xx_read_window(reg, 0xFE10, 16, iter_reg); 1982 iter_reg = qla24xx_read_window(reg, 0xFE20, 16, iter_reg); 1983 iter_reg = qla24xx_read_window(reg, 0xFE30, 16, iter_reg); 1984 iter_reg = qla24xx_read_window(reg, 0xFE40, 16, iter_reg); 1985 iter_reg = qla24xx_read_window(reg, 0xFE50, 16, iter_reg); 1986 iter_reg = qla24xx_read_window(reg, 0xFE60, 16, iter_reg); 1987 iter_reg = qla24xx_read_window(reg, 0xFE70, 16, iter_reg); 1988 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg); 1989 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg); 1990 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg); 1991 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg); 1992 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg); 1993 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg); 1994 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg); 1995 qla24xx_read_window(reg, 0xFF70, 16, iter_reg); 1996 1997 iter_reg = fw->rseq_0_reg; 1998 iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg); 1999 qla24xx_read_window(reg, 0xFFD0, 16, iter_reg); 2000 2001 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg); 2002 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg); 2003 qla24xx_read_window(reg, 0xFEF0, 16, fw->rseq_3_reg); 2004 2005 /* Auxiliary sequence registers. */ 2006 iter_reg = fw->aseq_gp_reg; 2007 iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg); 2008 iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg); 2009 iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg); 2010 iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg); 2011 iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg); 2012 iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg); 2013 iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg); 2014 iter_reg = qla24xx_read_window(reg, 0xB070, 16, iter_reg); 2015 iter_reg = qla24xx_read_window(reg, 0xB100, 16, iter_reg); 2016 iter_reg = qla24xx_read_window(reg, 0xB110, 16, iter_reg); 2017 iter_reg = qla24xx_read_window(reg, 0xB120, 16, iter_reg); 2018 iter_reg = qla24xx_read_window(reg, 0xB130, 16, iter_reg); 2019 iter_reg = qla24xx_read_window(reg, 0xB140, 16, iter_reg); 2020 iter_reg = qla24xx_read_window(reg, 0xB150, 16, iter_reg); 2021 iter_reg = qla24xx_read_window(reg, 0xB160, 16, iter_reg); 2022 qla24xx_read_window(reg, 0xB170, 16, iter_reg); 2023 2024 iter_reg = fw->aseq_0_reg; 2025 iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg); 2026 qla24xx_read_window(reg, 0xB0D0, 16, iter_reg); 2027 2028 qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg); 2029 qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg); 2030 qla24xx_read_window(reg, 0xB1F0, 16, fw->aseq_3_reg); 2031 2032 /* Command DMA registers. */ 2033 iter_reg = fw->cmd_dma_reg; 2034 iter_reg = qla24xx_read_window(reg, 0x7100, 16, iter_reg); 2035 iter_reg = qla24xx_read_window(reg, 0x7120, 16, iter_reg); 2036 iter_reg = qla24xx_read_window(reg, 0x7130, 16, iter_reg); 2037 qla24xx_read_window(reg, 0x71F0, 16, iter_reg); 2038 2039 /* Queues. */ 2040 iter_reg = fw->req0_dma_reg; 2041 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg); 2042 dmp_reg = ®->iobase_q; 2043 for (cnt = 0; cnt < 7; cnt++) 2044 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 2045 2046 iter_reg = fw->resp0_dma_reg; 2047 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg); 2048 dmp_reg = ®->iobase_q; 2049 for (cnt = 0; cnt < 7; cnt++) 2050 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 2051 2052 iter_reg = fw->req1_dma_reg; 2053 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg); 2054 dmp_reg = ®->iobase_q; 2055 for (cnt = 0; cnt < 7; cnt++) 2056 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); 2057 2058 /* Transmit DMA registers. */ 2059 iter_reg = fw->xmt0_dma_reg; 2060 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg); 2061 qla24xx_read_window(reg, 0x7610, 16, iter_reg); 2062 2063 iter_reg = fw->xmt1_dma_reg; 2064 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg); 2065 qla24xx_read_window(reg, 0x7630, 16, iter_reg); 2066 2067 iter_reg = fw->xmt2_dma_reg; 2068 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg); 2069 qla24xx_read_window(reg, 0x7650, 16, iter_reg); 2070 2071 iter_reg = fw->xmt3_dma_reg; 2072 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg); 2073 qla24xx_read_window(reg, 0x7670, 16, iter_reg); 2074 2075 iter_reg = fw->xmt4_dma_reg; 2076 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg); 2077 qla24xx_read_window(reg, 0x7690, 16, iter_reg); 2078 2079 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg); 2080 2081 /* Receive DMA registers. */ 2082 iter_reg = fw->rcvt0_data_dma_reg; 2083 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg); 2084 qla24xx_read_window(reg, 0x7710, 16, iter_reg); 2085 2086 iter_reg = fw->rcvt1_data_dma_reg; 2087 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg); 2088 qla24xx_read_window(reg, 0x7730, 16, iter_reg); 2089 2090 /* RISC registers. */ 2091 iter_reg = fw->risc_gp_reg; 2092 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg); 2093 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg); 2094 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg); 2095 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg); 2096 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg); 2097 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg); 2098 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg); 2099 qla24xx_read_window(reg, 0x0F70, 16, iter_reg); 2100 2101 /* Local memory controller registers. */ 2102 iter_reg = fw->lmc_reg; 2103 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg); 2104 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg); 2105 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg); 2106 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg); 2107 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg); 2108 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg); 2109 iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg); 2110 qla24xx_read_window(reg, 0x3070, 16, iter_reg); 2111 2112 /* Fibre Protocol Module registers. */ 2113 iter_reg = fw->fpm_hdw_reg; 2114 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg); 2115 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg); 2116 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg); 2117 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg); 2118 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg); 2119 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg); 2120 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg); 2121 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg); 2122 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg); 2123 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg); 2124 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg); 2125 iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg); 2126 iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg); 2127 iter_reg = qla24xx_read_window(reg, 0x40D0, 16, iter_reg); 2128 iter_reg = qla24xx_read_window(reg, 0x40E0, 16, iter_reg); 2129 qla24xx_read_window(reg, 0x40F0, 16, iter_reg); 2130 2131 /* RQ0 Array registers. */ 2132 iter_reg = fw->rq0_array_reg; 2133 iter_reg = qla24xx_read_window(reg, 0x5C00, 16, iter_reg); 2134 iter_reg = qla24xx_read_window(reg, 0x5C10, 16, iter_reg); 2135 iter_reg = qla24xx_read_window(reg, 0x5C20, 16, iter_reg); 2136 iter_reg = qla24xx_read_window(reg, 0x5C30, 16, iter_reg); 2137 iter_reg = qla24xx_read_window(reg, 0x5C40, 16, iter_reg); 2138 iter_reg = qla24xx_read_window(reg, 0x5C50, 16, iter_reg); 2139 iter_reg = qla24xx_read_window(reg, 0x5C60, 16, iter_reg); 2140 iter_reg = qla24xx_read_window(reg, 0x5C70, 16, iter_reg); 2141 iter_reg = qla24xx_read_window(reg, 0x5C80, 16, iter_reg); 2142 iter_reg = qla24xx_read_window(reg, 0x5C90, 16, iter_reg); 2143 iter_reg = qla24xx_read_window(reg, 0x5CA0, 16, iter_reg); 2144 iter_reg = qla24xx_read_window(reg, 0x5CB0, 16, iter_reg); 2145 iter_reg = qla24xx_read_window(reg, 0x5CC0, 16, iter_reg); 2146 iter_reg = qla24xx_read_window(reg, 0x5CD0, 16, iter_reg); 2147 iter_reg = qla24xx_read_window(reg, 0x5CE0, 16, iter_reg); 2148 qla24xx_read_window(reg, 0x5CF0, 16, iter_reg); 2149 2150 /* RQ1 Array registers. */ 2151 iter_reg = fw->rq1_array_reg; 2152 iter_reg = qla24xx_read_window(reg, 0x5D00, 16, iter_reg); 2153 iter_reg = qla24xx_read_window(reg, 0x5D10, 16, iter_reg); 2154 iter_reg = qla24xx_read_window(reg, 0x5D20, 16, iter_reg); 2155 iter_reg = qla24xx_read_window(reg, 0x5D30, 16, iter_reg); 2156 iter_reg = qla24xx_read_window(reg, 0x5D40, 16, iter_reg); 2157 iter_reg = qla24xx_read_window(reg, 0x5D50, 16, iter_reg); 2158 iter_reg = qla24xx_read_window(reg, 0x5D60, 16, iter_reg); 2159 iter_reg = qla24xx_read_window(reg, 0x5D70, 16, iter_reg); 2160 iter_reg = qla24xx_read_window(reg, 0x5D80, 16, iter_reg); 2161 iter_reg = qla24xx_read_window(reg, 0x5D90, 16, iter_reg); 2162 iter_reg = qla24xx_read_window(reg, 0x5DA0, 16, iter_reg); 2163 iter_reg = qla24xx_read_window(reg, 0x5DB0, 16, iter_reg); 2164 iter_reg = qla24xx_read_window(reg, 0x5DC0, 16, iter_reg); 2165 iter_reg = qla24xx_read_window(reg, 0x5DD0, 16, iter_reg); 2166 iter_reg = qla24xx_read_window(reg, 0x5DE0, 16, iter_reg); 2167 qla24xx_read_window(reg, 0x5DF0, 16, iter_reg); 2168 2169 /* RP0 Array registers. */ 2170 iter_reg = fw->rp0_array_reg; 2171 iter_reg = qla24xx_read_window(reg, 0x5E00, 16, iter_reg); 2172 iter_reg = qla24xx_read_window(reg, 0x5E10, 16, iter_reg); 2173 iter_reg = qla24xx_read_window(reg, 0x5E20, 16, iter_reg); 2174 iter_reg = qla24xx_read_window(reg, 0x5E30, 16, iter_reg); 2175 iter_reg = qla24xx_read_window(reg, 0x5E40, 16, iter_reg); 2176 iter_reg = qla24xx_read_window(reg, 0x5E50, 16, iter_reg); 2177 iter_reg = qla24xx_read_window(reg, 0x5E60, 16, iter_reg); 2178 iter_reg = qla24xx_read_window(reg, 0x5E70, 16, iter_reg); 2179 iter_reg = qla24xx_read_window(reg, 0x5E80, 16, iter_reg); 2180 iter_reg = qla24xx_read_window(reg, 0x5E90, 16, iter_reg); 2181 iter_reg = qla24xx_read_window(reg, 0x5EA0, 16, iter_reg); 2182 iter_reg = qla24xx_read_window(reg, 0x5EB0, 16, iter_reg); 2183 iter_reg = qla24xx_read_window(reg, 0x5EC0, 16, iter_reg); 2184 iter_reg = qla24xx_read_window(reg, 0x5ED0, 16, iter_reg); 2185 iter_reg = qla24xx_read_window(reg, 0x5EE0, 16, iter_reg); 2186 qla24xx_read_window(reg, 0x5EF0, 16, iter_reg); 2187 2188 /* RP1 Array registers. */ 2189 iter_reg = fw->rp1_array_reg; 2190 iter_reg = qla24xx_read_window(reg, 0x5F00, 16, iter_reg); 2191 iter_reg = qla24xx_read_window(reg, 0x5F10, 16, iter_reg); 2192 iter_reg = qla24xx_read_window(reg, 0x5F20, 16, iter_reg); 2193 iter_reg = qla24xx_read_window(reg, 0x5F30, 16, iter_reg); 2194 iter_reg = qla24xx_read_window(reg, 0x5F40, 16, iter_reg); 2195 iter_reg = qla24xx_read_window(reg, 0x5F50, 16, iter_reg); 2196 iter_reg = qla24xx_read_window(reg, 0x5F60, 16, iter_reg); 2197 iter_reg = qla24xx_read_window(reg, 0x5F70, 16, iter_reg); 2198 iter_reg = qla24xx_read_window(reg, 0x5F80, 16, iter_reg); 2199 iter_reg = qla24xx_read_window(reg, 0x5F90, 16, iter_reg); 2200 iter_reg = qla24xx_read_window(reg, 0x5FA0, 16, iter_reg); 2201 iter_reg = qla24xx_read_window(reg, 0x5FB0, 16, iter_reg); 2202 iter_reg = qla24xx_read_window(reg, 0x5FC0, 16, iter_reg); 2203 iter_reg = qla24xx_read_window(reg, 0x5FD0, 16, iter_reg); 2204 iter_reg = qla24xx_read_window(reg, 0x5FE0, 16, iter_reg); 2205 qla24xx_read_window(reg, 0x5FF0, 16, iter_reg); 2206 2207 iter_reg = fw->at0_array_reg; 2208 iter_reg = qla24xx_read_window(reg, 0x7080, 16, iter_reg); 2209 iter_reg = qla24xx_read_window(reg, 0x7090, 16, iter_reg); 2210 iter_reg = qla24xx_read_window(reg, 0x70A0, 16, iter_reg); 2211 iter_reg = qla24xx_read_window(reg, 0x70B0, 16, iter_reg); 2212 iter_reg = qla24xx_read_window(reg, 0x70C0, 16, iter_reg); 2213 iter_reg = qla24xx_read_window(reg, 0x70D0, 16, iter_reg); 2214 iter_reg = qla24xx_read_window(reg, 0x70E0, 16, iter_reg); 2215 qla24xx_read_window(reg, 0x70F0, 16, iter_reg); 2216 2217 /* I/O Queue Control registers. */ 2218 qla24xx_read_window(reg, 0x7800, 16, fw->queue_control_reg); 2219 2220 /* Frame Buffer registers. */ 2221 iter_reg = fw->fb_hdw_reg; 2222 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg); 2223 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg); 2224 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg); 2225 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg); 2226 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg); 2227 iter_reg = qla24xx_read_window(reg, 0x6060, 16, iter_reg); 2228 iter_reg = qla24xx_read_window(reg, 0x6070, 16, iter_reg); 2229 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg); 2230 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg); 2231 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg); 2232 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg); 2233 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg); 2234 iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg); 2235 iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg); 2236 iter_reg = qla24xx_read_window(reg, 0x6530, 16, iter_reg); 2237 iter_reg = qla24xx_read_window(reg, 0x6540, 16, iter_reg); 2238 iter_reg = qla24xx_read_window(reg, 0x6550, 16, iter_reg); 2239 iter_reg = qla24xx_read_window(reg, 0x6560, 16, iter_reg); 2240 iter_reg = qla24xx_read_window(reg, 0x6570, 16, iter_reg); 2241 iter_reg = qla24xx_read_window(reg, 0x6580, 16, iter_reg); 2242 iter_reg = qla24xx_read_window(reg, 0x6590, 16, iter_reg); 2243 iter_reg = qla24xx_read_window(reg, 0x65A0, 16, iter_reg); 2244 iter_reg = qla24xx_read_window(reg, 0x65B0, 16, iter_reg); 2245 iter_reg = qla24xx_read_window(reg, 0x65C0, 16, iter_reg); 2246 iter_reg = qla24xx_read_window(reg, 0x65D0, 16, iter_reg); 2247 iter_reg = qla24xx_read_window(reg, 0x65E0, 16, iter_reg); 2248 qla24xx_read_window(reg, 0x6F00, 16, iter_reg); 2249 2250 /* Multi queue registers */ 2251 nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset, 2252 &last_chain); 2253 2254 rval = qla24xx_soft_reset(ha); 2255 if (rval != QLA_SUCCESS) { 2256 ql_log(ql_log_warn, vha, 0xd00e, 2257 "SOFT RESET FAILED, forcing continuation of dump!!!\n"); 2258 rval = QLA_SUCCESS; 2259 2260 ql_log(ql_log_warn, vha, 0xd00f, "try a bigger hammer!!!\n"); 2261 2262 WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_RESET); 2263 RD_REG_DWORD(®->hccr); 2264 2265 WRT_REG_DWORD(®->hccr, HCCRX_REL_RISC_PAUSE); 2266 RD_REG_DWORD(®->hccr); 2267 2268 WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_RESET); 2269 RD_REG_DWORD(®->hccr); 2270 2271 for (cnt = 30000; cnt && (RD_REG_WORD(®->mailbox0)); cnt--) 2272 udelay(5); 2273 2274 if (!cnt) { 2275 nxt = fw->code_ram; 2276 nxt += sizeof(fw->code_ram); 2277 nxt += (ha->fw_memory_size - 0x100000 + 1); 2278 goto copy_queue; 2279 } else 2280 ql_log(ql_log_warn, vha, 0xd010, 2281 "bigger hammer success?\n"); 2282 } 2283 2284 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram), 2285 &nxt); 2286 if (rval != QLA_SUCCESS) 2287 goto qla83xx_fw_dump_failed_0; 2288 2289copy_queue: 2290 nxt = qla2xxx_copy_queues(ha, nxt); 2291 2292 nxt = qla24xx_copy_eft(ha, nxt); 2293 2294 /* Chain entries -- started with MQ. */ 2295 nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain); 2296 nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain); 2297 nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain); 2298 if (last_chain) { 2299 ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT); 2300 *last_chain |= __constant_htonl(DUMP_CHAIN_LAST); 2301 } 2302 2303 /* Adjust valid length. */ 2304 ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump); 2305 2306qla83xx_fw_dump_failed_0: 2307 qla2xxx_dump_post_process(base_vha, rval); 2308 2309qla83xx_fw_dump_failed: 2310 if (!hardware_locked) 2311 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2312} 2313 2314/****************************************************************************/ 2315/* Driver Debug Functions. */ 2316/****************************************************************************/ 2317 2318static inline int 2319ql_mask_match(uint32_t level) 2320{ 2321 if (ql2xextended_error_logging == 1) 2322 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK; 2323 return (level & ql2xextended_error_logging) == level; 2324} 2325 2326/* 2327 * This function is for formatting and logging debug information. 2328 * It is to be used when vha is available. It formats the message 2329 * and logs it to the messages file. 2330 * parameters: 2331 * level: The level of the debug messages to be printed. 2332 * If ql2xextended_error_logging value is correctly set, 2333 * this message will appear in the messages file. 2334 * vha: Pointer to the scsi_qla_host_t. 2335 * id: This is a unique identifier for the level. It identifies the 2336 * part of the code from where the message originated. 2337 * msg: The message to be displayed. 2338 */ 2339void 2340ql_dbg(uint32_t level, scsi_qla_host_t *vha, int32_t id, const char *fmt, ...) 2341{ 2342 va_list va; 2343 struct va_format vaf; 2344 2345 if (!ql_mask_match(level)) 2346 return; 2347 2348 va_start(va, fmt); 2349 2350 vaf.fmt = fmt; 2351 vaf.va = &va; 2352 2353 if (vha != NULL) { 2354 const struct pci_dev *pdev = vha->hw->pdev; 2355 /* <module-name> <pci-name> <msg-id>:<host> Message */ 2356 pr_warn("%s [%s]-%04x:%ld: %pV", 2357 QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset, 2358 vha->host_no, &vaf); 2359 } else { 2360 pr_warn("%s [%s]-%04x: : %pV", 2361 QL_MSGHDR, "0000:00:00.0", id + ql_dbg_offset, &vaf); 2362 } 2363 2364 va_end(va); 2365 2366} 2367 2368/* 2369 * This function is for formatting and logging debug information. 2370 * It is to be used when vha is not available and pci is available, 2371 * i.e., before host allocation. It formats the message and logs it 2372 * to the messages file. 2373 * parameters: 2374 * level: The level of the debug messages to be printed. 2375 * If ql2xextended_error_logging value is correctly set, 2376 * this message will appear in the messages file. 2377 * pdev: Pointer to the struct pci_dev. 2378 * id: This is a unique id for the level. It identifies the part 2379 * of the code from where the message originated. 2380 * msg: The message to be displayed. 2381 */ 2382void 2383ql_dbg_pci(uint32_t level, struct pci_dev *pdev, int32_t id, 2384 const char *fmt, ...) 2385{ 2386 va_list va; 2387 struct va_format vaf; 2388 2389 if (pdev == NULL) 2390 return; 2391 if (!ql_mask_match(level)) 2392 return; 2393 2394 va_start(va, fmt); 2395 2396 vaf.fmt = fmt; 2397 vaf.va = &va; 2398 2399 /* <module-name> <dev-name>:<msg-id> Message */ 2400 pr_warn("%s [%s]-%04x: : %pV", 2401 QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset, &vaf); 2402 2403 va_end(va); 2404} 2405 2406/* 2407 * This function is for formatting and logging log messages. 2408 * It is to be used when vha is available. It formats the message 2409 * and logs it to the messages file. All the messages will be logged 2410 * irrespective of value of ql2xextended_error_logging. 2411 * parameters: 2412 * level: The level of the log messages to be printed in the 2413 * messages file. 2414 * vha: Pointer to the scsi_qla_host_t 2415 * id: This is a unique id for the level. It identifies the 2416 * part of the code from where the message originated. 2417 * msg: The message to be displayed. 2418 */ 2419void 2420ql_log(uint32_t level, scsi_qla_host_t *vha, int32_t id, const char *fmt, ...) 2421{ 2422 va_list va; 2423 struct va_format vaf; 2424 char pbuf[128]; 2425 2426 if (level > ql_errlev) 2427 return; 2428 2429 if (vha != NULL) { 2430 const struct pci_dev *pdev = vha->hw->pdev; 2431 /* <module-name> <msg-id>:<host> Message */ 2432 snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x:%ld: ", 2433 QL_MSGHDR, dev_name(&(pdev->dev)), id, vha->host_no); 2434 } else { 2435 snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ", 2436 QL_MSGHDR, "0000:00:00.0", id); 2437 } 2438 pbuf[sizeof(pbuf) - 1] = 0; 2439 2440 va_start(va, fmt); 2441 2442 vaf.fmt = fmt; 2443 vaf.va = &va; 2444 2445 switch (level) { 2446 case ql_log_fatal: /* FATAL LOG */ 2447 pr_crit("%s%pV", pbuf, &vaf); 2448 break; 2449 case ql_log_warn: 2450 pr_err("%s%pV", pbuf, &vaf); 2451 break; 2452 case ql_log_info: 2453 pr_warn("%s%pV", pbuf, &vaf); 2454 break; 2455 default: 2456 pr_info("%s%pV", pbuf, &vaf); 2457 break; 2458 } 2459 2460 va_end(va); 2461} 2462 2463/* 2464 * This function is for formatting and logging log messages. 2465 * It is to be used when vha is not available and pci is available, 2466 * i.e., before host allocation. It formats the message and logs 2467 * it to the messages file. All the messages are logged irrespective 2468 * of the value of ql2xextended_error_logging. 2469 * parameters: 2470 * level: The level of the log messages to be printed in the 2471 * messages file. 2472 * pdev: Pointer to the struct pci_dev. 2473 * id: This is a unique id for the level. It identifies the 2474 * part of the code from where the message originated. 2475 * msg: The message to be displayed. 2476 */ 2477void 2478ql_log_pci(uint32_t level, struct pci_dev *pdev, int32_t id, 2479 const char *fmt, ...) 2480{ 2481 va_list va; 2482 struct va_format vaf; 2483 char pbuf[128]; 2484 2485 if (pdev == NULL) 2486 return; 2487 if (level > ql_errlev) 2488 return; 2489 2490 /* <module-name> <dev-name>:<msg-id> Message */ 2491 snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ", 2492 QL_MSGHDR, dev_name(&(pdev->dev)), id); 2493 pbuf[sizeof(pbuf) - 1] = 0; 2494 2495 va_start(va, fmt); 2496 2497 vaf.fmt = fmt; 2498 vaf.va = &va; 2499 2500 switch (level) { 2501 case ql_log_fatal: /* FATAL LOG */ 2502 pr_crit("%s%pV", pbuf, &vaf); 2503 break; 2504 case ql_log_warn: 2505 pr_err("%s%pV", pbuf, &vaf); 2506 break; 2507 case ql_log_info: 2508 pr_warn("%s%pV", pbuf, &vaf); 2509 break; 2510 default: 2511 pr_info("%s%pV", pbuf, &vaf); 2512 break; 2513 } 2514 2515 va_end(va); 2516} 2517 2518void 2519ql_dump_regs(uint32_t level, scsi_qla_host_t *vha, int32_t id) 2520{ 2521 int i; 2522 struct qla_hw_data *ha = vha->hw; 2523 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2524 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; 2525 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82; 2526 uint16_t __iomem *mbx_reg; 2527 2528 if (!ql_mask_match(level)) 2529 return; 2530 2531 if (IS_QLA82XX(ha)) 2532 mbx_reg = ®82->mailbox_in[0]; 2533 else if (IS_FWI2_CAPABLE(ha)) 2534 mbx_reg = ®24->mailbox0; 2535 else 2536 mbx_reg = MAILBOX_REG(ha, reg, 0); 2537 2538 ql_dbg(level, vha, id, "Mailbox registers:\n"); 2539 for (i = 0; i < 6; i++) 2540 ql_dbg(level, vha, id, 2541 "mbox[%d] 0x%04x\n", i, RD_REG_WORD(mbx_reg++)); 2542} 2543 2544 2545void 2546ql_dump_buffer(uint32_t level, scsi_qla_host_t *vha, int32_t id, 2547 uint8_t *b, uint32_t size) 2548{ 2549 uint32_t cnt; 2550 uint8_t c; 2551 2552 if (!ql_mask_match(level)) 2553 return; 2554 2555 ql_dbg(level, vha, id, " 0 1 2 3 4 5 6 7 8 " 2556 "9 Ah Bh Ch Dh Eh Fh\n"); 2557 ql_dbg(level, vha, id, "----------------------------------" 2558 "----------------------------\n"); 2559 2560 ql_dbg(level, vha, id, " "); 2561 for (cnt = 0; cnt < size;) { 2562 c = *b++; 2563 printk("%02x", (uint32_t) c); 2564 cnt++; 2565 if (!(cnt % 16)) 2566 printk("\n"); 2567 else 2568 printk(" "); 2569 } 2570 if (cnt % 16) 2571 ql_dbg(level, vha, id, "\n"); 2572} 2573