1/* 2 * MPC512x PSC in SPI mode driver. 3 * 4 * Copyright (C) 2007,2008 Freescale Semiconductor Inc. 5 * Original port from 52xx driver: 6 * Hongjun Chen <hong-jun.chen@freescale.com> 7 * 8 * Fork of mpc52xx_psc_spi.c: 9 * Copyright (C) 2006 TOPTICA Photonics AG., Dragos Carp 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or (at your 14 * option) any later version. 15 */ 16 17#include <linux/module.h> 18#include <linux/kernel.h> 19#include <linux/errno.h> 20#include <linux/interrupt.h> 21#include <linux/of_address.h> 22#include <linux/of_irq.h> 23#include <linux/of_platform.h> 24#include <linux/completion.h> 25#include <linux/io.h> 26#include <linux/delay.h> 27#include <linux/clk.h> 28#include <linux/spi/spi.h> 29#include <linux/fsl_devices.h> 30#include <linux/gpio.h> 31#include <asm/mpc52xx_psc.h> 32 33struct mpc512x_psc_spi { 34 void (*cs_control)(struct spi_device *spi, bool on); 35 36 /* driver internal data */ 37 struct mpc52xx_psc __iomem *psc; 38 struct mpc512x_psc_fifo __iomem *fifo; 39 unsigned int irq; 40 u8 bits_per_word; 41 struct clk *clk_mclk; 42 struct clk *clk_ipg; 43 u32 mclk_rate; 44 45 struct completion txisrdone; 46}; 47 48/* controller state */ 49struct mpc512x_psc_spi_cs { 50 int bits_per_word; 51 int speed_hz; 52}; 53 54/* set clock freq, clock ramp, bits per work 55 * if t is NULL then reset the values to the default values 56 */ 57static int mpc512x_psc_spi_transfer_setup(struct spi_device *spi, 58 struct spi_transfer *t) 59{ 60 struct mpc512x_psc_spi_cs *cs = spi->controller_state; 61 62 cs->speed_hz = (t && t->speed_hz) 63 ? t->speed_hz : spi->max_speed_hz; 64 cs->bits_per_word = (t && t->bits_per_word) 65 ? t->bits_per_word : spi->bits_per_word; 66 cs->bits_per_word = ((cs->bits_per_word + 7) / 8) * 8; 67 return 0; 68} 69 70static void mpc512x_psc_spi_activate_cs(struct spi_device *spi) 71{ 72 struct mpc512x_psc_spi_cs *cs = spi->controller_state; 73 struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master); 74 struct mpc52xx_psc __iomem *psc = mps->psc; 75 u32 sicr; 76 u32 ccr; 77 int speed; 78 u16 bclkdiv; 79 80 sicr = in_be32(&psc->sicr); 81 82 /* Set clock phase and polarity */ 83 if (spi->mode & SPI_CPHA) 84 sicr |= 0x00001000; 85 else 86 sicr &= ~0x00001000; 87 88 if (spi->mode & SPI_CPOL) 89 sicr |= 0x00002000; 90 else 91 sicr &= ~0x00002000; 92 93 if (spi->mode & SPI_LSB_FIRST) 94 sicr |= 0x10000000; 95 else 96 sicr &= ~0x10000000; 97 out_be32(&psc->sicr, sicr); 98 99 ccr = in_be32(&psc->ccr); 100 ccr &= 0xFF000000; 101 speed = cs->speed_hz; 102 if (!speed) 103 speed = 1000000; /* default 1MHz */ 104 bclkdiv = (mps->mclk_rate / speed) - 1; 105 106 ccr |= (((bclkdiv & 0xff) << 16) | (((bclkdiv >> 8) & 0xff) << 8)); 107 out_be32(&psc->ccr, ccr); 108 mps->bits_per_word = cs->bits_per_word; 109 110 if (mps->cs_control && gpio_is_valid(spi->cs_gpio)) 111 mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 1 : 0); 112} 113 114static void mpc512x_psc_spi_deactivate_cs(struct spi_device *spi) 115{ 116 struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master); 117 118 if (mps->cs_control && gpio_is_valid(spi->cs_gpio)) 119 mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 0 : 1); 120 121} 122 123/* extract and scale size field in txsz or rxsz */ 124#define MPC512x_PSC_FIFO_SZ(sz) ((sz & 0x7ff) << 2); 125 126#define EOFBYTE 1 127 128static int mpc512x_psc_spi_transfer_rxtx(struct spi_device *spi, 129 struct spi_transfer *t) 130{ 131 struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master); 132 struct mpc512x_psc_fifo __iomem *fifo = mps->fifo; 133 size_t tx_len = t->len; 134 size_t rx_len = t->len; 135 u8 *tx_buf = (u8 *)t->tx_buf; 136 u8 *rx_buf = (u8 *)t->rx_buf; 137 138 if (!tx_buf && !rx_buf && t->len) 139 return -EINVAL; 140 141 while (rx_len || tx_len) { 142 size_t txcount; 143 u8 data; 144 size_t fifosz; 145 size_t rxcount; 146 int rxtries; 147 148 /* 149 * send the TX bytes in as large a chunk as possible 150 * but neither exceed the TX nor the RX FIFOs 151 */ 152 fifosz = MPC512x_PSC_FIFO_SZ(in_be32(&fifo->txsz)); 153 txcount = min(fifosz, tx_len); 154 fifosz = MPC512x_PSC_FIFO_SZ(in_be32(&fifo->rxsz)); 155 fifosz -= in_be32(&fifo->rxcnt) + 1; 156 txcount = min(fifosz, txcount); 157 if (txcount) { 158 159 /* fill the TX FIFO */ 160 while (txcount-- > 0) { 161 data = tx_buf ? *tx_buf++ : 0; 162 if (tx_len == EOFBYTE && t->cs_change) 163 setbits32(&fifo->txcmd, 164 MPC512x_PSC_FIFO_EOF); 165 out_8(&fifo->txdata_8, data); 166 tx_len--; 167 } 168 169 /* have the ISR trigger when the TX FIFO is empty */ 170 reinit_completion(&mps->txisrdone); 171 out_be32(&fifo->txisr, MPC512x_PSC_FIFO_EMPTY); 172 out_be32(&fifo->tximr, MPC512x_PSC_FIFO_EMPTY); 173 wait_for_completion(&mps->txisrdone); 174 } 175 176 /* 177 * consume as much RX data as the FIFO holds, while we 178 * iterate over the transfer's TX data length 179 * 180 * only insist in draining all the remaining RX bytes 181 * when the TX bytes were exhausted (that's at the very 182 * end of this transfer, not when still iterating over 183 * the transfer's chunks) 184 */ 185 rxtries = 50; 186 do { 187 188 /* 189 * grab whatever was in the FIFO when we started 190 * looking, don't bother fetching what was added to 191 * the FIFO while we read from it -- we'll return 192 * here eventually and prefer sending out remaining 193 * TX data 194 */ 195 fifosz = in_be32(&fifo->rxcnt); 196 rxcount = min(fifosz, rx_len); 197 while (rxcount-- > 0) { 198 data = in_8(&fifo->rxdata_8); 199 if (rx_buf) 200 *rx_buf++ = data; 201 rx_len--; 202 } 203 204 /* 205 * come back later if there still is TX data to send, 206 * bail out of the RX drain loop if all of the TX data 207 * was sent and all of the RX data was received (i.e. 208 * when the transmission has completed) 209 */ 210 if (tx_len) 211 break; 212 if (!rx_len) 213 break; 214 215 /* 216 * TX data transmission has completed while RX data 217 * is still pending -- that's a transient situation 218 * which depends on wire speed and specific 219 * hardware implementation details (buffering) yet 220 * should resolve very quickly 221 * 222 * just yield for a moment to not hog the CPU for 223 * too long when running SPI at low speed 224 * 225 * the timeout range is rather arbitrary and tries 226 * to balance throughput against system load; the 227 * chosen values result in a minimal timeout of 50 228 * times 10us and thus work at speeds as low as 229 * some 20kbps, while the maximum timeout at the 230 * transfer's end could be 5ms _if_ nothing else 231 * ticks in the system _and_ RX data still wasn't 232 * received, which only occurs in situations that 233 * are exceptional; removing the unpredictability 234 * of the timeout either decreases throughput 235 * (longer timeouts), or puts more load on the 236 * system (fixed short timeouts) or requires the 237 * use of a timeout API instead of a counter and an 238 * unknown inner delay 239 */ 240 usleep_range(10, 100); 241 242 } while (--rxtries > 0); 243 if (!tx_len && rx_len && !rxtries) { 244 /* 245 * not enough RX bytes even after several retries 246 * and the resulting rather long timeout? 247 */ 248 rxcount = in_be32(&fifo->rxcnt); 249 dev_warn(&spi->dev, 250 "short xfer, missing %zd RX bytes, FIFO level %zd\n", 251 rx_len, rxcount); 252 } 253 254 /* 255 * drain and drop RX data which "should not be there" in 256 * the first place, for undisturbed transmission this turns 257 * into a NOP (except for the FIFO level fetch) 258 */ 259 if (!tx_len && !rx_len) { 260 while (in_be32(&fifo->rxcnt)) 261 in_8(&fifo->rxdata_8); 262 } 263 264 } 265 return 0; 266} 267 268static int mpc512x_psc_spi_msg_xfer(struct spi_master *master, 269 struct spi_message *m) 270{ 271 struct spi_device *spi; 272 unsigned cs_change; 273 int status; 274 struct spi_transfer *t; 275 276 spi = m->spi; 277 cs_change = 1; 278 status = 0; 279 list_for_each_entry(t, &m->transfers, transfer_list) { 280 if (t->bits_per_word || t->speed_hz) { 281 status = mpc512x_psc_spi_transfer_setup(spi, t); 282 if (status < 0) 283 break; 284 } 285 286 if (cs_change) 287 mpc512x_psc_spi_activate_cs(spi); 288 cs_change = t->cs_change; 289 290 status = mpc512x_psc_spi_transfer_rxtx(spi, t); 291 if (status) 292 break; 293 m->actual_length += t->len; 294 295 if (t->delay_usecs) 296 udelay(t->delay_usecs); 297 298 if (cs_change) 299 mpc512x_psc_spi_deactivate_cs(spi); 300 } 301 302 m->status = status; 303 if (m->complete) 304 m->complete(m->context); 305 306 if (status || !cs_change) 307 mpc512x_psc_spi_deactivate_cs(spi); 308 309 mpc512x_psc_spi_transfer_setup(spi, NULL); 310 311 spi_finalize_current_message(master); 312 return status; 313} 314 315static int mpc512x_psc_spi_prep_xfer_hw(struct spi_master *master) 316{ 317 struct mpc512x_psc_spi *mps = spi_master_get_devdata(master); 318 struct mpc52xx_psc __iomem *psc = mps->psc; 319 320 dev_dbg(&master->dev, "%s()\n", __func__); 321 322 /* Zero MR2 */ 323 in_8(&psc->mode); 324 out_8(&psc->mode, 0x0); 325 326 /* enable transmitter/receiver */ 327 out_8(&psc->command, MPC52xx_PSC_TX_ENABLE | MPC52xx_PSC_RX_ENABLE); 328 329 return 0; 330} 331 332static int mpc512x_psc_spi_unprep_xfer_hw(struct spi_master *master) 333{ 334 struct mpc512x_psc_spi *mps = spi_master_get_devdata(master); 335 struct mpc52xx_psc __iomem *psc = mps->psc; 336 struct mpc512x_psc_fifo __iomem *fifo = mps->fifo; 337 338 dev_dbg(&master->dev, "%s()\n", __func__); 339 340 /* disable transmitter/receiver and fifo interrupt */ 341 out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE); 342 out_be32(&fifo->tximr, 0); 343 344 return 0; 345} 346 347static int mpc512x_psc_spi_setup(struct spi_device *spi) 348{ 349 struct mpc512x_psc_spi_cs *cs = spi->controller_state; 350 int ret; 351 352 if (spi->bits_per_word % 8) 353 return -EINVAL; 354 355 if (!cs) { 356 cs = kzalloc(sizeof *cs, GFP_KERNEL); 357 if (!cs) 358 return -ENOMEM; 359 360 if (gpio_is_valid(spi->cs_gpio)) { 361 ret = gpio_request(spi->cs_gpio, dev_name(&spi->dev)); 362 if (ret) { 363 dev_err(&spi->dev, "can't get CS gpio: %d\n", 364 ret); 365 kfree(cs); 366 return ret; 367 } 368 gpio_direction_output(spi->cs_gpio, 369 spi->mode & SPI_CS_HIGH ? 0 : 1); 370 } 371 372 spi->controller_state = cs; 373 } 374 375 cs->bits_per_word = spi->bits_per_word; 376 cs->speed_hz = spi->max_speed_hz; 377 378 return 0; 379} 380 381static void mpc512x_psc_spi_cleanup(struct spi_device *spi) 382{ 383 if (gpio_is_valid(spi->cs_gpio)) 384 gpio_free(spi->cs_gpio); 385 kfree(spi->controller_state); 386} 387 388static int mpc512x_psc_spi_port_config(struct spi_master *master, 389 struct mpc512x_psc_spi *mps) 390{ 391 struct mpc52xx_psc __iomem *psc = mps->psc; 392 struct mpc512x_psc_fifo __iomem *fifo = mps->fifo; 393 u32 sicr; 394 u32 ccr; 395 int speed; 396 u16 bclkdiv; 397 398 /* Reset the PSC into a known state */ 399 out_8(&psc->command, MPC52xx_PSC_RST_RX); 400 out_8(&psc->command, MPC52xx_PSC_RST_TX); 401 out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE); 402 403 /* Disable psc interrupts all useful interrupts are in fifo */ 404 out_be16(&psc->isr_imr.imr, 0); 405 406 /* Disable fifo interrupts, will be enabled later */ 407 out_be32(&fifo->tximr, 0); 408 out_be32(&fifo->rximr, 0); 409 410 /* Setup fifo slice address and size */ 411 /*out_be32(&fifo->txsz, 0x0fe00004);*/ 412 /*out_be32(&fifo->rxsz, 0x0ff00004);*/ 413 414 sicr = 0x01000000 | /* SIM = 0001 -- 8 bit */ 415 0x00800000 | /* GenClk = 1 -- internal clk */ 416 0x00008000 | /* SPI = 1 */ 417 0x00004000 | /* MSTR = 1 -- SPI master */ 418 0x00000800; /* UseEOF = 1 -- SS low until EOF */ 419 420 out_be32(&psc->sicr, sicr); 421 422 ccr = in_be32(&psc->ccr); 423 ccr &= 0xFF000000; 424 speed = 1000000; /* default 1MHz */ 425 bclkdiv = (mps->mclk_rate / speed) - 1; 426 ccr |= (((bclkdiv & 0xff) << 16) | (((bclkdiv >> 8) & 0xff) << 8)); 427 out_be32(&psc->ccr, ccr); 428 429 /* Set 2ms DTL delay */ 430 out_8(&psc->ctur, 0x00); 431 out_8(&psc->ctlr, 0x82); 432 433 /* we don't use the alarms */ 434 out_be32(&fifo->rxalarm, 0xfff); 435 out_be32(&fifo->txalarm, 0); 436 437 /* Enable FIFO slices for Rx/Tx */ 438 out_be32(&fifo->rxcmd, 439 MPC512x_PSC_FIFO_ENABLE_SLICE | MPC512x_PSC_FIFO_ENABLE_DMA); 440 out_be32(&fifo->txcmd, 441 MPC512x_PSC_FIFO_ENABLE_SLICE | MPC512x_PSC_FIFO_ENABLE_DMA); 442 443 mps->bits_per_word = 8; 444 445 return 0; 446} 447 448static irqreturn_t mpc512x_psc_spi_isr(int irq, void *dev_id) 449{ 450 struct mpc512x_psc_spi *mps = (struct mpc512x_psc_spi *)dev_id; 451 struct mpc512x_psc_fifo __iomem *fifo = mps->fifo; 452 453 /* clear interrupt and wake up the rx/tx routine */ 454 if (in_be32(&fifo->txisr) & 455 in_be32(&fifo->tximr) & MPC512x_PSC_FIFO_EMPTY) { 456 out_be32(&fifo->txisr, MPC512x_PSC_FIFO_EMPTY); 457 out_be32(&fifo->tximr, 0); 458 complete(&mps->txisrdone); 459 return IRQ_HANDLED; 460 } 461 return IRQ_NONE; 462} 463 464static void mpc512x_spi_cs_control(struct spi_device *spi, bool onoff) 465{ 466 gpio_set_value(spi->cs_gpio, onoff); 467} 468 469static int mpc512x_psc_spi_do_probe(struct device *dev, u32 regaddr, 470 u32 size, unsigned int irq) 471{ 472 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); 473 struct mpc512x_psc_spi *mps; 474 struct spi_master *master; 475 int ret; 476 void *tempp; 477 struct clk *clk; 478 479 master = spi_alloc_master(dev, sizeof *mps); 480 if (master == NULL) 481 return -ENOMEM; 482 483 dev_set_drvdata(dev, master); 484 mps = spi_master_get_devdata(master); 485 mps->irq = irq; 486 487 if (pdata == NULL) { 488 mps->cs_control = mpc512x_spi_cs_control; 489 } else { 490 mps->cs_control = pdata->cs_control; 491 master->bus_num = pdata->bus_num; 492 master->num_chipselect = pdata->max_chipselect; 493 } 494 495 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST; 496 master->setup = mpc512x_psc_spi_setup; 497 master->prepare_transfer_hardware = mpc512x_psc_spi_prep_xfer_hw; 498 master->transfer_one_message = mpc512x_psc_spi_msg_xfer; 499 master->unprepare_transfer_hardware = mpc512x_psc_spi_unprep_xfer_hw; 500 master->cleanup = mpc512x_psc_spi_cleanup; 501 master->dev.of_node = dev->of_node; 502 503 tempp = devm_ioremap(dev, regaddr, size); 504 if (!tempp) { 505 dev_err(dev, "could not ioremap I/O port range\n"); 506 ret = -EFAULT; 507 goto free_master; 508 } 509 mps->psc = tempp; 510 mps->fifo = 511 (struct mpc512x_psc_fifo *)(tempp + sizeof(struct mpc52xx_psc)); 512 ret = devm_request_irq(dev, mps->irq, mpc512x_psc_spi_isr, IRQF_SHARED, 513 "mpc512x-psc-spi", mps); 514 if (ret) 515 goto free_master; 516 init_completion(&mps->txisrdone); 517 518 clk = devm_clk_get(dev, "mclk"); 519 if (IS_ERR(clk)) { 520 ret = PTR_ERR(clk); 521 goto free_master; 522 } 523 ret = clk_prepare_enable(clk); 524 if (ret) 525 goto free_master; 526 mps->clk_mclk = clk; 527 mps->mclk_rate = clk_get_rate(clk); 528 529 clk = devm_clk_get(dev, "ipg"); 530 if (IS_ERR(clk)) { 531 ret = PTR_ERR(clk); 532 goto free_mclk_clock; 533 } 534 ret = clk_prepare_enable(clk); 535 if (ret) 536 goto free_mclk_clock; 537 mps->clk_ipg = clk; 538 539 ret = mpc512x_psc_spi_port_config(master, mps); 540 if (ret < 0) 541 goto free_ipg_clock; 542 543 ret = devm_spi_register_master(dev, master); 544 if (ret < 0) 545 goto free_ipg_clock; 546 547 return ret; 548 549free_ipg_clock: 550 clk_disable_unprepare(mps->clk_ipg); 551free_mclk_clock: 552 clk_disable_unprepare(mps->clk_mclk); 553free_master: 554 spi_master_put(master); 555 556 return ret; 557} 558 559static int mpc512x_psc_spi_do_remove(struct device *dev) 560{ 561 struct spi_master *master = dev_get_drvdata(dev); 562 struct mpc512x_psc_spi *mps = spi_master_get_devdata(master); 563 564 clk_disable_unprepare(mps->clk_mclk); 565 clk_disable_unprepare(mps->clk_ipg); 566 567 return 0; 568} 569 570static int mpc512x_psc_spi_of_probe(struct platform_device *op) 571{ 572 const u32 *regaddr_p; 573 u64 regaddr64, size64; 574 575 regaddr_p = of_get_address(op->dev.of_node, 0, &size64, NULL); 576 if (!regaddr_p) { 577 dev_err(&op->dev, "Invalid PSC address\n"); 578 return -EINVAL; 579 } 580 regaddr64 = of_translate_address(op->dev.of_node, regaddr_p); 581 582 return mpc512x_psc_spi_do_probe(&op->dev, (u32) regaddr64, (u32) size64, 583 irq_of_parse_and_map(op->dev.of_node, 0)); 584} 585 586static int mpc512x_psc_spi_of_remove(struct platform_device *op) 587{ 588 return mpc512x_psc_spi_do_remove(&op->dev); 589} 590 591static struct of_device_id mpc512x_psc_spi_of_match[] = { 592 { .compatible = "fsl,mpc5121-psc-spi", }, 593 {}, 594}; 595 596MODULE_DEVICE_TABLE(of, mpc512x_psc_spi_of_match); 597 598static struct platform_driver mpc512x_psc_spi_of_driver = { 599 .probe = mpc512x_psc_spi_of_probe, 600 .remove = mpc512x_psc_spi_of_remove, 601 .driver = { 602 .name = "mpc512x-psc-spi", 603 .owner = THIS_MODULE, 604 .of_match_table = mpc512x_psc_spi_of_match, 605 }, 606}; 607module_platform_driver(mpc512x_psc_spi_of_driver); 608 609MODULE_AUTHOR("John Rigby"); 610MODULE_DESCRIPTION("MPC512x PSC SPI Driver"); 611MODULE_LICENSE("GPL"); 612