spi-rockchip.c revision 64e36824b32b061a9537dc2e026977806f75846f
1/* 2 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd 3 * Author: addy ke <addy.ke@rock-chips.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 */ 15 16#include <linux/init.h> 17#include <linux/module.h> 18#include <linux/clk.h> 19#include <linux/err.h> 20#include <linux/delay.h> 21#include <linux/interrupt.h> 22#include <linux/platform_device.h> 23#include <linux/slab.h> 24#include <linux/spi/spi.h> 25#include <linux/scatterlist.h> 26#include <linux/of.h> 27#include <linux/pm_runtime.h> 28#include <linux/io.h> 29#include <linux/scatterlist.h> 30#include <linux/dmaengine.h> 31 32#define DRIVER_NAME "rockchip-spi" 33 34/* SPI register offsets */ 35#define ROCKCHIP_SPI_CTRLR0 0x0000 36#define ROCKCHIP_SPI_CTRLR1 0x0004 37#define ROCKCHIP_SPI_SSIENR 0x0008 38#define ROCKCHIP_SPI_SER 0x000c 39#define ROCKCHIP_SPI_BAUDR 0x0010 40#define ROCKCHIP_SPI_TXFTLR 0x0014 41#define ROCKCHIP_SPI_RXFTLR 0x0018 42#define ROCKCHIP_SPI_TXFLR 0x001c 43#define ROCKCHIP_SPI_RXFLR 0x0020 44#define ROCKCHIP_SPI_SR 0x0024 45#define ROCKCHIP_SPI_IPR 0x0028 46#define ROCKCHIP_SPI_IMR 0x002c 47#define ROCKCHIP_SPI_ISR 0x0030 48#define ROCKCHIP_SPI_RISR 0x0034 49#define ROCKCHIP_SPI_ICR 0x0038 50#define ROCKCHIP_SPI_DMACR 0x003c 51#define ROCKCHIP_SPI_DMATDLR 0x0040 52#define ROCKCHIP_SPI_DMARDLR 0x0044 53#define ROCKCHIP_SPI_TXDR 0x0400 54#define ROCKCHIP_SPI_RXDR 0x0800 55 56/* Bit fields in CTRLR0 */ 57#define CR0_DFS_OFFSET 0 58 59#define CR0_CFS_OFFSET 2 60 61#define CR0_SCPH_OFFSET 6 62 63#define CR0_SCPOL_OFFSET 7 64 65#define CR0_CSM_OFFSET 8 66#define CR0_CSM_KEEP 0x0 67/* ss_n be high for half sclk_out cycles */ 68#define CR0_CSM_HALF 0X1 69/* ss_n be high for one sclk_out cycle */ 70#define CR0_CSM_ONE 0x2 71 72/* ss_n to sclk_out delay */ 73#define CR0_SSD_OFFSET 10 74/* 75 * The period between ss_n active and 76 * sclk_out active is half sclk_out cycles 77 */ 78#define CR0_SSD_HALF 0x0 79/* 80 * The period between ss_n active and 81 * sclk_out active is one sclk_out cycle 82 */ 83#define CR0_SSD_ONE 0x1 84 85#define CR0_EM_OFFSET 11 86#define CR0_EM_LITTLE 0x0 87#define CR0_EM_BIG 0x1 88 89#define CR0_FBM_OFFSET 12 90#define CR0_FBM_MSB 0x0 91#define CR0_FBM_LSB 0x1 92 93#define CR0_BHT_OFFSET 13 94#define CR0_BHT_16BIT 0x0 95#define CR0_BHT_8BIT 0x1 96 97#define CR0_RSD_OFFSET 14 98 99#define CR0_FRF_OFFSET 16 100#define CR0_FRF_SPI 0x0 101#define CR0_FRF_SSP 0x1 102#define CR0_FRF_MICROWIRE 0x2 103 104#define CR0_XFM_OFFSET 18 105#define CR0_XFM_MASK (0x03 << SPI_XFM_OFFSET) 106#define CR0_XFM_TR 0x0 107#define CR0_XFM_TO 0x1 108#define CR0_XFM_RO 0x2 109 110#define CR0_OPM_OFFSET 20 111#define CR0_OPM_MASTER 0x0 112#define CR0_OPM_SLAVE 0x1 113 114#define CR0_MTM_OFFSET 0x21 115 116/* Bit fields in SER, 2bit */ 117#define SER_MASK 0x3 118 119/* Bit fields in SR, 5bit */ 120#define SR_MASK 0x1f 121#define SR_BUSY (1 << 0) 122#define SR_TF_FULL (1 << 1) 123#define SR_TF_EMPTY (1 << 2) 124#define SR_RF_EMPTY (1 << 3) 125#define SR_RF_FULL (1 << 4) 126 127/* Bit fields in ISR, IMR, ISR, RISR, 5bit */ 128#define INT_MASK 0x1f 129#define INT_TF_EMPTY (1 << 0) 130#define INT_TF_OVERFLOW (1 << 1) 131#define INT_RF_UNDERFLOW (1 << 2) 132#define INT_RF_OVERFLOW (1 << 3) 133#define INT_RF_FULL (1 << 4) 134 135/* Bit fields in ICR, 4bit */ 136#define ICR_MASK 0x0f 137#define ICR_ALL (1 << 0) 138#define ICR_RF_UNDERFLOW (1 << 1) 139#define ICR_RF_OVERFLOW (1 << 2) 140#define ICR_TF_OVERFLOW (1 << 3) 141 142/* Bit fields in DMACR */ 143#define RF_DMA_EN (1 << 0) 144#define TF_DMA_EN (1 << 1) 145 146#define RXBUSY (1 << 0) 147#define TXBUSY (1 << 1) 148 149enum rockchip_ssi_type { 150 SSI_MOTO_SPI = 0, 151 SSI_TI_SSP, 152 SSI_NS_MICROWIRE, 153}; 154 155struct rockchip_spi_dma_data { 156 struct dma_chan *ch; 157 enum dma_transfer_direction direction; 158 dma_addr_t addr; 159}; 160 161struct rockchip_spi { 162 struct device *dev; 163 struct spi_master *master; 164 165 struct clk *spiclk; 166 struct clk *apb_pclk; 167 168 void __iomem *regs; 169 /*depth of the FIFO buffer */ 170 u32 fifo_len; 171 /* max bus freq supported */ 172 u32 max_freq; 173 /* supported slave numbers */ 174 enum rockchip_ssi_type type; 175 176 u16 mode; 177 u8 tmode; 178 u8 bpw; 179 u8 n_bytes; 180 unsigned len; 181 u32 speed; 182 183 const void *tx; 184 const void *tx_end; 185 void *rx; 186 void *rx_end; 187 188 u32 state; 189 190 spinlock_t lock; 191 192 struct completion xfer_completion; 193 194 u32 use_dma; 195 struct sg_table tx_sg; 196 struct sg_table rx_sg; 197 struct rockchip_spi_dma_data dma_rx; 198 struct rockchip_spi_dma_data dma_tx; 199}; 200 201static inline void spi_enable_chip(struct rockchip_spi *rs, int enable) 202{ 203 writel_relaxed((enable ? 1 : 0), rs->regs + ROCKCHIP_SPI_SSIENR); 204} 205 206static inline void spi_set_clk(struct rockchip_spi *rs, u16 div) 207{ 208 writel_relaxed(div, rs->regs + ROCKCHIP_SPI_BAUDR); 209} 210 211static inline void flush_fifo(struct rockchip_spi *rs) 212{ 213 while (readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR)) 214 readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR); 215} 216 217static u32 get_fifo_len(struct rockchip_spi *rs) 218{ 219 u32 fifo; 220 221 for (fifo = 2; fifo < 32; fifo++) { 222 writel_relaxed(fifo, rs->regs + ROCKCHIP_SPI_TXFTLR); 223 if (fifo != readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFTLR)) 224 break; 225 } 226 227 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_TXFTLR); 228 229 return (fifo == 31) ? 0 : fifo; 230} 231 232static inline u32 tx_max(struct rockchip_spi *rs) 233{ 234 u32 tx_left, tx_room; 235 236 tx_left = (rs->tx_end - rs->tx) / rs->n_bytes; 237 tx_room = rs->fifo_len - readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFLR); 238 239 return min(tx_left, tx_room); 240} 241 242static inline u32 rx_max(struct rockchip_spi *rs) 243{ 244 u32 rx_left = (rs->rx_end - rs->rx) / rs->n_bytes; 245 u32 rx_room = (u32)readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR); 246 247 return min(rx_left, rx_room); 248} 249 250static void rockchip_spi_set_cs(struct spi_device *spi, bool enable) 251{ 252 u32 ser; 253 struct rockchip_spi *rs = spi_master_get_devdata(spi->master); 254 255 ser = readl_relaxed(rs->regs + ROCKCHIP_SPI_SER) & SER_MASK; 256 257 /* 258 * drivers/spi/spi.c: 259 * static void spi_set_cs(struct spi_device *spi, bool enable) 260 * { 261 * if (spi->mode & SPI_CS_HIGH) 262 * enable = !enable; 263 * 264 * if (spi->cs_gpio >= 0) 265 * gpio_set_value(spi->cs_gpio, !enable); 266 * else if (spi->master->set_cs) 267 * spi->master->set_cs(spi, !enable); 268 * } 269 * 270 * Note: enable(rockchip_spi_set_cs) = !enable(spi_set_cs) 271 */ 272 if (!enable) 273 ser |= 1 << spi->chip_select; 274 else 275 ser &= ~(1 << spi->chip_select); 276 277 writel_relaxed(ser, rs->regs + ROCKCHIP_SPI_SER); 278} 279 280static int rockchip_spi_prepare_message(struct spi_master *master, 281 struct spi_message *msg) 282{ 283 struct rockchip_spi *rs = spi_master_get_devdata(master); 284 struct spi_device *spi = msg->spi; 285 286 if (spi->mode & SPI_CS_HIGH) { 287 dev_err(rs->dev, "spi_cs_hign: not support\n"); 288 return -EINVAL; 289 } 290 291 rs->mode = spi->mode; 292 293 return 0; 294} 295 296static int rockchip_spi_unprepare_message(struct spi_master *master, 297 struct spi_message *msg) 298{ 299 unsigned long flags; 300 struct rockchip_spi *rs = spi_master_get_devdata(master); 301 302 spin_lock_irqsave(&rs->lock, flags); 303 304 if (rs->use_dma) { 305 if (rs->state & RXBUSY) { 306 dmaengine_terminate_all(rs->dma_rx.ch); 307 flush_fifo(rs); 308 } 309 310 if (rs->state & TXBUSY) 311 dmaengine_terminate_all(rs->dma_tx.ch); 312 } 313 314 spin_unlock_irqrestore(&rs->lock, flags); 315 316 return 0; 317} 318 319static void rockchip_spi_pio_writer(struct rockchip_spi *rs) 320{ 321 u32 max = tx_max(rs); 322 u32 txw = 0; 323 324 while (max--) { 325 if (rs->n_bytes == 1) 326 txw = *(u8 *)(rs->tx); 327 else 328 txw = *(u16 *)(rs->tx); 329 330 writel_relaxed(txw, rs->regs + ROCKCHIP_SPI_TXDR); 331 rs->tx += rs->n_bytes; 332 } 333} 334 335static void rockchip_spi_pio_reader(struct rockchip_spi *rs) 336{ 337 u32 max = rx_max(rs); 338 u32 rxw; 339 340 while (max--) { 341 rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR); 342 if (rs->n_bytes == 1) 343 *(u8 *)(rs->rx) = (u8)rxw; 344 else 345 *(u16 *)(rs->rx) = (u16)rxw; 346 rs->rx += rs->n_bytes; 347 }; 348} 349 350static int rockchip_spi_pio_transfer(struct rockchip_spi *rs) 351{ 352 int remain = 0; 353 354 do { 355 if (rs->tx) { 356 remain = rs->tx_end - rs->tx; 357 rockchip_spi_pio_writer(rs); 358 } 359 360 if (rs->rx) { 361 remain = rs->rx_end - rs->rx; 362 rockchip_spi_pio_reader(rs); 363 } 364 365 cpu_relax(); 366 } while (remain); 367 368 return 0; 369} 370 371static void rockchip_spi_dma_rxcb(void *data) 372{ 373 unsigned long flags; 374 struct rockchip_spi *rs = data; 375 376 spin_lock_irqsave(&rs->lock, flags); 377 378 rs->state &= ~RXBUSY; 379 if (!(rs->state & TXBUSY)) 380 spi_finalize_current_transfer(rs->master); 381 382 spin_unlock_irqrestore(&rs->lock, flags); 383} 384 385static void rockchip_spi_dma_txcb(void *data) 386{ 387 unsigned long flags; 388 struct rockchip_spi *rs = data; 389 390 spin_lock_irqsave(&rs->lock, flags); 391 392 rs->state &= ~TXBUSY; 393 if (!(rs->state & RXBUSY)) 394 spi_finalize_current_transfer(rs->master); 395 396 spin_unlock_irqrestore(&rs->lock, flags); 397} 398 399static int rockchip_spi_dma_transfer(struct rockchip_spi *rs) 400{ 401 unsigned long flags; 402 struct dma_slave_config rxconf, txconf; 403 struct dma_async_tx_descriptor *rxdesc, *txdesc; 404 405 spin_lock_irqsave(&rs->lock, flags); 406 rs->state &= ~RXBUSY; 407 rs->state &= ~TXBUSY; 408 spin_unlock_irqrestore(&rs->lock, flags); 409 410 if (rs->rx) { 411 rxconf.direction = rs->dma_rx.direction; 412 rxconf.src_addr = rs->dma_rx.addr; 413 rxconf.src_addr_width = rs->n_bytes; 414 rxconf.src_maxburst = rs->n_bytes; 415 dmaengine_slave_config(rs->dma_rx.ch, &rxconf); 416 417 rxdesc = dmaengine_prep_slave_sg(rs->dma_rx.ch, 418 rs->rx_sg.sgl, rs->rx_sg.nents, 419 rs->dma_rx.direction, DMA_PREP_INTERRUPT); 420 421 rxdesc->callback = rockchip_spi_dma_rxcb; 422 rxdesc->callback_param = rs; 423 } 424 425 if (rs->tx) { 426 txconf.direction = rs->dma_tx.direction; 427 txconf.dst_addr = rs->dma_tx.addr; 428 txconf.dst_addr_width = rs->n_bytes; 429 txconf.dst_maxburst = rs->n_bytes; 430 dmaengine_slave_config(rs->dma_tx.ch, &txconf); 431 432 txdesc = dmaengine_prep_slave_sg(rs->dma_tx.ch, 433 rs->tx_sg.sgl, rs->tx_sg.nents, 434 rs->dma_tx.direction, DMA_PREP_INTERRUPT); 435 436 txdesc->callback = rockchip_spi_dma_txcb; 437 txdesc->callback_param = rs; 438 } 439 440 /* rx must be started before tx due to spi instinct */ 441 if (rs->rx) { 442 spin_lock_irqsave(&rs->lock, flags); 443 rs->state |= RXBUSY; 444 spin_unlock_irqrestore(&rs->lock, flags); 445 dmaengine_submit(rxdesc); 446 dma_async_issue_pending(rs->dma_rx.ch); 447 } 448 449 if (rs->tx) { 450 spin_lock_irqsave(&rs->lock, flags); 451 rs->state |= TXBUSY; 452 spin_unlock_irqrestore(&rs->lock, flags); 453 dmaengine_submit(txdesc); 454 dma_async_issue_pending(rs->dma_tx.ch); 455 } 456 457 return 1; 458} 459 460static void rockchip_spi_config(struct rockchip_spi *rs) 461{ 462 u32 div = 0; 463 u32 dmacr = 0; 464 465 u32 cr0 = (CR0_BHT_8BIT << CR0_BHT_OFFSET) 466 | (CR0_SSD_ONE << CR0_SSD_OFFSET); 467 468 cr0 |= (rs->n_bytes << CR0_DFS_OFFSET); 469 cr0 |= ((rs->mode & 0x3) << CR0_SCPH_OFFSET); 470 cr0 |= (rs->tmode << CR0_XFM_OFFSET); 471 cr0 |= (rs->type << CR0_FRF_OFFSET); 472 473 if (rs->use_dma) { 474 if (rs->tx) 475 dmacr |= TF_DMA_EN; 476 if (rs->rx) 477 dmacr |= RF_DMA_EN; 478 } 479 480 /* div doesn't support odd number */ 481 div = rs->max_freq / rs->speed; 482 div = (div + 1) & 0xfffe; 483 484 spi_enable_chip(rs, 0); 485 486 writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0); 487 488 writel_relaxed(rs->len - 1, rs->regs + ROCKCHIP_SPI_CTRLR1); 489 writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_TXFTLR); 490 writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_RXFTLR); 491 492 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_DMATDLR); 493 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_DMARDLR); 494 writel_relaxed(dmacr, rs->regs + ROCKCHIP_SPI_DMACR); 495 496 spi_set_clk(rs, div); 497 498 dev_dbg(rs->dev, "cr0 0x%x, div %d\n", 499 cr0, div); 500 501 spi_enable_chip(rs, 1); 502} 503 504static int rockchip_spi_transfer_one(struct spi_master *master, 505 struct spi_device *spi, 506 struct spi_transfer *xfer) 507{ 508 int ret = 0; 509 struct rockchip_spi *rs = spi_master_get_devdata(master); 510 511 WARN_ON((readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY)); 512 513 if (!xfer->tx_buf && !xfer->rx_buf) { 514 dev_err(rs->dev, "No buffer for transfer\n"); 515 return -EINVAL; 516 } 517 518 rs->speed = xfer->speed_hz; 519 rs->bpw = xfer->bits_per_word; 520 rs->n_bytes = rs->bpw >> 3; 521 522 rs->tx = xfer->tx_buf; 523 rs->tx_end = rs->tx + xfer->len; 524 rs->rx = xfer->rx_buf; 525 rs->rx_end = rs->rx + xfer->len; 526 rs->len = xfer->len; 527 528 rs->tx_sg = xfer->tx_sg; 529 rs->rx_sg = xfer->rx_sg; 530 531 /* Delay until the FIFO data completely */ 532 if (xfer->tx_buf) 533 xfer->delay_usecs 534 = rs->fifo_len * rs->bpw * 1000000 / rs->speed; 535 536 if (rs->tx && rs->rx) 537 rs->tmode = CR0_XFM_TR; 538 else if (rs->tx) 539 rs->tmode = CR0_XFM_TO; 540 else if (rs->rx) 541 rs->tmode = CR0_XFM_RO; 542 543 if (master->can_dma && master->can_dma(master, spi, xfer)) 544 rs->use_dma = 1; 545 else 546 rs->use_dma = 0; 547 548 rockchip_spi_config(rs); 549 550 if (rs->use_dma) 551 ret = rockchip_spi_dma_transfer(rs); 552 else 553 ret = rockchip_spi_pio_transfer(rs); 554 555 return ret; 556} 557 558static bool rockchip_spi_can_dma(struct spi_master *master, 559 struct spi_device *spi, 560 struct spi_transfer *xfer) 561{ 562 struct rockchip_spi *rs = spi_master_get_devdata(master); 563 564 return (xfer->len > rs->fifo_len); 565} 566 567static int rockchip_spi_probe(struct platform_device *pdev) 568{ 569 int ret = 0; 570 struct rockchip_spi *rs; 571 struct spi_master *master; 572 struct resource *mem; 573 574 master = spi_alloc_master(&pdev->dev, sizeof(struct rockchip_spi)); 575 if (!master) { 576 dev_err(&pdev->dev, "No memory for spi_master\n"); 577 return -ENOMEM; 578 } 579 platform_set_drvdata(pdev, master); 580 581 rs = spi_master_get_devdata(master); 582 memset(rs, 0, sizeof(struct rockchip_spi)); 583 584 /* Get basic io resource and map it */ 585 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 586 rs->regs = devm_ioremap_resource(&pdev->dev, mem); 587 if (IS_ERR(rs->regs)) { 588 dev_err(&pdev->dev, "Failed to map SPI region\n"); 589 ret = PTR_ERR(rs->regs); 590 goto err_ioremap_resource; 591 } 592 593 rs->apb_pclk = devm_clk_get(&pdev->dev, "apb_pclk"); 594 if (IS_ERR(rs->apb_pclk)) { 595 dev_err(&pdev->dev, "Failed to get apb_pclk\n"); 596 ret = PTR_ERR(rs->apb_pclk); 597 goto err_ioremap_resource; 598 } 599 600 rs->spiclk = devm_clk_get(&pdev->dev, "spiclk"); 601 if (IS_ERR(rs->spiclk)) { 602 dev_err(&pdev->dev, "Failed to get spi_pclk\n"); 603 ret = PTR_ERR(rs->spiclk); 604 goto err_ioremap_resource; 605 } 606 607 ret = clk_prepare_enable(rs->apb_pclk); 608 if (ret) { 609 dev_err(&pdev->dev, "Failed to enable apb_pclk\n"); 610 goto err_ioremap_resource; 611 } 612 613 ret = clk_prepare_enable(rs->spiclk); 614 if (ret) { 615 dev_err(&pdev->dev, "Failed to enable spi_clk\n"); 616 goto err_spiclk_enable; 617 } 618 619 spi_enable_chip(rs, 0); 620 621 rs->type = SSI_MOTO_SPI; 622 rs->master = master; 623 rs->dev = &pdev->dev; 624 rs->max_freq = clk_get_rate(rs->spiclk); 625 626 rs->fifo_len = get_fifo_len(rs); 627 if (!rs->fifo_len) { 628 dev_err(&pdev->dev, "Failed to get fifo length\n"); 629 goto err_get_fifo_len; 630 } 631 632 spin_lock_init(&rs->lock); 633 634 pm_runtime_set_active(&pdev->dev); 635 pm_runtime_enable(&pdev->dev); 636 637 master->auto_runtime_pm = true; 638 master->bus_num = pdev->id; 639 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; 640 master->num_chipselect = 2; 641 master->dev.of_node = pdev->dev.of_node; 642 master->bits_per_word_mask = SPI_BPW_MASK(16) | SPI_BPW_MASK(8); 643 644 master->set_cs = rockchip_spi_set_cs; 645 master->prepare_message = rockchip_spi_prepare_message; 646 master->unprepare_message = rockchip_spi_unprepare_message; 647 master->transfer_one = rockchip_spi_transfer_one; 648 649 rs->dma_tx.ch = dma_request_slave_channel(rs->dev, "tx"); 650 if (!rs->dma_tx.ch) 651 dev_warn(rs->dev, "Failed to request TX DMA channel\n"); 652 653 rs->dma_rx.ch = dma_request_slave_channel(rs->dev, "rx"); 654 if (!rs->dma_rx.ch) { 655 if (rs->dma_tx.ch) { 656 dma_release_channel(rs->dma_tx.ch); 657 rs->dma_tx.ch = NULL; 658 } 659 dev_warn(rs->dev, "Failed to request RX DMA channel\n"); 660 } 661 662 if (rs->dma_tx.ch && rs->dma_rx.ch) { 663 rs->dma_tx.addr = (dma_addr_t)(mem->start + ROCKCHIP_SPI_TXDR); 664 rs->dma_rx.addr = (dma_addr_t)(mem->start + ROCKCHIP_SPI_RXDR); 665 rs->dma_tx.direction = DMA_MEM_TO_DEV; 666 rs->dma_tx.direction = DMA_DEV_TO_MEM; 667 668 master->can_dma = rockchip_spi_can_dma; 669 master->dma_tx = rs->dma_tx.ch; 670 master->dma_rx = rs->dma_rx.ch; 671 } 672 673 ret = devm_spi_register_master(&pdev->dev, master); 674 if (ret) { 675 dev_err(&pdev->dev, "Failed to register master\n"); 676 goto err_register_master; 677 } 678 679 dev_info(&pdev->dev, "Rockchip SPI controller initialized\n"); 680 681 return 0; 682 683err_register_master: 684 if (rs->dma_tx.ch) 685 dma_release_channel(rs->dma_tx.ch); 686 if (rs->dma_rx.ch) 687 dma_release_channel(rs->dma_rx.ch); 688err_get_fifo_len: 689 clk_disable_unprepare(rs->spiclk); 690err_spiclk_enable: 691 clk_disable_unprepare(rs->apb_pclk); 692err_ioremap_resource: 693 spi_master_put(master); 694 695 return ret; 696} 697 698static int rockchip_spi_remove(struct platform_device *pdev) 699{ 700 struct spi_master *master = spi_master_get(platform_get_drvdata(pdev)); 701 struct rockchip_spi *rs = spi_master_get_devdata(master); 702 703 pm_runtime_disable(&pdev->dev); 704 705 clk_disable_unprepare(rs->spiclk); 706 clk_disable_unprepare(rs->apb_pclk); 707 708 if (rs->dma_tx.ch) 709 dma_release_channel(rs->dma_tx.ch); 710 if (rs->dma_rx.ch) 711 dma_release_channel(rs->dma_rx.ch); 712 713 spi_master_put(master); 714 715 return 0; 716} 717 718#ifdef CONFIG_PM_SLEEP 719static int rockchip_spi_suspend(struct device *dev) 720{ 721 int ret = 0; 722 struct spi_master *master = dev_get_drvdata(dev); 723 struct rockchip_spi *rs = spi_master_get_devdata(master); 724 725 ret = spi_master_suspend(rs->master); 726 if (ret) 727 return ret; 728 729 if (!pm_runtime_suspended(dev)) { 730 clk_disable_unprepare(rs->spiclk); 731 clk_disable_unprepare(rs->apb_pclk); 732 } 733 734 return ret; 735} 736 737static int rockchip_spi_resume(struct device *dev) 738{ 739 int ret = 0; 740 struct spi_master *master = dev_get_drvdata(dev); 741 struct rockchip_spi *rs = spi_master_get_devdata(master); 742 743 if (!pm_runtime_suspended(dev)) { 744 ret = clk_prepare_enable(rs->apb_pclk); 745 if (ret < 0) 746 return ret; 747 748 ret = clk_prepare_enable(rs->spiclk); 749 if (ret < 0) { 750 clk_disable_unprepare(rs->apb_pclk); 751 return ret; 752 } 753 } 754 755 ret = spi_master_resume(rs->master); 756 if (ret < 0) { 757 clk_disable_unprepare(rs->spiclk); 758 clk_disable_unprepare(rs->apb_pclk); 759 } 760 761 return ret; 762} 763#endif /* CONFIG_PM_SLEEP */ 764 765#ifdef CONFIG_PM_RUNTIME 766static int rockchip_spi_runtime_suspend(struct device *dev) 767{ 768 struct spi_master *master = dev_get_drvdata(dev); 769 struct rockchip_spi *rs = spi_master_get_devdata(master); 770 771 clk_disable_unprepare(rs->spiclk); 772 clk_disable_unprepare(rs->apb_pclk); 773 774 return 0; 775} 776 777static int rockchip_spi_runtime_resume(struct device *dev) 778{ 779 int ret; 780 struct spi_master *master = dev_get_drvdata(dev); 781 struct rockchip_spi *rs = spi_master_get_devdata(master); 782 783 ret = clk_prepare_enable(rs->apb_pclk); 784 if (ret) 785 return ret; 786 787 ret = clk_prepare_enable(rs->spiclk); 788 if (ret) 789 clk_disable_unprepare(rs->apb_pclk); 790 791 return ret; 792} 793#endif /* CONFIG_PM_RUNTIME */ 794 795static const struct dev_pm_ops rockchip_spi_pm = { 796 SET_SYSTEM_SLEEP_PM_OPS(rockchip_spi_suspend, rockchip_spi_resume) 797 SET_RUNTIME_PM_OPS(rockchip_spi_runtime_suspend, 798 rockchip_spi_runtime_resume, NULL) 799}; 800 801static const struct of_device_id rockchip_spi_dt_match[] = { 802 { .compatible = "rockchip,rk3066-spi", }, 803 { }, 804}; 805MODULE_DEVICE_TABLE(of, rockchip_spi_dt_match); 806 807static struct platform_driver rockchip_spi_driver = { 808 .driver = { 809 .name = DRIVER_NAME, 810 .owner = THIS_MODULE, 811 .pm = &rockchip_spi_pm, 812 .of_match_table = of_match_ptr(rockchip_spi_dt_match), 813 }, 814 .probe = rockchip_spi_probe, 815 .remove = rockchip_spi_remove, 816}; 817 818module_platform_driver(rockchip_spi_driver); 819 820MODULE_AUTHOR("addy ke <addy.ke@rock-chips.com>"); 821MODULE_DESCRIPTION("ROCKCHIP SPI Controller Driver"); 822MODULE_LICENSE("GPL v2"); 823