1/* 2 * SuperH MSIOF SPI Master Interface 3 * 4 * Copyright (c) 2009 Magnus Damm 5 * Copyright (C) 2014 Glider bvba 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 */ 12 13#include <linux/bitmap.h> 14#include <linux/clk.h> 15#include <linux/completion.h> 16#include <linux/delay.h> 17#include <linux/dma-mapping.h> 18#include <linux/dmaengine.h> 19#include <linux/err.h> 20#include <linux/gpio.h> 21#include <linux/interrupt.h> 22#include <linux/io.h> 23#include <linux/kernel.h> 24#include <linux/module.h> 25#include <linux/of.h> 26#include <linux/of_device.h> 27#include <linux/platform_device.h> 28#include <linux/pm_runtime.h> 29#include <linux/sh_dma.h> 30 31#include <linux/spi/sh_msiof.h> 32#include <linux/spi/spi.h> 33 34#include <asm/unaligned.h> 35 36 37struct sh_msiof_chipdata { 38 u16 tx_fifo_size; 39 u16 rx_fifo_size; 40 u16 master_flags; 41}; 42 43struct sh_msiof_spi_priv { 44 struct spi_master *master; 45 void __iomem *mapbase; 46 struct clk *clk; 47 struct platform_device *pdev; 48 const struct sh_msiof_chipdata *chipdata; 49 struct sh_msiof_spi_info *info; 50 struct completion done; 51 int tx_fifo_size; 52 int rx_fifo_size; 53 void *tx_dma_page; 54 void *rx_dma_page; 55 dma_addr_t tx_dma_addr; 56 dma_addr_t rx_dma_addr; 57}; 58 59#define TMDR1 0x00 /* Transmit Mode Register 1 */ 60#define TMDR2 0x04 /* Transmit Mode Register 2 */ 61#define TMDR3 0x08 /* Transmit Mode Register 3 */ 62#define RMDR1 0x10 /* Receive Mode Register 1 */ 63#define RMDR2 0x14 /* Receive Mode Register 2 */ 64#define RMDR3 0x18 /* Receive Mode Register 3 */ 65#define TSCR 0x20 /* Transmit Clock Select Register */ 66#define RSCR 0x22 /* Receive Clock Select Register (SH, A1, APE6) */ 67#define CTR 0x28 /* Control Register */ 68#define FCTR 0x30 /* FIFO Control Register */ 69#define STR 0x40 /* Status Register */ 70#define IER 0x44 /* Interrupt Enable Register */ 71#define TDR1 0x48 /* Transmit Control Data Register 1 (SH, A1) */ 72#define TDR2 0x4c /* Transmit Control Data Register 2 (SH, A1) */ 73#define TFDR 0x50 /* Transmit FIFO Data Register */ 74#define RDR1 0x58 /* Receive Control Data Register 1 (SH, A1) */ 75#define RDR2 0x5c /* Receive Control Data Register 2 (SH, A1) */ 76#define RFDR 0x60 /* Receive FIFO Data Register */ 77 78/* TMDR1 and RMDR1 */ 79#define MDR1_TRMD 0x80000000 /* Transfer Mode (1 = Master mode) */ 80#define MDR1_SYNCMD_MASK 0x30000000 /* SYNC Mode */ 81#define MDR1_SYNCMD_SPI 0x20000000 /* Level mode/SPI */ 82#define MDR1_SYNCMD_LR 0x30000000 /* L/R mode */ 83#define MDR1_SYNCAC_SHIFT 25 /* Sync Polarity (1 = Active-low) */ 84#define MDR1_BITLSB_SHIFT 24 /* MSB/LSB First (1 = LSB first) */ 85#define MDR1_FLD_MASK 0x000000c0 /* Frame Sync Signal Interval (0-3) */ 86#define MDR1_FLD_SHIFT 2 87#define MDR1_XXSTP 0x00000001 /* Transmission/Reception Stop on FIFO */ 88/* TMDR1 */ 89#define TMDR1_PCON 0x40000000 /* Transfer Signal Connection */ 90 91/* TMDR2 and RMDR2 */ 92#define MDR2_BITLEN1(i) (((i) - 1) << 24) /* Data Size (8-32 bits) */ 93#define MDR2_WDLEN1(i) (((i) - 1) << 16) /* Word Count (1-64/256 (SH, A1))) */ 94#define MDR2_GRPMASK1 0x00000001 /* Group Output Mask 1 (SH, A1) */ 95 96#define MAX_WDLEN 256U 97 98/* TSCR and RSCR */ 99#define SCR_BRPS_MASK 0x1f00 /* Prescaler Setting (1-32) */ 100#define SCR_BRPS(i) (((i) - 1) << 8) 101#define SCR_BRDV_MASK 0x0007 /* Baud Rate Generator's Division Ratio */ 102#define SCR_BRDV_DIV_2 0x0000 103#define SCR_BRDV_DIV_4 0x0001 104#define SCR_BRDV_DIV_8 0x0002 105#define SCR_BRDV_DIV_16 0x0003 106#define SCR_BRDV_DIV_32 0x0004 107#define SCR_BRDV_DIV_1 0x0007 108 109/* CTR */ 110#define CTR_TSCKIZ_MASK 0xc0000000 /* Transmit Clock I/O Polarity Select */ 111#define CTR_TSCKIZ_SCK 0x80000000 /* Disable SCK when TX disabled */ 112#define CTR_TSCKIZ_POL_SHIFT 30 /* Transmit Clock Polarity */ 113#define CTR_RSCKIZ_MASK 0x30000000 /* Receive Clock Polarity Select */ 114#define CTR_RSCKIZ_SCK 0x20000000 /* Must match CTR_TSCKIZ_SCK */ 115#define CTR_RSCKIZ_POL_SHIFT 28 /* Receive Clock Polarity */ 116#define CTR_TEDG_SHIFT 27 /* Transmit Timing (1 = falling edge) */ 117#define CTR_REDG_SHIFT 26 /* Receive Timing (1 = falling edge) */ 118#define CTR_TXDIZ_MASK 0x00c00000 /* Pin Output When TX is Disabled */ 119#define CTR_TXDIZ_LOW 0x00000000 /* 0 */ 120#define CTR_TXDIZ_HIGH 0x00400000 /* 1 */ 121#define CTR_TXDIZ_HIZ 0x00800000 /* High-impedance */ 122#define CTR_TSCKE 0x00008000 /* Transmit Serial Clock Output Enable */ 123#define CTR_TFSE 0x00004000 /* Transmit Frame Sync Signal Output Enable */ 124#define CTR_TXE 0x00000200 /* Transmit Enable */ 125#define CTR_RXE 0x00000100 /* Receive Enable */ 126 127/* FCTR */ 128#define FCTR_TFWM_MASK 0xe0000000 /* Transmit FIFO Watermark */ 129#define FCTR_TFWM_64 0x00000000 /* Transfer Request when 64 empty stages */ 130#define FCTR_TFWM_32 0x20000000 /* Transfer Request when 32 empty stages */ 131#define FCTR_TFWM_24 0x40000000 /* Transfer Request when 24 empty stages */ 132#define FCTR_TFWM_16 0x60000000 /* Transfer Request when 16 empty stages */ 133#define FCTR_TFWM_12 0x80000000 /* Transfer Request when 12 empty stages */ 134#define FCTR_TFWM_8 0xa0000000 /* Transfer Request when 8 empty stages */ 135#define FCTR_TFWM_4 0xc0000000 /* Transfer Request when 4 empty stages */ 136#define FCTR_TFWM_1 0xe0000000 /* Transfer Request when 1 empty stage */ 137#define FCTR_TFUA_MASK 0x07f00000 /* Transmit FIFO Usable Area */ 138#define FCTR_TFUA_SHIFT 20 139#define FCTR_TFUA(i) ((i) << FCTR_TFUA_SHIFT) 140#define FCTR_RFWM_MASK 0x0000e000 /* Receive FIFO Watermark */ 141#define FCTR_RFWM_1 0x00000000 /* Transfer Request when 1 valid stages */ 142#define FCTR_RFWM_4 0x00002000 /* Transfer Request when 4 valid stages */ 143#define FCTR_RFWM_8 0x00004000 /* Transfer Request when 8 valid stages */ 144#define FCTR_RFWM_16 0x00006000 /* Transfer Request when 16 valid stages */ 145#define FCTR_RFWM_32 0x00008000 /* Transfer Request when 32 valid stages */ 146#define FCTR_RFWM_64 0x0000a000 /* Transfer Request when 64 valid stages */ 147#define FCTR_RFWM_128 0x0000c000 /* Transfer Request when 128 valid stages */ 148#define FCTR_RFWM_256 0x0000e000 /* Transfer Request when 256 valid stages */ 149#define FCTR_RFUA_MASK 0x00001ff0 /* Receive FIFO Usable Area (0x40 = full) */ 150#define FCTR_RFUA_SHIFT 4 151#define FCTR_RFUA(i) ((i) << FCTR_RFUA_SHIFT) 152 153/* STR */ 154#define STR_TFEMP 0x20000000 /* Transmit FIFO Empty */ 155#define STR_TDREQ 0x10000000 /* Transmit Data Transfer Request */ 156#define STR_TEOF 0x00800000 /* Frame Transmission End */ 157#define STR_TFSERR 0x00200000 /* Transmit Frame Synchronization Error */ 158#define STR_TFOVF 0x00100000 /* Transmit FIFO Overflow */ 159#define STR_TFUDF 0x00080000 /* Transmit FIFO Underflow */ 160#define STR_RFFUL 0x00002000 /* Receive FIFO Full */ 161#define STR_RDREQ 0x00001000 /* Receive Data Transfer Request */ 162#define STR_REOF 0x00000080 /* Frame Reception End */ 163#define STR_RFSERR 0x00000020 /* Receive Frame Synchronization Error */ 164#define STR_RFUDF 0x00000010 /* Receive FIFO Underflow */ 165#define STR_RFOVF 0x00000008 /* Receive FIFO Overflow */ 166 167/* IER */ 168#define IER_TDMAE 0x80000000 /* Transmit Data DMA Transfer Req. Enable */ 169#define IER_TFEMPE 0x20000000 /* Transmit FIFO Empty Enable */ 170#define IER_TDREQE 0x10000000 /* Transmit Data Transfer Request Enable */ 171#define IER_TEOFE 0x00800000 /* Frame Transmission End Enable */ 172#define IER_TFSERRE 0x00200000 /* Transmit Frame Sync Error Enable */ 173#define IER_TFOVFE 0x00100000 /* Transmit FIFO Overflow Enable */ 174#define IER_TFUDFE 0x00080000 /* Transmit FIFO Underflow Enable */ 175#define IER_RDMAE 0x00008000 /* Receive Data DMA Transfer Req. Enable */ 176#define IER_RFFULE 0x00002000 /* Receive FIFO Full Enable */ 177#define IER_RDREQE 0x00001000 /* Receive Data Transfer Request Enable */ 178#define IER_REOFE 0x00000080 /* Frame Reception End Enable */ 179#define IER_RFSERRE 0x00000020 /* Receive Frame Sync Error Enable */ 180#define IER_RFUDFE 0x00000010 /* Receive FIFO Underflow Enable */ 181#define IER_RFOVFE 0x00000008 /* Receive FIFO Overflow Enable */ 182 183 184static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs) 185{ 186 switch (reg_offs) { 187 case TSCR: 188 case RSCR: 189 return ioread16(p->mapbase + reg_offs); 190 default: 191 return ioread32(p->mapbase + reg_offs); 192 } 193} 194 195static void sh_msiof_write(struct sh_msiof_spi_priv *p, int reg_offs, 196 u32 value) 197{ 198 switch (reg_offs) { 199 case TSCR: 200 case RSCR: 201 iowrite16(value, p->mapbase + reg_offs); 202 break; 203 default: 204 iowrite32(value, p->mapbase + reg_offs); 205 break; 206 } 207} 208 209static int sh_msiof_modify_ctr_wait(struct sh_msiof_spi_priv *p, 210 u32 clr, u32 set) 211{ 212 u32 mask = clr | set; 213 u32 data; 214 int k; 215 216 data = sh_msiof_read(p, CTR); 217 data &= ~clr; 218 data |= set; 219 sh_msiof_write(p, CTR, data); 220 221 for (k = 100; k > 0; k--) { 222 if ((sh_msiof_read(p, CTR) & mask) == set) 223 break; 224 225 udelay(10); 226 } 227 228 return k > 0 ? 0 : -ETIMEDOUT; 229} 230 231static irqreturn_t sh_msiof_spi_irq(int irq, void *data) 232{ 233 struct sh_msiof_spi_priv *p = data; 234 235 /* just disable the interrupt and wake up */ 236 sh_msiof_write(p, IER, 0); 237 complete(&p->done); 238 239 return IRQ_HANDLED; 240} 241 242static struct { 243 unsigned short div; 244 unsigned short scr; 245} const sh_msiof_spi_clk_table[] = { 246 { 1, SCR_BRPS( 1) | SCR_BRDV_DIV_1 }, 247 { 2, SCR_BRPS( 1) | SCR_BRDV_DIV_2 }, 248 { 4, SCR_BRPS( 1) | SCR_BRDV_DIV_4 }, 249 { 8, SCR_BRPS( 1) | SCR_BRDV_DIV_8 }, 250 { 16, SCR_BRPS( 1) | SCR_BRDV_DIV_16 }, 251 { 32, SCR_BRPS( 1) | SCR_BRDV_DIV_32 }, 252 { 64, SCR_BRPS(32) | SCR_BRDV_DIV_2 }, 253 { 128, SCR_BRPS(32) | SCR_BRDV_DIV_4 }, 254 { 256, SCR_BRPS(32) | SCR_BRDV_DIV_8 }, 255 { 512, SCR_BRPS(32) | SCR_BRDV_DIV_16 }, 256 { 1024, SCR_BRPS(32) | SCR_BRDV_DIV_32 }, 257}; 258 259static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p, 260 unsigned long parent_rate, u32 spi_hz) 261{ 262 unsigned long div = 1024; 263 size_t k; 264 265 if (!WARN_ON(!spi_hz || !parent_rate)) 266 div = DIV_ROUND_UP(parent_rate, spi_hz); 267 268 /* TODO: make more fine grained */ 269 270 for (k = 0; k < ARRAY_SIZE(sh_msiof_spi_clk_table); k++) { 271 if (sh_msiof_spi_clk_table[k].div >= div) 272 break; 273 } 274 275 k = min_t(int, k, ARRAY_SIZE(sh_msiof_spi_clk_table) - 1); 276 277 sh_msiof_write(p, TSCR, sh_msiof_spi_clk_table[k].scr); 278 if (!(p->chipdata->master_flags & SPI_MASTER_MUST_TX)) 279 sh_msiof_write(p, RSCR, sh_msiof_spi_clk_table[k].scr); 280} 281 282static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p, 283 u32 cpol, u32 cpha, 284 u32 tx_hi_z, u32 lsb_first, u32 cs_high) 285{ 286 u32 tmp; 287 int edge; 288 289 /* 290 * CPOL CPHA TSCKIZ RSCKIZ TEDG REDG 291 * 0 0 10 10 1 1 292 * 0 1 10 10 0 0 293 * 1 0 11 11 0 0 294 * 1 1 11 11 1 1 295 */ 296 tmp = MDR1_SYNCMD_SPI | 1 << MDR1_FLD_SHIFT | MDR1_XXSTP; 297 tmp |= !cs_high << MDR1_SYNCAC_SHIFT; 298 tmp |= lsb_first << MDR1_BITLSB_SHIFT; 299 sh_msiof_write(p, TMDR1, tmp | MDR1_TRMD | TMDR1_PCON); 300 if (p->chipdata->master_flags & SPI_MASTER_MUST_TX) { 301 /* These bits are reserved if RX needs TX */ 302 tmp &= ~0x0000ffff; 303 } 304 sh_msiof_write(p, RMDR1, tmp); 305 306 tmp = 0; 307 tmp |= CTR_TSCKIZ_SCK | cpol << CTR_TSCKIZ_POL_SHIFT; 308 tmp |= CTR_RSCKIZ_SCK | cpol << CTR_RSCKIZ_POL_SHIFT; 309 310 edge = cpol ^ !cpha; 311 312 tmp |= edge << CTR_TEDG_SHIFT; 313 tmp |= edge << CTR_REDG_SHIFT; 314 tmp |= tx_hi_z ? CTR_TXDIZ_HIZ : CTR_TXDIZ_LOW; 315 sh_msiof_write(p, CTR, tmp); 316} 317 318static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p, 319 const void *tx_buf, void *rx_buf, 320 u32 bits, u32 words) 321{ 322 u32 dr2 = MDR2_BITLEN1(bits) | MDR2_WDLEN1(words); 323 324 if (tx_buf || (p->chipdata->master_flags & SPI_MASTER_MUST_TX)) 325 sh_msiof_write(p, TMDR2, dr2); 326 else 327 sh_msiof_write(p, TMDR2, dr2 | MDR2_GRPMASK1); 328 329 if (rx_buf) 330 sh_msiof_write(p, RMDR2, dr2); 331} 332 333static void sh_msiof_reset_str(struct sh_msiof_spi_priv *p) 334{ 335 sh_msiof_write(p, STR, sh_msiof_read(p, STR)); 336} 337 338static void sh_msiof_spi_write_fifo_8(struct sh_msiof_spi_priv *p, 339 const void *tx_buf, int words, int fs) 340{ 341 const u8 *buf_8 = tx_buf; 342 int k; 343 344 for (k = 0; k < words; k++) 345 sh_msiof_write(p, TFDR, buf_8[k] << fs); 346} 347 348static void sh_msiof_spi_write_fifo_16(struct sh_msiof_spi_priv *p, 349 const void *tx_buf, int words, int fs) 350{ 351 const u16 *buf_16 = tx_buf; 352 int k; 353 354 for (k = 0; k < words; k++) 355 sh_msiof_write(p, TFDR, buf_16[k] << fs); 356} 357 358static void sh_msiof_spi_write_fifo_16u(struct sh_msiof_spi_priv *p, 359 const void *tx_buf, int words, int fs) 360{ 361 const u16 *buf_16 = tx_buf; 362 int k; 363 364 for (k = 0; k < words; k++) 365 sh_msiof_write(p, TFDR, get_unaligned(&buf_16[k]) << fs); 366} 367 368static void sh_msiof_spi_write_fifo_32(struct sh_msiof_spi_priv *p, 369 const void *tx_buf, int words, int fs) 370{ 371 const u32 *buf_32 = tx_buf; 372 int k; 373 374 for (k = 0; k < words; k++) 375 sh_msiof_write(p, TFDR, buf_32[k] << fs); 376} 377 378static void sh_msiof_spi_write_fifo_32u(struct sh_msiof_spi_priv *p, 379 const void *tx_buf, int words, int fs) 380{ 381 const u32 *buf_32 = tx_buf; 382 int k; 383 384 for (k = 0; k < words; k++) 385 sh_msiof_write(p, TFDR, get_unaligned(&buf_32[k]) << fs); 386} 387 388static void sh_msiof_spi_write_fifo_s32(struct sh_msiof_spi_priv *p, 389 const void *tx_buf, int words, int fs) 390{ 391 const u32 *buf_32 = tx_buf; 392 int k; 393 394 for (k = 0; k < words; k++) 395 sh_msiof_write(p, TFDR, swab32(buf_32[k] << fs)); 396} 397 398static void sh_msiof_spi_write_fifo_s32u(struct sh_msiof_spi_priv *p, 399 const void *tx_buf, int words, int fs) 400{ 401 const u32 *buf_32 = tx_buf; 402 int k; 403 404 for (k = 0; k < words; k++) 405 sh_msiof_write(p, TFDR, swab32(get_unaligned(&buf_32[k]) << fs)); 406} 407 408static void sh_msiof_spi_read_fifo_8(struct sh_msiof_spi_priv *p, 409 void *rx_buf, int words, int fs) 410{ 411 u8 *buf_8 = rx_buf; 412 int k; 413 414 for (k = 0; k < words; k++) 415 buf_8[k] = sh_msiof_read(p, RFDR) >> fs; 416} 417 418static void sh_msiof_spi_read_fifo_16(struct sh_msiof_spi_priv *p, 419 void *rx_buf, int words, int fs) 420{ 421 u16 *buf_16 = rx_buf; 422 int k; 423 424 for (k = 0; k < words; k++) 425 buf_16[k] = sh_msiof_read(p, RFDR) >> fs; 426} 427 428static void sh_msiof_spi_read_fifo_16u(struct sh_msiof_spi_priv *p, 429 void *rx_buf, int words, int fs) 430{ 431 u16 *buf_16 = rx_buf; 432 int k; 433 434 for (k = 0; k < words; k++) 435 put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_16[k]); 436} 437 438static void sh_msiof_spi_read_fifo_32(struct sh_msiof_spi_priv *p, 439 void *rx_buf, int words, int fs) 440{ 441 u32 *buf_32 = rx_buf; 442 int k; 443 444 for (k = 0; k < words; k++) 445 buf_32[k] = sh_msiof_read(p, RFDR) >> fs; 446} 447 448static void sh_msiof_spi_read_fifo_32u(struct sh_msiof_spi_priv *p, 449 void *rx_buf, int words, int fs) 450{ 451 u32 *buf_32 = rx_buf; 452 int k; 453 454 for (k = 0; k < words; k++) 455 put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_32[k]); 456} 457 458static void sh_msiof_spi_read_fifo_s32(struct sh_msiof_spi_priv *p, 459 void *rx_buf, int words, int fs) 460{ 461 u32 *buf_32 = rx_buf; 462 int k; 463 464 for (k = 0; k < words; k++) 465 buf_32[k] = swab32(sh_msiof_read(p, RFDR) >> fs); 466} 467 468static void sh_msiof_spi_read_fifo_s32u(struct sh_msiof_spi_priv *p, 469 void *rx_buf, int words, int fs) 470{ 471 u32 *buf_32 = rx_buf; 472 int k; 473 474 for (k = 0; k < words; k++) 475 put_unaligned(swab32(sh_msiof_read(p, RFDR) >> fs), &buf_32[k]); 476} 477 478static int sh_msiof_spi_setup(struct spi_device *spi) 479{ 480 struct device_node *np = spi->master->dev.of_node; 481 struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master); 482 483 if (!np) { 484 /* 485 * Use spi->controller_data for CS (same strategy as spi_gpio), 486 * if any. otherwise let HW control CS 487 */ 488 spi->cs_gpio = (uintptr_t)spi->controller_data; 489 } 490 491 /* Configure pins before deasserting CS */ 492 sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL), 493 !!(spi->mode & SPI_CPHA), 494 !!(spi->mode & SPI_3WIRE), 495 !!(spi->mode & SPI_LSB_FIRST), 496 !!(spi->mode & SPI_CS_HIGH)); 497 498 if (spi->cs_gpio >= 0) 499 gpio_set_value(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH)); 500 501 return 0; 502} 503 504static int sh_msiof_prepare_message(struct spi_master *master, 505 struct spi_message *msg) 506{ 507 struct sh_msiof_spi_priv *p = spi_master_get_devdata(master); 508 const struct spi_device *spi = msg->spi; 509 510 /* Configure pins before asserting CS */ 511 sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL), 512 !!(spi->mode & SPI_CPHA), 513 !!(spi->mode & SPI_3WIRE), 514 !!(spi->mode & SPI_LSB_FIRST), 515 !!(spi->mode & SPI_CS_HIGH)); 516 return 0; 517} 518 519static int sh_msiof_spi_start(struct sh_msiof_spi_priv *p, void *rx_buf) 520{ 521 int ret; 522 523 /* setup clock and rx/tx signals */ 524 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TSCKE); 525 if (rx_buf && !ret) 526 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_RXE); 527 if (!ret) 528 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TXE); 529 530 /* start by setting frame bit */ 531 if (!ret) 532 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TFSE); 533 534 return ret; 535} 536 537static int sh_msiof_spi_stop(struct sh_msiof_spi_priv *p, void *rx_buf) 538{ 539 int ret; 540 541 /* shut down frame, rx/tx and clock signals */ 542 ret = sh_msiof_modify_ctr_wait(p, CTR_TFSE, 0); 543 if (!ret) 544 ret = sh_msiof_modify_ctr_wait(p, CTR_TXE, 0); 545 if (rx_buf && !ret) 546 ret = sh_msiof_modify_ctr_wait(p, CTR_RXE, 0); 547 if (!ret) 548 ret = sh_msiof_modify_ctr_wait(p, CTR_TSCKE, 0); 549 550 return ret; 551} 552 553static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p, 554 void (*tx_fifo)(struct sh_msiof_spi_priv *, 555 const void *, int, int), 556 void (*rx_fifo)(struct sh_msiof_spi_priv *, 557 void *, int, int), 558 const void *tx_buf, void *rx_buf, 559 int words, int bits) 560{ 561 int fifo_shift; 562 int ret; 563 564 /* limit maximum word transfer to rx/tx fifo size */ 565 if (tx_buf) 566 words = min_t(int, words, p->tx_fifo_size); 567 if (rx_buf) 568 words = min_t(int, words, p->rx_fifo_size); 569 570 /* the fifo contents need shifting */ 571 fifo_shift = 32 - bits; 572 573 /* default FIFO watermarks for PIO */ 574 sh_msiof_write(p, FCTR, 0); 575 576 /* setup msiof transfer mode registers */ 577 sh_msiof_spi_set_mode_regs(p, tx_buf, rx_buf, bits, words); 578 sh_msiof_write(p, IER, IER_TEOFE | IER_REOFE); 579 580 /* write tx fifo */ 581 if (tx_buf) 582 tx_fifo(p, tx_buf, words, fifo_shift); 583 584 reinit_completion(&p->done); 585 586 ret = sh_msiof_spi_start(p, rx_buf); 587 if (ret) { 588 dev_err(&p->pdev->dev, "failed to start hardware\n"); 589 goto stop_ier; 590 } 591 592 /* wait for tx fifo to be emptied / rx fifo to be filled */ 593 ret = wait_for_completion_timeout(&p->done, HZ); 594 if (!ret) { 595 dev_err(&p->pdev->dev, "PIO timeout\n"); 596 ret = -ETIMEDOUT; 597 goto stop_reset; 598 } 599 600 /* read rx fifo */ 601 if (rx_buf) 602 rx_fifo(p, rx_buf, words, fifo_shift); 603 604 /* clear status bits */ 605 sh_msiof_reset_str(p); 606 607 ret = sh_msiof_spi_stop(p, rx_buf); 608 if (ret) { 609 dev_err(&p->pdev->dev, "failed to shut down hardware\n"); 610 return ret; 611 } 612 613 return words; 614 615stop_reset: 616 sh_msiof_reset_str(p); 617 sh_msiof_spi_stop(p, rx_buf); 618stop_ier: 619 sh_msiof_write(p, IER, 0); 620 return ret; 621} 622 623static void sh_msiof_dma_complete(void *arg) 624{ 625 struct sh_msiof_spi_priv *p = arg; 626 627 sh_msiof_write(p, IER, 0); 628 complete(&p->done); 629} 630 631static int sh_msiof_dma_once(struct sh_msiof_spi_priv *p, const void *tx, 632 void *rx, unsigned int len) 633{ 634 u32 ier_bits = 0; 635 struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL; 636 dma_cookie_t cookie; 637 int ret; 638 639 /* First prepare and submit the DMA request(s), as this may fail */ 640 if (rx) { 641 ier_bits |= IER_RDREQE | IER_RDMAE; 642 desc_rx = dmaengine_prep_slave_single(p->master->dma_rx, 643 p->rx_dma_addr, len, DMA_FROM_DEVICE, 644 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 645 if (!desc_rx) 646 return -EAGAIN; 647 648 desc_rx->callback = sh_msiof_dma_complete; 649 desc_rx->callback_param = p; 650 cookie = dmaengine_submit(desc_rx); 651 if (dma_submit_error(cookie)) 652 return cookie; 653 } 654 655 if (tx) { 656 ier_bits |= IER_TDREQE | IER_TDMAE; 657 dma_sync_single_for_device(p->master->dma_tx->device->dev, 658 p->tx_dma_addr, len, DMA_TO_DEVICE); 659 desc_tx = dmaengine_prep_slave_single(p->master->dma_tx, 660 p->tx_dma_addr, len, DMA_TO_DEVICE, 661 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 662 if (!desc_tx) { 663 ret = -EAGAIN; 664 goto no_dma_tx; 665 } 666 667 if (rx) { 668 /* No callback */ 669 desc_tx->callback = NULL; 670 } else { 671 desc_tx->callback = sh_msiof_dma_complete; 672 desc_tx->callback_param = p; 673 } 674 cookie = dmaengine_submit(desc_tx); 675 if (dma_submit_error(cookie)) { 676 ret = cookie; 677 goto no_dma_tx; 678 } 679 } 680 681 /* 1 stage FIFO watermarks for DMA */ 682 sh_msiof_write(p, FCTR, FCTR_TFWM_1 | FCTR_RFWM_1); 683 684 /* setup msiof transfer mode registers (32-bit words) */ 685 sh_msiof_spi_set_mode_regs(p, tx, rx, 32, len / 4); 686 687 sh_msiof_write(p, IER, ier_bits); 688 689 reinit_completion(&p->done); 690 691 /* Now start DMA */ 692 if (rx) 693 dma_async_issue_pending(p->master->dma_rx); 694 if (tx) 695 dma_async_issue_pending(p->master->dma_tx); 696 697 ret = sh_msiof_spi_start(p, rx); 698 if (ret) { 699 dev_err(&p->pdev->dev, "failed to start hardware\n"); 700 goto stop_dma; 701 } 702 703 /* wait for tx fifo to be emptied / rx fifo to be filled */ 704 ret = wait_for_completion_timeout(&p->done, HZ); 705 if (!ret) { 706 dev_err(&p->pdev->dev, "DMA timeout\n"); 707 ret = -ETIMEDOUT; 708 goto stop_reset; 709 } 710 711 /* clear status bits */ 712 sh_msiof_reset_str(p); 713 714 ret = sh_msiof_spi_stop(p, rx); 715 if (ret) { 716 dev_err(&p->pdev->dev, "failed to shut down hardware\n"); 717 return ret; 718 } 719 720 if (rx) 721 dma_sync_single_for_cpu(p->master->dma_rx->device->dev, 722 p->rx_dma_addr, len, 723 DMA_FROM_DEVICE); 724 725 return 0; 726 727stop_reset: 728 sh_msiof_reset_str(p); 729 sh_msiof_spi_stop(p, rx); 730stop_dma: 731 if (tx) 732 dmaengine_terminate_all(p->master->dma_tx); 733no_dma_tx: 734 if (rx) 735 dmaengine_terminate_all(p->master->dma_rx); 736 sh_msiof_write(p, IER, 0); 737 return ret; 738} 739 740static void copy_bswap32(u32 *dst, const u32 *src, unsigned int words) 741{ 742 /* src or dst can be unaligned, but not both */ 743 if ((unsigned long)src & 3) { 744 while (words--) { 745 *dst++ = swab32(get_unaligned(src)); 746 src++; 747 } 748 } else if ((unsigned long)dst & 3) { 749 while (words--) { 750 put_unaligned(swab32(*src++), dst); 751 dst++; 752 } 753 } else { 754 while (words--) 755 *dst++ = swab32(*src++); 756 } 757} 758 759static void copy_wswap32(u32 *dst, const u32 *src, unsigned int words) 760{ 761 /* src or dst can be unaligned, but not both */ 762 if ((unsigned long)src & 3) { 763 while (words--) { 764 *dst++ = swahw32(get_unaligned(src)); 765 src++; 766 } 767 } else if ((unsigned long)dst & 3) { 768 while (words--) { 769 put_unaligned(swahw32(*src++), dst); 770 dst++; 771 } 772 } else { 773 while (words--) 774 *dst++ = swahw32(*src++); 775 } 776} 777 778static void copy_plain32(u32 *dst, const u32 *src, unsigned int words) 779{ 780 memcpy(dst, src, words * 4); 781} 782 783static int sh_msiof_transfer_one(struct spi_master *master, 784 struct spi_device *spi, 785 struct spi_transfer *t) 786{ 787 struct sh_msiof_spi_priv *p = spi_master_get_devdata(master); 788 void (*copy32)(u32 *, const u32 *, unsigned int); 789 void (*tx_fifo)(struct sh_msiof_spi_priv *, const void *, int, int); 790 void (*rx_fifo)(struct sh_msiof_spi_priv *, void *, int, int); 791 const void *tx_buf = t->tx_buf; 792 void *rx_buf = t->rx_buf; 793 unsigned int len = t->len; 794 unsigned int bits = t->bits_per_word; 795 unsigned int bytes_per_word; 796 unsigned int words; 797 int n; 798 bool swab; 799 int ret; 800 801 /* setup clocks (clock already enabled in chipselect()) */ 802 sh_msiof_spi_set_clk_regs(p, clk_get_rate(p->clk), t->speed_hz); 803 804 while (master->dma_tx && len > 15) { 805 /* 806 * DMA supports 32-bit words only, hence pack 8-bit and 16-bit 807 * words, with byte resp. word swapping. 808 */ 809 unsigned int l = min(len, MAX_WDLEN * 4); 810 811 if (bits <= 8) { 812 if (l & 3) 813 break; 814 copy32 = copy_bswap32; 815 } else if (bits <= 16) { 816 if (l & 1) 817 break; 818 copy32 = copy_wswap32; 819 } else { 820 copy32 = copy_plain32; 821 } 822 823 if (tx_buf) 824 copy32(p->tx_dma_page, tx_buf, l / 4); 825 826 ret = sh_msiof_dma_once(p, tx_buf, rx_buf, l); 827 if (ret == -EAGAIN) { 828 pr_warn_once("%s %s: DMA not available, falling back to PIO\n", 829 dev_driver_string(&p->pdev->dev), 830 dev_name(&p->pdev->dev)); 831 break; 832 } 833 if (ret) 834 return ret; 835 836 if (rx_buf) { 837 copy32(rx_buf, p->rx_dma_page, l / 4); 838 rx_buf += l; 839 } 840 if (tx_buf) 841 tx_buf += l; 842 843 len -= l; 844 if (!len) 845 return 0; 846 } 847 848 if (bits <= 8 && len > 15 && !(len & 3)) { 849 bits = 32; 850 swab = true; 851 } else { 852 swab = false; 853 } 854 855 /* setup bytes per word and fifo read/write functions */ 856 if (bits <= 8) { 857 bytes_per_word = 1; 858 tx_fifo = sh_msiof_spi_write_fifo_8; 859 rx_fifo = sh_msiof_spi_read_fifo_8; 860 } else if (bits <= 16) { 861 bytes_per_word = 2; 862 if ((unsigned long)tx_buf & 0x01) 863 tx_fifo = sh_msiof_spi_write_fifo_16u; 864 else 865 tx_fifo = sh_msiof_spi_write_fifo_16; 866 867 if ((unsigned long)rx_buf & 0x01) 868 rx_fifo = sh_msiof_spi_read_fifo_16u; 869 else 870 rx_fifo = sh_msiof_spi_read_fifo_16; 871 } else if (swab) { 872 bytes_per_word = 4; 873 if ((unsigned long)tx_buf & 0x03) 874 tx_fifo = sh_msiof_spi_write_fifo_s32u; 875 else 876 tx_fifo = sh_msiof_spi_write_fifo_s32; 877 878 if ((unsigned long)rx_buf & 0x03) 879 rx_fifo = sh_msiof_spi_read_fifo_s32u; 880 else 881 rx_fifo = sh_msiof_spi_read_fifo_s32; 882 } else { 883 bytes_per_word = 4; 884 if ((unsigned long)tx_buf & 0x03) 885 tx_fifo = sh_msiof_spi_write_fifo_32u; 886 else 887 tx_fifo = sh_msiof_spi_write_fifo_32; 888 889 if ((unsigned long)rx_buf & 0x03) 890 rx_fifo = sh_msiof_spi_read_fifo_32u; 891 else 892 rx_fifo = sh_msiof_spi_read_fifo_32; 893 } 894 895 /* transfer in fifo sized chunks */ 896 words = len / bytes_per_word; 897 898 while (words > 0) { 899 n = sh_msiof_spi_txrx_once(p, tx_fifo, rx_fifo, tx_buf, rx_buf, 900 words, bits); 901 if (n < 0) 902 return n; 903 904 if (tx_buf) 905 tx_buf += n * bytes_per_word; 906 if (rx_buf) 907 rx_buf += n * bytes_per_word; 908 words -= n; 909 } 910 911 return 0; 912} 913 914static const struct sh_msiof_chipdata sh_data = { 915 .tx_fifo_size = 64, 916 .rx_fifo_size = 64, 917 .master_flags = 0, 918}; 919 920static const struct sh_msiof_chipdata r8a779x_data = { 921 .tx_fifo_size = 64, 922 .rx_fifo_size = 256, 923 .master_flags = SPI_MASTER_MUST_TX, 924}; 925 926static const struct of_device_id sh_msiof_match[] = { 927 { .compatible = "renesas,sh-msiof", .data = &sh_data }, 928 { .compatible = "renesas,sh-mobile-msiof", .data = &sh_data }, 929 { .compatible = "renesas,msiof-r8a7790", .data = &r8a779x_data }, 930 { .compatible = "renesas,msiof-r8a7791", .data = &r8a779x_data }, 931 { .compatible = "renesas,msiof-r8a7792", .data = &r8a779x_data }, 932 { .compatible = "renesas,msiof-r8a7793", .data = &r8a779x_data }, 933 { .compatible = "renesas,msiof-r8a7794", .data = &r8a779x_data }, 934 {}, 935}; 936MODULE_DEVICE_TABLE(of, sh_msiof_match); 937 938#ifdef CONFIG_OF 939static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev) 940{ 941 struct sh_msiof_spi_info *info; 942 struct device_node *np = dev->of_node; 943 u32 num_cs = 1; 944 945 info = devm_kzalloc(dev, sizeof(struct sh_msiof_spi_info), GFP_KERNEL); 946 if (!info) 947 return NULL; 948 949 /* Parse the MSIOF properties */ 950 of_property_read_u32(np, "num-cs", &num_cs); 951 of_property_read_u32(np, "renesas,tx-fifo-size", 952 &info->tx_fifo_override); 953 of_property_read_u32(np, "renesas,rx-fifo-size", 954 &info->rx_fifo_override); 955 956 info->num_chipselect = num_cs; 957 958 return info; 959} 960#else 961static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev) 962{ 963 return NULL; 964} 965#endif 966 967static struct dma_chan *sh_msiof_request_dma_chan(struct device *dev, 968 enum dma_transfer_direction dir, unsigned int id, dma_addr_t port_addr) 969{ 970 dma_cap_mask_t mask; 971 struct dma_chan *chan; 972 struct dma_slave_config cfg; 973 int ret; 974 975 dma_cap_zero(mask); 976 dma_cap_set(DMA_SLAVE, mask); 977 978 chan = dma_request_slave_channel_compat(mask, shdma_chan_filter, 979 (void *)(unsigned long)id, dev, 980 dir == DMA_MEM_TO_DEV ? "tx" : "rx"); 981 if (!chan) { 982 dev_warn(dev, "dma_request_slave_channel_compat failed\n"); 983 return NULL; 984 } 985 986 memset(&cfg, 0, sizeof(cfg)); 987 cfg.slave_id = id; 988 cfg.direction = dir; 989 if (dir == DMA_MEM_TO_DEV) { 990 cfg.dst_addr = port_addr; 991 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 992 } else { 993 cfg.src_addr = port_addr; 994 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 995 } 996 997 ret = dmaengine_slave_config(chan, &cfg); 998 if (ret) { 999 dev_warn(dev, "dmaengine_slave_config failed %d\n", ret); 1000 dma_release_channel(chan); 1001 return NULL; 1002 } 1003 1004 return chan; 1005} 1006 1007static int sh_msiof_request_dma(struct sh_msiof_spi_priv *p) 1008{ 1009 struct platform_device *pdev = p->pdev; 1010 struct device *dev = &pdev->dev; 1011 const struct sh_msiof_spi_info *info = dev_get_platdata(dev); 1012 unsigned int dma_tx_id, dma_rx_id; 1013 const struct resource *res; 1014 struct spi_master *master; 1015 struct device *tx_dev, *rx_dev; 1016 1017 if (dev->of_node) { 1018 /* In the OF case we will get the slave IDs from the DT */ 1019 dma_tx_id = 0; 1020 dma_rx_id = 0; 1021 } else if (info && info->dma_tx_id && info->dma_rx_id) { 1022 dma_tx_id = info->dma_tx_id; 1023 dma_rx_id = info->dma_rx_id; 1024 } else { 1025 /* The driver assumes no error */ 1026 return 0; 1027 } 1028 1029 /* The DMA engine uses the second register set, if present */ 1030 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1031 if (!res) 1032 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1033 1034 master = p->master; 1035 master->dma_tx = sh_msiof_request_dma_chan(dev, DMA_MEM_TO_DEV, 1036 dma_tx_id, 1037 res->start + TFDR); 1038 if (!master->dma_tx) 1039 return -ENODEV; 1040 1041 master->dma_rx = sh_msiof_request_dma_chan(dev, DMA_DEV_TO_MEM, 1042 dma_rx_id, 1043 res->start + RFDR); 1044 if (!master->dma_rx) 1045 goto free_tx_chan; 1046 1047 p->tx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA); 1048 if (!p->tx_dma_page) 1049 goto free_rx_chan; 1050 1051 p->rx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA); 1052 if (!p->rx_dma_page) 1053 goto free_tx_page; 1054 1055 tx_dev = master->dma_tx->device->dev; 1056 p->tx_dma_addr = dma_map_single(tx_dev, p->tx_dma_page, PAGE_SIZE, 1057 DMA_TO_DEVICE); 1058 if (dma_mapping_error(tx_dev, p->tx_dma_addr)) 1059 goto free_rx_page; 1060 1061 rx_dev = master->dma_rx->device->dev; 1062 p->rx_dma_addr = dma_map_single(rx_dev, p->rx_dma_page, PAGE_SIZE, 1063 DMA_FROM_DEVICE); 1064 if (dma_mapping_error(rx_dev, p->rx_dma_addr)) 1065 goto unmap_tx_page; 1066 1067 dev_info(dev, "DMA available"); 1068 return 0; 1069 1070unmap_tx_page: 1071 dma_unmap_single(tx_dev, p->tx_dma_addr, PAGE_SIZE, DMA_TO_DEVICE); 1072free_rx_page: 1073 free_page((unsigned long)p->rx_dma_page); 1074free_tx_page: 1075 free_page((unsigned long)p->tx_dma_page); 1076free_rx_chan: 1077 dma_release_channel(master->dma_rx); 1078free_tx_chan: 1079 dma_release_channel(master->dma_tx); 1080 master->dma_tx = NULL; 1081 return -ENODEV; 1082} 1083 1084static void sh_msiof_release_dma(struct sh_msiof_spi_priv *p) 1085{ 1086 struct spi_master *master = p->master; 1087 struct device *dev; 1088 1089 if (!master->dma_tx) 1090 return; 1091 1092 dev = &p->pdev->dev; 1093 dma_unmap_single(master->dma_rx->device->dev, p->rx_dma_addr, 1094 PAGE_SIZE, DMA_FROM_DEVICE); 1095 dma_unmap_single(master->dma_tx->device->dev, p->tx_dma_addr, 1096 PAGE_SIZE, DMA_TO_DEVICE); 1097 free_page((unsigned long)p->rx_dma_page); 1098 free_page((unsigned long)p->tx_dma_page); 1099 dma_release_channel(master->dma_rx); 1100 dma_release_channel(master->dma_tx); 1101} 1102 1103static int sh_msiof_spi_probe(struct platform_device *pdev) 1104{ 1105 struct resource *r; 1106 struct spi_master *master; 1107 const struct of_device_id *of_id; 1108 struct sh_msiof_spi_priv *p; 1109 int i; 1110 int ret; 1111 1112 master = spi_alloc_master(&pdev->dev, sizeof(struct sh_msiof_spi_priv)); 1113 if (master == NULL) { 1114 dev_err(&pdev->dev, "failed to allocate spi master\n"); 1115 return -ENOMEM; 1116 } 1117 1118 p = spi_master_get_devdata(master); 1119 1120 platform_set_drvdata(pdev, p); 1121 p->master = master; 1122 1123 of_id = of_match_device(sh_msiof_match, &pdev->dev); 1124 if (of_id) { 1125 p->chipdata = of_id->data; 1126 p->info = sh_msiof_spi_parse_dt(&pdev->dev); 1127 } else { 1128 p->chipdata = (const void *)pdev->id_entry->driver_data; 1129 p->info = dev_get_platdata(&pdev->dev); 1130 } 1131 1132 if (!p->info) { 1133 dev_err(&pdev->dev, "failed to obtain device info\n"); 1134 ret = -ENXIO; 1135 goto err1; 1136 } 1137 1138 init_completion(&p->done); 1139 1140 p->clk = devm_clk_get(&pdev->dev, NULL); 1141 if (IS_ERR(p->clk)) { 1142 dev_err(&pdev->dev, "cannot get clock\n"); 1143 ret = PTR_ERR(p->clk); 1144 goto err1; 1145 } 1146 1147 i = platform_get_irq(pdev, 0); 1148 if (i < 0) { 1149 dev_err(&pdev->dev, "cannot get platform IRQ\n"); 1150 ret = -ENOENT; 1151 goto err1; 1152 } 1153 1154 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1155 p->mapbase = devm_ioremap_resource(&pdev->dev, r); 1156 if (IS_ERR(p->mapbase)) { 1157 ret = PTR_ERR(p->mapbase); 1158 goto err1; 1159 } 1160 1161 ret = devm_request_irq(&pdev->dev, i, sh_msiof_spi_irq, 0, 1162 dev_name(&pdev->dev), p); 1163 if (ret) { 1164 dev_err(&pdev->dev, "unable to request irq\n"); 1165 goto err1; 1166 } 1167 1168 p->pdev = pdev; 1169 pm_runtime_enable(&pdev->dev); 1170 1171 /* Platform data may override FIFO sizes */ 1172 p->tx_fifo_size = p->chipdata->tx_fifo_size; 1173 p->rx_fifo_size = p->chipdata->rx_fifo_size; 1174 if (p->info->tx_fifo_override) 1175 p->tx_fifo_size = p->info->tx_fifo_override; 1176 if (p->info->rx_fifo_override) 1177 p->rx_fifo_size = p->info->rx_fifo_override; 1178 1179 /* init master code */ 1180 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; 1181 master->mode_bits |= SPI_LSB_FIRST | SPI_3WIRE; 1182 master->flags = p->chipdata->master_flags; 1183 master->bus_num = pdev->id; 1184 master->dev.of_node = pdev->dev.of_node; 1185 master->num_chipselect = p->info->num_chipselect; 1186 master->setup = sh_msiof_spi_setup; 1187 master->prepare_message = sh_msiof_prepare_message; 1188 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32); 1189 master->auto_runtime_pm = true; 1190 master->transfer_one = sh_msiof_transfer_one; 1191 1192 ret = sh_msiof_request_dma(p); 1193 if (ret < 0) 1194 dev_warn(&pdev->dev, "DMA not available, using PIO\n"); 1195 1196 ret = devm_spi_register_master(&pdev->dev, master); 1197 if (ret < 0) { 1198 dev_err(&pdev->dev, "spi_register_master error.\n"); 1199 goto err2; 1200 } 1201 1202 return 0; 1203 1204 err2: 1205 sh_msiof_release_dma(p); 1206 pm_runtime_disable(&pdev->dev); 1207 err1: 1208 spi_master_put(master); 1209 return ret; 1210} 1211 1212static int sh_msiof_spi_remove(struct platform_device *pdev) 1213{ 1214 struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev); 1215 1216 sh_msiof_release_dma(p); 1217 pm_runtime_disable(&pdev->dev); 1218 return 0; 1219} 1220 1221static struct platform_device_id spi_driver_ids[] = { 1222 { "spi_sh_msiof", (kernel_ulong_t)&sh_data }, 1223 { "spi_r8a7790_msiof", (kernel_ulong_t)&r8a779x_data }, 1224 { "spi_r8a7791_msiof", (kernel_ulong_t)&r8a779x_data }, 1225 { "spi_r8a7792_msiof", (kernel_ulong_t)&r8a779x_data }, 1226 { "spi_r8a7793_msiof", (kernel_ulong_t)&r8a779x_data }, 1227 { "spi_r8a7794_msiof", (kernel_ulong_t)&r8a779x_data }, 1228 {}, 1229}; 1230MODULE_DEVICE_TABLE(platform, spi_driver_ids); 1231 1232static struct platform_driver sh_msiof_spi_drv = { 1233 .probe = sh_msiof_spi_probe, 1234 .remove = sh_msiof_spi_remove, 1235 .id_table = spi_driver_ids, 1236 .driver = { 1237 .name = "spi_sh_msiof", 1238 .owner = THIS_MODULE, 1239 .of_match_table = of_match_ptr(sh_msiof_match), 1240 }, 1241}; 1242module_platform_driver(sh_msiof_spi_drv); 1243 1244MODULE_DESCRIPTION("SuperH MSIOF SPI Master Interface Driver"); 1245MODULE_AUTHOR("Magnus Damm"); 1246MODULE_LICENSE("GPL v2"); 1247MODULE_ALIAS("platform:spi_sh_msiof"); 1248