hwdrv_apci3120.c revision f50cebb9baa5fd0e561f436bd53ffa35df16edb2
1/** 2@verbatim 3 4Copyright (C) 2004,2005 ADDI-DATA GmbH for the source code of this module. 5 6 ADDI-DATA GmbH 7 Dieselstrasse 3 8 D-77833 Ottersweier 9 Tel: +19(0)7223/9493-0 10 Fax: +49(0)7223/9493-92 11 http://www.addi-data.com 12 info@addi-data.com 13 14This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. 15 16This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. 17 18@endverbatim 19*/ 20/* 21 +-----------------------------------------------------------------------+ 22 | (C) ADDI-DATA GmbH Dieselstrasse 3 D-77833 Ottersweier | 23 +-----------------------------------------------------------------------+ 24 | Tel : +49 (0) 7223/9493-0 | email : info@addi-data.com | 25 | Fax : +49 (0) 7223/9493-92 | Internet : http://www.addi-data.com | 26 +-----------------------------------------------------------------------+ 27 | Project : APCI-3120 | Compiler : GCC | 28 | Module name : hwdrv_apci3120.c| Version : 2.96 | 29 +-------------------------------+---------------------------------------+ 30 | Project manager: Eric Stolz | Date : 02/12/2002 | 31 +-----------------------------------------------------------------------+ 32 | Description :APCI3120 Module. Hardware abstraction Layer for APCI3120| 33 +-----------------------------------------------------------------------+ 34 | UPDATE'S | 35 +-----------------------------------------------------------------------+ 36 | Date | Author | Description of updates | 37 +----------+-----------+------------------------------------------------+ 38 | | | | 39 | | | | 40 +----------+-----------+------------------------------------------------+ 41*/ 42 43#include <linux/delay.h> 44 45/* 46 * ADDON RELATED ADDITIONS 47 */ 48/* Constant */ 49#define APCI3120_ENABLE_TRANSFER_ADD_ON_LOW 0x00 50#define APCI3120_ENABLE_TRANSFER_ADD_ON_HIGH 0x1200 51#define APCI3120_A2P_FIFO_MANAGEMENT 0x04000400L 52#define APCI3120_AMWEN_ENABLE 0x02 53#define APCI3120_A2P_FIFO_WRITE_ENABLE 0x01 54#define APCI3120_FIFO_ADVANCE_ON_BYTE_2 0x20000000L 55#define APCI3120_ENABLE_WRITE_TC_INT 0x00004000L 56#define APCI3120_CLEAR_WRITE_TC_INT 0x00040000L 57#define APCI3120_DISABLE_AMWEN_AND_A2P_FIFO_WRITE 0x0 58#define APCI3120_DISABLE_BUS_MASTER_ADD_ON 0x0 59#define APCI3120_DISABLE_BUS_MASTER_PCI 0x0 60 61/* ADD_ON ::: this needed since apci supports 16 bit interface to add on */ 62#define APCI3120_ADD_ON_AGCSTS_LOW 0x3C 63#define APCI3120_ADD_ON_AGCSTS_HIGH (APCI3120_ADD_ON_AGCSTS_LOW + 2) 64#define APCI3120_ADD_ON_MWAR_LOW 0x24 65#define APCI3120_ADD_ON_MWAR_HIGH (APCI3120_ADD_ON_MWAR_LOW + 2) 66#define APCI3120_ADD_ON_MWTC_LOW 0x058 67#define APCI3120_ADD_ON_MWTC_HIGH (APCI3120_ADD_ON_MWTC_LOW + 2) 68 69/* AMCC */ 70#define APCI3120_AMCC_OP_MCSR 0x3C 71#define APCI3120_AMCC_OP_REG_INTCSR 0x38 72 73/* for transfer count enable bit */ 74#define AGCSTS_TC_ENABLE 0x10000000 75 76/* used for test on mixture of BIP/UNI ranges */ 77#define APCI3120_BIPOLAR_RANGES 4 78 79#define APCI3120_ADDRESS_RANGE 16 80 81#define APCI3120_DISABLE 0 82#define APCI3120_ENABLE 1 83 84#define APCI3120_START 1 85#define APCI3120_STOP 0 86 87#define APCI3120_EOC_MODE 1 88#define APCI3120_EOS_MODE 2 89#define APCI3120_DMA_MODE 3 90 91/* DIGITAL INPUT-OUTPUT DEFINE */ 92 93#define APCI3120_DIGITAL_OUTPUT 0x0d 94#define APCI3120_RD_STATUS 0x02 95#define APCI3120_RD_FIFO 0x00 96 97/* digital output insn_write ON /OFF selection */ 98#define APCI3120_SET4DIGITALOUTPUTON 1 99#define APCI3120_SET4DIGITALOUTPUTOFF 0 100 101/* analog output SELECT BIT */ 102#define APCI3120_ANALOG_OP_CHANNEL_1 0x0000 103#define APCI3120_ANALOG_OP_CHANNEL_2 0x4000 104#define APCI3120_ANALOG_OP_CHANNEL_3 0x8000 105#define APCI3120_ANALOG_OP_CHANNEL_4 0xc000 106#define APCI3120_ANALOG_OP_CHANNEL_5 0x0000 107#define APCI3120_ANALOG_OP_CHANNEL_6 0x4000 108#define APCI3120_ANALOG_OP_CHANNEL_7 0x8000 109#define APCI3120_ANALOG_OP_CHANNEL_8 0xc000 110 111/* Enable external trigger bit in nWrAddress */ 112#define APCI3120_ENABLE_EXT_TRIGGER 0x8000 113 114/* ANALOG OUTPUT AND INPUT DEFINE */ 115#define APCI3120_UNIPOLAR 0x80 116#define APCI3120_BIPOLAR 0x00 117#define APCI3120_ANALOG_OUTPUT_1 0x08 118#define APCI3120_ANALOG_OUTPUT_2 0x0a 119#define APCI3120_1_GAIN 0x00 120#define APCI3120_2_GAIN 0x10 121#define APCI3120_5_GAIN 0x20 122#define APCI3120_10_GAIN 0x30 123#define APCI3120_SEQ_RAM_ADDRESS 0x06 124#define APCI3120_RESET_FIFO 0x0c 125#define APCI3120_TIMER_0_MODE_2 0x01 126#define APCI3120_TIMER_0_MODE_4 0x2 127#define APCI3120_SELECT_TIMER_0_WORD 0x00 128#define APCI3120_ENABLE_TIMER0 0x1000 129#define APCI3120_CLEAR_PR 0xf0ff 130#define APCI3120_CLEAR_PA 0xfff0 131#define APCI3120_CLEAR_PA_PR (APCI3120_CLEAR_PR & APCI3120_CLEAR_PA) 132 133/* nWrMode_Select */ 134#define APCI3120_ENABLE_SCAN 0x8 135#define APCI3120_DISABLE_SCAN (~APCI3120_ENABLE_SCAN) 136#define APCI3120_ENABLE_EOS_INT 0x2 137 138#define APCI3120_DISABLE_EOS_INT (~APCI3120_ENABLE_EOS_INT) 139#define APCI3120_ENABLE_EOC_INT 0x1 140#define APCI3120_DISABLE_EOC_INT (~APCI3120_ENABLE_EOC_INT) 141#define APCI3120_DISABLE_ALL_INTERRUPT_WITHOUT_TIMER \ 142 (APCI3120_DISABLE_EOS_INT & APCI3120_DISABLE_EOC_INT) 143#define APCI3120_DISABLE_ALL_INTERRUPT \ 144 (APCI3120_DISABLE_TIMER_INT & APCI3120_DISABLE_EOS_INT & APCI3120_DISABLE_EOC_INT) 145 146/* status register bits */ 147#define APCI3120_EOC 0x8000 148#define APCI3120_EOS 0x2000 149 150/* software trigger dummy register */ 151#define APCI3120_START_CONVERSION 0x02 152 153/* TIMER DEFINE */ 154#define APCI3120_QUARTZ_A 70 155#define APCI3120_QUARTZ_B 50 156#define APCI3120_TIMER 1 157#define APCI3120_WATCHDOG 2 158#define APCI3120_TIMER_DISABLE 0 159#define APCI3120_TIMER_ENABLE 1 160#define APCI3120_ENABLE_TIMER2 0x4000 161#define APCI3120_DISABLE_TIMER2 (~APCI3120_ENABLE_TIMER2) 162#define APCI3120_ENABLE_TIMER_INT 0x04 163#define APCI3120_DISABLE_TIMER_INT (~APCI3120_ENABLE_TIMER_INT) 164#define APCI3120_WRITE_MODE_SELECT 0x0e 165#define APCI3120_SELECT_TIMER_0_WORD 0x00 166#define APCI3120_SELECT_TIMER_1_WORD 0x01 167#define APCI3120_TIMER_1_MODE_2 0x4 168 169/* $$ BIT FOR MODE IN nCsTimerCtr1 */ 170#define APCI3120_TIMER_2_MODE_0 0x0 171#define APCI3120_TIMER_2_MODE_2 0x10 172#define APCI3120_TIMER_2_MODE_5 0x30 173 174/* $$ BIT FOR MODE IN nCsTimerCtr0 */ 175#define APCI3120_SELECT_TIMER_2_LOW_WORD 0x02 176#define APCI3120_SELECT_TIMER_2_HIGH_WORD 0x03 177 178#define APCI3120_TIMER_CRT0 0x0d 179#define APCI3120_TIMER_CRT1 0x0c 180 181#define APCI3120_TIMER_VALUE 0x04 182#define APCI3120_TIMER_STATUS_REGISTER 0x0d 183#define APCI3120_RD_STATUS 0x02 184#define APCI3120_WR_ADDRESS 0x00 185#define APCI3120_ENABLE_WATCHDOG 0x20 186#define APCI3120_DISABLE_WATCHDOG (~APCI3120_ENABLE_WATCHDOG) 187#define APCI3120_ENABLE_TIMER_COUNTER 0x10 188#define APCI3120_DISABLE_TIMER_COUNTER (~APCI3120_ENABLE_TIMER_COUNTER) 189#define APCI3120_FC_TIMER 0x1000 190#define APCI3120_ENABLE_TIMER0 0x1000 191#define APCI3120_ENABLE_TIMER1 0x2000 192#define APCI3120_ENABLE_TIMER2 0x4000 193#define APCI3120_DISABLE_TIMER0 (~APCI3120_ENABLE_TIMER0) 194#define APCI3120_DISABLE_TIMER1 (~APCI3120_ENABLE_TIMER1) 195#define APCI3120_DISABLE_TIMER2 (~APCI3120_ENABLE_TIMER2) 196 197#define APCI3120_TIMER2_SELECT_EOS 0xc0 198#define APCI3120_COUNTER 3 199#define APCI3120_DISABLE_ALL_TIMER (APCI3120_DISABLE_TIMER0 & \ 200 APCI3120_DISABLE_TIMER1 & \ 201 APCI3120_DISABLE_TIMER2) 202 203#define MAX_ANALOGINPUT_CHANNELS 32 204 205struct str_AnalogReadInformation { 206 /* EOC or EOS */ 207 unsigned char b_Type; 208 /* Interrupt use or not */ 209 unsigned char b_InterruptFlag; 210 /* Selection of the conversion time */ 211 unsigned int ui_ConvertTiming; 212 /* Number of channel to read */ 213 unsigned char b_NbrOfChannel; 214 /* Number of the channel to be read */ 215 unsigned int ui_ChannelList[MAX_ANALOGINPUT_CHANNELS]; 216 /* Gain of each channel */ 217 unsigned int ui_RangeList[MAX_ANALOGINPUT_CHANNELS]; 218}; 219 220/* ANALOG INPUT RANGE */ 221static const struct comedi_lrange range_apci3120_ai = { 222 8, { 223 BIP_RANGE(10), 224 BIP_RANGE(5), 225 BIP_RANGE(2), 226 BIP_RANGE(1), 227 UNI_RANGE(10), 228 UNI_RANGE(5), 229 UNI_RANGE(2), 230 UNI_RANGE(1) 231 } 232}; 233 234/* ANALOG OUTPUT RANGE */ 235static const struct comedi_lrange range_apci3120_ao = { 236 2, { 237 BIP_RANGE(10), 238 UNI_RANGE(10) 239 } 240}; 241 242 243/* FUNCTION DEFINITIONS */ 244 245/* 246+----------------------------------------------------------------------------+ 247| ANALOG INPUT SUBDEVICE | 248+----------------------------------------------------------------------------+ 249*/ 250 251static int apci3120_ai_insn_config(struct comedi_device *dev, 252 struct comedi_subdevice *s, 253 struct comedi_insn *insn, 254 unsigned int *data) 255{ 256 const struct addi_board *this_board = comedi_board(dev); 257 struct addi_private *devpriv = dev->private; 258 unsigned int i; 259 260 if ((data[0] != APCI3120_EOC_MODE) && (data[0] != APCI3120_EOS_MODE)) 261 return -1; 262 263 /* Check for Conversion time to be added ?? */ 264 devpriv->ui_EocEosConversionTime = data[2]; 265 266 if (data[0] == APCI3120_EOS_MODE) { 267 268 /* Test the number of the channel */ 269 for (i = 0; i < data[3]; i++) { 270 271 if (CR_CHAN(data[4 + i]) >= 272 this_board->i_NbrAiChannel) { 273 printk("bad channel list\n"); 274 return -2; 275 } 276 } 277 278 devpriv->b_InterruptMode = APCI3120_EOS_MODE; 279 280 if (data[1]) 281 devpriv->b_EocEosInterrupt = APCI3120_ENABLE; 282 else 283 devpriv->b_EocEosInterrupt = APCI3120_DISABLE; 284 /* Copy channel list and Range List to devpriv */ 285 286 devpriv->ui_AiNbrofChannels = data[3]; 287 for (i = 0; i < devpriv->ui_AiNbrofChannels; i++) 288 devpriv->ui_AiChannelList[i] = data[4 + i]; 289 290 } else { /* EOC */ 291 devpriv->b_InterruptMode = APCI3120_EOC_MODE; 292 if (data[1]) 293 devpriv->b_EocEosInterrupt = APCI3120_ENABLE; 294 else 295 devpriv->b_EocEosInterrupt = APCI3120_DISABLE; 296 } 297 298 return insn->n; 299} 300 301/* 302 * This function will first check channel list is ok or not and then 303 * initialize the sequence RAM with the polarity, Gain,Channel number. 304 * If the last argument of function "check"is 1 then it only checks 305 * the channel list is ok or not. 306 */ 307static int apci3120_setup_chan_list(struct comedi_device *dev, 308 struct comedi_subdevice *s, 309 int n_chan, 310 unsigned int *chanlist, 311 char check) 312{ 313 struct addi_private *devpriv = dev->private; 314 unsigned int i; /* , differencial=0, bipolar=0; */ 315 unsigned int gain; 316 unsigned short us_TmpValue; 317 318 /* correct channel and range number check itself comedi/range.c */ 319 if (n_chan < 1) { 320 if (!check) 321 comedi_error(dev, "range/channel list is empty!"); 322 return 0; 323 } 324 /* All is ok, so we can setup channel/range list */ 325 if (check) 326 return 1; 327 328 /* Code to set the PA and PR...Here it set PA to 0.. */ 329 devpriv->us_OutputRegister = 330 devpriv->us_OutputRegister & APCI3120_CLEAR_PA_PR; 331 devpriv->us_OutputRegister = ((n_chan - 1) & 0xf) << 8; 332 outw(devpriv->us_OutputRegister, dev->iobase + APCI3120_WR_ADDRESS); 333 334 for (i = 0; i < n_chan; i++) { 335 /* store range list to card */ 336 us_TmpValue = CR_CHAN(chanlist[i]); /* get channel number; */ 337 338 if (CR_RANGE(chanlist[i]) < APCI3120_BIPOLAR_RANGES) 339 us_TmpValue &= ((~APCI3120_UNIPOLAR) & 0xff); /* set bipolar */ 340 else 341 us_TmpValue |= APCI3120_UNIPOLAR; /* enable unipolar...... */ 342 343 gain = CR_RANGE(chanlist[i]); /* get gain number */ 344 us_TmpValue |= ((gain & 0x03) << 4); /* <<4 for G0 and G1 bit in RAM */ 345 us_TmpValue |= i << 8; /* To select the RAM LOCATION.... */ 346 outw(us_TmpValue, dev->iobase + APCI3120_SEQ_RAM_ADDRESS); 347 348 printk("\n Gain = %i", 349 (((unsigned char)CR_RANGE(chanlist[i]) & 0x03) << 2)); 350 printk("\n Channel = %i", CR_CHAN(chanlist[i])); 351 printk("\n Polarity = %i", us_TmpValue & APCI3120_UNIPOLAR); 352 } 353 return 1; /* we can serve this with scan logic */ 354} 355 356/* 357 * Reads analog input in synchronous mode EOC and EOS is selected 358 * as per configured if no conversion time is set uses default 359 * conversion time 10 microsec. 360 */ 361static int apci3120_ai_insn_read(struct comedi_device *dev, 362 struct comedi_subdevice *s, 363 struct comedi_insn *insn, 364 unsigned int *data) 365{ 366 const struct addi_board *this_board = comedi_board(dev); 367 struct addi_private *devpriv = dev->private; 368 unsigned short us_ConvertTiming, us_TmpValue, i; 369 unsigned char b_Tmp; 370 371 /* fix conversion time to 10 us */ 372 if (!devpriv->ui_EocEosConversionTime) { 373 printk("No timer0 Value using 10 us\n"); 374 us_ConvertTiming = 10; 375 } else 376 us_ConvertTiming = (unsigned short) (devpriv->ui_EocEosConversionTime / 1000); /* nano to useconds */ 377 378 /* this_board->ai_read(dev,us_ConvertTiming,insn->n,&insn->chanspec,data,insn->unused[0]); */ 379 380 /* Clear software registers */ 381 devpriv->b_TimerSelectMode = 0; 382 devpriv->b_ModeSelectRegister = 0; 383 devpriv->us_OutputRegister = 0; 384/* devpriv->b_DigitalOutputRegister=0; */ 385 386 if (insn->unused[0] == 222) { /* second insn read */ 387 for (i = 0; i < insn->n; i++) 388 data[i] = devpriv->ui_AiReadData[i]; 389 } else { 390 devpriv->tsk_Current = current; /* Save the current process task structure */ 391/* 392 * Testing if board have the new Quartz and calculate the time value 393 * to set in the timer 394 */ 395 396 us_TmpValue = 397 (unsigned short) inw(devpriv->iobase + APCI3120_RD_STATUS); 398 399 /* EL250804: Testing if board APCI3120 have the new Quartz or if it is an APCI3001 */ 400 if ((us_TmpValue & 0x00B0) == 0x00B0 401 || !strcmp(this_board->pc_DriverName, "apci3001")) { 402 us_ConvertTiming = (us_ConvertTiming * 2) - 2; 403 } else { 404 us_ConvertTiming = 405 ((us_ConvertTiming * 12926) / 10000) - 1; 406 } 407 408 us_TmpValue = (unsigned short) devpriv->b_InterruptMode; 409 410 switch (us_TmpValue) { 411 412 case APCI3120_EOC_MODE: 413 414/* 415 * Testing the interrupt flag and set the EOC bit Clears the FIFO 416 */ 417 inw(devpriv->iobase + APCI3120_RESET_FIFO); 418 419 /* Initialize the sequence array */ 420 if (!apci3120_setup_chan_list(dev, s, 1, 421 &insn->chanspec, 0)) 422 return -EINVAL; 423 424 /* Initialize Timer 0 mode 4 */ 425 devpriv->b_TimerSelectMode = 426 (devpriv-> 427 b_TimerSelectMode & 0xFC) | 428 APCI3120_TIMER_0_MODE_4; 429 outb(devpriv->b_TimerSelectMode, 430 devpriv->iobase + APCI3120_TIMER_CRT1); 431 432 /* Reset the scan bit and Disables the EOS, DMA, EOC interrupt */ 433 devpriv->b_ModeSelectRegister = 434 devpriv-> 435 b_ModeSelectRegister & APCI3120_DISABLE_SCAN; 436 437 if (devpriv->b_EocEosInterrupt == APCI3120_ENABLE) { 438 439 /* Disables the EOS,DMA and enables the EOC interrupt */ 440 devpriv->b_ModeSelectRegister = 441 (devpriv-> 442 b_ModeSelectRegister & 443 APCI3120_DISABLE_EOS_INT) | 444 APCI3120_ENABLE_EOC_INT; 445 inw(devpriv->iobase); 446 447 } else { 448 devpriv->b_ModeSelectRegister = 449 devpriv-> 450 b_ModeSelectRegister & 451 APCI3120_DISABLE_ALL_INTERRUPT_WITHOUT_TIMER; 452 } 453 454 outb(devpriv->b_ModeSelectRegister, 455 devpriv->iobase + APCI3120_WRITE_MODE_SELECT); 456 457 /* Sets gate 0 */ 458 devpriv->us_OutputRegister = 459 (devpriv-> 460 us_OutputRegister & APCI3120_CLEAR_PA_PR) | 461 APCI3120_ENABLE_TIMER0; 462 outw(devpriv->us_OutputRegister, 463 devpriv->iobase + APCI3120_WR_ADDRESS); 464 465 /* Select Timer 0 */ 466 b_Tmp = ((devpriv-> 467 b_DigitalOutputRegister) & 0xF0) | 468 APCI3120_SELECT_TIMER_0_WORD; 469 outb(b_Tmp, devpriv->iobase + APCI3120_TIMER_CRT0); 470 471 /* Set the conversion time */ 472 outw(us_ConvertTiming, 473 devpriv->iobase + APCI3120_TIMER_VALUE); 474 475 us_TmpValue = 476 (unsigned short) inw(dev->iobase + APCI3120_RD_STATUS); 477 478 if (devpriv->b_EocEosInterrupt == APCI3120_DISABLE) { 479 480 do { 481 /* Waiting for the end of conversion */ 482 us_TmpValue = 483 inw(devpriv->iobase + 484 APCI3120_RD_STATUS); 485 } while ((us_TmpValue & APCI3120_EOC) == 486 APCI3120_EOC); 487 488 /* Read the result in FIFO and put it in insn data pointer */ 489 us_TmpValue = inw(devpriv->iobase + 0); 490 *data = us_TmpValue; 491 492 inw(devpriv->iobase + APCI3120_RESET_FIFO); 493 } 494 495 break; 496 497 case APCI3120_EOS_MODE: 498 499 inw(devpriv->iobase); 500 /* Clears the FIFO */ 501 inw(devpriv->iobase + APCI3120_RESET_FIFO); 502 /* clear PA PR and disable timer 0 */ 503 504 devpriv->us_OutputRegister = 505 (devpriv-> 506 us_OutputRegister & APCI3120_CLEAR_PA_PR) | 507 APCI3120_DISABLE_TIMER0; 508 509 outw(devpriv->us_OutputRegister, 510 devpriv->iobase + APCI3120_WR_ADDRESS); 511 512 if (!apci3120_setup_chan_list(dev, s, 513 devpriv->ui_AiNbrofChannels, 514 devpriv->ui_AiChannelList, 0)) 515 return -EINVAL; 516 517 /* Initialize Timer 0 mode 2 */ 518 devpriv->b_TimerSelectMode = 519 (devpriv-> 520 b_TimerSelectMode & 0xFC) | 521 APCI3120_TIMER_0_MODE_2; 522 outb(devpriv->b_TimerSelectMode, 523 devpriv->iobase + APCI3120_TIMER_CRT1); 524 525 /* Select Timer 0 */ 526 b_Tmp = ((devpriv-> 527 b_DigitalOutputRegister) & 0xF0) | 528 APCI3120_SELECT_TIMER_0_WORD; 529 outb(b_Tmp, devpriv->iobase + APCI3120_TIMER_CRT0); 530 531 /* Set the conversion time */ 532 outw(us_ConvertTiming, 533 devpriv->iobase + APCI3120_TIMER_VALUE); 534 535 /* Set the scan bit */ 536 devpriv->b_ModeSelectRegister = 537 devpriv-> 538 b_ModeSelectRegister | APCI3120_ENABLE_SCAN; 539 outb(devpriv->b_ModeSelectRegister, 540 devpriv->iobase + APCI3120_WRITE_MODE_SELECT); 541 542 /* If Interrupt function is loaded */ 543 if (devpriv->b_EocEosInterrupt == APCI3120_ENABLE) { 544 /* Disables the EOC,DMA and enables the EOS interrupt */ 545 devpriv->b_ModeSelectRegister = 546 (devpriv-> 547 b_ModeSelectRegister & 548 APCI3120_DISABLE_EOC_INT) | 549 APCI3120_ENABLE_EOS_INT; 550 inw(devpriv->iobase); 551 552 } else 553 devpriv->b_ModeSelectRegister = 554 devpriv-> 555 b_ModeSelectRegister & 556 APCI3120_DISABLE_ALL_INTERRUPT_WITHOUT_TIMER; 557 558 outb(devpriv->b_ModeSelectRegister, 559 devpriv->iobase + APCI3120_WRITE_MODE_SELECT); 560 561 inw(devpriv->iobase + APCI3120_RD_STATUS); 562 563 /* Sets gate 0 */ 564 565 devpriv->us_OutputRegister = 566 devpriv-> 567 us_OutputRegister | APCI3120_ENABLE_TIMER0; 568 outw(devpriv->us_OutputRegister, 569 devpriv->iobase + APCI3120_WR_ADDRESS); 570 571 /* Start conversion */ 572 outw(0, devpriv->iobase + APCI3120_START_CONVERSION); 573 574 /* Waiting of end of conversion if interrupt is not installed */ 575 if (devpriv->b_EocEosInterrupt == APCI3120_DISABLE) { 576 /* Waiting the end of conversion */ 577 do { 578 us_TmpValue = 579 inw(devpriv->iobase + 580 APCI3120_RD_STATUS); 581 } while ((us_TmpValue & APCI3120_EOS) != 582 APCI3120_EOS); 583 584 for (i = 0; i < devpriv->ui_AiNbrofChannels; 585 i++) { 586 /* Read the result in FIFO and write them in shared memory */ 587 us_TmpValue = inw(devpriv->iobase); 588 data[i] = (unsigned int) us_TmpValue; 589 } 590 591 devpriv->b_InterruptMode = APCI3120_EOC_MODE; /* Restore defaults. */ 592 } 593 break; 594 595 default: 596 printk("inputs wrong\n"); 597 598 } 599 devpriv->ui_EocEosConversionTime = 0; /* re initializing the variable; */ 600 } 601 602 return insn->n; 603 604} 605 606static int apci3120_reset(struct comedi_device *dev) 607{ 608 struct addi_private *devpriv = dev->private; 609 unsigned int i; 610 unsigned short us_TmpValue; 611 612 devpriv->b_AiCyclicAcquisition = APCI3120_DISABLE; 613 devpriv->b_EocEosInterrupt = APCI3120_DISABLE; 614 devpriv->b_InterruptMode = APCI3120_EOC_MODE; 615 devpriv->ui_EocEosConversionTime = 0; /* set eoc eos conv time to 0 */ 616 devpriv->b_OutputMemoryStatus = 0; 617 618 /* variables used in timer subdevice */ 619 devpriv->b_Timer2Mode = 0; 620 devpriv->b_Timer2Interrupt = 0; 621 devpriv->b_ExttrigEnable = 0; /* Disable ext trigger */ 622 623 /* Disable all interrupts, watchdog for the anolog output */ 624 devpriv->b_ModeSelectRegister = 0; 625 outb(devpriv->b_ModeSelectRegister, 626 dev->iobase + APCI3120_WRITE_MODE_SELECT); 627 628 /* Disables all counters, ext trigger and clears PA, PR */ 629 devpriv->us_OutputRegister = 0; 630 outw(devpriv->us_OutputRegister, dev->iobase + APCI3120_WR_ADDRESS); 631 632/* 633 * Code to set the all anolog o/p channel to 0v 8191 is decimal 634 * value for zero(0 v)volt in bipolar mode(default) 635 */ 636 outw(8191 | APCI3120_ANALOG_OP_CHANNEL_1, dev->iobase + APCI3120_ANALOG_OUTPUT_1); /* channel 1 */ 637 outw(8191 | APCI3120_ANALOG_OP_CHANNEL_2, dev->iobase + APCI3120_ANALOG_OUTPUT_1); /* channel 2 */ 638 outw(8191 | APCI3120_ANALOG_OP_CHANNEL_3, dev->iobase + APCI3120_ANALOG_OUTPUT_1); /* channel 3 */ 639 outw(8191 | APCI3120_ANALOG_OP_CHANNEL_4, dev->iobase + APCI3120_ANALOG_OUTPUT_1); /* channel 4 */ 640 641 outw(8191 | APCI3120_ANALOG_OP_CHANNEL_5, dev->iobase + APCI3120_ANALOG_OUTPUT_2); /* channel 5 */ 642 outw(8191 | APCI3120_ANALOG_OP_CHANNEL_6, dev->iobase + APCI3120_ANALOG_OUTPUT_2); /* channel 6 */ 643 outw(8191 | APCI3120_ANALOG_OP_CHANNEL_7, dev->iobase + APCI3120_ANALOG_OUTPUT_2); /* channel 7 */ 644 outw(8191 | APCI3120_ANALOG_OP_CHANNEL_8, dev->iobase + APCI3120_ANALOG_OUTPUT_2); /* channel 8 */ 645 646 /* Reset digital output to L0W */ 647 648/* ES05 outb(0x0,dev->iobase+APCI3120_DIGITAL_OUTPUT); */ 649 udelay(10); 650 651 inw(dev->iobase + 0); /* make a dummy read */ 652 inb(dev->iobase + APCI3120_RESET_FIFO); /* flush FIFO */ 653 inw(dev->iobase + APCI3120_RD_STATUS); /* flush A/D status register */ 654 655 /* code to reset the RAM sequence */ 656 for (i = 0; i < 16; i++) { 657 us_TmpValue = i << 8; /* select the location */ 658 outw(us_TmpValue, dev->iobase + APCI3120_SEQ_RAM_ADDRESS); 659 } 660 return 0; 661} 662 663static int apci3120_exttrig_enable(struct comedi_device *dev) 664{ 665 struct addi_private *devpriv = dev->private; 666 667 devpriv->us_OutputRegister |= APCI3120_ENABLE_EXT_TRIGGER; 668 outw(devpriv->us_OutputRegister, dev->iobase + APCI3120_WR_ADDRESS); 669 return 0; 670} 671 672static int apci3120_exttrig_disable(struct comedi_device *dev) 673{ 674 struct addi_private *devpriv = dev->private; 675 676 devpriv->us_OutputRegister &= ~APCI3120_ENABLE_EXT_TRIGGER; 677 outw(devpriv->us_OutputRegister, dev->iobase + APCI3120_WR_ADDRESS); 678 return 0; 679} 680 681static int apci3120_cancel(struct comedi_device *dev, 682 struct comedi_subdevice *s) 683{ 684 struct addi_private *devpriv = dev->private; 685 686 /* Disable A2P Fifo write and AMWEN signal */ 687 outw(0, devpriv->i_IobaseAddon + 4); 688 689 /* Disable Bus Master ADD ON */ 690 outw(APCI3120_ADD_ON_AGCSTS_LOW, devpriv->i_IobaseAddon + 0); 691 outw(0, devpriv->i_IobaseAddon + 2); 692 outw(APCI3120_ADD_ON_AGCSTS_HIGH, devpriv->i_IobaseAddon + 0); 693 outw(0, devpriv->i_IobaseAddon + 2); 694 695 /* Disable BUS Master PCI */ 696 outl(0, devpriv->i_IobaseAmcc + AMCC_OP_REG_MCSR); 697 698 /* outl(inl(devpriv->i_IobaseAmcc+AMCC_OP_REG_INTCSR)&(~AINT_WRITE_COMPL), 699 * devpriv->i_IobaseAmcc+AMCC_OP_REG_INTCSR); stop amcc irqs */ 700 701 /* outl(inl(devpriv->i_IobaseAmcc+AMCC_OP_REG_MCSR)&(~EN_A2P_TRANSFERS), 702 * devpriv->i_IobaseAmcc+AMCC_OP_REG_MCSR); stop DMA */ 703 704 /* Disable ext trigger */ 705 apci3120_exttrig_disable(dev); 706 707 devpriv->us_OutputRegister = 0; 708 /* stop counters */ 709 outw(devpriv-> 710 us_OutputRegister & APCI3120_DISABLE_TIMER0 & 711 APCI3120_DISABLE_TIMER1, dev->iobase + APCI3120_WR_ADDRESS); 712 713 outw(APCI3120_DISABLE_ALL_TIMER, dev->iobase + APCI3120_WR_ADDRESS); 714 715 /* DISABLE_ALL_INTERRUPT */ 716 outb(APCI3120_DISABLE_ALL_INTERRUPT, 717 dev->iobase + APCI3120_WRITE_MODE_SELECT); 718 /* Flush FIFO */ 719 inb(dev->iobase + APCI3120_RESET_FIFO); 720 inw(dev->iobase + APCI3120_RD_STATUS); 721 devpriv->ui_AiActualScan = 0; 722 s->async->cur_chan = 0; 723 devpriv->b_AiContinuous = 0; 724 devpriv->ui_DmaActualBuffer = 0; 725 726 devpriv->b_AiCyclicAcquisition = APCI3120_DISABLE; 727 devpriv->b_InterruptMode = APCI3120_EOC_MODE; 728 devpriv->b_EocEosInterrupt = APCI3120_DISABLE; 729 apci3120_reset(dev); 730 return 0; 731} 732 733static int apci3120_ai_cmdtest(struct comedi_device *dev, 734 struct comedi_subdevice *s, 735 struct comedi_cmd *cmd) 736{ 737 int err = 0; 738 739 /* Step 1 : check if triggers are trivially valid */ 740 741 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_EXT); 742 err |= cfc_check_trigger_src(&cmd->scan_begin_src, 743 TRIG_TIMER | TRIG_FOLLOW); 744 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_TIMER); 745 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT); 746 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE); 747 748 if (err) 749 return 1; 750 751 /* Step 2a : make sure trigger sources are unique */ 752 753 err |= cfc_check_trigger_is_unique(cmd->start_src); 754 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src); 755 err |= cfc_check_trigger_is_unique(cmd->stop_src); 756 757 /* Step 2b : and mutually compatible */ 758 759 if (err) 760 return 2; 761 762 /* Step 3: check if arguments are trivially valid */ 763 764 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0); 765 766 if (cmd->scan_begin_src == TRIG_TIMER) /* Test Delay timing */ 767 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg, 100000); 768 769 if (cmd->convert_src == TRIG_TIMER) { /* Test Acquisition timing */ 770 if (cmd->scan_begin_src == TRIG_TIMER) { 771 if (cmd->convert_arg) 772 err |= cfc_check_trigger_arg_min( 773 &cmd->convert_arg, 10000); 774 } else { 775 err |= cfc_check_trigger_arg_min(&cmd->convert_arg, 776 10000); 777 } 778 } 779 780 err |= cfc_check_trigger_arg_min(&cmd->chanlist_len, 1); 781 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len); 782 783 if (cmd->stop_src == TRIG_COUNT) 784 err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1); 785 else /* TRIG_NONE */ 786 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0); 787 788 if (err) 789 return 3; 790 791 /* step 4: fix up any arguments */ 792 793 if (cmd->convert_src == TRIG_TIMER) { 794 795 if (cmd->scan_begin_src == TRIG_TIMER && 796 cmd->scan_begin_arg < 797 cmd->convert_arg * cmd->scan_end_arg) { 798 cmd->scan_begin_arg = 799 cmd->convert_arg * cmd->scan_end_arg; 800 err++; 801 } 802 } 803 804 if (err) 805 return 4; 806 807 return 0; 808} 809 810/* 811 * This is used for analog input cyclic acquisition. 812 * Performs the command operations. 813 * If DMA is configured does DMA initialization otherwise does the 814 * acquisition with EOS interrupt. 815 */ 816static int apci3120_cyclic_ai(int mode, 817 struct comedi_device *dev, 818 struct comedi_subdevice *s) 819{ 820 const struct addi_board *this_board = comedi_board(dev); 821 struct addi_private *devpriv = dev->private; 822 unsigned char b_Tmp; 823 unsigned int ui_Tmp, ui_DelayTiming = 0, ui_TimerValue1 = 0, dmalen0 = 824 0, dmalen1 = 0, ui_TimerValue2 = 825 0, ui_TimerValue0, ui_ConvertTiming; 826 unsigned short us_TmpValue; 827 828 /* BEGIN JK 07.05.04: Comparison between WIN32 and Linux driver */ 829 /* devpriv->b_AiCyclicAcquisition=APCI3120_ENABLE; */ 830 /* END JK 07.05.04: Comparison between WIN32 and Linux driver */ 831 832 /*******************/ 833 /* Resets the FIFO */ 834 /*******************/ 835 inb(dev->iobase + APCI3120_RESET_FIFO); 836 837 /* BEGIN JK 07.05.04: Comparison between WIN32 and Linux driver */ 838 /* inw(dev->iobase+APCI3120_RD_STATUS); */ 839 /* END JK 07.05.04: Comparison between WIN32 and Linux driver */ 840 841 /***************************/ 842 /* Acquisition initialized */ 843 /***************************/ 844 /* BEGIN JK 07.05.04: Comparison between WIN32 and Linux driver */ 845 devpriv->b_AiCyclicAcquisition = APCI3120_ENABLE; 846 /* END JK 07.05.04: Comparison between WIN32 and Linux driver */ 847 848 /* clear software registers */ 849 devpriv->b_TimerSelectMode = 0; 850 devpriv->us_OutputRegister = 0; 851 devpriv->b_ModeSelectRegister = 0; 852 /* devpriv->b_DigitalOutputRegister=0; */ 853 854 /* COMMENT JK 07.05.04: Followings calls are in i_APCI3120_StartAnalogInputAcquisition */ 855 856 /****************************/ 857 /* Clear Timer Write TC int */ 858 /****************************/ 859 outl(APCI3120_CLEAR_WRITE_TC_INT, 860 devpriv->i_IobaseAmcc + APCI3120_AMCC_OP_REG_INTCSR); 861 862 /************************************/ 863 /* Clears the timer status register */ 864 /************************************/ 865 866 /* BEGIN JK 07.05.04: Comparison between WIN32 and Linux driver */ 867 /* inw(dev->iobase+APCI3120_TIMER_STATUS_REGISTER); */ 868 /* inb(dev->iobase + APCI3120_TIMER_STATUS_REGISTER); */ 869 /* END JK 07.05.04: Comparison between WIN32 and Linux driver */ 870 871 /**************************/ 872 /* Disables All Timer */ 873 /* Sets PR and PA to 0 */ 874 /**************************/ 875 devpriv->us_OutputRegister = devpriv->us_OutputRegister & 876 APCI3120_DISABLE_TIMER0 & 877 APCI3120_DISABLE_TIMER1 & APCI3120_CLEAR_PA_PR; 878 879 outw(devpriv->us_OutputRegister, dev->iobase + APCI3120_WR_ADDRESS); 880 881 /*******************/ 882 /* Resets the FIFO */ 883 /*******************/ 884 /* BEGIN JK 07.05.04: Comparison between WIN32 and Linux driver */ 885 inb(devpriv->iobase + APCI3120_RESET_FIFO); 886 /* END JK 07.05.04: Comparison between WIN32 and Linux driver */ 887 888 devpriv->ui_AiActualScan = 0; 889 s->async->cur_chan = 0; 890 devpriv->ui_DmaActualBuffer = 0; 891 892 /* value for timer2 minus -2 has to be done .....dunno y?? */ 893 ui_TimerValue2 = devpriv->ui_AiNbrofScans - 2; 894 ui_ConvertTiming = devpriv->ui_AiTimer0; 895 896 if (mode == 2) 897 ui_DelayTiming = devpriv->ui_AiTimer1; 898 899 /**********************************/ 900 /* Initializes the sequence array */ 901 /**********************************/ 902 if (!apci3120_setup_chan_list(dev, s, devpriv->ui_AiNbrofChannels, 903 devpriv->pui_AiChannelList, 0)) 904 return -EINVAL; 905 906 us_TmpValue = (unsigned short) inw(dev->iobase + APCI3120_RD_STATUS); 907/*** EL241003 : add this section in comment because floats must not be used 908 if((us_TmpValue & 0x00B0)==0x00B0) 909 { 910 f_ConvertValue=(((float)ui_ConvertTiming * 0.002) - 2); 911 ui_TimerValue0=(unsigned int)f_ConvertValue; 912 if (mode==2) 913 { 914 f_DelayValue = (((float)ui_DelayTiming * 0.00002) - 2); 915 ui_TimerValue1 = (unsigned int) f_DelayValue; 916 } 917 } 918 else 919 { 920 f_ConvertValue=(((float)ui_ConvertTiming * 0.0012926) - 1); 921 ui_TimerValue0=(unsigned int)f_ConvertValue; 922 if (mode == 2) 923 { 924 f_DelayValue = (((float)ui_DelayTiming * 0.000012926) - 1); 925 ui_TimerValue1 = (unsigned int) f_DelayValue; 926 } 927 } 928***********************************************************************************************/ 929/*** EL241003 Begin : add this section to replace floats calculation by integer calculations **/ 930 /* EL250804: Testing if board APCI3120 have the new Quartz or if it is an APCI3001 */ 931 if ((us_TmpValue & 0x00B0) == 0x00B0 932 || !strcmp(this_board->pc_DriverName, "apci3001")) { 933 ui_TimerValue0 = ui_ConvertTiming * 2 - 2000; 934 ui_TimerValue0 = ui_TimerValue0 / 1000; 935 936 if (mode == 2) { 937 ui_DelayTiming = ui_DelayTiming / 1000; 938 ui_TimerValue1 = ui_DelayTiming * 2 - 200; 939 ui_TimerValue1 = ui_TimerValue1 / 100; 940 } 941 } else { 942 ui_ConvertTiming = ui_ConvertTiming / 1000; 943 ui_TimerValue0 = ui_ConvertTiming * 12926 - 10000; 944 ui_TimerValue0 = ui_TimerValue0 / 10000; 945 946 if (mode == 2) { 947 ui_DelayTiming = ui_DelayTiming / 1000; 948 ui_TimerValue1 = ui_DelayTiming * 12926 - 1; 949 ui_TimerValue1 = ui_TimerValue1 / 1000000; 950 } 951 } 952/*** EL241003 End ******************************************************************************/ 953 954 if (devpriv->b_ExttrigEnable == APCI3120_ENABLE) 955 apci3120_exttrig_enable(dev); /* activate EXT trigger */ 956 switch (mode) { 957 case 1: 958 /* init timer0 in mode 2 */ 959 devpriv->b_TimerSelectMode = 960 (devpriv-> 961 b_TimerSelectMode & 0xFC) | APCI3120_TIMER_0_MODE_2; 962 outb(devpriv->b_TimerSelectMode, 963 dev->iobase + APCI3120_TIMER_CRT1); 964 965 /* Select Timer 0 */ 966 b_Tmp = ((devpriv-> 967 b_DigitalOutputRegister) & 0xF0) | 968 APCI3120_SELECT_TIMER_0_WORD; 969 outb(b_Tmp, dev->iobase + APCI3120_TIMER_CRT0); 970 /* Set the conversion time */ 971 outw(((unsigned short) ui_TimerValue0), 972 dev->iobase + APCI3120_TIMER_VALUE); 973 break; 974 975 case 2: 976 /* init timer1 in mode 2 */ 977 devpriv->b_TimerSelectMode = 978 (devpriv-> 979 b_TimerSelectMode & 0xF3) | APCI3120_TIMER_1_MODE_2; 980 outb(devpriv->b_TimerSelectMode, 981 dev->iobase + APCI3120_TIMER_CRT1); 982 983 /* Select Timer 1 */ 984 b_Tmp = ((devpriv-> 985 b_DigitalOutputRegister) & 0xF0) | 986 APCI3120_SELECT_TIMER_1_WORD; 987 outb(b_Tmp, dev->iobase + APCI3120_TIMER_CRT0); 988 /* Set the conversion time */ 989 outw(((unsigned short) ui_TimerValue1), 990 dev->iobase + APCI3120_TIMER_VALUE); 991 992 /* init timer0 in mode 2 */ 993 devpriv->b_TimerSelectMode = 994 (devpriv-> 995 b_TimerSelectMode & 0xFC) | APCI3120_TIMER_0_MODE_2; 996 outb(devpriv->b_TimerSelectMode, 997 dev->iobase + APCI3120_TIMER_CRT1); 998 999 /* Select Timer 0 */ 1000 b_Tmp = ((devpriv-> 1001 b_DigitalOutputRegister) & 0xF0) | 1002 APCI3120_SELECT_TIMER_0_WORD; 1003 outb(b_Tmp, dev->iobase + APCI3120_TIMER_CRT0); 1004 1005 /* Set the conversion time */ 1006 outw(((unsigned short) ui_TimerValue0), 1007 dev->iobase + APCI3120_TIMER_VALUE); 1008 break; 1009 1010 } 1011 /* ##########common for all modes################# */ 1012 1013 /***********************/ 1014 /* Clears the SCAN bit */ 1015 /***********************/ 1016 1017 /* BEGIN JK 07.05.04: Comparison between WIN32 and Linux driver */ 1018 /* devpriv->b_ModeSelectRegister=devpriv->b_ModeSelectRegister | APCI3120_DISABLE_SCAN; */ 1019 1020 devpriv->b_ModeSelectRegister = devpriv->b_ModeSelectRegister & 1021 APCI3120_DISABLE_SCAN; 1022 /* END JK 07.05.04: Comparison between WIN32 and Linux driver */ 1023 1024 outb(devpriv->b_ModeSelectRegister, 1025 dev->iobase + APCI3120_WRITE_MODE_SELECT); 1026 1027 /* If DMA is disabled */ 1028 if (devpriv->us_UseDma == APCI3120_DISABLE) { 1029 /* disable EOC and enable EOS */ 1030 devpriv->b_InterruptMode = APCI3120_EOS_MODE; 1031 devpriv->b_EocEosInterrupt = APCI3120_ENABLE; 1032 1033 devpriv->b_ModeSelectRegister = 1034 (devpriv-> 1035 b_ModeSelectRegister & APCI3120_DISABLE_EOC_INT) | 1036 APCI3120_ENABLE_EOS_INT; 1037 outb(devpriv->b_ModeSelectRegister, 1038 dev->iobase + APCI3120_WRITE_MODE_SELECT); 1039 1040 if (!devpriv->b_AiContinuous) { 1041/* 1042 * configure Timer2 For counting EOS Reset gate 2 of Timer 2 to 1043 * disable it (Set Bit D14 to 0) 1044 */ 1045 devpriv->us_OutputRegister = 1046 devpriv-> 1047 us_OutputRegister & APCI3120_DISABLE_TIMER2; 1048 outw(devpriv->us_OutputRegister, 1049 dev->iobase + APCI3120_WR_ADDRESS); 1050 1051 /* DISABLE TIMER intERRUPT */ 1052 devpriv->b_ModeSelectRegister = 1053 devpriv-> 1054 b_ModeSelectRegister & 1055 APCI3120_DISABLE_TIMER_INT & 0xEF; 1056 outb(devpriv->b_ModeSelectRegister, 1057 dev->iobase + APCI3120_WRITE_MODE_SELECT); 1058 1059 /* (1) Init timer 2 in mode 0 and write timer value */ 1060 devpriv->b_TimerSelectMode = 1061 (devpriv-> 1062 b_TimerSelectMode & 0x0F) | 1063 APCI3120_TIMER_2_MODE_0; 1064 outb(devpriv->b_TimerSelectMode, 1065 dev->iobase + APCI3120_TIMER_CRT1); 1066 1067 /* Writing LOW unsigned short */ 1068 b_Tmp = ((devpriv-> 1069 b_DigitalOutputRegister) & 0xF0) | 1070 APCI3120_SELECT_TIMER_2_LOW_WORD; 1071 outb(b_Tmp, dev->iobase + APCI3120_TIMER_CRT0); 1072 outw(LOWORD(ui_TimerValue2), 1073 dev->iobase + APCI3120_TIMER_VALUE); 1074 1075 /* Writing HIGH unsigned short */ 1076 b_Tmp = ((devpriv-> 1077 b_DigitalOutputRegister) & 0xF0) | 1078 APCI3120_SELECT_TIMER_2_HIGH_WORD; 1079 outb(b_Tmp, dev->iobase + APCI3120_TIMER_CRT0); 1080 outw(HIWORD(ui_TimerValue2), 1081 dev->iobase + APCI3120_TIMER_VALUE); 1082 1083 /* (2) Reset FC_TIMER BIT Clearing timer status register */ 1084 inb(dev->iobase + APCI3120_TIMER_STATUS_REGISTER); 1085 /* enable timer counter and disable watch dog */ 1086 devpriv->b_ModeSelectRegister = 1087 (devpriv-> 1088 b_ModeSelectRegister | 1089 APCI3120_ENABLE_TIMER_COUNTER) & 1090 APCI3120_DISABLE_WATCHDOG; 1091 /* select EOS clock input for timer 2 */ 1092 devpriv->b_ModeSelectRegister = 1093 devpriv-> 1094 b_ModeSelectRegister | 1095 APCI3120_TIMER2_SELECT_EOS; 1096 /* Enable timer2 interrupt */ 1097 devpriv->b_ModeSelectRegister = 1098 devpriv-> 1099 b_ModeSelectRegister | 1100 APCI3120_ENABLE_TIMER_INT; 1101 outb(devpriv->b_ModeSelectRegister, 1102 dev->iobase + APCI3120_WRITE_MODE_SELECT); 1103 devpriv->b_Timer2Mode = APCI3120_COUNTER; 1104 devpriv->b_Timer2Interrupt = APCI3120_ENABLE; 1105 } 1106 } else { 1107 /* If DMA Enabled */ 1108 1109 /* BEGIN JK 07.05.04: Comparison between WIN32 and Linux driver */ 1110 /* inw(dev->iobase+0); reset EOC bit */ 1111 /* END JK 07.05.04: Comparison between WIN32 and Linux driver */ 1112 devpriv->b_InterruptMode = APCI3120_DMA_MODE; 1113 1114 /************************************/ 1115 /* Disables the EOC, EOS interrupt */ 1116 /************************************/ 1117 devpriv->b_ModeSelectRegister = devpriv->b_ModeSelectRegister & 1118 APCI3120_DISABLE_EOC_INT & APCI3120_DISABLE_EOS_INT; 1119 1120 outb(devpriv->b_ModeSelectRegister, 1121 dev->iobase + APCI3120_WRITE_MODE_SELECT); 1122 1123 dmalen0 = devpriv->ui_DmaBufferSize[0]; 1124 dmalen1 = devpriv->ui_DmaBufferSize[1]; 1125 1126 if (!devpriv->b_AiContinuous) { 1127 1128 if (dmalen0 > (devpriv->ui_AiNbrofScans * devpriv->ui_AiScanLength * 2)) { /* must we fill full first buffer? */ 1129 dmalen0 = 1130 devpriv->ui_AiNbrofScans * 1131 devpriv->ui_AiScanLength * 2; 1132 } else if (dmalen1 > (devpriv->ui_AiNbrofScans * devpriv->ui_AiScanLength * 2 - dmalen0)) /* and must we fill full second buffer when first is once filled? */ 1133 dmalen1 = 1134 devpriv->ui_AiNbrofScans * 1135 devpriv->ui_AiScanLength * 2 - dmalen0; 1136 } 1137 1138 if (devpriv->ui_AiFlags & TRIG_WAKE_EOS) { 1139 /* don't we want wake up every scan? */ 1140 if (dmalen0 > (devpriv->ui_AiScanLength * 2)) { 1141 dmalen0 = devpriv->ui_AiScanLength * 2; 1142 if (devpriv->ui_AiScanLength & 1) 1143 dmalen0 += 2; 1144 } 1145 if (dmalen1 > (devpriv->ui_AiScanLength * 2)) { 1146 dmalen1 = devpriv->ui_AiScanLength * 2; 1147 if (devpriv->ui_AiScanLength & 1) 1148 dmalen1 -= 2; 1149 if (dmalen1 < 4) 1150 dmalen1 = 4; 1151 } 1152 } else { /* isn't output buff smaller that our DMA buff? */ 1153 if (dmalen0 > (devpriv->ui_AiDataLength)) 1154 dmalen0 = devpriv->ui_AiDataLength; 1155 if (dmalen1 > (devpriv->ui_AiDataLength)) 1156 dmalen1 = devpriv->ui_AiDataLength; 1157 } 1158 devpriv->ui_DmaBufferUsesize[0] = dmalen0; 1159 devpriv->ui_DmaBufferUsesize[1] = dmalen1; 1160 1161 /* Initialize DMA */ 1162 1163/* 1164 * Set Transfer count enable bit and A2P_fifo reset bit in AGCSTS 1165 * register 1 1166 */ 1167 ui_Tmp = AGCSTS_TC_ENABLE | AGCSTS_RESET_A2P_FIFO; 1168 outl(ui_Tmp, devpriv->i_IobaseAmcc + AMCC_OP_REG_AGCSTS); 1169 1170 /* changed since 16 bit interface for add on */ 1171 /*********************/ 1172 /* ENABLE BUS MASTER */ 1173 /*********************/ 1174 outw(APCI3120_ADD_ON_AGCSTS_LOW, devpriv->i_IobaseAddon + 0); 1175 outw(APCI3120_ENABLE_TRANSFER_ADD_ON_LOW, 1176 devpriv->i_IobaseAddon + 2); 1177 1178 outw(APCI3120_ADD_ON_AGCSTS_HIGH, devpriv->i_IobaseAddon + 0); 1179 outw(APCI3120_ENABLE_TRANSFER_ADD_ON_HIGH, 1180 devpriv->i_IobaseAddon + 2); 1181 1182/* 1183 * TO VERIFIED BEGIN JK 07.05.04: Comparison between WIN32 and Linux 1184 * driver 1185 */ 1186 outw(0x1000, devpriv->i_IobaseAddon + 2); 1187 /* END JK 07.05.04: Comparison between WIN32 and Linux driver */ 1188 1189 /* 2 No change */ 1190 /* A2P FIFO MANAGEMENT */ 1191 /* A2P fifo reset & transfer control enable */ 1192 1193 /***********************/ 1194 /* A2P FIFO MANAGEMENT */ 1195 /***********************/ 1196 outl(APCI3120_A2P_FIFO_MANAGEMENT, devpriv->i_IobaseAmcc + 1197 APCI3120_AMCC_OP_MCSR); 1198 1199/* 1200 * 3 1201 * beginning address of dma buf The 32 bit address of dma buffer 1202 * is converted into two 16 bit addresses Can done by using _attach 1203 * and put into into an array array used may be for differnet pages 1204 */ 1205 1206 /* DMA Start Address Low */ 1207 outw(APCI3120_ADD_ON_MWAR_LOW, devpriv->i_IobaseAddon + 0); 1208 outw((devpriv->ul_DmaBufferHw[0] & 0xFFFF), 1209 devpriv->i_IobaseAddon + 2); 1210 1211 /*************************/ 1212 /* DMA Start Address High */ 1213 /*************************/ 1214 outw(APCI3120_ADD_ON_MWAR_HIGH, devpriv->i_IobaseAddon + 0); 1215 outw((devpriv->ul_DmaBufferHw[0] / 65536), 1216 devpriv->i_IobaseAddon + 2); 1217 1218/* 1219 * 4 1220 * amount of bytes to be transferred set transfer count used ADDON 1221 * MWTC register commented testing 1222 * outl(devpriv->ui_DmaBufferUsesize[0], 1223 * devpriv->i_IobaseAddon+AMCC_OP_REG_AMWTC); 1224 */ 1225 1226 /**************************/ 1227 /* Nbr of acquisition LOW */ 1228 /**************************/ 1229 outw(APCI3120_ADD_ON_MWTC_LOW, devpriv->i_IobaseAddon + 0); 1230 outw((devpriv->ui_DmaBufferUsesize[0] & 0xFFFF), 1231 devpriv->i_IobaseAddon + 2); 1232 1233 /***************************/ 1234 /* Nbr of acquisition HIGH */ 1235 /***************************/ 1236 outw(APCI3120_ADD_ON_MWTC_HIGH, devpriv->i_IobaseAddon + 0); 1237 outw((devpriv->ui_DmaBufferUsesize[0] / 65536), 1238 devpriv->i_IobaseAddon + 2); 1239 1240/* 1241 * 5 1242 * To configure A2P FIFO testing outl( 1243 * FIFO_ADVANCE_ON_BYTE_2,devpriv->i_IobaseAmcc+AMCC_OP_REG_INTCSR); 1244 */ 1245 1246 /******************/ 1247 /* A2P FIFO RESET */ 1248 /******************/ 1249/* 1250 * TO VERIFY BEGIN JK 07.05.04: Comparison between WIN32 and Linux 1251 * driver 1252 */ 1253 outl(0x04000000UL, devpriv->i_IobaseAmcc + AMCC_OP_REG_MCSR); 1254 /* END JK 07.05.04: Comparison between WIN32 and Linux driver */ 1255 1256/* 1257 * 6 1258 * ENABLE A2P FIFO WRITE AND ENABLE AMWEN AMWEN_ENABLE | 1259 * A2P_FIFO_WRITE_ENABLE (0x01|0x02)=0x03 1260 */ 1261 1262 /* BEGIN JK 07.05.04: Comparison between WIN32 and Linux driver */ 1263 /* outw(3,devpriv->i_IobaseAddon + 4); */ 1264 /* END JK 07.05.04: Comparison between WIN32 and Linux driver */ 1265 1266/* 1267 * 7 1268 * initialise end of dma interrupt AINT_WRITE_COMPL = 1269 * ENABLE_WRITE_TC_INT(ADDI) 1270 */ 1271 /***************************************************/ 1272 /* A2P FIFO CONFIGURATE, END OF DMA intERRUPT INIT */ 1273 /***************************************************/ 1274 outl((APCI3120_FIFO_ADVANCE_ON_BYTE_2 | 1275 APCI3120_ENABLE_WRITE_TC_INT), 1276 devpriv->i_IobaseAmcc + AMCC_OP_REG_INTCSR); 1277 1278 /* BEGIN JK 07.05.04: Comparison between WIN32 and Linux driver */ 1279 /******************************************/ 1280 /* ENABLE A2P FIFO WRITE AND ENABLE AMWEN */ 1281 /******************************************/ 1282 outw(3, devpriv->i_IobaseAddon + 4); 1283 /* END JK 07.05.04: Comparison between WIN32 and Linux driver */ 1284 1285 /******************/ 1286 /* A2P FIFO RESET */ 1287 /******************/ 1288 /* BEGIN JK 07.05.04: Comparison between WIN32 and Linux driver */ 1289 outl(0x04000000UL, 1290 devpriv->i_IobaseAmcc + APCI3120_AMCC_OP_MCSR); 1291 /* END JK 07.05.04: Comparison between WIN32 and Linux driver */ 1292 } 1293 1294 if ((devpriv->us_UseDma == APCI3120_DISABLE) 1295 && !devpriv->b_AiContinuous) { 1296 /* set gate 2 to start conversion */ 1297 devpriv->us_OutputRegister = 1298 devpriv->us_OutputRegister | APCI3120_ENABLE_TIMER2; 1299 outw(devpriv->us_OutputRegister, 1300 dev->iobase + APCI3120_WR_ADDRESS); 1301 } 1302 1303 switch (mode) { 1304 case 1: 1305 /* set gate 0 to start conversion */ 1306 devpriv->us_OutputRegister = 1307 devpriv->us_OutputRegister | APCI3120_ENABLE_TIMER0; 1308 outw(devpriv->us_OutputRegister, 1309 dev->iobase + APCI3120_WR_ADDRESS); 1310 break; 1311 case 2: 1312 /* set gate 0 and gate 1 */ 1313 devpriv->us_OutputRegister = 1314 devpriv->us_OutputRegister | APCI3120_ENABLE_TIMER1; 1315 devpriv->us_OutputRegister = 1316 devpriv->us_OutputRegister | APCI3120_ENABLE_TIMER0; 1317 outw(devpriv->us_OutputRegister, 1318 dev->iobase + APCI3120_WR_ADDRESS); 1319 break; 1320 1321 } 1322 1323 return 0; 1324 1325} 1326 1327/* 1328 * Does asynchronous acquisition. 1329 * Determines the mode 1 or 2. 1330 */ 1331static int apci3120_ai_cmd(struct comedi_device *dev, 1332 struct comedi_subdevice *s) 1333{ 1334 struct addi_private *devpriv = dev->private; 1335 struct comedi_cmd *cmd = &s->async->cmd; 1336 1337 /* loading private structure with cmd structure inputs */ 1338 devpriv->ui_AiFlags = cmd->flags; 1339 devpriv->ui_AiNbrofChannels = cmd->chanlist_len; 1340 devpriv->ui_AiScanLength = cmd->scan_end_arg; 1341 devpriv->pui_AiChannelList = cmd->chanlist; 1342 1343 /* UPDATE-0.7.57->0.7.68devpriv->ui_AiDataLength=s->async->data_len; */ 1344 devpriv->ui_AiDataLength = s->async->prealloc_bufsz; 1345 1346 if (cmd->stop_src == TRIG_COUNT) 1347 devpriv->ui_AiNbrofScans = cmd->stop_arg; 1348 else 1349 devpriv->ui_AiNbrofScans = 0; 1350 1351 devpriv->ui_AiTimer0 = 0; /* variables changed to timer0,timer1 */ 1352 devpriv->ui_AiTimer1 = 0; 1353 if ((devpriv->ui_AiNbrofScans == 0) || (devpriv->ui_AiNbrofScans == -1)) 1354 devpriv->b_AiContinuous = 1; /* user want neverending analog acquisition */ 1355 /* stopped using cancel */ 1356 1357 if (cmd->start_src == TRIG_EXT) 1358 devpriv->b_ExttrigEnable = APCI3120_ENABLE; 1359 else 1360 devpriv->b_ExttrigEnable = APCI3120_DISABLE; 1361 1362 if (cmd->scan_begin_src == TRIG_FOLLOW) { 1363 /* mode 1 or 3 */ 1364 if (cmd->convert_src == TRIG_TIMER) { 1365 /* mode 1 */ 1366 1367 devpriv->ui_AiTimer0 = cmd->convert_arg; /* timer constant in nano seconds */ 1368 /* return this_board->ai_cmd(1,dev,s); */ 1369 return apci3120_cyclic_ai(1, dev, s); 1370 } 1371 1372 } 1373 if ((cmd->scan_begin_src == TRIG_TIMER) 1374 && (cmd->convert_src == TRIG_TIMER)) { 1375 /* mode 2 */ 1376 devpriv->ui_AiTimer1 = cmd->scan_begin_arg; 1377 devpriv->ui_AiTimer0 = cmd->convert_arg; /* variable changed timer2 to timer0 */ 1378 /* return this_board->ai_cmd(2,dev,s); */ 1379 return apci3120_cyclic_ai(2, dev, s); 1380 } 1381 return -1; 1382} 1383 1384/* 1385 * This function copies the data from DMA buffer to the Comedi buffer. 1386 */ 1387static void v_APCI3120_InterruptDmaMoveBlock16bit(struct comedi_device *dev, 1388 struct comedi_subdevice *s, 1389 unsigned short *dma_buffer, 1390 unsigned int num_samples) 1391{ 1392 struct addi_private *devpriv = dev->private; 1393 1394 devpriv->ui_AiActualScan += 1395 (s->async->cur_chan + num_samples) / devpriv->ui_AiScanLength; 1396 s->async->cur_chan += num_samples; 1397 s->async->cur_chan %= devpriv->ui_AiScanLength; 1398 1399 cfc_write_array_to_buffer(s, dma_buffer, num_samples * sizeof(short)); 1400} 1401 1402/* 1403 * This is a handler for the DMA interrupt. 1404 * This function copies the data to Comedi Buffer. 1405 * For continuous DMA it reinitializes the DMA operation. 1406 * For single mode DMA it stop the acquisition. 1407 */ 1408static void apci3120_interrupt_dma(int irq, void *d) 1409{ 1410 struct comedi_device *dev = d; 1411 struct addi_private *devpriv = dev->private; 1412 struct comedi_subdevice *s = dev->read_subdev; 1413 unsigned int next_dma_buf, samplesinbuf; 1414 unsigned long low_word, high_word, var; 1415 unsigned int ui_Tmp; 1416 1417 samplesinbuf = 1418 devpriv->ui_DmaBufferUsesize[devpriv->ui_DmaActualBuffer] - 1419 inl(devpriv->i_IobaseAmcc + AMCC_OP_REG_MWTC); 1420 1421 if (samplesinbuf < 1422 devpriv->ui_DmaBufferUsesize[devpriv->ui_DmaActualBuffer]) { 1423 comedi_error(dev, "Interrupted DMA transfer!"); 1424 } 1425 if (samplesinbuf & 1) { 1426 comedi_error(dev, "Odd count of bytes in DMA ring!"); 1427 apci3120_cancel(dev, s); 1428 devpriv->b_AiCyclicAcquisition = APCI3120_DISABLE; 1429 1430 return; 1431 } 1432 samplesinbuf = samplesinbuf >> 1; /* number of received samples */ 1433 if (devpriv->b_DmaDoubleBuffer) { 1434 /* switch DMA buffers if is used double buffering */ 1435 next_dma_buf = 1 - devpriv->ui_DmaActualBuffer; 1436 1437 ui_Tmp = AGCSTS_TC_ENABLE | AGCSTS_RESET_A2P_FIFO; 1438 outl(ui_Tmp, devpriv->i_IobaseAddon + AMCC_OP_REG_AGCSTS); 1439 1440 /* changed since 16 bit interface for add on */ 1441 outw(APCI3120_ADD_ON_AGCSTS_LOW, devpriv->i_IobaseAddon + 0); 1442 outw(APCI3120_ENABLE_TRANSFER_ADD_ON_LOW, 1443 devpriv->i_IobaseAddon + 2); 1444 outw(APCI3120_ADD_ON_AGCSTS_HIGH, devpriv->i_IobaseAddon + 0); 1445 outw(APCI3120_ENABLE_TRANSFER_ADD_ON_HIGH, devpriv->i_IobaseAddon + 2); /* 0x1000 is out putted in windows driver */ 1446 1447 var = devpriv->ul_DmaBufferHw[next_dma_buf]; 1448 low_word = var & 0xffff; 1449 var = devpriv->ul_DmaBufferHw[next_dma_buf]; 1450 high_word = var / 65536; 1451 1452 /* DMA Start Address Low */ 1453 outw(APCI3120_ADD_ON_MWAR_LOW, devpriv->i_IobaseAddon + 0); 1454 outw(low_word, devpriv->i_IobaseAddon + 2); 1455 1456 /* DMA Start Address High */ 1457 outw(APCI3120_ADD_ON_MWAR_HIGH, devpriv->i_IobaseAddon + 0); 1458 outw(high_word, devpriv->i_IobaseAddon + 2); 1459 1460 var = devpriv->ui_DmaBufferUsesize[next_dma_buf]; 1461 low_word = var & 0xffff; 1462 var = devpriv->ui_DmaBufferUsesize[next_dma_buf]; 1463 high_word = var / 65536; 1464 1465 /* Nbr of acquisition LOW */ 1466 outw(APCI3120_ADD_ON_MWTC_LOW, devpriv->i_IobaseAddon + 0); 1467 outw(low_word, devpriv->i_IobaseAddon + 2); 1468 1469 /* Nbr of acquisition HIGH */ 1470 outw(APCI3120_ADD_ON_MWTC_HIGH, devpriv->i_IobaseAddon + 0); 1471 outw(high_word, devpriv->i_IobaseAddon + 2); 1472 1473/* 1474 * To configure A2P FIFO 1475 * ENABLE A2P FIFO WRITE AND ENABLE AMWEN 1476 * AMWEN_ENABLE | A2P_FIFO_WRITE_ENABLE (0x01|0x02)=0x03 1477 */ 1478 outw(3, devpriv->i_IobaseAddon + 4); 1479 /* initialise end of dma interrupt AINT_WRITE_COMPL = ENABLE_WRITE_TC_INT(ADDI) */ 1480 outl((APCI3120_FIFO_ADVANCE_ON_BYTE_2 | 1481 APCI3120_ENABLE_WRITE_TC_INT), 1482 devpriv->i_IobaseAmcc + AMCC_OP_REG_INTCSR); 1483 1484 } 1485 if (samplesinbuf) { 1486 v_APCI3120_InterruptDmaMoveBlock16bit(dev, s, 1487 devpriv->ul_DmaBufferVirtual[devpriv-> 1488 ui_DmaActualBuffer], samplesinbuf); 1489 1490 if (!(devpriv->ui_AiFlags & TRIG_WAKE_EOS)) { 1491 s->async->events |= COMEDI_CB_EOS; 1492 comedi_event(dev, s); 1493 } 1494 } 1495 if (!devpriv->b_AiContinuous) 1496 if (devpriv->ui_AiActualScan >= devpriv->ui_AiNbrofScans) { 1497 /* all data sampled */ 1498 apci3120_cancel(dev, s); 1499 devpriv->b_AiCyclicAcquisition = APCI3120_DISABLE; 1500 s->async->events |= COMEDI_CB_EOA; 1501 comedi_event(dev, s); 1502 return; 1503 } 1504 1505 if (devpriv->b_DmaDoubleBuffer) { /* switch dma buffers */ 1506 devpriv->ui_DmaActualBuffer = 1 - devpriv->ui_DmaActualBuffer; 1507 } else { 1508/* 1509 * restart DMA if is not used double buffering 1510 * ADDED REINITIALISE THE DMA 1511 */ 1512 ui_Tmp = AGCSTS_TC_ENABLE | AGCSTS_RESET_A2P_FIFO; 1513 outl(ui_Tmp, devpriv->i_IobaseAddon + AMCC_OP_REG_AGCSTS); 1514 1515 /* changed since 16 bit interface for add on */ 1516 outw(APCI3120_ADD_ON_AGCSTS_LOW, devpriv->i_IobaseAddon + 0); 1517 outw(APCI3120_ENABLE_TRANSFER_ADD_ON_LOW, 1518 devpriv->i_IobaseAddon + 2); 1519 outw(APCI3120_ADD_ON_AGCSTS_HIGH, devpriv->i_IobaseAddon + 0); 1520 outw(APCI3120_ENABLE_TRANSFER_ADD_ON_HIGH, devpriv->i_IobaseAddon + 2); /* */ 1521/* 1522 * A2P FIFO MANAGEMENT 1523 * A2P fifo reset & transfer control enable 1524 */ 1525 outl(APCI3120_A2P_FIFO_MANAGEMENT, 1526 devpriv->i_IobaseAmcc + AMCC_OP_REG_MCSR); 1527 1528 var = devpriv->ul_DmaBufferHw[0]; 1529 low_word = var & 0xffff; 1530 var = devpriv->ul_DmaBufferHw[0]; 1531 high_word = var / 65536; 1532 outw(APCI3120_ADD_ON_MWAR_LOW, devpriv->i_IobaseAddon + 0); 1533 outw(low_word, devpriv->i_IobaseAddon + 2); 1534 outw(APCI3120_ADD_ON_MWAR_HIGH, devpriv->i_IobaseAddon + 0); 1535 outw(high_word, devpriv->i_IobaseAddon + 2); 1536 1537 var = devpriv->ui_DmaBufferUsesize[0]; 1538 low_word = var & 0xffff; /* changed */ 1539 var = devpriv->ui_DmaBufferUsesize[0]; 1540 high_word = var / 65536; 1541 outw(APCI3120_ADD_ON_MWTC_LOW, devpriv->i_IobaseAddon + 0); 1542 outw(low_word, devpriv->i_IobaseAddon + 2); 1543 outw(APCI3120_ADD_ON_MWTC_HIGH, devpriv->i_IobaseAddon + 0); 1544 outw(high_word, devpriv->i_IobaseAddon + 2); 1545 1546/* 1547 * To configure A2P FIFO 1548 * ENABLE A2P FIFO WRITE AND ENABLE AMWEN 1549 * AMWEN_ENABLE | A2P_FIFO_WRITE_ENABLE (0x01|0x02)=0x03 1550 */ 1551 outw(3, devpriv->i_IobaseAddon + 4); 1552 /* initialise end of dma interrupt AINT_WRITE_COMPL = ENABLE_WRITE_TC_INT(ADDI) */ 1553 outl((APCI3120_FIFO_ADVANCE_ON_BYTE_2 | 1554 APCI3120_ENABLE_WRITE_TC_INT), 1555 devpriv->i_IobaseAmcc + AMCC_OP_REG_INTCSR); 1556 } 1557} 1558 1559/* 1560 * This function handles EOS interrupt. 1561 * This function copies the acquired data(from FIFO) to Comedi buffer. 1562 */ 1563static int apci3120_interrupt_handle_eos(struct comedi_device *dev) 1564{ 1565 struct addi_private *devpriv = dev->private; 1566 struct comedi_subdevice *s = dev->read_subdev; 1567 int n_chan, i; 1568 int err = 1; 1569 1570 n_chan = devpriv->ui_AiNbrofChannels; 1571 1572 for (i = 0; i < n_chan; i++) 1573 err &= comedi_buf_put(s->async, inw(dev->iobase + 0)); 1574 1575 s->async->events |= COMEDI_CB_EOS; 1576 1577 if (err == 0) 1578 s->async->events |= COMEDI_CB_OVERFLOW; 1579 1580 comedi_event(dev, s); 1581 1582 return 0; 1583} 1584 1585static void apci3120_interrupt(int irq, void *d) 1586{ 1587 struct comedi_device *dev = d; 1588 struct addi_private *devpriv = dev->private; 1589 struct comedi_subdevice *s = dev->read_subdev; 1590 unsigned short int_daq; 1591 unsigned int int_amcc, ui_Check, i; 1592 unsigned short us_TmpValue; 1593 unsigned char b_DummyRead; 1594 1595 ui_Check = 1; 1596 1597 int_daq = inw(dev->iobase + APCI3120_RD_STATUS) & 0xf000; /* get IRQ reasons */ 1598 int_amcc = inl(devpriv->i_IobaseAmcc + AMCC_OP_REG_INTCSR); /* get AMCC int register */ 1599 1600 if ((!int_daq) && (!(int_amcc & ANY_S593X_INT))) { 1601 comedi_error(dev, "IRQ from unknown source"); 1602 return; 1603 } 1604 1605 outl(int_amcc | 0x00ff0000, devpriv->i_IobaseAmcc + AMCC_OP_REG_INTCSR); /* shutdown IRQ reasons in AMCC */ 1606 1607 int_daq = (int_daq >> 12) & 0xF; 1608 1609 if (devpriv->b_ExttrigEnable == APCI3120_ENABLE) { 1610 /* Disable ext trigger */ 1611 apci3120_exttrig_disable(dev); 1612 devpriv->b_ExttrigEnable = APCI3120_DISABLE; 1613 } 1614 /* clear the timer 2 interrupt */ 1615 inb(devpriv->i_IobaseAmcc + APCI3120_TIMER_STATUS_REGISTER); 1616 1617 if (int_amcc & MASTER_ABORT_INT) 1618 comedi_error(dev, "AMCC IRQ - MASTER DMA ABORT!"); 1619 if (int_amcc & TARGET_ABORT_INT) 1620 comedi_error(dev, "AMCC IRQ - TARGET DMA ABORT!"); 1621 1622 /* Ckeck if EOC interrupt */ 1623 if (((int_daq & 0x8) == 0) 1624 && (devpriv->b_InterruptMode == APCI3120_EOC_MODE)) { 1625 if (devpriv->b_EocEosInterrupt == APCI3120_ENABLE) { 1626 1627 /* Read the AI Value */ 1628 1629 devpriv->ui_AiReadData[0] = 1630 (unsigned int) inw(devpriv->iobase + 0); 1631 devpriv->b_EocEosInterrupt = APCI3120_DISABLE; 1632 send_sig(SIGIO, devpriv->tsk_Current, 0); /* send signal to the sample */ 1633 } else { 1634 /* Disable EOC Interrupt */ 1635 devpriv->b_ModeSelectRegister = 1636 devpriv-> 1637 b_ModeSelectRegister & APCI3120_DISABLE_EOC_INT; 1638 outb(devpriv->b_ModeSelectRegister, 1639 devpriv->iobase + APCI3120_WRITE_MODE_SELECT); 1640 1641 } 1642 } 1643 1644 /* Check If EOS interrupt */ 1645 if ((int_daq & 0x2) && (devpriv->b_InterruptMode == APCI3120_EOS_MODE)) { 1646 1647 if (devpriv->b_EocEosInterrupt == APCI3120_ENABLE) { /* enable this in without DMA ??? */ 1648 1649 if (devpriv->b_AiCyclicAcquisition == APCI3120_ENABLE) { 1650 ui_Check = 0; 1651 apci3120_interrupt_handle_eos(dev); 1652 devpriv->ui_AiActualScan++; 1653 devpriv->b_ModeSelectRegister = 1654 devpriv-> 1655 b_ModeSelectRegister | 1656 APCI3120_ENABLE_EOS_INT; 1657 outb(devpriv->b_ModeSelectRegister, 1658 dev->iobase + 1659 APCI3120_WRITE_MODE_SELECT); 1660 } else { 1661 ui_Check = 0; 1662 for (i = 0; i < devpriv->ui_AiNbrofChannels; 1663 i++) { 1664 us_TmpValue = inw(devpriv->iobase + 0); 1665 devpriv->ui_AiReadData[i] = 1666 (unsigned int) us_TmpValue; 1667 } 1668 devpriv->b_EocEosInterrupt = APCI3120_DISABLE; 1669 devpriv->b_InterruptMode = APCI3120_EOC_MODE; 1670 1671 send_sig(SIGIO, devpriv->tsk_Current, 0); /* send signal to the sample */ 1672 1673 } 1674 1675 } else { 1676 devpriv->b_ModeSelectRegister = 1677 devpriv-> 1678 b_ModeSelectRegister & APCI3120_DISABLE_EOS_INT; 1679 outb(devpriv->b_ModeSelectRegister, 1680 dev->iobase + APCI3120_WRITE_MODE_SELECT); 1681 devpriv->b_EocEosInterrupt = APCI3120_DISABLE; /* Default settings */ 1682 devpriv->b_InterruptMode = APCI3120_EOC_MODE; 1683 } 1684 1685 } 1686 /* Timer2 interrupt */ 1687 if (int_daq & 0x1) { 1688 1689 switch (devpriv->b_Timer2Mode) { 1690 case APCI3120_COUNTER: 1691 1692 devpriv->b_AiCyclicAcquisition = APCI3120_DISABLE; 1693 devpriv->b_ModeSelectRegister = 1694 devpriv-> 1695 b_ModeSelectRegister & APCI3120_DISABLE_EOS_INT; 1696 outb(devpriv->b_ModeSelectRegister, 1697 dev->iobase + APCI3120_WRITE_MODE_SELECT); 1698 1699 /* stop timer 2 */ 1700 devpriv->us_OutputRegister = 1701 devpriv-> 1702 us_OutputRegister & APCI3120_DISABLE_ALL_TIMER; 1703 outw(devpriv->us_OutputRegister, 1704 dev->iobase + APCI3120_WR_ADDRESS); 1705 1706 /* stop timer 0 and timer 1 */ 1707 apci3120_cancel(dev, s); 1708 devpriv->b_AiCyclicAcquisition = APCI3120_DISABLE; 1709 1710 /* UPDATE-0.7.57->0.7.68comedi_done(dev,s); */ 1711 s->async->events |= COMEDI_CB_EOA; 1712 comedi_event(dev, s); 1713 1714 break; 1715 1716 case APCI3120_TIMER: 1717 1718 /* Send a signal to from kernel to user space */ 1719 send_sig(SIGIO, devpriv->tsk_Current, 0); 1720 break; 1721 1722 case APCI3120_WATCHDOG: 1723 1724 /* Send a signal to from kernel to user space */ 1725 send_sig(SIGIO, devpriv->tsk_Current, 0); 1726 break; 1727 1728 default: 1729 1730 /* disable Timer Interrupt */ 1731 1732 devpriv->b_ModeSelectRegister = 1733 devpriv-> 1734 b_ModeSelectRegister & 1735 APCI3120_DISABLE_TIMER_INT; 1736 1737 outb(devpriv->b_ModeSelectRegister, 1738 dev->iobase + APCI3120_WRITE_MODE_SELECT); 1739 1740 } 1741 1742 b_DummyRead = inb(dev->iobase + APCI3120_TIMER_STATUS_REGISTER); 1743 1744 } 1745 1746 if ((int_daq & 0x4) && (devpriv->b_InterruptMode == APCI3120_DMA_MODE)) { 1747 if (devpriv->b_AiCyclicAcquisition == APCI3120_ENABLE) { 1748 1749 /****************************/ 1750 /* Clear Timer Write TC int */ 1751 /****************************/ 1752 1753 outl(APCI3120_CLEAR_WRITE_TC_INT, 1754 devpriv->i_IobaseAmcc + 1755 APCI3120_AMCC_OP_REG_INTCSR); 1756 1757 /************************************/ 1758 /* Clears the timer status register */ 1759 /************************************/ 1760 inw(dev->iobase + APCI3120_TIMER_STATUS_REGISTER); 1761 /* do some data transfer */ 1762 apci3120_interrupt_dma(irq, d); 1763 } else { 1764 /* Stops the Timer */ 1765 outw(devpriv-> 1766 us_OutputRegister & APCI3120_DISABLE_TIMER0 & 1767 APCI3120_DISABLE_TIMER1, 1768 dev->iobase + APCI3120_WR_ADDRESS); 1769 } 1770 1771 } 1772 1773 return; 1774} 1775 1776/* 1777 * Configure Timer 2 1778 * 1779 * data[0] = TIMER configure as timer 1780 * = WATCHDOG configure as watchdog 1781 * data[1] = Timer constant 1782 * data[2] = Timer2 interrupt (1)enable or(0) disable 1783 */ 1784static int apci3120_config_insn_timer(struct comedi_device *dev, 1785 struct comedi_subdevice *s, 1786 struct comedi_insn *insn, 1787 unsigned int *data) 1788{ 1789 const struct addi_board *this_board = comedi_board(dev); 1790 struct addi_private *devpriv = dev->private; 1791 unsigned int ui_Timervalue2; 1792 unsigned short us_TmpValue; 1793 unsigned char b_Tmp; 1794 1795 if (!data[1]) 1796 comedi_error(dev, "config:No timer constant !"); 1797 1798 devpriv->b_Timer2Interrupt = (unsigned char) data[2]; /* save info whether to enable or disable interrupt */ 1799 1800 ui_Timervalue2 = data[1] / 1000; /* convert nano seconds to u seconds */ 1801 1802 /* this_board->timer_config(dev, ui_Timervalue2,(unsigned char)data[0]); */ 1803 us_TmpValue = (unsigned short) inw(devpriv->iobase + APCI3120_RD_STATUS); 1804 1805/* 1806 * EL250804: Testing if board APCI3120 have the new Quartz or if it 1807 * is an APCI3001 and calculate the time value to set in the timer 1808 */ 1809 if ((us_TmpValue & 0x00B0) == 0x00B0 1810 || !strcmp(this_board->pc_DriverName, "apci3001")) { 1811 /* Calculate the time value to set in the timer */ 1812 ui_Timervalue2 = ui_Timervalue2 / 50; 1813 } else { 1814 /* Calculate the time value to set in the timer */ 1815 ui_Timervalue2 = ui_Timervalue2 / 70; 1816 } 1817 1818 /* Reset gate 2 of Timer 2 to disable it (Set Bit D14 to 0) */ 1819 devpriv->us_OutputRegister = 1820 devpriv->us_OutputRegister & APCI3120_DISABLE_TIMER2; 1821 outw(devpriv->us_OutputRegister, devpriv->iobase + APCI3120_WR_ADDRESS); 1822 1823 /* Disable TIMER Interrupt */ 1824 devpriv->b_ModeSelectRegister = 1825 devpriv-> 1826 b_ModeSelectRegister & APCI3120_DISABLE_TIMER_INT & 0xEF; 1827 1828 /* Disable Eoc and Eos Interrupts */ 1829 devpriv->b_ModeSelectRegister = 1830 devpriv-> 1831 b_ModeSelectRegister & APCI3120_DISABLE_EOC_INT & 1832 APCI3120_DISABLE_EOS_INT; 1833 outb(devpriv->b_ModeSelectRegister, 1834 devpriv->iobase + APCI3120_WRITE_MODE_SELECT); 1835 if (data[0] == APCI3120_TIMER) { /* initialize timer */ 1836 /* devpriv->b_ModeSelectRegister=devpriv->b_ModeSelectRegister | 1837 * APCI3120_ENABLE_TIMER_INT; */ 1838 1839 /* outb(devpriv->b_ModeSelectRegister,devpriv->iobase+APCI3120_WRITE_MODE_SELECT); */ 1840 1841 /* Set the Timer 2 in mode 2(Timer) */ 1842 devpriv->b_TimerSelectMode = 1843 (devpriv-> 1844 b_TimerSelectMode & 0x0F) | APCI3120_TIMER_2_MODE_2; 1845 outb(devpriv->b_TimerSelectMode, 1846 devpriv->iobase + APCI3120_TIMER_CRT1); 1847 1848/* 1849 * Configure the timer 2 for writing the LOW unsigned short of timer 1850 * is Delay value You must make a b_tmp variable with 1851 * DigitalOutPutRegister because at Address_1+APCI3120_TIMER_CRT0 1852 * you can set the digital output and configure the timer 2,and if 1853 * you don't make this, digital output are erase (Set to 0) 1854 */ 1855 1856 /* Writing LOW unsigned short */ 1857 b_Tmp = ((devpriv-> 1858 b_DigitalOutputRegister) & 0xF0) | 1859 APCI3120_SELECT_TIMER_2_LOW_WORD; 1860 outb(b_Tmp, devpriv->iobase + APCI3120_TIMER_CRT0); 1861 outw(LOWORD(ui_Timervalue2), 1862 devpriv->iobase + APCI3120_TIMER_VALUE); 1863 1864 /* Writing HIGH unsigned short */ 1865 b_Tmp = ((devpriv-> 1866 b_DigitalOutputRegister) & 0xF0) | 1867 APCI3120_SELECT_TIMER_2_HIGH_WORD; 1868 outb(b_Tmp, devpriv->iobase + APCI3120_TIMER_CRT0); 1869 outw(HIWORD(ui_Timervalue2), 1870 devpriv->iobase + APCI3120_TIMER_VALUE); 1871 /* timer2 in Timer mode enabled */ 1872 devpriv->b_Timer2Mode = APCI3120_TIMER; 1873 1874 } else { /* Initialize Watch dog */ 1875 1876 /* Set the Timer 2 in mode 5(Watchdog) */ 1877 1878 devpriv->b_TimerSelectMode = 1879 (devpriv-> 1880 b_TimerSelectMode & 0x0F) | APCI3120_TIMER_2_MODE_5; 1881 outb(devpriv->b_TimerSelectMode, 1882 devpriv->iobase + APCI3120_TIMER_CRT1); 1883 1884/* 1885 * Configure the timer 2 for writing the LOW unsigned short of timer 1886 * is Delay value You must make a b_tmp variable with 1887 * DigitalOutPutRegister because at Address_1+APCI3120_TIMER_CRT0 1888 * you can set the digital output and configure the timer 2,and if 1889 * you don't make this, digital output are erase (Set to 0) 1890 */ 1891 1892 /* Writing LOW unsigned short */ 1893 b_Tmp = ((devpriv-> 1894 b_DigitalOutputRegister) & 0xF0) | 1895 APCI3120_SELECT_TIMER_2_LOW_WORD; 1896 outb(b_Tmp, devpriv->iobase + APCI3120_TIMER_CRT0); 1897 outw(LOWORD(ui_Timervalue2), 1898 devpriv->iobase + APCI3120_TIMER_VALUE); 1899 1900 /* Writing HIGH unsigned short */ 1901 b_Tmp = ((devpriv-> 1902 b_DigitalOutputRegister) & 0xF0) | 1903 APCI3120_SELECT_TIMER_2_HIGH_WORD; 1904 outb(b_Tmp, devpriv->iobase + APCI3120_TIMER_CRT0); 1905 1906 outw(HIWORD(ui_Timervalue2), 1907 devpriv->iobase + APCI3120_TIMER_VALUE); 1908 /* watchdog enabled */ 1909 devpriv->b_Timer2Mode = APCI3120_WATCHDOG; 1910 1911 } 1912 1913 return insn->n; 1914 1915} 1916 1917/* 1918 * To start and stop the timer 1919 * 1920 * data[0] = 1 (start) 1921 * = 0 (stop) 1922 * = 2 (write new value) 1923 * data[1] = new value 1924 * 1925 * devpriv->b_Timer2Mode = 0 DISABLE 1926 * = 1 Timer 1927 * = 2 Watch dog 1928 */ 1929static int apci3120_write_insn_timer(struct comedi_device *dev, 1930 struct comedi_subdevice *s, 1931 struct comedi_insn *insn, 1932 unsigned int *data) 1933{ 1934 const struct addi_board *this_board = comedi_board(dev); 1935 struct addi_private *devpriv = dev->private; 1936 unsigned int ui_Timervalue2 = 0; 1937 unsigned short us_TmpValue; 1938 unsigned char b_Tmp; 1939 1940 if ((devpriv->b_Timer2Mode != APCI3120_WATCHDOG) 1941 && (devpriv->b_Timer2Mode != APCI3120_TIMER)) { 1942 comedi_error(dev, "\nwrite:timer2 not configured "); 1943 return -EINVAL; 1944 } 1945 1946 if (data[0] == 2) { /* write new value */ 1947 if (devpriv->b_Timer2Mode != APCI3120_TIMER) { 1948 comedi_error(dev, 1949 "write :timer2 not configured in TIMER MODE"); 1950 return -EINVAL; 1951 } 1952 1953 if (data[1]) 1954 ui_Timervalue2 = data[1]; 1955 else 1956 ui_Timervalue2 = 0; 1957 } 1958 1959 /* this_board->timer_write(dev,data[0],ui_Timervalue2); */ 1960 1961 switch (data[0]) { 1962 case APCI3120_START: 1963 1964 /* Reset FC_TIMER BIT */ 1965 inb(devpriv->iobase + APCI3120_TIMER_STATUS_REGISTER); 1966 if (devpriv->b_Timer2Mode == APCI3120_TIMER) { /* start timer */ 1967 /* Enable Timer */ 1968 devpriv->b_ModeSelectRegister = 1969 devpriv->b_ModeSelectRegister & 0x0B; 1970 } else { /* start watch dog */ 1971 /* Enable WatchDog */ 1972 devpriv->b_ModeSelectRegister = 1973 (devpriv-> 1974 b_ModeSelectRegister & 0x0B) | 1975 APCI3120_ENABLE_WATCHDOG; 1976 } 1977 1978 /* enable disable interrupt */ 1979 if ((devpriv->b_Timer2Interrupt) == APCI3120_ENABLE) { 1980 1981 devpriv->b_ModeSelectRegister = 1982 devpriv-> 1983 b_ModeSelectRegister | 1984 APCI3120_ENABLE_TIMER_INT; 1985 /* save the task structure to pass info to user */ 1986 devpriv->tsk_Current = current; 1987 } else { 1988 1989 devpriv->b_ModeSelectRegister = 1990 devpriv-> 1991 b_ModeSelectRegister & 1992 APCI3120_DISABLE_TIMER_INT; 1993 } 1994 outb(devpriv->b_ModeSelectRegister, 1995 devpriv->iobase + APCI3120_WRITE_MODE_SELECT); 1996 1997 if (devpriv->b_Timer2Mode == APCI3120_TIMER) { /* start timer */ 1998 /* For Timer mode is Gate2 must be activated **timer started */ 1999 devpriv->us_OutputRegister = 2000 devpriv-> 2001 us_OutputRegister | APCI3120_ENABLE_TIMER2; 2002 outw(devpriv->us_OutputRegister, 2003 devpriv->iobase + APCI3120_WR_ADDRESS); 2004 } 2005 2006 break; 2007 2008 case APCI3120_STOP: 2009 if (devpriv->b_Timer2Mode == APCI3120_TIMER) { 2010 /* Disable timer */ 2011 devpriv->b_ModeSelectRegister = 2012 devpriv-> 2013 b_ModeSelectRegister & 2014 APCI3120_DISABLE_TIMER_COUNTER; 2015 } else { 2016 /* Disable WatchDog */ 2017 devpriv->b_ModeSelectRegister = 2018 devpriv-> 2019 b_ModeSelectRegister & 2020 APCI3120_DISABLE_WATCHDOG; 2021 } 2022 /* Disable timer interrupt */ 2023 devpriv->b_ModeSelectRegister = 2024 devpriv-> 2025 b_ModeSelectRegister & APCI3120_DISABLE_TIMER_INT; 2026 2027 /* Write above states to register */ 2028 outb(devpriv->b_ModeSelectRegister, 2029 devpriv->iobase + APCI3120_WRITE_MODE_SELECT); 2030 2031 /* Reset Gate 2 */ 2032 devpriv->us_OutputRegister = 2033 devpriv->us_OutputRegister & APCI3120_DISABLE_TIMER_INT; 2034 outw(devpriv->us_OutputRegister, 2035 devpriv->iobase + APCI3120_WR_ADDRESS); 2036 2037 /* Reset FC_TIMER BIT */ 2038 inb(devpriv->iobase + APCI3120_TIMER_STATUS_REGISTER); 2039 2040 /* Disable timer */ 2041 /* devpriv->b_Timer2Mode=APCI3120_DISABLE; */ 2042 2043 break; 2044 2045 case 2: /* write new value to Timer */ 2046 if (devpriv->b_Timer2Mode != APCI3120_TIMER) { 2047 comedi_error(dev, 2048 "write :timer2 not configured in TIMER MODE"); 2049 return -EINVAL; 2050 } 2051 /* ui_Timervalue2=data[1]; // passed as argument */ 2052 us_TmpValue = 2053 (unsigned short) inw(devpriv->iobase + APCI3120_RD_STATUS); 2054 2055/* 2056 * EL250804: Testing if board APCI3120 have the new Quartz or if it 2057 * is an APCI3001 and calculate the time value to set in the timer 2058 */ 2059 if ((us_TmpValue & 0x00B0) == 0x00B0 2060 || !strcmp(this_board->pc_DriverName, "apci3001")) { 2061 /* Calculate the time value to set in the timer */ 2062 ui_Timervalue2 = ui_Timervalue2 / 50; 2063 } else { 2064 /* Calculate the time value to set in the timer */ 2065 ui_Timervalue2 = ui_Timervalue2 / 70; 2066 } 2067 /* Writing LOW unsigned short */ 2068 b_Tmp = ((devpriv-> 2069 b_DigitalOutputRegister) & 0xF0) | 2070 APCI3120_SELECT_TIMER_2_LOW_WORD; 2071 outb(b_Tmp, devpriv->iobase + APCI3120_TIMER_CRT0); 2072 2073 outw(LOWORD(ui_Timervalue2), 2074 devpriv->iobase + APCI3120_TIMER_VALUE); 2075 2076 /* Writing HIGH unsigned short */ 2077 b_Tmp = ((devpriv-> 2078 b_DigitalOutputRegister) & 0xF0) | 2079 APCI3120_SELECT_TIMER_2_HIGH_WORD; 2080 outb(b_Tmp, devpriv->iobase + APCI3120_TIMER_CRT0); 2081 2082 outw(HIWORD(ui_Timervalue2), 2083 devpriv->iobase + APCI3120_TIMER_VALUE); 2084 2085 break; 2086 default: 2087 return -EINVAL; /* Not a valid input */ 2088 } 2089 2090 return insn->n; 2091} 2092 2093/* 2094 * Read the Timer value 2095 * 2096 * for Timer: data[0]= Timer constant 2097 * 2098 * for watchdog: data[0] = 0 (still running) 2099 * = 1 (run down) 2100 */ 2101static int apci3120_read_insn_timer(struct comedi_device *dev, 2102 struct comedi_subdevice *s, 2103 struct comedi_insn *insn, 2104 unsigned int *data) 2105{ 2106 struct addi_private *devpriv = dev->private; 2107 unsigned char b_Tmp; 2108 unsigned short us_TmpValue, us_TmpValue_2, us_StatusValue; 2109 2110 if ((devpriv->b_Timer2Mode != APCI3120_WATCHDOG) 2111 && (devpriv->b_Timer2Mode != APCI3120_TIMER)) { 2112 comedi_error(dev, "\nread:timer2 not configured "); 2113 } 2114 2115 /* this_board->timer_read(dev,data); */ 2116 if (devpriv->b_Timer2Mode == APCI3120_TIMER) { 2117 2118 /* Read the LOW unsigned short of Timer 2 register */ 2119 b_Tmp = ((devpriv-> 2120 b_DigitalOutputRegister) & 0xF0) | 2121 APCI3120_SELECT_TIMER_2_LOW_WORD; 2122 outb(b_Tmp, devpriv->iobase + APCI3120_TIMER_CRT0); 2123 2124 us_TmpValue = inw(devpriv->iobase + APCI3120_TIMER_VALUE); 2125 2126 /* Read the HIGH unsigned short of Timer 2 register */ 2127 b_Tmp = ((devpriv-> 2128 b_DigitalOutputRegister) & 0xF0) | 2129 APCI3120_SELECT_TIMER_2_HIGH_WORD; 2130 outb(b_Tmp, devpriv->iobase + APCI3120_TIMER_CRT0); 2131 2132 us_TmpValue_2 = inw(devpriv->iobase + APCI3120_TIMER_VALUE); 2133 2134 /* combining both words */ 2135 data[0] = (unsigned int) ((us_TmpValue) | ((us_TmpValue_2) << 16)); 2136 2137 } else { /* Read watch dog status */ 2138 2139 us_StatusValue = inw(devpriv->iobase + APCI3120_RD_STATUS); 2140 us_StatusValue = 2141 ((us_StatusValue & APCI3120_FC_TIMER) >> 12) & 1; 2142 if (us_StatusValue == 1) { 2143 /* RESET FC_TIMER BIT */ 2144 inb(devpriv->iobase + APCI3120_TIMER_STATUS_REGISTER); 2145 } 2146 data[0] = us_StatusValue; /* when data[0] = 1 then the watch dog has rundown */ 2147 } 2148 return insn->n; 2149} 2150 2151static int apci3120_di_insn_bits(struct comedi_device *dev, 2152 struct comedi_subdevice *s, 2153 struct comedi_insn *insn, 2154 unsigned int *data) 2155{ 2156 struct addi_private *devpriv = dev->private; 2157 unsigned int val; 2158 2159 /* the input channels are bits 11:8 of the status reg */ 2160 val = inw(devpriv->iobase + APCI3120_RD_STATUS); 2161 data[1] = (val >> 8) & 0xf; 2162 2163 return insn->n; 2164} 2165 2166static int apci3120_do_insn_bits(struct comedi_device *dev, 2167 struct comedi_subdevice *s, 2168 struct comedi_insn *insn, 2169 unsigned int *data) 2170{ 2171 struct addi_private *devpriv = dev->private; 2172 2173 if (comedi_dio_update_state(s, data)) { 2174 /* The do channels are bits 7:4 of the do register */ 2175 devpriv->b_DigitalOutputRegister = s->state << 4; 2176 2177 outb(devpriv->b_DigitalOutputRegister, 2178 devpriv->iobase + APCI3120_DIGITAL_OUTPUT); 2179 } 2180 2181 data[1] = s->state; 2182 2183 return insn->n; 2184} 2185 2186static int apci3120_ao_insn_write(struct comedi_device *dev, 2187 struct comedi_subdevice *s, 2188 struct comedi_insn *insn, 2189 unsigned int *data) 2190{ 2191 struct addi_private *devpriv = dev->private; 2192 unsigned int ui_Range, ui_Channel; 2193 unsigned short us_TmpValue; 2194 2195 ui_Range = CR_RANGE(insn->chanspec); 2196 ui_Channel = CR_CHAN(insn->chanspec); 2197 2198 /* this_board->ao_write(dev, ui_Range, ui_Channel,data[0]); */ 2199 if (ui_Range) { /* if 1 then unipolar */ 2200 2201 if (data[0] != 0) 2202 data[0] = 2203 ((((ui_Channel & 0x03) << 14) & 0xC000) | (1 << 2204 13) | (data[0] + 8191)); 2205 else 2206 data[0] = 2207 ((((ui_Channel & 0x03) << 14) & 0xC000) | (1 << 2208 13) | 8192); 2209 2210 } else { /* if 0 then bipolar */ 2211 data[0] = 2212 ((((ui_Channel & 0x03) << 14) & 0xC000) | (0 << 13) | 2213 data[0]); 2214 2215 } 2216 2217/* 2218 * out put n values at the given channel. printk("\nwaiting for 2219 * DA_READY BIT"); 2220 */ 2221 do { /* Waiting of DA_READY BIT */ 2222 us_TmpValue = 2223 ((unsigned short) inw(devpriv->iobase + 2224 APCI3120_RD_STATUS)) & 0x0001; 2225 } while (us_TmpValue != 0x0001); 2226 2227 if (ui_Channel <= 3) 2228/* 2229 * for channel 0-3 out at the register 1 (wrDac1-8) data[i] 2230 * typecasted to ushort since word write is to be done 2231 */ 2232 outw((unsigned short) data[0], 2233 devpriv->iobase + APCI3120_ANALOG_OUTPUT_1); 2234 else 2235/* 2236 * for channel 4-7 out at the register 2 (wrDac5-8) data[i] 2237 * typecasted to ushort since word write is to be done 2238 */ 2239 outw((unsigned short) data[0], 2240 devpriv->iobase + APCI3120_ANALOG_OUTPUT_2); 2241 2242 return insn->n; 2243} 2244