1/* 2 3comedi/drivers/adl_pci9111.c 4 5Hardware driver for PCI9111 ADLink cards: 6 7PCI-9111HR 8 9Copyright (C) 2002-2005 Emmanuel Pacaud <emmanuel.pacaud@univ-poitiers.fr> 10 11This program is free software; you can redistribute it and/or modify 12it under the terms of the GNU General Public License as published by 13the Free Software Foundation; either version 2 of the License, or 14(at your option) any later version. 15 16This program is distributed in the hope that it will be useful, 17but WITHOUT ANY WARRANTY; without even the implied warranty of 18MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19GNU General Public License for more details. 20*/ 21 22/* 23Driver: adl_pci9111 24Description: Adlink PCI-9111HR 25Author: Emmanuel Pacaud <emmanuel.pacaud@univ-poitiers.fr> 26Devices: [ADLink] PCI-9111HR (adl_pci9111) 27Status: experimental 28 29Supports: 30 31 - ai_insn read 32 - ao_insn read/write 33 - di_insn read 34 - do_insn read/write 35 - ai_do_cmd mode with the following sources: 36 37 - start_src TRIG_NOW 38 - scan_begin_src TRIG_FOLLOW TRIG_TIMER TRIG_EXT 39 - convert_src TRIG_TIMER TRIG_EXT 40 - scan_end_src TRIG_COUNT 41 - stop_src TRIG_COUNT TRIG_NONE 42 43The scanned channels must be consecutive and start from 0. They must 44all have the same range and aref. 45 46Configuration options: not applicable, uses PCI auto config 47*/ 48 49/* 50CHANGELOG: 51 522005/02/17 Extend AI streaming capabilities. Now, scan_begin_arg can be 53a multiple of chanlist_len*convert_arg. 542002/02/19 Fixed the two's complement conversion in pci9111_(hr_)ai_get_data. 552002/02/18 Added external trigger support for analog input. 56 57TODO: 58 59 - Really test implemented functionality. 60 - Add support for the PCI-9111DG with a probe routine to identify 61 the card type (perhaps with the help of the channel number readback 62 of the A/D Data register). 63 - Add external multiplexer support. 64 65*/ 66 67#include <linux/module.h> 68#include <linux/pci.h> 69#include <linux/delay.h> 70#include <linux/interrupt.h> 71 72#include "../comedidev.h" 73 74#include "8253.h" 75#include "plx9052.h" 76#include "comedi_fc.h" 77 78#define PCI9111_FIFO_HALF_SIZE 512 79 80#define PCI9111_AI_ACQUISITION_PERIOD_MIN_NS 10000 81 82#define PCI9111_RANGE_SETTING_DELAY 10 83#define PCI9111_AI_INSTANT_READ_UDELAY_US 2 84 85/* 86 * IO address map and bit defines 87 */ 88#define PCI9111_AI_FIFO_REG 0x00 89#define PCI9111_AO_REG 0x00 90#define PCI9111_DIO_REG 0x02 91#define PCI9111_EDIO_REG 0x04 92#define PCI9111_AI_CHANNEL_REG 0x06 93#define PCI9111_AI_RANGE_STAT_REG 0x08 94#define PCI9111_AI_STAT_AD_BUSY (1 << 7) 95#define PCI9111_AI_STAT_FF_FF (1 << 6) 96#define PCI9111_AI_STAT_FF_HF (1 << 5) 97#define PCI9111_AI_STAT_FF_EF (1 << 4) 98#define PCI9111_AI_RANGE_MASK (7 << 0) 99#define PCI9111_AI_TRIG_CTRL_REG 0x0a 100#define PCI9111_AI_TRIG_CTRL_TRGEVENT (1 << 5) 101#define PCI9111_AI_TRIG_CTRL_POTRG (1 << 4) 102#define PCI9111_AI_TRIG_CTRL_PTRG (1 << 3) 103#define PCI9111_AI_TRIG_CTRL_ETIS (1 << 2) 104#define PCI9111_AI_TRIG_CTRL_TPST (1 << 1) 105#define PCI9111_AI_TRIG_CTRL_ASCAN (1 << 0) 106#define PCI9111_INT_CTRL_REG 0x0c 107#define PCI9111_INT_CTRL_ISC2 (1 << 3) 108#define PCI9111_INT_CTRL_FFEN (1 << 2) 109#define PCI9111_INT_CTRL_ISC1 (1 << 1) 110#define PCI9111_INT_CTRL_ISC0 (1 << 0) 111#define PCI9111_SOFT_TRIG_REG 0x0e 112#define PCI9111_8254_BASE_REG 0x40 113#define PCI9111_INT_CLR_REG 0x48 114 115/* PLX 9052 Local Interrupt 1 enabled and active */ 116#define PCI9111_LI1_ACTIVE (PLX9052_INTCSR_LI1ENAB | \ 117 PLX9052_INTCSR_LI1STAT) 118 119/* PLX 9052 Local Interrupt 2 enabled and active */ 120#define PCI9111_LI2_ACTIVE (PLX9052_INTCSR_LI2ENAB | \ 121 PLX9052_INTCSR_LI2STAT) 122 123static const struct comedi_lrange pci9111_ai_range = { 124 5, { 125 BIP_RANGE(10), 126 BIP_RANGE(5), 127 BIP_RANGE(2.5), 128 BIP_RANGE(1.25), 129 BIP_RANGE(0.625) 130 } 131}; 132 133struct pci9111_private_data { 134 unsigned long lcr_io_base; 135 136 int stop_counter; 137 138 unsigned int scan_delay; 139 unsigned int chunk_counter; 140 unsigned int chunk_num_samples; 141 142 unsigned int div1; 143 unsigned int div2; 144 145 unsigned short ai_bounce_buffer[2 * PCI9111_FIFO_HALF_SIZE]; 146}; 147 148static void plx9050_interrupt_control(unsigned long io_base, 149 bool LINTi1_enable, 150 bool LINTi1_active_high, 151 bool LINTi2_enable, 152 bool LINTi2_active_high, 153 bool interrupt_enable) 154{ 155 int flags = 0; 156 157 if (LINTi1_enable) 158 flags |= PLX9052_INTCSR_LI1ENAB; 159 if (LINTi1_active_high) 160 flags |= PLX9052_INTCSR_LI1POL; 161 if (LINTi2_enable) 162 flags |= PLX9052_INTCSR_LI2ENAB; 163 if (LINTi2_active_high) 164 flags |= PLX9052_INTCSR_LI2POL; 165 166 if (interrupt_enable) 167 flags |= PLX9052_INTCSR_PCIENAB; 168 169 outb(flags, io_base + PLX9052_INTCSR); 170} 171 172static void pci9111_timer_set(struct comedi_device *dev) 173{ 174 struct pci9111_private_data *dev_private = dev->private; 175 unsigned long timer_base = dev->iobase + PCI9111_8254_BASE_REG; 176 177 i8254_set_mode(timer_base, 1, 0, I8254_MODE0 | I8254_BINARY); 178 i8254_set_mode(timer_base, 1, 1, I8254_MODE2 | I8254_BINARY); 179 i8254_set_mode(timer_base, 1, 2, I8254_MODE2 | I8254_BINARY); 180 181 udelay(1); 182 183 i8254_write(timer_base, 1, 2, dev_private->div2); 184 i8254_write(timer_base, 1, 1, dev_private->div1); 185} 186 187enum pci9111_ISC0_sources { 188 irq_on_eoc, 189 irq_on_fifo_half_full 190}; 191 192enum pci9111_ISC1_sources { 193 irq_on_timer_tick, 194 irq_on_external_trigger 195}; 196 197static void pci9111_interrupt_source_set(struct comedi_device *dev, 198 enum pci9111_ISC0_sources irq_0_source, 199 enum pci9111_ISC1_sources irq_1_source) 200{ 201 int flags; 202 203 /* Read the current interrupt control bits */ 204 flags = inb(dev->iobase + PCI9111_AI_TRIG_CTRL_REG); 205 /* Shift the bits so they are compatible with the write register */ 206 flags >>= 4; 207 /* Mask off the ISCx bits */ 208 flags &= 0xc0; 209 210 /* Now set the new ISCx bits */ 211 if (irq_0_source == irq_on_fifo_half_full) 212 flags |= PCI9111_INT_CTRL_ISC0; 213 214 if (irq_1_source == irq_on_external_trigger) 215 flags |= PCI9111_INT_CTRL_ISC1; 216 217 outb(flags, dev->iobase + PCI9111_INT_CTRL_REG); 218} 219 220static void pci9111_fifo_reset(struct comedi_device *dev) 221{ 222 unsigned long int_ctrl_reg = dev->iobase + PCI9111_INT_CTRL_REG; 223 224 /* To reset the FIFO, set FFEN sequence as 0 -> 1 -> 0 */ 225 outb(0, int_ctrl_reg); 226 outb(PCI9111_INT_CTRL_FFEN, int_ctrl_reg); 227 outb(0, int_ctrl_reg); 228} 229 230static int pci9111_ai_cancel(struct comedi_device *dev, 231 struct comedi_subdevice *s) 232{ 233 struct pci9111_private_data *dev_private = dev->private; 234 235 /* Disable interrupts */ 236 plx9050_interrupt_control(dev_private->lcr_io_base, true, true, true, 237 true, false); 238 239 /* disable A/D triggers (software trigger mode) and auto scan off */ 240 outb(0, dev->iobase + PCI9111_AI_TRIG_CTRL_REG); 241 242 pci9111_fifo_reset(dev); 243 244 return 0; 245} 246 247static int pci9111_ai_check_chanlist(struct comedi_device *dev, 248 struct comedi_subdevice *s, 249 struct comedi_cmd *cmd) 250{ 251 unsigned int range0 = CR_RANGE(cmd->chanlist[0]); 252 unsigned int aref0 = CR_AREF(cmd->chanlist[0]); 253 int i; 254 255 for (i = 1; i < cmd->chanlist_len; i++) { 256 unsigned int chan = CR_CHAN(cmd->chanlist[i]); 257 unsigned int range = CR_RANGE(cmd->chanlist[i]); 258 unsigned int aref = CR_AREF(cmd->chanlist[i]); 259 260 if (chan != i) { 261 dev_dbg(dev->class_dev, 262 "entries in chanlist must be consecutive channels,counting upwards from 0\n"); 263 return -EINVAL; 264 } 265 266 if (range != range0) { 267 dev_dbg(dev->class_dev, 268 "entries in chanlist must all have the same gain\n"); 269 return -EINVAL; 270 } 271 272 if (aref != aref0) { 273 dev_dbg(dev->class_dev, 274 "entries in chanlist must all have the same reference\n"); 275 return -EINVAL; 276 } 277 } 278 279 return 0; 280} 281 282static int pci9111_ai_do_cmd_test(struct comedi_device *dev, 283 struct comedi_subdevice *s, 284 struct comedi_cmd *cmd) 285{ 286 struct pci9111_private_data *dev_private = dev->private; 287 int err = 0; 288 unsigned int arg; 289 290 /* Step 1 : check if triggers are trivially valid */ 291 292 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW); 293 err |= cfc_check_trigger_src(&cmd->scan_begin_src, 294 TRIG_TIMER | TRIG_FOLLOW | TRIG_EXT); 295 err |= cfc_check_trigger_src(&cmd->convert_src, 296 TRIG_TIMER | TRIG_EXT); 297 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT); 298 err |= cfc_check_trigger_src(&cmd->stop_src, 299 TRIG_COUNT | TRIG_NONE); 300 301 if (err) 302 return 1; 303 304 /* Step 2a : make sure trigger sources are unique */ 305 306 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src); 307 err |= cfc_check_trigger_is_unique(cmd->convert_src); 308 err |= cfc_check_trigger_is_unique(cmd->stop_src); 309 310 /* Step 2b : and mutually compatible */ 311 312 if (cmd->scan_begin_src != TRIG_FOLLOW) { 313 if (cmd->scan_begin_src != cmd->convert_src) 314 err |= -EINVAL; 315 } 316 317 if (err) 318 return 2; 319 320 /* Step 3: check if arguments are trivially valid */ 321 322 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0); 323 324 if (cmd->convert_src == TRIG_TIMER) 325 err |= cfc_check_trigger_arg_min(&cmd->convert_arg, 326 PCI9111_AI_ACQUISITION_PERIOD_MIN_NS); 327 else /* TRIG_EXT */ 328 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0); 329 330 if (cmd->scan_begin_src == TRIG_TIMER) 331 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg, 332 PCI9111_AI_ACQUISITION_PERIOD_MIN_NS); 333 else /* TRIG_FOLLOW || TRIG_EXT */ 334 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0); 335 336 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len); 337 338 if (cmd->stop_src == TRIG_COUNT) 339 err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1); 340 else /* TRIG_NONE */ 341 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0); 342 343 if (err) 344 return 3; 345 346 /* Step 4: fix up any arguments */ 347 348 if (cmd->convert_src == TRIG_TIMER) { 349 arg = cmd->convert_arg; 350 i8253_cascade_ns_to_timer(I8254_OSC_BASE_2MHZ, 351 &dev_private->div1, 352 &dev_private->div2, 353 &arg, cmd->flags); 354 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, arg); 355 } 356 357 /* 358 * There's only one timer on this card, so the scan_begin timer 359 * must be a multiple of chanlist_len*convert_arg 360 */ 361 if (cmd->scan_begin_src == TRIG_TIMER) { 362 arg = cmd->chanlist_len * cmd->convert_arg; 363 364 if (arg < cmd->scan_begin_arg) 365 arg *= (cmd->scan_begin_arg / arg); 366 367 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, arg); 368 } 369 370 if (err) 371 return 4; 372 373 /* Step 5: check channel list if it exists */ 374 if (cmd->chanlist && cmd->chanlist_len > 0) 375 err |= pci9111_ai_check_chanlist(dev, s, cmd); 376 377 if (err) 378 return 5; 379 380 return 0; 381 382} 383 384static int pci9111_ai_do_cmd(struct comedi_device *dev, 385 struct comedi_subdevice *s) 386{ 387 struct pci9111_private_data *dev_private = dev->private; 388 struct comedi_cmd *cmd = &s->async->cmd; 389 unsigned int last_chan = CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1]); 390 unsigned int trig = 0; 391 392 /* Set channel scan limit */ 393 /* PCI9111 allows only scanning from channel 0 to channel n */ 394 /* TODO: handle the case of an external multiplexer */ 395 396 if (cmd->chanlist_len > 1) 397 trig |= PCI9111_AI_TRIG_CTRL_ASCAN; 398 399 outb(last_chan, dev->iobase + PCI9111_AI_CHANNEL_REG); 400 401 /* Set gain */ 402 /* This is the same gain on every channel */ 403 404 outb(CR_RANGE(cmd->chanlist[0]) & PCI9111_AI_RANGE_MASK, 405 dev->iobase + PCI9111_AI_RANGE_STAT_REG); 406 407 /* Set counter */ 408 if (cmd->stop_src == TRIG_COUNT) 409 dev_private->stop_counter = cmd->stop_arg * cmd->chanlist_len; 410 else /* TRIG_NONE */ 411 dev_private->stop_counter = 0; 412 413 /* Set timer pacer */ 414 dev_private->scan_delay = 0; 415 if (cmd->convert_src == TRIG_TIMER) { 416 trig |= PCI9111_AI_TRIG_CTRL_TPST; 417 pci9111_timer_set(dev); 418 pci9111_fifo_reset(dev); 419 pci9111_interrupt_source_set(dev, irq_on_fifo_half_full, 420 irq_on_timer_tick); 421 plx9050_interrupt_control(dev_private->lcr_io_base, true, true, 422 false, true, true); 423 424 if (cmd->scan_begin_src == TRIG_TIMER) { 425 dev_private->scan_delay = (cmd->scan_begin_arg / 426 (cmd->convert_arg * cmd->chanlist_len)) - 1; 427 } 428 } else { /* TRIG_EXT */ 429 trig |= PCI9111_AI_TRIG_CTRL_ETIS; 430 pci9111_fifo_reset(dev); 431 pci9111_interrupt_source_set(dev, irq_on_fifo_half_full, 432 irq_on_timer_tick); 433 plx9050_interrupt_control(dev_private->lcr_io_base, true, true, 434 false, true, true); 435 } 436 outb(trig, dev->iobase + PCI9111_AI_TRIG_CTRL_REG); 437 438 dev_private->stop_counter *= (1 + dev_private->scan_delay); 439 dev_private->chunk_counter = 0; 440 dev_private->chunk_num_samples = cmd->chanlist_len * 441 (1 + dev_private->scan_delay); 442 443 return 0; 444} 445 446static void pci9111_ai_munge(struct comedi_device *dev, 447 struct comedi_subdevice *s, void *data, 448 unsigned int num_bytes, 449 unsigned int start_chan_index) 450{ 451 unsigned short *array = data; 452 unsigned int maxdata = s->maxdata; 453 unsigned int invert = (maxdata + 1) >> 1; 454 unsigned int shift = (maxdata == 0xffff) ? 0 : 4; 455 unsigned int num_samples = num_bytes / sizeof(short); 456 unsigned int i; 457 458 for (i = 0; i < num_samples; i++) 459 array[i] = ((array[i] >> shift) & maxdata) ^ invert; 460} 461 462static void pci9111_handle_fifo_half_full(struct comedi_device *dev, 463 struct comedi_subdevice *s) 464{ 465 struct pci9111_private_data *devpriv = dev->private; 466 struct comedi_cmd *cmd = &s->async->cmd; 467 unsigned int total = 0; 468 unsigned int samples; 469 470 if (cmd->stop_src == TRIG_COUNT && 471 PCI9111_FIFO_HALF_SIZE > devpriv->stop_counter) 472 samples = devpriv->stop_counter; 473 else 474 samples = PCI9111_FIFO_HALF_SIZE; 475 476 insw(dev->iobase + PCI9111_AI_FIFO_REG, 477 devpriv->ai_bounce_buffer, samples); 478 479 if (devpriv->scan_delay < 1) { 480 total = cfc_write_array_to_buffer(s, 481 devpriv->ai_bounce_buffer, 482 samples * sizeof(short)); 483 } else { 484 unsigned int pos = 0; 485 unsigned int to_read; 486 487 while (pos < samples) { 488 if (devpriv->chunk_counter < cmd->chanlist_len) { 489 to_read = cmd->chanlist_len - 490 devpriv->chunk_counter; 491 492 if (to_read > samples - pos) 493 to_read = samples - pos; 494 495 total += cfc_write_array_to_buffer(s, 496 devpriv->ai_bounce_buffer + pos, 497 to_read * sizeof(short)); 498 } else { 499 to_read = devpriv->chunk_num_samples - 500 devpriv->chunk_counter; 501 502 if (to_read > samples - pos) 503 to_read = samples - pos; 504 505 total += to_read * sizeof(short); 506 } 507 508 pos += to_read; 509 devpriv->chunk_counter += to_read; 510 511 if (devpriv->chunk_counter >= 512 devpriv->chunk_num_samples) 513 devpriv->chunk_counter = 0; 514 } 515 } 516 517 devpriv->stop_counter -= total / sizeof(short); 518} 519 520static irqreturn_t pci9111_interrupt(int irq, void *p_device) 521{ 522 struct comedi_device *dev = p_device; 523 struct pci9111_private_data *dev_private = dev->private; 524 struct comedi_subdevice *s = dev->read_subdev; 525 struct comedi_async *async; 526 struct comedi_cmd *cmd; 527 unsigned int status; 528 unsigned long irq_flags; 529 unsigned char intcsr; 530 531 if (!dev->attached) { 532 /* Ignore interrupt before device fully attached. */ 533 /* Might not even have allocated subdevices yet! */ 534 return IRQ_NONE; 535 } 536 537 async = s->async; 538 cmd = &async->cmd; 539 540 spin_lock_irqsave(&dev->spinlock, irq_flags); 541 542 /* Check if we are source of interrupt */ 543 intcsr = inb(dev_private->lcr_io_base + PLX9052_INTCSR); 544 if (!(((intcsr & PLX9052_INTCSR_PCIENAB) != 0) && 545 (((intcsr & PCI9111_LI1_ACTIVE) == PCI9111_LI1_ACTIVE) || 546 ((intcsr & PCI9111_LI2_ACTIVE) == PCI9111_LI2_ACTIVE)))) { 547 /* Not the source of the interrupt. */ 548 /* (N.B. not using PLX9052_INTCSR_SOFTINT) */ 549 spin_unlock_irqrestore(&dev->spinlock, irq_flags); 550 return IRQ_NONE; 551 } 552 553 if ((intcsr & PCI9111_LI1_ACTIVE) == PCI9111_LI1_ACTIVE) { 554 /* Interrupt comes from fifo_half-full signal */ 555 556 status = inb(dev->iobase + PCI9111_AI_RANGE_STAT_REG); 557 558 /* '0' means FIFO is full, data may have been lost */ 559 if (!(status & PCI9111_AI_STAT_FF_FF)) { 560 spin_unlock_irqrestore(&dev->spinlock, irq_flags); 561 dev_dbg(dev->class_dev, "fifo overflow\n"); 562 outb(0, dev->iobase + PCI9111_INT_CLR_REG); 563 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA; 564 cfc_handle_events(dev, s); 565 566 return IRQ_HANDLED; 567 } 568 569 /* '0' means FIFO is half-full */ 570 if (!(status & PCI9111_AI_STAT_FF_HF)) 571 pci9111_handle_fifo_half_full(dev, s); 572 } 573 574 if (cmd->stop_src == TRIG_COUNT && dev_private->stop_counter == 0) 575 async->events |= COMEDI_CB_EOA; 576 577 outb(0, dev->iobase + PCI9111_INT_CLR_REG); 578 579 spin_unlock_irqrestore(&dev->spinlock, irq_flags); 580 581 cfc_handle_events(dev, s); 582 583 return IRQ_HANDLED; 584} 585 586static int pci9111_ai_eoc(struct comedi_device *dev, 587 struct comedi_subdevice *s, 588 struct comedi_insn *insn, 589 unsigned long context) 590{ 591 unsigned int status; 592 593 status = inb(dev->iobase + PCI9111_AI_RANGE_STAT_REG); 594 if (status & PCI9111_AI_STAT_FF_EF) 595 return 0; 596 return -EBUSY; 597} 598 599static int pci9111_ai_insn_read(struct comedi_device *dev, 600 struct comedi_subdevice *s, 601 struct comedi_insn *insn, unsigned int *data) 602{ 603 unsigned int chan = CR_CHAN(insn->chanspec); 604 unsigned int range = CR_RANGE(insn->chanspec); 605 unsigned int maxdata = s->maxdata; 606 unsigned int invert = (maxdata + 1) >> 1; 607 unsigned int shift = (maxdata == 0xffff) ? 0 : 4; 608 unsigned int status; 609 int ret; 610 int i; 611 612 outb(chan, dev->iobase + PCI9111_AI_CHANNEL_REG); 613 614 status = inb(dev->iobase + PCI9111_AI_RANGE_STAT_REG); 615 if ((status & PCI9111_AI_RANGE_MASK) != range) { 616 outb(range & PCI9111_AI_RANGE_MASK, 617 dev->iobase + PCI9111_AI_RANGE_STAT_REG); 618 } 619 620 pci9111_fifo_reset(dev); 621 622 for (i = 0; i < insn->n; i++) { 623 /* Generate a software trigger */ 624 outb(0, dev->iobase + PCI9111_SOFT_TRIG_REG); 625 626 ret = comedi_timeout(dev, s, insn, pci9111_ai_eoc, 0); 627 if (ret) { 628 pci9111_fifo_reset(dev); 629 return ret; 630 } 631 632 data[i] = inw(dev->iobase + PCI9111_AI_FIFO_REG); 633 data[i] = ((data[i] >> shift) & maxdata) ^ invert; 634 } 635 636 return i; 637} 638 639static int pci9111_ao_insn_write(struct comedi_device *dev, 640 struct comedi_subdevice *s, 641 struct comedi_insn *insn, 642 unsigned int *data) 643{ 644 unsigned int chan = CR_CHAN(insn->chanspec); 645 unsigned int val = s->readback[chan]; 646 int i; 647 648 for (i = 0; i < insn->n; i++) { 649 val = data[i]; 650 outw(val, dev->iobase + PCI9111_AO_REG); 651 } 652 s->readback[chan] = val; 653 654 return insn->n; 655} 656 657static int pci9111_di_insn_bits(struct comedi_device *dev, 658 struct comedi_subdevice *s, 659 struct comedi_insn *insn, 660 unsigned int *data) 661{ 662 data[1] = inw(dev->iobase + PCI9111_DIO_REG); 663 664 return insn->n; 665} 666 667static int pci9111_do_insn_bits(struct comedi_device *dev, 668 struct comedi_subdevice *s, 669 struct comedi_insn *insn, 670 unsigned int *data) 671{ 672 if (comedi_dio_update_state(s, data)) 673 outw(s->state, dev->iobase + PCI9111_DIO_REG); 674 675 data[1] = s->state; 676 677 return insn->n; 678} 679 680static int pci9111_reset(struct comedi_device *dev) 681{ 682 struct pci9111_private_data *dev_private = dev->private; 683 684 /* Set trigger source to software */ 685 plx9050_interrupt_control(dev_private->lcr_io_base, true, true, true, 686 true, false); 687 688 /* disable A/D triggers (software trigger mode) and auto scan off */ 689 outb(0, dev->iobase + PCI9111_AI_TRIG_CTRL_REG); 690 691 /* Reset 8254 chip */ 692 dev_private->div1 = 0; 693 dev_private->div2 = 0; 694 pci9111_timer_set(dev); 695 696 return 0; 697} 698 699static int pci9111_auto_attach(struct comedi_device *dev, 700 unsigned long context_unused) 701{ 702 struct pci_dev *pcidev = comedi_to_pci_dev(dev); 703 struct pci9111_private_data *dev_private; 704 struct comedi_subdevice *s; 705 int ret; 706 707 dev_private = comedi_alloc_devpriv(dev, sizeof(*dev_private)); 708 if (!dev_private) 709 return -ENOMEM; 710 711 ret = comedi_pci_enable(dev); 712 if (ret) 713 return ret; 714 dev_private->lcr_io_base = pci_resource_start(pcidev, 1); 715 dev->iobase = pci_resource_start(pcidev, 2); 716 717 pci9111_reset(dev); 718 719 if (pcidev->irq) { 720 ret = request_irq(pcidev->irq, pci9111_interrupt, 721 IRQF_SHARED, dev->board_name, dev); 722 if (ret == 0) 723 dev->irq = pcidev->irq; 724 } 725 726 ret = comedi_alloc_subdevices(dev, 4); 727 if (ret) 728 return ret; 729 730 s = &dev->subdevices[0]; 731 s->type = COMEDI_SUBD_AI; 732 s->subdev_flags = SDF_READABLE | SDF_COMMON; 733 s->n_chan = 16; 734 s->maxdata = 0xffff; 735 s->range_table = &pci9111_ai_range; 736 s->insn_read = pci9111_ai_insn_read; 737 if (dev->irq) { 738 dev->read_subdev = s; 739 s->subdev_flags |= SDF_CMD_READ; 740 s->len_chanlist = s->n_chan; 741 s->do_cmdtest = pci9111_ai_do_cmd_test; 742 s->do_cmd = pci9111_ai_do_cmd; 743 s->cancel = pci9111_ai_cancel; 744 s->munge = pci9111_ai_munge; 745 } 746 747 s = &dev->subdevices[1]; 748 s->type = COMEDI_SUBD_AO; 749 s->subdev_flags = SDF_WRITABLE | SDF_COMMON; 750 s->n_chan = 1; 751 s->maxdata = 0x0fff; 752 s->len_chanlist = 1; 753 s->range_table = &range_bipolar10; 754 s->insn_write = pci9111_ao_insn_write; 755 s->insn_read = comedi_readback_insn_read; 756 757 ret = comedi_alloc_subdev_readback(s); 758 if (ret) 759 return ret; 760 761 s = &dev->subdevices[2]; 762 s->type = COMEDI_SUBD_DI; 763 s->subdev_flags = SDF_READABLE; 764 s->n_chan = 16; 765 s->maxdata = 1; 766 s->range_table = &range_digital; 767 s->insn_bits = pci9111_di_insn_bits; 768 769 s = &dev->subdevices[3]; 770 s->type = COMEDI_SUBD_DO; 771 s->subdev_flags = SDF_READABLE | SDF_WRITABLE; 772 s->n_chan = 16; 773 s->maxdata = 1; 774 s->range_table = &range_digital; 775 s->insn_bits = pci9111_do_insn_bits; 776 777 return 0; 778} 779 780static void pci9111_detach(struct comedi_device *dev) 781{ 782 if (dev->iobase) 783 pci9111_reset(dev); 784 comedi_pci_detach(dev); 785} 786 787static struct comedi_driver adl_pci9111_driver = { 788 .driver_name = "adl_pci9111", 789 .module = THIS_MODULE, 790 .auto_attach = pci9111_auto_attach, 791 .detach = pci9111_detach, 792}; 793 794static int pci9111_pci_probe(struct pci_dev *dev, 795 const struct pci_device_id *id) 796{ 797 return comedi_pci_auto_config(dev, &adl_pci9111_driver, 798 id->driver_data); 799} 800 801static const struct pci_device_id pci9111_pci_table[] = { 802 { PCI_DEVICE(PCI_VENDOR_ID_ADLINK, 0x9111) }, 803 /* { PCI_DEVICE(PCI_VENDOR_ID_ADLINK, PCI9111_HG_DEVICE_ID) }, */ 804 { 0 } 805}; 806MODULE_DEVICE_TABLE(pci, pci9111_pci_table); 807 808static struct pci_driver adl_pci9111_pci_driver = { 809 .name = "adl_pci9111", 810 .id_table = pci9111_pci_table, 811 .probe = pci9111_pci_probe, 812 .remove = comedi_pci_auto_unconfig, 813}; 814module_comedi_pci_driver(adl_pci9111_driver, adl_pci9111_pci_driver); 815 816MODULE_AUTHOR("Comedi http://www.comedi.org"); 817MODULE_DESCRIPTION("Comedi low-level driver"); 818MODULE_LICENSE("GPL"); 819