1e948cb522499441996a9580b55bde1585b5c22c5Ian Abbott/*
2e948cb522499441996a9580b55bde1585b5c22c5Ian Abbott    comedi/drivers/amplc_dio200.c
3e948cb522499441996a9580b55bde1585b5c22c5Ian Abbott
47ff7e4c2c460f55a96d09b33ce421f91a9b6a0fbIan Abbott    Driver for Amplicon PC212E, PC214E, PC215E, PC218E, PC272E.
57ff7e4c2c460f55a96d09b33ce421f91a9b6a0fbIan Abbott
67ff7e4c2c460f55a96d09b33ce421f91a9b6a0fbIan Abbott    Copyright (C) 2005-2013 MEV Ltd. <http://www.mev.co.uk/>
7e948cb522499441996a9580b55bde1585b5c22c5Ian Abbott
8e948cb522499441996a9580b55bde1585b5c22c5Ian Abbott    COMEDI - Linux Control and Measurement Device Interface
9e948cb522499441996a9580b55bde1585b5c22c5Ian Abbott    Copyright (C) 1998,2000 David A. Schleef <ds@schleef.org>
10e948cb522499441996a9580b55bde1585b5c22c5Ian Abbott
11e948cb522499441996a9580b55bde1585b5c22c5Ian Abbott    This program is free software; you can redistribute it and/or modify
12e948cb522499441996a9580b55bde1585b5c22c5Ian Abbott    it under the terms of the GNU General Public License as published by
13e948cb522499441996a9580b55bde1585b5c22c5Ian Abbott    the Free Software Foundation; either version 2 of the License, or
14e948cb522499441996a9580b55bde1585b5c22c5Ian Abbott    (at your option) any later version.
15e948cb522499441996a9580b55bde1585b5c22c5Ian Abbott
16e948cb522499441996a9580b55bde1585b5c22c5Ian Abbott    This program is distributed in the hope that it will be useful,
17e948cb522499441996a9580b55bde1585b5c22c5Ian Abbott    but WITHOUT ANY WARRANTY; without even the implied warranty of
18e948cb522499441996a9580b55bde1585b5c22c5Ian Abbott    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19e948cb522499441996a9580b55bde1585b5c22c5Ian Abbott    GNU General Public License for more details.
20e948cb522499441996a9580b55bde1585b5c22c5Ian Abbott*/
21e948cb522499441996a9580b55bde1585b5c22c5Ian Abbott/*
2241b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott * Driver: amplc_dio200
237ff7e4c2c460f55a96d09b33ce421f91a9b6a0fbIan Abbott * Description: Amplicon 200 Series ISA Digital I/O
2441b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott * Author: Ian Abbott <abbotti@mev.co.uk>
2541b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott * Devices: [Amplicon] PC212E (pc212e), PC214E (pc214e), PC215E (pc215e),
267ff7e4c2c460f55a96d09b33ce421f91a9b6a0fbIan Abbott *   PC218E (pc218e), PC272E (pc272e)
277ff7e4c2c460f55a96d09b33ce421f91a9b6a0fbIan Abbott * Updated: Mon, 18 Mar 2013 14:40:41 +0000
287ff7e4c2c460f55a96d09b33ce421f91a9b6a0fbIan Abbott *
2941b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott * Status: works
3041b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *
317ff7e4c2c460f55a96d09b33ce421f91a9b6a0fbIan Abbott * Configuration options:
3241b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *   [0] - I/O port base address
3341b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *   [1] - IRQ (optional, but commands won't work without it)
3441b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *
3541b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott * Passing a zero for an option is the same as leaving it unspecified.
3641b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *
3741b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott * SUBDEVICES
3841b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *
397ff7e4c2c460f55a96d09b33ce421f91a9b6a0fbIan Abbott *                     PC212E         PC214E         PC215E
4041b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *                  -------------  -------------  -------------
412421a0242e17445ab35f7b450d0768518f0f63e6Ian Abbott *   Subdevices           6              4              5
422421a0242e17445ab35f7b450d0768518f0f63e6Ian Abbott *    0                 PPI-X          PPI-X          PPI-X
432421a0242e17445ab35f7b450d0768518f0f63e6Ian Abbott *    1                 CTR-Y1         PPI-Y          PPI-Y
442421a0242e17445ab35f7b450d0768518f0f63e6Ian Abbott *    2                 CTR-Y2         CTR-Z1*        CTR-Z1
452421a0242e17445ab35f7b450d0768518f0f63e6Ian Abbott *    3                 CTR-Z1       INTERRUPT*       CTR-Z2
462421a0242e17445ab35f7b450d0768518f0f63e6Ian Abbott *    4                 CTR-Z2                      INTERRUPT
472421a0242e17445ab35f7b450d0768518f0f63e6Ian Abbott *    5               INTERRUPT
4841b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *
497ff7e4c2c460f55a96d09b33ce421f91a9b6a0fbIan Abbott *                     PC218E         PC272E
5041b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *                  -------------  -------------
517ff7e4c2c460f55a96d09b33ce421f91a9b6a0fbIan Abbott *   Subdevices           7              4
527ff7e4c2c460f55a96d09b33ce421f91a9b6a0fbIan Abbott *    0                 CTR-X1         PPI-X
537ff7e4c2c460f55a96d09b33ce421f91a9b6a0fbIan Abbott *    1                 CTR-X2         PPI-Y
547ff7e4c2c460f55a96d09b33ce421f91a9b6a0fbIan Abbott *    2                 CTR-Y1         PPI-Z
557ff7e4c2c460f55a96d09b33ce421f91a9b6a0fbIan Abbott *    3                 CTR-Y2       INTERRUPT
567ff7e4c2c460f55a96d09b33ce421f91a9b6a0fbIan Abbott *    4                 CTR-Z1
577ff7e4c2c460f55a96d09b33ce421f91a9b6a0fbIan Abbott *    5                 CTR-Z2
587ff7e4c2c460f55a96d09b33ce421f91a9b6a0fbIan Abbott *    6               INTERRUPT
5941b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *
6041b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott * Each PPI is a 8255 chip providing 24 DIO channels.  The DIO channels
6141b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott * are configurable as inputs or outputs in four groups:
6241b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *
6341b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *   Port A  - channels  0 to  7
6441b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *   Port B  - channels  8 to 15
6541b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *   Port CL - channels 16 to 19
6641b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *   Port CH - channels 20 to 23
6741b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *
6841b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott * Only mode 0 of the 8255 chips is supported.
6941b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *
7041b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott * Each CTR is a 8254 chip providing 3 16-bit counter channels.  Each
7141b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott * channel is configured individually with INSN_CONFIG instructions.  The
7241b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott * specific type of configuration instruction is specified in data[0].
7341b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott * Some configuration instructions expect an additional parameter in
7441b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott * data[1]; others return a value in data[1].  The following configuration
7541b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott * instructions are supported:
7641b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *
7741b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *   INSN_CONFIG_SET_COUNTER_MODE.  Sets the counter channel's mode and
7841b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *     BCD/binary setting specified in data[1].
7941b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *
8041b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *   INSN_CONFIG_8254_READ_STATUS.  Reads the status register value for the
8141b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *     counter channel into data[1].
8241b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *
8341b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *   INSN_CONFIG_SET_CLOCK_SRC.  Sets the counter channel's clock source as
8441b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *     specified in data[1] (this is a hardware-specific value).  Not
8541b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *     supported on PC214E.  For the other boards, valid clock sources are
8641b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *     0 to 7 as follows:
8741b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *
8841b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *       0.  CLK n, the counter channel's dedicated CLK input from the SK1
8941b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *         connector.  (N.B. for other values, the counter channel's CLKn
9041b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *         pin on the SK1 connector is an output!)
9141b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *       1.  Internal 10 MHz clock.
9241b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *       2.  Internal 1 MHz clock.
9341b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *       3.  Internal 100 kHz clock.
9441b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *       4.  Internal 10 kHz clock.
9541b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *       5.  Internal 1 kHz clock.
9641b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *       6.  OUT n-1, the output of counter channel n-1 (see note 1 below).
9741b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *       7.  Ext Clock, the counter chip's dedicated Ext Clock input from
9841b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *         the SK1 connector.  This pin is shared by all three counter
9941b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *         channels on the chip.
10041b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *
10141b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *   INSN_CONFIG_GET_CLOCK_SRC.  Returns the counter channel's current
10241b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *     clock source in data[1].  For internal clock sources, data[2] is set
10341b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *     to the period in ns.
10441b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *
10541b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *   INSN_CONFIG_SET_GATE_SRC.  Sets the counter channel's gate source as
10641b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *     specified in data[2] (this is a hardware-specific value).  Not
10741b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *     supported on PC214E.  For the other boards, valid gate sources are 0
10841b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *     to 7 as follows:
10941b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *
11041b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *       0.  VCC (internal +5V d.c.), i.e. gate permanently enabled.
11141b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *       1.  GND (internal 0V d.c.), i.e. gate permanently disabled.
11241b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *       2.  GAT n, the counter channel's dedicated GAT input from the SK1
11341b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *         connector.  (N.B. for other values, the counter channel's GATn
11441b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *         pin on the SK1 connector is an output!)
11541b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *       3.  /OUT n-2, the inverted output of counter channel n-2 (see note
11641b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *         2 below).
11741b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *       4.  Reserved.
11841b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *       5.  Reserved.
11941b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *       6.  Reserved.
12041b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *       7.  Reserved.
12141b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *
12241b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *   INSN_CONFIG_GET_GATE_SRC.  Returns the counter channel's current gate
12341b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *     source in data[2].
12441b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *
12541b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott * Clock and gate interconnection notes:
12641b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *
12741b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *   1.  Clock source OUT n-1 is the output of the preceding channel on the
12841b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *   same counter subdevice if n > 0, or the output of channel 2 on the
12941b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *   preceding counter subdevice (see note 3) if n = 0.
13041b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *
13141b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *   2.  Gate source /OUT n-2 is the inverted output of channel 0 on the
13241b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *   same counter subdevice if n = 2, or the inverted output of channel n+1
13341b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *   on the preceding counter subdevice (see note 3) if n < 2.
13441b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *
13541b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *   3.  The counter subdevices are connected in a ring, so the highest
13641b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *   counter subdevice precedes the lowest.
13741b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *
13841b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott * The 'INTERRUPT' subdevice pretends to be a digital input subdevice.  The
13941b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott * digital inputs come from the interrupt status register.  The number of
14041b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott * channels matches the number of interrupt sources.  The PC214E does not
14141b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott * have an interrupt status register; see notes on 'INTERRUPT SOURCES'
14241b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott * below.
14341b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *
14441b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott * INTERRUPT SOURCES
14541b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *
1467ff7e4c2c460f55a96d09b33ce421f91a9b6a0fbIan Abbott *                     PC212E         PC214E         PC215E
1472421a0242e17445ab35f7b450d0768518f0f63e6Ian Abbott *                  -------------  -------------  -------------
1482421a0242e17445ab35f7b450d0768518f0f63e6Ian Abbott *   Sources              6              1              6
1492421a0242e17445ab35f7b450d0768518f0f63e6Ian Abbott *    0               PPI-X-C0       JUMPER-J5      PPI-X-C0
1502421a0242e17445ab35f7b450d0768518f0f63e6Ian Abbott *    1               PPI-X-C3                      PPI-X-C3
1512421a0242e17445ab35f7b450d0768518f0f63e6Ian Abbott *    2              CTR-Y1-OUT1                    PPI-Y-C0
1522421a0242e17445ab35f7b450d0768518f0f63e6Ian Abbott *    3              CTR-Y2-OUT1                    PPI-Y-C3
1532421a0242e17445ab35f7b450d0768518f0f63e6Ian Abbott *    4              CTR-Z1-OUT1                   CTR-Z1-OUT1
1542421a0242e17445ab35f7b450d0768518f0f63e6Ian Abbott *    5              CTR-Z2-OUT1                   CTR-Z2-OUT1
1552421a0242e17445ab35f7b450d0768518f0f63e6Ian Abbott *
1567ff7e4c2c460f55a96d09b33ce421f91a9b6a0fbIan Abbott *                     PC218E         PC272E
15741b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *                  -------------  -------------
1582421a0242e17445ab35f7b450d0768518f0f63e6Ian Abbott *   Sources              6              6
1597ff7e4c2c460f55a96d09b33ce421f91a9b6a0fbIan Abbott *    0              CTR-X1-OUT1     PPI-X-C0
1607ff7e4c2c460f55a96d09b33ce421f91a9b6a0fbIan Abbott *    1              CTR-X2-OUT1     PPI-X-C3
1617ff7e4c2c460f55a96d09b33ce421f91a9b6a0fbIan Abbott *    2              CTR-Y1-OUT1     PPI-Y-C0
1627ff7e4c2c460f55a96d09b33ce421f91a9b6a0fbIan Abbott *    3              CTR-Y2-OUT1     PPI-Y-C3
1637ff7e4c2c460f55a96d09b33ce421f91a9b6a0fbIan Abbott *    4              CTR-Z1-OUT1     PPI-Z-C0
1647ff7e4c2c460f55a96d09b33ce421f91a9b6a0fbIan Abbott *    5              CTR-Z2-OUT1     PPI-Z-C3
16541b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *
16641b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott * When an interrupt source is enabled in the interrupt source enable
16741b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott * register, a rising edge on the source signal latches the corresponding
16841b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott * bit to 1 in the interrupt status register.
16941b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *
17041b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott * When the interrupt status register value as a whole (actually, just the
17141b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott * 6 least significant bits) goes from zero to non-zero, the board will
1727ff7e4c2c460f55a96d09b33ce421f91a9b6a0fbIan Abbott * generate an interrupt.  No further interrupts will occur until the
1737ff7e4c2c460f55a96d09b33ce421f91a9b6a0fbIan Abbott * interrupt status register is cleared to zero.  To clear a bit to zero in
1747ff7e4c2c460f55a96d09b33ce421f91a9b6a0fbIan Abbott * the interrupt status register, the corresponding interrupt source must
1757ff7e4c2c460f55a96d09b33ce421f91a9b6a0fbIan Abbott * be disabled in the interrupt source enable register (there is no
1767ff7e4c2c460f55a96d09b33ce421f91a9b6a0fbIan Abbott * separate interrupt clear register).
17741b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *
17841b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott * The PC214E does not have an interrupt source enable register or an
17941b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott * interrupt status register; its 'INTERRUPT' subdevice has a single
18041b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott * channel and its interrupt source is selected by the position of jumper
18141b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott * J5.
18241b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *
18341b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott * COMMANDS
18441b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott *
18541b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott * The driver supports a read streaming acquisition command on the
18641b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott * 'INTERRUPT' subdevice.  The channel list selects the interrupt sources
18741b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott * to be enabled.  All channels will be sampled together (convert_src ==
18841b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott * TRIG_NOW).  The scan begins a short time after the hardware interrupt
18941b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott * occurs, subject to interrupt latencies (scan_begin_src == TRIG_EXT,
19041b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott * scan_begin_arg == 0).  The value read from the interrupt status register
19141b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott * is packed into a short value, one bit per requested channel, in the
19241b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott * order they appear in the channel list.
19341b25f871405a4abd6055ca47d3f3056c75200e7Ian Abbott */
194e948cb522499441996a9580b55bde1585b5c22c5Ian Abbott
195ce157f8032bbd46d9427034c335b0afd751da25dH Hartley Sweeten#include <linux/module.h>
196e948cb522499441996a9580b55bde1585b5c22c5Ian Abbott#include "../comedidev.h"
197e948cb522499441996a9580b55bde1585b5c22c5Ian Abbott
1987ff7e4c2c460f55a96d09b33ce421f91a9b6a0fbIan Abbott#include "amplc_dio200.h"
199f7282f05e1cb39556b5e29d113803e934f3e6d3eIan Abbott
200f7282f05e1cb39556b5e29d113803e934f3e6d3eIan Abbott/*
201e948cb522499441996a9580b55bde1585b5c22c5Ian Abbott * Board descriptions.
202e948cb522499441996a9580b55bde1585b5c22c5Ian Abbott */
2033d9bfccd13252efffbe2f31e8e66cecfd9e6cc65Ian Abbottstatic const struct dio200_board dio200_isa_boards[] = {
204e948cb522499441996a9580b55bde1585b5c22c5Ian Abbott	{
205f6ce09504ddc81aec07ddfcb16ad3c5b80ab19d0H Hartley Sweeten		.name		= "pc212e",
206f6ce09504ddc81aec07ddfcb16ad3c5b80ab19d0H Hartley Sweeten		.n_subdevs	= 6,
207f6ce09504ddc81aec07ddfcb16ad3c5b80ab19d0H Hartley Sweeten		.sdtype		= {
208f6ce09504ddc81aec07ddfcb16ad3c5b80ab19d0H Hartley Sweeten			sd_8255, sd_8254, sd_8254, sd_8254, sd_8254, sd_intr
209f7282f05e1cb39556b5e29d113803e934f3e6d3eIan Abbott		},
210f6ce09504ddc81aec07ddfcb16ad3c5b80ab19d0H Hartley Sweeten		.sdinfo		= { 0x00, 0x08, 0x0c, 0x10, 0x14, 0x3f },
211f6ce09504ddc81aec07ddfcb16ad3c5b80ab19d0H Hartley Sweeten		.has_int_sce	= true,
212f6ce09504ddc81aec07ddfcb16ad3c5b80ab19d0H Hartley Sweeten		.has_clk_gat_sce = true,
213f6ce09504ddc81aec07ddfcb16ad3c5b80ab19d0H Hartley Sweeten	}, {
214f6ce09504ddc81aec07ddfcb16ad3c5b80ab19d0H Hartley Sweeten		.name		= "pc214e",
215f6ce09504ddc81aec07ddfcb16ad3c5b80ab19d0H Hartley Sweeten		.n_subdevs	= 4,
216f6ce09504ddc81aec07ddfcb16ad3c5b80ab19d0H Hartley Sweeten		.sdtype		= {
217f6ce09504ddc81aec07ddfcb16ad3c5b80ab19d0H Hartley Sweeten			sd_8255, sd_8255, sd_8254, sd_intr
218f7282f05e1cb39556b5e29d113803e934f3e6d3eIan Abbott		},
219f6ce09504ddc81aec07ddfcb16ad3c5b80ab19d0H Hartley Sweeten		.sdinfo		= { 0x00, 0x08, 0x10, 0x01 },
220f6ce09504ddc81aec07ddfcb16ad3c5b80ab19d0H Hartley Sweeten	}, {
221f6ce09504ddc81aec07ddfcb16ad3c5b80ab19d0H Hartley Sweeten		.name		= "pc215e",
222f6ce09504ddc81aec07ddfcb16ad3c5b80ab19d0H Hartley Sweeten		.n_subdevs	= 5,
223f6ce09504ddc81aec07ddfcb16ad3c5b80ab19d0H Hartley Sweeten		.sdtype		= {
224f6ce09504ddc81aec07ddfcb16ad3c5b80ab19d0H Hartley Sweeten			sd_8255, sd_8255, sd_8254, sd_8254, sd_intr
225f7282f05e1cb39556b5e29d113803e934f3e6d3eIan Abbott		},
226f6ce09504ddc81aec07ddfcb16ad3c5b80ab19d0H Hartley Sweeten		.sdinfo		= { 0x00, 0x08, 0x10, 0x14, 0x3f },
227f6ce09504ddc81aec07ddfcb16ad3c5b80ab19d0H Hartley Sweeten		.has_int_sce	= true,
228f6ce09504ddc81aec07ddfcb16ad3c5b80ab19d0H Hartley Sweeten		.has_clk_gat_sce = true,
229f6ce09504ddc81aec07ddfcb16ad3c5b80ab19d0H Hartley Sweeten	}, {
230f6ce09504ddc81aec07ddfcb16ad3c5b80ab19d0H Hartley Sweeten		.name		= "pc218e",
231f6ce09504ddc81aec07ddfcb16ad3c5b80ab19d0H Hartley Sweeten		.n_subdevs	= 7,
232f6ce09504ddc81aec07ddfcb16ad3c5b80ab19d0H Hartley Sweeten		.sdtype		= {
233f6ce09504ddc81aec07ddfcb16ad3c5b80ab19d0H Hartley Sweeten			sd_8254, sd_8254, sd_8255, sd_8254, sd_8254, sd_intr
234f7282f05e1cb39556b5e29d113803e934f3e6d3eIan Abbott		},
235f6ce09504ddc81aec07ddfcb16ad3c5b80ab19d0H Hartley Sweeten		.sdinfo		= { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x3f },
236f6ce09504ddc81aec07ddfcb16ad3c5b80ab19d0H Hartley Sweeten		.has_int_sce	= true,
237f6ce09504ddc81aec07ddfcb16ad3c5b80ab19d0H Hartley Sweeten		.has_clk_gat_sce = true,
238f6ce09504ddc81aec07ddfcb16ad3c5b80ab19d0H Hartley Sweeten	}, {
239f6ce09504ddc81aec07ddfcb16ad3c5b80ab19d0H Hartley Sweeten		.name		= "pc272e",
240f6ce09504ddc81aec07ddfcb16ad3c5b80ab19d0H Hartley Sweeten		.n_subdevs	= 4,
241f6ce09504ddc81aec07ddfcb16ad3c5b80ab19d0H Hartley Sweeten		.sdtype		= {
242f6ce09504ddc81aec07ddfcb16ad3c5b80ab19d0H Hartley Sweeten			sd_8255, sd_8255, sd_8255, sd_intr
243f7282f05e1cb39556b5e29d113803e934f3e6d3eIan Abbott		},
244f6ce09504ddc81aec07ddfcb16ad3c5b80ab19d0H Hartley Sweeten		.sdinfo		= { 0x00, 0x08, 0x10, 0x3f },
245f6ce09504ddc81aec07ddfcb16ad3c5b80ab19d0H Hartley Sweeten		.has_int_sce = true,
2463d9bfccd13252efffbe2f31e8e66cecfd9e6cc65Ian Abbott	},
2473d9bfccd13252efffbe2f31e8e66cecfd9e6cc65Ian Abbott};
24887276012ead9f96f249fedf715b1052106f2e0d0Ian Abbott
2497ff7e4c2c460f55a96d09b33ce421f91a9b6a0fbIan Abbottstatic int dio200_attach(struct comedi_device *dev, struct comedi_devconfig *it)
250e948cb522499441996a9580b55bde1585b5c22c5Ian Abbott{
2517ff7e4c2c460f55a96d09b33ce421f91a9b6a0fbIan Abbott	int ret;
252e948cb522499441996a9580b55bde1585b5c22c5Ian Abbott
253cf200de92ffd97ee46f6affeb8240448319af8aeH Hartley Sweeten	ret = comedi_request_region(dev, it->options[0], 0x20);
25471827d43421824a11ac50d83b9e212061a84b025H Hartley Sweeten	if (ret)
2557ff7e4c2c460f55a96d09b33ce421f91a9b6a0fbIan Abbott		return ret;
2560c3dfdc2d9a913c227a71f8cf728a70316c3abb4H Hartley Sweeten
257acb165135dcf48875e44fe323aa63653785bf01cH Hartley Sweeten	return amplc_dio200_common_attach(dev, it->options[1], 0);
258e948cb522499441996a9580b55bde1585b5c22c5Ian Abbott}
259e948cb522499441996a9580b55bde1585b5c22c5Ian Abbott
260fd97962b4142fc3460d3628c3842be6d33b9aa94Ian Abbottstatic struct comedi_driver amplc_dio200_driver = {
261849db1aacd223b25826246171519413fad601df6H Hartley Sweeten	.driver_name	= "amplc_dio200",
262849db1aacd223b25826246171519413fad601df6H Hartley Sweeten	.module		= THIS_MODULE,
263849db1aacd223b25826246171519413fad601df6H Hartley Sweeten	.attach		= dio200_attach,
264bb83abed7dd79ae1f0471c53144934efa57d7919H Hartley Sweeten	.detach		= comedi_legacy_detach,
265849db1aacd223b25826246171519413fad601df6H Hartley Sweeten	.board_name	= &dio200_isa_boards[0].name,
266849db1aacd223b25826246171519413fad601df6H Hartley Sweeten	.offset		= sizeof(struct dio200_board),
267849db1aacd223b25826246171519413fad601df6H Hartley Sweeten	.num_names	= ARRAY_SIZE(dio200_isa_boards),
268fd97962b4142fc3460d3628c3842be6d33b9aa94Ian Abbott};
269fd97962b4142fc3460d3628c3842be6d33b9aa94Ian Abbottmodule_comedi_driver(amplc_dio200_driver);
270fd97962b4142fc3460d3628c3842be6d33b9aa94Ian Abbott
27190f703d30dd3e0c16ff80f35e34e511385a05ad5Arun ThomasMODULE_AUTHOR("Comedi http://www.comedi.org");
2727ff7e4c2c460f55a96d09b33ce421f91a9b6a0fbIan AbbottMODULE_DESCRIPTION("Comedi driver for Amplicon 200 Series ISA DIO boards");
27390f703d30dd3e0c16ff80f35e34e511385a05ad5Arun ThomasMODULE_LICENSE("GPL");
274