cb_pcidas.c revision 0a85b6f0ab0d2edb0d41b32697111ce0e4f43496
1/* 2 comedi/drivers/cb_pcidas.c 3 4 Developed by Ivan Martinez and Frank Mori Hess, with valuable help from 5 David Schleef and the rest of the Comedi developers comunity. 6 7 Copyright (C) 2001-2003 Ivan Martinez <imr@oersted.dtu.dk> 8 Copyright (C) 2001,2002 Frank Mori Hess <fmhess@users.sourceforge.net> 9 10 COMEDI - Linux Control and Measurement Device Interface 11 Copyright (C) 1997-8 David A. Schleef <ds@schleef.org> 12 13 This program is free software; you can redistribute it and/or modify 14 it under the terms of the GNU General Public License as published by 15 the Free Software Foundation; either version 2 of the License, or 16 (at your option) any later version. 17 18 This program is distributed in the hope that it will be useful, 19 but WITHOUT ANY WARRANTY; without even the implied warranty of 20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 GNU General Public License for more details. 22 23 You should have received a copy of the GNU General Public License 24 along with this program; if not, write to the Free Software 25 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 26 27************************************************************************ 28*/ 29/* 30Driver: cb_pcidas 31Description: MeasurementComputing PCI-DAS series with the AMCC S5933 PCI controller 32Author: Ivan Martinez <imr@oersted.dtu.dk>, 33 Frank Mori Hess <fmhess@users.sourceforge.net> 34Updated: 2003-3-11 35Devices: [Measurement Computing] PCI-DAS1602/16 (cb_pcidas), 36 PCI-DAS1602/16jr, PCI-DAS1602/12, PCI-DAS1200, PCI-DAS1200jr, 37 PCI-DAS1000, PCI-DAS1001, PCI_DAS1002 38 39Status: 40 There are many reports of the driver being used with most of the 41 supported cards. Despite no detailed log is maintained, it can 42 be said that the driver is quite tested and stable. 43 44 The boards may be autocalibrated using the comedi_calibrate 45 utility. 46 47Configuration options: 48 [0] - PCI bus of device (optional) 49 [1] - PCI slot of device (optional) 50 If bus/slot is not specified, the first supported 51 PCI device found will be used. 52 53For commands, the scanned channels must be consecutive 54(i.e. 4-5-6-7, 2-3-4,...), and must all have the same 55range and aref. 56*/ 57/* 58 59TODO: 60 61analog triggering on 1602 series 62*/ 63 64#include "../comedidev.h" 65#include <linux/delay.h> 66#include <linux/interrupt.h> 67 68#include "8253.h" 69#include "8255.h" 70#include "amcc_s5933.h" 71#include "comedi_pci.h" 72#include "comedi_fc.h" 73 74#undef CB_PCIDAS_DEBUG /* disable debugging code */ 75/* #define CB_PCIDAS_DEBUG enable debugging code */ 76 77/* PCI vendor number of ComputerBoards/MeasurementComputing */ 78#define PCI_VENDOR_ID_CB 0x1307 79#define TIMER_BASE 100 /* 10MHz master clock */ 80#define AI_BUFFER_SIZE 1024 /* maximum fifo size of any supported board */ 81#define AO_BUFFER_SIZE 1024 /* maximum fifo size of any supported board */ 82#define NUM_CHANNELS_8800 8 83#define NUM_CHANNELS_7376 1 84#define NUM_CHANNELS_8402 2 85#define NUM_CHANNELS_DAC08 1 86 87/* PCI-DAS base addresses */ 88 89/* indices of base address regions */ 90#define S5933_BADRINDEX 0 91#define CONT_STAT_BADRINDEX 1 92#define ADC_FIFO_BADRINDEX 2 93#define PACER_BADRINDEX 3 94#define AO_BADRINDEX 4 95/* sizes of io regions */ 96#define CONT_STAT_SIZE 10 97#define ADC_FIFO_SIZE 4 98#define PACER_SIZE 12 99#define AO_SIZE 4 100 101/* Control/Status registers */ 102#define INT_ADCFIFO 0 /* INTERRUPT / ADC FIFO register */ 103#define INT_EOS 0x1 /* interrupt end of scan */ 104#define INT_FHF 0x2 /* interrupt fifo half full */ 105#define INT_FNE 0x3 /* interrupt fifo not empty */ 106#define INT_MASK 0x3 /* mask of interrupt select bits */ 107#define INTE 0x4 /* interrupt enable */ 108#define DAHFIE 0x8 /* dac half full interrupt enable */ 109#define EOAIE 0x10 /* end of aquisition interrupt enable */ 110#define DAHFI 0x20 /* dac half full read status / write interrupt clear */ 111#define EOAI 0x40 /* read end of acq. interrupt status / write clear */ 112#define INT 0x80 /* read interrupt status / write clear */ 113#define EOBI 0x200 /* read end of burst interrupt status */ 114#define ADHFI 0x400 /* read half-full interrupt status */ 115#define ADNEI 0x800 /* read fifo not empty interrupt latch status */ 116#define ADNE 0x1000 /* read, fifo not empty (realtime, not latched) status */ 117#define DAEMIE 0x1000 /* write, dac empty interrupt enable */ 118#define LADFUL 0x2000 /* read fifo overflow / write clear */ 119#define DAEMI 0x4000 /* dac fifo empty interrupt status / write clear */ 120 121#define ADCMUX_CONT 2 /* ADC CHANNEL MUX AND CONTROL register */ 122#define BEGIN_SCAN(x) ((x) & 0xf) 123#define END_SCAN(x) (((x) & 0xf) << 4) 124#define GAIN_BITS(x) (((x) & 0x3) << 8) 125#define UNIP 0x800 /* Analog front-end unipolar for range */ 126#define SE 0x400 /* Inputs in single-ended mode */ 127#define PACER_MASK 0x3000 /* pacer source bits */ 128#define PACER_INT 0x1000 /* internal pacer */ 129#define PACER_EXT_FALL 0x2000 /* external falling edge */ 130#define PACER_EXT_RISE 0x3000 /* external rising edge */ 131#define EOC 0x4000 /* adc not busy */ 132 133#define TRIG_CONTSTAT 4 /* TRIGGER CONTROL/STATUS register */ 134#define SW_TRIGGER 0x1 /* software start trigger */ 135#define EXT_TRIGGER 0x2 /* external start trigger */ 136#define ANALOG_TRIGGER 0x3 /* external analog trigger */ 137#define TRIGGER_MASK 0x3 /* mask of bits that determine start trigger */ 138#define TGEN 0x10 /* enable external start trigger */ 139#define BURSTE 0x20 /* burst mode enable */ 140#define XTRCL 0x80 /* clear external trigger */ 141 142#define CALIBRATION_REG 6 /* CALIBRATION register */ 143#define SELECT_8800_BIT 0x100 /* select 8800 caldac */ 144#define SELECT_TRIMPOT_BIT 0x200 /* select ad7376 trim pot */ 145#define SELECT_DAC08_BIT 0x400 /* select dac08 caldac */ 146#define CAL_SRC_BITS(x) (((x) & 0x7) << 11) 147#define CAL_EN_BIT 0x4000 /* read calibration source instead of analog input channel 0 */ 148#define SERIAL_DATA_IN_BIT 0x8000 /* serial data stream going to 8800 and 7376 */ 149 150#define DAC_CSR 0x8 /* dac control and status register */ 151enum dac_csr_bits { 152 DACEN = 0x2, /* dac enable */ 153 DAC_MODE_UPDATE_BOTH = 0x80, /* update both dacs when dac0 is written */ 154}; 155static inline unsigned int DAC_RANGE(unsigned int channel, unsigned int range) 156{ 157 return (range & 0x3) << (8 + 2 * (channel & 0x1)); 158} 159 160static inline unsigned int DAC_RANGE_MASK(unsigned int channel) 161{ 162 return 0x3 << (8 + 2 * (channel & 0x1)); 163}; 164 165/* bits for 1602 series only */ 166enum dac_csr_bits_1602 { 167 DAC_EMPTY = 0x1, /* dac fifo empty, read, write clear */ 168 DAC_START = 0x4, /* start/arm dac fifo operations */ 169 DAC_PACER_MASK = 0x18, /* bits that set dac pacer source */ 170 DAC_PACER_INT = 0x8, /* dac internal pacing */ 171 DAC_PACER_EXT_FALL = 0x10, /* dac external pacing, falling edge */ 172 DAC_PACER_EXT_RISE = 0x18, /* dac external pacing, rising edge */ 173}; 174static inline unsigned int DAC_CHAN_EN(unsigned int channel) 175{ 176 return 1 << (5 + (channel & 0x1)); /* enable channel 0 or 1 */ 177}; 178 179/* analog input fifo */ 180#define ADCDATA 0 /* ADC DATA register */ 181#define ADCFIFOCLR 2 /* ADC FIFO CLEAR */ 182 183/* pacer, counter, dio registers */ 184#define ADC8254 0 185#define DIO_8255 4 186#define DAC8254 8 187 188/* analog output registers for 100x, 1200 series */ 189static inline unsigned int DAC_DATA_REG(unsigned int channel) 190{ 191 return 2 * (channel & 0x1); 192} 193 194/* analog output registers for 1602 series*/ 195#define DACDATA 0 /* DAC DATA register */ 196#define DACFIFOCLR 2 /* DAC FIFO CLEAR */ 197 198/* bit in hexadecimal representation of range index that indicates unipolar input range */ 199#define IS_UNIPOLAR 0x4 200/* analog input ranges for most boards */ 201static const struct comedi_lrange cb_pcidas_ranges = { 202 8, 203 { 204 BIP_RANGE(10), 205 BIP_RANGE(5), 206 BIP_RANGE(2.5), 207 BIP_RANGE(1.25), 208 UNI_RANGE(10), 209 UNI_RANGE(5), 210 UNI_RANGE(2.5), 211 UNI_RANGE(1.25) 212 } 213}; 214 215/* pci-das1001 input ranges */ 216static const struct comedi_lrange cb_pcidas_alt_ranges = { 217 8, 218 { 219 BIP_RANGE(10), 220 BIP_RANGE(1), 221 BIP_RANGE(0.1), 222 BIP_RANGE(0.01), 223 UNI_RANGE(10), 224 UNI_RANGE(1), 225 UNI_RANGE(0.1), 226 UNI_RANGE(0.01) 227 } 228}; 229 230/* analog output ranges */ 231static const struct comedi_lrange cb_pcidas_ao_ranges = { 232 4, 233 { 234 BIP_RANGE(5), 235 BIP_RANGE(10), 236 UNI_RANGE(5), 237 UNI_RANGE(10), 238 } 239}; 240 241enum trimpot_model { 242 AD7376, 243 AD8402, 244}; 245 246struct cb_pcidas_board { 247 const char *name; 248 unsigned short device_id; 249 int ai_se_chans; /* Inputs in single-ended mode */ 250 int ai_diff_chans; /* Inputs in differential mode */ 251 int ai_bits; /* analog input resolution */ 252 int ai_speed; /* fastest conversion period in ns */ 253 int ao_nchan; /* number of analog out channels */ 254 int has_ao_fifo; /* analog output has fifo */ 255 int ao_scan_speed; /* analog output speed for 1602 series (for a scan, not conversion) */ 256 int fifo_size; /* number of samples fifo can hold */ 257 const struct comedi_lrange *ranges; 258 enum trimpot_model trimpot; 259 unsigned has_dac08:1; 260}; 261 262static const struct cb_pcidas_board cb_pcidas_boards[] = { 263 { 264 .name = "pci-das1602/16", 265 .device_id = 0x1, 266 .ai_se_chans = 16, 267 .ai_diff_chans = 8, 268 .ai_bits = 16, 269 .ai_speed = 5000, 270 .ao_nchan = 2, 271 .has_ao_fifo = 1, 272 .ao_scan_speed = 10000, 273 .fifo_size = 512, 274 .ranges = &cb_pcidas_ranges, 275 .trimpot = AD8402, 276 .has_dac08 = 1, 277 }, 278 { 279 .name = "pci-das1200", 280 .device_id = 0xF, 281 .ai_se_chans = 16, 282 .ai_diff_chans = 8, 283 .ai_bits = 12, 284 .ai_speed = 3200, 285 .ao_nchan = 2, 286 .has_ao_fifo = 0, 287 .fifo_size = 1024, 288 .ranges = &cb_pcidas_ranges, 289 .trimpot = AD7376, 290 .has_dac08 = 0, 291 }, 292 { 293 .name = "pci-das1602/12", 294 .device_id = 0x10, 295 .ai_se_chans = 16, 296 .ai_diff_chans = 8, 297 .ai_bits = 12, 298 .ai_speed = 3200, 299 .ao_nchan = 2, 300 .has_ao_fifo = 1, 301 .ao_scan_speed = 4000, 302 .fifo_size = 1024, 303 .ranges = &cb_pcidas_ranges, 304 .trimpot = AD7376, 305 .has_dac08 = 0, 306 }, 307 { 308 .name = "pci-das1200/jr", 309 .device_id = 0x19, 310 .ai_se_chans = 16, 311 .ai_diff_chans = 8, 312 .ai_bits = 12, 313 .ai_speed = 3200, 314 .ao_nchan = 0, 315 .has_ao_fifo = 0, 316 .fifo_size = 1024, 317 .ranges = &cb_pcidas_ranges, 318 .trimpot = AD7376, 319 .has_dac08 = 0, 320 }, 321 { 322 .name = "pci-das1602/16/jr", 323 .device_id = 0x1C, 324 .ai_se_chans = 16, 325 .ai_diff_chans = 8, 326 .ai_bits = 16, 327 .ai_speed = 5000, 328 .ao_nchan = 0, 329 .has_ao_fifo = 0, 330 .fifo_size = 512, 331 .ranges = &cb_pcidas_ranges, 332 .trimpot = AD8402, 333 .has_dac08 = 1, 334 }, 335 { 336 .name = "pci-das1000", 337 .device_id = 0x4C, 338 .ai_se_chans = 16, 339 .ai_diff_chans = 8, 340 .ai_bits = 12, 341 .ai_speed = 4000, 342 .ao_nchan = 0, 343 .has_ao_fifo = 0, 344 .fifo_size = 1024, 345 .ranges = &cb_pcidas_ranges, 346 .trimpot = AD7376, 347 .has_dac08 = 0, 348 }, 349 { 350 .name = "pci-das1001", 351 .device_id = 0x1a, 352 .ai_se_chans = 16, 353 .ai_diff_chans = 8, 354 .ai_bits = 12, 355 .ai_speed = 6800, 356 .ao_nchan = 2, 357 .has_ao_fifo = 0, 358 .fifo_size = 1024, 359 .ranges = &cb_pcidas_alt_ranges, 360 .trimpot = AD7376, 361 .has_dac08 = 0, 362 }, 363 { 364 .name = "pci-das1002", 365 .device_id = 0x1b, 366 .ai_se_chans = 16, 367 .ai_diff_chans = 8, 368 .ai_bits = 12, 369 .ai_speed = 6800, 370 .ao_nchan = 2, 371 .has_ao_fifo = 0, 372 .fifo_size = 1024, 373 .ranges = &cb_pcidas_ranges, 374 .trimpot = AD7376, 375 .has_dac08 = 0, 376 }, 377}; 378 379static DEFINE_PCI_DEVICE_TABLE(cb_pcidas_pci_table) = { 380 { 381 PCI_VENDOR_ID_CB, 0x0001, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { 382 PCI_VENDOR_ID_CB, 0x000f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { 383 PCI_VENDOR_ID_CB, 0x0010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { 384 PCI_VENDOR_ID_CB, 0x0019, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { 385 PCI_VENDOR_ID_CB, 0x001c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { 386 PCI_VENDOR_ID_CB, 0x004c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { 387 PCI_VENDOR_ID_CB, 0x001a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { 388 PCI_VENDOR_ID_CB, 0x001b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { 389 0} 390}; 391 392MODULE_DEVICE_TABLE(pci, cb_pcidas_pci_table); 393 394/* 395 * Useful for shorthand access to the particular board structure 396 */ 397#define thisboard ((const struct cb_pcidas_board *)dev->board_ptr) 398 399/* this structure is for data unique to this hardware driver. If 400 several hardware drivers keep similar information in this structure, 401 feel free to suggest moving the variable to the struct comedi_device struct. */ 402struct cb_pcidas_private { 403 /* would be useful for a PCI device */ 404 struct pci_dev *pci_dev; 405 /* base addresses */ 406 unsigned long s5933_config; 407 unsigned long control_status; 408 unsigned long adc_fifo; 409 unsigned long pacer_counter_dio; 410 unsigned long ao_registers; 411 /* divisors of master clock for analog input pacing */ 412 unsigned int divisor1; 413 unsigned int divisor2; 414 volatile unsigned int count; /* number of analog input samples remaining */ 415 volatile unsigned int adc_fifo_bits; /* bits to write to interupt/adcfifo register */ 416 volatile unsigned int s5933_intcsr_bits; /* bits to write to amcc s5933 interrupt control/status register */ 417 volatile unsigned int ao_control_bits; /* bits to write to ao control and status register */ 418 short ai_buffer[AI_BUFFER_SIZE]; 419 short ao_buffer[AO_BUFFER_SIZE]; 420 /* divisors of master clock for analog output pacing */ 421 unsigned int ao_divisor1; 422 unsigned int ao_divisor2; 423 volatile unsigned int ao_count; /* number of analog output samples remaining */ 424 int ao_value[2]; /* remember what the analog outputs are set to, to allow readback */ 425 unsigned int caldac_value[NUM_CHANNELS_8800]; /* for readback of caldac */ 426 unsigned int trimpot_value[NUM_CHANNELS_8402]; /* for readback of trimpot */ 427 unsigned int dac08_value; 428 unsigned int calibration_source; 429}; 430 431/* 432 * most drivers define the following macro to make it easy to 433 * access the private structure. 434 */ 435#define devpriv ((struct cb_pcidas_private *)dev->private) 436 437/* 438 * The struct comedi_driver structure tells the Comedi core module 439 * which functions to call to configure/deconfigure (attach/detach) 440 * the board, and also about the kernel module that contains 441 * the device code. 442 */ 443static int cb_pcidas_attach(struct comedi_device *dev, 444 struct comedi_devconfig *it); 445static int cb_pcidas_detach(struct comedi_device *dev); 446static struct comedi_driver driver_cb_pcidas = { 447 .driver_name = "cb_pcidas", 448 .module = THIS_MODULE, 449 .attach = cb_pcidas_attach, 450 .detach = cb_pcidas_detach, 451}; 452 453static int cb_pcidas_ai_rinsn(struct comedi_device *dev, 454 struct comedi_subdevice *s, 455 struct comedi_insn *insn, unsigned int *data); 456static int ai_config_insn(struct comedi_device *dev, struct comedi_subdevice *s, 457 struct comedi_insn *insn, unsigned int *data); 458static int cb_pcidas_ao_nofifo_winsn(struct comedi_device *dev, 459 struct comedi_subdevice *s, 460 struct comedi_insn *insn, 461 unsigned int *data); 462static int cb_pcidas_ao_fifo_winsn(struct comedi_device *dev, 463 struct comedi_subdevice *s, 464 struct comedi_insn *insn, 465 unsigned int *data); 466static int cb_pcidas_ao_readback_insn(struct comedi_device *dev, 467 struct comedi_subdevice *s, 468 struct comedi_insn *insn, 469 unsigned int *data); 470static int cb_pcidas_ai_cmd(struct comedi_device *dev, 471 struct comedi_subdevice *s); 472static int cb_pcidas_ai_cmdtest(struct comedi_device *dev, 473 struct comedi_subdevice *s, 474 struct comedi_cmd *cmd); 475static int cb_pcidas_ao_cmd(struct comedi_device *dev, 476 struct comedi_subdevice *s); 477static int cb_pcidas_ao_inttrig(struct comedi_device *dev, 478 struct comedi_subdevice *subdev, 479 unsigned int trig_num); 480static int cb_pcidas_ao_cmdtest(struct comedi_device *dev, 481 struct comedi_subdevice *s, 482 struct comedi_cmd *cmd); 483static irqreturn_t cb_pcidas_interrupt(int irq, void *d); 484static void handle_ao_interrupt(struct comedi_device *dev, unsigned int status); 485static int cb_pcidas_cancel(struct comedi_device *dev, 486 struct comedi_subdevice *s); 487static int cb_pcidas_ao_cancel(struct comedi_device *dev, 488 struct comedi_subdevice *s); 489static void cb_pcidas_load_counters(struct comedi_device *dev, unsigned int *ns, 490 int round_flags); 491static int eeprom_read_insn(struct comedi_device *dev, 492 struct comedi_subdevice *s, 493 struct comedi_insn *insn, unsigned int *data); 494static int caldac_read_insn(struct comedi_device *dev, 495 struct comedi_subdevice *s, 496 struct comedi_insn *insn, unsigned int *data); 497static int caldac_write_insn(struct comedi_device *dev, 498 struct comedi_subdevice *s, 499 struct comedi_insn *insn, unsigned int *data); 500static int trimpot_read_insn(struct comedi_device *dev, 501 struct comedi_subdevice *s, 502 struct comedi_insn *insn, unsigned int *data); 503static int cb_pcidas_trimpot_write(struct comedi_device *dev, 504 unsigned int channel, unsigned int value); 505static int trimpot_write_insn(struct comedi_device *dev, 506 struct comedi_subdevice *s, 507 struct comedi_insn *insn, unsigned int *data); 508static int dac08_read_insn(struct comedi_device *dev, 509 struct comedi_subdevice *s, struct comedi_insn *insn, 510 unsigned int *data); 511static int dac08_write(struct comedi_device *dev, unsigned int value); 512static int dac08_write_insn(struct comedi_device *dev, 513 struct comedi_subdevice *s, 514 struct comedi_insn *insn, unsigned int *data); 515static int caldac_8800_write(struct comedi_device *dev, unsigned int address, 516 uint8_t value); 517static int trimpot_7376_write(struct comedi_device *dev, uint8_t value); 518static int trimpot_8402_write(struct comedi_device *dev, unsigned int channel, 519 uint8_t value); 520static int nvram_read(struct comedi_device *dev, unsigned int address, 521 uint8_t * data); 522 523static inline unsigned int cal_enable_bits(struct comedi_device *dev) 524{ 525 return CAL_EN_BIT | CAL_SRC_BITS(devpriv->calibration_source); 526} 527 528/* 529 * Attach is called by the Comedi core to configure the driver 530 * for a particular board. 531 */ 532static int cb_pcidas_attach(struct comedi_device *dev, 533 struct comedi_devconfig *it) 534{ 535 struct comedi_subdevice *s; 536 struct pci_dev *pcidev; 537 int index; 538 int i; 539 540 printk("comedi%d: cb_pcidas: ", dev->minor); 541 542/* 543 * Allocate the private structure area. 544 */ 545 if (alloc_private(dev, sizeof(struct cb_pcidas_private)) < 0) 546 return -ENOMEM; 547 548/* 549 * Probe the device to determine what device in the series it is. 550 */ 551 printk("\n"); 552 553 for (pcidev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, NULL); 554 pcidev != NULL; 555 pcidev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, pcidev)) { 556 /* is it not a computer boards card? */ 557 if (pcidev->vendor != PCI_VENDOR_ID_CB) 558 continue; 559 /* loop through cards supported by this driver */ 560 for (index = 0; index < ARRAY_SIZE(cb_pcidas_boards); index++) { 561 if (cb_pcidas_boards[index].device_id != pcidev->device) 562 continue; 563 /* was a particular bus/slot requested? */ 564 if (it->options[0] || it->options[1]) { 565 /* are we on the wrong bus/slot? */ 566 if (pcidev->bus->number != it->options[0] || 567 PCI_SLOT(pcidev->devfn) != it->options[1]) { 568 continue; 569 } 570 } 571 devpriv->pci_dev = pcidev; 572 dev->board_ptr = cb_pcidas_boards + index; 573 goto found; 574 } 575 } 576 577 printk("No supported ComputerBoards/MeasurementComputing card found on " 578 "requested position\n"); 579 return -EIO; 580 581found: 582 583 printk("Found %s on bus %i, slot %i\n", cb_pcidas_boards[index].name, 584 pcidev->bus->number, PCI_SLOT(pcidev->devfn)); 585 586 /* 587 * Enable PCI device and reserve I/O ports. 588 */ 589 if (comedi_pci_enable(pcidev, "cb_pcidas")) { 590 printk(" Failed to enable PCI device and request regions\n"); 591 return -EIO; 592 } 593 /* 594 * Initialize devpriv->control_status and devpriv->adc_fifo to point to 595 * their base address. 596 */ 597 devpriv->s5933_config = 598 pci_resource_start(devpriv->pci_dev, S5933_BADRINDEX); 599 devpriv->control_status = 600 pci_resource_start(devpriv->pci_dev, CONT_STAT_BADRINDEX); 601 devpriv->adc_fifo = 602 pci_resource_start(devpriv->pci_dev, ADC_FIFO_BADRINDEX); 603 devpriv->pacer_counter_dio = 604 pci_resource_start(devpriv->pci_dev, PACER_BADRINDEX); 605 if (thisboard->ao_nchan) { 606 devpriv->ao_registers = 607 pci_resource_start(devpriv->pci_dev, AO_BADRINDEX); 608 } 609 /* disable and clear interrupts on amcc s5933 */ 610 outl(INTCSR_INBOX_INTR_STATUS, 611 devpriv->s5933_config + AMCC_OP_REG_INTCSR); 612 613 /* get irq */ 614 if (request_irq(devpriv->pci_dev->irq, cb_pcidas_interrupt, 615 IRQF_SHARED, "cb_pcidas", dev)) { 616 printk(" unable to allocate irq %d\n", devpriv->pci_dev->irq); 617 return -EINVAL; 618 } 619 dev->irq = devpriv->pci_dev->irq; 620 621 /* Initialize dev->board_name */ 622 dev->board_name = thisboard->name; 623 624/* 625 * Allocate the subdevice structures. 626 */ 627 if (alloc_subdevices(dev, 7) < 0) 628 return -ENOMEM; 629 630 s = dev->subdevices + 0; 631 /* analog input subdevice */ 632 dev->read_subdev = s; 633 s->type = COMEDI_SUBD_AI; 634 s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_DIFF | SDF_CMD_READ; 635 /* WARNING: Number of inputs in differential mode is ignored */ 636 s->n_chan = thisboard->ai_se_chans; 637 s->len_chanlist = thisboard->ai_se_chans; 638 s->maxdata = (1 << thisboard->ai_bits) - 1; 639 s->range_table = thisboard->ranges; 640 s->insn_read = cb_pcidas_ai_rinsn; 641 s->insn_config = ai_config_insn; 642 s->do_cmd = cb_pcidas_ai_cmd; 643 s->do_cmdtest = cb_pcidas_ai_cmdtest; 644 s->cancel = cb_pcidas_cancel; 645 646 /* analog output subdevice */ 647 s = dev->subdevices + 1; 648 if (thisboard->ao_nchan) { 649 s->type = COMEDI_SUBD_AO; 650 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_GROUND; 651 s->n_chan = thisboard->ao_nchan; 652 /* analog out resolution is the same as analog input resolution, so use ai_bits */ 653 s->maxdata = (1 << thisboard->ai_bits) - 1; 654 s->range_table = &cb_pcidas_ao_ranges; 655 s->insn_read = cb_pcidas_ao_readback_insn; 656 if (thisboard->has_ao_fifo) { 657 dev->write_subdev = s; 658 s->subdev_flags |= SDF_CMD_WRITE; 659 s->insn_write = cb_pcidas_ao_fifo_winsn; 660 s->do_cmdtest = cb_pcidas_ao_cmdtest; 661 s->do_cmd = cb_pcidas_ao_cmd; 662 s->cancel = cb_pcidas_ao_cancel; 663 } else { 664 s->insn_write = cb_pcidas_ao_nofifo_winsn; 665 } 666 } else { 667 s->type = COMEDI_SUBD_UNUSED; 668 } 669 670 /* 8255 */ 671 s = dev->subdevices + 2; 672 subdev_8255_init(dev, s, NULL, devpriv->pacer_counter_dio + DIO_8255); 673 674 /* serial EEPROM, */ 675 s = dev->subdevices + 3; 676 s->type = COMEDI_SUBD_MEMORY; 677 s->subdev_flags = SDF_READABLE | SDF_INTERNAL; 678 s->n_chan = 256; 679 s->maxdata = 0xff; 680 s->insn_read = eeprom_read_insn; 681 682 /* 8800 caldac */ 683 s = dev->subdevices + 4; 684 s->type = COMEDI_SUBD_CALIB; 685 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; 686 s->n_chan = NUM_CHANNELS_8800; 687 s->maxdata = 0xff; 688 s->insn_read = caldac_read_insn; 689 s->insn_write = caldac_write_insn; 690 for (i = 0; i < s->n_chan; i++) 691 caldac_8800_write(dev, i, s->maxdata / 2); 692 693 /* trim potentiometer */ 694 s = dev->subdevices + 5; 695 s->type = COMEDI_SUBD_CALIB; 696 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; 697 if (thisboard->trimpot == AD7376) { 698 s->n_chan = NUM_CHANNELS_7376; 699 s->maxdata = 0x7f; 700 } else { 701 s->n_chan = NUM_CHANNELS_8402; 702 s->maxdata = 0xff; 703 } 704 s->insn_read = trimpot_read_insn; 705 s->insn_write = trimpot_write_insn; 706 for (i = 0; i < s->n_chan; i++) 707 cb_pcidas_trimpot_write(dev, i, s->maxdata / 2); 708 709 /* dac08 caldac */ 710 s = dev->subdevices + 6; 711 if (thisboard->has_dac08) { 712 s->type = COMEDI_SUBD_CALIB; 713 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; 714 s->n_chan = NUM_CHANNELS_DAC08; 715 s->insn_read = dac08_read_insn; 716 s->insn_write = dac08_write_insn; 717 s->maxdata = 0xff; 718 dac08_write(dev, s->maxdata / 2); 719 } else 720 s->type = COMEDI_SUBD_UNUSED; 721 722 /* make sure mailbox 4 is empty */ 723 inl(devpriv->s5933_config + AMCC_OP_REG_IMB4); 724 /* Set bits to enable incoming mailbox interrupts on amcc s5933. */ 725 devpriv->s5933_intcsr_bits = 726 INTCSR_INBOX_BYTE(3) | INTCSR_INBOX_SELECT(3) | 727 INTCSR_INBOX_FULL_INT; 728 /* clear and enable interrupt on amcc s5933 */ 729 outl(devpriv->s5933_intcsr_bits | INTCSR_INBOX_INTR_STATUS, 730 devpriv->s5933_config + AMCC_OP_REG_INTCSR); 731 732 return 1; 733} 734 735/* 736 * cb_pcidas_detach is called to deconfigure a device. It should deallocate 737 * resources. 738 * This function is also called when _attach() fails, so it should be 739 * careful not to release resources that were not necessarily 740 * allocated by _attach(). dev->private and dev->subdevices are 741 * deallocated automatically by the core. 742 */ 743static int cb_pcidas_detach(struct comedi_device *dev) 744{ 745 printk("comedi%d: cb_pcidas: remove\n", dev->minor); 746 747 if (devpriv) { 748 if (devpriv->s5933_config) { 749 /* disable and clear interrupts on amcc s5933 */ 750 outl(INTCSR_INBOX_INTR_STATUS, 751 devpriv->s5933_config + AMCC_OP_REG_INTCSR); 752#ifdef CB_PCIDAS_DEBUG 753 printk("detaching, incsr is 0x%x\n", 754 inl(devpriv->s5933_config + AMCC_OP_REG_INTCSR)); 755#endif 756 } 757 } 758 if (dev->irq) 759 free_irq(dev->irq, dev); 760 if (dev->subdevices) 761 subdev_8255_cleanup(dev, dev->subdevices + 2); 762 if (devpriv && devpriv->pci_dev) { 763 if (devpriv->s5933_config) { 764 comedi_pci_disable(devpriv->pci_dev); 765 } 766 pci_dev_put(devpriv->pci_dev); 767 } 768 769 return 0; 770} 771 772/* 773 * "instructions" read/write data in "one-shot" or "software-triggered" 774 * mode. 775 */ 776static int cb_pcidas_ai_rinsn(struct comedi_device *dev, 777 struct comedi_subdevice *s, 778 struct comedi_insn *insn, unsigned int *data) 779{ 780 int n, i; 781 unsigned int bits; 782 static const int timeout = 10000; 783 int channel; 784 /* enable calibration input if appropriate */ 785 if (insn->chanspec & CR_ALT_SOURCE) { 786 outw(cal_enable_bits(dev), 787 devpriv->control_status + CALIBRATION_REG); 788 channel = 0; 789 } else { 790 outw(0, devpriv->control_status + CALIBRATION_REG); 791 channel = CR_CHAN(insn->chanspec); 792 } 793 /* set mux limits and gain */ 794 bits = BEGIN_SCAN(channel) | 795 END_SCAN(channel) | GAIN_BITS(CR_RANGE(insn->chanspec)); 796 /* set unipolar/bipolar */ 797 if (CR_RANGE(insn->chanspec) & IS_UNIPOLAR) 798 bits |= UNIP; 799 /* set singleended/differential */ 800 if (CR_AREF(insn->chanspec) != AREF_DIFF) 801 bits |= SE; 802 outw(bits, devpriv->control_status + ADCMUX_CONT); 803 804 /* clear fifo */ 805 outw(0, devpriv->adc_fifo + ADCFIFOCLR); 806 807 /* convert n samples */ 808 for (n = 0; n < insn->n; n++) { 809 /* trigger conversion */ 810 outw(0, devpriv->adc_fifo + ADCDATA); 811 812 /* wait for conversion to end */ 813 /* return -ETIMEDOUT if there is a timeout */ 814 for (i = 0; i < timeout; i++) { 815 if (inw(devpriv->control_status + ADCMUX_CONT) & EOC) 816 break; 817 } 818 if (i == timeout) 819 return -ETIMEDOUT; 820 821 /* read data */ 822 data[n] = inw(devpriv->adc_fifo + ADCDATA); 823 } 824 825 /* return the number of samples read/written */ 826 return n; 827} 828 829static int ai_config_calibration_source(struct comedi_device *dev, 830 unsigned int *data) 831{ 832 static const int num_calibration_sources = 8; 833 unsigned int source = data[1]; 834 835 if (source >= num_calibration_sources) { 836 printk("invalid calibration source: %i\n", source); 837 return -EINVAL; 838 } 839 840 devpriv->calibration_source = source; 841 842 return 2; 843} 844 845static int ai_config_insn(struct comedi_device *dev, struct comedi_subdevice *s, 846 struct comedi_insn *insn, unsigned int *data) 847{ 848 int id = data[0]; 849 850 switch (id) { 851 case INSN_CONFIG_ALT_SOURCE: 852 return ai_config_calibration_source(dev, data); 853 break; 854 default: 855 return -EINVAL; 856 break; 857 } 858 return -EINVAL; 859} 860 861/* analog output insn for pcidas-1000 and 1200 series */ 862static int cb_pcidas_ao_nofifo_winsn(struct comedi_device *dev, 863 struct comedi_subdevice *s, 864 struct comedi_insn *insn, 865 unsigned int *data) 866{ 867 int channel; 868 unsigned long flags; 869 870 /* set channel and range */ 871 channel = CR_CHAN(insn->chanspec); 872 spin_lock_irqsave(&dev->spinlock, flags); 873 devpriv->ao_control_bits &= 874 ~DAC_MODE_UPDATE_BOTH & ~DAC_RANGE_MASK(channel); 875 devpriv->ao_control_bits |= 876 DACEN | DAC_RANGE(channel, CR_RANGE(insn->chanspec)); 877 outw(devpriv->ao_control_bits, devpriv->control_status + DAC_CSR); 878 spin_unlock_irqrestore(&dev->spinlock, flags); 879 880 /* remember value for readback */ 881 devpriv->ao_value[channel] = data[0]; 882 /* send data */ 883 outw(data[0], devpriv->ao_registers + DAC_DATA_REG(channel)); 884 885 return 1; 886} 887 888/* analog output insn for pcidas-1602 series */ 889static int cb_pcidas_ao_fifo_winsn(struct comedi_device *dev, 890 struct comedi_subdevice *s, 891 struct comedi_insn *insn, unsigned int *data) 892{ 893 int channel; 894 unsigned long flags; 895 896 /* clear dac fifo */ 897 outw(0, devpriv->ao_registers + DACFIFOCLR); 898 899 /* set channel and range */ 900 channel = CR_CHAN(insn->chanspec); 901 spin_lock_irqsave(&dev->spinlock, flags); 902 devpriv->ao_control_bits &= 903 ~DAC_CHAN_EN(0) & ~DAC_CHAN_EN(1) & ~DAC_RANGE_MASK(channel) & 904 ~DAC_PACER_MASK; 905 devpriv->ao_control_bits |= 906 DACEN | DAC_RANGE(channel, 907 CR_RANGE(insn-> 908 chanspec)) | DAC_CHAN_EN(channel) | 909 DAC_START; 910 outw(devpriv->ao_control_bits, devpriv->control_status + DAC_CSR); 911 spin_unlock_irqrestore(&dev->spinlock, flags); 912 913 /* remember value for readback */ 914 devpriv->ao_value[channel] = data[0]; 915 /* send data */ 916 outw(data[0], devpriv->ao_registers + DACDATA); 917 918 return 1; 919} 920 921/* analog output readback insn */ 922/* XXX loses track of analog output value back after an analog ouput command is executed */ 923static int cb_pcidas_ao_readback_insn(struct comedi_device *dev, 924 struct comedi_subdevice *s, 925 struct comedi_insn *insn, 926 unsigned int *data) 927{ 928 data[0] = devpriv->ao_value[CR_CHAN(insn->chanspec)]; 929 930 return 1; 931} 932 933static int eeprom_read_insn(struct comedi_device *dev, 934 struct comedi_subdevice *s, 935 struct comedi_insn *insn, unsigned int *data) 936{ 937 uint8_t nvram_data; 938 int retval; 939 940 retval = nvram_read(dev, CR_CHAN(insn->chanspec), &nvram_data); 941 if (retval < 0) 942 return retval; 943 944 data[0] = nvram_data; 945 946 return 1; 947} 948 949static int caldac_write_insn(struct comedi_device *dev, 950 struct comedi_subdevice *s, 951 struct comedi_insn *insn, unsigned int *data) 952{ 953 const unsigned int channel = CR_CHAN(insn->chanspec); 954 955 return caldac_8800_write(dev, channel, data[0]); 956} 957 958static int caldac_read_insn(struct comedi_device *dev, 959 struct comedi_subdevice *s, 960 struct comedi_insn *insn, unsigned int *data) 961{ 962 data[0] = devpriv->caldac_value[CR_CHAN(insn->chanspec)]; 963 964 return 1; 965} 966 967/* 1602/16 pregain offset */ 968static int dac08_write(struct comedi_device *dev, unsigned int value) 969{ 970 if (devpriv->dac08_value == value) 971 return 1; 972 973 devpriv->dac08_value = value; 974 975 outw(cal_enable_bits(dev) | (value & 0xff), 976 devpriv->control_status + CALIBRATION_REG); 977 udelay(1); 978 outw(cal_enable_bits(dev) | SELECT_DAC08_BIT | (value & 0xff), 979 devpriv->control_status + CALIBRATION_REG); 980 udelay(1); 981 outw(cal_enable_bits(dev) | (value & 0xff), 982 devpriv->control_status + CALIBRATION_REG); 983 udelay(1); 984 985 return 1; 986} 987 988static int dac08_write_insn(struct comedi_device *dev, 989 struct comedi_subdevice *s, 990 struct comedi_insn *insn, unsigned int *data) 991{ 992 return dac08_write(dev, data[0]); 993} 994 995static int dac08_read_insn(struct comedi_device *dev, 996 struct comedi_subdevice *s, struct comedi_insn *insn, 997 unsigned int *data) 998{ 999 data[0] = devpriv->dac08_value; 1000 1001 return 1; 1002} 1003 1004static int cb_pcidas_trimpot_write(struct comedi_device *dev, 1005 unsigned int channel, unsigned int value) 1006{ 1007 if (devpriv->trimpot_value[channel] == value) 1008 return 1; 1009 1010 devpriv->trimpot_value[channel] = value; 1011 switch (thisboard->trimpot) { 1012 case AD7376: 1013 trimpot_7376_write(dev, value); 1014 break; 1015 case AD8402: 1016 trimpot_8402_write(dev, channel, value); 1017 break; 1018 default: 1019 comedi_error(dev, "driver bug?"); 1020 return -1; 1021 break; 1022 } 1023 1024 return 1; 1025} 1026 1027static int trimpot_write_insn(struct comedi_device *dev, 1028 struct comedi_subdevice *s, 1029 struct comedi_insn *insn, unsigned int *data) 1030{ 1031 unsigned int channel = CR_CHAN(insn->chanspec); 1032 1033 return cb_pcidas_trimpot_write(dev, channel, data[0]); 1034} 1035 1036static int trimpot_read_insn(struct comedi_device *dev, 1037 struct comedi_subdevice *s, 1038 struct comedi_insn *insn, unsigned int *data) 1039{ 1040 unsigned int channel = CR_CHAN(insn->chanspec); 1041 1042 data[0] = devpriv->trimpot_value[channel]; 1043 1044 return 1; 1045} 1046 1047static int cb_pcidas_ai_cmdtest(struct comedi_device *dev, 1048 struct comedi_subdevice *s, 1049 struct comedi_cmd *cmd) 1050{ 1051 int err = 0; 1052 int tmp; 1053 int i, gain, start_chan; 1054 1055 /* cmdtest tests a particular command to see if it is valid. 1056 * Using the cmdtest ioctl, a user can create a valid cmd 1057 * and then have it executes by the cmd ioctl. 1058 * 1059 * cmdtest returns 1,2,3,4 or 0, depending on which tests 1060 * the command passes. */ 1061 1062 /* step 1: make sure trigger sources are trivially valid */ 1063 1064 tmp = cmd->start_src; 1065 cmd->start_src &= TRIG_NOW | TRIG_EXT; 1066 if (!cmd->start_src || tmp != cmd->start_src) 1067 err++; 1068 1069 tmp = cmd->scan_begin_src; 1070 cmd->scan_begin_src &= TRIG_FOLLOW | TRIG_TIMER | TRIG_EXT; 1071 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src) 1072 err++; 1073 1074 tmp = cmd->convert_src; 1075 cmd->convert_src &= TRIG_TIMER | TRIG_NOW | TRIG_EXT; 1076 if (!cmd->convert_src || tmp != cmd->convert_src) 1077 err++; 1078 1079 tmp = cmd->scan_end_src; 1080 cmd->scan_end_src &= TRIG_COUNT; 1081 if (!cmd->scan_end_src || tmp != cmd->scan_end_src) 1082 err++; 1083 1084 tmp = cmd->stop_src; 1085 cmd->stop_src &= TRIG_COUNT | TRIG_NONE; 1086 if (!cmd->stop_src || tmp != cmd->stop_src) 1087 err++; 1088 1089 if (err) 1090 return 1; 1091 1092 /* step 2: make sure trigger sources are unique and mutually compatible */ 1093 1094 if (cmd->start_src != TRIG_NOW && cmd->start_src != TRIG_EXT) 1095 err++; 1096 if (cmd->scan_begin_src != TRIG_FOLLOW && 1097 cmd->scan_begin_src != TRIG_TIMER && 1098 cmd->scan_begin_src != TRIG_EXT) 1099 err++; 1100 if (cmd->convert_src != TRIG_TIMER && 1101 cmd->convert_src != TRIG_EXT && cmd->convert_src != TRIG_NOW) 1102 err++; 1103 if (cmd->stop_src != TRIG_COUNT && cmd->stop_src != TRIG_NONE) 1104 err++; 1105 1106 /* make sure trigger sources are compatible with each other */ 1107 if (cmd->scan_begin_src == TRIG_FOLLOW && cmd->convert_src == TRIG_NOW) 1108 err++; 1109 if (cmd->scan_begin_src != TRIG_FOLLOW && cmd->convert_src != TRIG_NOW) 1110 err++; 1111 if (cmd->start_src == TRIG_EXT && 1112 (cmd->convert_src == TRIG_EXT || cmd->scan_begin_src == TRIG_EXT)) 1113 err++; 1114 1115 if (err) 1116 return 2; 1117 1118 /* step 3: make sure arguments are trivially compatible */ 1119 1120 if (cmd->start_arg != 0) { 1121 cmd->start_arg = 0; 1122 err++; 1123 } 1124 1125 if (cmd->scan_begin_src == TRIG_TIMER) { 1126 if (cmd->scan_begin_arg < 1127 thisboard->ai_speed * cmd->chanlist_len) { 1128 cmd->scan_begin_arg = 1129 thisboard->ai_speed * cmd->chanlist_len; 1130 err++; 1131 } 1132 } 1133 if (cmd->convert_src == TRIG_TIMER) { 1134 if (cmd->convert_arg < thisboard->ai_speed) { 1135 cmd->convert_arg = thisboard->ai_speed; 1136 err++; 1137 } 1138 } 1139 1140 if (cmd->scan_end_arg != cmd->chanlist_len) { 1141 cmd->scan_end_arg = cmd->chanlist_len; 1142 err++; 1143 } 1144 if (cmd->stop_src == TRIG_NONE) { 1145 /* TRIG_NONE */ 1146 if (cmd->stop_arg != 0) { 1147 cmd->stop_arg = 0; 1148 err++; 1149 } 1150 } 1151 1152 if (err) 1153 return 3; 1154 1155 /* step 4: fix up any arguments */ 1156 1157 if (cmd->scan_begin_src == TRIG_TIMER) { 1158 tmp = cmd->scan_begin_arg; 1159 i8253_cascade_ns_to_timer_2div(TIMER_BASE, 1160 &(devpriv->divisor1), 1161 &(devpriv->divisor2), 1162 &(cmd->scan_begin_arg), 1163 cmd->flags & TRIG_ROUND_MASK); 1164 if (tmp != cmd->scan_begin_arg) 1165 err++; 1166 } 1167 if (cmd->convert_src == TRIG_TIMER) { 1168 tmp = cmd->convert_arg; 1169 i8253_cascade_ns_to_timer_2div(TIMER_BASE, 1170 &(devpriv->divisor1), 1171 &(devpriv->divisor2), 1172 &(cmd->convert_arg), 1173 cmd->flags & TRIG_ROUND_MASK); 1174 if (tmp != cmd->convert_arg) 1175 err++; 1176 } 1177 1178 if (err) 1179 return 4; 1180 1181 /* check channel/gain list against card's limitations */ 1182 if (cmd->chanlist) { 1183 gain = CR_RANGE(cmd->chanlist[0]); 1184 start_chan = CR_CHAN(cmd->chanlist[0]); 1185 for (i = 1; i < cmd->chanlist_len; i++) { 1186 if (CR_CHAN(cmd->chanlist[i]) != 1187 (start_chan + i) % s->n_chan) { 1188 comedi_error(dev, 1189 "entries in chanlist must be consecutive channels, counting upwards\n"); 1190 err++; 1191 } 1192 if (CR_RANGE(cmd->chanlist[i]) != gain) { 1193 comedi_error(dev, 1194 "entries in chanlist must all have the same gain\n"); 1195 err++; 1196 } 1197 } 1198 } 1199 1200 if (err) 1201 return 5; 1202 1203 return 0; 1204} 1205 1206static int cb_pcidas_ai_cmd(struct comedi_device *dev, 1207 struct comedi_subdevice *s) 1208{ 1209 struct comedi_async *async = s->async; 1210 struct comedi_cmd *cmd = &async->cmd; 1211 unsigned int bits; 1212 unsigned long flags; 1213 1214 /* make sure CAL_EN_BIT is disabled */ 1215 outw(0, devpriv->control_status + CALIBRATION_REG); 1216 /* initialize before settings pacer source and count values */ 1217 outw(0, devpriv->control_status + TRIG_CONTSTAT); 1218 /* clear fifo */ 1219 outw(0, devpriv->adc_fifo + ADCFIFOCLR); 1220 1221 /* set mux limits, gain and pacer source */ 1222 bits = BEGIN_SCAN(CR_CHAN(cmd->chanlist[0])) | 1223 END_SCAN(CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1])) | 1224 GAIN_BITS(CR_RANGE(cmd->chanlist[0])); 1225 /* set unipolar/bipolar */ 1226 if (CR_RANGE(cmd->chanlist[0]) & IS_UNIPOLAR) 1227 bits |= UNIP; 1228 /* set singleended/differential */ 1229 if (CR_AREF(cmd->chanlist[0]) != AREF_DIFF) 1230 bits |= SE; 1231 /* set pacer source */ 1232 if (cmd->convert_src == TRIG_EXT || cmd->scan_begin_src == TRIG_EXT) 1233 bits |= PACER_EXT_RISE; 1234 else 1235 bits |= PACER_INT; 1236 outw(bits, devpriv->control_status + ADCMUX_CONT); 1237 1238#ifdef CB_PCIDAS_DEBUG 1239 printk("comedi: sent 0x%x to adcmux control\n", bits); 1240#endif 1241 1242 /* load counters */ 1243 if (cmd->convert_src == TRIG_TIMER) 1244 cb_pcidas_load_counters(dev, &cmd->convert_arg, 1245 cmd->flags & TRIG_ROUND_MASK); 1246 else if (cmd->scan_begin_src == TRIG_TIMER) 1247 cb_pcidas_load_counters(dev, &cmd->scan_begin_arg, 1248 cmd->flags & TRIG_ROUND_MASK); 1249 1250 /* set number of conversions */ 1251 if (cmd->stop_src == TRIG_COUNT) { 1252 devpriv->count = cmd->chanlist_len * cmd->stop_arg; 1253 } 1254 /* enable interrupts */ 1255 spin_lock_irqsave(&dev->spinlock, flags); 1256 devpriv->adc_fifo_bits |= INTE; 1257 devpriv->adc_fifo_bits &= ~INT_MASK; 1258 if (cmd->flags & TRIG_WAKE_EOS) { 1259 if (cmd->convert_src == TRIG_NOW && cmd->chanlist_len > 1) 1260 devpriv->adc_fifo_bits |= INT_EOS; /* interrupt end of burst */ 1261 else 1262 devpriv->adc_fifo_bits |= INT_FNE; /* interrupt fifo not empty */ 1263 } else { 1264 devpriv->adc_fifo_bits |= INT_FHF; /* interrupt fifo half full */ 1265 } 1266#ifdef CB_PCIDAS_DEBUG 1267 printk("comedi: adc_fifo_bits are 0x%x\n", devpriv->adc_fifo_bits); 1268#endif 1269 /* enable (and clear) interrupts */ 1270 outw(devpriv->adc_fifo_bits | EOAI | INT | LADFUL, 1271 devpriv->control_status + INT_ADCFIFO); 1272 spin_unlock_irqrestore(&dev->spinlock, flags); 1273 1274 /* set start trigger and burst mode */ 1275 bits = 0; 1276 if (cmd->start_src == TRIG_NOW) 1277 bits |= SW_TRIGGER; 1278 else if (cmd->start_src == TRIG_EXT) 1279 bits |= EXT_TRIGGER | TGEN | XTRCL; 1280 else { 1281 comedi_error(dev, "bug!"); 1282 return -1; 1283 } 1284 if (cmd->convert_src == TRIG_NOW && cmd->chanlist_len > 1) 1285 bits |= BURSTE; 1286 outw(bits, devpriv->control_status + TRIG_CONTSTAT); 1287#ifdef CB_PCIDAS_DEBUG 1288 printk("comedi: sent 0x%x to trig control\n", bits); 1289#endif 1290 1291 return 0; 1292} 1293 1294static int cb_pcidas_ao_cmdtest(struct comedi_device *dev, 1295 struct comedi_subdevice *s, 1296 struct comedi_cmd *cmd) 1297{ 1298 int err = 0; 1299 int tmp; 1300 1301 /* cmdtest tests a particular command to see if it is valid. 1302 * Using the cmdtest ioctl, a user can create a valid cmd 1303 * and then have it executes by the cmd ioctl. 1304 * 1305 * cmdtest returns 1,2,3,4 or 0, depending on which tests 1306 * the command passes. */ 1307 1308 /* step 1: make sure trigger sources are trivially valid */ 1309 1310 tmp = cmd->start_src; 1311 cmd->start_src &= TRIG_INT; 1312 if (!cmd->start_src || tmp != cmd->start_src) 1313 err++; 1314 1315 tmp = cmd->scan_begin_src; 1316 cmd->scan_begin_src &= TRIG_TIMER | TRIG_EXT; 1317 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src) 1318 err++; 1319 1320 tmp = cmd->convert_src; 1321 cmd->convert_src &= TRIG_NOW; 1322 if (!cmd->convert_src || tmp != cmd->convert_src) 1323 err++; 1324 1325 tmp = cmd->scan_end_src; 1326 cmd->scan_end_src &= TRIG_COUNT; 1327 if (!cmd->scan_end_src || tmp != cmd->scan_end_src) 1328 err++; 1329 1330 tmp = cmd->stop_src; 1331 cmd->stop_src &= TRIG_COUNT | TRIG_NONE; 1332 if (!cmd->stop_src || tmp != cmd->stop_src) 1333 err++; 1334 1335 if (err) 1336 return 1; 1337 1338 /* step 2: make sure trigger sources are unique and mutually compatible */ 1339 1340 if (cmd->scan_begin_src != TRIG_TIMER && 1341 cmd->scan_begin_src != TRIG_EXT) 1342 err++; 1343 if (cmd->stop_src != TRIG_COUNT && cmd->stop_src != TRIG_NONE) 1344 err++; 1345 1346 if (err) 1347 return 2; 1348 1349 /* step 3: make sure arguments are trivially compatible */ 1350 1351 if (cmd->start_arg != 0) { 1352 cmd->start_arg = 0; 1353 err++; 1354 } 1355 1356 if (cmd->scan_begin_src == TRIG_TIMER) { 1357 if (cmd->scan_begin_arg < thisboard->ao_scan_speed) { 1358 cmd->scan_begin_arg = thisboard->ao_scan_speed; 1359 err++; 1360 } 1361 } 1362 1363 if (cmd->scan_end_arg != cmd->chanlist_len) { 1364 cmd->scan_end_arg = cmd->chanlist_len; 1365 err++; 1366 } 1367 if (cmd->stop_src == TRIG_NONE) { 1368 /* TRIG_NONE */ 1369 if (cmd->stop_arg != 0) { 1370 cmd->stop_arg = 0; 1371 err++; 1372 } 1373 } 1374 1375 if (err) 1376 return 3; 1377 1378 /* step 4: fix up any arguments */ 1379 1380 if (cmd->scan_begin_src == TRIG_TIMER) { 1381 tmp = cmd->scan_begin_arg; 1382 i8253_cascade_ns_to_timer_2div(TIMER_BASE, 1383 &(devpriv->ao_divisor1), 1384 &(devpriv->ao_divisor2), 1385 &(cmd->scan_begin_arg), 1386 cmd->flags & TRIG_ROUND_MASK); 1387 if (tmp != cmd->scan_begin_arg) 1388 err++; 1389 } 1390 1391 if (err) 1392 return 4; 1393 1394 /* check channel/gain list against card's limitations */ 1395 if (cmd->chanlist && cmd->chanlist_len > 1) { 1396 if (CR_CHAN(cmd->chanlist[0]) != 0 || 1397 CR_CHAN(cmd->chanlist[1]) != 1) { 1398 comedi_error(dev, 1399 "channels must be ordered channel 0, channel 1 in chanlist\n"); 1400 err++; 1401 } 1402 } 1403 1404 if (err) 1405 return 5; 1406 1407 return 0; 1408} 1409 1410static int cb_pcidas_ao_cmd(struct comedi_device *dev, 1411 struct comedi_subdevice *s) 1412{ 1413 struct comedi_async *async = s->async; 1414 struct comedi_cmd *cmd = &async->cmd; 1415 unsigned int i; 1416 unsigned long flags; 1417 1418 /* set channel limits, gain */ 1419 spin_lock_irqsave(&dev->spinlock, flags); 1420 for (i = 0; i < cmd->chanlist_len; i++) { 1421 /* enable channel */ 1422 devpriv->ao_control_bits |= 1423 DAC_CHAN_EN(CR_CHAN(cmd->chanlist[i])); 1424 /* set range */ 1425 devpriv->ao_control_bits |= DAC_RANGE(CR_CHAN(cmd->chanlist[i]), 1426 CR_RANGE(cmd-> 1427 chanlist[i])); 1428 } 1429 1430 /* disable analog out before settings pacer source and count values */ 1431 outw(devpriv->ao_control_bits, devpriv->control_status + DAC_CSR); 1432 spin_unlock_irqrestore(&dev->spinlock, flags); 1433 1434 /* clear fifo */ 1435 outw(0, devpriv->ao_registers + DACFIFOCLR); 1436 1437 /* load counters */ 1438 if (cmd->scan_begin_src == TRIG_TIMER) { 1439 i8253_cascade_ns_to_timer_2div(TIMER_BASE, 1440 &(devpriv->ao_divisor1), 1441 &(devpriv->ao_divisor2), 1442 &(cmd->scan_begin_arg), 1443 cmd->flags); 1444 1445 /* Write the values of ctr1 and ctr2 into counters 1 and 2 */ 1446 i8254_load(devpriv->pacer_counter_dio + DAC8254, 0, 1, 1447 devpriv->ao_divisor1, 2); 1448 i8254_load(devpriv->pacer_counter_dio + DAC8254, 0, 2, 1449 devpriv->ao_divisor2, 2); 1450 } 1451 /* set number of conversions */ 1452 if (cmd->stop_src == TRIG_COUNT) { 1453 devpriv->ao_count = cmd->chanlist_len * cmd->stop_arg; 1454 } 1455 /* set pacer source */ 1456 spin_lock_irqsave(&dev->spinlock, flags); 1457 switch (cmd->scan_begin_src) { 1458 case TRIG_TIMER: 1459 devpriv->ao_control_bits |= DAC_PACER_INT; 1460 break; 1461 case TRIG_EXT: 1462 devpriv->ao_control_bits |= DAC_PACER_EXT_RISE; 1463 break; 1464 default: 1465 spin_unlock_irqrestore(&dev->spinlock, flags); 1466 comedi_error(dev, "error setting dac pacer source"); 1467 return -1; 1468 break; 1469 } 1470 spin_unlock_irqrestore(&dev->spinlock, flags); 1471 1472 async->inttrig = cb_pcidas_ao_inttrig; 1473 1474 return 0; 1475} 1476 1477static int cb_pcidas_ao_inttrig(struct comedi_device *dev, 1478 struct comedi_subdevice *s, 1479 unsigned int trig_num) 1480{ 1481 unsigned int num_bytes, num_points = thisboard->fifo_size; 1482 struct comedi_async *async = s->async; 1483 struct comedi_cmd *cmd = &s->async->cmd; 1484 unsigned long flags; 1485 1486 if (trig_num != 0) 1487 return -EINVAL; 1488 1489 /* load up fifo */ 1490 if (cmd->stop_src == TRIG_COUNT && devpriv->ao_count < num_points) 1491 num_points = devpriv->ao_count; 1492 1493 num_bytes = cfc_read_array_from_buffer(s, devpriv->ao_buffer, 1494 num_points * sizeof(short)); 1495 num_points = num_bytes / sizeof(short); 1496 1497 if (cmd->stop_src == TRIG_COUNT) { 1498 devpriv->ao_count -= num_points; 1499 } 1500 /* write data to board's fifo */ 1501 outsw(devpriv->ao_registers + DACDATA, devpriv->ao_buffer, num_bytes); 1502 1503 /* enable dac half-full and empty interrupts */ 1504 spin_lock_irqsave(&dev->spinlock, flags); 1505 devpriv->adc_fifo_bits |= DAEMIE | DAHFIE; 1506#ifdef CB_PCIDAS_DEBUG 1507 printk("comedi: adc_fifo_bits are 0x%x\n", devpriv->adc_fifo_bits); 1508#endif 1509 /* enable and clear interrupts */ 1510 outw(devpriv->adc_fifo_bits | DAEMI | DAHFI, 1511 devpriv->control_status + INT_ADCFIFO); 1512 1513 /* start dac */ 1514 devpriv->ao_control_bits |= DAC_START | DACEN | DAC_EMPTY; 1515 outw(devpriv->ao_control_bits, devpriv->control_status + DAC_CSR); 1516#ifdef CB_PCIDAS_DEBUG 1517 printk("comedi: sent 0x%x to dac control\n", devpriv->ao_control_bits); 1518#endif 1519 spin_unlock_irqrestore(&dev->spinlock, flags); 1520 1521 async->inttrig = NULL; 1522 1523 return 0; 1524} 1525 1526static irqreturn_t cb_pcidas_interrupt(int irq, void *d) 1527{ 1528 struct comedi_device *dev = (struct comedi_device *)d; 1529 struct comedi_subdevice *s = dev->read_subdev; 1530 struct comedi_async *async; 1531 int status, s5933_status; 1532 int half_fifo = thisboard->fifo_size / 2; 1533 unsigned int num_samples, i; 1534 static const int timeout = 10000; 1535 unsigned long flags; 1536 1537 if (dev->attached == 0) { 1538 return IRQ_NONE; 1539 } 1540 1541 async = s->async; 1542 async->events = 0; 1543 1544 s5933_status = inl(devpriv->s5933_config + AMCC_OP_REG_INTCSR); 1545#ifdef CB_PCIDAS_DEBUG 1546 printk("intcsr 0x%x\n", s5933_status); 1547 printk("mbef 0x%x\n", inl(devpriv->s5933_config + AMCC_OP_REG_MBEF)); 1548#endif 1549 1550 if ((INTCSR_INTR_ASSERTED & s5933_status) == 0) 1551 return IRQ_NONE; 1552 1553 /* make sure mailbox 4 is empty */ 1554 inl_p(devpriv->s5933_config + AMCC_OP_REG_IMB4); 1555 /* clear interrupt on amcc s5933 */ 1556 outl(devpriv->s5933_intcsr_bits | INTCSR_INBOX_INTR_STATUS, 1557 devpriv->s5933_config + AMCC_OP_REG_INTCSR); 1558 1559 status = inw(devpriv->control_status + INT_ADCFIFO); 1560#ifdef CB_PCIDAS_DEBUG 1561 if ((status & (INT | EOAI | LADFUL | DAHFI | DAEMI)) == 0) { 1562 comedi_error(dev, "spurious interrupt"); 1563 } 1564#endif 1565 1566 /* check for analog output interrupt */ 1567 if (status & (DAHFI | DAEMI)) { 1568 handle_ao_interrupt(dev, status); 1569 } 1570 /* check for analog input interrupts */ 1571 /* if fifo half-full */ 1572 if (status & ADHFI) { 1573 /* read data */ 1574 num_samples = half_fifo; 1575 if (async->cmd.stop_src == TRIG_COUNT && 1576 num_samples > devpriv->count) { 1577 num_samples = devpriv->count; 1578 } 1579 insw(devpriv->adc_fifo + ADCDATA, devpriv->ai_buffer, 1580 num_samples); 1581 cfc_write_array_to_buffer(s, devpriv->ai_buffer, 1582 num_samples * sizeof(short)); 1583 devpriv->count -= num_samples; 1584 if (async->cmd.stop_src == TRIG_COUNT && devpriv->count == 0) { 1585 async->events |= COMEDI_CB_EOA; 1586 cb_pcidas_cancel(dev, s); 1587 } 1588 /* clear half-full interrupt latch */ 1589 spin_lock_irqsave(&dev->spinlock, flags); 1590 outw(devpriv->adc_fifo_bits | INT, 1591 devpriv->control_status + INT_ADCFIFO); 1592 spin_unlock_irqrestore(&dev->spinlock, flags); 1593 /* else if fifo not empty */ 1594 } else if (status & (ADNEI | EOBI)) { 1595 for (i = 0; i < timeout; i++) { 1596 /* break if fifo is empty */ 1597 if ((ADNE & inw(devpriv->control_status + 1598 INT_ADCFIFO)) == 0) 1599 break; 1600 cfc_write_to_buffer(s, inw(devpriv->adc_fifo)); 1601 if (async->cmd.stop_src == TRIG_COUNT && --devpriv->count == 0) { /* end of acquisition */ 1602 cb_pcidas_cancel(dev, s); 1603 async->events |= COMEDI_CB_EOA; 1604 break; 1605 } 1606 } 1607 /* clear not-empty interrupt latch */ 1608 spin_lock_irqsave(&dev->spinlock, flags); 1609 outw(devpriv->adc_fifo_bits | INT, 1610 devpriv->control_status + INT_ADCFIFO); 1611 spin_unlock_irqrestore(&dev->spinlock, flags); 1612 } else if (status & EOAI) { 1613 comedi_error(dev, 1614 "bug! encountered end of aquisition interrupt?"); 1615 /* clear EOA interrupt latch */ 1616 spin_lock_irqsave(&dev->spinlock, flags); 1617 outw(devpriv->adc_fifo_bits | EOAI, 1618 devpriv->control_status + INT_ADCFIFO); 1619 spin_unlock_irqrestore(&dev->spinlock, flags); 1620 } 1621 /* check for fifo overflow */ 1622 if (status & LADFUL) { 1623 comedi_error(dev, "fifo overflow"); 1624 /* clear overflow interrupt latch */ 1625 spin_lock_irqsave(&dev->spinlock, flags); 1626 outw(devpriv->adc_fifo_bits | LADFUL, 1627 devpriv->control_status + INT_ADCFIFO); 1628 spin_unlock_irqrestore(&dev->spinlock, flags); 1629 cb_pcidas_cancel(dev, s); 1630 async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR; 1631 } 1632 1633 comedi_event(dev, s); 1634 1635 return IRQ_HANDLED; 1636} 1637 1638static void handle_ao_interrupt(struct comedi_device *dev, unsigned int status) 1639{ 1640 struct comedi_subdevice *s = dev->write_subdev; 1641 struct comedi_async *async = s->async; 1642 struct comedi_cmd *cmd = &async->cmd; 1643 unsigned int half_fifo = thisboard->fifo_size / 2; 1644 unsigned int num_points; 1645 unsigned long flags; 1646 1647 async->events = 0; 1648 1649 if (status & DAEMI) { 1650 /* clear dac empty interrupt latch */ 1651 spin_lock_irqsave(&dev->spinlock, flags); 1652 outw(devpriv->adc_fifo_bits | DAEMI, 1653 devpriv->control_status + INT_ADCFIFO); 1654 spin_unlock_irqrestore(&dev->spinlock, flags); 1655 if (inw(devpriv->ao_registers + DAC_CSR) & DAC_EMPTY) { 1656 if (cmd->stop_src == TRIG_NONE || 1657 (cmd->stop_src == TRIG_COUNT 1658 && devpriv->ao_count)) { 1659 comedi_error(dev, "dac fifo underflow"); 1660 cb_pcidas_ao_cancel(dev, s); 1661 async->events |= COMEDI_CB_ERROR; 1662 } 1663 async->events |= COMEDI_CB_EOA; 1664 } 1665 } else if (status & DAHFI) { 1666 unsigned int num_bytes; 1667 1668 /* figure out how many points we are writing to fifo */ 1669 num_points = half_fifo; 1670 if (cmd->stop_src == TRIG_COUNT && 1671 devpriv->ao_count < num_points) 1672 num_points = devpriv->ao_count; 1673 num_bytes = 1674 cfc_read_array_from_buffer(s, devpriv->ao_buffer, 1675 num_points * sizeof(short)); 1676 num_points = num_bytes / sizeof(short); 1677 1678 if (async->cmd.stop_src == TRIG_COUNT) { 1679 devpriv->ao_count -= num_points; 1680 } 1681 /* write data to board's fifo */ 1682 outsw(devpriv->ao_registers + DACDATA, devpriv->ao_buffer, 1683 num_points); 1684 /* clear half-full interrupt latch */ 1685 spin_lock_irqsave(&dev->spinlock, flags); 1686 outw(devpriv->adc_fifo_bits | DAHFI, 1687 devpriv->control_status + INT_ADCFIFO); 1688 spin_unlock_irqrestore(&dev->spinlock, flags); 1689 } 1690 1691 comedi_event(dev, s); 1692} 1693 1694/* cancel analog input command */ 1695static int cb_pcidas_cancel(struct comedi_device *dev, 1696 struct comedi_subdevice *s) 1697{ 1698 unsigned long flags; 1699 1700 spin_lock_irqsave(&dev->spinlock, flags); 1701 /* disable interrupts */ 1702 devpriv->adc_fifo_bits &= ~INTE & ~EOAIE; 1703 outw(devpriv->adc_fifo_bits, devpriv->control_status + INT_ADCFIFO); 1704 spin_unlock_irqrestore(&dev->spinlock, flags); 1705 1706 /* disable start trigger source and burst mode */ 1707 outw(0, devpriv->control_status + TRIG_CONTSTAT); 1708 /* software pacer source */ 1709 outw(0, devpriv->control_status + ADCMUX_CONT); 1710 1711 return 0; 1712} 1713 1714/* cancel analog output command */ 1715static int cb_pcidas_ao_cancel(struct comedi_device *dev, 1716 struct comedi_subdevice *s) 1717{ 1718 unsigned long flags; 1719 1720 spin_lock_irqsave(&dev->spinlock, flags); 1721 /* disable interrupts */ 1722 devpriv->adc_fifo_bits &= ~DAHFIE & ~DAEMIE; 1723 outw(devpriv->adc_fifo_bits, devpriv->control_status + INT_ADCFIFO); 1724 1725 /* disable output */ 1726 devpriv->ao_control_bits &= ~DACEN & ~DAC_PACER_MASK; 1727 outw(devpriv->ao_control_bits, devpriv->control_status + DAC_CSR); 1728 spin_unlock_irqrestore(&dev->spinlock, flags); 1729 1730 return 0; 1731} 1732 1733static void cb_pcidas_load_counters(struct comedi_device *dev, unsigned int *ns, 1734 int rounding_flags) 1735{ 1736 i8253_cascade_ns_to_timer_2div(TIMER_BASE, &(devpriv->divisor1), 1737 &(devpriv->divisor2), ns, 1738 rounding_flags & TRIG_ROUND_MASK); 1739 1740 /* Write the values of ctr1 and ctr2 into counters 1 and 2 */ 1741 i8254_load(devpriv->pacer_counter_dio + ADC8254, 0, 1, 1742 devpriv->divisor1, 2); 1743 i8254_load(devpriv->pacer_counter_dio + ADC8254, 0, 2, 1744 devpriv->divisor2, 2); 1745} 1746 1747static void write_calibration_bitstream(struct comedi_device *dev, 1748 unsigned int register_bits, 1749 unsigned int bitstream, 1750 unsigned int bitstream_length) 1751{ 1752 static const int write_delay = 1; 1753 unsigned int bit; 1754 1755 for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) { 1756 if (bitstream & bit) 1757 register_bits |= SERIAL_DATA_IN_BIT; 1758 else 1759 register_bits &= ~SERIAL_DATA_IN_BIT; 1760 udelay(write_delay); 1761 outw(register_bits, devpriv->control_status + CALIBRATION_REG); 1762 } 1763} 1764 1765static int caldac_8800_write(struct comedi_device *dev, unsigned int address, 1766 uint8_t value) 1767{ 1768 static const int num_caldac_channels = 8; 1769 static const int bitstream_length = 11; 1770 unsigned int bitstream = ((address & 0x7) << 8) | value; 1771 static const int caldac_8800_udelay = 1; 1772 1773 if (address >= num_caldac_channels) { 1774 comedi_error(dev, "illegal caldac channel"); 1775 return -1; 1776 } 1777 1778 if (value == devpriv->caldac_value[address]) 1779 return 1; 1780 1781 devpriv->caldac_value[address] = value; 1782 1783 write_calibration_bitstream(dev, cal_enable_bits(dev), bitstream, 1784 bitstream_length); 1785 1786 udelay(caldac_8800_udelay); 1787 outw(cal_enable_bits(dev) | SELECT_8800_BIT, 1788 devpriv->control_status + CALIBRATION_REG); 1789 udelay(caldac_8800_udelay); 1790 outw(cal_enable_bits(dev), devpriv->control_status + CALIBRATION_REG); 1791 1792 return 1; 1793} 1794 1795static int trimpot_7376_write(struct comedi_device *dev, uint8_t value) 1796{ 1797 static const int bitstream_length = 7; 1798 unsigned int bitstream = value & 0x7f; 1799 unsigned int register_bits; 1800 static const int ad7376_udelay = 1; 1801 1802 register_bits = cal_enable_bits(dev) | SELECT_TRIMPOT_BIT; 1803 udelay(ad7376_udelay); 1804 outw(register_bits, devpriv->control_status + CALIBRATION_REG); 1805 1806 write_calibration_bitstream(dev, register_bits, bitstream, 1807 bitstream_length); 1808 1809 udelay(ad7376_udelay); 1810 outw(cal_enable_bits(dev), devpriv->control_status + CALIBRATION_REG); 1811 1812 return 0; 1813} 1814 1815/* For 1602/16 only 1816 * ch 0 : adc gain 1817 * ch 1 : adc postgain offset */ 1818static int trimpot_8402_write(struct comedi_device *dev, unsigned int channel, 1819 uint8_t value) 1820{ 1821 static const int bitstream_length = 10; 1822 unsigned int bitstream = ((channel & 0x3) << 8) | (value & 0xff); 1823 unsigned int register_bits; 1824 static const int ad8402_udelay = 1; 1825 1826 register_bits = cal_enable_bits(dev) | SELECT_TRIMPOT_BIT; 1827 udelay(ad8402_udelay); 1828 outw(register_bits, devpriv->control_status + CALIBRATION_REG); 1829 1830 write_calibration_bitstream(dev, register_bits, bitstream, 1831 bitstream_length); 1832 1833 udelay(ad8402_udelay); 1834 outw(cal_enable_bits(dev), devpriv->control_status + CALIBRATION_REG); 1835 1836 return 0; 1837} 1838 1839static int wait_for_nvram_ready(unsigned long s5933_base_addr) 1840{ 1841 static const int timeout = 1000; 1842 unsigned int i; 1843 1844 for (i = 0; i < timeout; i++) { 1845 if ((inb(s5933_base_addr + 1846 AMCC_OP_REG_MCSR_NVCMD) & MCSR_NV_BUSY) 1847 == 0) 1848 return 0; 1849 udelay(1); 1850 } 1851 return -1; 1852} 1853 1854static int nvram_read(struct comedi_device *dev, unsigned int address, 1855 uint8_t * data) 1856{ 1857 unsigned long iobase = devpriv->s5933_config; 1858 1859 if (wait_for_nvram_ready(iobase) < 0) 1860 return -ETIMEDOUT; 1861 1862 outb(MCSR_NV_ENABLE | MCSR_NV_LOAD_LOW_ADDR, 1863 iobase + AMCC_OP_REG_MCSR_NVCMD); 1864 outb(address & 0xff, iobase + AMCC_OP_REG_MCSR_NVDATA); 1865 outb(MCSR_NV_ENABLE | MCSR_NV_LOAD_HIGH_ADDR, 1866 iobase + AMCC_OP_REG_MCSR_NVCMD); 1867 outb((address >> 8) & 0xff, iobase + AMCC_OP_REG_MCSR_NVDATA); 1868 outb(MCSR_NV_ENABLE | MCSR_NV_READ, iobase + AMCC_OP_REG_MCSR_NVCMD); 1869 1870 if (wait_for_nvram_ready(iobase) < 0) 1871 return -ETIMEDOUT; 1872 1873 *data = inb(iobase + AMCC_OP_REG_MCSR_NVDATA); 1874 1875 return 0; 1876} 1877 1878/* 1879 * A convenient macro that defines init_module() and cleanup_module(), 1880 * as necessary. 1881 */ 1882COMEDI_PCI_INITCLEANUP(driver_cb_pcidas, cb_pcidas_pci_table); 1883