ni_labpc.c revision 0229979a329e7354adb17d3ccb98bce82d73eb59
1/* 2 * comedi/drivers/ni_labpc.c 3 * Driver for National Instruments Lab-PC series boards and compatibles 4 * Copyright (C) 2001-2003 Frank Mori Hess <fmhess@users.sourceforge.net> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 */ 20 21/* 22 * Driver: ni_labpc 23 * Description: National Instruments Lab-PC (& compatibles) 24 * Devices: (National Instruments) Lab-PC-1200 [lab-pc-1200] 25 * (National Instruments) Lab-PC-1200AI [lab-pc-1200ai] 26 * (National Instruments) Lab-PC+ [lab-pc+] 27 * (National Instruments) PCI-1200 [pci-1200] 28 * Author: Frank Mori Hess <fmhess@users.sourceforge.net> 29 * Status: works 30 * 31 * Configuration options - ISA boards: 32 * [0] - I/O port base address 33 * [1] - IRQ (optional, required for timed or externally triggered 34 * conversions) 35 * [2] - DMA channel (optional) 36 * 37 * Configuration options - PCI boards: 38 * not applicable, uses PCI auto config 39 * 40 * Tested with lab-pc-1200. For the older Lab-PC+, not all input 41 * ranges and analog references will work, the available ranges/arefs 42 * will depend on how you have configured the jumpers on your board 43 * (see your owner's manual). 44 * 45 * Kernel-level ISA plug-and-play support for the lab-pc-1200 boards 46 * has not yet been added to the driver, mainly due to the fact that 47 * I don't know the device id numbers. If you have one of these boards, 48 * please file a bug report at http://comedi.org/ so I can get the 49 * necessary information from you. 50 * 51 * The 1200 series boards have onboard calibration dacs for correcting 52 * analog input/output offsets and gains. The proper settings for these 53 * caldacs are stored on the board's eeprom. To read the caldac values 54 * from the eeprom and store them into a file that can be then be used 55 * by comedilib, use the comedi_calibrate program. 56 * 57 * The Lab-pc+ has quirky chanlist requirements when scanning multiple 58 * channels. Multiple channel scan sequence must start at highest channel, 59 * then decrement down to channel 0. The rest of the cards can scan down 60 * like lab-pc+ or scan up from channel zero. Chanlists consisting of all 61 * one channel are also legal, and allow you to pace conversions in bursts. 62 * 63 * NI manuals: 64 * 341309a (labpc-1200 register manual) 65 * 340914a (pci-1200) 66 * 320502b (lab-pc+) 67 */ 68 69#include <linux/pci.h> 70#include <linux/interrupt.h> 71#include <linux/slab.h> 72#include <linux/io.h> 73#include <linux/delay.h> 74 75#include "../comedidev.h" 76 77#include <asm/dma.h> 78 79#include "8253.h" 80#include "8255.h" 81#include "mite.h" 82#include "comedi_fc.h" 83#include "ni_labpc.h" 84 85/* 86 * Register map (all registers are 8-bit) 87 */ 88#define STAT1_REG 0x00 /* R: Status 1 reg */ 89#define STAT1_DAVAIL (1 << 0) 90#define STAT1_OVERRUN (1 << 1) 91#define STAT1_OVERFLOW (1 << 2) 92#define STAT1_CNTINT (1 << 3) 93#define STAT1_GATA0 (1 << 5) 94#define STAT1_EXTGATA0 (1 << 6) 95#define CMD1_REG 0x00 /* W: Command 1 reg */ 96#define CMD1_MA(x) (((x) & 0x7) << 0) 97#define CMD1_TWOSCMP (1 << 3) 98#define CMD1_GAIN_MASK (7 << 4) 99#define CMD1_SCANEN (1 << 7) 100#define CMD2_REG 0x01 /* W: Command 2 reg */ 101#define CMD2_PRETRIG (1 << 0) 102#define CMD2_HWTRIG (1 << 1) 103#define CMD2_SWTRIG (1 << 2) 104#define CMD2_TBSEL (1 << 3) 105#define CMD2_2SDAC0 (1 << 4) 106#define CMD2_2SDAC1 (1 << 5) 107#define CMD2_LDAC(x) (1 << (6 + (x))) 108#define CMD3_REG 0x02 /* W: Command 3 reg */ 109#define CMD3_DMAEN (1 << 0) 110#define CMD3_DIOINTEN (1 << 1) 111#define CMD3_DMATCINTEN (1 << 2) 112#define CMD3_CNTINTEN (1 << 3) 113#define CMD3_ERRINTEN (1 << 4) 114#define CMD3_FIFOINTEN (1 << 5) 115#define ADC_START_CONVERT_REG 0x03 /* W: Start Convert reg */ 116#define DAC_LSB_REG(x) (0x04 + 2 * (x)) /* W: DAC0/1 LSB reg */ 117#define DAC_MSB_REG(x) (0x05 + 2 * (x)) /* W: DAC0/1 MSB reg */ 118#define ADC_FIFO_CLEAR_REG 0x08 /* W: A/D FIFO Clear reg */ 119#define ADC_FIFO_REG 0x0a /* R: A/D FIFO reg */ 120#define DMATC_CLEAR_REG 0x0a /* W: DMA Interrupt Clear reg */ 121#define TIMER_CLEAR_REG 0x0c /* W: Timer Interrupt Clear reg */ 122#define CMD6_REG 0x0e /* W: Command 6 reg */ 123#define CMD6_NRSE (1 << 0) 124#define CMD6_ADCUNI (1 << 1) 125#define CMD6_DACUNI(x) (1 << (2 + (x))) 126#define CMD6_HFINTEN (1 << 5) 127#define CMD6_DQINTEN (1 << 6) 128#define CMD6_SCANUP (1 << 7) 129#define CMD4_REG 0x0f /* W: Command 3 reg */ 130#define CMD4_INTSCAN (1 << 0) 131#define CMD4_EOIRCV (1 << 1) 132#define CMD4_ECLKDRV (1 << 2) 133#define CMD4_SEDIFF (1 << 3) 134#define CMD4_ECLKRCV (1 << 4) 135#define DIO_BASE_REG 0x10 /* R/W: 8255 DIO base reg */ 136#define COUNTER_A_BASE_REG 0x14 /* R/W: 8253 Counter A base reg */ 137#define COUNTER_B_BASE_REG 0x18 /* R/W: 8253 Counter B base reg */ 138#define CMD5_REG 0x1c /* W: Command 5 reg */ 139#define CMD5_WRTPRT (1 << 2) 140#define CMD5_DITHEREN (1 << 3) 141#define CMD5_CALDACLD (1 << 4) 142#define CMD5_SCLK (1 << 5) 143#define CMD5_SDATA (1 << 6) 144#define CMD5_EEPROMCS (1 << 7) 145#define STAT2_REG 0x1d /* R: Status 2 reg */ 146#define STAT2_PROMOUT (1 << 0) 147#define STAT2_OUTA1 (1 << 1) 148#define STAT2_FIFONHF (1 << 2) 149#define INTERVAL_COUNT_REG 0x1e /* W: Interval Counter Data reg */ 150#define INTERVAL_STROBE_REG 0x1f /* W: Interval Counter Strobe reg */ 151 152#define LABPC_SIZE 0x20 /* size of ISA io region */ 153#define LABPC_TIMER_BASE 500 /* 2 MHz master clock */ 154#define LABPC_ADC_TIMEOUT 1000 155 156enum scan_mode { 157 MODE_SINGLE_CHAN, 158 MODE_SINGLE_CHAN_INTERVAL, 159 MODE_MULT_CHAN_UP, 160 MODE_MULT_CHAN_DOWN, 161}; 162 163static const int labpc_plus_ai_gain_bits[] = { 164 0x00, 0x10, 0x20, 0x30, 0x40, 0x50, 0x60, 0x70, 165 0x00, 0x10, 0x20, 0x30, 0x40, 0x50, 0x60, 0x70, 166}; 167 168static const struct comedi_lrange range_labpc_plus_ai = { 169 16, { 170 BIP_RANGE(5), 171 BIP_RANGE(4), 172 BIP_RANGE(2.5), 173 BIP_RANGE(1), 174 BIP_RANGE(0.5), 175 BIP_RANGE(0.25), 176 BIP_RANGE(0.1), 177 BIP_RANGE(0.05), 178 UNI_RANGE(10), 179 UNI_RANGE(8), 180 UNI_RANGE(5), 181 UNI_RANGE(2), 182 UNI_RANGE(1), 183 UNI_RANGE(0.5), 184 UNI_RANGE(0.2), 185 UNI_RANGE(0.1) 186 } 187}; 188 189const int labpc_1200_ai_gain_bits[] = { 190 0x00, 0x20, 0x30, 0x40, 0x50, 0x60, 0x70, 191 0x00, 0x20, 0x30, 0x40, 0x50, 0x60, 0x70, 192}; 193EXPORT_SYMBOL_GPL(labpc_1200_ai_gain_bits); 194 195const struct comedi_lrange range_labpc_1200_ai = { 196 14, { 197 BIP_RANGE(5), 198 BIP_RANGE(2.5), 199 BIP_RANGE(1), 200 BIP_RANGE(0.5), 201 BIP_RANGE(0.25), 202 BIP_RANGE(0.1), 203 BIP_RANGE(0.05), 204 UNI_RANGE(10), 205 UNI_RANGE(5), 206 UNI_RANGE(2), 207 UNI_RANGE(1), 208 UNI_RANGE(0.5), 209 UNI_RANGE(0.2), 210 UNI_RANGE(0.1) 211 } 212}; 213EXPORT_SYMBOL_GPL(range_labpc_1200_ai); 214 215static const struct comedi_lrange range_labpc_ao = { 216 2, { 217 BIP_RANGE(5), 218 UNI_RANGE(10) 219 } 220}; 221 222/* functions that do inb/outb and readb/writeb so we can use 223 * function pointers to decide which to use */ 224static inline unsigned int labpc_inb(unsigned long address) 225{ 226 return inb(address); 227} 228 229static inline void labpc_outb(unsigned int byte, unsigned long address) 230{ 231 outb(byte, address); 232} 233 234static inline unsigned int labpc_readb(unsigned long address) 235{ 236 return readb((void __iomem *)address); 237} 238 239static inline void labpc_writeb(unsigned int byte, unsigned long address) 240{ 241 writeb(byte, (void __iomem *)address); 242} 243 244static const struct labpc_boardinfo labpc_boards[] = { 245 { 246 .name = "lab-pc-1200", 247 .ai_speed = 10000, 248 .bustype = isa_bustype, 249 .register_layout = labpc_1200_layout, 250 .has_ao = 1, 251 .ai_range_table = &range_labpc_1200_ai, 252 .ai_range_code = labpc_1200_ai_gain_bits, 253 .ai_scan_up = 1, 254 }, { 255 .name = "lab-pc-1200ai", 256 .ai_speed = 10000, 257 .bustype = isa_bustype, 258 .register_layout = labpc_1200_layout, 259 .ai_range_table = &range_labpc_1200_ai, 260 .ai_range_code = labpc_1200_ai_gain_bits, 261 .ai_scan_up = 1, 262 }, { 263 .name = "lab-pc+", 264 .ai_speed = 12000, 265 .bustype = isa_bustype, 266 .register_layout = labpc_plus_layout, 267 .has_ao = 1, 268 .ai_range_table = &range_labpc_plus_ai, 269 .ai_range_code = labpc_plus_ai_gain_bits, 270 }, 271#ifdef CONFIG_COMEDI_PCI_DRIVERS 272 { 273 .name = "pci-1200", 274 .device_id = 0x161, 275 .ai_speed = 10000, 276 .bustype = pci_bustype, 277 .register_layout = labpc_1200_layout, 278 .has_ao = 1, 279 .ai_range_table = &range_labpc_1200_ai, 280 .ai_range_code = labpc_1200_ai_gain_bits, 281 .ai_scan_up = 1, 282 .has_mmio = 1, 283 }, 284#endif 285}; 286 287/* size in bytes of dma buffer */ 288static const int dma_buffer_size = 0xff00; 289/* 2 bytes per sample */ 290static const int sample_size = 2; 291 292static int labpc_counter_load(struct comedi_device *dev, 293 unsigned long base_address, 294 unsigned int counter_number, 295 unsigned int count, unsigned int mode) 296{ 297 const struct labpc_boardinfo *board = comedi_board(dev); 298 299 if (board->has_mmio) 300 return i8254_mm_load((void __iomem *)base_address, 0, 301 counter_number, count, mode); 302 else 303 return i8254_load(base_address, 0, counter_number, count, mode); 304} 305 306static int labpc_counter_set_mode(struct comedi_device *dev, 307 unsigned long base_address, 308 unsigned int counter_number, 309 unsigned int mode) 310{ 311 const struct labpc_boardinfo *board = comedi_board(dev); 312 313 if (board->has_mmio) 314 return i8254_mm_set_mode((void __iomem *)base_address, 0, 315 counter_number, mode); 316 else 317 return i8254_set_mode(base_address, 0, counter_number, mode); 318} 319 320static bool labpc_range_is_unipolar(struct comedi_subdevice *s, 321 unsigned int range) 322{ 323 const struct comedi_lrange *lrange = s->range_table; 324 const struct comedi_krange *krange = &lrange->range[range]; 325 326 if (krange->min < 0) 327 return false; 328 else 329 return true; 330} 331 332static int labpc_cancel(struct comedi_device *dev, struct comedi_subdevice *s) 333{ 334 struct labpc_private *devpriv = dev->private; 335 unsigned long flags; 336 337 spin_lock_irqsave(&dev->spinlock, flags); 338 devpriv->cmd2 &= ~(CMD2_SWTRIG | CMD2_HWTRIG | CMD2_PRETRIG); 339 devpriv->write_byte(devpriv->cmd2, dev->iobase + CMD2_REG); 340 spin_unlock_irqrestore(&dev->spinlock, flags); 341 342 devpriv->cmd3 = 0; 343 devpriv->write_byte(devpriv->cmd3, dev->iobase + CMD3_REG); 344 345 return 0; 346} 347 348static void labpc_ai_set_chan_and_gain(struct comedi_device *dev, 349 enum scan_mode mode, 350 unsigned int chan, 351 unsigned int range, 352 unsigned int aref) 353{ 354 const struct labpc_boardinfo *board = comedi_board(dev); 355 struct labpc_private *devpriv = dev->private; 356 357 /* munge channel bits for differential/scan disabled mode */ 358 if ((mode == MODE_SINGLE_CHAN || mode == MODE_SINGLE_CHAN_INTERVAL) && 359 aref == AREF_DIFF) 360 chan *= 2; 361 devpriv->cmd1 = CMD1_MA(chan); 362 devpriv->cmd1 |= board->ai_range_code[range]; 363 364 devpriv->write_byte(devpriv->cmd1, dev->iobase + CMD1_REG); 365} 366 367static void labpc_setup_cmd6_reg(struct comedi_device *dev, 368 struct comedi_subdevice *s, 369 enum scan_mode mode, 370 enum transfer_type xfer, 371 unsigned int range, 372 unsigned int aref, 373 bool ena_intr) 374{ 375 const struct labpc_boardinfo *board = comedi_board(dev); 376 struct labpc_private *devpriv = dev->private; 377 378 if (board->register_layout != labpc_1200_layout) 379 return; 380 381 /* reference inputs to ground or common? */ 382 if (aref != AREF_GROUND) 383 devpriv->cmd6 |= CMD6_NRSE; 384 else 385 devpriv->cmd6 &= ~CMD6_NRSE; 386 387 /* bipolar or unipolar range? */ 388 if (labpc_range_is_unipolar(s, range)) 389 devpriv->cmd6 |= CMD6_ADCUNI; 390 else 391 devpriv->cmd6 &= ~CMD6_ADCUNI; 392 393 /* interrupt on fifo half full? */ 394 if (xfer == fifo_half_full_transfer) 395 devpriv->cmd6 |= CMD6_HFINTEN; 396 else 397 devpriv->cmd6 &= ~CMD6_HFINTEN; 398 399 /* enable interrupt on counter a1 terminal count? */ 400 if (ena_intr) 401 devpriv->cmd6 |= CMD6_DQINTEN; 402 else 403 devpriv->cmd6 &= ~CMD6_DQINTEN; 404 405 /* are we scanning up or down through channels? */ 406 if (mode == MODE_MULT_CHAN_UP) 407 devpriv->cmd6 |= CMD6_SCANUP; 408 else 409 devpriv->cmd6 &= ~CMD6_SCANUP; 410 411 devpriv->write_byte(devpriv->cmd6, dev->iobase + CMD6_REG); 412} 413 414static unsigned int labpc_read_adc_fifo(struct comedi_device *dev) 415{ 416 struct labpc_private *devpriv = dev->private; 417 unsigned int lsb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG); 418 unsigned int msb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG); 419 420 return (msb << 8) | lsb; 421} 422 423static void labpc_clear_adc_fifo(struct comedi_device *dev) 424{ 425 struct labpc_private *devpriv = dev->private; 426 427 devpriv->write_byte(0x1, dev->iobase + ADC_FIFO_CLEAR_REG); 428 labpc_read_adc_fifo(dev); 429} 430 431static int labpc_ai_wait_for_data(struct comedi_device *dev, 432 int timeout) 433{ 434 struct labpc_private *devpriv = dev->private; 435 int i; 436 437 for (i = 0; i < timeout; i++) { 438 devpriv->stat1 = devpriv->read_byte(dev->iobase + STAT1_REG); 439 if (devpriv->stat1 & STAT1_DAVAIL) 440 return 0; 441 udelay(1); 442 } 443 return -ETIME; 444} 445 446static int labpc_ai_insn_read(struct comedi_device *dev, 447 struct comedi_subdevice *s, 448 struct comedi_insn *insn, 449 unsigned int *data) 450{ 451 struct labpc_private *devpriv = dev->private; 452 unsigned int chan = CR_CHAN(insn->chanspec); 453 unsigned int range = CR_RANGE(insn->chanspec); 454 unsigned int aref = CR_AREF(insn->chanspec); 455 int ret; 456 int i; 457 458 /* disable timed conversions, interrupt generation and dma */ 459 labpc_cancel(dev, s); 460 461 labpc_ai_set_chan_and_gain(dev, MODE_SINGLE_CHAN, chan, range, aref); 462 463 labpc_setup_cmd6_reg(dev, s, MODE_SINGLE_CHAN, fifo_not_empty_transfer, 464 range, aref, false); 465 466 /* setup cmd4 register */ 467 devpriv->cmd4 = 0; 468 devpriv->cmd4 |= CMD4_ECLKRCV; 469 /* single-ended/differential */ 470 if (aref == AREF_DIFF) 471 devpriv->cmd4 |= CMD4_SEDIFF; 472 devpriv->write_byte(devpriv->cmd4, dev->iobase + CMD4_REG); 473 474 /* initialize pacer counter to prevent any problems */ 475 ret = labpc_counter_set_mode(dev, dev->iobase + COUNTER_A_BASE_REG, 476 0, I8254_MODE2); 477 if (ret) 478 return ret; 479 480 labpc_clear_adc_fifo(dev); 481 482 for (i = 0; i < insn->n; i++) { 483 /* trigger conversion */ 484 devpriv->write_byte(0x1, dev->iobase + ADC_START_CONVERT_REG); 485 486 ret = labpc_ai_wait_for_data(dev, LABPC_ADC_TIMEOUT); 487 if (ret) 488 return ret; 489 490 data[i] = labpc_read_adc_fifo(dev); 491 } 492 493 return insn->n; 494} 495 496#ifdef CONFIG_ISA_DMA_API 497/* utility function that suggests a dma transfer size in bytes */ 498static unsigned int labpc_suggest_transfer_size(const struct comedi_cmd *cmd) 499{ 500 unsigned int size; 501 unsigned int freq; 502 503 if (cmd->convert_src == TRIG_TIMER) 504 freq = 1000000000 / cmd->convert_arg; 505 /* return some default value */ 506 else 507 freq = 0xffffffff; 508 509 /* make buffer fill in no more than 1/3 second */ 510 size = (freq / 3) * sample_size; 511 512 /* set a minimum and maximum size allowed */ 513 if (size > dma_buffer_size) 514 size = dma_buffer_size - dma_buffer_size % sample_size; 515 else if (size < sample_size) 516 size = sample_size; 517 518 return size; 519} 520#endif 521 522static int labpc_use_continuous_mode(const struct comedi_cmd *cmd, 523 enum scan_mode mode) 524{ 525 if (mode == MODE_SINGLE_CHAN) 526 return 1; 527 528 if (cmd->scan_begin_src == TRIG_FOLLOW) 529 return 1; 530 531 return 0; 532} 533 534static unsigned int labpc_ai_convert_period(const struct comedi_cmd *cmd, 535 enum scan_mode mode) 536{ 537 if (cmd->convert_src != TRIG_TIMER) 538 return 0; 539 540 if (mode == MODE_SINGLE_CHAN && cmd->scan_begin_src == TRIG_TIMER) 541 return cmd->scan_begin_arg; 542 543 return cmd->convert_arg; 544} 545 546static void labpc_set_ai_convert_period(struct comedi_cmd *cmd, 547 enum scan_mode mode, unsigned int ns) 548{ 549 if (cmd->convert_src != TRIG_TIMER) 550 return; 551 552 if (mode == MODE_SINGLE_CHAN && 553 cmd->scan_begin_src == TRIG_TIMER) { 554 cmd->scan_begin_arg = ns; 555 if (cmd->convert_arg > cmd->scan_begin_arg) 556 cmd->convert_arg = cmd->scan_begin_arg; 557 } else 558 cmd->convert_arg = ns; 559} 560 561static unsigned int labpc_ai_scan_period(const struct comedi_cmd *cmd, 562 enum scan_mode mode) 563{ 564 if (cmd->scan_begin_src != TRIG_TIMER) 565 return 0; 566 567 if (mode == MODE_SINGLE_CHAN && cmd->convert_src == TRIG_TIMER) 568 return 0; 569 570 return cmd->scan_begin_arg; 571} 572 573static void labpc_set_ai_scan_period(struct comedi_cmd *cmd, 574 enum scan_mode mode, unsigned int ns) 575{ 576 if (cmd->scan_begin_src != TRIG_TIMER) 577 return; 578 579 if (mode == MODE_SINGLE_CHAN && cmd->convert_src == TRIG_TIMER) 580 return; 581 582 cmd->scan_begin_arg = ns; 583} 584 585/* figures out what counter values to use based on command */ 586static void labpc_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd, 587 enum scan_mode mode) 588{ 589 struct labpc_private *devpriv = dev->private; 590 /* max value for 16 bit counter in mode 2 */ 591 const int max_counter_value = 0x10000; 592 /* min value for 16 bit counter in mode 2 */ 593 const int min_counter_value = 2; 594 unsigned int base_period; 595 unsigned int scan_period; 596 unsigned int convert_period; 597 598 /* 599 * if both convert and scan triggers are TRIG_TIMER, then they 600 * both rely on counter b0 601 */ 602 convert_period = labpc_ai_convert_period(cmd, mode); 603 scan_period = labpc_ai_scan_period(cmd, mode); 604 if (convert_period && scan_period) { 605 /* 606 * pick the lowest b0 divisor value we can (for maximum input 607 * clock speed on convert and scan counters) 608 */ 609 devpriv->divisor_b0 = (scan_period - 1) / 610 (LABPC_TIMER_BASE * max_counter_value) + 1; 611 if (devpriv->divisor_b0 < min_counter_value) 612 devpriv->divisor_b0 = min_counter_value; 613 if (devpriv->divisor_b0 > max_counter_value) 614 devpriv->divisor_b0 = max_counter_value; 615 616 base_period = LABPC_TIMER_BASE * devpriv->divisor_b0; 617 618 /* set a0 for conversion frequency and b1 for scan frequency */ 619 switch (cmd->flags & TRIG_ROUND_MASK) { 620 default: 621 case TRIG_ROUND_NEAREST: 622 devpriv->divisor_a0 = 623 (convert_period + (base_period / 2)) / base_period; 624 devpriv->divisor_b1 = 625 (scan_period + (base_period / 2)) / base_period; 626 break; 627 case TRIG_ROUND_UP: 628 devpriv->divisor_a0 = 629 (convert_period + (base_period - 1)) / base_period; 630 devpriv->divisor_b1 = 631 (scan_period + (base_period - 1)) / base_period; 632 break; 633 case TRIG_ROUND_DOWN: 634 devpriv->divisor_a0 = convert_period / base_period; 635 devpriv->divisor_b1 = scan_period / base_period; 636 break; 637 } 638 /* make sure a0 and b1 values are acceptable */ 639 if (devpriv->divisor_a0 < min_counter_value) 640 devpriv->divisor_a0 = min_counter_value; 641 if (devpriv->divisor_a0 > max_counter_value) 642 devpriv->divisor_a0 = max_counter_value; 643 if (devpriv->divisor_b1 < min_counter_value) 644 devpriv->divisor_b1 = min_counter_value; 645 if (devpriv->divisor_b1 > max_counter_value) 646 devpriv->divisor_b1 = max_counter_value; 647 /* write corrected timings to command */ 648 labpc_set_ai_convert_period(cmd, mode, 649 base_period * devpriv->divisor_a0); 650 labpc_set_ai_scan_period(cmd, mode, 651 base_period * devpriv->divisor_b1); 652 /* 653 * if only one TRIG_TIMER is used, we can employ the generic 654 * cascaded timing functions 655 */ 656 } else if (scan_period) { 657 /* 658 * calculate cascaded counter values 659 * that give desired scan timing 660 */ 661 i8253_cascade_ns_to_timer_2div(LABPC_TIMER_BASE, 662 &(devpriv->divisor_b1), 663 &(devpriv->divisor_b0), 664 &scan_period, 665 cmd->flags & TRIG_ROUND_MASK); 666 labpc_set_ai_scan_period(cmd, mode, scan_period); 667 } else if (convert_period) { 668 /* 669 * calculate cascaded counter values 670 * that give desired conversion timing 671 */ 672 i8253_cascade_ns_to_timer_2div(LABPC_TIMER_BASE, 673 &(devpriv->divisor_a0), 674 &(devpriv->divisor_b0), 675 &convert_period, 676 cmd->flags & TRIG_ROUND_MASK); 677 labpc_set_ai_convert_period(cmd, mode, convert_period); 678 } 679} 680 681static enum scan_mode labpc_ai_scan_mode(const struct comedi_cmd *cmd) 682{ 683 if (cmd->chanlist_len == 1) 684 return MODE_SINGLE_CHAN; 685 686 /* chanlist may be NULL during cmdtest. */ 687 if (cmd->chanlist == NULL) 688 return MODE_MULT_CHAN_UP; 689 690 if (CR_CHAN(cmd->chanlist[0]) == CR_CHAN(cmd->chanlist[1])) 691 return MODE_SINGLE_CHAN_INTERVAL; 692 693 if (CR_CHAN(cmd->chanlist[0]) < CR_CHAN(cmd->chanlist[1])) 694 return MODE_MULT_CHAN_UP; 695 696 if (CR_CHAN(cmd->chanlist[0]) > CR_CHAN(cmd->chanlist[1])) 697 return MODE_MULT_CHAN_DOWN; 698 699 pr_err("ni_labpc: bug! cannot determine AI scan mode\n"); 700 return 0; 701} 702 703static int labpc_ai_chanlist_invalid(const struct comedi_device *dev, 704 const struct comedi_cmd *cmd, 705 enum scan_mode mode) 706{ 707 int channel, range, aref, i; 708 709 if (cmd->chanlist == NULL) 710 return 0; 711 712 if (mode == MODE_SINGLE_CHAN) 713 return 0; 714 715 if (mode == MODE_SINGLE_CHAN_INTERVAL) { 716 if (cmd->chanlist_len > 0xff) { 717 comedi_error(dev, 718 "ni_labpc: chanlist too long for single channel interval mode\n"); 719 return 1; 720 } 721 } 722 723 channel = CR_CHAN(cmd->chanlist[0]); 724 range = CR_RANGE(cmd->chanlist[0]); 725 aref = CR_AREF(cmd->chanlist[0]); 726 727 for (i = 0; i < cmd->chanlist_len; i++) { 728 729 switch (mode) { 730 case MODE_SINGLE_CHAN_INTERVAL: 731 if (CR_CHAN(cmd->chanlist[i]) != channel) { 732 comedi_error(dev, 733 "channel scanning order specified in chanlist is not supported by hardware.\n"); 734 return 1; 735 } 736 break; 737 case MODE_MULT_CHAN_UP: 738 if (CR_CHAN(cmd->chanlist[i]) != i) { 739 comedi_error(dev, 740 "channel scanning order specified in chanlist is not supported by hardware.\n"); 741 return 1; 742 } 743 break; 744 case MODE_MULT_CHAN_DOWN: 745 if (CR_CHAN(cmd->chanlist[i]) != 746 cmd->chanlist_len - i - 1) { 747 comedi_error(dev, 748 "channel scanning order specified in chanlist is not supported by hardware.\n"); 749 return 1; 750 } 751 break; 752 default: 753 dev_err(dev->class_dev, 754 "ni_labpc: bug! in chanlist check\n"); 755 return 1; 756 break; 757 } 758 759 if (CR_RANGE(cmd->chanlist[i]) != range) { 760 comedi_error(dev, 761 "entries in chanlist must all have the same range\n"); 762 return 1; 763 } 764 765 if (CR_AREF(cmd->chanlist[i]) != aref) { 766 comedi_error(dev, 767 "entries in chanlist must all have the same reference\n"); 768 return 1; 769 } 770 } 771 772 return 0; 773} 774 775static int labpc_ai_cmdtest(struct comedi_device *dev, 776 struct comedi_subdevice *s, struct comedi_cmd *cmd) 777{ 778 const struct labpc_boardinfo *board = comedi_board(dev); 779 int err = 0; 780 int tmp, tmp2; 781 unsigned int stop_mask; 782 enum scan_mode mode; 783 784 /* Step 1 : check if triggers are trivially valid */ 785 786 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_EXT); 787 err |= cfc_check_trigger_src(&cmd->scan_begin_src, 788 TRIG_TIMER | TRIG_FOLLOW | TRIG_EXT); 789 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_TIMER | TRIG_EXT); 790 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT); 791 792 stop_mask = TRIG_COUNT | TRIG_NONE; 793 if (board->register_layout == labpc_1200_layout) 794 stop_mask |= TRIG_EXT; 795 err |= cfc_check_trigger_src(&cmd->stop_src, stop_mask); 796 797 if (err) 798 return 1; 799 800 /* Step 2a : make sure trigger sources are unique */ 801 802 err |= cfc_check_trigger_is_unique(cmd->start_src); 803 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src); 804 err |= cfc_check_trigger_is_unique(cmd->convert_src); 805 err |= cfc_check_trigger_is_unique(cmd->stop_src); 806 807 /* Step 2b : and mutually compatible */ 808 809 /* can't have external stop and start triggers at once */ 810 if (cmd->start_src == TRIG_EXT && cmd->stop_src == TRIG_EXT) 811 err++; 812 813 if (err) 814 return 2; 815 816 /* Step 3: check if arguments are trivially valid */ 817 818 if (cmd->start_arg == TRIG_NOW) 819 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0); 820 821 if (!cmd->chanlist_len) 822 err |= -EINVAL; 823 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len); 824 825 if (cmd->convert_src == TRIG_TIMER) 826 err |= cfc_check_trigger_arg_min(&cmd->convert_arg, 827 board->ai_speed); 828 829 /* make sure scan timing is not too fast */ 830 if (cmd->scan_begin_src == TRIG_TIMER) { 831 if (cmd->convert_src == TRIG_TIMER) 832 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg, 833 cmd->convert_arg * cmd->chanlist_len); 834 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg, 835 board->ai_speed * cmd->chanlist_len); 836 } 837 838 switch (cmd->stop_src) { 839 case TRIG_COUNT: 840 err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1); 841 break; 842 case TRIG_NONE: 843 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0); 844 break; 845 /* 846 * TRIG_EXT doesn't care since it doesn't 847 * trigger off a numbered channel 848 */ 849 default: 850 break; 851 } 852 853 if (err) 854 return 3; 855 856 /* step 4: fix up any arguments */ 857 858 tmp = cmd->convert_arg; 859 tmp2 = cmd->scan_begin_arg; 860 mode = labpc_ai_scan_mode(cmd); 861 labpc_adc_timing(dev, cmd, mode); 862 if (tmp != cmd->convert_arg || tmp2 != cmd->scan_begin_arg) 863 err++; 864 865 if (err) 866 return 4; 867 868 if (labpc_ai_chanlist_invalid(dev, cmd, mode)) 869 return 5; 870 871 return 0; 872} 873 874static int labpc_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) 875{ 876 const struct labpc_boardinfo *board = comedi_board(dev); 877 struct labpc_private *devpriv = dev->private; 878 struct comedi_async *async = s->async; 879 struct comedi_cmd *cmd = &async->cmd; 880 enum scan_mode mode = labpc_ai_scan_mode(cmd); 881 unsigned int chanspec = (mode == MODE_MULT_CHAN_UP) 882 ? cmd->chanlist[cmd->chanlist_len - 1] 883 : cmd->chanlist[0]; 884 unsigned int chan = CR_CHAN(chanspec); 885 unsigned int range = CR_RANGE(chanspec); 886 unsigned int aref = CR_AREF(chanspec); 887 enum transfer_type xfer; 888 unsigned long flags; 889 int ret; 890 891 /* make sure board is disabled before setting up acquisition */ 892 labpc_cancel(dev, s); 893 894 /* initialize software conversion count */ 895 if (cmd->stop_src == TRIG_COUNT) 896 devpriv->count = cmd->stop_arg * cmd->chanlist_len; 897 898 /* setup hardware conversion counter */ 899 if (cmd->stop_src == TRIG_EXT) { 900 /* 901 * load counter a1 with count of 3 902 * (pc+ manual says this is minimum allowed) using mode 0 903 */ 904 ret = labpc_counter_load(dev, dev->iobase + COUNTER_A_BASE_REG, 905 1, 3, I8254_MODE0); 906 } else { 907 /* just put counter a1 in mode 0 to set its output low */ 908 ret = labpc_counter_set_mode(dev, 909 dev->iobase + COUNTER_A_BASE_REG, 910 1, I8254_MODE0); 911 } 912 if (ret) { 913 comedi_error(dev, "error loading counter a1"); 914 return ret; 915 } 916 917#ifdef CONFIG_ISA_DMA_API 918 /* figure out what method we will use to transfer data */ 919 if (devpriv->dma_chan && /* need a dma channel allocated */ 920 /* 921 * dma unsafe at RT priority, 922 * and too much setup time for TRIG_WAKE_EOS for 923 */ 924 (cmd->flags & (TRIG_WAKE_EOS | TRIG_RT)) == 0 && 925 /* only available on the isa boards */ 926 board->bustype == isa_bustype) { 927 xfer = isa_dma_transfer; 928 /* pc-plus has no fifo-half full interrupt */ 929 } else 930#endif 931 if (board->register_layout == labpc_1200_layout && 932 /* wake-end-of-scan should interrupt on fifo not empty */ 933 (cmd->flags & TRIG_WAKE_EOS) == 0 && 934 /* make sure we are taking more than just a few points */ 935 (cmd->stop_src != TRIG_COUNT || devpriv->count > 256)) { 936 xfer = fifo_half_full_transfer; 937 } else 938 xfer = fifo_not_empty_transfer; 939 devpriv->current_transfer = xfer; 940 941 labpc_ai_set_chan_and_gain(dev, mode, chan, range, aref); 942 943 labpc_setup_cmd6_reg(dev, s, mode, xfer, range, aref, 944 (cmd->stop_src == TRIG_EXT)); 945 946 /* manual says to set scan enable bit on second pass */ 947 if (mode == MODE_MULT_CHAN_UP || mode == MODE_MULT_CHAN_DOWN) { 948 devpriv->cmd1 |= CMD1_SCANEN; 949 /* need a brief delay before enabling scan, or scan 950 * list will get screwed when you switch 951 * between scan up to scan down mode - dunno why */ 952 udelay(1); 953 devpriv->write_byte(devpriv->cmd1, dev->iobase + CMD1_REG); 954 } 955 956 devpriv->write_byte(cmd->chanlist_len, 957 dev->iobase + INTERVAL_COUNT_REG); 958 /* load count */ 959 devpriv->write_byte(0x1, dev->iobase + INTERVAL_STROBE_REG); 960 961 if (cmd->convert_src == TRIG_TIMER || 962 cmd->scan_begin_src == TRIG_TIMER) { 963 /* set up pacing */ 964 labpc_adc_timing(dev, cmd, mode); 965 /* load counter b0 in mode 3 */ 966 ret = labpc_counter_load(dev, dev->iobase + COUNTER_B_BASE_REG, 967 0, devpriv->divisor_b0, I8254_MODE3); 968 if (ret < 0) { 969 comedi_error(dev, "error loading counter b0"); 970 return -1; 971 } 972 } 973 /* set up conversion pacing */ 974 if (labpc_ai_convert_period(cmd, mode)) { 975 /* load counter a0 in mode 2 */ 976 ret = labpc_counter_load(dev, dev->iobase + COUNTER_A_BASE_REG, 977 0, devpriv->divisor_a0, I8254_MODE2); 978 } else { 979 /* initialize pacer counter to prevent any problems */ 980 ret = labpc_counter_set_mode(dev, 981 dev->iobase + COUNTER_A_BASE_REG, 982 0, I8254_MODE2); 983 } 984 if (ret) { 985 comedi_error(dev, "error loading counter a0"); 986 return ret; 987 } 988 989 /* set up scan pacing */ 990 if (labpc_ai_scan_period(cmd, mode)) { 991 /* load counter b1 in mode 2 */ 992 ret = labpc_counter_load(dev, dev->iobase + COUNTER_B_BASE_REG, 993 1, devpriv->divisor_b1, I8254_MODE2); 994 if (ret < 0) { 995 comedi_error(dev, "error loading counter b1"); 996 return -1; 997 } 998 } 999 1000 labpc_clear_adc_fifo(dev); 1001 1002#ifdef CONFIG_ISA_DMA_API 1003 /* set up dma transfer */ 1004 if (xfer == isa_dma_transfer) { 1005 unsigned long irq_flags; 1006 1007 irq_flags = claim_dma_lock(); 1008 disable_dma(devpriv->dma_chan); 1009 /* clear flip-flop to make sure 2-byte registers for 1010 * count and address get set correctly */ 1011 clear_dma_ff(devpriv->dma_chan); 1012 set_dma_addr(devpriv->dma_chan, 1013 virt_to_bus(devpriv->dma_buffer)); 1014 /* set appropriate size of transfer */ 1015 devpriv->dma_transfer_size = labpc_suggest_transfer_size(cmd); 1016 if (cmd->stop_src == TRIG_COUNT && 1017 devpriv->count * sample_size < devpriv->dma_transfer_size) { 1018 devpriv->dma_transfer_size = 1019 devpriv->count * sample_size; 1020 } 1021 set_dma_count(devpriv->dma_chan, devpriv->dma_transfer_size); 1022 enable_dma(devpriv->dma_chan); 1023 release_dma_lock(irq_flags); 1024 /* enable board's dma */ 1025 devpriv->cmd3 |= (CMD3_DMAEN | CMD3_DMATCINTEN); 1026 } else 1027 devpriv->cmd3 &= ~(CMD3_DMAEN | CMD3_DMATCINTEN); 1028#endif 1029 1030 /* enable error interrupts */ 1031 devpriv->cmd3 |= CMD3_ERRINTEN; 1032 /* enable fifo not empty interrupt? */ 1033 if (xfer == fifo_not_empty_transfer) 1034 devpriv->cmd3 |= CMD3_FIFOINTEN; 1035 else 1036 devpriv->cmd3 &= ~CMD3_FIFOINTEN; 1037 devpriv->write_byte(devpriv->cmd3, dev->iobase + CMD3_REG); 1038 1039 /* setup any external triggering/pacing (cmd4 register) */ 1040 devpriv->cmd4 = 0; 1041 if (cmd->convert_src != TRIG_EXT) 1042 devpriv->cmd4 |= CMD4_ECLKRCV; 1043 /* XXX should discard first scan when using interval scanning 1044 * since manual says it is not synced with scan clock */ 1045 if (labpc_use_continuous_mode(cmd, mode) == 0) { 1046 devpriv->cmd4 |= CMD4_INTSCAN; 1047 if (cmd->scan_begin_src == TRIG_EXT) 1048 devpriv->cmd4 |= CMD4_EOIRCV; 1049 } 1050 /* single-ended/differential */ 1051 if (aref == AREF_DIFF) 1052 devpriv->cmd4 |= CMD4_SEDIFF; 1053 devpriv->write_byte(devpriv->cmd4, dev->iobase + CMD4_REG); 1054 1055 /* startup acquisition */ 1056 1057 /* cmd2 reg */ 1058 /* use 2 cascaded counters for pacing */ 1059 spin_lock_irqsave(&dev->spinlock, flags); 1060 devpriv->cmd2 |= CMD2_TBSEL; 1061 switch (cmd->start_src) { 1062 case TRIG_EXT: 1063 devpriv->cmd2 |= CMD2_HWTRIG; 1064 devpriv->cmd2 &= ~(CMD2_PRETRIG | CMD2_SWTRIG); 1065 break; 1066 case TRIG_NOW: 1067 devpriv->cmd2 |= CMD2_SWTRIG; 1068 devpriv->cmd2 &= ~(CMD2_PRETRIG | CMD2_HWTRIG); 1069 break; 1070 default: 1071 comedi_error(dev, "bug with start_src"); 1072 spin_unlock_irqrestore(&dev->spinlock, flags); 1073 return -1; 1074 break; 1075 } 1076 switch (cmd->stop_src) { 1077 case TRIG_EXT: 1078 devpriv->cmd2 |= (CMD2_HWTRIG | CMD2_PRETRIG); 1079 break; 1080 case TRIG_COUNT: 1081 case TRIG_NONE: 1082 break; 1083 default: 1084 comedi_error(dev, "bug with stop_src"); 1085 spin_unlock_irqrestore(&dev->spinlock, flags); 1086 return -1; 1087 } 1088 devpriv->write_byte(devpriv->cmd2, dev->iobase + CMD2_REG); 1089 spin_unlock_irqrestore(&dev->spinlock, flags); 1090 1091 return 0; 1092} 1093 1094#ifdef CONFIG_ISA_DMA_API 1095static void labpc_drain_dma(struct comedi_device *dev) 1096{ 1097 struct labpc_private *devpriv = dev->private; 1098 struct comedi_subdevice *s = dev->read_subdev; 1099 struct comedi_async *async = s->async; 1100 int status; 1101 unsigned long flags; 1102 unsigned int max_points, num_points, residue, leftover; 1103 int i; 1104 1105 status = devpriv->stat1; 1106 1107 flags = claim_dma_lock(); 1108 disable_dma(devpriv->dma_chan); 1109 /* clear flip-flop to make sure 2-byte registers for 1110 * count and address get set correctly */ 1111 clear_dma_ff(devpriv->dma_chan); 1112 1113 /* figure out how many points to read */ 1114 max_points = devpriv->dma_transfer_size / sample_size; 1115 /* residue is the number of points left to be done on the dma 1116 * transfer. It should always be zero at this point unless 1117 * the stop_src is set to external triggering. 1118 */ 1119 residue = get_dma_residue(devpriv->dma_chan) / sample_size; 1120 num_points = max_points - residue; 1121 if (devpriv->count < num_points && async->cmd.stop_src == TRIG_COUNT) 1122 num_points = devpriv->count; 1123 1124 /* figure out how many points will be stored next time */ 1125 leftover = 0; 1126 if (async->cmd.stop_src != TRIG_COUNT) { 1127 leftover = devpriv->dma_transfer_size / sample_size; 1128 } else if (devpriv->count > num_points) { 1129 leftover = devpriv->count - num_points; 1130 if (leftover > max_points) 1131 leftover = max_points; 1132 } 1133 1134 /* write data to comedi buffer */ 1135 for (i = 0; i < num_points; i++) 1136 cfc_write_to_buffer(s, devpriv->dma_buffer[i]); 1137 1138 if (async->cmd.stop_src == TRIG_COUNT) 1139 devpriv->count -= num_points; 1140 1141 /* set address and count for next transfer */ 1142 set_dma_addr(devpriv->dma_chan, virt_to_bus(devpriv->dma_buffer)); 1143 set_dma_count(devpriv->dma_chan, leftover * sample_size); 1144 release_dma_lock(flags); 1145 1146 async->events |= COMEDI_CB_BLOCK; 1147} 1148 1149static void handle_isa_dma(struct comedi_device *dev) 1150{ 1151 struct labpc_private *devpriv = dev->private; 1152 1153 labpc_drain_dma(dev); 1154 1155 enable_dma(devpriv->dma_chan); 1156 1157 /* clear dma tc interrupt */ 1158 devpriv->write_byte(0x1, dev->iobase + DMATC_CLEAR_REG); 1159} 1160#endif 1161 1162/* read all available samples from ai fifo */ 1163static int labpc_drain_fifo(struct comedi_device *dev) 1164{ 1165 struct labpc_private *devpriv = dev->private; 1166 short data; 1167 struct comedi_async *async = dev->read_subdev->async; 1168 const int timeout = 10000; 1169 unsigned int i; 1170 1171 devpriv->stat1 = devpriv->read_byte(dev->iobase + STAT1_REG); 1172 1173 for (i = 0; (devpriv->stat1 & STAT1_DAVAIL) && i < timeout; 1174 i++) { 1175 /* quit if we have all the data we want */ 1176 if (async->cmd.stop_src == TRIG_COUNT) { 1177 if (devpriv->count == 0) 1178 break; 1179 devpriv->count--; 1180 } 1181 data = labpc_read_adc_fifo(dev); 1182 cfc_write_to_buffer(dev->read_subdev, data); 1183 devpriv->stat1 = devpriv->read_byte(dev->iobase + STAT1_REG); 1184 } 1185 if (i == timeout) { 1186 comedi_error(dev, "ai timeout, fifo never empties"); 1187 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA; 1188 return -1; 1189 } 1190 1191 return 0; 1192} 1193 1194/* makes sure all data acquired by board is transferred to comedi (used 1195 * when acquisition is terminated by stop_src == TRIG_EXT). */ 1196static void labpc_drain_dregs(struct comedi_device *dev) 1197{ 1198#ifdef CONFIG_ISA_DMA_API 1199 struct labpc_private *devpriv = dev->private; 1200 1201 if (devpriv->current_transfer == isa_dma_transfer) 1202 labpc_drain_dma(dev); 1203#endif 1204 1205 labpc_drain_fifo(dev); 1206} 1207 1208/* interrupt service routine */ 1209static irqreturn_t labpc_interrupt(int irq, void *d) 1210{ 1211 struct comedi_device *dev = d; 1212 const struct labpc_boardinfo *board = comedi_board(dev); 1213 struct labpc_private *devpriv = dev->private; 1214 struct comedi_subdevice *s = dev->read_subdev; 1215 struct comedi_async *async; 1216 struct comedi_cmd *cmd; 1217 1218 if (!dev->attached) { 1219 comedi_error(dev, "premature interrupt"); 1220 return IRQ_HANDLED; 1221 } 1222 1223 async = s->async; 1224 cmd = &async->cmd; 1225 async->events = 0; 1226 1227 /* read board status */ 1228 devpriv->stat1 = devpriv->read_byte(dev->iobase + STAT1_REG); 1229 if (board->register_layout == labpc_1200_layout) 1230 devpriv->stat2 = devpriv->read_byte(dev->iobase + STAT2_REG); 1231 1232 if ((devpriv->stat1 & (STAT1_GATA0 | STAT1_CNTINT | STAT1_OVERFLOW | 1233 STAT1_OVERRUN | STAT1_DAVAIL)) == 0 1234 && (devpriv->stat2 & STAT2_OUTA1) == 0 1235 && (devpriv->stat2 & STAT2_FIFONHF)) { 1236 return IRQ_NONE; 1237 } 1238 1239 if (devpriv->stat1 & STAT1_OVERRUN) { 1240 /* clear error interrupt */ 1241 devpriv->write_byte(0x1, dev->iobase + ADC_FIFO_CLEAR_REG); 1242 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA; 1243 comedi_event(dev, s); 1244 comedi_error(dev, "overrun"); 1245 return IRQ_HANDLED; 1246 } 1247 1248#ifdef CONFIG_ISA_DMA_API 1249 if (devpriv->current_transfer == isa_dma_transfer) { 1250 /* 1251 * if a dma terminal count of external stop trigger 1252 * has occurred 1253 */ 1254 if (devpriv->stat1 & STAT1_GATA0 || 1255 (board->register_layout == labpc_1200_layout 1256 && devpriv->stat2 & STAT2_OUTA1)) { 1257 handle_isa_dma(dev); 1258 } 1259 } else 1260#endif 1261 labpc_drain_fifo(dev); 1262 1263 if (devpriv->stat1 & STAT1_CNTINT) { 1264 comedi_error(dev, "handled timer interrupt?"); 1265 /* clear it */ 1266 devpriv->write_byte(0x1, dev->iobase + TIMER_CLEAR_REG); 1267 } 1268 1269 if (devpriv->stat1 & STAT1_OVERFLOW) { 1270 /* clear error interrupt */ 1271 devpriv->write_byte(0x1, dev->iobase + ADC_FIFO_CLEAR_REG); 1272 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA; 1273 comedi_event(dev, s); 1274 comedi_error(dev, "overflow"); 1275 return IRQ_HANDLED; 1276 } 1277 /* handle external stop trigger */ 1278 if (cmd->stop_src == TRIG_EXT) { 1279 if (devpriv->stat2 & STAT2_OUTA1) { 1280 labpc_drain_dregs(dev); 1281 labpc_cancel(dev, s); 1282 async->events |= COMEDI_CB_EOA; 1283 } 1284 } 1285 1286 /* TRIG_COUNT end of acquisition */ 1287 if (cmd->stop_src == TRIG_COUNT) { 1288 if (devpriv->count == 0) { 1289 labpc_cancel(dev, s); 1290 async->events |= COMEDI_CB_EOA; 1291 } 1292 } 1293 1294 comedi_event(dev, s); 1295 return IRQ_HANDLED; 1296} 1297 1298static int labpc_ao_insn_write(struct comedi_device *dev, 1299 struct comedi_subdevice *s, 1300 struct comedi_insn *insn, 1301 unsigned int *data) 1302{ 1303 const struct labpc_boardinfo *board = comedi_board(dev); 1304 struct labpc_private *devpriv = dev->private; 1305 int channel, range; 1306 unsigned long flags; 1307 int lsb, msb; 1308 1309 channel = CR_CHAN(insn->chanspec); 1310 1311 /* turn off pacing of analog output channel */ 1312 /* note: hardware bug in daqcard-1200 means pacing cannot 1313 * be independently enabled/disabled for its the two channels */ 1314 spin_lock_irqsave(&dev->spinlock, flags); 1315 devpriv->cmd2 &= ~CMD2_LDAC(channel); 1316 devpriv->write_byte(devpriv->cmd2, dev->iobase + CMD2_REG); 1317 spin_unlock_irqrestore(&dev->spinlock, flags); 1318 1319 /* set range */ 1320 if (board->register_layout == labpc_1200_layout) { 1321 range = CR_RANGE(insn->chanspec); 1322 if (labpc_range_is_unipolar(s, range)) 1323 devpriv->cmd6 |= CMD6_DACUNI(channel); 1324 else 1325 devpriv->cmd6 &= ~CMD6_DACUNI(channel); 1326 /* write to register */ 1327 devpriv->write_byte(devpriv->cmd6, dev->iobase + CMD6_REG); 1328 } 1329 /* send data */ 1330 lsb = data[0] & 0xff; 1331 msb = (data[0] >> 8) & 0xff; 1332 devpriv->write_byte(lsb, dev->iobase + DAC_LSB_REG(channel)); 1333 devpriv->write_byte(msb, dev->iobase + DAC_MSB_REG(channel)); 1334 1335 /* remember value for readback */ 1336 devpriv->ao_value[channel] = data[0]; 1337 1338 return 1; 1339} 1340 1341static int labpc_ao_insn_read(struct comedi_device *dev, 1342 struct comedi_subdevice *s, 1343 struct comedi_insn *insn, 1344 unsigned int *data) 1345{ 1346 struct labpc_private *devpriv = dev->private; 1347 1348 data[0] = devpriv->ao_value[CR_CHAN(insn->chanspec)]; 1349 1350 return 1; 1351} 1352 1353static int labpc_8255_mmio(int dir, int port, int data, unsigned long iobase) 1354{ 1355 if (dir) { 1356 writeb(data, (void __iomem *)(iobase + port)); 1357 return 0; 1358 } else { 1359 return readb((void __iomem *)(iobase + port)); 1360 } 1361} 1362 1363/* lowlevel write to eeprom/dac */ 1364static void labpc_serial_out(struct comedi_device *dev, unsigned int value, 1365 unsigned int value_width) 1366{ 1367 struct labpc_private *devpriv = dev->private; 1368 int i; 1369 1370 for (i = 1; i <= value_width; i++) { 1371 /* clear serial clock */ 1372 devpriv->cmd5 &= ~CMD5_SCLK; 1373 /* send bits most significant bit first */ 1374 if (value & (1 << (value_width - i))) 1375 devpriv->cmd5 |= CMD5_SDATA; 1376 else 1377 devpriv->cmd5 &= ~CMD5_SDATA; 1378 udelay(1); 1379 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); 1380 /* set clock to load bit */ 1381 devpriv->cmd5 |= CMD5_SCLK; 1382 udelay(1); 1383 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); 1384 } 1385} 1386 1387/* lowlevel read from eeprom */ 1388static unsigned int labpc_serial_in(struct comedi_device *dev) 1389{ 1390 struct labpc_private *devpriv = dev->private; 1391 unsigned int value = 0; 1392 int i; 1393 const int value_width = 8; /* number of bits wide values are */ 1394 1395 for (i = 1; i <= value_width; i++) { 1396 /* set serial clock */ 1397 devpriv->cmd5 |= CMD5_SCLK; 1398 udelay(1); 1399 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); 1400 /* clear clock bit */ 1401 devpriv->cmd5 &= ~CMD5_SCLK; 1402 udelay(1); 1403 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); 1404 /* read bits most significant bit first */ 1405 udelay(1); 1406 devpriv->stat2 = devpriv->read_byte(dev->iobase + STAT2_REG); 1407 if (devpriv->stat2 & STAT2_PROMOUT) 1408 value |= 1 << (value_width - i); 1409 } 1410 1411 return value; 1412} 1413 1414static unsigned int labpc_eeprom_read(struct comedi_device *dev, 1415 unsigned int address) 1416{ 1417 struct labpc_private *devpriv = dev->private; 1418 unsigned int value; 1419 /* bits to tell eeprom to expect a read */ 1420 const int read_instruction = 0x3; 1421 /* 8 bit write lengths to eeprom */ 1422 const int write_length = 8; 1423 1424 /* enable read/write to eeprom */ 1425 devpriv->cmd5 &= ~CMD5_EEPROMCS; 1426 udelay(1); 1427 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); 1428 devpriv->cmd5 |= (CMD5_EEPROMCS | CMD5_WRTPRT); 1429 udelay(1); 1430 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); 1431 1432 /* send read instruction */ 1433 labpc_serial_out(dev, read_instruction, write_length); 1434 /* send 8 bit address to read from */ 1435 labpc_serial_out(dev, address, write_length); 1436 /* read result */ 1437 value = labpc_serial_in(dev); 1438 1439 /* disable read/write to eeprom */ 1440 devpriv->cmd5 &= ~(CMD5_EEPROMCS | CMD5_WRTPRT); 1441 udelay(1); 1442 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); 1443 1444 return value; 1445} 1446 1447static unsigned int labpc_eeprom_read_status(struct comedi_device *dev) 1448{ 1449 struct labpc_private *devpriv = dev->private; 1450 unsigned int value; 1451 const int read_status_instruction = 0x5; 1452 const int write_length = 8; /* 8 bit write lengths to eeprom */ 1453 1454 /* enable read/write to eeprom */ 1455 devpriv->cmd5 &= ~CMD5_EEPROMCS; 1456 udelay(1); 1457 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); 1458 devpriv->cmd5 |= (CMD5_EEPROMCS | CMD5_WRTPRT); 1459 udelay(1); 1460 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); 1461 1462 /* send read status instruction */ 1463 labpc_serial_out(dev, read_status_instruction, write_length); 1464 /* read result */ 1465 value = labpc_serial_in(dev); 1466 1467 /* disable read/write to eeprom */ 1468 devpriv->cmd5 &= ~(CMD5_EEPROMCS | CMD5_WRTPRT); 1469 udelay(1); 1470 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); 1471 1472 return value; 1473} 1474 1475static int labpc_eeprom_write(struct comedi_device *dev, 1476 unsigned int address, unsigned int value) 1477{ 1478 struct labpc_private *devpriv = dev->private; 1479 const int write_enable_instruction = 0x6; 1480 const int write_instruction = 0x2; 1481 const int write_length = 8; /* 8 bit write lengths to eeprom */ 1482 const int write_in_progress_bit = 0x1; 1483 const int timeout = 10000; 1484 int i; 1485 1486 /* make sure there isn't already a write in progress */ 1487 for (i = 0; i < timeout; i++) { 1488 if ((labpc_eeprom_read_status(dev) & write_in_progress_bit) == 1489 0) 1490 break; 1491 } 1492 if (i == timeout) { 1493 comedi_error(dev, "eeprom write timed out"); 1494 return -ETIME; 1495 } 1496 /* update software copy of eeprom */ 1497 devpriv->eeprom_data[address] = value; 1498 1499 /* enable read/write to eeprom */ 1500 devpriv->cmd5 &= ~CMD5_EEPROMCS; 1501 udelay(1); 1502 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); 1503 devpriv->cmd5 |= (CMD5_EEPROMCS | CMD5_WRTPRT); 1504 udelay(1); 1505 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); 1506 1507 /* send write_enable instruction */ 1508 labpc_serial_out(dev, write_enable_instruction, write_length); 1509 devpriv->cmd5 &= ~CMD5_EEPROMCS; 1510 udelay(1); 1511 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); 1512 1513 /* send write instruction */ 1514 devpriv->cmd5 |= CMD5_EEPROMCS; 1515 udelay(1); 1516 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); 1517 labpc_serial_out(dev, write_instruction, write_length); 1518 /* send 8 bit address to write to */ 1519 labpc_serial_out(dev, address, write_length); 1520 /* write value */ 1521 labpc_serial_out(dev, value, write_length); 1522 devpriv->cmd5 &= ~CMD5_EEPROMCS; 1523 udelay(1); 1524 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); 1525 1526 /* disable read/write to eeprom */ 1527 devpriv->cmd5 &= ~(CMD5_EEPROMCS | CMD5_WRTPRT); 1528 udelay(1); 1529 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); 1530 1531 return 0; 1532} 1533 1534/* writes to 8 bit calibration dacs */ 1535static void write_caldac(struct comedi_device *dev, unsigned int channel, 1536 unsigned int value) 1537{ 1538 struct labpc_private *devpriv = dev->private; 1539 1540 if (value == devpriv->caldac[channel]) 1541 return; 1542 devpriv->caldac[channel] = value; 1543 1544 /* clear caldac load bit and make sure we don't write to eeprom */ 1545 devpriv->cmd5 &= ~(CMD5_CALDACLD | CMD5_EEPROMCS | CMD5_WRTPRT); 1546 udelay(1); 1547 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); 1548 1549 /* write 4 bit channel */ 1550 labpc_serial_out(dev, channel, 4); 1551 /* write 8 bit caldac value */ 1552 labpc_serial_out(dev, value, 8); 1553 1554 /* set and clear caldac bit to load caldac value */ 1555 devpriv->cmd5 |= CMD5_CALDACLD; 1556 udelay(1); 1557 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); 1558 devpriv->cmd5 &= ~CMD5_CALDACLD; 1559 udelay(1); 1560 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); 1561} 1562 1563static int labpc_calib_insn_write(struct comedi_device *dev, 1564 struct comedi_subdevice *s, 1565 struct comedi_insn *insn, 1566 unsigned int *data) 1567{ 1568 int channel = CR_CHAN(insn->chanspec); 1569 1570 write_caldac(dev, channel, data[0]); 1571 return 1; 1572} 1573 1574static int labpc_calib_insn_read(struct comedi_device *dev, 1575 struct comedi_subdevice *s, 1576 struct comedi_insn *insn, 1577 unsigned int *data) 1578{ 1579 struct labpc_private *devpriv = dev->private; 1580 1581 data[0] = devpriv->caldac[CR_CHAN(insn->chanspec)]; 1582 1583 return 1; 1584} 1585 1586static int labpc_eeprom_insn_write(struct comedi_device *dev, 1587 struct comedi_subdevice *s, 1588 struct comedi_insn *insn, 1589 unsigned int *data) 1590{ 1591 int channel = CR_CHAN(insn->chanspec); 1592 int ret; 1593 1594 /* only allow writes to user area of eeprom */ 1595 if (channel < 16 || channel > 127) { 1596 dev_dbg(dev->class_dev, 1597 "eeprom writes are only allowed to channels 16 through 127 (the pointer and user areas)\n"); 1598 return -EINVAL; 1599 } 1600 1601 ret = labpc_eeprom_write(dev, channel, data[0]); 1602 if (ret < 0) 1603 return ret; 1604 1605 return 1; 1606} 1607 1608static int labpc_eeprom_insn_read(struct comedi_device *dev, 1609 struct comedi_subdevice *s, 1610 struct comedi_insn *insn, 1611 unsigned int *data) 1612{ 1613 struct labpc_private *devpriv = dev->private; 1614 1615 data[0] = devpriv->eeprom_data[CR_CHAN(insn->chanspec)]; 1616 1617 return 1; 1618} 1619 1620int labpc_common_attach(struct comedi_device *dev, unsigned long iobase, 1621 unsigned int irq, unsigned int dma_chan) 1622{ 1623 const struct labpc_boardinfo *board = comedi_board(dev); 1624 struct labpc_private *devpriv = dev->private; 1625 struct comedi_subdevice *s; 1626 unsigned long isr_flags; 1627 int ret; 1628 int i; 1629 1630 dev->board_name = board->name; 1631 1632 dev_info(dev->class_dev, "ni_labpc: %s\n", dev->board_name); 1633 if (iobase == 0) { 1634 dev_err(dev->class_dev, "io base address is zero!\n"); 1635 return -EINVAL; 1636 } 1637 /* request io regions for isa boards */ 1638 if (board->bustype == isa_bustype) { 1639 /* check if io addresses are available */ 1640 if (!request_region(iobase, LABPC_SIZE, dev->board_name)) { 1641 dev_err(dev->class_dev, "I/O port conflict\n"); 1642 return -EIO; 1643 } 1644 } 1645 dev->iobase = iobase; 1646 1647 if (board->has_mmio) { 1648 devpriv->read_byte = labpc_readb; 1649 devpriv->write_byte = labpc_writeb; 1650 } else { 1651 devpriv->read_byte = labpc_inb; 1652 devpriv->write_byte = labpc_outb; 1653 } 1654 /* initialize board's command registers */ 1655 devpriv->write_byte(devpriv->cmd1, dev->iobase + CMD1_REG); 1656 devpriv->write_byte(devpriv->cmd2, dev->iobase + CMD2_REG); 1657 devpriv->write_byte(devpriv->cmd3, dev->iobase + CMD3_REG); 1658 devpriv->write_byte(devpriv->cmd4, dev->iobase + CMD4_REG); 1659 if (board->register_layout == labpc_1200_layout) { 1660 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); 1661 devpriv->write_byte(devpriv->cmd6, dev->iobase + CMD6_REG); 1662 } 1663 1664 if (irq) { 1665 isr_flags = 0; 1666 if (board->bustype == pci_bustype || 1667 board->bustype == pcmcia_bustype) 1668 isr_flags |= IRQF_SHARED; 1669 ret = request_irq(irq, labpc_interrupt, isr_flags, 1670 dev->board_name, dev); 1671 if (ret == 0) 1672 dev->irq = irq; 1673 } 1674 1675#ifdef CONFIG_ISA_DMA_API 1676 /* grab dma channel */ 1677 if (dma_chan > 3) { 1678 dev_err(dev->class_dev, "invalid dma channel %u\n", dma_chan); 1679 return -EINVAL; 1680 } else if (dma_chan) { 1681 unsigned long dma_flags; 1682 1683 /* allocate dma buffer */ 1684 devpriv->dma_buffer = kmalloc(dma_buffer_size, 1685 GFP_KERNEL | GFP_DMA); 1686 if (devpriv->dma_buffer == NULL) 1687 return -ENOMEM; 1688 1689 if (request_dma(dma_chan, dev->board_name)) { 1690 dev_err(dev->class_dev, 1691 "failed to allocate dma channel %u\n", 1692 dma_chan); 1693 return -EINVAL; 1694 } 1695 devpriv->dma_chan = dma_chan; 1696 dma_flags = claim_dma_lock(); 1697 disable_dma(devpriv->dma_chan); 1698 set_dma_mode(devpriv->dma_chan, DMA_MODE_READ); 1699 release_dma_lock(dma_flags); 1700 } 1701#endif 1702 1703 ret = comedi_alloc_subdevices(dev, 5); 1704 if (ret) 1705 return ret; 1706 1707 /* analog input subdevice */ 1708 s = &dev->subdevices[0]; 1709 s->type = COMEDI_SUBD_AI; 1710 s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_COMMON | SDF_DIFF; 1711 s->n_chan = 8; 1712 s->len_chanlist = 8; 1713 s->maxdata = 0x0fff; 1714 s->range_table = board->ai_range_table; 1715 s->insn_read = labpc_ai_insn_read; 1716 if (dev->irq) { 1717 dev->read_subdev = s; 1718 s->subdev_flags |= SDF_CMD_READ; 1719 s->do_cmd = labpc_ai_cmd; 1720 s->do_cmdtest = labpc_ai_cmdtest; 1721 s->cancel = labpc_cancel; 1722 } 1723 1724 /* analog output */ 1725 s = &dev->subdevices[1]; 1726 if (board->has_ao) { 1727 s->type = COMEDI_SUBD_AO; 1728 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_GROUND; 1729 s->n_chan = NUM_AO_CHAN; 1730 s->maxdata = 0x0fff; 1731 s->range_table = &range_labpc_ao; 1732 s->insn_read = labpc_ao_insn_read; 1733 s->insn_write = labpc_ao_insn_write; 1734 1735 /* initialize analog outputs to a known value */ 1736 for (i = 0; i < s->n_chan; i++) { 1737 short lsb, msb; 1738 1739 devpriv->ao_value[i] = s->maxdata / 2; 1740 lsb = devpriv->ao_value[i] & 0xff; 1741 msb = (devpriv->ao_value[i] >> 8) & 0xff; 1742 devpriv->write_byte(lsb, dev->iobase + DAC_LSB_REG(i)); 1743 devpriv->write_byte(msb, dev->iobase + DAC_MSB_REG(i)); 1744 } 1745 } else { 1746 s->type = COMEDI_SUBD_UNUSED; 1747 } 1748 1749 /* 8255 dio */ 1750 s = &dev->subdevices[2]; 1751 ret = subdev_8255_init(dev, s, 1752 (board->has_mmio) ? labpc_8255_mmio : NULL, 1753 dev->iobase + DIO_BASE_REG); 1754 if (ret) 1755 return ret; 1756 1757 /* calibration subdevices for boards that have one */ 1758 s = &dev->subdevices[3]; 1759 if (board->register_layout == labpc_1200_layout) { 1760 s->type = COMEDI_SUBD_CALIB; 1761 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; 1762 s->n_chan = 16; 1763 s->maxdata = 0xff; 1764 s->insn_read = labpc_calib_insn_read; 1765 s->insn_write = labpc_calib_insn_write; 1766 1767 for (i = 0; i < s->n_chan; i++) 1768 write_caldac(dev, i, s->maxdata / 2); 1769 } else 1770 s->type = COMEDI_SUBD_UNUSED; 1771 1772 /* EEPROM */ 1773 s = &dev->subdevices[4]; 1774 if (board->register_layout == labpc_1200_layout) { 1775 s->type = COMEDI_SUBD_MEMORY; 1776 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; 1777 s->n_chan = EEPROM_SIZE; 1778 s->maxdata = 0xff; 1779 s->insn_read = labpc_eeprom_insn_read; 1780 s->insn_write = labpc_eeprom_insn_write; 1781 1782 for (i = 0; i < s->n_chan; i++) 1783 devpriv->eeprom_data[i] = labpc_eeprom_read(dev, i); 1784 } else 1785 s->type = COMEDI_SUBD_UNUSED; 1786 1787 return 0; 1788} 1789EXPORT_SYMBOL_GPL(labpc_common_attach); 1790 1791static int labpc_attach(struct comedi_device *dev, struct comedi_devconfig *it) 1792{ 1793 const struct labpc_boardinfo *board = comedi_board(dev); 1794 struct labpc_private *devpriv; 1795 unsigned long iobase = 0; 1796 unsigned int irq = 0; 1797 unsigned int dma_chan = 0; 1798 1799 devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL); 1800 if (!devpriv) 1801 return -ENOMEM; 1802 dev->private = devpriv; 1803 1804 /* get base address, irq etc. based on bustype */ 1805 switch (board->bustype) { 1806 case isa_bustype: 1807#ifdef CONFIG_ISA_DMA_API 1808 iobase = it->options[0]; 1809 irq = it->options[1]; 1810 dma_chan = it->options[2]; 1811#else 1812 dev_err(dev->class_dev, 1813 "ni_labpc driver has not been built with ISA DMA support.\n"); 1814 return -EINVAL; 1815#endif 1816 break; 1817 case pci_bustype: 1818#ifdef CONFIG_COMEDI_PCI_DRIVERS 1819 dev_err(dev->class_dev, 1820 "manual configuration of PCI board '%s' is not supported\n", 1821 board->name); 1822 return -EINVAL; 1823#else 1824 dev_err(dev->class_dev, 1825 "ni_labpc driver has not been built with PCI support.\n"); 1826 return -EINVAL; 1827#endif 1828 break; 1829 default: 1830 dev_err(dev->class_dev, 1831 "ni_labpc: bug! couldn't determine board type\n"); 1832 return -EINVAL; 1833 break; 1834 } 1835 1836 return labpc_common_attach(dev, iobase, irq, dma_chan); 1837} 1838 1839static const struct labpc_boardinfo * 1840labpc_pci_find_boardinfo(struct pci_dev *pcidev) 1841{ 1842 unsigned int device_id = pcidev->device; 1843 unsigned int n; 1844 1845 for (n = 0; n < ARRAY_SIZE(labpc_boards); n++) { 1846 const struct labpc_boardinfo *board = &labpc_boards[n]; 1847 if (board->bustype == pci_bustype && 1848 board->device_id == device_id) 1849 return board; 1850 } 1851 return NULL; 1852} 1853 1854static int labpc_auto_attach(struct comedi_device *dev, 1855 unsigned long context_unused) 1856{ 1857 struct pci_dev *pcidev = comedi_to_pci_dev(dev); 1858 struct labpc_private *devpriv; 1859 unsigned long iobase; 1860 unsigned int irq; 1861 int ret; 1862 1863 if (!IS_ENABLED(CONFIG_COMEDI_PCI_DRIVERS)) 1864 return -ENODEV; 1865 1866 ret = comedi_pci_enable(dev); 1867 if (ret) 1868 return ret; 1869 1870 devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL); 1871 if (!devpriv) 1872 return -ENOMEM; 1873 dev->private = devpriv; 1874 1875 dev->board_ptr = labpc_pci_find_boardinfo(pcidev); 1876 if (!dev->board_ptr) 1877 return -ENODEV; 1878 devpriv->mite = mite_alloc(pcidev); 1879 if (!devpriv->mite) 1880 return -ENOMEM; 1881 ret = mite_setup(devpriv->mite); 1882 if (ret < 0) 1883 return ret; 1884 iobase = (unsigned long)devpriv->mite->daq_io_addr; 1885 irq = mite_irq(devpriv->mite); 1886 return labpc_common_attach(dev, iobase, irq, 0); 1887} 1888 1889void labpc_common_detach(struct comedi_device *dev) 1890{ 1891 const struct labpc_boardinfo *board = comedi_board(dev); 1892 struct labpc_private *devpriv = dev->private; 1893 struct comedi_subdevice *s; 1894 1895 if (!board) 1896 return; 1897 if (dev->subdevices) { 1898 s = &dev->subdevices[2]; 1899 subdev_8255_cleanup(dev, s); 1900 } 1901#ifdef CONFIG_ISA_DMA_API 1902 /* only free stuff if it has been allocated by _attach */ 1903 kfree(devpriv->dma_buffer); 1904 if (devpriv->dma_chan) 1905 free_dma(devpriv->dma_chan); 1906#endif 1907 if (dev->irq) 1908 free_irq(dev->irq, dev); 1909 if (board->bustype == isa_bustype && dev->iobase) 1910 release_region(dev->iobase, LABPC_SIZE); 1911#ifdef CONFIG_COMEDI_PCI_DRIVERS 1912 if (devpriv->mite) { 1913 mite_unsetup(devpriv->mite); 1914 mite_free(devpriv->mite); 1915 } 1916 if (board->bustype == pci_bustype) 1917 comedi_pci_disable(dev); 1918#endif 1919} 1920EXPORT_SYMBOL_GPL(labpc_common_detach); 1921 1922static struct comedi_driver labpc_driver = { 1923 .driver_name = "ni_labpc", 1924 .module = THIS_MODULE, 1925 .attach = labpc_attach, 1926 .auto_attach = labpc_auto_attach, 1927 .detach = labpc_common_detach, 1928 .num_names = ARRAY_SIZE(labpc_boards), 1929 .board_name = &labpc_boards[0].name, 1930 .offset = sizeof(struct labpc_boardinfo), 1931}; 1932 1933#ifdef CONFIG_COMEDI_PCI_DRIVERS 1934static DEFINE_PCI_DEVICE_TABLE(labpc_pci_table) = { 1935 { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x161) }, 1936 { 0 } 1937}; 1938MODULE_DEVICE_TABLE(pci, labpc_pci_table); 1939 1940static int labpc_pci_probe(struct pci_dev *dev, 1941 const struct pci_device_id *id) 1942{ 1943 return comedi_pci_auto_config(dev, &labpc_driver, id->driver_data); 1944} 1945 1946static struct pci_driver labpc_pci_driver = { 1947 .name = "ni_labpc", 1948 .id_table = labpc_pci_table, 1949 .probe = labpc_pci_probe, 1950 .remove = comedi_pci_auto_unconfig, 1951}; 1952module_comedi_pci_driver(labpc_driver, labpc_pci_driver); 1953#else 1954module_comedi_driver(labpc_driver); 1955#endif 1956 1957 1958MODULE_AUTHOR("Comedi http://www.comedi.org"); 1959MODULE_DESCRIPTION("Comedi low-level driver"); 1960MODULE_LICENSE("GPL"); 1961