ni_labpc.c revision 5e51f0db14b4a2013f4f64885191076475c5b86f
1/* 2 comedi/drivers/ni_labpc.c 3 Driver for National Instruments Lab-PC series boards and compatibles 4 Copyright (C) 2001, 2002, 2003 Frank Mori Hess <fmhess@users.sourceforge.net> 5 6 This program is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 2 of the License, or 9 (at your option) any later version. 10 11 This program is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with this program; if not, write to the Free Software 18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 20************************************************************************ 21*/ 22/* 23Driver: ni_labpc 24Description: National Instruments Lab-PC (& compatibles) 25Author: Frank Mori Hess <fmhess@users.sourceforge.net> 26Devices: [National Instruments] Lab-PC-1200 (labpc-1200), 27 Lab-PC-1200AI (labpc-1200ai), Lab-PC+ (lab-pc+), PCI-1200 (ni_labpc) 28Status: works 29 30Tested with lab-pc-1200. For the older Lab-PC+, not all input ranges 31and analog references will work, the available ranges/arefs will 32depend on how you have configured the jumpers on your board 33(see your owner's manual). 34 35Kernel-level ISA plug-and-play support for the lab-pc-1200 36boards has not 37yet been added to the driver, mainly due to the fact that 38I don't know the device id numbers. If you have one 39of these boards, 40please file a bug report at http://comedi.org/ 41so I can get the necessary information from you. 42 43The 1200 series boards have onboard calibration dacs for correcting 44analog input/output offsets and gains. The proper settings for these 45caldacs are stored on the board's eeprom. To read the caldac values 46from the eeprom and store them into a file that can be then be used by 47comedilib, use the comedi_calibrate program. 48 49Configuration options - ISA boards: 50 [0] - I/O port base address 51 [1] - IRQ (optional, required for timed or externally triggered conversions) 52 [2] - DMA channel (optional) 53 54Configuration options - PCI boards: 55 [0] - bus (optional) 56 [1] - slot (optional) 57 58The Lab-pc+ has quirky chanlist requirements 59when scanning multiple channels. Multiple channel scan 60sequence must start at highest channel, then decrement down to 61channel 0. The rest of the cards can scan down like lab-pc+ or scan 62up from channel zero. Chanlists consisting of all one channel 63are also legal, and allow you to pace conversions in bursts. 64 65*/ 66 67/* 68 69NI manuals: 70341309a (labpc-1200 register manual) 71340914a (pci-1200) 72320502b (lab-pc+) 73 74*/ 75 76#include <linux/interrupt.h> 77#include <linux/slab.h> 78#include <linux/io.h> 79#include "../comedidev.h" 80 81#include <linux/delay.h> 82#include <asm/dma.h> 83 84#include "8253.h" 85#include "8255.h" 86#include "mite.h" 87#include "comedi_fc.h" 88#include "ni_labpc.h" 89 90#define DRV_NAME "ni_labpc" 91 92/* size of io region used by board */ 93#define LABPC_SIZE 32 94/* 2 MHz master clock */ 95#define LABPC_TIMER_BASE 500 96 97/* Registers for the lab-pc+ */ 98 99/* write-only registers */ 100#define COMMAND1_REG 0x0 101#define ADC_GAIN_MASK (0x7 << 4) 102#define ADC_CHAN_BITS(x) ((x) & 0x7) 103/* enables multi channel scans */ 104#define ADC_SCAN_EN_BIT 0x80 105#define COMMAND2_REG 0x1 106/* enable pretriggering (used in conjunction with SWTRIG) */ 107#define PRETRIG_BIT 0x1 108/* enable paced conversions on external trigger */ 109#define HWTRIG_BIT 0x2 110/* enable paced conversions */ 111#define SWTRIG_BIT 0x4 112/* use two cascaded counters for pacing */ 113#define CASCADE_BIT 0x8 114#define DAC_PACED_BIT(channel) (0x40 << ((channel) & 0x1)) 115#define COMMAND3_REG 0x2 116/* enable dma transfers */ 117#define DMA_EN_BIT 0x1 118/* enable interrupts for 8255 */ 119#define DIO_INTR_EN_BIT 0x2 120/* enable dma terminal count interrupt */ 121#define DMATC_INTR_EN_BIT 0x4 122/* enable timer interrupt */ 123#define TIMER_INTR_EN_BIT 0x8 124/* enable error interrupt */ 125#define ERR_INTR_EN_BIT 0x10 126/* enable fifo not empty interrupt */ 127#define ADC_FNE_INTR_EN_BIT 0x20 128#define ADC_CONVERT_REG 0x3 129#define DAC_LSB_REG(channel) (0x4 + 2 * ((channel) & 0x1)) 130#define DAC_MSB_REG(channel) (0x5 + 2 * ((channel) & 0x1)) 131#define ADC_CLEAR_REG 0x8 132#define DMATC_CLEAR_REG 0xa 133#define TIMER_CLEAR_REG 0xc 134/* 1200 boards only */ 135#define COMMAND6_REG 0xe 136/* select ground or common-mode reference */ 137#define ADC_COMMON_BIT 0x1 138/* adc unipolar */ 139#define ADC_UNIP_BIT 0x2 140/* dac unipolar */ 141#define DAC_UNIP_BIT(channel) (0x4 << ((channel) & 0x1)) 142/* enable fifo half full interrupt */ 143#define ADC_FHF_INTR_EN_BIT 0x20 144/* enable interrupt on end of hardware count */ 145#define A1_INTR_EN_BIT 0x40 146/* scan up from channel zero instead of down to zero */ 147#define ADC_SCAN_UP_BIT 0x80 148#define COMMAND4_REG 0xf 149/* enables 'interval' scanning */ 150#define INTERVAL_SCAN_EN_BIT 0x1 151/* enables external signal on counter b1 output to trigger scan */ 152#define EXT_SCAN_EN_BIT 0x2 153/* chooses direction (output or input) for EXTCONV* line */ 154#define EXT_CONVERT_OUT_BIT 0x4 155/* chooses differential inputs for adc (in conjunction with board jumper) */ 156#define ADC_DIFF_BIT 0x8 157#define EXT_CONVERT_DISABLE_BIT 0x10 158/* 1200 boards only, calibration stuff */ 159#define COMMAND5_REG 0x1c 160/* enable eeprom for write */ 161#define EEPROM_WRITE_UNPROTECT_BIT 0x4 162/* enable dithering */ 163#define DITHER_EN_BIT 0x8 164/* load calibration dac */ 165#define CALDAC_LOAD_BIT 0x10 166/* serial clock - rising edge writes, falling edge reads */ 167#define SCLOCK_BIT 0x20 168/* serial data bit for writing to eeprom or calibration dacs */ 169#define SDATA_BIT 0x40 170/* enable eeprom for read/write */ 171#define EEPROM_EN_BIT 0x80 172#define INTERVAL_COUNT_REG 0x1e 173#define INTERVAL_LOAD_REG 0x1f 174#define INTERVAL_LOAD_BITS 0x1 175 176/* read-only registers */ 177#define STATUS1_REG 0x0 178/* data is available in fifo */ 179#define DATA_AVAIL_BIT 0x1 180/* overrun has occurred */ 181#define OVERRUN_BIT 0x2 182/* fifo overflow */ 183#define OVERFLOW_BIT 0x4 184/* timer interrupt has occurred */ 185#define TIMER_BIT 0x8 186/* dma terminal count has occurred */ 187#define DMATC_BIT 0x10 188/* external trigger has occurred */ 189#define EXT_TRIG_BIT 0x40 190/* 1200 boards only */ 191#define STATUS2_REG 0x1d 192/* programmable eeprom serial output */ 193#define EEPROM_OUT_BIT 0x1 194/* counter A1 terminal count */ 195#define A1_TC_BIT 0x2 196/* fifo not half full */ 197#define FNHF_BIT 0x4 198#define ADC_FIFO_REG 0xa 199 200#define DIO_BASE_REG 0x10 201#define COUNTER_A_BASE_REG 0x14 202#define COUNTER_A_CONTROL_REG (COUNTER_A_BASE_REG + 0x3) 203/* check modes put conversion pacer output in harmless state (a0 mode 2) */ 204#define INIT_A0_BITS 0x14 205/* put hardware conversion counter output in harmless state (a1 mode 0) */ 206#define INIT_A1_BITS 0x70 207#define COUNTER_B_BASE_REG 0x18 208 209static int labpc_cancel(struct comedi_device *dev, struct comedi_subdevice *s); 210static irqreturn_t labpc_interrupt(int irq, void *d); 211static int labpc_drain_fifo(struct comedi_device *dev); 212#ifdef CONFIG_ISA_DMA_API 213static void labpc_drain_dma(struct comedi_device *dev); 214static void handle_isa_dma(struct comedi_device *dev); 215#endif 216static void labpc_drain_dregs(struct comedi_device *dev); 217static int labpc_ai_cmdtest(struct comedi_device *dev, 218 struct comedi_subdevice *s, struct comedi_cmd *cmd); 219static int labpc_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s); 220static int labpc_ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, 221 struct comedi_insn *insn, unsigned int *data); 222static int labpc_ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s, 223 struct comedi_insn *insn, unsigned int *data); 224static int labpc_ao_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, 225 struct comedi_insn *insn, unsigned int *data); 226static int labpc_calib_read_insn(struct comedi_device *dev, 227 struct comedi_subdevice *s, 228 struct comedi_insn *insn, unsigned int *data); 229static int labpc_calib_write_insn(struct comedi_device *dev, 230 struct comedi_subdevice *s, 231 struct comedi_insn *insn, unsigned int *data); 232static int labpc_eeprom_read_insn(struct comedi_device *dev, 233 struct comedi_subdevice *s, 234 struct comedi_insn *insn, unsigned int *data); 235static int labpc_eeprom_write_insn(struct comedi_device *dev, 236 struct comedi_subdevice *s, 237 struct comedi_insn *insn, 238 unsigned int *data); 239static void labpc_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd); 240#ifdef CONFIG_ISA_DMA_API 241static unsigned int labpc_suggest_transfer_size(struct comedi_cmd cmd); 242#endif 243#ifdef CONFIG_COMEDI_PCI_DRIVERS 244static int labpc_find_device(struct comedi_device *dev, int bus, int slot); 245#endif 246static int labpc_dio_mem_callback(int dir, int port, int data, 247 unsigned long arg); 248static void labpc_serial_out(struct comedi_device *dev, unsigned int value, 249 unsigned int num_bits); 250static unsigned int labpc_serial_in(struct comedi_device *dev); 251static unsigned int labpc_eeprom_read(struct comedi_device *dev, 252 unsigned int address); 253static unsigned int labpc_eeprom_read_status(struct comedi_device *dev); 254static int labpc_eeprom_write(struct comedi_device *dev, 255 unsigned int address, 256 unsigned int value); 257static void write_caldac(struct comedi_device *dev, unsigned int channel, 258 unsigned int value); 259 260enum scan_mode { 261 MODE_SINGLE_CHAN, 262 MODE_SINGLE_CHAN_INTERVAL, 263 MODE_MULT_CHAN_UP, 264 MODE_MULT_CHAN_DOWN, 265}; 266 267/* analog input ranges */ 268#define NUM_LABPC_PLUS_AI_RANGES 16 269/* indicates unipolar ranges */ 270static const int labpc_plus_is_unipolar[NUM_LABPC_PLUS_AI_RANGES] = { 271 0, 272 0, 273 0, 274 0, 275 0, 276 0, 277 0, 278 0, 279 1, 280 1, 281 1, 282 1, 283 1, 284 1, 285 1, 286 1, 287}; 288 289/* map range index to gain bits */ 290static const int labpc_plus_ai_gain_bits[NUM_LABPC_PLUS_AI_RANGES] = { 291 0x00, 292 0x10, 293 0x20, 294 0x30, 295 0x40, 296 0x50, 297 0x60, 298 0x70, 299 0x00, 300 0x10, 301 0x20, 302 0x30, 303 0x40, 304 0x50, 305 0x60, 306 0x70, 307}; 308 309static const struct comedi_lrange range_labpc_plus_ai = { 310 NUM_LABPC_PLUS_AI_RANGES, 311 { 312 BIP_RANGE(5), 313 BIP_RANGE(4), 314 BIP_RANGE(2.5), 315 BIP_RANGE(1), 316 BIP_RANGE(0.5), 317 BIP_RANGE(0.25), 318 BIP_RANGE(0.1), 319 BIP_RANGE(0.05), 320 UNI_RANGE(10), 321 UNI_RANGE(8), 322 UNI_RANGE(5), 323 UNI_RANGE(2), 324 UNI_RANGE(1), 325 UNI_RANGE(0.5), 326 UNI_RANGE(0.2), 327 UNI_RANGE(0.1), 328 } 329}; 330 331#define NUM_LABPC_1200_AI_RANGES 14 332/* indicates unipolar ranges */ 333const int labpc_1200_is_unipolar[NUM_LABPC_1200_AI_RANGES] = { 334 0, 335 0, 336 0, 337 0, 338 0, 339 0, 340 0, 341 1, 342 1, 343 1, 344 1, 345 1, 346 1, 347 1, 348}; 349EXPORT_SYMBOL_GPL(labpc_1200_is_unipolar); 350 351/* map range index to gain bits */ 352const int labpc_1200_ai_gain_bits[NUM_LABPC_1200_AI_RANGES] = { 353 0x00, 354 0x20, 355 0x30, 356 0x40, 357 0x50, 358 0x60, 359 0x70, 360 0x00, 361 0x20, 362 0x30, 363 0x40, 364 0x50, 365 0x60, 366 0x70, 367}; 368EXPORT_SYMBOL_GPL(labpc_1200_ai_gain_bits); 369 370const struct comedi_lrange range_labpc_1200_ai = { 371 NUM_LABPC_1200_AI_RANGES, 372 { 373 BIP_RANGE(5), 374 BIP_RANGE(2.5), 375 BIP_RANGE(1), 376 BIP_RANGE(0.5), 377 BIP_RANGE(0.25), 378 BIP_RANGE(0.1), 379 BIP_RANGE(0.05), 380 UNI_RANGE(10), 381 UNI_RANGE(5), 382 UNI_RANGE(2), 383 UNI_RANGE(1), 384 UNI_RANGE(0.5), 385 UNI_RANGE(0.2), 386 UNI_RANGE(0.1), 387 } 388}; 389EXPORT_SYMBOL_GPL(range_labpc_1200_ai); 390 391/* analog output ranges */ 392#define AO_RANGE_IS_UNIPOLAR 0x1 393static const struct comedi_lrange range_labpc_ao = { 394 2, 395 { 396 BIP_RANGE(5), 397 UNI_RANGE(10), 398 } 399}; 400 401/* functions that do inb/outb and readb/writeb so we can use 402 * function pointers to decide which to use */ 403static inline unsigned int labpc_inb(unsigned long address) 404{ 405 return inb(address); 406} 407 408static inline void labpc_outb(unsigned int byte, unsigned long address) 409{ 410 outb(byte, address); 411} 412 413static inline unsigned int labpc_readb(unsigned long address) 414{ 415 return readb((void *)address); 416} 417 418static inline void labpc_writeb(unsigned int byte, unsigned long address) 419{ 420 writeb(byte, (void *)address); 421} 422 423static const struct labpc_board_struct labpc_boards[] = { 424 { 425 .name = "lab-pc-1200", 426 .ai_speed = 10000, 427 .bustype = isa_bustype, 428 .register_layout = labpc_1200_layout, 429 .has_ao = 1, 430 .ai_range_table = &range_labpc_1200_ai, 431 .ai_range_code = labpc_1200_ai_gain_bits, 432 .ai_range_is_unipolar = labpc_1200_is_unipolar, 433 .ai_scan_up = 1, 434 .memory_mapped_io = 0, 435 }, 436 { 437 .name = "lab-pc-1200ai", 438 .ai_speed = 10000, 439 .bustype = isa_bustype, 440 .register_layout = labpc_1200_layout, 441 .has_ao = 0, 442 .ai_range_table = &range_labpc_1200_ai, 443 .ai_range_code = labpc_1200_ai_gain_bits, 444 .ai_range_is_unipolar = labpc_1200_is_unipolar, 445 .ai_scan_up = 1, 446 .memory_mapped_io = 0, 447 }, 448 { 449 .name = "lab-pc+", 450 .ai_speed = 12000, 451 .bustype = isa_bustype, 452 .register_layout = labpc_plus_layout, 453 .has_ao = 1, 454 .ai_range_table = &range_labpc_plus_ai, 455 .ai_range_code = labpc_plus_ai_gain_bits, 456 .ai_range_is_unipolar = labpc_plus_is_unipolar, 457 .ai_scan_up = 0, 458 .memory_mapped_io = 0, 459 }, 460#ifdef CONFIG_COMEDI_PCI_DRIVERS 461 { 462 .name = "pci-1200", 463 .device_id = 0x161, 464 .ai_speed = 10000, 465 .bustype = pci_bustype, 466 .register_layout = labpc_1200_layout, 467 .has_ao = 1, 468 .ai_range_table = &range_labpc_1200_ai, 469 .ai_range_code = labpc_1200_ai_gain_bits, 470 .ai_range_is_unipolar = labpc_1200_is_unipolar, 471 .ai_scan_up = 1, 472 .memory_mapped_io = 1, 473 }, 474/* dummy entry so pci board works when comedi_config is passed driver name */ 475 { 476 .name = DRV_NAME, 477 .bustype = pci_bustype, 478 }, 479#endif 480}; 481 482/* 483 * Useful for shorthand access to the particular board structure 484 */ 485#define thisboard ((struct labpc_board_struct *)dev->board_ptr) 486 487/* size in bytes of dma buffer */ 488static const int dma_buffer_size = 0xff00; 489/* 2 bytes per sample */ 490static const int sample_size = 2; 491 492#define devpriv ((struct labpc_private *)dev->private) 493 494static inline int labpc_counter_load(struct comedi_device *dev, 495 unsigned long base_address, 496 unsigned int counter_number, 497 unsigned int count, unsigned int mode) 498{ 499 if (thisboard->memory_mapped_io) 500 return i8254_mm_load((void *)base_address, 0, counter_number, 501 count, mode); 502 else 503 return i8254_load(base_address, 0, counter_number, count, mode); 504} 505 506int labpc_common_attach(struct comedi_device *dev, unsigned long iobase, 507 unsigned int irq, unsigned int dma_chan) 508{ 509 struct comedi_subdevice *s; 510 int i; 511 unsigned long isr_flags; 512#ifdef CONFIG_ISA_DMA_API 513 unsigned long dma_flags; 514#endif 515 short lsb, msb; 516 int ret; 517 518 dev_info(dev->class_dev, "ni_labpc: %s\n", thisboard->name); 519 if (iobase == 0) { 520 dev_err(dev->class_dev, "io base address is zero!\n"); 521 return -EINVAL; 522 } 523 /* request io regions for isa boards */ 524 if (thisboard->bustype == isa_bustype) { 525 /* check if io addresses are available */ 526 if (!request_region(iobase, LABPC_SIZE, DRV_NAME)) { 527 dev_err(dev->class_dev, "I/O port conflict\n"); 528 return -EIO; 529 } 530 } 531 dev->iobase = iobase; 532 533 if (thisboard->memory_mapped_io) { 534 devpriv->read_byte = labpc_readb; 535 devpriv->write_byte = labpc_writeb; 536 } else { 537 devpriv->read_byte = labpc_inb; 538 devpriv->write_byte = labpc_outb; 539 } 540 /* initialize board's command registers */ 541 devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG); 542 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG); 543 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG); 544 devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG); 545 if (thisboard->register_layout == labpc_1200_layout) { 546 devpriv->write_byte(devpriv->command5_bits, 547 dev->iobase + COMMAND5_REG); 548 devpriv->write_byte(devpriv->command6_bits, 549 dev->iobase + COMMAND6_REG); 550 } 551 552 /* grab our IRQ */ 553 if (irq) { 554 isr_flags = 0; 555 if (thisboard->bustype == pci_bustype 556 || thisboard->bustype == pcmcia_bustype) 557 isr_flags |= IRQF_SHARED; 558 if (request_irq(irq, labpc_interrupt, isr_flags, 559 DRV_NAME, dev)) { 560 dev_err(dev->class_dev, "unable to allocate irq %u\n", 561 irq); 562 return -EINVAL; 563 } 564 } 565 dev->irq = irq; 566 567#ifdef CONFIG_ISA_DMA_API 568 /* grab dma channel */ 569 if (dma_chan > 3) { 570 dev_err(dev->class_dev, "invalid dma channel %u\n", dma_chan); 571 return -EINVAL; 572 } else if (dma_chan) { 573 /* allocate dma buffer */ 574 devpriv->dma_buffer = 575 kmalloc(dma_buffer_size, GFP_KERNEL | GFP_DMA); 576 if (devpriv->dma_buffer == NULL) { 577 dev_err(dev->class_dev, 578 "failed to allocate dma buffer\n"); 579 return -ENOMEM; 580 } 581 if (request_dma(dma_chan, DRV_NAME)) { 582 dev_err(dev->class_dev, 583 "failed to allocate dma channel %u\n", 584 dma_chan); 585 return -EINVAL; 586 } 587 devpriv->dma_chan = dma_chan; 588 dma_flags = claim_dma_lock(); 589 disable_dma(devpriv->dma_chan); 590 set_dma_mode(devpriv->dma_chan, DMA_MODE_READ); 591 release_dma_lock(dma_flags); 592 } 593#endif 594 595 dev->board_name = thisboard->name; 596 597 ret = comedi_alloc_subdevices(dev, 5); 598 if (ret) 599 return ret; 600 601 /* analog input subdevice */ 602 s = &dev->subdevices[0]; 603 dev->read_subdev = s; 604 s->type = COMEDI_SUBD_AI; 605 s->subdev_flags = 606 SDF_READABLE | SDF_GROUND | SDF_COMMON | SDF_DIFF | SDF_CMD_READ; 607 s->n_chan = 8; 608 s->len_chanlist = 8; 609 s->maxdata = (1 << 12) - 1; /* 12 bit resolution */ 610 s->range_table = thisboard->ai_range_table; 611 s->do_cmd = labpc_ai_cmd; 612 s->do_cmdtest = labpc_ai_cmdtest; 613 s->insn_read = labpc_ai_rinsn; 614 s->cancel = labpc_cancel; 615 616 /* analog output */ 617 s = &dev->subdevices[1]; 618 if (thisboard->has_ao) { 619 /* 620 * Could provide command support, except it only has a 621 * one sample hardware buffer for analog output and no 622 * underrun flag. 623 */ 624 s->type = COMEDI_SUBD_AO; 625 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_GROUND; 626 s->n_chan = NUM_AO_CHAN; 627 s->maxdata = (1 << 12) - 1; /* 12 bit resolution */ 628 s->range_table = &range_labpc_ao; 629 s->insn_read = labpc_ao_rinsn; 630 s->insn_write = labpc_ao_winsn; 631 /* initialize analog outputs to a known value */ 632 for (i = 0; i < s->n_chan; i++) { 633 devpriv->ao_value[i] = s->maxdata / 2; 634 lsb = devpriv->ao_value[i] & 0xff; 635 msb = (devpriv->ao_value[i] >> 8) & 0xff; 636 devpriv->write_byte(lsb, dev->iobase + DAC_LSB_REG(i)); 637 devpriv->write_byte(msb, dev->iobase + DAC_MSB_REG(i)); 638 } 639 } else { 640 s->type = COMEDI_SUBD_UNUSED; 641 } 642 643 /* 8255 dio */ 644 s = &dev->subdevices[2]; 645 /* if board uses io memory we have to give a custom callback 646 * function to the 8255 driver */ 647 if (thisboard->memory_mapped_io) 648 subdev_8255_init(dev, s, labpc_dio_mem_callback, 649 (unsigned long)(dev->iobase + DIO_BASE_REG)); 650 else 651 subdev_8255_init(dev, s, NULL, dev->iobase + DIO_BASE_REG); 652 653 /* calibration subdevices for boards that have one */ 654 s = &dev->subdevices[3]; 655 if (thisboard->register_layout == labpc_1200_layout) { 656 s->type = COMEDI_SUBD_CALIB; 657 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; 658 s->n_chan = 16; 659 s->maxdata = 0xff; 660 s->insn_read = labpc_calib_read_insn; 661 s->insn_write = labpc_calib_write_insn; 662 663 for (i = 0; i < s->n_chan; i++) 664 write_caldac(dev, i, s->maxdata / 2); 665 } else 666 s->type = COMEDI_SUBD_UNUSED; 667 668 /* EEPROM */ 669 s = &dev->subdevices[4]; 670 if (thisboard->register_layout == labpc_1200_layout) { 671 s->type = COMEDI_SUBD_MEMORY; 672 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; 673 s->n_chan = EEPROM_SIZE; 674 s->maxdata = 0xff; 675 s->insn_read = labpc_eeprom_read_insn; 676 s->insn_write = labpc_eeprom_write_insn; 677 678 for (i = 0; i < EEPROM_SIZE; i++) 679 devpriv->eeprom_data[i] = labpc_eeprom_read(dev, i); 680 } else 681 s->type = COMEDI_SUBD_UNUSED; 682 683 return 0; 684} 685EXPORT_SYMBOL_GPL(labpc_common_attach); 686 687static int labpc_attach(struct comedi_device *dev, struct comedi_devconfig *it) 688{ 689 unsigned long iobase = 0; 690 unsigned int irq = 0; 691 unsigned int dma_chan = 0; 692#ifdef CONFIG_COMEDI_PCI_DRIVERS 693 int retval; 694#endif 695 696 /* allocate and initialize dev->private */ 697 if (alloc_private(dev, sizeof(struct labpc_private)) < 0) 698 return -ENOMEM; 699 700 /* get base address, irq etc. based on bustype */ 701 switch (thisboard->bustype) { 702 case isa_bustype: 703#ifdef CONFIG_ISA_DMA_API 704 iobase = it->options[0]; 705 irq = it->options[1]; 706 dma_chan = it->options[2]; 707#else 708 dev_err(dev->class_dev, 709 "ni_labpc driver has not been built with ISA DMA support.\n"); 710 return -EINVAL; 711#endif 712 break; 713 case pci_bustype: 714#ifdef CONFIG_COMEDI_PCI_DRIVERS 715 retval = labpc_find_device(dev, it->options[0], it->options[1]); 716 if (retval < 0) 717 return retval; 718 retval = mite_setup(devpriv->mite); 719 if (retval < 0) 720 return retval; 721 iobase = (unsigned long)devpriv->mite->daq_io_addr; 722 irq = mite_irq(devpriv->mite); 723#else 724 dev_err(dev->class_dev, 725 "ni_labpc driver has not been built with PCI support.\n"); 726 return -EINVAL; 727#endif 728 break; 729 default: 730 dev_err(dev->class_dev, 731 "ni_labpc: bug! couldn't determine board type\n"); 732 return -EINVAL; 733 break; 734 } 735 736 return labpc_common_attach(dev, iobase, irq, dma_chan); 737} 738 739/* adapted from ni_pcimio for finding mite based boards (pc-1200) */ 740#ifdef CONFIG_COMEDI_PCI_DRIVERS 741static int labpc_find_device(struct comedi_device *dev, int bus, int slot) 742{ 743 struct mite_struct *mite; 744 int i; 745 for (mite = mite_devices; mite; mite = mite->next) { 746 if (mite->used) 747 continue; 748/* if bus/slot are specified then make sure we have the right bus/slot */ 749 if (bus || slot) { 750 if (bus != mite->pcidev->bus->number 751 || slot != PCI_SLOT(mite->pcidev->devfn)) 752 continue; 753 } 754 for (i = 0; i < ARRAY_SIZE(labpc_boards); i++) { 755 if (labpc_boards[i].bustype != pci_bustype) 756 continue; 757 if (mite_device_id(mite) == labpc_boards[i].device_id) { 758 devpriv->mite = mite; 759/* fixup board pointer, in case we were using the dummy "ni_labpc" entry */ 760 dev->board_ptr = &labpc_boards[i]; 761 return 0; 762 } 763 } 764 } 765 dev_err(dev->class_dev, "no device found\n"); 766 mite_list_devices(); 767 return -EIO; 768} 769#endif 770 771void labpc_common_detach(struct comedi_device *dev) 772{ 773 struct comedi_subdevice *s; 774 775 if (dev->subdevices) { 776 s = &dev->subdevices[2]; 777 subdev_8255_cleanup(dev, s); 778 } 779#ifdef CONFIG_ISA_DMA_API 780 /* only free stuff if it has been allocated by _attach */ 781 kfree(devpriv->dma_buffer); 782 if (devpriv->dma_chan) 783 free_dma(devpriv->dma_chan); 784#endif 785 if (dev->irq) 786 free_irq(dev->irq, dev); 787 if (thisboard->bustype == isa_bustype && dev->iobase) 788 release_region(dev->iobase, LABPC_SIZE); 789#ifdef CONFIG_COMEDI_PCI_DRIVERS 790 if (devpriv->mite) 791 mite_unsetup(devpriv->mite); 792#endif 793}; 794EXPORT_SYMBOL_GPL(labpc_common_detach); 795 796static void labpc_clear_adc_fifo(const struct comedi_device *dev) 797{ 798 devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG); 799 devpriv->read_byte(dev->iobase + ADC_FIFO_REG); 800 devpriv->read_byte(dev->iobase + ADC_FIFO_REG); 801} 802 803static int labpc_cancel(struct comedi_device *dev, struct comedi_subdevice *s) 804{ 805 unsigned long flags; 806 807 spin_lock_irqsave(&dev->spinlock, flags); 808 devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT; 809 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG); 810 spin_unlock_irqrestore(&dev->spinlock, flags); 811 812 devpriv->command3_bits = 0; 813 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG); 814 815 return 0; 816} 817 818static enum scan_mode labpc_ai_scan_mode(const struct comedi_cmd *cmd) 819{ 820 if (cmd->chanlist_len == 1) 821 return MODE_SINGLE_CHAN; 822 823 /* chanlist may be NULL during cmdtest. */ 824 if (cmd->chanlist == NULL) 825 return MODE_MULT_CHAN_UP; 826 827 if (CR_CHAN(cmd->chanlist[0]) == CR_CHAN(cmd->chanlist[1])) 828 return MODE_SINGLE_CHAN_INTERVAL; 829 830 if (CR_CHAN(cmd->chanlist[0]) < CR_CHAN(cmd->chanlist[1])) 831 return MODE_MULT_CHAN_UP; 832 833 if (CR_CHAN(cmd->chanlist[0]) > CR_CHAN(cmd->chanlist[1])) 834 return MODE_MULT_CHAN_DOWN; 835 836 pr_err("ni_labpc: bug! cannot determine AI scan mode\n"); 837 return 0; 838} 839 840static int labpc_ai_chanlist_invalid(const struct comedi_device *dev, 841 const struct comedi_cmd *cmd) 842{ 843 int mode, channel, range, aref, i; 844 845 if (cmd->chanlist == NULL) 846 return 0; 847 848 mode = labpc_ai_scan_mode(cmd); 849 850 if (mode == MODE_SINGLE_CHAN) 851 return 0; 852 853 if (mode == MODE_SINGLE_CHAN_INTERVAL) { 854 if (cmd->chanlist_len > 0xff) { 855 comedi_error(dev, 856 "ni_labpc: chanlist too long for single channel interval mode\n"); 857 return 1; 858 } 859 } 860 861 channel = CR_CHAN(cmd->chanlist[0]); 862 range = CR_RANGE(cmd->chanlist[0]); 863 aref = CR_AREF(cmd->chanlist[0]); 864 865 for (i = 0; i < cmd->chanlist_len; i++) { 866 867 switch (mode) { 868 case MODE_SINGLE_CHAN_INTERVAL: 869 if (CR_CHAN(cmd->chanlist[i]) != channel) { 870 comedi_error(dev, 871 "channel scanning order specified in chanlist is not supported by hardware.\n"); 872 return 1; 873 } 874 break; 875 case MODE_MULT_CHAN_UP: 876 if (CR_CHAN(cmd->chanlist[i]) != i) { 877 comedi_error(dev, 878 "channel scanning order specified in chanlist is not supported by hardware.\n"); 879 return 1; 880 } 881 break; 882 case MODE_MULT_CHAN_DOWN: 883 if (CR_CHAN(cmd->chanlist[i]) != 884 cmd->chanlist_len - i - 1) { 885 comedi_error(dev, 886 "channel scanning order specified in chanlist is not supported by hardware.\n"); 887 return 1; 888 } 889 break; 890 default: 891 dev_err(dev->class_dev, 892 "ni_labpc: bug! in chanlist check\n"); 893 return 1; 894 break; 895 } 896 897 if (CR_RANGE(cmd->chanlist[i]) != range) { 898 comedi_error(dev, 899 "entries in chanlist must all have the same range\n"); 900 return 1; 901 } 902 903 if (CR_AREF(cmd->chanlist[i]) != aref) { 904 comedi_error(dev, 905 "entries in chanlist must all have the same reference\n"); 906 return 1; 907 } 908 } 909 910 return 0; 911} 912 913static int labpc_use_continuous_mode(const struct comedi_cmd *cmd) 914{ 915 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN) 916 return 1; 917 918 if (cmd->scan_begin_src == TRIG_FOLLOW) 919 return 1; 920 921 return 0; 922} 923 924static unsigned int labpc_ai_convert_period(const struct comedi_cmd *cmd) 925{ 926 if (cmd->convert_src != TRIG_TIMER) 927 return 0; 928 929 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN && 930 cmd->scan_begin_src == TRIG_TIMER) 931 return cmd->scan_begin_arg; 932 933 return cmd->convert_arg; 934} 935 936static void labpc_set_ai_convert_period(struct comedi_cmd *cmd, unsigned int ns) 937{ 938 if (cmd->convert_src != TRIG_TIMER) 939 return; 940 941 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN && 942 cmd->scan_begin_src == TRIG_TIMER) { 943 cmd->scan_begin_arg = ns; 944 if (cmd->convert_arg > cmd->scan_begin_arg) 945 cmd->convert_arg = cmd->scan_begin_arg; 946 } else 947 cmd->convert_arg = ns; 948} 949 950static unsigned int labpc_ai_scan_period(const struct comedi_cmd *cmd) 951{ 952 if (cmd->scan_begin_src != TRIG_TIMER) 953 return 0; 954 955 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN && 956 cmd->convert_src == TRIG_TIMER) 957 return 0; 958 959 return cmd->scan_begin_arg; 960} 961 962static void labpc_set_ai_scan_period(struct comedi_cmd *cmd, unsigned int ns) 963{ 964 if (cmd->scan_begin_src != TRIG_TIMER) 965 return; 966 967 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN && 968 cmd->convert_src == TRIG_TIMER) 969 return; 970 971 cmd->scan_begin_arg = ns; 972} 973 974static int labpc_ai_cmdtest(struct comedi_device *dev, 975 struct comedi_subdevice *s, struct comedi_cmd *cmd) 976{ 977 int err = 0; 978 int tmp, tmp2; 979 int stop_mask; 980 981 /* step 1: make sure trigger sources are trivially valid */ 982 983 tmp = cmd->start_src; 984 cmd->start_src &= TRIG_NOW | TRIG_EXT; 985 if (!cmd->start_src || tmp != cmd->start_src) 986 err++; 987 988 tmp = cmd->scan_begin_src; 989 cmd->scan_begin_src &= TRIG_TIMER | TRIG_FOLLOW | TRIG_EXT; 990 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src) 991 err++; 992 993 tmp = cmd->convert_src; 994 cmd->convert_src &= TRIG_TIMER | TRIG_EXT; 995 if (!cmd->convert_src || tmp != cmd->convert_src) 996 err++; 997 998 tmp = cmd->scan_end_src; 999 cmd->scan_end_src &= TRIG_COUNT; 1000 if (!cmd->scan_end_src || tmp != cmd->scan_end_src) 1001 err++; 1002 1003 tmp = cmd->stop_src; 1004 stop_mask = TRIG_COUNT | TRIG_NONE; 1005 if (thisboard->register_layout == labpc_1200_layout) 1006 stop_mask |= TRIG_EXT; 1007 cmd->stop_src &= stop_mask; 1008 if (!cmd->stop_src || tmp != cmd->stop_src) 1009 err++; 1010 1011 if (err) 1012 return 1; 1013 1014 /* step 2: make sure trigger sources are unique and mutually compatible */ 1015 1016 if (cmd->start_src != TRIG_NOW && cmd->start_src != TRIG_EXT) 1017 err++; 1018 if (cmd->scan_begin_src != TRIG_TIMER && 1019 cmd->scan_begin_src != TRIG_FOLLOW && 1020 cmd->scan_begin_src != TRIG_EXT) 1021 err++; 1022 if (cmd->convert_src != TRIG_TIMER && cmd->convert_src != TRIG_EXT) 1023 err++; 1024 if (cmd->stop_src != TRIG_COUNT && 1025 cmd->stop_src != TRIG_EXT && cmd->stop_src != TRIG_NONE) 1026 err++; 1027 1028 /* can't have external stop and start triggers at once */ 1029 if (cmd->start_src == TRIG_EXT && cmd->stop_src == TRIG_EXT) 1030 err++; 1031 1032 if (err) 1033 return 2; 1034 1035 /* step 3: make sure arguments are trivially compatible */ 1036 1037 if (cmd->start_arg == TRIG_NOW && cmd->start_arg != 0) { 1038 cmd->start_arg = 0; 1039 err++; 1040 } 1041 1042 if (!cmd->chanlist_len) 1043 err++; 1044 1045 if (cmd->scan_end_arg != cmd->chanlist_len) { 1046 cmd->scan_end_arg = cmd->chanlist_len; 1047 err++; 1048 } 1049 1050 if (cmd->convert_src == TRIG_TIMER) { 1051 if (cmd->convert_arg < thisboard->ai_speed) { 1052 cmd->convert_arg = thisboard->ai_speed; 1053 err++; 1054 } 1055 } 1056 /* make sure scan timing is not too fast */ 1057 if (cmd->scan_begin_src == TRIG_TIMER) { 1058 if (cmd->convert_src == TRIG_TIMER && 1059 cmd->scan_begin_arg < 1060 cmd->convert_arg * cmd->chanlist_len) { 1061 cmd->scan_begin_arg = 1062 cmd->convert_arg * cmd->chanlist_len; 1063 err++; 1064 } 1065 if (cmd->scan_begin_arg < 1066 thisboard->ai_speed * cmd->chanlist_len) { 1067 cmd->scan_begin_arg = 1068 thisboard->ai_speed * cmd->chanlist_len; 1069 err++; 1070 } 1071 } 1072 /* stop source */ 1073 switch (cmd->stop_src) { 1074 case TRIG_COUNT: 1075 if (!cmd->stop_arg) { 1076 cmd->stop_arg = 1; 1077 err++; 1078 } 1079 break; 1080 case TRIG_NONE: 1081 if (cmd->stop_arg != 0) { 1082 cmd->stop_arg = 0; 1083 err++; 1084 } 1085 break; 1086 /* 1087 * TRIG_EXT doesn't care since it doesn't 1088 * trigger off a numbered channel 1089 */ 1090 default: 1091 break; 1092 } 1093 1094 if (err) 1095 return 3; 1096 1097 /* step 4: fix up any arguments */ 1098 1099 tmp = cmd->convert_arg; 1100 tmp2 = cmd->scan_begin_arg; 1101 labpc_adc_timing(dev, cmd); 1102 if (tmp != cmd->convert_arg || tmp2 != cmd->scan_begin_arg) 1103 err++; 1104 1105 if (err) 1106 return 4; 1107 1108 if (labpc_ai_chanlist_invalid(dev, cmd)) 1109 return 5; 1110 1111 return 0; 1112} 1113 1114static int labpc_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) 1115{ 1116 int channel, range, aref; 1117#ifdef CONFIG_ISA_DMA_API 1118 unsigned long irq_flags; 1119#endif 1120 int ret; 1121 struct comedi_async *async = s->async; 1122 struct comedi_cmd *cmd = &async->cmd; 1123 enum transfer_type xfer; 1124 unsigned long flags; 1125 1126 if (!dev->irq) { 1127 comedi_error(dev, "no irq assigned, cannot perform command"); 1128 return -1; 1129 } 1130 1131 range = CR_RANGE(cmd->chanlist[0]); 1132 aref = CR_AREF(cmd->chanlist[0]); 1133 1134 /* make sure board is disabled before setting up acquisition */ 1135 spin_lock_irqsave(&dev->spinlock, flags); 1136 devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT; 1137 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG); 1138 spin_unlock_irqrestore(&dev->spinlock, flags); 1139 1140 devpriv->command3_bits = 0; 1141 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG); 1142 1143 /* initialize software conversion count */ 1144 if (cmd->stop_src == TRIG_COUNT) 1145 devpriv->count = cmd->stop_arg * cmd->chanlist_len; 1146 1147 /* setup hardware conversion counter */ 1148 if (cmd->stop_src == TRIG_EXT) { 1149 /* 1150 * load counter a1 with count of 3 1151 * (pc+ manual says this is minimum allowed) using mode 0 1152 */ 1153 ret = labpc_counter_load(dev, dev->iobase + COUNTER_A_BASE_REG, 1154 1, 3, 0); 1155 if (ret < 0) { 1156 comedi_error(dev, "error loading counter a1"); 1157 return -1; 1158 } 1159 } else /* 1160 * otherwise, just put a1 in mode 0 1161 * with no count to set its output low 1162 */ 1163 devpriv->write_byte(INIT_A1_BITS, 1164 dev->iobase + COUNTER_A_CONTROL_REG); 1165 1166#ifdef CONFIG_ISA_DMA_API 1167 /* figure out what method we will use to transfer data */ 1168 if (devpriv->dma_chan && /* need a dma channel allocated */ 1169 /* 1170 * dma unsafe at RT priority, 1171 * and too much setup time for TRIG_WAKE_EOS for 1172 */ 1173 (cmd->flags & (TRIG_WAKE_EOS | TRIG_RT)) == 0 && 1174 /* only available on the isa boards */ 1175 thisboard->bustype == isa_bustype) { 1176 xfer = isa_dma_transfer; 1177 /* pc-plus has no fifo-half full interrupt */ 1178 } else 1179#endif 1180 if (thisboard->register_layout == labpc_1200_layout && 1181 /* wake-end-of-scan should interrupt on fifo not empty */ 1182 (cmd->flags & TRIG_WAKE_EOS) == 0 && 1183 /* make sure we are taking more than just a few points */ 1184 (cmd->stop_src != TRIG_COUNT || devpriv->count > 256)) { 1185 xfer = fifo_half_full_transfer; 1186 } else 1187 xfer = fifo_not_empty_transfer; 1188 devpriv->current_transfer = xfer; 1189 1190 /* setup command6 register for 1200 boards */ 1191 if (thisboard->register_layout == labpc_1200_layout) { 1192 /* reference inputs to ground or common? */ 1193 if (aref != AREF_GROUND) 1194 devpriv->command6_bits |= ADC_COMMON_BIT; 1195 else 1196 devpriv->command6_bits &= ~ADC_COMMON_BIT; 1197 /* bipolar or unipolar range? */ 1198 if (thisboard->ai_range_is_unipolar[range]) 1199 devpriv->command6_bits |= ADC_UNIP_BIT; 1200 else 1201 devpriv->command6_bits &= ~ADC_UNIP_BIT; 1202 /* interrupt on fifo half full? */ 1203 if (xfer == fifo_half_full_transfer) 1204 devpriv->command6_bits |= ADC_FHF_INTR_EN_BIT; 1205 else 1206 devpriv->command6_bits &= ~ADC_FHF_INTR_EN_BIT; 1207 /* enable interrupt on counter a1 terminal count? */ 1208 if (cmd->stop_src == TRIG_EXT) 1209 devpriv->command6_bits |= A1_INTR_EN_BIT; 1210 else 1211 devpriv->command6_bits &= ~A1_INTR_EN_BIT; 1212 /* are we scanning up or down through channels? */ 1213 if (labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_UP) 1214 devpriv->command6_bits |= ADC_SCAN_UP_BIT; 1215 else 1216 devpriv->command6_bits &= ~ADC_SCAN_UP_BIT; 1217 /* write to register */ 1218 devpriv->write_byte(devpriv->command6_bits, 1219 dev->iobase + COMMAND6_REG); 1220 } 1221 1222 /* setup channel list, etc (command1 register) */ 1223 devpriv->command1_bits = 0; 1224 if (labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_UP) 1225 channel = CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1]); 1226 else 1227 channel = CR_CHAN(cmd->chanlist[0]); 1228 /* munge channel bits for differential / scan disabled mode */ 1229 if (labpc_ai_scan_mode(cmd) != MODE_SINGLE_CHAN && aref == AREF_DIFF) 1230 channel *= 2; 1231 devpriv->command1_bits |= ADC_CHAN_BITS(channel); 1232 devpriv->command1_bits |= thisboard->ai_range_code[range]; 1233 devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG); 1234 /* manual says to set scan enable bit on second pass */ 1235 if (labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_UP || 1236 labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_DOWN) { 1237 devpriv->command1_bits |= ADC_SCAN_EN_BIT; 1238 /* need a brief delay before enabling scan, or scan 1239 * list will get screwed when you switch 1240 * between scan up to scan down mode - dunno why */ 1241 udelay(1); 1242 devpriv->write_byte(devpriv->command1_bits, 1243 dev->iobase + COMMAND1_REG); 1244 } 1245 /* setup any external triggering/pacing (command4 register) */ 1246 devpriv->command4_bits = 0; 1247 if (cmd->convert_src != TRIG_EXT) 1248 devpriv->command4_bits |= EXT_CONVERT_DISABLE_BIT; 1249 /* XXX should discard first scan when using interval scanning 1250 * since manual says it is not synced with scan clock */ 1251 if (labpc_use_continuous_mode(cmd) == 0) { 1252 devpriv->command4_bits |= INTERVAL_SCAN_EN_BIT; 1253 if (cmd->scan_begin_src == TRIG_EXT) 1254 devpriv->command4_bits |= EXT_SCAN_EN_BIT; 1255 } 1256 /* single-ended/differential */ 1257 if (aref == AREF_DIFF) 1258 devpriv->command4_bits |= ADC_DIFF_BIT; 1259 devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG); 1260 1261 devpriv->write_byte(cmd->chanlist_len, 1262 dev->iobase + INTERVAL_COUNT_REG); 1263 /* load count */ 1264 devpriv->write_byte(INTERVAL_LOAD_BITS, 1265 dev->iobase + INTERVAL_LOAD_REG); 1266 1267 if (cmd->convert_src == TRIG_TIMER || cmd->scan_begin_src == TRIG_TIMER) { 1268 /* set up pacing */ 1269 labpc_adc_timing(dev, cmd); 1270 /* load counter b0 in mode 3 */ 1271 ret = labpc_counter_load(dev, dev->iobase + COUNTER_B_BASE_REG, 1272 0, devpriv->divisor_b0, 3); 1273 if (ret < 0) { 1274 comedi_error(dev, "error loading counter b0"); 1275 return -1; 1276 } 1277 } 1278 /* set up conversion pacing */ 1279 if (labpc_ai_convert_period(cmd)) { 1280 /* load counter a0 in mode 2 */ 1281 ret = labpc_counter_load(dev, dev->iobase + COUNTER_A_BASE_REG, 1282 0, devpriv->divisor_a0, 2); 1283 if (ret < 0) { 1284 comedi_error(dev, "error loading counter a0"); 1285 return -1; 1286 } 1287 } else 1288 devpriv->write_byte(INIT_A0_BITS, 1289 dev->iobase + COUNTER_A_CONTROL_REG); 1290 1291 /* set up scan pacing */ 1292 if (labpc_ai_scan_period(cmd)) { 1293 /* load counter b1 in mode 2 */ 1294 ret = labpc_counter_load(dev, dev->iobase + COUNTER_B_BASE_REG, 1295 1, devpriv->divisor_b1, 2); 1296 if (ret < 0) { 1297 comedi_error(dev, "error loading counter b1"); 1298 return -1; 1299 } 1300 } 1301 1302 labpc_clear_adc_fifo(dev); 1303 1304#ifdef CONFIG_ISA_DMA_API 1305 /* set up dma transfer */ 1306 if (xfer == isa_dma_transfer) { 1307 irq_flags = claim_dma_lock(); 1308 disable_dma(devpriv->dma_chan); 1309 /* clear flip-flop to make sure 2-byte registers for 1310 * count and address get set correctly */ 1311 clear_dma_ff(devpriv->dma_chan); 1312 set_dma_addr(devpriv->dma_chan, 1313 virt_to_bus(devpriv->dma_buffer)); 1314 /* set appropriate size of transfer */ 1315 devpriv->dma_transfer_size = labpc_suggest_transfer_size(*cmd); 1316 if (cmd->stop_src == TRIG_COUNT && 1317 devpriv->count * sample_size < devpriv->dma_transfer_size) { 1318 devpriv->dma_transfer_size = 1319 devpriv->count * sample_size; 1320 } 1321 set_dma_count(devpriv->dma_chan, devpriv->dma_transfer_size); 1322 enable_dma(devpriv->dma_chan); 1323 release_dma_lock(irq_flags); 1324 /* enable board's dma */ 1325 devpriv->command3_bits |= DMA_EN_BIT | DMATC_INTR_EN_BIT; 1326 } else 1327 devpriv->command3_bits &= ~DMA_EN_BIT & ~DMATC_INTR_EN_BIT; 1328#endif 1329 1330 /* enable error interrupts */ 1331 devpriv->command3_bits |= ERR_INTR_EN_BIT; 1332 /* enable fifo not empty interrupt? */ 1333 if (xfer == fifo_not_empty_transfer) 1334 devpriv->command3_bits |= ADC_FNE_INTR_EN_BIT; 1335 else 1336 devpriv->command3_bits &= ~ADC_FNE_INTR_EN_BIT; 1337 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG); 1338 1339 /* startup acquisition */ 1340 1341 /* command2 reg */ 1342 /* use 2 cascaded counters for pacing */ 1343 spin_lock_irqsave(&dev->spinlock, flags); 1344 devpriv->command2_bits |= CASCADE_BIT; 1345 switch (cmd->start_src) { 1346 case TRIG_EXT: 1347 devpriv->command2_bits |= HWTRIG_BIT; 1348 devpriv->command2_bits &= ~PRETRIG_BIT & ~SWTRIG_BIT; 1349 break; 1350 case TRIG_NOW: 1351 devpriv->command2_bits |= SWTRIG_BIT; 1352 devpriv->command2_bits &= ~PRETRIG_BIT & ~HWTRIG_BIT; 1353 break; 1354 default: 1355 comedi_error(dev, "bug with start_src"); 1356 spin_unlock_irqrestore(&dev->spinlock, flags); 1357 return -1; 1358 break; 1359 } 1360 switch (cmd->stop_src) { 1361 case TRIG_EXT: 1362 devpriv->command2_bits |= HWTRIG_BIT | PRETRIG_BIT; 1363 break; 1364 case TRIG_COUNT: 1365 case TRIG_NONE: 1366 break; 1367 default: 1368 comedi_error(dev, "bug with stop_src"); 1369 spin_unlock_irqrestore(&dev->spinlock, flags); 1370 return -1; 1371 } 1372 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG); 1373 spin_unlock_irqrestore(&dev->spinlock, flags); 1374 1375 return 0; 1376} 1377 1378/* interrupt service routine */ 1379static irqreturn_t labpc_interrupt(int irq, void *d) 1380{ 1381 struct comedi_device *dev = d; 1382 struct comedi_subdevice *s = dev->read_subdev; 1383 struct comedi_async *async; 1384 struct comedi_cmd *cmd; 1385 1386 if (dev->attached == 0) { 1387 comedi_error(dev, "premature interrupt"); 1388 return IRQ_HANDLED; 1389 } 1390 1391 async = s->async; 1392 cmd = &async->cmd; 1393 async->events = 0; 1394 1395 /* read board status */ 1396 devpriv->status1_bits = devpriv->read_byte(dev->iobase + STATUS1_REG); 1397 if (thisboard->register_layout == labpc_1200_layout) 1398 devpriv->status2_bits = 1399 devpriv->read_byte(dev->iobase + STATUS2_REG); 1400 1401 if ((devpriv->status1_bits & (DMATC_BIT | TIMER_BIT | OVERFLOW_BIT | 1402 OVERRUN_BIT | DATA_AVAIL_BIT)) == 0 1403 && (devpriv->status2_bits & A1_TC_BIT) == 0 1404 && (devpriv->status2_bits & FNHF_BIT)) { 1405 return IRQ_NONE; 1406 } 1407 1408 if (devpriv->status1_bits & OVERRUN_BIT) { 1409 /* clear error interrupt */ 1410 devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG); 1411 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA; 1412 comedi_event(dev, s); 1413 comedi_error(dev, "overrun"); 1414 return IRQ_HANDLED; 1415 } 1416 1417#ifdef CONFIG_ISA_DMA_API 1418 if (devpriv->current_transfer == isa_dma_transfer) { 1419 /* 1420 * if a dma terminal count of external stop trigger 1421 * has occurred 1422 */ 1423 if (devpriv->status1_bits & DMATC_BIT || 1424 (thisboard->register_layout == labpc_1200_layout 1425 && devpriv->status2_bits & A1_TC_BIT)) { 1426 handle_isa_dma(dev); 1427 } 1428 } else 1429#endif 1430 labpc_drain_fifo(dev); 1431 1432 if (devpriv->status1_bits & TIMER_BIT) { 1433 comedi_error(dev, "handled timer interrupt?"); 1434 /* clear it */ 1435 devpriv->write_byte(0x1, dev->iobase + TIMER_CLEAR_REG); 1436 } 1437 1438 if (devpriv->status1_bits & OVERFLOW_BIT) { 1439 /* clear error interrupt */ 1440 devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG); 1441 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA; 1442 comedi_event(dev, s); 1443 comedi_error(dev, "overflow"); 1444 return IRQ_HANDLED; 1445 } 1446 /* handle external stop trigger */ 1447 if (cmd->stop_src == TRIG_EXT) { 1448 if (devpriv->status2_bits & A1_TC_BIT) { 1449 labpc_drain_dregs(dev); 1450 labpc_cancel(dev, s); 1451 async->events |= COMEDI_CB_EOA; 1452 } 1453 } 1454 1455 /* TRIG_COUNT end of acquisition */ 1456 if (cmd->stop_src == TRIG_COUNT) { 1457 if (devpriv->count == 0) { 1458 labpc_cancel(dev, s); 1459 async->events |= COMEDI_CB_EOA; 1460 } 1461 } 1462 1463 comedi_event(dev, s); 1464 return IRQ_HANDLED; 1465} 1466 1467/* read all available samples from ai fifo */ 1468static int labpc_drain_fifo(struct comedi_device *dev) 1469{ 1470 unsigned int lsb, msb; 1471 short data; 1472 struct comedi_async *async = dev->read_subdev->async; 1473 const int timeout = 10000; 1474 unsigned int i; 1475 1476 devpriv->status1_bits = devpriv->read_byte(dev->iobase + STATUS1_REG); 1477 1478 for (i = 0; (devpriv->status1_bits & DATA_AVAIL_BIT) && i < timeout; 1479 i++) { 1480 /* quit if we have all the data we want */ 1481 if (async->cmd.stop_src == TRIG_COUNT) { 1482 if (devpriv->count == 0) 1483 break; 1484 devpriv->count--; 1485 } 1486 lsb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG); 1487 msb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG); 1488 data = (msb << 8) | lsb; 1489 cfc_write_to_buffer(dev->read_subdev, data); 1490 devpriv->status1_bits = 1491 devpriv->read_byte(dev->iobase + STATUS1_REG); 1492 } 1493 if (i == timeout) { 1494 comedi_error(dev, "ai timeout, fifo never empties"); 1495 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA; 1496 return -1; 1497 } 1498 1499 return 0; 1500} 1501 1502#ifdef CONFIG_ISA_DMA_API 1503static void labpc_drain_dma(struct comedi_device *dev) 1504{ 1505 struct comedi_subdevice *s = dev->read_subdev; 1506 struct comedi_async *async = s->async; 1507 int status; 1508 unsigned long flags; 1509 unsigned int max_points, num_points, residue, leftover; 1510 int i; 1511 1512 status = devpriv->status1_bits; 1513 1514 flags = claim_dma_lock(); 1515 disable_dma(devpriv->dma_chan); 1516 /* clear flip-flop to make sure 2-byte registers for 1517 * count and address get set correctly */ 1518 clear_dma_ff(devpriv->dma_chan); 1519 1520 /* figure out how many points to read */ 1521 max_points = devpriv->dma_transfer_size / sample_size; 1522 /* residue is the number of points left to be done on the dma 1523 * transfer. It should always be zero at this point unless 1524 * the stop_src is set to external triggering. 1525 */ 1526 residue = get_dma_residue(devpriv->dma_chan) / sample_size; 1527 num_points = max_points - residue; 1528 if (devpriv->count < num_points && async->cmd.stop_src == TRIG_COUNT) 1529 num_points = devpriv->count; 1530 1531 /* figure out how many points will be stored next time */ 1532 leftover = 0; 1533 if (async->cmd.stop_src != TRIG_COUNT) { 1534 leftover = devpriv->dma_transfer_size / sample_size; 1535 } else if (devpriv->count > num_points) { 1536 leftover = devpriv->count - num_points; 1537 if (leftover > max_points) 1538 leftover = max_points; 1539 } 1540 1541 /* write data to comedi buffer */ 1542 for (i = 0; i < num_points; i++) 1543 cfc_write_to_buffer(s, devpriv->dma_buffer[i]); 1544 1545 if (async->cmd.stop_src == TRIG_COUNT) 1546 devpriv->count -= num_points; 1547 1548 /* set address and count for next transfer */ 1549 set_dma_addr(devpriv->dma_chan, virt_to_bus(devpriv->dma_buffer)); 1550 set_dma_count(devpriv->dma_chan, leftover * sample_size); 1551 release_dma_lock(flags); 1552 1553 async->events |= COMEDI_CB_BLOCK; 1554} 1555 1556static void handle_isa_dma(struct comedi_device *dev) 1557{ 1558 labpc_drain_dma(dev); 1559 1560 enable_dma(devpriv->dma_chan); 1561 1562 /* clear dma tc interrupt */ 1563 devpriv->write_byte(0x1, dev->iobase + DMATC_CLEAR_REG); 1564} 1565#endif 1566 1567/* makes sure all data acquired by board is transferred to comedi (used 1568 * when acquisition is terminated by stop_src == TRIG_EXT). */ 1569static void labpc_drain_dregs(struct comedi_device *dev) 1570{ 1571#ifdef CONFIG_ISA_DMA_API 1572 if (devpriv->current_transfer == isa_dma_transfer) 1573 labpc_drain_dma(dev); 1574#endif 1575 1576 labpc_drain_fifo(dev); 1577} 1578 1579static int labpc_ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, 1580 struct comedi_insn *insn, unsigned int *data) 1581{ 1582 int i, n; 1583 int chan, range; 1584 int lsb, msb; 1585 int timeout = 1000; 1586 unsigned long flags; 1587 1588 /* disable timed conversions */ 1589 spin_lock_irqsave(&dev->spinlock, flags); 1590 devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT; 1591 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG); 1592 spin_unlock_irqrestore(&dev->spinlock, flags); 1593 1594 /* disable interrupt generation and dma */ 1595 devpriv->command3_bits = 0; 1596 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG); 1597 1598 /* set gain and channel */ 1599 devpriv->command1_bits = 0; 1600 chan = CR_CHAN(insn->chanspec); 1601 range = CR_RANGE(insn->chanspec); 1602 devpriv->command1_bits |= thisboard->ai_range_code[range]; 1603 /* munge channel bits for differential/scan disabled mode */ 1604 if (CR_AREF(insn->chanspec) == AREF_DIFF) 1605 chan *= 2; 1606 devpriv->command1_bits |= ADC_CHAN_BITS(chan); 1607 devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG); 1608 1609 /* setup command6 register for 1200 boards */ 1610 if (thisboard->register_layout == labpc_1200_layout) { 1611 /* reference inputs to ground or common? */ 1612 if (CR_AREF(insn->chanspec) != AREF_GROUND) 1613 devpriv->command6_bits |= ADC_COMMON_BIT; 1614 else 1615 devpriv->command6_bits &= ~ADC_COMMON_BIT; 1616 /* bipolar or unipolar range? */ 1617 if (thisboard->ai_range_is_unipolar[range]) 1618 devpriv->command6_bits |= ADC_UNIP_BIT; 1619 else 1620 devpriv->command6_bits &= ~ADC_UNIP_BIT; 1621 /* don't interrupt on fifo half full */ 1622 devpriv->command6_bits &= ~ADC_FHF_INTR_EN_BIT; 1623 /* don't enable interrupt on counter a1 terminal count? */ 1624 devpriv->command6_bits &= ~A1_INTR_EN_BIT; 1625 /* write to register */ 1626 devpriv->write_byte(devpriv->command6_bits, 1627 dev->iobase + COMMAND6_REG); 1628 } 1629 /* setup command4 register */ 1630 devpriv->command4_bits = 0; 1631 devpriv->command4_bits |= EXT_CONVERT_DISABLE_BIT; 1632 /* single-ended/differential */ 1633 if (CR_AREF(insn->chanspec) == AREF_DIFF) 1634 devpriv->command4_bits |= ADC_DIFF_BIT; 1635 devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG); 1636 1637 /* 1638 * initialize pacer counter output to make sure it doesn't 1639 * cause any problems 1640 */ 1641 devpriv->write_byte(INIT_A0_BITS, dev->iobase + COUNTER_A_CONTROL_REG); 1642 1643 labpc_clear_adc_fifo(dev); 1644 1645 for (n = 0; n < insn->n; n++) { 1646 /* trigger conversion */ 1647 devpriv->write_byte(0x1, dev->iobase + ADC_CONVERT_REG); 1648 1649 for (i = 0; i < timeout; i++) { 1650 if (devpriv->read_byte(dev->iobase + 1651 STATUS1_REG) & DATA_AVAIL_BIT) 1652 break; 1653 udelay(1); 1654 } 1655 if (i == timeout) { 1656 comedi_error(dev, "timeout"); 1657 return -ETIME; 1658 } 1659 lsb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG); 1660 msb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG); 1661 data[n] = (msb << 8) | lsb; 1662 } 1663 1664 return n; 1665} 1666 1667/* analog output insn */ 1668static int labpc_ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s, 1669 struct comedi_insn *insn, unsigned int *data) 1670{ 1671 int channel, range; 1672 unsigned long flags; 1673 int lsb, msb; 1674 1675 channel = CR_CHAN(insn->chanspec); 1676 1677 /* turn off pacing of analog output channel */ 1678 /* note: hardware bug in daqcard-1200 means pacing cannot 1679 * be independently enabled/disabled for its the two channels */ 1680 spin_lock_irqsave(&dev->spinlock, flags); 1681 devpriv->command2_bits &= ~DAC_PACED_BIT(channel); 1682 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG); 1683 spin_unlock_irqrestore(&dev->spinlock, flags); 1684 1685 /* set range */ 1686 if (thisboard->register_layout == labpc_1200_layout) { 1687 range = CR_RANGE(insn->chanspec); 1688 if (range & AO_RANGE_IS_UNIPOLAR) 1689 devpriv->command6_bits |= DAC_UNIP_BIT(channel); 1690 else 1691 devpriv->command6_bits &= ~DAC_UNIP_BIT(channel); 1692 /* write to register */ 1693 devpriv->write_byte(devpriv->command6_bits, 1694 dev->iobase + COMMAND6_REG); 1695 } 1696 /* send data */ 1697 lsb = data[0] & 0xff; 1698 msb = (data[0] >> 8) & 0xff; 1699 devpriv->write_byte(lsb, dev->iobase + DAC_LSB_REG(channel)); 1700 devpriv->write_byte(msb, dev->iobase + DAC_MSB_REG(channel)); 1701 1702 /* remember value for readback */ 1703 devpriv->ao_value[channel] = data[0]; 1704 1705 return 1; 1706} 1707 1708/* analog output readback insn */ 1709static int labpc_ao_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, 1710 struct comedi_insn *insn, unsigned int *data) 1711{ 1712 data[0] = devpriv->ao_value[CR_CHAN(insn->chanspec)]; 1713 1714 return 1; 1715} 1716 1717static int labpc_calib_read_insn(struct comedi_device *dev, 1718 struct comedi_subdevice *s, 1719 struct comedi_insn *insn, unsigned int *data) 1720{ 1721 data[0] = devpriv->caldac[CR_CHAN(insn->chanspec)]; 1722 1723 return 1; 1724} 1725 1726static int labpc_calib_write_insn(struct comedi_device *dev, 1727 struct comedi_subdevice *s, 1728 struct comedi_insn *insn, unsigned int *data) 1729{ 1730 int channel = CR_CHAN(insn->chanspec); 1731 1732 write_caldac(dev, channel, data[0]); 1733 return 1; 1734} 1735 1736static int labpc_eeprom_read_insn(struct comedi_device *dev, 1737 struct comedi_subdevice *s, 1738 struct comedi_insn *insn, unsigned int *data) 1739{ 1740 data[0] = devpriv->eeprom_data[CR_CHAN(insn->chanspec)]; 1741 1742 return 1; 1743} 1744 1745static int labpc_eeprom_write_insn(struct comedi_device *dev, 1746 struct comedi_subdevice *s, 1747 struct comedi_insn *insn, unsigned int *data) 1748{ 1749 int channel = CR_CHAN(insn->chanspec); 1750 int ret; 1751 1752 /* only allow writes to user area of eeprom */ 1753 if (channel < 16 || channel > 127) { 1754 dev_dbg(dev->class_dev, 1755 "eeprom writes are only allowed to channels 16 through 127 (the pointer and user areas)\n"); 1756 return -EINVAL; 1757 } 1758 1759 ret = labpc_eeprom_write(dev, channel, data[0]); 1760 if (ret < 0) 1761 return ret; 1762 1763 return 1; 1764} 1765 1766#ifdef CONFIG_ISA_DMA_API 1767/* utility function that suggests a dma transfer size in bytes */ 1768static unsigned int labpc_suggest_transfer_size(struct comedi_cmd cmd) 1769{ 1770 unsigned int size; 1771 unsigned int freq; 1772 1773 if (cmd.convert_src == TRIG_TIMER) 1774 freq = 1000000000 / cmd.convert_arg; 1775 /* return some default value */ 1776 else 1777 freq = 0xffffffff; 1778 1779 /* make buffer fill in no more than 1/3 second */ 1780 size = (freq / 3) * sample_size; 1781 1782 /* set a minimum and maximum size allowed */ 1783 if (size > dma_buffer_size) 1784 size = dma_buffer_size - dma_buffer_size % sample_size; 1785 else if (size < sample_size) 1786 size = sample_size; 1787 1788 return size; 1789} 1790#endif 1791 1792/* figures out what counter values to use based on command */ 1793static void labpc_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd) 1794{ 1795 /* max value for 16 bit counter in mode 2 */ 1796 const int max_counter_value = 0x10000; 1797 /* min value for 16 bit counter in mode 2 */ 1798 const int min_counter_value = 2; 1799 unsigned int base_period; 1800 1801 /* 1802 * if both convert and scan triggers are TRIG_TIMER, then they 1803 * both rely on counter b0 1804 */ 1805 if (labpc_ai_convert_period(cmd) && labpc_ai_scan_period(cmd)) { 1806 /* 1807 * pick the lowest b0 divisor value we can (for maximum input 1808 * clock speed on convert and scan counters) 1809 */ 1810 devpriv->divisor_b0 = (labpc_ai_scan_period(cmd) - 1) / 1811 (LABPC_TIMER_BASE * max_counter_value) + 1; 1812 if (devpriv->divisor_b0 < min_counter_value) 1813 devpriv->divisor_b0 = min_counter_value; 1814 if (devpriv->divisor_b0 > max_counter_value) 1815 devpriv->divisor_b0 = max_counter_value; 1816 1817 base_period = LABPC_TIMER_BASE * devpriv->divisor_b0; 1818 1819 /* set a0 for conversion frequency and b1 for scan frequency */ 1820 switch (cmd->flags & TRIG_ROUND_MASK) { 1821 default: 1822 case TRIG_ROUND_NEAREST: 1823 devpriv->divisor_a0 = 1824 (labpc_ai_convert_period(cmd) + 1825 (base_period / 2)) / base_period; 1826 devpriv->divisor_b1 = 1827 (labpc_ai_scan_period(cmd) + 1828 (base_period / 2)) / base_period; 1829 break; 1830 case TRIG_ROUND_UP: 1831 devpriv->divisor_a0 = 1832 (labpc_ai_convert_period(cmd) + (base_period - 1833 1)) / base_period; 1834 devpriv->divisor_b1 = 1835 (labpc_ai_scan_period(cmd) + (base_period - 1836 1)) / base_period; 1837 break; 1838 case TRIG_ROUND_DOWN: 1839 devpriv->divisor_a0 = 1840 labpc_ai_convert_period(cmd) / base_period; 1841 devpriv->divisor_b1 = 1842 labpc_ai_scan_period(cmd) / base_period; 1843 break; 1844 } 1845 /* make sure a0 and b1 values are acceptable */ 1846 if (devpriv->divisor_a0 < min_counter_value) 1847 devpriv->divisor_a0 = min_counter_value; 1848 if (devpriv->divisor_a0 > max_counter_value) 1849 devpriv->divisor_a0 = max_counter_value; 1850 if (devpriv->divisor_b1 < min_counter_value) 1851 devpriv->divisor_b1 = min_counter_value; 1852 if (devpriv->divisor_b1 > max_counter_value) 1853 devpriv->divisor_b1 = max_counter_value; 1854 /* write corrected timings to command */ 1855 labpc_set_ai_convert_period(cmd, 1856 base_period * devpriv->divisor_a0); 1857 labpc_set_ai_scan_period(cmd, 1858 base_period * devpriv->divisor_b1); 1859 /* 1860 * if only one TRIG_TIMER is used, we can employ the generic 1861 * cascaded timing functions 1862 */ 1863 } else if (labpc_ai_scan_period(cmd)) { 1864 unsigned int scan_period; 1865 1866 scan_period = labpc_ai_scan_period(cmd); 1867 /* 1868 * calculate cascaded counter values 1869 * that give desired scan timing 1870 */ 1871 i8253_cascade_ns_to_timer_2div(LABPC_TIMER_BASE, 1872 &(devpriv->divisor_b1), 1873 &(devpriv->divisor_b0), 1874 &scan_period, 1875 cmd->flags & TRIG_ROUND_MASK); 1876 labpc_set_ai_scan_period(cmd, scan_period); 1877 } else if (labpc_ai_convert_period(cmd)) { 1878 unsigned int convert_period; 1879 1880 convert_period = labpc_ai_convert_period(cmd); 1881 /* 1882 * calculate cascaded counter values 1883 * that give desired conversion timing 1884 */ 1885 i8253_cascade_ns_to_timer_2div(LABPC_TIMER_BASE, 1886 &(devpriv->divisor_a0), 1887 &(devpriv->divisor_b0), 1888 &convert_period, 1889 cmd->flags & TRIG_ROUND_MASK); 1890 labpc_set_ai_convert_period(cmd, convert_period); 1891 } 1892} 1893 1894static int labpc_dio_mem_callback(int dir, int port, int data, 1895 unsigned long iobase) 1896{ 1897 if (dir) { 1898 writeb(data, (void *)(iobase + port)); 1899 return 0; 1900 } else { 1901 return readb((void *)(iobase + port)); 1902 } 1903} 1904 1905/* lowlevel write to eeprom/dac */ 1906static void labpc_serial_out(struct comedi_device *dev, unsigned int value, 1907 unsigned int value_width) 1908{ 1909 int i; 1910 1911 for (i = 1; i <= value_width; i++) { 1912 /* clear serial clock */ 1913 devpriv->command5_bits &= ~SCLOCK_BIT; 1914 /* send bits most significant bit first */ 1915 if (value & (1 << (value_width - i))) 1916 devpriv->command5_bits |= SDATA_BIT; 1917 else 1918 devpriv->command5_bits &= ~SDATA_BIT; 1919 udelay(1); 1920 devpriv->write_byte(devpriv->command5_bits, 1921 dev->iobase + COMMAND5_REG); 1922 /* set clock to load bit */ 1923 devpriv->command5_bits |= SCLOCK_BIT; 1924 udelay(1); 1925 devpriv->write_byte(devpriv->command5_bits, 1926 dev->iobase + COMMAND5_REG); 1927 } 1928} 1929 1930/* lowlevel read from eeprom */ 1931static unsigned int labpc_serial_in(struct comedi_device *dev) 1932{ 1933 unsigned int value = 0; 1934 int i; 1935 const int value_width = 8; /* number of bits wide values are */ 1936 1937 for (i = 1; i <= value_width; i++) { 1938 /* set serial clock */ 1939 devpriv->command5_bits |= SCLOCK_BIT; 1940 udelay(1); 1941 devpriv->write_byte(devpriv->command5_bits, 1942 dev->iobase + COMMAND5_REG); 1943 /* clear clock bit */ 1944 devpriv->command5_bits &= ~SCLOCK_BIT; 1945 udelay(1); 1946 devpriv->write_byte(devpriv->command5_bits, 1947 dev->iobase + COMMAND5_REG); 1948 /* read bits most significant bit first */ 1949 udelay(1); 1950 devpriv->status2_bits = 1951 devpriv->read_byte(dev->iobase + STATUS2_REG); 1952 if (devpriv->status2_bits & EEPROM_OUT_BIT) 1953 value |= 1 << (value_width - i); 1954 } 1955 1956 return value; 1957} 1958 1959static unsigned int labpc_eeprom_read(struct comedi_device *dev, 1960 unsigned int address) 1961{ 1962 unsigned int value; 1963 /* bits to tell eeprom to expect a read */ 1964 const int read_instruction = 0x3; 1965 /* 8 bit write lengths to eeprom */ 1966 const int write_length = 8; 1967 1968 /* enable read/write to eeprom */ 1969 devpriv->command5_bits &= ~EEPROM_EN_BIT; 1970 udelay(1); 1971 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 1972 devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT; 1973 udelay(1); 1974 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 1975 1976 /* send read instruction */ 1977 labpc_serial_out(dev, read_instruction, write_length); 1978 /* send 8 bit address to read from */ 1979 labpc_serial_out(dev, address, write_length); 1980 /* read result */ 1981 value = labpc_serial_in(dev); 1982 1983 /* disable read/write to eeprom */ 1984 devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT; 1985 udelay(1); 1986 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 1987 1988 return value; 1989} 1990 1991static int labpc_eeprom_write(struct comedi_device *dev, 1992 unsigned int address, unsigned int value) 1993{ 1994 const int write_enable_instruction = 0x6; 1995 const int write_instruction = 0x2; 1996 const int write_length = 8; /* 8 bit write lengths to eeprom */ 1997 const int write_in_progress_bit = 0x1; 1998 const int timeout = 10000; 1999 int i; 2000 2001 /* make sure there isn't already a write in progress */ 2002 for (i = 0; i < timeout; i++) { 2003 if ((labpc_eeprom_read_status(dev) & write_in_progress_bit) == 2004 0) 2005 break; 2006 } 2007 if (i == timeout) { 2008 comedi_error(dev, "eeprom write timed out"); 2009 return -ETIME; 2010 } 2011 /* update software copy of eeprom */ 2012 devpriv->eeprom_data[address] = value; 2013 2014 /* enable read/write to eeprom */ 2015 devpriv->command5_bits &= ~EEPROM_EN_BIT; 2016 udelay(1); 2017 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 2018 devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT; 2019 udelay(1); 2020 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 2021 2022 /* send write_enable instruction */ 2023 labpc_serial_out(dev, write_enable_instruction, write_length); 2024 devpriv->command5_bits &= ~EEPROM_EN_BIT; 2025 udelay(1); 2026 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 2027 2028 /* send write instruction */ 2029 devpriv->command5_bits |= EEPROM_EN_BIT; 2030 udelay(1); 2031 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 2032 labpc_serial_out(dev, write_instruction, write_length); 2033 /* send 8 bit address to write to */ 2034 labpc_serial_out(dev, address, write_length); 2035 /* write value */ 2036 labpc_serial_out(dev, value, write_length); 2037 devpriv->command5_bits &= ~EEPROM_EN_BIT; 2038 udelay(1); 2039 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 2040 2041 /* disable read/write to eeprom */ 2042 devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT; 2043 udelay(1); 2044 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 2045 2046 return 0; 2047} 2048 2049static unsigned int labpc_eeprom_read_status(struct comedi_device *dev) 2050{ 2051 unsigned int value; 2052 const int read_status_instruction = 0x5; 2053 const int write_length = 8; /* 8 bit write lengths to eeprom */ 2054 2055 /* enable read/write to eeprom */ 2056 devpriv->command5_bits &= ~EEPROM_EN_BIT; 2057 udelay(1); 2058 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 2059 devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT; 2060 udelay(1); 2061 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 2062 2063 /* send read status instruction */ 2064 labpc_serial_out(dev, read_status_instruction, write_length); 2065 /* read result */ 2066 value = labpc_serial_in(dev); 2067 2068 /* disable read/write to eeprom */ 2069 devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT; 2070 udelay(1); 2071 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 2072 2073 return value; 2074} 2075 2076/* writes to 8 bit calibration dacs */ 2077static void write_caldac(struct comedi_device *dev, unsigned int channel, 2078 unsigned int value) 2079{ 2080 if (value == devpriv->caldac[channel]) 2081 return; 2082 devpriv->caldac[channel] = value; 2083 2084 /* clear caldac load bit and make sure we don't write to eeprom */ 2085 devpriv->command5_bits &= 2086 ~CALDAC_LOAD_BIT & ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT; 2087 udelay(1); 2088 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 2089 2090 /* write 4 bit channel */ 2091 labpc_serial_out(dev, channel, 4); 2092 /* write 8 bit caldac value */ 2093 labpc_serial_out(dev, value, 8); 2094 2095 /* set and clear caldac bit to load caldac value */ 2096 devpriv->command5_bits |= CALDAC_LOAD_BIT; 2097 udelay(1); 2098 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 2099 devpriv->command5_bits &= ~CALDAC_LOAD_BIT; 2100 udelay(1); 2101 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); 2102} 2103 2104static struct comedi_driver labpc_driver = { 2105 .driver_name = DRV_NAME, 2106 .module = THIS_MODULE, 2107 .attach = labpc_attach, 2108 .detach = labpc_common_detach, 2109 .num_names = ARRAY_SIZE(labpc_boards), 2110 .board_name = &labpc_boards[0].name, 2111 .offset = sizeof(struct labpc_board_struct), 2112}; 2113 2114#ifdef CONFIG_COMEDI_PCI_DRIVERS 2115static DEFINE_PCI_DEVICE_TABLE(labpc_pci_table) = { 2116 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x161)}, 2117 {0} 2118}; 2119MODULE_DEVICE_TABLE(pci, labpc_pci_table); 2120 2121static int __devinit labpc_pci_probe(struct pci_dev *dev, 2122 const struct pci_device_id *ent) 2123{ 2124 return comedi_pci_auto_config(dev, &labpc_driver); 2125} 2126 2127static void __devexit labpc_pci_remove(struct pci_dev *dev) 2128{ 2129 comedi_pci_auto_unconfig(dev); 2130} 2131 2132static struct pci_driver labpc_pci_driver = { 2133 .name = DRV_NAME, 2134 .id_table = labpc_pci_table, 2135 .probe = labpc_pci_probe, 2136 .remove = __devexit_p(labpc_pci_remove) 2137}; 2138module_comedi_pci_driver(labpc_driver, labpc_pci_driver); 2139#else 2140module_comedi_driver(labpc_driver); 2141#endif 2142 2143 2144MODULE_AUTHOR("Comedi http://www.comedi.org"); 2145MODULE_DESCRIPTION("Comedi low-level driver"); 2146MODULE_LICENSE("GPL"); 2147