ni_labpc.c revision 63d6ba20bab01ea1a92b3fe7718416a8527e009a
1/* 2 * comedi/drivers/ni_labpc.c 3 * Driver for National Instruments Lab-PC series boards and compatibles 4 * Copyright (C) 2001-2003 Frank Mori Hess <fmhess@users.sourceforge.net> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 */ 20 21/* 22 * Driver: ni_labpc 23 * Description: National Instruments Lab-PC (& compatibles) 24 * Devices: (National Instruments) Lab-PC-1200 [lab-pc-1200] 25 * (National Instruments) Lab-PC-1200AI [lab-pc-1200ai] 26 * (National Instruments) Lab-PC+ [lab-pc+] 27 * Author: Frank Mori Hess <fmhess@users.sourceforge.net> 28 * Status: works 29 * 30 * Configuration options - ISA boards: 31 * [0] - I/O port base address 32 * [1] - IRQ (optional, required for timed or externally triggered 33 * conversions) 34 * [2] - DMA channel (optional) 35 * 36 * Tested with lab-pc-1200. For the older Lab-PC+, not all input 37 * ranges and analog references will work, the available ranges/arefs 38 * will depend on how you have configured the jumpers on your board 39 * (see your owner's manual). 40 * 41 * Kernel-level ISA plug-and-play support for the lab-pc-1200 boards 42 * has not yet been added to the driver, mainly due to the fact that 43 * I don't know the device id numbers. If you have one of these boards, 44 * please file a bug report at http://comedi.org/ so I can get the 45 * necessary information from you. 46 * 47 * The 1200 series boards have onboard calibration dacs for correcting 48 * analog input/output offsets and gains. The proper settings for these 49 * caldacs are stored on the board's eeprom. To read the caldac values 50 * from the eeprom and store them into a file that can be then be used 51 * by comedilib, use the comedi_calibrate program. 52 * 53 * The Lab-pc+ has quirky chanlist requirements when scanning multiple 54 * channels. Multiple channel scan sequence must start at highest channel, 55 * then decrement down to channel 0. The rest of the cards can scan down 56 * like lab-pc+ or scan up from channel zero. Chanlists consisting of all 57 * one channel are also legal, and allow you to pace conversions in bursts. 58 * 59 * NI manuals: 60 * 341309a (labpc-1200 register manual) 61 * 320502b (lab-pc+) 62 */ 63 64#include <linux/interrupt.h> 65#include <linux/slab.h> 66#include <linux/io.h> 67#include <linux/delay.h> 68 69#include "../comedidev.h" 70 71#include <asm/dma.h> 72 73#include "8253.h" 74#include "8255.h" 75#include "comedi_fc.h" 76#include "ni_labpc.h" 77 78/* 79 * Register map (all registers are 8-bit) 80 */ 81#define STAT1_REG 0x00 /* R: Status 1 reg */ 82#define STAT1_DAVAIL (1 << 0) 83#define STAT1_OVERRUN (1 << 1) 84#define STAT1_OVERFLOW (1 << 2) 85#define STAT1_CNTINT (1 << 3) 86#define STAT1_GATA0 (1 << 5) 87#define STAT1_EXTGATA0 (1 << 6) 88#define CMD1_REG 0x00 /* W: Command 1 reg */ 89#define CMD1_MA(x) (((x) & 0x7) << 0) 90#define CMD1_TWOSCMP (1 << 3) 91#define CMD1_GAIN_MASK (7 << 4) 92#define CMD1_SCANEN (1 << 7) 93#define CMD2_REG 0x01 /* W: Command 2 reg */ 94#define CMD2_PRETRIG (1 << 0) 95#define CMD2_HWTRIG (1 << 1) 96#define CMD2_SWTRIG (1 << 2) 97#define CMD2_TBSEL (1 << 3) 98#define CMD2_2SDAC0 (1 << 4) 99#define CMD2_2SDAC1 (1 << 5) 100#define CMD2_LDAC(x) (1 << (6 + (x))) 101#define CMD3_REG 0x02 /* W: Command 3 reg */ 102#define CMD3_DMAEN (1 << 0) 103#define CMD3_DIOINTEN (1 << 1) 104#define CMD3_DMATCINTEN (1 << 2) 105#define CMD3_CNTINTEN (1 << 3) 106#define CMD3_ERRINTEN (1 << 4) 107#define CMD3_FIFOINTEN (1 << 5) 108#define ADC_START_CONVERT_REG 0x03 /* W: Start Convert reg */ 109#define DAC_LSB_REG(x) (0x04 + 2 * (x)) /* W: DAC0/1 LSB reg */ 110#define DAC_MSB_REG(x) (0x05 + 2 * (x)) /* W: DAC0/1 MSB reg */ 111#define ADC_FIFO_CLEAR_REG 0x08 /* W: A/D FIFO Clear reg */ 112#define ADC_FIFO_REG 0x0a /* R: A/D FIFO reg */ 113#define DMATC_CLEAR_REG 0x0a /* W: DMA Interrupt Clear reg */ 114#define TIMER_CLEAR_REG 0x0c /* W: Timer Interrupt Clear reg */ 115#define CMD6_REG 0x0e /* W: Command 6 reg */ 116#define CMD6_NRSE (1 << 0) 117#define CMD6_ADCUNI (1 << 1) 118#define CMD6_DACUNI(x) (1 << (2 + (x))) 119#define CMD6_HFINTEN (1 << 5) 120#define CMD6_DQINTEN (1 << 6) 121#define CMD6_SCANUP (1 << 7) 122#define CMD4_REG 0x0f /* W: Command 3 reg */ 123#define CMD4_INTSCAN (1 << 0) 124#define CMD4_EOIRCV (1 << 1) 125#define CMD4_ECLKDRV (1 << 2) 126#define CMD4_SEDIFF (1 << 3) 127#define CMD4_ECLKRCV (1 << 4) 128#define DIO_BASE_REG 0x10 /* R/W: 8255 DIO base reg */ 129#define COUNTER_A_BASE_REG 0x14 /* R/W: 8253 Counter A base reg */ 130#define COUNTER_B_BASE_REG 0x18 /* R/W: 8253 Counter B base reg */ 131#define CMD5_REG 0x1c /* W: Command 5 reg */ 132#define CMD5_WRTPRT (1 << 2) 133#define CMD5_DITHEREN (1 << 3) 134#define CMD5_CALDACLD (1 << 4) 135#define CMD5_SCLK (1 << 5) 136#define CMD5_SDATA (1 << 6) 137#define CMD5_EEPROMCS (1 << 7) 138#define STAT2_REG 0x1d /* R: Status 2 reg */ 139#define STAT2_PROMOUT (1 << 0) 140#define STAT2_OUTA1 (1 << 1) 141#define STAT2_FIFONHF (1 << 2) 142#define INTERVAL_COUNT_REG 0x1e /* W: Interval Counter Data reg */ 143#define INTERVAL_STROBE_REG 0x1f /* W: Interval Counter Strobe reg */ 144 145#define LABPC_SIZE 0x20 /* size of ISA io region */ 146#define LABPC_TIMER_BASE 500 /* 2 MHz master clock */ 147#define LABPC_ADC_TIMEOUT 1000 148 149enum scan_mode { 150 MODE_SINGLE_CHAN, 151 MODE_SINGLE_CHAN_INTERVAL, 152 MODE_MULT_CHAN_UP, 153 MODE_MULT_CHAN_DOWN, 154}; 155 156static const int labpc_plus_ai_gain_bits[] = { 157 0x00, 0x10, 0x20, 0x30, 0x40, 0x50, 0x60, 0x70, 158 0x00, 0x10, 0x20, 0x30, 0x40, 0x50, 0x60, 0x70, 159}; 160 161static const struct comedi_lrange range_labpc_plus_ai = { 162 16, { 163 BIP_RANGE(5), 164 BIP_RANGE(4), 165 BIP_RANGE(2.5), 166 BIP_RANGE(1), 167 BIP_RANGE(0.5), 168 BIP_RANGE(0.25), 169 BIP_RANGE(0.1), 170 BIP_RANGE(0.05), 171 UNI_RANGE(10), 172 UNI_RANGE(8), 173 UNI_RANGE(5), 174 UNI_RANGE(2), 175 UNI_RANGE(1), 176 UNI_RANGE(0.5), 177 UNI_RANGE(0.2), 178 UNI_RANGE(0.1) 179 } 180}; 181 182const int labpc_1200_ai_gain_bits[] = { 183 0x00, 0x20, 0x30, 0x40, 0x50, 0x60, 0x70, 184 0x00, 0x20, 0x30, 0x40, 0x50, 0x60, 0x70, 185}; 186EXPORT_SYMBOL_GPL(labpc_1200_ai_gain_bits); 187 188const struct comedi_lrange range_labpc_1200_ai = { 189 14, { 190 BIP_RANGE(5), 191 BIP_RANGE(2.5), 192 BIP_RANGE(1), 193 BIP_RANGE(0.5), 194 BIP_RANGE(0.25), 195 BIP_RANGE(0.1), 196 BIP_RANGE(0.05), 197 UNI_RANGE(10), 198 UNI_RANGE(5), 199 UNI_RANGE(2), 200 UNI_RANGE(1), 201 UNI_RANGE(0.5), 202 UNI_RANGE(0.2), 203 UNI_RANGE(0.1) 204 } 205}; 206EXPORT_SYMBOL_GPL(range_labpc_1200_ai); 207 208static const struct comedi_lrange range_labpc_ao = { 209 2, { 210 BIP_RANGE(5), 211 UNI_RANGE(10) 212 } 213}; 214 215/* functions that do inb/outb and readb/writeb so we can use 216 * function pointers to decide which to use */ 217static inline unsigned int labpc_inb(unsigned long address) 218{ 219 return inb(address); 220} 221 222static inline void labpc_outb(unsigned int byte, unsigned long address) 223{ 224 outb(byte, address); 225} 226 227static inline unsigned int labpc_readb(unsigned long address) 228{ 229 return readb((void __iomem *)address); 230} 231 232static inline void labpc_writeb(unsigned int byte, unsigned long address) 233{ 234 writeb(byte, (void __iomem *)address); 235} 236 237#if IS_ENABLED(CONFIG_COMEDI_NI_LABPC_ISA) 238static const struct labpc_boardinfo labpc_boards[] = { 239 { 240 .name = "lab-pc-1200", 241 .ai_range_table = &range_labpc_1200_ai, 242 .ai_range_code = labpc_1200_ai_gain_bits, 243 .ai_speed = 10000, 244 .ai_scan_up = 1, 245 .has_ao = 1, 246 .is_labpc1200 = 1, 247 }, { 248 .name = "lab-pc-1200ai", 249 .ai_range_table = &range_labpc_1200_ai, 250 .ai_range_code = labpc_1200_ai_gain_bits, 251 .ai_speed = 10000, 252 .ai_scan_up = 1, 253 .is_labpc1200 = 1, 254 }, { 255 .name = "lab-pc+", 256 .ai_range_table = &range_labpc_plus_ai, 257 .ai_range_code = labpc_plus_ai_gain_bits, 258 .ai_speed = 12000, 259 .has_ao = 1, 260 }, 261}; 262#endif 263 264/* size in bytes of dma buffer */ 265static const int dma_buffer_size = 0xff00; 266/* 2 bytes per sample */ 267static const int sample_size = 2; 268 269static int labpc_counter_load(struct comedi_device *dev, 270 unsigned long base_address, 271 unsigned int counter_number, 272 unsigned int count, unsigned int mode) 273{ 274 const struct labpc_boardinfo *board = comedi_board(dev); 275 276 if (board->has_mmio) 277 return i8254_mm_load((void __iomem *)base_address, 0, 278 counter_number, count, mode); 279 else 280 return i8254_load(base_address, 0, counter_number, count, mode); 281} 282 283static int labpc_counter_set_mode(struct comedi_device *dev, 284 unsigned long base_address, 285 unsigned int counter_number, 286 unsigned int mode) 287{ 288 const struct labpc_boardinfo *board = comedi_board(dev); 289 290 if (board->has_mmio) 291 return i8254_mm_set_mode((void __iomem *)base_address, 0, 292 counter_number, mode); 293 else 294 return i8254_set_mode(base_address, 0, counter_number, mode); 295} 296 297static bool labpc_range_is_unipolar(struct comedi_subdevice *s, 298 unsigned int range) 299{ 300 return s->range_table->range[range].min >= 0; 301} 302 303static int labpc_cancel(struct comedi_device *dev, struct comedi_subdevice *s) 304{ 305 struct labpc_private *devpriv = dev->private; 306 unsigned long flags; 307 308 spin_lock_irqsave(&dev->spinlock, flags); 309 devpriv->cmd2 &= ~(CMD2_SWTRIG | CMD2_HWTRIG | CMD2_PRETRIG); 310 devpriv->write_byte(devpriv->cmd2, dev->iobase + CMD2_REG); 311 spin_unlock_irqrestore(&dev->spinlock, flags); 312 313 devpriv->cmd3 = 0; 314 devpriv->write_byte(devpriv->cmd3, dev->iobase + CMD3_REG); 315 316 return 0; 317} 318 319static void labpc_ai_set_chan_and_gain(struct comedi_device *dev, 320 enum scan_mode mode, 321 unsigned int chan, 322 unsigned int range, 323 unsigned int aref) 324{ 325 const struct labpc_boardinfo *board = comedi_board(dev); 326 struct labpc_private *devpriv = dev->private; 327 328 /* munge channel bits for differential/scan disabled mode */ 329 if ((mode == MODE_SINGLE_CHAN || mode == MODE_SINGLE_CHAN_INTERVAL) && 330 aref == AREF_DIFF) 331 chan *= 2; 332 devpriv->cmd1 = CMD1_MA(chan); 333 devpriv->cmd1 |= board->ai_range_code[range]; 334 335 devpriv->write_byte(devpriv->cmd1, dev->iobase + CMD1_REG); 336} 337 338static void labpc_setup_cmd6_reg(struct comedi_device *dev, 339 struct comedi_subdevice *s, 340 enum scan_mode mode, 341 enum transfer_type xfer, 342 unsigned int range, 343 unsigned int aref, 344 bool ena_intr) 345{ 346 const struct labpc_boardinfo *board = comedi_board(dev); 347 struct labpc_private *devpriv = dev->private; 348 349 if (!board->is_labpc1200) 350 return; 351 352 /* reference inputs to ground or common? */ 353 if (aref != AREF_GROUND) 354 devpriv->cmd6 |= CMD6_NRSE; 355 else 356 devpriv->cmd6 &= ~CMD6_NRSE; 357 358 /* bipolar or unipolar range? */ 359 if (labpc_range_is_unipolar(s, range)) 360 devpriv->cmd6 |= CMD6_ADCUNI; 361 else 362 devpriv->cmd6 &= ~CMD6_ADCUNI; 363 364 /* interrupt on fifo half full? */ 365 if (xfer == fifo_half_full_transfer) 366 devpriv->cmd6 |= CMD6_HFINTEN; 367 else 368 devpriv->cmd6 &= ~CMD6_HFINTEN; 369 370 /* enable interrupt on counter a1 terminal count? */ 371 if (ena_intr) 372 devpriv->cmd6 |= CMD6_DQINTEN; 373 else 374 devpriv->cmd6 &= ~CMD6_DQINTEN; 375 376 /* are we scanning up or down through channels? */ 377 if (mode == MODE_MULT_CHAN_UP) 378 devpriv->cmd6 |= CMD6_SCANUP; 379 else 380 devpriv->cmd6 &= ~CMD6_SCANUP; 381 382 devpriv->write_byte(devpriv->cmd6, dev->iobase + CMD6_REG); 383} 384 385static unsigned int labpc_read_adc_fifo(struct comedi_device *dev) 386{ 387 struct labpc_private *devpriv = dev->private; 388 unsigned int lsb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG); 389 unsigned int msb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG); 390 391 return (msb << 8) | lsb; 392} 393 394static void labpc_clear_adc_fifo(struct comedi_device *dev) 395{ 396 struct labpc_private *devpriv = dev->private; 397 398 devpriv->write_byte(0x1, dev->iobase + ADC_FIFO_CLEAR_REG); 399 labpc_read_adc_fifo(dev); 400} 401 402static int labpc_ai_wait_for_data(struct comedi_device *dev, 403 int timeout) 404{ 405 struct labpc_private *devpriv = dev->private; 406 int i; 407 408 for (i = 0; i < timeout; i++) { 409 devpriv->stat1 = devpriv->read_byte(dev->iobase + STAT1_REG); 410 if (devpriv->stat1 & STAT1_DAVAIL) 411 return 0; 412 udelay(1); 413 } 414 return -ETIME; 415} 416 417static int labpc_ai_insn_read(struct comedi_device *dev, 418 struct comedi_subdevice *s, 419 struct comedi_insn *insn, 420 unsigned int *data) 421{ 422 struct labpc_private *devpriv = dev->private; 423 unsigned int chan = CR_CHAN(insn->chanspec); 424 unsigned int range = CR_RANGE(insn->chanspec); 425 unsigned int aref = CR_AREF(insn->chanspec); 426 int ret; 427 int i; 428 429 /* disable timed conversions, interrupt generation and dma */ 430 labpc_cancel(dev, s); 431 432 labpc_ai_set_chan_and_gain(dev, MODE_SINGLE_CHAN, chan, range, aref); 433 434 labpc_setup_cmd6_reg(dev, s, MODE_SINGLE_CHAN, fifo_not_empty_transfer, 435 range, aref, false); 436 437 /* setup cmd4 register */ 438 devpriv->cmd4 = 0; 439 devpriv->cmd4 |= CMD4_ECLKRCV; 440 /* single-ended/differential */ 441 if (aref == AREF_DIFF) 442 devpriv->cmd4 |= CMD4_SEDIFF; 443 devpriv->write_byte(devpriv->cmd4, dev->iobase + CMD4_REG); 444 445 /* initialize pacer counter to prevent any problems */ 446 ret = labpc_counter_set_mode(dev, dev->iobase + COUNTER_A_BASE_REG, 447 0, I8254_MODE2); 448 if (ret) 449 return ret; 450 451 labpc_clear_adc_fifo(dev); 452 453 for (i = 0; i < insn->n; i++) { 454 /* trigger conversion */ 455 devpriv->write_byte(0x1, dev->iobase + ADC_START_CONVERT_REG); 456 457 ret = labpc_ai_wait_for_data(dev, LABPC_ADC_TIMEOUT); 458 if (ret) 459 return ret; 460 461 data[i] = labpc_read_adc_fifo(dev); 462 } 463 464 return insn->n; 465} 466 467#ifdef CONFIG_ISA_DMA_API 468/* utility function that suggests a dma transfer size in bytes */ 469static unsigned int labpc_suggest_transfer_size(const struct comedi_cmd *cmd) 470{ 471 unsigned int size; 472 unsigned int freq; 473 474 if (cmd->convert_src == TRIG_TIMER) 475 freq = 1000000000 / cmd->convert_arg; 476 /* return some default value */ 477 else 478 freq = 0xffffffff; 479 480 /* make buffer fill in no more than 1/3 second */ 481 size = (freq / 3) * sample_size; 482 483 /* set a minimum and maximum size allowed */ 484 if (size > dma_buffer_size) 485 size = dma_buffer_size - dma_buffer_size % sample_size; 486 else if (size < sample_size) 487 size = sample_size; 488 489 return size; 490} 491#endif 492 493static bool labpc_use_continuous_mode(const struct comedi_cmd *cmd, 494 enum scan_mode mode) 495{ 496 if (mode == MODE_SINGLE_CHAN || cmd->scan_begin_src == TRIG_FOLLOW) 497 return true; 498 499 return false; 500} 501 502static unsigned int labpc_ai_convert_period(const struct comedi_cmd *cmd, 503 enum scan_mode mode) 504{ 505 if (cmd->convert_src != TRIG_TIMER) 506 return 0; 507 508 if (mode == MODE_SINGLE_CHAN && cmd->scan_begin_src == TRIG_TIMER) 509 return cmd->scan_begin_arg; 510 511 return cmd->convert_arg; 512} 513 514static void labpc_set_ai_convert_period(struct comedi_cmd *cmd, 515 enum scan_mode mode, unsigned int ns) 516{ 517 if (cmd->convert_src != TRIG_TIMER) 518 return; 519 520 if (mode == MODE_SINGLE_CHAN && 521 cmd->scan_begin_src == TRIG_TIMER) { 522 cmd->scan_begin_arg = ns; 523 if (cmd->convert_arg > cmd->scan_begin_arg) 524 cmd->convert_arg = cmd->scan_begin_arg; 525 } else 526 cmd->convert_arg = ns; 527} 528 529static unsigned int labpc_ai_scan_period(const struct comedi_cmd *cmd, 530 enum scan_mode mode) 531{ 532 if (cmd->scan_begin_src != TRIG_TIMER) 533 return 0; 534 535 if (mode == MODE_SINGLE_CHAN && cmd->convert_src == TRIG_TIMER) 536 return 0; 537 538 return cmd->scan_begin_arg; 539} 540 541static void labpc_set_ai_scan_period(struct comedi_cmd *cmd, 542 enum scan_mode mode, unsigned int ns) 543{ 544 if (cmd->scan_begin_src != TRIG_TIMER) 545 return; 546 547 if (mode == MODE_SINGLE_CHAN && cmd->convert_src == TRIG_TIMER) 548 return; 549 550 cmd->scan_begin_arg = ns; 551} 552 553/* figures out what counter values to use based on command */ 554static void labpc_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd, 555 enum scan_mode mode) 556{ 557 struct labpc_private *devpriv = dev->private; 558 /* max value for 16 bit counter in mode 2 */ 559 const int max_counter_value = 0x10000; 560 /* min value for 16 bit counter in mode 2 */ 561 const int min_counter_value = 2; 562 unsigned int base_period; 563 unsigned int scan_period; 564 unsigned int convert_period; 565 566 /* 567 * if both convert and scan triggers are TRIG_TIMER, then they 568 * both rely on counter b0 569 */ 570 convert_period = labpc_ai_convert_period(cmd, mode); 571 scan_period = labpc_ai_scan_period(cmd, mode); 572 if (convert_period && scan_period) { 573 /* 574 * pick the lowest b0 divisor value we can (for maximum input 575 * clock speed on convert and scan counters) 576 */ 577 devpriv->divisor_b0 = (scan_period - 1) / 578 (LABPC_TIMER_BASE * max_counter_value) + 1; 579 if (devpriv->divisor_b0 < min_counter_value) 580 devpriv->divisor_b0 = min_counter_value; 581 if (devpriv->divisor_b0 > max_counter_value) 582 devpriv->divisor_b0 = max_counter_value; 583 584 base_period = LABPC_TIMER_BASE * devpriv->divisor_b0; 585 586 /* set a0 for conversion frequency and b1 for scan frequency */ 587 switch (cmd->flags & TRIG_ROUND_MASK) { 588 default: 589 case TRIG_ROUND_NEAREST: 590 devpriv->divisor_a0 = 591 (convert_period + (base_period / 2)) / base_period; 592 devpriv->divisor_b1 = 593 (scan_period + (base_period / 2)) / base_period; 594 break; 595 case TRIG_ROUND_UP: 596 devpriv->divisor_a0 = 597 (convert_period + (base_period - 1)) / base_period; 598 devpriv->divisor_b1 = 599 (scan_period + (base_period - 1)) / base_period; 600 break; 601 case TRIG_ROUND_DOWN: 602 devpriv->divisor_a0 = convert_period / base_period; 603 devpriv->divisor_b1 = scan_period / base_period; 604 break; 605 } 606 /* make sure a0 and b1 values are acceptable */ 607 if (devpriv->divisor_a0 < min_counter_value) 608 devpriv->divisor_a0 = min_counter_value; 609 if (devpriv->divisor_a0 > max_counter_value) 610 devpriv->divisor_a0 = max_counter_value; 611 if (devpriv->divisor_b1 < min_counter_value) 612 devpriv->divisor_b1 = min_counter_value; 613 if (devpriv->divisor_b1 > max_counter_value) 614 devpriv->divisor_b1 = max_counter_value; 615 /* write corrected timings to command */ 616 labpc_set_ai_convert_period(cmd, mode, 617 base_period * devpriv->divisor_a0); 618 labpc_set_ai_scan_period(cmd, mode, 619 base_period * devpriv->divisor_b1); 620 /* 621 * if only one TRIG_TIMER is used, we can employ the generic 622 * cascaded timing functions 623 */ 624 } else if (scan_period) { 625 /* 626 * calculate cascaded counter values 627 * that give desired scan timing 628 */ 629 i8253_cascade_ns_to_timer_2div(LABPC_TIMER_BASE, 630 &(devpriv->divisor_b1), 631 &(devpriv->divisor_b0), 632 &scan_period, 633 cmd->flags & TRIG_ROUND_MASK); 634 labpc_set_ai_scan_period(cmd, mode, scan_period); 635 } else if (convert_period) { 636 /* 637 * calculate cascaded counter values 638 * that give desired conversion timing 639 */ 640 i8253_cascade_ns_to_timer_2div(LABPC_TIMER_BASE, 641 &(devpriv->divisor_a0), 642 &(devpriv->divisor_b0), 643 &convert_period, 644 cmd->flags & TRIG_ROUND_MASK); 645 labpc_set_ai_convert_period(cmd, mode, convert_period); 646 } 647} 648 649static enum scan_mode labpc_ai_scan_mode(const struct comedi_cmd *cmd) 650{ 651 if (cmd->chanlist_len == 1) 652 return MODE_SINGLE_CHAN; 653 654 /* chanlist may be NULL during cmdtest. */ 655 if (cmd->chanlist == NULL) 656 return MODE_MULT_CHAN_UP; 657 658 if (CR_CHAN(cmd->chanlist[0]) == CR_CHAN(cmd->chanlist[1])) 659 return MODE_SINGLE_CHAN_INTERVAL; 660 661 if (CR_CHAN(cmd->chanlist[0]) < CR_CHAN(cmd->chanlist[1])) 662 return MODE_MULT_CHAN_UP; 663 664 if (CR_CHAN(cmd->chanlist[0]) > CR_CHAN(cmd->chanlist[1])) 665 return MODE_MULT_CHAN_DOWN; 666 667 pr_err("ni_labpc: bug! cannot determine AI scan mode\n"); 668 return 0; 669} 670 671static int labpc_ai_chanlist_invalid(const struct comedi_device *dev, 672 const struct comedi_cmd *cmd, 673 enum scan_mode mode) 674{ 675 int channel, range, aref, i; 676 677 if (cmd->chanlist == NULL) 678 return 0; 679 680 if (mode == MODE_SINGLE_CHAN) 681 return 0; 682 683 if (mode == MODE_SINGLE_CHAN_INTERVAL) { 684 if (cmd->chanlist_len > 0xff) { 685 comedi_error(dev, 686 "ni_labpc: chanlist too long for single channel interval mode\n"); 687 return 1; 688 } 689 } 690 691 channel = CR_CHAN(cmd->chanlist[0]); 692 range = CR_RANGE(cmd->chanlist[0]); 693 aref = CR_AREF(cmd->chanlist[0]); 694 695 for (i = 0; i < cmd->chanlist_len; i++) { 696 697 switch (mode) { 698 case MODE_SINGLE_CHAN_INTERVAL: 699 if (CR_CHAN(cmd->chanlist[i]) != channel) { 700 comedi_error(dev, 701 "channel scanning order specified in chanlist is not supported by hardware.\n"); 702 return 1; 703 } 704 break; 705 case MODE_MULT_CHAN_UP: 706 if (CR_CHAN(cmd->chanlist[i]) != i) { 707 comedi_error(dev, 708 "channel scanning order specified in chanlist is not supported by hardware.\n"); 709 return 1; 710 } 711 break; 712 case MODE_MULT_CHAN_DOWN: 713 if (CR_CHAN(cmd->chanlist[i]) != 714 cmd->chanlist_len - i - 1) { 715 comedi_error(dev, 716 "channel scanning order specified in chanlist is not supported by hardware.\n"); 717 return 1; 718 } 719 break; 720 default: 721 dev_err(dev->class_dev, 722 "ni_labpc: bug! in chanlist check\n"); 723 return 1; 724 break; 725 } 726 727 if (CR_RANGE(cmd->chanlist[i]) != range) { 728 comedi_error(dev, 729 "entries in chanlist must all have the same range\n"); 730 return 1; 731 } 732 733 if (CR_AREF(cmd->chanlist[i]) != aref) { 734 comedi_error(dev, 735 "entries in chanlist must all have the same reference\n"); 736 return 1; 737 } 738 } 739 740 return 0; 741} 742 743static int labpc_ai_cmdtest(struct comedi_device *dev, 744 struct comedi_subdevice *s, struct comedi_cmd *cmd) 745{ 746 const struct labpc_boardinfo *board = comedi_board(dev); 747 int err = 0; 748 int tmp, tmp2; 749 unsigned int stop_mask; 750 enum scan_mode mode; 751 752 /* Step 1 : check if triggers are trivially valid */ 753 754 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_EXT); 755 err |= cfc_check_trigger_src(&cmd->scan_begin_src, 756 TRIG_TIMER | TRIG_FOLLOW | TRIG_EXT); 757 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_TIMER | TRIG_EXT); 758 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT); 759 760 stop_mask = TRIG_COUNT | TRIG_NONE; 761 if (board->is_labpc1200) 762 stop_mask |= TRIG_EXT; 763 err |= cfc_check_trigger_src(&cmd->stop_src, stop_mask); 764 765 if (err) 766 return 1; 767 768 /* Step 2a : make sure trigger sources are unique */ 769 770 err |= cfc_check_trigger_is_unique(cmd->start_src); 771 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src); 772 err |= cfc_check_trigger_is_unique(cmd->convert_src); 773 err |= cfc_check_trigger_is_unique(cmd->stop_src); 774 775 /* Step 2b : and mutually compatible */ 776 777 /* can't have external stop and start triggers at once */ 778 if (cmd->start_src == TRIG_EXT && cmd->stop_src == TRIG_EXT) 779 err++; 780 781 if (err) 782 return 2; 783 784 /* Step 3: check if arguments are trivially valid */ 785 786 if (cmd->start_arg == TRIG_NOW) 787 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0); 788 789 if (!cmd->chanlist_len) 790 err |= -EINVAL; 791 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len); 792 793 if (cmd->convert_src == TRIG_TIMER) 794 err |= cfc_check_trigger_arg_min(&cmd->convert_arg, 795 board->ai_speed); 796 797 /* make sure scan timing is not too fast */ 798 if (cmd->scan_begin_src == TRIG_TIMER) { 799 if (cmd->convert_src == TRIG_TIMER) 800 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg, 801 cmd->convert_arg * cmd->chanlist_len); 802 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg, 803 board->ai_speed * cmd->chanlist_len); 804 } 805 806 switch (cmd->stop_src) { 807 case TRIG_COUNT: 808 err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1); 809 break; 810 case TRIG_NONE: 811 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0); 812 break; 813 /* 814 * TRIG_EXT doesn't care since it doesn't 815 * trigger off a numbered channel 816 */ 817 default: 818 break; 819 } 820 821 if (err) 822 return 3; 823 824 /* step 4: fix up any arguments */ 825 826 tmp = cmd->convert_arg; 827 tmp2 = cmd->scan_begin_arg; 828 mode = labpc_ai_scan_mode(cmd); 829 labpc_adc_timing(dev, cmd, mode); 830 if (tmp != cmd->convert_arg || tmp2 != cmd->scan_begin_arg) 831 err++; 832 833 if (err) 834 return 4; 835 836 if (labpc_ai_chanlist_invalid(dev, cmd, mode)) 837 return 5; 838 839 return 0; 840} 841 842static int labpc_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) 843{ 844 const struct labpc_boardinfo *board = comedi_board(dev); 845 struct labpc_private *devpriv = dev->private; 846 struct comedi_async *async = s->async; 847 struct comedi_cmd *cmd = &async->cmd; 848 enum scan_mode mode = labpc_ai_scan_mode(cmd); 849 unsigned int chanspec = (mode == MODE_MULT_CHAN_UP) 850 ? cmd->chanlist[cmd->chanlist_len - 1] 851 : cmd->chanlist[0]; 852 unsigned int chan = CR_CHAN(chanspec); 853 unsigned int range = CR_RANGE(chanspec); 854 unsigned int aref = CR_AREF(chanspec); 855 enum transfer_type xfer; 856 unsigned long flags; 857 int ret; 858 859 /* make sure board is disabled before setting up acquisition */ 860 labpc_cancel(dev, s); 861 862 /* initialize software conversion count */ 863 if (cmd->stop_src == TRIG_COUNT) 864 devpriv->count = cmd->stop_arg * cmd->chanlist_len; 865 866 /* setup hardware conversion counter */ 867 if (cmd->stop_src == TRIG_EXT) { 868 /* 869 * load counter a1 with count of 3 870 * (pc+ manual says this is minimum allowed) using mode 0 871 */ 872 ret = labpc_counter_load(dev, dev->iobase + COUNTER_A_BASE_REG, 873 1, 3, I8254_MODE0); 874 } else { 875 /* just put counter a1 in mode 0 to set its output low */ 876 ret = labpc_counter_set_mode(dev, 877 dev->iobase + COUNTER_A_BASE_REG, 878 1, I8254_MODE0); 879 } 880 if (ret) { 881 comedi_error(dev, "error loading counter a1"); 882 return ret; 883 } 884 885#ifdef CONFIG_ISA_DMA_API 886 /* figure out what method we will use to transfer data */ 887 if (devpriv->dma_chan && /* need a dma channel allocated */ 888 /* 889 * dma unsafe at RT priority, 890 * and too much setup time for TRIG_WAKE_EOS for 891 */ 892 (cmd->flags & (TRIG_WAKE_EOS | TRIG_RT)) == 0) { 893 xfer = isa_dma_transfer; 894 /* pc-plus has no fifo-half full interrupt */ 895 } else 896#endif 897 if (board->is_labpc1200 && 898 /* wake-end-of-scan should interrupt on fifo not empty */ 899 (cmd->flags & TRIG_WAKE_EOS) == 0 && 900 /* make sure we are taking more than just a few points */ 901 (cmd->stop_src != TRIG_COUNT || devpriv->count > 256)) { 902 xfer = fifo_half_full_transfer; 903 } else 904 xfer = fifo_not_empty_transfer; 905 devpriv->current_transfer = xfer; 906 907 labpc_ai_set_chan_and_gain(dev, mode, chan, range, aref); 908 909 labpc_setup_cmd6_reg(dev, s, mode, xfer, range, aref, 910 (cmd->stop_src == TRIG_EXT)); 911 912 /* manual says to set scan enable bit on second pass */ 913 if (mode == MODE_MULT_CHAN_UP || mode == MODE_MULT_CHAN_DOWN) { 914 devpriv->cmd1 |= CMD1_SCANEN; 915 /* need a brief delay before enabling scan, or scan 916 * list will get screwed when you switch 917 * between scan up to scan down mode - dunno why */ 918 udelay(1); 919 devpriv->write_byte(devpriv->cmd1, dev->iobase + CMD1_REG); 920 } 921 922 devpriv->write_byte(cmd->chanlist_len, 923 dev->iobase + INTERVAL_COUNT_REG); 924 /* load count */ 925 devpriv->write_byte(0x1, dev->iobase + INTERVAL_STROBE_REG); 926 927 if (cmd->convert_src == TRIG_TIMER || 928 cmd->scan_begin_src == TRIG_TIMER) { 929 /* set up pacing */ 930 labpc_adc_timing(dev, cmd, mode); 931 /* load counter b0 in mode 3 */ 932 ret = labpc_counter_load(dev, dev->iobase + COUNTER_B_BASE_REG, 933 0, devpriv->divisor_b0, I8254_MODE3); 934 if (ret < 0) { 935 comedi_error(dev, "error loading counter b0"); 936 return -1; 937 } 938 } 939 /* set up conversion pacing */ 940 if (labpc_ai_convert_period(cmd, mode)) { 941 /* load counter a0 in mode 2 */ 942 ret = labpc_counter_load(dev, dev->iobase + COUNTER_A_BASE_REG, 943 0, devpriv->divisor_a0, I8254_MODE2); 944 } else { 945 /* initialize pacer counter to prevent any problems */ 946 ret = labpc_counter_set_mode(dev, 947 dev->iobase + COUNTER_A_BASE_REG, 948 0, I8254_MODE2); 949 } 950 if (ret) { 951 comedi_error(dev, "error loading counter a0"); 952 return ret; 953 } 954 955 /* set up scan pacing */ 956 if (labpc_ai_scan_period(cmd, mode)) { 957 /* load counter b1 in mode 2 */ 958 ret = labpc_counter_load(dev, dev->iobase + COUNTER_B_BASE_REG, 959 1, devpriv->divisor_b1, I8254_MODE2); 960 if (ret < 0) { 961 comedi_error(dev, "error loading counter b1"); 962 return -1; 963 } 964 } 965 966 labpc_clear_adc_fifo(dev); 967 968#ifdef CONFIG_ISA_DMA_API 969 /* set up dma transfer */ 970 if (xfer == isa_dma_transfer) { 971 unsigned long irq_flags; 972 973 irq_flags = claim_dma_lock(); 974 disable_dma(devpriv->dma_chan); 975 /* clear flip-flop to make sure 2-byte registers for 976 * count and address get set correctly */ 977 clear_dma_ff(devpriv->dma_chan); 978 set_dma_addr(devpriv->dma_chan, 979 virt_to_bus(devpriv->dma_buffer)); 980 /* set appropriate size of transfer */ 981 devpriv->dma_transfer_size = labpc_suggest_transfer_size(cmd); 982 if (cmd->stop_src == TRIG_COUNT && 983 devpriv->count * sample_size < devpriv->dma_transfer_size) { 984 devpriv->dma_transfer_size = 985 devpriv->count * sample_size; 986 } 987 set_dma_count(devpriv->dma_chan, devpriv->dma_transfer_size); 988 enable_dma(devpriv->dma_chan); 989 release_dma_lock(irq_flags); 990 /* enable board's dma */ 991 devpriv->cmd3 |= (CMD3_DMAEN | CMD3_DMATCINTEN); 992 } else 993 devpriv->cmd3 &= ~(CMD3_DMAEN | CMD3_DMATCINTEN); 994#endif 995 996 /* enable error interrupts */ 997 devpriv->cmd3 |= CMD3_ERRINTEN; 998 /* enable fifo not empty interrupt? */ 999 if (xfer == fifo_not_empty_transfer) 1000 devpriv->cmd3 |= CMD3_FIFOINTEN; 1001 else 1002 devpriv->cmd3 &= ~CMD3_FIFOINTEN; 1003 devpriv->write_byte(devpriv->cmd3, dev->iobase + CMD3_REG); 1004 1005 /* setup any external triggering/pacing (cmd4 register) */ 1006 devpriv->cmd4 = 0; 1007 if (cmd->convert_src != TRIG_EXT) 1008 devpriv->cmd4 |= CMD4_ECLKRCV; 1009 /* XXX should discard first scan when using interval scanning 1010 * since manual says it is not synced with scan clock */ 1011 if (!labpc_use_continuous_mode(cmd, mode)) { 1012 devpriv->cmd4 |= CMD4_INTSCAN; 1013 if (cmd->scan_begin_src == TRIG_EXT) 1014 devpriv->cmd4 |= CMD4_EOIRCV; 1015 } 1016 /* single-ended/differential */ 1017 if (aref == AREF_DIFF) 1018 devpriv->cmd4 |= CMD4_SEDIFF; 1019 devpriv->write_byte(devpriv->cmd4, dev->iobase + CMD4_REG); 1020 1021 /* startup acquisition */ 1022 1023 spin_lock_irqsave(&dev->spinlock, flags); 1024 1025 /* use 2 cascaded counters for pacing */ 1026 devpriv->cmd2 |= CMD2_TBSEL; 1027 1028 devpriv->cmd2 &= ~(CMD2_SWTRIG | CMD2_HWTRIG | CMD2_PRETRIG); 1029 if (cmd->start_src == TRIG_EXT) 1030 devpriv->cmd2 |= CMD2_HWTRIG; 1031 else 1032 devpriv->cmd2 |= CMD2_SWTRIG; 1033 if (cmd->stop_src == TRIG_EXT) 1034 devpriv->cmd2 |= (CMD2_HWTRIG | CMD2_PRETRIG); 1035 1036 devpriv->write_byte(devpriv->cmd2, dev->iobase + CMD2_REG); 1037 1038 spin_unlock_irqrestore(&dev->spinlock, flags); 1039 1040 return 0; 1041} 1042 1043#ifdef CONFIG_ISA_DMA_API 1044static void labpc_drain_dma(struct comedi_device *dev) 1045{ 1046 struct labpc_private *devpriv = dev->private; 1047 struct comedi_subdevice *s = dev->read_subdev; 1048 struct comedi_async *async = s->async; 1049 int status; 1050 unsigned long flags; 1051 unsigned int max_points, num_points, residue, leftover; 1052 int i; 1053 1054 status = devpriv->stat1; 1055 1056 flags = claim_dma_lock(); 1057 disable_dma(devpriv->dma_chan); 1058 /* clear flip-flop to make sure 2-byte registers for 1059 * count and address get set correctly */ 1060 clear_dma_ff(devpriv->dma_chan); 1061 1062 /* figure out how many points to read */ 1063 max_points = devpriv->dma_transfer_size / sample_size; 1064 /* residue is the number of points left to be done on the dma 1065 * transfer. It should always be zero at this point unless 1066 * the stop_src is set to external triggering. 1067 */ 1068 residue = get_dma_residue(devpriv->dma_chan) / sample_size; 1069 num_points = max_points - residue; 1070 if (devpriv->count < num_points && async->cmd.stop_src == TRIG_COUNT) 1071 num_points = devpriv->count; 1072 1073 /* figure out how many points will be stored next time */ 1074 leftover = 0; 1075 if (async->cmd.stop_src != TRIG_COUNT) { 1076 leftover = devpriv->dma_transfer_size / sample_size; 1077 } else if (devpriv->count > num_points) { 1078 leftover = devpriv->count - num_points; 1079 if (leftover > max_points) 1080 leftover = max_points; 1081 } 1082 1083 /* write data to comedi buffer */ 1084 for (i = 0; i < num_points; i++) 1085 cfc_write_to_buffer(s, devpriv->dma_buffer[i]); 1086 1087 if (async->cmd.stop_src == TRIG_COUNT) 1088 devpriv->count -= num_points; 1089 1090 /* set address and count for next transfer */ 1091 set_dma_addr(devpriv->dma_chan, virt_to_bus(devpriv->dma_buffer)); 1092 set_dma_count(devpriv->dma_chan, leftover * sample_size); 1093 release_dma_lock(flags); 1094 1095 async->events |= COMEDI_CB_BLOCK; 1096} 1097 1098static void handle_isa_dma(struct comedi_device *dev) 1099{ 1100 struct labpc_private *devpriv = dev->private; 1101 1102 labpc_drain_dma(dev); 1103 1104 enable_dma(devpriv->dma_chan); 1105 1106 /* clear dma tc interrupt */ 1107 devpriv->write_byte(0x1, dev->iobase + DMATC_CLEAR_REG); 1108} 1109#endif 1110 1111/* read all available samples from ai fifo */ 1112static int labpc_drain_fifo(struct comedi_device *dev) 1113{ 1114 struct labpc_private *devpriv = dev->private; 1115 short data; 1116 struct comedi_async *async = dev->read_subdev->async; 1117 const int timeout = 10000; 1118 unsigned int i; 1119 1120 devpriv->stat1 = devpriv->read_byte(dev->iobase + STAT1_REG); 1121 1122 for (i = 0; (devpriv->stat1 & STAT1_DAVAIL) && i < timeout; 1123 i++) { 1124 /* quit if we have all the data we want */ 1125 if (async->cmd.stop_src == TRIG_COUNT) { 1126 if (devpriv->count == 0) 1127 break; 1128 devpriv->count--; 1129 } 1130 data = labpc_read_adc_fifo(dev); 1131 cfc_write_to_buffer(dev->read_subdev, data); 1132 devpriv->stat1 = devpriv->read_byte(dev->iobase + STAT1_REG); 1133 } 1134 if (i == timeout) { 1135 comedi_error(dev, "ai timeout, fifo never empties"); 1136 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA; 1137 return -1; 1138 } 1139 1140 return 0; 1141} 1142 1143/* makes sure all data acquired by board is transferred to comedi (used 1144 * when acquisition is terminated by stop_src == TRIG_EXT). */ 1145static void labpc_drain_dregs(struct comedi_device *dev) 1146{ 1147#ifdef CONFIG_ISA_DMA_API 1148 struct labpc_private *devpriv = dev->private; 1149 1150 if (devpriv->current_transfer == isa_dma_transfer) 1151 labpc_drain_dma(dev); 1152#endif 1153 1154 labpc_drain_fifo(dev); 1155} 1156 1157/* interrupt service routine */ 1158static irqreturn_t labpc_interrupt(int irq, void *d) 1159{ 1160 struct comedi_device *dev = d; 1161 const struct labpc_boardinfo *board = comedi_board(dev); 1162 struct labpc_private *devpriv = dev->private; 1163 struct comedi_subdevice *s = dev->read_subdev; 1164 struct comedi_async *async; 1165 struct comedi_cmd *cmd; 1166 1167 if (!dev->attached) { 1168 comedi_error(dev, "premature interrupt"); 1169 return IRQ_HANDLED; 1170 } 1171 1172 async = s->async; 1173 cmd = &async->cmd; 1174 async->events = 0; 1175 1176 /* read board status */ 1177 devpriv->stat1 = devpriv->read_byte(dev->iobase + STAT1_REG); 1178 if (board->is_labpc1200) 1179 devpriv->stat2 = devpriv->read_byte(dev->iobase + STAT2_REG); 1180 1181 if ((devpriv->stat1 & (STAT1_GATA0 | STAT1_CNTINT | STAT1_OVERFLOW | 1182 STAT1_OVERRUN | STAT1_DAVAIL)) == 0 1183 && (devpriv->stat2 & STAT2_OUTA1) == 0 1184 && (devpriv->stat2 & STAT2_FIFONHF)) { 1185 return IRQ_NONE; 1186 } 1187 1188 if (devpriv->stat1 & STAT1_OVERRUN) { 1189 /* clear error interrupt */ 1190 devpriv->write_byte(0x1, dev->iobase + ADC_FIFO_CLEAR_REG); 1191 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA; 1192 comedi_event(dev, s); 1193 comedi_error(dev, "overrun"); 1194 return IRQ_HANDLED; 1195 } 1196 1197#ifdef CONFIG_ISA_DMA_API 1198 if (devpriv->current_transfer == isa_dma_transfer) { 1199 /* 1200 * if a dma terminal count of external stop trigger 1201 * has occurred 1202 */ 1203 if (devpriv->stat1 & STAT1_GATA0 || 1204 (board->is_labpc1200 && devpriv->stat2 & STAT2_OUTA1)) { 1205 handle_isa_dma(dev); 1206 } 1207 } else 1208#endif 1209 labpc_drain_fifo(dev); 1210 1211 if (devpriv->stat1 & STAT1_CNTINT) { 1212 comedi_error(dev, "handled timer interrupt?"); 1213 /* clear it */ 1214 devpriv->write_byte(0x1, dev->iobase + TIMER_CLEAR_REG); 1215 } 1216 1217 if (devpriv->stat1 & STAT1_OVERFLOW) { 1218 /* clear error interrupt */ 1219 devpriv->write_byte(0x1, dev->iobase + ADC_FIFO_CLEAR_REG); 1220 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA; 1221 comedi_event(dev, s); 1222 comedi_error(dev, "overflow"); 1223 return IRQ_HANDLED; 1224 } 1225 /* handle external stop trigger */ 1226 if (cmd->stop_src == TRIG_EXT) { 1227 if (devpriv->stat2 & STAT2_OUTA1) { 1228 labpc_drain_dregs(dev); 1229 labpc_cancel(dev, s); 1230 async->events |= COMEDI_CB_EOA; 1231 } 1232 } 1233 1234 /* TRIG_COUNT end of acquisition */ 1235 if (cmd->stop_src == TRIG_COUNT) { 1236 if (devpriv->count == 0) { 1237 labpc_cancel(dev, s); 1238 async->events |= COMEDI_CB_EOA; 1239 } 1240 } 1241 1242 comedi_event(dev, s); 1243 return IRQ_HANDLED; 1244} 1245 1246static int labpc_ao_insn_write(struct comedi_device *dev, 1247 struct comedi_subdevice *s, 1248 struct comedi_insn *insn, 1249 unsigned int *data) 1250{ 1251 const struct labpc_boardinfo *board = comedi_board(dev); 1252 struct labpc_private *devpriv = dev->private; 1253 int channel, range; 1254 unsigned long flags; 1255 int lsb, msb; 1256 1257 channel = CR_CHAN(insn->chanspec); 1258 1259 /* turn off pacing of analog output channel */ 1260 /* note: hardware bug in daqcard-1200 means pacing cannot 1261 * be independently enabled/disabled for its the two channels */ 1262 spin_lock_irqsave(&dev->spinlock, flags); 1263 devpriv->cmd2 &= ~CMD2_LDAC(channel); 1264 devpriv->write_byte(devpriv->cmd2, dev->iobase + CMD2_REG); 1265 spin_unlock_irqrestore(&dev->spinlock, flags); 1266 1267 /* set range */ 1268 if (board->is_labpc1200) { 1269 range = CR_RANGE(insn->chanspec); 1270 if (labpc_range_is_unipolar(s, range)) 1271 devpriv->cmd6 |= CMD6_DACUNI(channel); 1272 else 1273 devpriv->cmd6 &= ~CMD6_DACUNI(channel); 1274 /* write to register */ 1275 devpriv->write_byte(devpriv->cmd6, dev->iobase + CMD6_REG); 1276 } 1277 /* send data */ 1278 lsb = data[0] & 0xff; 1279 msb = (data[0] >> 8) & 0xff; 1280 devpriv->write_byte(lsb, dev->iobase + DAC_LSB_REG(channel)); 1281 devpriv->write_byte(msb, dev->iobase + DAC_MSB_REG(channel)); 1282 1283 /* remember value for readback */ 1284 devpriv->ao_value[channel] = data[0]; 1285 1286 return 1; 1287} 1288 1289static int labpc_ao_insn_read(struct comedi_device *dev, 1290 struct comedi_subdevice *s, 1291 struct comedi_insn *insn, 1292 unsigned int *data) 1293{ 1294 struct labpc_private *devpriv = dev->private; 1295 1296 data[0] = devpriv->ao_value[CR_CHAN(insn->chanspec)]; 1297 1298 return 1; 1299} 1300 1301static int labpc_8255_mmio(int dir, int port, int data, unsigned long iobase) 1302{ 1303 if (dir) { 1304 writeb(data, (void __iomem *)(iobase + port)); 1305 return 0; 1306 } else { 1307 return readb((void __iomem *)(iobase + port)); 1308 } 1309} 1310 1311/* lowlevel write to eeprom/dac */ 1312static void labpc_serial_out(struct comedi_device *dev, unsigned int value, 1313 unsigned int value_width) 1314{ 1315 struct labpc_private *devpriv = dev->private; 1316 int i; 1317 1318 for (i = 1; i <= value_width; i++) { 1319 /* clear serial clock */ 1320 devpriv->cmd5 &= ~CMD5_SCLK; 1321 /* send bits most significant bit first */ 1322 if (value & (1 << (value_width - i))) 1323 devpriv->cmd5 |= CMD5_SDATA; 1324 else 1325 devpriv->cmd5 &= ~CMD5_SDATA; 1326 udelay(1); 1327 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); 1328 /* set clock to load bit */ 1329 devpriv->cmd5 |= CMD5_SCLK; 1330 udelay(1); 1331 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); 1332 } 1333} 1334 1335/* lowlevel read from eeprom */ 1336static unsigned int labpc_serial_in(struct comedi_device *dev) 1337{ 1338 struct labpc_private *devpriv = dev->private; 1339 unsigned int value = 0; 1340 int i; 1341 const int value_width = 8; /* number of bits wide values are */ 1342 1343 for (i = 1; i <= value_width; i++) { 1344 /* set serial clock */ 1345 devpriv->cmd5 |= CMD5_SCLK; 1346 udelay(1); 1347 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); 1348 /* clear clock bit */ 1349 devpriv->cmd5 &= ~CMD5_SCLK; 1350 udelay(1); 1351 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); 1352 /* read bits most significant bit first */ 1353 udelay(1); 1354 devpriv->stat2 = devpriv->read_byte(dev->iobase + STAT2_REG); 1355 if (devpriv->stat2 & STAT2_PROMOUT) 1356 value |= 1 << (value_width - i); 1357 } 1358 1359 return value; 1360} 1361 1362static unsigned int labpc_eeprom_read(struct comedi_device *dev, 1363 unsigned int address) 1364{ 1365 struct labpc_private *devpriv = dev->private; 1366 unsigned int value; 1367 /* bits to tell eeprom to expect a read */ 1368 const int read_instruction = 0x3; 1369 /* 8 bit write lengths to eeprom */ 1370 const int write_length = 8; 1371 1372 /* enable read/write to eeprom */ 1373 devpriv->cmd5 &= ~CMD5_EEPROMCS; 1374 udelay(1); 1375 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); 1376 devpriv->cmd5 |= (CMD5_EEPROMCS | CMD5_WRTPRT); 1377 udelay(1); 1378 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); 1379 1380 /* send read instruction */ 1381 labpc_serial_out(dev, read_instruction, write_length); 1382 /* send 8 bit address to read from */ 1383 labpc_serial_out(dev, address, write_length); 1384 /* read result */ 1385 value = labpc_serial_in(dev); 1386 1387 /* disable read/write to eeprom */ 1388 devpriv->cmd5 &= ~(CMD5_EEPROMCS | CMD5_WRTPRT); 1389 udelay(1); 1390 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); 1391 1392 return value; 1393} 1394 1395static unsigned int labpc_eeprom_read_status(struct comedi_device *dev) 1396{ 1397 struct labpc_private *devpriv = dev->private; 1398 unsigned int value; 1399 const int read_status_instruction = 0x5; 1400 const int write_length = 8; /* 8 bit write lengths to eeprom */ 1401 1402 /* enable read/write to eeprom */ 1403 devpriv->cmd5 &= ~CMD5_EEPROMCS; 1404 udelay(1); 1405 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); 1406 devpriv->cmd5 |= (CMD5_EEPROMCS | CMD5_WRTPRT); 1407 udelay(1); 1408 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); 1409 1410 /* send read status instruction */ 1411 labpc_serial_out(dev, read_status_instruction, write_length); 1412 /* read result */ 1413 value = labpc_serial_in(dev); 1414 1415 /* disable read/write to eeprom */ 1416 devpriv->cmd5 &= ~(CMD5_EEPROMCS | CMD5_WRTPRT); 1417 udelay(1); 1418 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); 1419 1420 return value; 1421} 1422 1423static int labpc_eeprom_write(struct comedi_device *dev, 1424 unsigned int address, unsigned int value) 1425{ 1426 struct labpc_private *devpriv = dev->private; 1427 const int write_enable_instruction = 0x6; 1428 const int write_instruction = 0x2; 1429 const int write_length = 8; /* 8 bit write lengths to eeprom */ 1430 const int write_in_progress_bit = 0x1; 1431 const int timeout = 10000; 1432 int i; 1433 1434 /* make sure there isn't already a write in progress */ 1435 for (i = 0; i < timeout; i++) { 1436 if ((labpc_eeprom_read_status(dev) & write_in_progress_bit) == 1437 0) 1438 break; 1439 } 1440 if (i == timeout) { 1441 comedi_error(dev, "eeprom write timed out"); 1442 return -ETIME; 1443 } 1444 /* update software copy of eeprom */ 1445 devpriv->eeprom_data[address] = value; 1446 1447 /* enable read/write to eeprom */ 1448 devpriv->cmd5 &= ~CMD5_EEPROMCS; 1449 udelay(1); 1450 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); 1451 devpriv->cmd5 |= (CMD5_EEPROMCS | CMD5_WRTPRT); 1452 udelay(1); 1453 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); 1454 1455 /* send write_enable instruction */ 1456 labpc_serial_out(dev, write_enable_instruction, write_length); 1457 devpriv->cmd5 &= ~CMD5_EEPROMCS; 1458 udelay(1); 1459 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); 1460 1461 /* send write instruction */ 1462 devpriv->cmd5 |= CMD5_EEPROMCS; 1463 udelay(1); 1464 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); 1465 labpc_serial_out(dev, write_instruction, write_length); 1466 /* send 8 bit address to write to */ 1467 labpc_serial_out(dev, address, write_length); 1468 /* write value */ 1469 labpc_serial_out(dev, value, write_length); 1470 devpriv->cmd5 &= ~CMD5_EEPROMCS; 1471 udelay(1); 1472 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); 1473 1474 /* disable read/write to eeprom */ 1475 devpriv->cmd5 &= ~(CMD5_EEPROMCS | CMD5_WRTPRT); 1476 udelay(1); 1477 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); 1478 1479 return 0; 1480} 1481 1482/* writes to 8 bit calibration dacs */ 1483static void write_caldac(struct comedi_device *dev, unsigned int channel, 1484 unsigned int value) 1485{ 1486 struct labpc_private *devpriv = dev->private; 1487 1488 if (value == devpriv->caldac[channel]) 1489 return; 1490 devpriv->caldac[channel] = value; 1491 1492 /* clear caldac load bit and make sure we don't write to eeprom */ 1493 devpriv->cmd5 &= ~(CMD5_CALDACLD | CMD5_EEPROMCS | CMD5_WRTPRT); 1494 udelay(1); 1495 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); 1496 1497 /* write 4 bit channel */ 1498 labpc_serial_out(dev, channel, 4); 1499 /* write 8 bit caldac value */ 1500 labpc_serial_out(dev, value, 8); 1501 1502 /* set and clear caldac bit to load caldac value */ 1503 devpriv->cmd5 |= CMD5_CALDACLD; 1504 udelay(1); 1505 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); 1506 devpriv->cmd5 &= ~CMD5_CALDACLD; 1507 udelay(1); 1508 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); 1509} 1510 1511static int labpc_calib_insn_write(struct comedi_device *dev, 1512 struct comedi_subdevice *s, 1513 struct comedi_insn *insn, 1514 unsigned int *data) 1515{ 1516 unsigned int chan = CR_CHAN(insn->chanspec); 1517 1518 /* 1519 * Only write the last data value to the caldac. Preceding 1520 * data would be overwritten anyway. 1521 */ 1522 if (insn->n > 0) 1523 write_caldac(dev, chan, data[insn->n - 1]); 1524 1525 return insn->n; 1526} 1527 1528static int labpc_calib_insn_read(struct comedi_device *dev, 1529 struct comedi_subdevice *s, 1530 struct comedi_insn *insn, 1531 unsigned int *data) 1532{ 1533 struct labpc_private *devpriv = dev->private; 1534 unsigned int chan = CR_CHAN(insn->chanspec); 1535 int i; 1536 1537 for (i = 0; i < insn->n; i++) 1538 data[i] = devpriv->caldac[chan]; 1539 1540 return insn->n; 1541} 1542 1543static int labpc_eeprom_insn_write(struct comedi_device *dev, 1544 struct comedi_subdevice *s, 1545 struct comedi_insn *insn, 1546 unsigned int *data) 1547{ 1548 unsigned int chan = CR_CHAN(insn->chanspec); 1549 int ret; 1550 1551 /* only allow writes to user area of eeprom */ 1552 if (chan < 16 || chan > 127) 1553 return -EINVAL; 1554 1555 /* 1556 * Only write the last data value to the eeprom. Preceding 1557 * data would be overwritten anyway. 1558 */ 1559 if (insn->n > 0) { 1560 ret = labpc_eeprom_write(dev, chan, data[insn->n - 1]); 1561 if (ret) 1562 return ret; 1563 } 1564 1565 return insn->n; 1566} 1567 1568static int labpc_eeprom_insn_read(struct comedi_device *dev, 1569 struct comedi_subdevice *s, 1570 struct comedi_insn *insn, 1571 unsigned int *data) 1572{ 1573 struct labpc_private *devpriv = dev->private; 1574 unsigned int chan = CR_CHAN(insn->chanspec); 1575 int i; 1576 1577 for (i = 0; i < insn->n; i++) 1578 data[i] = devpriv->eeprom_data[chan]; 1579 1580 return insn->n; 1581} 1582 1583int labpc_common_attach(struct comedi_device *dev, 1584 unsigned int irq, unsigned long isr_flags) 1585{ 1586 const struct labpc_boardinfo *board = comedi_board(dev); 1587 struct labpc_private *devpriv = dev->private; 1588 struct comedi_subdevice *s; 1589 int ret; 1590 int i; 1591 1592 if (board->has_mmio) { 1593 devpriv->read_byte = labpc_readb; 1594 devpriv->write_byte = labpc_writeb; 1595 } else { 1596 devpriv->read_byte = labpc_inb; 1597 devpriv->write_byte = labpc_outb; 1598 } 1599 1600 /* initialize board's command registers */ 1601 devpriv->write_byte(devpriv->cmd1, dev->iobase + CMD1_REG); 1602 devpriv->write_byte(devpriv->cmd2, dev->iobase + CMD2_REG); 1603 devpriv->write_byte(devpriv->cmd3, dev->iobase + CMD3_REG); 1604 devpriv->write_byte(devpriv->cmd4, dev->iobase + CMD4_REG); 1605 if (board->is_labpc1200) { 1606 devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); 1607 devpriv->write_byte(devpriv->cmd6, dev->iobase + CMD6_REG); 1608 } 1609 1610 if (irq) { 1611 ret = request_irq(irq, labpc_interrupt, isr_flags, 1612 dev->board_name, dev); 1613 if (ret == 0) 1614 dev->irq = irq; 1615 } 1616 1617 ret = comedi_alloc_subdevices(dev, 5); 1618 if (ret) 1619 return ret; 1620 1621 /* analog input subdevice */ 1622 s = &dev->subdevices[0]; 1623 s->type = COMEDI_SUBD_AI; 1624 s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_COMMON | SDF_DIFF; 1625 s->n_chan = 8; 1626 s->len_chanlist = 8; 1627 s->maxdata = 0x0fff; 1628 s->range_table = board->ai_range_table; 1629 s->insn_read = labpc_ai_insn_read; 1630 if (dev->irq) { 1631 dev->read_subdev = s; 1632 s->subdev_flags |= SDF_CMD_READ; 1633 s->do_cmd = labpc_ai_cmd; 1634 s->do_cmdtest = labpc_ai_cmdtest; 1635 s->cancel = labpc_cancel; 1636 } 1637 1638 /* analog output */ 1639 s = &dev->subdevices[1]; 1640 if (board->has_ao) { 1641 s->type = COMEDI_SUBD_AO; 1642 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_GROUND; 1643 s->n_chan = NUM_AO_CHAN; 1644 s->maxdata = 0x0fff; 1645 s->range_table = &range_labpc_ao; 1646 s->insn_read = labpc_ao_insn_read; 1647 s->insn_write = labpc_ao_insn_write; 1648 1649 /* initialize analog outputs to a known value */ 1650 for (i = 0; i < s->n_chan; i++) { 1651 short lsb, msb; 1652 1653 devpriv->ao_value[i] = s->maxdata / 2; 1654 lsb = devpriv->ao_value[i] & 0xff; 1655 msb = (devpriv->ao_value[i] >> 8) & 0xff; 1656 devpriv->write_byte(lsb, dev->iobase + DAC_LSB_REG(i)); 1657 devpriv->write_byte(msb, dev->iobase + DAC_MSB_REG(i)); 1658 } 1659 } else { 1660 s->type = COMEDI_SUBD_UNUSED; 1661 } 1662 1663 /* 8255 dio */ 1664 s = &dev->subdevices[2]; 1665 ret = subdev_8255_init(dev, s, 1666 (board->has_mmio) ? labpc_8255_mmio : NULL, 1667 dev->iobase + DIO_BASE_REG); 1668 if (ret) 1669 return ret; 1670 1671 /* calibration subdevices for boards that have one */ 1672 s = &dev->subdevices[3]; 1673 if (board->is_labpc1200) { 1674 s->type = COMEDI_SUBD_CALIB; 1675 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; 1676 s->n_chan = 16; 1677 s->maxdata = 0xff; 1678 s->insn_read = labpc_calib_insn_read; 1679 s->insn_write = labpc_calib_insn_write; 1680 1681 for (i = 0; i < s->n_chan; i++) 1682 write_caldac(dev, i, s->maxdata / 2); 1683 } else 1684 s->type = COMEDI_SUBD_UNUSED; 1685 1686 /* EEPROM */ 1687 s = &dev->subdevices[4]; 1688 if (board->is_labpc1200) { 1689 s->type = COMEDI_SUBD_MEMORY; 1690 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; 1691 s->n_chan = EEPROM_SIZE; 1692 s->maxdata = 0xff; 1693 s->insn_read = labpc_eeprom_insn_read; 1694 s->insn_write = labpc_eeprom_insn_write; 1695 1696 for (i = 0; i < s->n_chan; i++) 1697 devpriv->eeprom_data[i] = labpc_eeprom_read(dev, i); 1698 } else 1699 s->type = COMEDI_SUBD_UNUSED; 1700 1701 return 0; 1702} 1703EXPORT_SYMBOL_GPL(labpc_common_attach); 1704 1705void labpc_common_detach(struct comedi_device *dev) 1706{ 1707 comedi_spriv_free(dev, 2); 1708} 1709EXPORT_SYMBOL_GPL(labpc_common_detach); 1710 1711#if IS_ENABLED(CONFIG_COMEDI_NI_LABPC_ISA) 1712static int labpc_attach(struct comedi_device *dev, struct comedi_devconfig *it) 1713{ 1714 struct labpc_private *devpriv; 1715 unsigned int irq = it->options[1]; 1716 unsigned int dma_chan = it->options[2]; 1717 int ret; 1718 1719 devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL); 1720 if (!devpriv) 1721 return -ENOMEM; 1722 dev->private = devpriv; 1723 1724 ret = comedi_request_region(dev, it->options[0], LABPC_SIZE); 1725 if (ret) 1726 return ret; 1727 1728 ret = labpc_common_attach(dev, irq, 0); 1729 if (ret) 1730 return ret; 1731 1732#ifdef CONFIG_ISA_DMA_API 1733 if (dev->irq && (dma_chan == 1 || dma_chan == 3)) { 1734 devpriv->dma_buffer = kmalloc(dma_buffer_size, 1735 GFP_KERNEL | GFP_DMA); 1736 if (devpriv->dma_buffer) { 1737 ret = request_dma(dma_chan, dev->board_name); 1738 if (ret == 0) { 1739 unsigned long dma_flags; 1740 1741 devpriv->dma_chan = dma_chan; 1742 dma_flags = claim_dma_lock(); 1743 disable_dma(devpriv->dma_chan); 1744 set_dma_mode(devpriv->dma_chan, DMA_MODE_READ); 1745 release_dma_lock(dma_flags); 1746 } else { 1747 kfree(devpriv->dma_buffer); 1748 } 1749 } 1750 } 1751#endif 1752 1753 return 0; 1754} 1755 1756static void labpc_detach(struct comedi_device *dev) 1757{ 1758 struct labpc_private *devpriv = dev->private; 1759 1760 labpc_common_detach(dev); 1761 1762 if (devpriv) { 1763 kfree(devpriv->dma_buffer); 1764 if (devpriv->dma_chan) 1765 free_dma(devpriv->dma_chan); 1766 } 1767 comedi_legacy_detach(dev); 1768} 1769 1770static struct comedi_driver labpc_driver = { 1771 .driver_name = "ni_labpc", 1772 .module = THIS_MODULE, 1773 .attach = labpc_attach, 1774 .detach = labpc_detach, 1775 .num_names = ARRAY_SIZE(labpc_boards), 1776 .board_name = &labpc_boards[0].name, 1777 .offset = sizeof(struct labpc_boardinfo), 1778}; 1779module_comedi_driver(labpc_driver); 1780#else 1781static int __init labpc_common_init(void) 1782{ 1783 return 0; 1784} 1785module_init(labpc_common_init); 1786 1787static void __exit labpc_common_exit(void) 1788{ 1789} 1790module_exit(labpc_common_exit); 1791#endif 1792 1793MODULE_AUTHOR("Comedi http://www.comedi.org"); 1794MODULE_DESCRIPTION("Comedi low-level driver"); 1795MODULE_LICENSE("GPL"); 1796