1/* 2 * comedi/drivers/ni_labpc_common.c 3 * 4 * Common support code for "ni_labpc", "ni_labpc_pci" and "ni_labpc_cs". 5 * 6 * Copyright (C) 2001-2003 Frank Mori Hess <fmhess@users.sourceforge.net> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19#include <linux/module.h> 20#include <linux/interrupt.h> 21#include <linux/io.h> 22#include <linux/delay.h> 23 24#include "../comedidev.h" 25 26#include "8253.h" 27#include "8255.h" 28#include "comedi_fc.h" 29#include "ni_labpc.h" 30#include "ni_labpc_regs.h" 31#include "ni_labpc_isadma.h" 32 33enum scan_mode { 34 MODE_SINGLE_CHAN, 35 MODE_SINGLE_CHAN_INTERVAL, 36 MODE_MULT_CHAN_UP, 37 MODE_MULT_CHAN_DOWN, 38}; 39 40static const struct comedi_lrange range_labpc_plus_ai = { 41 16, { 42 BIP_RANGE(5), 43 BIP_RANGE(4), 44 BIP_RANGE(2.5), 45 BIP_RANGE(1), 46 BIP_RANGE(0.5), 47 BIP_RANGE(0.25), 48 BIP_RANGE(0.1), 49 BIP_RANGE(0.05), 50 UNI_RANGE(10), 51 UNI_RANGE(8), 52 UNI_RANGE(5), 53 UNI_RANGE(2), 54 UNI_RANGE(1), 55 UNI_RANGE(0.5), 56 UNI_RANGE(0.2), 57 UNI_RANGE(0.1) 58 } 59}; 60 61static const struct comedi_lrange range_labpc_1200_ai = { 62 14, { 63 BIP_RANGE(5), 64 BIP_RANGE(2.5), 65 BIP_RANGE(1), 66 BIP_RANGE(0.5), 67 BIP_RANGE(0.25), 68 BIP_RANGE(0.1), 69 BIP_RANGE(0.05), 70 UNI_RANGE(10), 71 UNI_RANGE(5), 72 UNI_RANGE(2), 73 UNI_RANGE(1), 74 UNI_RANGE(0.5), 75 UNI_RANGE(0.2), 76 UNI_RANGE(0.1) 77 } 78}; 79 80static const struct comedi_lrange range_labpc_ao = { 81 2, { 82 BIP_RANGE(5), 83 UNI_RANGE(10) 84 } 85}; 86 87/* functions that do inb/outb and readb/writeb so we can use 88 * function pointers to decide which to use */ 89static unsigned int labpc_inb(struct comedi_device *dev, unsigned long reg) 90{ 91 return inb(dev->iobase + reg); 92} 93 94static void labpc_outb(struct comedi_device *dev, 95 unsigned int byte, unsigned long reg) 96{ 97 outb(byte, dev->iobase + reg); 98} 99 100static unsigned int labpc_readb(struct comedi_device *dev, unsigned long reg) 101{ 102 return readb(dev->mmio + reg); 103} 104 105static void labpc_writeb(struct comedi_device *dev, 106 unsigned int byte, unsigned long reg) 107{ 108 writeb(byte, dev->mmio + reg); 109} 110 111static void labpc_counter_load(struct comedi_device *dev, 112 unsigned long reg, 113 unsigned int counter_number, 114 unsigned int count, 115 unsigned int mode) 116{ 117 if (dev->mmio) { 118 i8254_mm_set_mode(dev->mmio + reg, 0, counter_number, mode); 119 i8254_mm_write(dev->mmio + reg, 0, counter_number, count); 120 } else { 121 i8254_set_mode(dev->iobase + reg, 0, counter_number, mode); 122 i8254_write(dev->iobase + reg, 0, counter_number, count); 123 } 124} 125 126static void labpc_counter_set_mode(struct comedi_device *dev, 127 unsigned long reg, 128 unsigned int counter_number, 129 unsigned int mode) 130{ 131 if (dev->mmio) 132 i8254_mm_set_mode(dev->mmio + reg, 0, counter_number, mode); 133 else 134 i8254_set_mode(dev->iobase + reg, 0, counter_number, mode); 135} 136 137static int labpc_cancel(struct comedi_device *dev, struct comedi_subdevice *s) 138{ 139 struct labpc_private *devpriv = dev->private; 140 unsigned long flags; 141 142 spin_lock_irqsave(&dev->spinlock, flags); 143 devpriv->cmd2 &= ~(CMD2_SWTRIG | CMD2_HWTRIG | CMD2_PRETRIG); 144 devpriv->write_byte(dev, devpriv->cmd2, CMD2_REG); 145 spin_unlock_irqrestore(&dev->spinlock, flags); 146 147 devpriv->cmd3 = 0; 148 devpriv->write_byte(dev, devpriv->cmd3, CMD3_REG); 149 150 return 0; 151} 152 153static void labpc_ai_set_chan_and_gain(struct comedi_device *dev, 154 enum scan_mode mode, 155 unsigned int chan, 156 unsigned int range, 157 unsigned int aref) 158{ 159 const struct labpc_boardinfo *board = dev->board_ptr; 160 struct labpc_private *devpriv = dev->private; 161 162 if (board->is_labpc1200) { 163 /* 164 * The LabPC-1200 boards do not have a gain 165 * of '0x10'. Skip the range values that would 166 * result in this gain. 167 */ 168 range += (range > 0) + (range > 7); 169 } 170 171 /* munge channel bits for differential/scan disabled mode */ 172 if ((mode == MODE_SINGLE_CHAN || mode == MODE_SINGLE_CHAN_INTERVAL) && 173 aref == AREF_DIFF) 174 chan *= 2; 175 devpriv->cmd1 = CMD1_MA(chan); 176 devpriv->cmd1 |= CMD1_GAIN(range); 177 178 devpriv->write_byte(dev, devpriv->cmd1, CMD1_REG); 179} 180 181static void labpc_setup_cmd6_reg(struct comedi_device *dev, 182 struct comedi_subdevice *s, 183 enum scan_mode mode, 184 enum transfer_type xfer, 185 unsigned int range, 186 unsigned int aref, 187 bool ena_intr) 188{ 189 const struct labpc_boardinfo *board = dev->board_ptr; 190 struct labpc_private *devpriv = dev->private; 191 192 if (!board->is_labpc1200) 193 return; 194 195 /* reference inputs to ground or common? */ 196 if (aref != AREF_GROUND) 197 devpriv->cmd6 |= CMD6_NRSE; 198 else 199 devpriv->cmd6 &= ~CMD6_NRSE; 200 201 /* bipolar or unipolar range? */ 202 if (comedi_range_is_unipolar(s, range)) 203 devpriv->cmd6 |= CMD6_ADCUNI; 204 else 205 devpriv->cmd6 &= ~CMD6_ADCUNI; 206 207 /* interrupt on fifo half full? */ 208 if (xfer == fifo_half_full_transfer) 209 devpriv->cmd6 |= CMD6_HFINTEN; 210 else 211 devpriv->cmd6 &= ~CMD6_HFINTEN; 212 213 /* enable interrupt on counter a1 terminal count? */ 214 if (ena_intr) 215 devpriv->cmd6 |= CMD6_DQINTEN; 216 else 217 devpriv->cmd6 &= ~CMD6_DQINTEN; 218 219 /* are we scanning up or down through channels? */ 220 if (mode == MODE_MULT_CHAN_UP) 221 devpriv->cmd6 |= CMD6_SCANUP; 222 else 223 devpriv->cmd6 &= ~CMD6_SCANUP; 224 225 devpriv->write_byte(dev, devpriv->cmd6, CMD6_REG); 226} 227 228static unsigned int labpc_read_adc_fifo(struct comedi_device *dev) 229{ 230 struct labpc_private *devpriv = dev->private; 231 unsigned int lsb = devpriv->read_byte(dev, ADC_FIFO_REG); 232 unsigned int msb = devpriv->read_byte(dev, ADC_FIFO_REG); 233 234 return (msb << 8) | lsb; 235} 236 237static void labpc_clear_adc_fifo(struct comedi_device *dev) 238{ 239 struct labpc_private *devpriv = dev->private; 240 241 devpriv->write_byte(dev, 0x1, ADC_FIFO_CLEAR_REG); 242 labpc_read_adc_fifo(dev); 243} 244 245static int labpc_ai_eoc(struct comedi_device *dev, 246 struct comedi_subdevice *s, 247 struct comedi_insn *insn, 248 unsigned long context) 249{ 250 struct labpc_private *devpriv = dev->private; 251 252 devpriv->stat1 = devpriv->read_byte(dev, STAT1_REG); 253 if (devpriv->stat1 & STAT1_DAVAIL) 254 return 0; 255 return -EBUSY; 256} 257 258static int labpc_ai_insn_read(struct comedi_device *dev, 259 struct comedi_subdevice *s, 260 struct comedi_insn *insn, 261 unsigned int *data) 262{ 263 struct labpc_private *devpriv = dev->private; 264 unsigned int chan = CR_CHAN(insn->chanspec); 265 unsigned int range = CR_RANGE(insn->chanspec); 266 unsigned int aref = CR_AREF(insn->chanspec); 267 int ret; 268 int i; 269 270 /* disable timed conversions, interrupt generation and dma */ 271 labpc_cancel(dev, s); 272 273 labpc_ai_set_chan_and_gain(dev, MODE_SINGLE_CHAN, chan, range, aref); 274 275 labpc_setup_cmd6_reg(dev, s, MODE_SINGLE_CHAN, fifo_not_empty_transfer, 276 range, aref, false); 277 278 /* setup cmd4 register */ 279 devpriv->cmd4 = 0; 280 devpriv->cmd4 |= CMD4_ECLKRCV; 281 /* single-ended/differential */ 282 if (aref == AREF_DIFF) 283 devpriv->cmd4 |= CMD4_SEDIFF; 284 devpriv->write_byte(dev, devpriv->cmd4, CMD4_REG); 285 286 /* initialize pacer counter to prevent any problems */ 287 labpc_counter_set_mode(dev, COUNTER_A_BASE_REG, 0, I8254_MODE2); 288 289 labpc_clear_adc_fifo(dev); 290 291 for (i = 0; i < insn->n; i++) { 292 /* trigger conversion */ 293 devpriv->write_byte(dev, 0x1, ADC_START_CONVERT_REG); 294 295 ret = comedi_timeout(dev, s, insn, labpc_ai_eoc, 0); 296 if (ret) 297 return ret; 298 299 data[i] = labpc_read_adc_fifo(dev); 300 } 301 302 return insn->n; 303} 304 305static bool labpc_use_continuous_mode(const struct comedi_cmd *cmd, 306 enum scan_mode mode) 307{ 308 if (mode == MODE_SINGLE_CHAN || cmd->scan_begin_src == TRIG_FOLLOW) 309 return true; 310 311 return false; 312} 313 314static unsigned int labpc_ai_convert_period(const struct comedi_cmd *cmd, 315 enum scan_mode mode) 316{ 317 if (cmd->convert_src != TRIG_TIMER) 318 return 0; 319 320 if (mode == MODE_SINGLE_CHAN && cmd->scan_begin_src == TRIG_TIMER) 321 return cmd->scan_begin_arg; 322 323 return cmd->convert_arg; 324} 325 326static void labpc_set_ai_convert_period(struct comedi_cmd *cmd, 327 enum scan_mode mode, unsigned int ns) 328{ 329 if (cmd->convert_src != TRIG_TIMER) 330 return; 331 332 if (mode == MODE_SINGLE_CHAN && 333 cmd->scan_begin_src == TRIG_TIMER) { 334 cmd->scan_begin_arg = ns; 335 if (cmd->convert_arg > cmd->scan_begin_arg) 336 cmd->convert_arg = cmd->scan_begin_arg; 337 } else { 338 cmd->convert_arg = ns; 339 } 340} 341 342static unsigned int labpc_ai_scan_period(const struct comedi_cmd *cmd, 343 enum scan_mode mode) 344{ 345 if (cmd->scan_begin_src != TRIG_TIMER) 346 return 0; 347 348 if (mode == MODE_SINGLE_CHAN && cmd->convert_src == TRIG_TIMER) 349 return 0; 350 351 return cmd->scan_begin_arg; 352} 353 354static void labpc_set_ai_scan_period(struct comedi_cmd *cmd, 355 enum scan_mode mode, unsigned int ns) 356{ 357 if (cmd->scan_begin_src != TRIG_TIMER) 358 return; 359 360 if (mode == MODE_SINGLE_CHAN && cmd->convert_src == TRIG_TIMER) 361 return; 362 363 cmd->scan_begin_arg = ns; 364} 365 366/* figures out what counter values to use based on command */ 367static void labpc_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd, 368 enum scan_mode mode) 369{ 370 struct labpc_private *devpriv = dev->private; 371 /* max value for 16 bit counter in mode 2 */ 372 const int max_counter_value = 0x10000; 373 /* min value for 16 bit counter in mode 2 */ 374 const int min_counter_value = 2; 375 unsigned int base_period; 376 unsigned int scan_period; 377 unsigned int convert_period; 378 379 /* 380 * if both convert and scan triggers are TRIG_TIMER, then they 381 * both rely on counter b0 382 */ 383 convert_period = labpc_ai_convert_period(cmd, mode); 384 scan_period = labpc_ai_scan_period(cmd, mode); 385 if (convert_period && scan_period) { 386 /* 387 * pick the lowest b0 divisor value we can (for maximum input 388 * clock speed on convert and scan counters) 389 */ 390 devpriv->divisor_b0 = (scan_period - 1) / 391 (I8254_OSC_BASE_2MHZ * max_counter_value) + 1; 392 if (devpriv->divisor_b0 < min_counter_value) 393 devpriv->divisor_b0 = min_counter_value; 394 if (devpriv->divisor_b0 > max_counter_value) 395 devpriv->divisor_b0 = max_counter_value; 396 397 base_period = I8254_OSC_BASE_2MHZ * devpriv->divisor_b0; 398 399 /* set a0 for conversion frequency and b1 for scan frequency */ 400 switch (cmd->flags & CMDF_ROUND_MASK) { 401 default: 402 case CMDF_ROUND_NEAREST: 403 devpriv->divisor_a0 = 404 (convert_period + (base_period / 2)) / base_period; 405 devpriv->divisor_b1 = 406 (scan_period + (base_period / 2)) / base_period; 407 break; 408 case CMDF_ROUND_UP: 409 devpriv->divisor_a0 = 410 (convert_period + (base_period - 1)) / base_period; 411 devpriv->divisor_b1 = 412 (scan_period + (base_period - 1)) / base_period; 413 break; 414 case CMDF_ROUND_DOWN: 415 devpriv->divisor_a0 = convert_period / base_period; 416 devpriv->divisor_b1 = scan_period / base_period; 417 break; 418 } 419 /* make sure a0 and b1 values are acceptable */ 420 if (devpriv->divisor_a0 < min_counter_value) 421 devpriv->divisor_a0 = min_counter_value; 422 if (devpriv->divisor_a0 > max_counter_value) 423 devpriv->divisor_a0 = max_counter_value; 424 if (devpriv->divisor_b1 < min_counter_value) 425 devpriv->divisor_b1 = min_counter_value; 426 if (devpriv->divisor_b1 > max_counter_value) 427 devpriv->divisor_b1 = max_counter_value; 428 /* write corrected timings to command */ 429 labpc_set_ai_convert_period(cmd, mode, 430 base_period * devpriv->divisor_a0); 431 labpc_set_ai_scan_period(cmd, mode, 432 base_period * devpriv->divisor_b1); 433 /* 434 * if only one TRIG_TIMER is used, we can employ the generic 435 * cascaded timing functions 436 */ 437 } else if (scan_period) { 438 /* 439 * calculate cascaded counter values 440 * that give desired scan timing 441 */ 442 i8253_cascade_ns_to_timer(I8254_OSC_BASE_2MHZ, 443 &devpriv->divisor_b1, 444 &devpriv->divisor_b0, 445 &scan_period, cmd->flags); 446 labpc_set_ai_scan_period(cmd, mode, scan_period); 447 } else if (convert_period) { 448 /* 449 * calculate cascaded counter values 450 * that give desired conversion timing 451 */ 452 i8253_cascade_ns_to_timer(I8254_OSC_BASE_2MHZ, 453 &devpriv->divisor_a0, 454 &devpriv->divisor_b0, 455 &convert_period, cmd->flags); 456 labpc_set_ai_convert_period(cmd, mode, convert_period); 457 } 458} 459 460static enum scan_mode labpc_ai_scan_mode(const struct comedi_cmd *cmd) 461{ 462 unsigned int chan0; 463 unsigned int chan1; 464 465 if (cmd->chanlist_len == 1) 466 return MODE_SINGLE_CHAN; 467 468 /* chanlist may be NULL during cmdtest */ 469 if (cmd->chanlist == NULL) 470 return MODE_MULT_CHAN_UP; 471 472 chan0 = CR_CHAN(cmd->chanlist[0]); 473 chan1 = CR_CHAN(cmd->chanlist[1]); 474 475 if (chan0 < chan1) 476 return MODE_MULT_CHAN_UP; 477 478 if (chan0 > chan1) 479 return MODE_MULT_CHAN_DOWN; 480 481 return MODE_SINGLE_CHAN_INTERVAL; 482} 483 484static int labpc_ai_check_chanlist(struct comedi_device *dev, 485 struct comedi_subdevice *s, 486 struct comedi_cmd *cmd) 487{ 488 enum scan_mode mode = labpc_ai_scan_mode(cmd); 489 unsigned int chan0 = CR_CHAN(cmd->chanlist[0]); 490 unsigned int range0 = CR_RANGE(cmd->chanlist[0]); 491 unsigned int aref0 = CR_AREF(cmd->chanlist[0]); 492 int i; 493 494 if (mode == MODE_SINGLE_CHAN) 495 return 0; 496 497 for (i = 0; i < cmd->chanlist_len; i++) { 498 unsigned int chan = CR_CHAN(cmd->chanlist[i]); 499 unsigned int range = CR_RANGE(cmd->chanlist[i]); 500 unsigned int aref = CR_AREF(cmd->chanlist[i]); 501 502 switch (mode) { 503 case MODE_SINGLE_CHAN: 504 break; 505 case MODE_SINGLE_CHAN_INTERVAL: 506 if (chan != chan0) { 507 dev_dbg(dev->class_dev, 508 "channel scanning order specified in chanlist is not supported by hardware\n"); 509 return -EINVAL; 510 } 511 break; 512 case MODE_MULT_CHAN_UP: 513 if (chan != i) { 514 dev_dbg(dev->class_dev, 515 "channel scanning order specified in chanlist is not supported by hardware\n"); 516 return -EINVAL; 517 } 518 break; 519 case MODE_MULT_CHAN_DOWN: 520 if (chan != (cmd->chanlist_len - i - 1)) { 521 dev_dbg(dev->class_dev, 522 "channel scanning order specified in chanlist is not supported by hardware\n"); 523 return -EINVAL; 524 } 525 break; 526 } 527 528 if (range != range0) { 529 dev_dbg(dev->class_dev, 530 "entries in chanlist must all have the same range\n"); 531 return -EINVAL; 532 } 533 534 if (aref != aref0) { 535 dev_dbg(dev->class_dev, 536 "entries in chanlist must all have the same reference\n"); 537 return -EINVAL; 538 } 539 } 540 541 return 0; 542} 543 544static int labpc_ai_cmdtest(struct comedi_device *dev, 545 struct comedi_subdevice *s, struct comedi_cmd *cmd) 546{ 547 const struct labpc_boardinfo *board = dev->board_ptr; 548 int err = 0; 549 int tmp, tmp2; 550 unsigned int stop_mask; 551 enum scan_mode mode; 552 553 /* Step 1 : check if triggers are trivially valid */ 554 555 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_EXT); 556 err |= cfc_check_trigger_src(&cmd->scan_begin_src, 557 TRIG_TIMER | TRIG_FOLLOW | TRIG_EXT); 558 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_TIMER | TRIG_EXT); 559 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT); 560 561 stop_mask = TRIG_COUNT | TRIG_NONE; 562 if (board->is_labpc1200) 563 stop_mask |= TRIG_EXT; 564 err |= cfc_check_trigger_src(&cmd->stop_src, stop_mask); 565 566 if (err) 567 return 1; 568 569 /* Step 2a : make sure trigger sources are unique */ 570 571 err |= cfc_check_trigger_is_unique(cmd->start_src); 572 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src); 573 err |= cfc_check_trigger_is_unique(cmd->convert_src); 574 err |= cfc_check_trigger_is_unique(cmd->stop_src); 575 576 /* Step 2b : and mutually compatible */ 577 578 /* can't have external stop and start triggers at once */ 579 if (cmd->start_src == TRIG_EXT && cmd->stop_src == TRIG_EXT) 580 err++; 581 582 if (err) 583 return 2; 584 585 /* Step 3: check if arguments are trivially valid */ 586 587 switch (cmd->start_src) { 588 case TRIG_NOW: 589 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0); 590 break; 591 case TRIG_EXT: 592 /* start_arg value is ignored */ 593 break; 594 } 595 596 if (!cmd->chanlist_len) 597 err |= -EINVAL; 598 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len); 599 600 if (cmd->convert_src == TRIG_TIMER) 601 err |= cfc_check_trigger_arg_min(&cmd->convert_arg, 602 board->ai_speed); 603 604 /* make sure scan timing is not too fast */ 605 if (cmd->scan_begin_src == TRIG_TIMER) { 606 if (cmd->convert_src == TRIG_TIMER) 607 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg, 608 cmd->convert_arg * cmd->chanlist_len); 609 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg, 610 board->ai_speed * cmd->chanlist_len); 611 } 612 613 switch (cmd->stop_src) { 614 case TRIG_COUNT: 615 err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1); 616 break; 617 case TRIG_NONE: 618 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0); 619 break; 620 /* 621 * TRIG_EXT doesn't care since it doesn't 622 * trigger off a numbered channel 623 */ 624 default: 625 break; 626 } 627 628 if (err) 629 return 3; 630 631 /* step 4: fix up any arguments */ 632 633 tmp = cmd->convert_arg; 634 tmp2 = cmd->scan_begin_arg; 635 mode = labpc_ai_scan_mode(cmd); 636 labpc_adc_timing(dev, cmd, mode); 637 if (tmp != cmd->convert_arg || tmp2 != cmd->scan_begin_arg) 638 err++; 639 640 if (err) 641 return 4; 642 643 /* Step 5: check channel list if it exists */ 644 if (cmd->chanlist && cmd->chanlist_len > 0) 645 err |= labpc_ai_check_chanlist(dev, s, cmd); 646 647 if (err) 648 return 5; 649 650 return 0; 651} 652 653static int labpc_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) 654{ 655 const struct labpc_boardinfo *board = dev->board_ptr; 656 struct labpc_private *devpriv = dev->private; 657 struct comedi_async *async = s->async; 658 struct comedi_cmd *cmd = &async->cmd; 659 enum scan_mode mode = labpc_ai_scan_mode(cmd); 660 unsigned int chanspec = (mode == MODE_MULT_CHAN_UP) ? 661 cmd->chanlist[cmd->chanlist_len - 1] : 662 cmd->chanlist[0]; 663 unsigned int chan = CR_CHAN(chanspec); 664 unsigned int range = CR_RANGE(chanspec); 665 unsigned int aref = CR_AREF(chanspec); 666 enum transfer_type xfer; 667 unsigned long flags; 668 669 /* make sure board is disabled before setting up acquisition */ 670 labpc_cancel(dev, s); 671 672 /* initialize software conversion count */ 673 if (cmd->stop_src == TRIG_COUNT) 674 devpriv->count = cmd->stop_arg * cmd->chanlist_len; 675 676 /* setup hardware conversion counter */ 677 if (cmd->stop_src == TRIG_EXT) { 678 /* 679 * load counter a1 with count of 3 680 * (pc+ manual says this is minimum allowed) using mode 0 681 */ 682 labpc_counter_load(dev, COUNTER_A_BASE_REG, 683 1, 3, I8254_MODE0); 684 } else { 685 /* just put counter a1 in mode 0 to set its output low */ 686 labpc_counter_set_mode(dev, COUNTER_A_BASE_REG, 1, I8254_MODE0); 687 } 688 689 /* figure out what method we will use to transfer data */ 690 if (labpc_have_dma_chan(dev) && 691 /* dma unsafe at RT priority, 692 * and too much setup time for CMDF_WAKE_EOS */ 693 (cmd->flags & (CMDF_WAKE_EOS | CMDF_PRIORITY)) == 0) 694 xfer = isa_dma_transfer; 695 else if (/* pc-plus has no fifo-half full interrupt */ 696 board->is_labpc1200 && 697 /* wake-end-of-scan should interrupt on fifo not empty */ 698 (cmd->flags & CMDF_WAKE_EOS) == 0 && 699 /* make sure we are taking more than just a few points */ 700 (cmd->stop_src != TRIG_COUNT || devpriv->count > 256)) 701 xfer = fifo_half_full_transfer; 702 else 703 xfer = fifo_not_empty_transfer; 704 devpriv->current_transfer = xfer; 705 706 labpc_ai_set_chan_and_gain(dev, mode, chan, range, aref); 707 708 labpc_setup_cmd6_reg(dev, s, mode, xfer, range, aref, 709 (cmd->stop_src == TRIG_EXT)); 710 711 /* manual says to set scan enable bit on second pass */ 712 if (mode == MODE_MULT_CHAN_UP || mode == MODE_MULT_CHAN_DOWN) { 713 devpriv->cmd1 |= CMD1_SCANEN; 714 /* need a brief delay before enabling scan, or scan 715 * list will get screwed when you switch 716 * between scan up to scan down mode - dunno why */ 717 udelay(1); 718 devpriv->write_byte(dev, devpriv->cmd1, CMD1_REG); 719 } 720 721 devpriv->write_byte(dev, cmd->chanlist_len, INTERVAL_COUNT_REG); 722 /* load count */ 723 devpriv->write_byte(dev, 0x1, INTERVAL_STROBE_REG); 724 725 if (cmd->convert_src == TRIG_TIMER || 726 cmd->scan_begin_src == TRIG_TIMER) { 727 /* set up pacing */ 728 labpc_adc_timing(dev, cmd, mode); 729 /* load counter b0 in mode 3 */ 730 labpc_counter_load(dev, COUNTER_B_BASE_REG, 731 0, devpriv->divisor_b0, I8254_MODE3); 732 } 733 /* set up conversion pacing */ 734 if (labpc_ai_convert_period(cmd, mode)) { 735 /* load counter a0 in mode 2 */ 736 labpc_counter_load(dev, COUNTER_A_BASE_REG, 737 0, devpriv->divisor_a0, I8254_MODE2); 738 } else { 739 /* initialize pacer counter to prevent any problems */ 740 labpc_counter_set_mode(dev, COUNTER_A_BASE_REG, 0, I8254_MODE2); 741 } 742 743 /* set up scan pacing */ 744 if (labpc_ai_scan_period(cmd, mode)) { 745 /* load counter b1 in mode 2 */ 746 labpc_counter_load(dev, COUNTER_B_BASE_REG, 747 1, devpriv->divisor_b1, I8254_MODE2); 748 } 749 750 labpc_clear_adc_fifo(dev); 751 752 if (xfer == isa_dma_transfer) 753 labpc_setup_dma(dev, s); 754 755 /* enable error interrupts */ 756 devpriv->cmd3 |= CMD3_ERRINTEN; 757 /* enable fifo not empty interrupt? */ 758 if (xfer == fifo_not_empty_transfer) 759 devpriv->cmd3 |= CMD3_FIFOINTEN; 760 devpriv->write_byte(dev, devpriv->cmd3, CMD3_REG); 761 762 /* setup any external triggering/pacing (cmd4 register) */ 763 devpriv->cmd4 = 0; 764 if (cmd->convert_src != TRIG_EXT) 765 devpriv->cmd4 |= CMD4_ECLKRCV; 766 /* XXX should discard first scan when using interval scanning 767 * since manual says it is not synced with scan clock */ 768 if (!labpc_use_continuous_mode(cmd, mode)) { 769 devpriv->cmd4 |= CMD4_INTSCAN; 770 if (cmd->scan_begin_src == TRIG_EXT) 771 devpriv->cmd4 |= CMD4_EOIRCV; 772 } 773 /* single-ended/differential */ 774 if (aref == AREF_DIFF) 775 devpriv->cmd4 |= CMD4_SEDIFF; 776 devpriv->write_byte(dev, devpriv->cmd4, CMD4_REG); 777 778 /* startup acquisition */ 779 780 spin_lock_irqsave(&dev->spinlock, flags); 781 782 /* use 2 cascaded counters for pacing */ 783 devpriv->cmd2 |= CMD2_TBSEL; 784 785 devpriv->cmd2 &= ~(CMD2_SWTRIG | CMD2_HWTRIG | CMD2_PRETRIG); 786 if (cmd->start_src == TRIG_EXT) 787 devpriv->cmd2 |= CMD2_HWTRIG; 788 else 789 devpriv->cmd2 |= CMD2_SWTRIG; 790 if (cmd->stop_src == TRIG_EXT) 791 devpriv->cmd2 |= (CMD2_HWTRIG | CMD2_PRETRIG); 792 793 devpriv->write_byte(dev, devpriv->cmd2, CMD2_REG); 794 795 spin_unlock_irqrestore(&dev->spinlock, flags); 796 797 return 0; 798} 799 800/* read all available samples from ai fifo */ 801static int labpc_drain_fifo(struct comedi_device *dev) 802{ 803 struct labpc_private *devpriv = dev->private; 804 struct comedi_async *async = dev->read_subdev->async; 805 struct comedi_cmd *cmd = &async->cmd; 806 unsigned short data; 807 const int timeout = 10000; 808 unsigned int i; 809 810 devpriv->stat1 = devpriv->read_byte(dev, STAT1_REG); 811 812 for (i = 0; (devpriv->stat1 & STAT1_DAVAIL) && i < timeout; 813 i++) { 814 /* quit if we have all the data we want */ 815 if (cmd->stop_src == TRIG_COUNT) { 816 if (devpriv->count == 0) 817 break; 818 devpriv->count--; 819 } 820 data = labpc_read_adc_fifo(dev); 821 cfc_write_to_buffer(dev->read_subdev, data); 822 devpriv->stat1 = devpriv->read_byte(dev, STAT1_REG); 823 } 824 if (i == timeout) { 825 dev_err(dev->class_dev, "ai timeout, fifo never empties\n"); 826 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA; 827 return -1; 828 } 829 830 return 0; 831} 832 833/* makes sure all data acquired by board is transferred to comedi (used 834 * when acquisition is terminated by stop_src == TRIG_EXT). */ 835static void labpc_drain_dregs(struct comedi_device *dev) 836{ 837 struct labpc_private *devpriv = dev->private; 838 839 if (devpriv->current_transfer == isa_dma_transfer) 840 labpc_drain_dma(dev); 841 842 labpc_drain_fifo(dev); 843} 844 845/* interrupt service routine */ 846static irqreturn_t labpc_interrupt(int irq, void *d) 847{ 848 struct comedi_device *dev = d; 849 const struct labpc_boardinfo *board = dev->board_ptr; 850 struct labpc_private *devpriv = dev->private; 851 struct comedi_subdevice *s = dev->read_subdev; 852 struct comedi_async *async; 853 struct comedi_cmd *cmd; 854 855 if (!dev->attached) { 856 dev_err(dev->class_dev, "premature interrupt\n"); 857 return IRQ_HANDLED; 858 } 859 860 async = s->async; 861 cmd = &async->cmd; 862 863 /* read board status */ 864 devpriv->stat1 = devpriv->read_byte(dev, STAT1_REG); 865 if (board->is_labpc1200) 866 devpriv->stat2 = devpriv->read_byte(dev, STAT2_REG); 867 868 if ((devpriv->stat1 & (STAT1_GATA0 | STAT1_CNTINT | STAT1_OVERFLOW | 869 STAT1_OVERRUN | STAT1_DAVAIL)) == 0 && 870 (devpriv->stat2 & STAT2_OUTA1) == 0 && 871 (devpriv->stat2 & STAT2_FIFONHF)) { 872 return IRQ_NONE; 873 } 874 875 if (devpriv->stat1 & STAT1_OVERRUN) { 876 /* clear error interrupt */ 877 devpriv->write_byte(dev, 0x1, ADC_FIFO_CLEAR_REG); 878 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA; 879 cfc_handle_events(dev, s); 880 dev_err(dev->class_dev, "overrun\n"); 881 return IRQ_HANDLED; 882 } 883 884 if (devpriv->current_transfer == isa_dma_transfer) 885 labpc_handle_dma_status(dev); 886 else 887 labpc_drain_fifo(dev); 888 889 if (devpriv->stat1 & STAT1_CNTINT) { 890 dev_err(dev->class_dev, "handled timer interrupt?\n"); 891 /* clear it */ 892 devpriv->write_byte(dev, 0x1, TIMER_CLEAR_REG); 893 } 894 895 if (devpriv->stat1 & STAT1_OVERFLOW) { 896 /* clear error interrupt */ 897 devpriv->write_byte(dev, 0x1, ADC_FIFO_CLEAR_REG); 898 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA; 899 cfc_handle_events(dev, s); 900 dev_err(dev->class_dev, "overflow\n"); 901 return IRQ_HANDLED; 902 } 903 /* handle external stop trigger */ 904 if (cmd->stop_src == TRIG_EXT) { 905 if (devpriv->stat2 & STAT2_OUTA1) { 906 labpc_drain_dregs(dev); 907 async->events |= COMEDI_CB_EOA; 908 } 909 } 910 911 /* TRIG_COUNT end of acquisition */ 912 if (cmd->stop_src == TRIG_COUNT) { 913 if (devpriv->count == 0) 914 async->events |= COMEDI_CB_EOA; 915 } 916 917 cfc_handle_events(dev, s); 918 return IRQ_HANDLED; 919} 920 921static int labpc_ao_insn_write(struct comedi_device *dev, 922 struct comedi_subdevice *s, 923 struct comedi_insn *insn, 924 unsigned int *data) 925{ 926 const struct labpc_boardinfo *board = dev->board_ptr; 927 struct labpc_private *devpriv = dev->private; 928 int channel, range; 929 unsigned long flags; 930 int lsb, msb; 931 932 channel = CR_CHAN(insn->chanspec); 933 934 /* turn off pacing of analog output channel */ 935 /* note: hardware bug in daqcard-1200 means pacing cannot 936 * be independently enabled/disabled for its the two channels */ 937 spin_lock_irqsave(&dev->spinlock, flags); 938 devpriv->cmd2 &= ~CMD2_LDAC(channel); 939 devpriv->write_byte(dev, devpriv->cmd2, CMD2_REG); 940 spin_unlock_irqrestore(&dev->spinlock, flags); 941 942 /* set range */ 943 if (board->is_labpc1200) { 944 range = CR_RANGE(insn->chanspec); 945 if (comedi_range_is_unipolar(s, range)) 946 devpriv->cmd6 |= CMD6_DACUNI(channel); 947 else 948 devpriv->cmd6 &= ~CMD6_DACUNI(channel); 949 /* write to register */ 950 devpriv->write_byte(dev, devpriv->cmd6, CMD6_REG); 951 } 952 /* send data */ 953 lsb = data[0] & 0xff; 954 msb = (data[0] >> 8) & 0xff; 955 devpriv->write_byte(dev, lsb, DAC_LSB_REG(channel)); 956 devpriv->write_byte(dev, msb, DAC_MSB_REG(channel)); 957 958 /* remember value for readback */ 959 devpriv->ao_value[channel] = data[0]; 960 961 return 1; 962} 963 964static int labpc_ao_insn_read(struct comedi_device *dev, 965 struct comedi_subdevice *s, 966 struct comedi_insn *insn, 967 unsigned int *data) 968{ 969 struct labpc_private *devpriv = dev->private; 970 971 data[0] = devpriv->ao_value[CR_CHAN(insn->chanspec)]; 972 973 return 1; 974} 975 976/* lowlevel write to eeprom/dac */ 977static void labpc_serial_out(struct comedi_device *dev, unsigned int value, 978 unsigned int value_width) 979{ 980 struct labpc_private *devpriv = dev->private; 981 int i; 982 983 for (i = 1; i <= value_width; i++) { 984 /* clear serial clock */ 985 devpriv->cmd5 &= ~CMD5_SCLK; 986 /* send bits most significant bit first */ 987 if (value & (1 << (value_width - i))) 988 devpriv->cmd5 |= CMD5_SDATA; 989 else 990 devpriv->cmd5 &= ~CMD5_SDATA; 991 udelay(1); 992 devpriv->write_byte(dev, devpriv->cmd5, CMD5_REG); 993 /* set clock to load bit */ 994 devpriv->cmd5 |= CMD5_SCLK; 995 udelay(1); 996 devpriv->write_byte(dev, devpriv->cmd5, CMD5_REG); 997 } 998} 999 1000/* lowlevel read from eeprom */ 1001static unsigned int labpc_serial_in(struct comedi_device *dev) 1002{ 1003 struct labpc_private *devpriv = dev->private; 1004 unsigned int value = 0; 1005 int i; 1006 const int value_width = 8; /* number of bits wide values are */ 1007 1008 for (i = 1; i <= value_width; i++) { 1009 /* set serial clock */ 1010 devpriv->cmd5 |= CMD5_SCLK; 1011 udelay(1); 1012 devpriv->write_byte(dev, devpriv->cmd5, CMD5_REG); 1013 /* clear clock bit */ 1014 devpriv->cmd5 &= ~CMD5_SCLK; 1015 udelay(1); 1016 devpriv->write_byte(dev, devpriv->cmd5, CMD5_REG); 1017 /* read bits most significant bit first */ 1018 udelay(1); 1019 devpriv->stat2 = devpriv->read_byte(dev, STAT2_REG); 1020 if (devpriv->stat2 & STAT2_PROMOUT) 1021 value |= 1 << (value_width - i); 1022 } 1023 1024 return value; 1025} 1026 1027static unsigned int labpc_eeprom_read(struct comedi_device *dev, 1028 unsigned int address) 1029{ 1030 struct labpc_private *devpriv = dev->private; 1031 unsigned int value; 1032 /* bits to tell eeprom to expect a read */ 1033 const int read_instruction = 0x3; 1034 /* 8 bit write lengths to eeprom */ 1035 const int write_length = 8; 1036 1037 /* enable read/write to eeprom */ 1038 devpriv->cmd5 &= ~CMD5_EEPROMCS; 1039 udelay(1); 1040 devpriv->write_byte(dev, devpriv->cmd5, CMD5_REG); 1041 devpriv->cmd5 |= (CMD5_EEPROMCS | CMD5_WRTPRT); 1042 udelay(1); 1043 devpriv->write_byte(dev, devpriv->cmd5, CMD5_REG); 1044 1045 /* send read instruction */ 1046 labpc_serial_out(dev, read_instruction, write_length); 1047 /* send 8 bit address to read from */ 1048 labpc_serial_out(dev, address, write_length); 1049 /* read result */ 1050 value = labpc_serial_in(dev); 1051 1052 /* disable read/write to eeprom */ 1053 devpriv->cmd5 &= ~(CMD5_EEPROMCS | CMD5_WRTPRT); 1054 udelay(1); 1055 devpriv->write_byte(dev, devpriv->cmd5, CMD5_REG); 1056 1057 return value; 1058} 1059 1060static unsigned int labpc_eeprom_read_status(struct comedi_device *dev) 1061{ 1062 struct labpc_private *devpriv = dev->private; 1063 unsigned int value; 1064 const int read_status_instruction = 0x5; 1065 const int write_length = 8; /* 8 bit write lengths to eeprom */ 1066 1067 /* enable read/write to eeprom */ 1068 devpriv->cmd5 &= ~CMD5_EEPROMCS; 1069 udelay(1); 1070 devpriv->write_byte(dev, devpriv->cmd5, CMD5_REG); 1071 devpriv->cmd5 |= (CMD5_EEPROMCS | CMD5_WRTPRT); 1072 udelay(1); 1073 devpriv->write_byte(dev, devpriv->cmd5, CMD5_REG); 1074 1075 /* send read status instruction */ 1076 labpc_serial_out(dev, read_status_instruction, write_length); 1077 /* read result */ 1078 value = labpc_serial_in(dev); 1079 1080 /* disable read/write to eeprom */ 1081 devpriv->cmd5 &= ~(CMD5_EEPROMCS | CMD5_WRTPRT); 1082 udelay(1); 1083 devpriv->write_byte(dev, devpriv->cmd5, CMD5_REG); 1084 1085 return value; 1086} 1087 1088static int labpc_eeprom_write(struct comedi_device *dev, 1089 unsigned int address, unsigned int value) 1090{ 1091 struct labpc_private *devpriv = dev->private; 1092 const int write_enable_instruction = 0x6; 1093 const int write_instruction = 0x2; 1094 const int write_length = 8; /* 8 bit write lengths to eeprom */ 1095 const int write_in_progress_bit = 0x1; 1096 const int timeout = 10000; 1097 int i; 1098 1099 /* make sure there isn't already a write in progress */ 1100 for (i = 0; i < timeout; i++) { 1101 if ((labpc_eeprom_read_status(dev) & write_in_progress_bit) == 1102 0) 1103 break; 1104 } 1105 if (i == timeout) { 1106 dev_err(dev->class_dev, "eeprom write timed out\n"); 1107 return -ETIME; 1108 } 1109 /* update software copy of eeprom */ 1110 devpriv->eeprom_data[address] = value; 1111 1112 /* enable read/write to eeprom */ 1113 devpriv->cmd5 &= ~CMD5_EEPROMCS; 1114 udelay(1); 1115 devpriv->write_byte(dev, devpriv->cmd5, CMD5_REG); 1116 devpriv->cmd5 |= (CMD5_EEPROMCS | CMD5_WRTPRT); 1117 udelay(1); 1118 devpriv->write_byte(dev, devpriv->cmd5, CMD5_REG); 1119 1120 /* send write_enable instruction */ 1121 labpc_serial_out(dev, write_enable_instruction, write_length); 1122 devpriv->cmd5 &= ~CMD5_EEPROMCS; 1123 udelay(1); 1124 devpriv->write_byte(dev, devpriv->cmd5, CMD5_REG); 1125 1126 /* send write instruction */ 1127 devpriv->cmd5 |= CMD5_EEPROMCS; 1128 udelay(1); 1129 devpriv->write_byte(dev, devpriv->cmd5, CMD5_REG); 1130 labpc_serial_out(dev, write_instruction, write_length); 1131 /* send 8 bit address to write to */ 1132 labpc_serial_out(dev, address, write_length); 1133 /* write value */ 1134 labpc_serial_out(dev, value, write_length); 1135 devpriv->cmd5 &= ~CMD5_EEPROMCS; 1136 udelay(1); 1137 devpriv->write_byte(dev, devpriv->cmd5, CMD5_REG); 1138 1139 /* disable read/write to eeprom */ 1140 devpriv->cmd5 &= ~(CMD5_EEPROMCS | CMD5_WRTPRT); 1141 udelay(1); 1142 devpriv->write_byte(dev, devpriv->cmd5, CMD5_REG); 1143 1144 return 0; 1145} 1146 1147/* writes to 8 bit calibration dacs */ 1148static void write_caldac(struct comedi_device *dev, unsigned int channel, 1149 unsigned int value) 1150{ 1151 struct labpc_private *devpriv = dev->private; 1152 1153 if (value == devpriv->caldac[channel]) 1154 return; 1155 devpriv->caldac[channel] = value; 1156 1157 /* clear caldac load bit and make sure we don't write to eeprom */ 1158 devpriv->cmd5 &= ~(CMD5_CALDACLD | CMD5_EEPROMCS | CMD5_WRTPRT); 1159 udelay(1); 1160 devpriv->write_byte(dev, devpriv->cmd5, CMD5_REG); 1161 1162 /* write 4 bit channel */ 1163 labpc_serial_out(dev, channel, 4); 1164 /* write 8 bit caldac value */ 1165 labpc_serial_out(dev, value, 8); 1166 1167 /* set and clear caldac bit to load caldac value */ 1168 devpriv->cmd5 |= CMD5_CALDACLD; 1169 udelay(1); 1170 devpriv->write_byte(dev, devpriv->cmd5, CMD5_REG); 1171 devpriv->cmd5 &= ~CMD5_CALDACLD; 1172 udelay(1); 1173 devpriv->write_byte(dev, devpriv->cmd5, CMD5_REG); 1174} 1175 1176static int labpc_calib_insn_write(struct comedi_device *dev, 1177 struct comedi_subdevice *s, 1178 struct comedi_insn *insn, 1179 unsigned int *data) 1180{ 1181 unsigned int chan = CR_CHAN(insn->chanspec); 1182 1183 /* 1184 * Only write the last data value to the caldac. Preceding 1185 * data would be overwritten anyway. 1186 */ 1187 if (insn->n > 0) 1188 write_caldac(dev, chan, data[insn->n - 1]); 1189 1190 return insn->n; 1191} 1192 1193static int labpc_calib_insn_read(struct comedi_device *dev, 1194 struct comedi_subdevice *s, 1195 struct comedi_insn *insn, 1196 unsigned int *data) 1197{ 1198 struct labpc_private *devpriv = dev->private; 1199 unsigned int chan = CR_CHAN(insn->chanspec); 1200 int i; 1201 1202 for (i = 0; i < insn->n; i++) 1203 data[i] = devpriv->caldac[chan]; 1204 1205 return insn->n; 1206} 1207 1208static int labpc_eeprom_insn_write(struct comedi_device *dev, 1209 struct comedi_subdevice *s, 1210 struct comedi_insn *insn, 1211 unsigned int *data) 1212{ 1213 unsigned int chan = CR_CHAN(insn->chanspec); 1214 int ret; 1215 1216 /* only allow writes to user area of eeprom */ 1217 if (chan < 16 || chan > 127) 1218 return -EINVAL; 1219 1220 /* 1221 * Only write the last data value to the eeprom. Preceding 1222 * data would be overwritten anyway. 1223 */ 1224 if (insn->n > 0) { 1225 ret = labpc_eeprom_write(dev, chan, data[insn->n - 1]); 1226 if (ret) 1227 return ret; 1228 } 1229 1230 return insn->n; 1231} 1232 1233static int labpc_eeprom_insn_read(struct comedi_device *dev, 1234 struct comedi_subdevice *s, 1235 struct comedi_insn *insn, 1236 unsigned int *data) 1237{ 1238 struct labpc_private *devpriv = dev->private; 1239 unsigned int chan = CR_CHAN(insn->chanspec); 1240 int i; 1241 1242 for (i = 0; i < insn->n; i++) 1243 data[i] = devpriv->eeprom_data[chan]; 1244 1245 return insn->n; 1246} 1247 1248int labpc_common_attach(struct comedi_device *dev, 1249 unsigned int irq, unsigned long isr_flags) 1250{ 1251 const struct labpc_boardinfo *board = dev->board_ptr; 1252 struct labpc_private *devpriv = dev->private; 1253 struct comedi_subdevice *s; 1254 int ret; 1255 int i; 1256 1257 if (dev->mmio) { 1258 devpriv->read_byte = labpc_readb; 1259 devpriv->write_byte = labpc_writeb; 1260 } else { 1261 devpriv->read_byte = labpc_inb; 1262 devpriv->write_byte = labpc_outb; 1263 } 1264 1265 /* initialize board's command registers */ 1266 devpriv->write_byte(dev, devpriv->cmd1, CMD1_REG); 1267 devpriv->write_byte(dev, devpriv->cmd2, CMD2_REG); 1268 devpriv->write_byte(dev, devpriv->cmd3, CMD3_REG); 1269 devpriv->write_byte(dev, devpriv->cmd4, CMD4_REG); 1270 if (board->is_labpc1200) { 1271 devpriv->write_byte(dev, devpriv->cmd5, CMD5_REG); 1272 devpriv->write_byte(dev, devpriv->cmd6, CMD6_REG); 1273 } 1274 1275 if (irq) { 1276 ret = request_irq(irq, labpc_interrupt, isr_flags, 1277 dev->board_name, dev); 1278 if (ret == 0) 1279 dev->irq = irq; 1280 } 1281 1282 ret = comedi_alloc_subdevices(dev, 5); 1283 if (ret) 1284 return ret; 1285 1286 /* analog input subdevice */ 1287 s = &dev->subdevices[0]; 1288 s->type = COMEDI_SUBD_AI; 1289 s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_COMMON | SDF_DIFF; 1290 s->n_chan = 8; 1291 s->len_chanlist = 8; 1292 s->maxdata = 0x0fff; 1293 s->range_table = board->is_labpc1200 ? 1294 &range_labpc_1200_ai : &range_labpc_plus_ai; 1295 s->insn_read = labpc_ai_insn_read; 1296 if (dev->irq) { 1297 dev->read_subdev = s; 1298 s->subdev_flags |= SDF_CMD_READ; 1299 s->do_cmd = labpc_ai_cmd; 1300 s->do_cmdtest = labpc_ai_cmdtest; 1301 s->cancel = labpc_cancel; 1302 } 1303 1304 /* analog output */ 1305 s = &dev->subdevices[1]; 1306 if (board->has_ao) { 1307 s->type = COMEDI_SUBD_AO; 1308 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_GROUND; 1309 s->n_chan = NUM_AO_CHAN; 1310 s->maxdata = 0x0fff; 1311 s->range_table = &range_labpc_ao; 1312 s->insn_read = labpc_ao_insn_read; 1313 s->insn_write = labpc_ao_insn_write; 1314 1315 /* initialize analog outputs to a known value */ 1316 for (i = 0; i < s->n_chan; i++) { 1317 short lsb, msb; 1318 1319 devpriv->ao_value[i] = s->maxdata / 2; 1320 lsb = devpriv->ao_value[i] & 0xff; 1321 msb = (devpriv->ao_value[i] >> 8) & 0xff; 1322 devpriv->write_byte(dev, lsb, DAC_LSB_REG(i)); 1323 devpriv->write_byte(dev, msb, DAC_MSB_REG(i)); 1324 } 1325 } else { 1326 s->type = COMEDI_SUBD_UNUSED; 1327 } 1328 1329 /* 8255 dio */ 1330 s = &dev->subdevices[2]; 1331 if (dev->mmio) 1332 ret = subdev_8255_mm_init(dev, s, NULL, DIO_BASE_REG); 1333 else 1334 ret = subdev_8255_init(dev, s, NULL, DIO_BASE_REG); 1335 if (ret) 1336 return ret; 1337 1338 /* calibration subdevices for boards that have one */ 1339 s = &dev->subdevices[3]; 1340 if (board->is_labpc1200) { 1341 s->type = COMEDI_SUBD_CALIB; 1342 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; 1343 s->n_chan = 16; 1344 s->maxdata = 0xff; 1345 s->insn_read = labpc_calib_insn_read; 1346 s->insn_write = labpc_calib_insn_write; 1347 1348 for (i = 0; i < s->n_chan; i++) 1349 write_caldac(dev, i, s->maxdata / 2); 1350 } else { 1351 s->type = COMEDI_SUBD_UNUSED; 1352 } 1353 1354 /* EEPROM */ 1355 s = &dev->subdevices[4]; 1356 if (board->is_labpc1200) { 1357 s->type = COMEDI_SUBD_MEMORY; 1358 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; 1359 s->n_chan = EEPROM_SIZE; 1360 s->maxdata = 0xff; 1361 s->insn_read = labpc_eeprom_insn_read; 1362 s->insn_write = labpc_eeprom_insn_write; 1363 1364 for (i = 0; i < s->n_chan; i++) 1365 devpriv->eeprom_data[i] = labpc_eeprom_read(dev, i); 1366 } else { 1367 s->type = COMEDI_SUBD_UNUSED; 1368 } 1369 1370 return 0; 1371} 1372EXPORT_SYMBOL_GPL(labpc_common_attach); 1373 1374static int __init labpc_common_init(void) 1375{ 1376 return 0; 1377} 1378module_init(labpc_common_init); 1379 1380static void __exit labpc_common_exit(void) 1381{ 1382} 1383module_exit(labpc_common_exit); 1384 1385MODULE_AUTHOR("Comedi http://www.comedi.org"); 1386MODULE_DESCRIPTION("Comedi helper for ni_labpc, ni_labpc_pci, ni_labpc_cs"); 1387MODULE_LICENSE("GPL"); 1388