1/* 2 module/ni_stc.h 3 Register descriptions for NI DAQ-STC chip 4 5 COMEDI - Linux Control and Measurement Device Interface 6 Copyright (C) 1998-9 David A. Schleef <ds@schleef.org> 7 8 This program is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 2 of the License, or 11 (at your option) any later version. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17*/ 18 19/* 20 References: 21 DAQ-STC Technical Reference Manual 22*/ 23 24#ifndef _COMEDI_NI_STC_H 25#define _COMEDI_NI_STC_H 26 27#include "ni_tio.h" 28 29#define _bit15 0x8000 30#define _bit14 0x4000 31#define _bit13 0x2000 32#define _bit12 0x1000 33#define _bit11 0x0800 34#define _bit10 0x0400 35#define _bit9 0x0200 36#define _bit8 0x0100 37#define _bit7 0x0080 38#define _bit6 0x0040 39#define _bit5 0x0020 40#define _bit4 0x0010 41#define _bit3 0x0008 42#define _bit2 0x0004 43#define _bit1 0x0002 44#define _bit0 0x0001 45 46#define NUM_PFI_OUTPUT_SELECT_REGS 6 47 48/* Registers in the National Instruments DAQ-STC chip */ 49 50#define Interrupt_A_Ack_Register 2 51#define G0_Gate_Interrupt_Ack _bit15 52#define G0_TC_Interrupt_Ack _bit14 53#define AI_Error_Interrupt_Ack _bit13 54#define AI_STOP_Interrupt_Ack _bit12 55#define AI_START_Interrupt_Ack _bit11 56#define AI_START2_Interrupt_Ack _bit10 57#define AI_START1_Interrupt_Ack _bit9 58#define AI_SC_TC_Interrupt_Ack _bit8 59#define AI_SC_TC_Error_Confirm _bit7 60#define G0_TC_Error_Confirm _bit6 61#define G0_Gate_Error_Confirm _bit5 62 63#define AI_Status_1_Register 2 64#define Interrupt_A_St 0x8000 65#define AI_FIFO_Full_St 0x4000 66#define AI_FIFO_Half_Full_St 0x2000 67#define AI_FIFO_Empty_St 0x1000 68#define AI_Overrun_St 0x0800 69#define AI_Overflow_St 0x0400 70#define AI_SC_TC_Error_St 0x0200 71#define AI_START2_St 0x0100 72#define AI_START1_St 0x0080 73#define AI_SC_TC_St 0x0040 74#define AI_START_St 0x0020 75#define AI_STOP_St 0x0010 76#define G0_TC_St 0x0008 77#define G0_Gate_Interrupt_St 0x0004 78#define AI_FIFO_Request_St 0x0002 79#define Pass_Thru_0_Interrupt_St 0x0001 80 81#define AI_Status_2_Register 5 82 83#define Interrupt_B_Ack_Register 3 84enum Interrupt_B_Ack_Bits { 85 G1_Gate_Error_Confirm = _bit1, 86 G1_TC_Error_Confirm = _bit2, 87 AO_BC_TC_Trigger_Error_Confirm = _bit3, 88 AO_BC_TC_Error_Confirm = _bit4, 89 AO_UI2_TC_Error_Confrim = _bit5, 90 AO_UI2_TC_Interrupt_Ack = _bit6, 91 AO_UC_TC_Interrupt_Ack = _bit7, 92 AO_BC_TC_Interrupt_Ack = _bit8, 93 AO_START1_Interrupt_Ack = _bit9, 94 AO_UPDATE_Interrupt_Ack = _bit10, 95 AO_START_Interrupt_Ack = _bit11, 96 AO_STOP_Interrupt_Ack = _bit12, 97 AO_Error_Interrupt_Ack = _bit13, 98 G1_TC_Interrupt_Ack = _bit14, 99 G1_Gate_Interrupt_Ack = _bit15 100}; 101 102#define AO_Status_1_Register 3 103#define Interrupt_B_St _bit15 104#define AO_FIFO_Full_St _bit14 105#define AO_FIFO_Half_Full_St _bit13 106#define AO_FIFO_Empty_St _bit12 107#define AO_BC_TC_Error_St _bit11 108#define AO_START_St _bit10 109#define AO_Overrun_St _bit9 110#define AO_START1_St _bit8 111#define AO_BC_TC_St _bit7 112#define AO_UC_TC_St _bit6 113#define AO_UPDATE_St _bit5 114#define AO_UI2_TC_St _bit4 115#define G1_TC_St _bit3 116#define G1_Gate_Interrupt_St _bit2 117#define AO_FIFO_Request_St _bit1 118#define Pass_Thru_1_Interrupt_St _bit0 119 120#define AI_Command_2_Register 4 121#define AI_End_On_SC_TC _bit15 122#define AI_End_On_End_Of_Scan _bit14 123#define AI_START1_Disable _bit11 124#define AI_SC_Save_Trace _bit10 125#define AI_SI_Switch_Load_On_SC_TC _bit9 126#define AI_SI_Switch_Load_On_STOP _bit8 127#define AI_SI_Switch_Load_On_TC _bit7 128#define AI_SC_Switch_Load_On_TC _bit4 129#define AI_STOP_Pulse _bit3 130#define AI_START_Pulse _bit2 131#define AI_START2_Pulse _bit1 132#define AI_START1_Pulse _bit0 133 134#define AO_Command_2_Register 5 135#define AO_End_On_BC_TC(x) (((x) & 0x3) << 14) 136#define AO_Start_Stop_Gate_Enable _bit13 137#define AO_UC_Save_Trace _bit12 138#define AO_BC_Gate_Enable _bit11 139#define AO_BC_Save_Trace _bit10 140#define AO_UI_Switch_Load_On_BC_TC _bit9 141#define AO_UI_Switch_Load_On_Stop _bit8 142#define AO_UI_Switch_Load_On_TC _bit7 143#define AO_UC_Switch_Load_On_BC_TC _bit6 144#define AO_UC_Switch_Load_On_TC _bit5 145#define AO_BC_Switch_Load_On_TC _bit4 146#define AO_Mute_B _bit3 147#define AO_Mute_A _bit2 148#define AO_UPDATE2_Pulse _bit1 149#define AO_START1_Pulse _bit0 150 151#define AO_Status_2_Register 6 152 153#define DIO_Parallel_Input_Register 7 154 155#define AI_Command_1_Register 8 156#define AI_Analog_Trigger_Reset _bit14 157#define AI_Disarm _bit13 158#define AI_SI2_Arm _bit12 159#define AI_SI2_Load _bit11 160#define AI_SI_Arm _bit10 161#define AI_SI_Load _bit9 162#define AI_DIV_Arm _bit8 163#define AI_DIV_Load _bit7 164#define AI_SC_Arm _bit6 165#define AI_SC_Load _bit5 166#define AI_SCAN_IN_PROG_Pulse _bit4 167#define AI_EXTMUX_CLK_Pulse _bit3 168#define AI_LOCALMUX_CLK_Pulse _bit2 169#define AI_SC_TC_Pulse _bit1 170#define AI_CONVERT_Pulse _bit0 171 172#define AO_Command_1_Register 9 173#define AO_Analog_Trigger_Reset _bit15 174#define AO_START_Pulse _bit14 175#define AO_Disarm _bit13 176#define AO_UI2_Arm_Disarm _bit12 177#define AO_UI2_Load _bit11 178#define AO_UI_Arm _bit10 179#define AO_UI_Load _bit9 180#define AO_UC_Arm _bit8 181#define AO_UC_Load _bit7 182#define AO_BC_Arm _bit6 183#define AO_BC_Load _bit5 184#define AO_DAC1_Update_Mode _bit4 185#define AO_LDAC1_Source_Select _bit3 186#define AO_DAC0_Update_Mode _bit2 187#define AO_LDAC0_Source_Select _bit1 188#define AO_UPDATE_Pulse _bit0 189 190#define DIO_Output_Register 10 191#define DIO_Parallel_Data_Out(a) ((a)&0xff) 192#define DIO_Parallel_Data_Mask 0xff 193#define DIO_SDOUT _bit0 194#define DIO_SDIN _bit4 195#define DIO_Serial_Data_Out(a) (((a)&0xff)<<8) 196#define DIO_Serial_Data_Mask 0xff00 197 198#define DIO_Control_Register 11 199#define DIO_Software_Serial_Control _bit11 200#define DIO_HW_Serial_Timebase _bit10 201#define DIO_HW_Serial_Enable _bit9 202#define DIO_HW_Serial_Start _bit8 203#define DIO_Pins_Dir(a) ((a)&0xff) 204#define DIO_Pins_Dir_Mask 0xff 205 206#define AI_Mode_1_Register 12 207#define AI_CONVERT_Source_Select(a) (((a) & 0x1f) << 11) 208#define AI_SI_Source_select(a) (((a) & 0x1f) << 6) 209#define AI_CONVERT_Source_Polarity _bit5 210#define AI_SI_Source_Polarity _bit4 211#define AI_Start_Stop _bit3 212#define AI_Mode_1_Reserved _bit2 213#define AI_Continuous _bit1 214#define AI_Trigger_Once _bit0 215 216#define AI_Mode_2_Register 13 217#define AI_SC_Gate_Enable _bit15 218#define AI_Start_Stop_Gate_Enable _bit14 219#define AI_Pre_Trigger _bit13 220#define AI_External_MUX_Present _bit12 221#define AI_SI2_Initial_Load_Source _bit9 222#define AI_SI2_Reload_Mode _bit8 223#define AI_SI_Initial_Load_Source _bit7 224#define AI_SI_Reload_Mode(a) (((a) & 0x7)<<4) 225#define AI_SI_Write_Switch _bit3 226#define AI_SC_Initial_Load_Source _bit2 227#define AI_SC_Reload_Mode _bit1 228#define AI_SC_Write_Switch _bit0 229 230#define AI_SI_Load_A_Registers 14 231#define AI_SI_Load_B_Registers 16 232#define AI_SC_Load_A_Registers 18 233#define AI_SC_Load_B_Registers 20 234#define AI_SI_Save_Registers 64 235#define AI_SC_Save_Registers 66 236 237#define AI_SI2_Load_A_Register 23 238#define AI_SI2_Load_B_Register 25 239 240#define Joint_Status_1_Register 27 241#define DIO_Serial_IO_In_Progress_St _bit12 242 243#define DIO_Serial_Input_Register 28 244#define Joint_Status_2_Register 29 245enum Joint_Status_2_Bits { 246 AO_TMRDACWRs_In_Progress_St = 0x20, 247}; 248 249#define AO_Mode_1_Register 38 250#define AO_UPDATE_Source_Select(x) (((x)&0x1f)<<11) 251#define AO_UI_Source_Select(x) (((x)&0x1f)<<6) 252#define AO_Multiple_Channels _bit5 253#define AO_UPDATE_Source_Polarity _bit4 254#define AO_UI_Source_Polarity _bit3 255#define AO_UC_Switch_Load_Every_TC _bit2 256#define AO_Continuous _bit1 257#define AO_Trigger_Once _bit0 258 259#define AO_Mode_2_Register 39 260#define AO_FIFO_Mode_Mask (0x3 << 14) 261enum AO_FIFO_Mode_Bits { 262 AO_FIFO_Mode_HF_to_F = (3 << 14), 263 AO_FIFO_Mode_F = (2 << 14), 264 AO_FIFO_Mode_HF = (1 << 14), 265 AO_FIFO_Mode_E = (0 << 14), 266}; 267#define AO_FIFO_Retransmit_Enable _bit13 268#define AO_START1_Disable _bit12 269#define AO_UC_Initial_Load_Source _bit11 270#define AO_UC_Write_Switch _bit10 271#define AO_UI2_Initial_Load_Source _bit9 272#define AO_UI2_Reload_Mode _bit8 273#define AO_UI_Initial_Load_Source _bit7 274#define AO_UI_Reload_Mode(x) (((x) & 0x7) << 4) 275#define AO_UI_Write_Switch _bit3 276#define AO_BC_Initial_Load_Source _bit2 277#define AO_BC_Reload_Mode _bit1 278#define AO_BC_Write_Switch _bit0 279 280#define AO_UI_Load_A_Register 40 281#define AO_UI_Load_A_Register_High 40 282#define AO_UI_Load_A_Register_Low 41 283#define AO_UI_Load_B_Register 42 284#define AO_UI_Save_Registers 16 285#define AO_BC_Load_A_Register 44 286#define AO_BC_Load_A_Register_High 44 287#define AO_BC_Load_A_Register_Low 45 288#define AO_BC_Load_B_Register 46 289#define AO_BC_Load_B_Register_High 46 290#define AO_BC_Load_B_Register_Low 47 291#define AO_BC_Save_Registers 18 292#define AO_UC_Load_A_Register 48 293#define AO_UC_Load_A_Register_High 48 294#define AO_UC_Load_A_Register_Low 49 295#define AO_UC_Load_B_Register 50 296#define AO_UC_Save_Registers 20 297 298#define Clock_and_FOUT_Register 56 299enum Clock_and_FOUT_bits { 300 FOUT_Enable = _bit15, 301 FOUT_Timebase_Select = _bit14, 302 DIO_Serial_Out_Divide_By_2 = _bit13, 303 Slow_Internal_Time_Divide_By_2 = _bit12, 304 Slow_Internal_Timebase = _bit11, 305 G_Source_Divide_By_2 = _bit10, 306 Clock_To_Board_Divide_By_2 = _bit9, 307 Clock_To_Board = _bit8, 308 AI_Output_Divide_By_2 = _bit7, 309 AI_Source_Divide_By_2 = _bit6, 310 AO_Output_Divide_By_2 = _bit5, 311 AO_Source_Divide_By_2 = _bit4, 312 FOUT_Divider_mask = 0xf 313}; 314static inline unsigned FOUT_Divider(unsigned divider) 315{ 316 return divider & FOUT_Divider_mask; 317} 318 319#define IO_Bidirection_Pin_Register 57 320#define RTSI_Trig_Direction_Register 58 321enum RTSI_Trig_Direction_Bits { 322 Drive_RTSI_Clock_Bit = 0x1, 323 Use_RTSI_Clock_Bit = 0x2, 324}; 325static inline unsigned RTSI_Output_Bit(unsigned channel, int is_mseries) 326{ 327 unsigned max_channel; 328 unsigned base_bit_shift; 329 if (is_mseries) { 330 base_bit_shift = 8; 331 max_channel = 7; 332 } else { 333 base_bit_shift = 9; 334 max_channel = 6; 335 } 336 if (channel > max_channel) { 337 printk("%s: bug, invalid RTSI_channel=%i\n", __func__, channel); 338 return 0; 339 } 340 return 1 << (base_bit_shift + channel); 341} 342 343#define Interrupt_Control_Register 59 344#define Interrupt_B_Enable _bit15 345#define Interrupt_B_Output_Select(x) ((x)<<12) 346#define Interrupt_A_Enable _bit11 347#define Interrupt_A_Output_Select(x) ((x)<<8) 348#define Pass_Thru_0_Interrupt_Polarity _bit3 349#define Pass_Thru_1_Interrupt_Polarity _bit2 350#define Interrupt_Output_On_3_Pins _bit1 351#define Interrupt_Output_Polarity _bit0 352 353#define AI_Output_Control_Register 60 354#define AI_START_Output_Select _bit10 355#define AI_SCAN_IN_PROG_Output_Select(x) (((x) & 0x3) << 8) 356#define AI_EXTMUX_CLK_Output_Select(x) (((x) & 0x3) << 6) 357#define AI_LOCALMUX_CLK_Output_Select(x) ((x)<<4) 358#define AI_SC_TC_Output_Select(x) ((x)<<2) 359enum ai_convert_output_selection { 360 AI_CONVERT_Output_High_Z = 0, 361 AI_CONVERT_Output_Ground = 1, 362 AI_CONVERT_Output_Enable_Low = 2, 363 AI_CONVERT_Output_Enable_High = 3 364}; 365static unsigned AI_CONVERT_Output_Select(enum ai_convert_output_selection 366 selection) 367{ 368 return selection & 0x3; 369} 370 371#define AI_START_STOP_Select_Register 62 372#define AI_START_Polarity _bit15 373#define AI_STOP_Polarity _bit14 374#define AI_STOP_Sync _bit13 375#define AI_STOP_Edge _bit12 376#define AI_STOP_Select(a) (((a) & 0x1f)<<7) 377#define AI_START_Sync _bit6 378#define AI_START_Edge _bit5 379#define AI_START_Select(a) ((a) & 0x1f) 380 381#define AI_Trigger_Select_Register 63 382#define AI_START1_Polarity _bit15 383#define AI_START2_Polarity _bit14 384#define AI_START2_Sync _bit13 385#define AI_START2_Edge _bit12 386#define AI_START2_Select(a) (((a) & 0x1f) << 7) 387#define AI_START1_Sync _bit6 388#define AI_START1_Edge _bit5 389#define AI_START1_Select(a) ((a) & 0x1f) 390 391#define AI_DIV_Load_A_Register 64 392 393#define AO_Start_Select_Register 66 394#define AO_UI2_Software_Gate _bit15 395#define AO_UI2_External_Gate_Polarity _bit14 396#define AO_START_Polarity _bit13 397#define AO_AOFREQ_Enable _bit12 398#define AO_UI2_External_Gate_Select(a) (((a) & 0x1f) << 7) 399#define AO_START_Sync _bit6 400#define AO_START_Edge _bit5 401#define AO_START_Select(a) ((a) & 0x1f) 402 403#define AO_Trigger_Select_Register 67 404#define AO_UI2_External_Gate_Enable _bit15 405#define AO_Delayed_START1 _bit14 406#define AO_START1_Polarity _bit13 407#define AO_UI2_Source_Polarity _bit12 408#define AO_UI2_Source_Select(x) (((x)&0x1f)<<7) 409#define AO_START1_Sync _bit6 410#define AO_START1_Edge _bit5 411#define AO_START1_Select(x) (((x)&0x1f)<<0) 412 413#define AO_Mode_3_Register 70 414#define AO_UI2_Switch_Load_Next_TC _bit13 415#define AO_UC_Switch_Load_Every_BC_TC _bit12 416#define AO_Trigger_Length _bit11 417#define AO_Stop_On_Overrun_Error _bit5 418#define AO_Stop_On_BC_TC_Trigger_Error _bit4 419#define AO_Stop_On_BC_TC_Error _bit3 420#define AO_Not_An_UPDATE _bit2 421#define AO_Software_Gate _bit1 422#define AO_Last_Gate_Disable _bit0 /* M Series only */ 423 424#define Joint_Reset_Register 72 425#define Software_Reset _bit11 426#define AO_Configuration_End _bit9 427#define AI_Configuration_End _bit8 428#define AO_Configuration_Start _bit5 429#define AI_Configuration_Start _bit4 430#define G1_Reset _bit3 431#define G0_Reset _bit2 432#define AO_Reset _bit1 433#define AI_Reset _bit0 434 435#define Interrupt_A_Enable_Register 73 436#define Pass_Thru_0_Interrupt_Enable _bit9 437#define G0_Gate_Interrupt_Enable _bit8 438#define AI_FIFO_Interrupt_Enable _bit7 439#define G0_TC_Interrupt_Enable _bit6 440#define AI_Error_Interrupt_Enable _bit5 441#define AI_STOP_Interrupt_Enable _bit4 442#define AI_START_Interrupt_Enable _bit3 443#define AI_START2_Interrupt_Enable _bit2 444#define AI_START1_Interrupt_Enable _bit1 445#define AI_SC_TC_Interrupt_Enable _bit0 446 447#define Interrupt_B_Enable_Register 75 448#define Pass_Thru_1_Interrupt_Enable _bit11 449#define G1_Gate_Interrupt_Enable _bit10 450#define G1_TC_Interrupt_Enable _bit9 451#define AO_FIFO_Interrupt_Enable _bit8 452#define AO_UI2_TC_Interrupt_Enable _bit7 453#define AO_UC_TC_Interrupt_Enable _bit6 454#define AO_Error_Interrupt_Enable _bit5 455#define AO_STOP_Interrupt_Enable _bit4 456#define AO_START_Interrupt_Enable _bit3 457#define AO_UPDATE_Interrupt_Enable _bit2 458#define AO_START1_Interrupt_Enable _bit1 459#define AO_BC_TC_Interrupt_Enable _bit0 460 461#define Second_IRQ_A_Enable_Register 74 462enum Second_IRQ_A_Enable_Bits { 463 AI_SC_TC_Second_Irq_Enable = _bit0, 464 AI_START1_Second_Irq_Enable = _bit1, 465 AI_START2_Second_Irq_Enable = _bit2, 466 AI_START_Second_Irq_Enable = _bit3, 467 AI_STOP_Second_Irq_Enable = _bit4, 468 AI_Error_Second_Irq_Enable = _bit5, 469 G0_TC_Second_Irq_Enable = _bit6, 470 AI_FIFO_Second_Irq_Enable = _bit7, 471 G0_Gate_Second_Irq_Enable = _bit8, 472 Pass_Thru_0_Second_Irq_Enable = _bit9 473}; 474 475#define Second_IRQ_B_Enable_Register 76 476enum Second_IRQ_B_Enable_Bits { 477 AO_BC_TC_Second_Irq_Enable = _bit0, 478 AO_START1_Second_Irq_Enable = _bit1, 479 AO_UPDATE_Second_Irq_Enable = _bit2, 480 AO_START_Second_Irq_Enable = _bit3, 481 AO_STOP_Second_Irq_Enable = _bit4, 482 AO_Error_Second_Irq_Enable = _bit5, 483 AO_UC_TC_Second_Irq_Enable = _bit6, 484 AO_UI2_TC_Second_Irq_Enable = _bit7, 485 AO_FIFO_Second_Irq_Enable = _bit8, 486 G1_TC_Second_Irq_Enable = _bit9, 487 G1_Gate_Second_Irq_Enable = _bit10, 488 Pass_Thru_1_Second_Irq_Enable = _bit11 489}; 490 491#define AI_Personal_Register 77 492#define AI_SHIFTIN_Pulse_Width _bit15 493#define AI_EOC_Polarity _bit14 494#define AI_SOC_Polarity _bit13 495#define AI_SHIFTIN_Polarity _bit12 496#define AI_CONVERT_Pulse_Timebase _bit11 497#define AI_CONVERT_Pulse_Width _bit10 498#define AI_CONVERT_Original_Pulse _bit9 499#define AI_FIFO_Flags_Polarity _bit8 500#define AI_Overrun_Mode _bit7 501#define AI_EXTMUX_CLK_Pulse_Width _bit6 502#define AI_LOCALMUX_CLK_Pulse_Width _bit5 503#define AI_AIFREQ_Polarity _bit4 504 505#define AO_Personal_Register 78 506enum AO_Personal_Bits { 507 AO_Interval_Buffer_Mode = 1 << 3, 508 AO_BC_Source_Select = 1 << 4, 509 AO_UPDATE_Pulse_Width = 1 << 5, 510 AO_UPDATE_Pulse_Timebase = 1 << 6, 511 AO_UPDATE_Original_Pulse = 1 << 7, 512 AO_DMA_PIO_Control = 1 << 8, /* M Series: reserved */ 513 AO_AOFREQ_Polarity = 1 << 9, /* M Series: reserved */ 514 AO_FIFO_Enable = 1 << 10, 515 AO_FIFO_Flags_Polarity = 1 << 11, /* M Series: reserved */ 516 AO_TMRDACWR_Pulse_Width = 1 << 12, 517 AO_Fast_CPU = 1 << 13, /* M Series: reserved */ 518 AO_Number_Of_DAC_Packages = 1 << 14, /* 1 for "single" mode, 0 for "dual" */ 519 AO_Multiple_DACS_Per_Package = 1 << 15 /* m-series only */ 520}; 521#define RTSI_Trig_A_Output_Register 79 522#define RTSI_Trig_B_Output_Register 80 523enum RTSI_Trig_B_Output_Bits { 524 RTSI_Sub_Selection_1_Bit = 0x8000 /* not for m-series */ 525}; 526static inline unsigned RTSI_Trig_Output_Bits(unsigned rtsi_channel, 527 unsigned source) 528{ 529 return (source & 0xf) << ((rtsi_channel % 4) * 4); 530}; 531 532static inline unsigned RTSI_Trig_Output_Mask(unsigned rtsi_channel) 533{ 534 return 0xf << ((rtsi_channel % 4) * 4); 535}; 536 537/* inverse to RTSI_Trig_Output_Bits() */ 538static inline unsigned RTSI_Trig_Output_Source(unsigned rtsi_channel, 539 unsigned bits) 540{ 541 return (bits >> ((rtsi_channel % 4) * 4)) & 0xf; 542}; 543 544#define RTSI_Board_Register 81 545#define Write_Strobe_0_Register 82 546#define Write_Strobe_1_Register 83 547#define Write_Strobe_2_Register 84 548#define Write_Strobe_3_Register 85 549 550#define AO_Output_Control_Register 86 551#define AO_External_Gate_Enable _bit15 552#define AO_External_Gate_Select(x) (((x)&0x1f)<<10) 553#define AO_Number_Of_Channels(x) (((x)&0xf)<<6) 554#define AO_UPDATE2_Output_Select(x) (((x)&0x3)<<4) 555#define AO_External_Gate_Polarity _bit3 556#define AO_UPDATE2_Output_Toggle _bit2 557enum ao_update_output_selection { 558 AO_Update_Output_High_Z = 0, 559 AO_Update_Output_Ground = 1, 560 AO_Update_Output_Enable_Low = 2, 561 AO_Update_Output_Enable_High = 3 562}; 563static unsigned AO_UPDATE_Output_Select(enum ao_update_output_selection 564 selection) 565{ 566 return selection & 0x3; 567} 568 569#define AI_Mode_3_Register 87 570#define AI_Trigger_Length _bit15 571#define AI_Delay_START _bit14 572#define AI_Software_Gate _bit13 573#define AI_SI_Special_Trigger_Delay _bit12 574#define AI_SI2_Source_Select _bit11 575#define AI_Delayed_START2 _bit10 576#define AI_Delayed_START1 _bit9 577#define AI_External_Gate_Mode _bit8 578#define AI_FIFO_Mode_HF_to_E (3<<6) 579#define AI_FIFO_Mode_F (2<<6) 580#define AI_FIFO_Mode_HF (1<<6) 581#define AI_FIFO_Mode_NE (0<<6) 582#define AI_External_Gate_Polarity _bit5 583#define AI_External_Gate_Select(a) ((a) & 0x1f) 584 585#define G_Autoincrement_Register(a) (68+(a)) 586#define G_Command_Register(a) (6+(a)) 587#define G_HW_Save_Register(a) (8+(a)*2) 588#define G_HW_Save_Register_High(a) (8+(a)*2) 589#define G_HW_Save_Register_Low(a) (9+(a)*2) 590#define G_Input_Select_Register(a) (36+(a)) 591#define G_Load_A_Register(a) (28+(a)*4) 592#define G_Load_A_Register_High(a) (28+(a)*4) 593#define G_Load_A_Register_Low(a) (29+(a)*4) 594#define G_Load_B_Register(a) (30+(a)*4) 595#define G_Load_B_Register_High(a) (30+(a)*4) 596#define G_Load_B_Register_Low(a) (31+(a)*4) 597#define G_Mode_Register(a) (26+(a)) 598#define G_Save_Register(a) (12+(a)*2) 599#define G_Save_Register_High(a) (12+(a)*2) 600#define G_Save_Register_Low(a) (13+(a)*2) 601#define G_Status_Register 4 602#define Analog_Trigger_Etc_Register 61 603 604/* command register */ 605#define G_Disarm_Copy _bit15 /* strobe */ 606#define G_Save_Trace_Copy _bit14 607#define G_Arm_Copy _bit13 /* strobe */ 608#define G_Bank_Switch_Start _bit10 /* strobe */ 609#define G_Little_Big_Endian _bit9 610#define G_Synchronized_Gate _bit8 611#define G_Write_Switch _bit7 612#define G_Up_Down(a) (((a)&0x03)<<5) 613#define G_Disarm _bit4 /* strobe */ 614#define G_Analog_Trigger_Reset _bit3 /* strobe */ 615#define G_Save_Trace _bit1 616#define G_Arm _bit0 /* strobe */ 617 618/*channel agnostic names for the command register #defines */ 619#define G_Bank_Switch_Enable _bit12 620#define G_Bank_Switch_Mode _bit11 621#define G_Load _bit2 /* strobe */ 622 623/* input select register */ 624#define G_Gate_Select(a) (((a)&0x1f)<<7) 625#define G_Source_Select(a) (((a)&0x1f)<<2) 626#define G_Write_Acknowledges_Irq _bit1 627#define G_Read_Acknowledges_Irq _bit0 628 629/* same input select register, but with channel agnostic names */ 630#define G_Source_Polarity _bit15 631#define G_Output_Polarity _bit14 632#define G_OR_Gate _bit13 633#define G_Gate_Select_Load_Source _bit12 634 635/* mode register */ 636#define G_Loading_On_TC _bit12 637#define G_Output_Mode(a) (((a)&0x03)<<8) 638#define G_Trigger_Mode_For_Edge_Gate(a) (((a)&0x03)<<3) 639#define G_Gating_Mode(a) (((a)&0x03)<<0) 640 641/* same input mode register, but with channel agnostic names */ 642#define G_Load_Source_Select _bit7 643#define G_Reload_Source_Switching _bit15 644#define G_Loading_On_Gate _bit14 645#define G_Gate_Polarity _bit13 646 647#define G_Counting_Once(a) (((a)&0x03)<<10) 648#define G_Stop_Mode(a) (((a)&0x03)<<5) 649#define G_Gate_On_Both_Edges _bit2 650 651/* G_Status_Register */ 652#define G1_Gate_Error_St _bit15 653#define G0_Gate_Error_St _bit14 654#define G1_TC_Error_St _bit13 655#define G0_TC_Error_St _bit12 656#define G1_No_Load_Between_Gates_St _bit11 657#define G0_No_Load_Between_Gates_St _bit10 658#define G1_Armed_St _bit9 659#define G0_Armed_St _bit8 660#define G1_Stale_Data_St _bit7 661#define G0_Stale_Data_St _bit6 662#define G1_Next_Load_Source_St _bit5 663#define G0_Next_Load_Source_St _bit4 664#define G1_Counting_St _bit3 665#define G0_Counting_St _bit2 666#define G1_Save_St _bit1 667#define G0_Save_St _bit0 668 669/* general purpose counter timer */ 670#define G_Autoincrement(a) ((a)<<0) 671 672/*Analog_Trigger_Etc_Register*/ 673#define Analog_Trigger_Mode(x) ((x) & 0x7) 674#define Analog_Trigger_Enable _bit3 675#define Analog_Trigger_Drive _bit4 676#define GPFO_1_Output_Select _bit7 677#define GPFO_0_Output_Select(a) ((a)<<11) 678#define GPFO_0_Output_Enable _bit14 679#define GPFO_1_Output_Enable _bit15 680 681/* Additional windowed registers unique to E series */ 682 683/* 16 bit registers shadowed from DAQ-STC */ 684#define Window_Address 0x00 685#define Window_Data 0x02 686 687#define Configuration_Memory_Clear 82 688#define ADC_FIFO_Clear 83 689#define DAC_FIFO_Clear 84 690 691/* i/o port offsets */ 692 693/* 8 bit registers */ 694#define XXX_Status 0x01 695enum XXX_Status_Bits { 696 PROMOUT = 0x1, 697 AI_FIFO_LOWER_NOT_EMPTY = 0x8, 698}; 699#define Serial_Command 0x0d 700#define Misc_Command 0x0f 701#define Port_A 0x19 702#define Port_B 0x1b 703#define Port_C 0x1d 704#define Configuration 0x1f 705#define Strobes 0x01 706#define Channel_A_Mode 0x03 707#define Channel_B_Mode 0x05 708#define Channel_C_Mode 0x07 709#define AI_AO_Select 0x09 710enum AI_AO_Select_Bits { 711 AI_DMA_Select_Shift = 0, 712 AI_DMA_Select_Mask = 0xf, 713 AO_DMA_Select_Shift = 4, 714 AO_DMA_Select_Mask = 0xf << AO_DMA_Select_Shift 715}; 716#define G0_G1_Select 0x0b 717static inline unsigned ni_stc_dma_channel_select_bitfield(unsigned channel) 718{ 719 if (channel < 4) 720 return 1 << channel; 721 if (channel == 4) 722 return 0x3; 723 if (channel == 5) 724 return 0x5; 725 BUG(); 726 return 0; 727} 728 729static inline unsigned GPCT_DMA_Select_Bits(unsigned gpct_index, 730 unsigned mite_channel) 731{ 732 BUG_ON(gpct_index > 1); 733 return ni_stc_dma_channel_select_bitfield(mite_channel) << (4 * 734 gpct_index); 735} 736 737static inline unsigned GPCT_DMA_Select_Mask(unsigned gpct_index) 738{ 739 BUG_ON(gpct_index > 1); 740 return 0xf << (4 * gpct_index); 741} 742 743/* 16 bit registers */ 744 745#define Configuration_Memory_Low 0x10 746enum Configuration_Memory_Low_Bits { 747 AI_DITHER = 0x200, 748 AI_LAST_CHANNEL = 0x8000, 749}; 750#define Configuration_Memory_High 0x12 751enum Configuration_Memory_High_Bits { 752 AI_AC_COUPLE = 0x800, 753 AI_DIFFERENTIAL = 0x1000, 754 AI_COMMON = 0x2000, 755 AI_GROUND = 0x3000, 756}; 757static inline unsigned int AI_CONFIG_CHANNEL(unsigned int channel) 758{ 759 return channel & 0x3f; 760} 761 762#define ADC_FIFO_Data_Register 0x1c 763 764#define AO_Configuration 0x16 765#define AO_Bipolar _bit0 766#define AO_Deglitch _bit1 767#define AO_Ext_Ref _bit2 768#define AO_Ground_Ref _bit3 769#define AO_Channel(x) ((x) << 8) 770 771#define DAC_FIFO_Data 0x1e 772#define DAC0_Direct_Data 0x18 773#define DAC1_Direct_Data 0x1a 774 775/* 611x registers (these boards differ from the e-series) */ 776 777#define Magic_611x 0x19 /* w8 (new) */ 778#define Calibration_Channel_Select_611x 0x1a /* w16 (new) */ 779#define ADC_FIFO_Data_611x 0x1c /* r32 (incompatible) */ 780#define AI_FIFO_Offset_Load_611x 0x05 /* r8 (new) */ 781#define DAC_FIFO_Data_611x 0x14 /* w32 (incompatible) */ 782#define Cal_Gain_Select_611x 0x05 /* w8 (new) */ 783 784#define AO_Window_Address_611x 0x18 785#define AO_Window_Data_611x 0x1e 786 787/* 6143 registers */ 788#define Magic_6143 0x19 /* w8 */ 789#define G0G1_DMA_Select_6143 0x0B /* w8 */ 790#define PipelineDelay_6143 0x1f /* w8 */ 791#define EOC_Set_6143 0x1D /* w8 */ 792#define AIDMA_Select_6143 0x09 /* w8 */ 793#define AIFIFO_Data_6143 0x8C /* w32 */ 794#define AIFIFO_Flag_6143 0x84 /* w32 */ 795#define AIFIFO_Control_6143 0x88 /* w32 */ 796#define AIFIFO_Status_6143 0x88 /* w32 */ 797#define AIFIFO_DMAThreshold_6143 0x90 /* w32 */ 798#define AIFIFO_Words_Available_6143 0x94 /* w32 */ 799 800#define Calibration_Channel_6143 0x42 /* w16 */ 801#define Calibration_LowTime_6143 0x20 /* w16 */ 802#define Calibration_HighTime_6143 0x22 /* w16 */ 803#define Relay_Counter_Load_Val__6143 0x4C /* w32 */ 804#define Signature_6143 0x50 /* w32 */ 805#define Release_Date_6143 0x54 /* w32 */ 806#define Release_Oldest_Date_6143 0x58 /* w32 */ 807 808#define Calibration_Channel_6143_RelayOn 0x8000 /* Calibration relay switch On */ 809#define Calibration_Channel_6143_RelayOff 0x4000 /* Calibration relay switch Off */ 810#define Calibration_Channel_Gnd_Gnd 0x00 /* Offset Calibration */ 811#define Calibration_Channel_2v5_Gnd 0x02 /* 2.5V Reference */ 812#define Calibration_Channel_Pwm_Gnd 0x05 /* +/- 5V Self Cal */ 813#define Calibration_Channel_2v5_Pwm 0x0a /* PWM Calibration */ 814#define Calibration_Channel_Pwm_Pwm 0x0d /* CMRR */ 815#define Calibration_Channel_Gnd_Pwm 0x0e /* PWM Calibration */ 816 817/* 671x, 611x registers */ 818 819/* 671xi, 611x windowed ao registers */ 820enum windowed_regs_67xx_61xx { 821 AO_Immediate_671x = 0x11, /* W 16 */ 822 AO_Timed_611x = 0x10, /* W 16 */ 823 AO_FIFO_Offset_Load_611x = 0x13, /* W32 */ 824 AO_Later_Single_Point_Updates = 0x14, /* W 16 */ 825 AO_Waveform_Generation_611x = 0x15, /* W 16 */ 826 AO_Misc_611x = 0x16, /* W 16 */ 827 AO_Calibration_Channel_Select_67xx = 0x17, /* W 16 */ 828 AO_Configuration_2_67xx = 0x18, /* W 16 */ 829 CAL_ADC_Command_67xx = 0x19, /* W 8 */ 830 CAL_ADC_Status_67xx = 0x1a, /* R 8 */ 831 CAL_ADC_Data_67xx = 0x1b, /* R 16 */ 832 CAL_ADC_Config_Data_High_Word_67xx = 0x1c, /* RW 16 */ 833 CAL_ADC_Config_Data_Low_Word_67xx = 0x1d, /* RW 16 */ 834}; 835static inline unsigned int DACx_Direct_Data_671x(int channel) 836{ 837 return channel; 838} 839 840enum AO_Misc_611x_Bits { 841 CLEAR_WG = 1, 842}; 843enum cs5529_configuration_bits { 844 CSCFG_CAL_CONTROL_MASK = 0x7, 845 CSCFG_SELF_CAL_OFFSET = 0x1, 846 CSCFG_SELF_CAL_GAIN = 0x2, 847 CSCFG_SELF_CAL_OFFSET_GAIN = 0x3, 848 CSCFG_SYSTEM_CAL_OFFSET = 0x5, 849 CSCFG_SYSTEM_CAL_GAIN = 0x6, 850 CSCFG_DONE = 1 << 3, 851 CSCFG_POWER_SAVE_SELECT = 1 << 4, 852 CSCFG_PORT_MODE = 1 << 5, 853 CSCFG_RESET_VALID = 1 << 6, 854 CSCFG_RESET = 1 << 7, 855 CSCFG_UNIPOLAR = 1 << 12, 856 CSCFG_WORD_RATE_2180_CYCLES = 0x0 << 13, 857 CSCFG_WORD_RATE_1092_CYCLES = 0x1 << 13, 858 CSCFG_WORD_RATE_532_CYCLES = 0x2 << 13, 859 CSCFG_WORD_RATE_388_CYCLES = 0x3 << 13, 860 CSCFG_WORD_RATE_324_CYCLES = 0x4 << 13, 861 CSCFG_WORD_RATE_17444_CYCLES = 0x5 << 13, 862 CSCFG_WORD_RATE_8724_CYCLES = 0x6 << 13, 863 CSCFG_WORD_RATE_4364_CYCLES = 0x7 << 13, 864 CSCFG_WORD_RATE_MASK = 0x7 << 13, 865 CSCFG_LOW_POWER = 1 << 16, 866}; 867static inline unsigned int CS5529_CONFIG_DOUT(int output) 868{ 869 return 1 << (18 + output); 870} 871 872static inline unsigned int CS5529_CONFIG_AOUT(int output) 873{ 874 return 1 << (22 + output); 875} 876 877enum cs5529_command_bits { 878 CSCMD_POWER_SAVE = 0x1, 879 CSCMD_REGISTER_SELECT_MASK = 0xe, 880 CSCMD_OFFSET_REGISTER = 0x0, 881 CSCMD_GAIN_REGISTER = 0x2, 882 CSCMD_CONFIG_REGISTER = 0x4, 883 CSCMD_READ = 0x10, 884 CSCMD_CONTINUOUS_CONVERSIONS = 0x20, 885 CSCMD_SINGLE_CONVERSION = 0x40, 886 CSCMD_COMMAND = 0x80, 887}; 888enum cs5529_status_bits { 889 CSS_ADC_BUSY = 0x1, 890 CSS_OSC_DETECT = 0x2, /* indicates adc error */ 891 CSS_OVERRANGE = 0x4, 892}; 893#define SerDacLd(x) (0x08<<(x)) 894 895/* 896 This is stuff unique to the NI E series drivers, 897 but I thought I'd put it here anyway. 898*/ 899 900enum { ai_gain_16 = 901 0, ai_gain_8, ai_gain_14, ai_gain_4, ai_gain_611x, ai_gain_622x, 902 ai_gain_628x, ai_gain_6143 903}; 904enum caldac_enum { caldac_none = 0, mb88341, dac8800, dac8043, ad8522, 905 ad8804, ad8842, ad8804_debug 906}; 907enum ni_reg_type { 908 ni_reg_normal = 0x0, 909 ni_reg_611x = 0x1, 910 ni_reg_6711 = 0x2, 911 ni_reg_6713 = 0x4, 912 ni_reg_67xx_mask = 0x6, 913 ni_reg_6xxx_mask = 0x7, 914 ni_reg_622x = 0x8, 915 ni_reg_625x = 0x10, 916 ni_reg_628x = 0x18, 917 ni_reg_m_series_mask = 0x18, 918 ni_reg_6143 = 0x20 919}; 920 921static const struct comedi_lrange range_ni_E_ao_ext; 922 923enum m_series_register_offsets { 924 M_Offset_CDIO_DMA_Select = 0x7, /* write */ 925 M_Offset_SCXI_Status = 0x7, /* read */ 926 M_Offset_AI_AO_Select = 0x9, /* write, same offset as e-series */ 927 M_Offset_SCXI_Serial_Data_In = 0x9, /* read */ 928 M_Offset_G0_G1_Select = 0xb, /* write, same offset as e-series */ 929 M_Offset_Misc_Command = 0xf, 930 M_Offset_SCXI_Serial_Data_Out = 0x11, 931 M_Offset_SCXI_Control = 0x13, 932 M_Offset_SCXI_Output_Enable = 0x15, 933 M_Offset_AI_FIFO_Data = 0x1c, 934 M_Offset_Static_Digital_Output = 0x24, /* write */ 935 M_Offset_Static_Digital_Input = 0x24, /* read */ 936 M_Offset_DIO_Direction = 0x28, 937 M_Offset_Cal_PWM = 0x40, 938 M_Offset_AI_Config_FIFO_Data = 0x5e, 939 M_Offset_Interrupt_C_Enable = 0x88, /* write */ 940 M_Offset_Interrupt_C_Status = 0x88, /* read */ 941 M_Offset_Analog_Trigger_Control = 0x8c, 942 M_Offset_AO_Serial_Interrupt_Enable = 0xa0, 943 M_Offset_AO_Serial_Interrupt_Ack = 0xa1, /* write */ 944 M_Offset_AO_Serial_Interrupt_Status = 0xa1, /* read */ 945 M_Offset_AO_Calibration = 0xa3, 946 M_Offset_AO_FIFO_Data = 0xa4, 947 M_Offset_PFI_Filter = 0xb0, 948 M_Offset_RTSI_Filter = 0xb4, 949 M_Offset_SCXI_Legacy_Compatibility = 0xbc, 950 M_Offset_Interrupt_A_Ack = 0x104, /* write */ 951 M_Offset_AI_Status_1 = 0x104, /* read */ 952 M_Offset_Interrupt_B_Ack = 0x106, /* write */ 953 M_Offset_AO_Status_1 = 0x106, /* read */ 954 M_Offset_AI_Command_2 = 0x108, /* write */ 955 M_Offset_G01_Status = 0x108, /* read */ 956 M_Offset_AO_Command_2 = 0x10a, 957 M_Offset_AO_Status_2 = 0x10c, /* read */ 958 M_Offset_G0_Command = 0x10c, /* write */ 959 M_Offset_G1_Command = 0x10e, /* write */ 960 M_Offset_G0_HW_Save = 0x110, 961 M_Offset_G0_HW_Save_High = 0x110, 962 M_Offset_AI_Command_1 = 0x110, 963 M_Offset_G0_HW_Save_Low = 0x112, 964 M_Offset_AO_Command_1 = 0x112, 965 M_Offset_G1_HW_Save = 0x114, 966 M_Offset_G1_HW_Save_High = 0x114, 967 M_Offset_G1_HW_Save_Low = 0x116, 968 M_Offset_AI_Mode_1 = 0x118, 969 M_Offset_G0_Save = 0x118, 970 M_Offset_G0_Save_High = 0x118, 971 M_Offset_AI_Mode_2 = 0x11a, 972 M_Offset_G0_Save_Low = 0x11a, 973 M_Offset_AI_SI_Load_A = 0x11c, 974 M_Offset_G1_Save = 0x11c, 975 M_Offset_G1_Save_High = 0x11c, 976 M_Offset_G1_Save_Low = 0x11e, 977 M_Offset_AI_SI_Load_B = 0x120, /* write */ 978 M_Offset_AO_UI_Save = 0x120, /* read */ 979 M_Offset_AI_SC_Load_A = 0x124, /* write */ 980 M_Offset_AO_BC_Save = 0x124, /* read */ 981 M_Offset_AI_SC_Load_B = 0x128, /* write */ 982 M_Offset_AO_UC_Save = 0x128, /* read */ 983 M_Offset_AI_SI2_Load_A = 0x12c, 984 M_Offset_AI_SI2_Load_B = 0x130, 985 M_Offset_G0_Mode = 0x134, 986 M_Offset_G1_Mode = 0x136, /* write */ 987 M_Offset_Joint_Status_1 = 0x136, /* read */ 988 M_Offset_G0_Load_A = 0x138, 989 M_Offset_Joint_Status_2 = 0x13a, 990 M_Offset_G0_Load_B = 0x13c, 991 M_Offset_G1_Load_A = 0x140, 992 M_Offset_G1_Load_B = 0x144, 993 M_Offset_G0_Input_Select = 0x148, 994 M_Offset_G1_Input_Select = 0x14a, 995 M_Offset_AO_Mode_1 = 0x14c, 996 M_Offset_AO_Mode_2 = 0x14e, 997 M_Offset_AO_UI_Load_A = 0x150, 998 M_Offset_AO_UI_Load_B = 0x154, 999 M_Offset_AO_BC_Load_A = 0x158, 1000 M_Offset_AO_BC_Load_B = 0x15c, 1001 M_Offset_AO_UC_Load_A = 0x160, 1002 M_Offset_AO_UC_Load_B = 0x164, 1003 M_Offset_Clock_and_FOUT = 0x170, 1004 M_Offset_IO_Bidirection_Pin = 0x172, 1005 M_Offset_RTSI_Trig_Direction = 0x174, 1006 M_Offset_Interrupt_Control = 0x176, 1007 M_Offset_AI_Output_Control = 0x178, 1008 M_Offset_Analog_Trigger_Etc = 0x17a, 1009 M_Offset_AI_START_STOP_Select = 0x17c, 1010 M_Offset_AI_Trigger_Select = 0x17e, 1011 M_Offset_AI_SI_Save = 0x180, /* read */ 1012 M_Offset_AI_DIV_Load_A = 0x180, /* write */ 1013 M_Offset_AI_SC_Save = 0x184, /* read */ 1014 M_Offset_AO_Start_Select = 0x184, /* write */ 1015 M_Offset_AO_Trigger_Select = 0x186, 1016 M_Offset_AO_Mode_3 = 0x18c, 1017 M_Offset_G0_Autoincrement = 0x188, 1018 M_Offset_G1_Autoincrement = 0x18a, 1019 M_Offset_Joint_Reset = 0x190, 1020 M_Offset_Interrupt_A_Enable = 0x192, 1021 M_Offset_Interrupt_B_Enable = 0x196, 1022 M_Offset_AI_Personal = 0x19a, 1023 M_Offset_AO_Personal = 0x19c, 1024 M_Offset_RTSI_Trig_A_Output = 0x19e, 1025 M_Offset_RTSI_Trig_B_Output = 0x1a0, 1026 M_Offset_RTSI_Shared_MUX = 0x1a2, 1027 M_Offset_AO_Output_Control = 0x1ac, 1028 M_Offset_AI_Mode_3 = 0x1ae, 1029 M_Offset_Configuration_Memory_Clear = 0x1a4, 1030 M_Offset_AI_FIFO_Clear = 0x1a6, 1031 M_Offset_AO_FIFO_Clear = 0x1a8, 1032 M_Offset_G0_Counting_Mode = 0x1b0, 1033 M_Offset_G1_Counting_Mode = 0x1b2, 1034 M_Offset_G0_Second_Gate = 0x1b4, 1035 M_Offset_G1_Second_Gate = 0x1b6, 1036 M_Offset_G0_DMA_Config = 0x1b8, /* write */ 1037 M_Offset_G0_DMA_Status = 0x1b8, /* read */ 1038 M_Offset_G1_DMA_Config = 0x1ba, /* write */ 1039 M_Offset_G1_DMA_Status = 0x1ba, /* read */ 1040 M_Offset_G0_MSeries_ABZ = 0x1c0, 1041 M_Offset_G1_MSeries_ABZ = 0x1c2, 1042 M_Offset_Clock_and_Fout2 = 0x1c4, 1043 M_Offset_PLL_Control = 0x1c6, 1044 M_Offset_PLL_Status = 0x1c8, 1045 M_Offset_PFI_Output_Select_1 = 0x1d0, 1046 M_Offset_PFI_Output_Select_2 = 0x1d2, 1047 M_Offset_PFI_Output_Select_3 = 0x1d4, 1048 M_Offset_PFI_Output_Select_4 = 0x1d6, 1049 M_Offset_PFI_Output_Select_5 = 0x1d8, 1050 M_Offset_PFI_Output_Select_6 = 0x1da, 1051 M_Offset_PFI_DI = 0x1dc, 1052 M_Offset_PFI_DO = 0x1de, 1053 M_Offset_AI_Config_FIFO_Bypass = 0x218, 1054 M_Offset_SCXI_DIO_Enable = 0x21c, 1055 M_Offset_CDI_FIFO_Data = 0x220, /* read */ 1056 M_Offset_CDO_FIFO_Data = 0x220, /* write */ 1057 M_Offset_CDIO_Status = 0x224, /* read */ 1058 M_Offset_CDIO_Command = 0x224, /* write */ 1059 M_Offset_CDI_Mode = 0x228, 1060 M_Offset_CDO_Mode = 0x22c, 1061 M_Offset_CDI_Mask_Enable = 0x230, 1062 M_Offset_CDO_Mask_Enable = 0x234, 1063}; 1064static inline int M_Offset_AO_Waveform_Order(int channel) 1065{ 1066 return 0xc2 + 0x4 * channel; 1067}; 1068 1069static inline int M_Offset_AO_Config_Bank(int channel) 1070{ 1071 return 0xc3 + 0x4 * channel; 1072}; 1073 1074static inline int M_Offset_DAC_Direct_Data(int channel) 1075{ 1076 return 0xc0 + 0x4 * channel; 1077} 1078 1079static inline int M_Offset_Gen_PWM(int channel) 1080{ 1081 return 0x44 + 0x2 * channel; 1082} 1083 1084static inline int M_Offset_Static_AI_Control(int i) 1085{ 1086 int offset[] = { 1087 0x64, 1088 0x261, 1089 0x262, 1090 0x263, 1091 }; 1092 if (((unsigned)i) >= ARRAY_SIZE(offset)) { 1093 printk("%s: invalid channel=%i\n", __func__, i); 1094 return offset[0]; 1095 } 1096 return offset[i]; 1097}; 1098 1099static inline int M_Offset_AO_Reference_Attenuation(int channel) 1100{ 1101 int offset[] = { 1102 0x264, 1103 0x265, 1104 0x266, 1105 0x267 1106 }; 1107 if (((unsigned)channel) >= ARRAY_SIZE(offset)) { 1108 printk("%s: invalid channel=%i\n", __func__, channel); 1109 return offset[0]; 1110 } 1111 return offset[channel]; 1112}; 1113 1114static inline unsigned M_Offset_PFI_Output_Select(unsigned n) 1115{ 1116 if (n < 1 || n > NUM_PFI_OUTPUT_SELECT_REGS) { 1117 printk("%s: invalid pfi output select register=%i\n", 1118 __func__, n); 1119 return M_Offset_PFI_Output_Select_1; 1120 } 1121 return M_Offset_PFI_Output_Select_1 + (n - 1) * 2; 1122} 1123 1124enum MSeries_AI_Config_FIFO_Data_Bits { 1125 MSeries_AI_Config_Channel_Type_Mask = 0x7 << 6, 1126 MSeries_AI_Config_Channel_Type_Calibration_Bits = 0x0, 1127 MSeries_AI_Config_Channel_Type_Differential_Bits = 0x1 << 6, 1128 MSeries_AI_Config_Channel_Type_Common_Ref_Bits = 0x2 << 6, 1129 MSeries_AI_Config_Channel_Type_Ground_Ref_Bits = 0x3 << 6, 1130 MSeries_AI_Config_Channel_Type_Aux_Bits = 0x5 << 6, 1131 MSeries_AI_Config_Channel_Type_Ghost_Bits = 0x7 << 6, 1132 MSeries_AI_Config_Polarity_Bit = 0x1000, /* 0 for 2's complement encoding */ 1133 MSeries_AI_Config_Dither_Bit = 0x2000, 1134 MSeries_AI_Config_Last_Channel_Bit = 0x4000, 1135}; 1136static inline unsigned MSeries_AI_Config_Channel_Bits(unsigned channel) 1137{ 1138 return channel & 0xf; 1139} 1140 1141static inline unsigned MSeries_AI_Config_Bank_Bits(enum ni_reg_type reg_type, 1142 unsigned channel) 1143{ 1144 unsigned bits = channel & 0x30; 1145 if (reg_type == ni_reg_622x) { 1146 if (channel & 0x40) 1147 bits |= 0x400; 1148 } 1149 return bits; 1150} 1151 1152static inline unsigned MSeries_AI_Config_Gain_Bits(unsigned range) 1153{ 1154 return (range & 0x7) << 9; 1155} 1156 1157enum MSeries_Clock_and_Fout2_Bits { 1158 MSeries_PLL_In_Source_Select_RTSI0_Bits = 0xb, 1159 MSeries_PLL_In_Source_Select_Star_Trigger_Bits = 0x14, 1160 MSeries_PLL_In_Source_Select_RTSI7_Bits = 0x1b, 1161 MSeries_PLL_In_Source_Select_PXI_Clock10 = 0x1d, 1162 MSeries_PLL_In_Source_Select_Mask = 0x1f, 1163 MSeries_Timebase1_Select_Bit = 0x20, /* use PLL for timebase 1 */ 1164 MSeries_Timebase3_Select_Bit = 0x40, /* use PLL for timebase 3 */ 1165 /* use 10MHz instead of 20MHz for RTSI clock frequency. Appears 1166 to have no effect, at least on pxi-6281, which always uses 1167 20MHz rtsi clock frequency */ 1168 MSeries_RTSI_10MHz_Bit = 0x80 1169}; 1170static inline unsigned MSeries_PLL_In_Source_Select_RTSI_Bits(unsigned 1171 RTSI_channel) 1172{ 1173 if (RTSI_channel > 7) { 1174 printk("%s: bug, invalid RTSI_channel=%i\n", __func__, 1175 RTSI_channel); 1176 return 0; 1177 } 1178 if (RTSI_channel == 7) 1179 return MSeries_PLL_In_Source_Select_RTSI7_Bits; 1180 else 1181 return MSeries_PLL_In_Source_Select_RTSI0_Bits + RTSI_channel; 1182} 1183 1184enum MSeries_PLL_Control_Bits { 1185 MSeries_PLL_Enable_Bit = 0x1000, 1186 MSeries_PLL_VCO_Mode_200_325MHz_Bits = 0x0, 1187 MSeries_PLL_VCO_Mode_175_225MHz_Bits = 0x2000, 1188 MSeries_PLL_VCO_Mode_100_225MHz_Bits = 0x4000, 1189 MSeries_PLL_VCO_Mode_75_150MHz_Bits = 0x6000, 1190}; 1191static inline unsigned MSeries_PLL_Divisor_Bits(unsigned divisor) 1192{ 1193 static const unsigned max_divisor = 0x10; 1194 if (divisor < 1 || divisor > max_divisor) { 1195 printk("%s: bug, invalid divisor=%i\n", __func__, divisor); 1196 return 0; 1197 } 1198 return (divisor & 0xf) << 8; 1199} 1200 1201static inline unsigned MSeries_PLL_Multiplier_Bits(unsigned multiplier) 1202{ 1203 static const unsigned max_multiplier = 0x100; 1204 if (multiplier < 1 || multiplier > max_multiplier) { 1205 printk("%s: bug, invalid multiplier=%i\n", __func__, 1206 multiplier); 1207 return 0; 1208 } 1209 return multiplier & 0xff; 1210} 1211 1212enum MSeries_PLL_Status { 1213 MSeries_PLL_Locked_Bit = 0x1 1214}; 1215 1216enum MSeries_AI_Config_FIFO_Bypass_Bits { 1217 MSeries_AI_Bypass_Channel_Mask = 0x7, 1218 MSeries_AI_Bypass_Bank_Mask = 0x78, 1219 MSeries_AI_Bypass_Cal_Sel_Pos_Mask = 0x380, 1220 MSeries_AI_Bypass_Cal_Sel_Neg_Mask = 0x1c00, 1221 MSeries_AI_Bypass_Mode_Mux_Mask = 0x6000, 1222 MSeries_AO_Bypass_AO_Cal_Sel_Mask = 0x38000, 1223 MSeries_AI_Bypass_Gain_Mask = 0x1c0000, 1224 MSeries_AI_Bypass_Dither_Bit = 0x200000, 1225 MSeries_AI_Bypass_Polarity_Bit = 0x400000, /* 0 for 2's complement encoding */ 1226 MSeries_AI_Bypass_Config_FIFO_Bit = 0x80000000 1227}; 1228static inline unsigned MSeries_AI_Bypass_Cal_Sel_Pos_Bits(int 1229 calibration_source) 1230{ 1231 return (calibration_source << 7) & MSeries_AI_Bypass_Cal_Sel_Pos_Mask; 1232} 1233 1234static inline unsigned MSeries_AI_Bypass_Cal_Sel_Neg_Bits(int 1235 calibration_source) 1236{ 1237 return (calibration_source << 10) & MSeries_AI_Bypass_Cal_Sel_Pos_Mask; 1238} 1239 1240static inline unsigned MSeries_AI_Bypass_Gain_Bits(int gain) 1241{ 1242 return (gain << 18) & MSeries_AI_Bypass_Gain_Mask; 1243} 1244 1245enum MSeries_AO_Config_Bank_Bits { 1246 MSeries_AO_DAC_Offset_Select_Mask = 0x7, 1247 MSeries_AO_DAC_Offset_0V_Bits = 0x0, 1248 MSeries_AO_DAC_Offset_5V_Bits = 0x1, 1249 MSeries_AO_DAC_Reference_Mask = 0x38, 1250 MSeries_AO_DAC_Reference_10V_Internal_Bits = 0x0, 1251 MSeries_AO_DAC_Reference_5V_Internal_Bits = 0x8, 1252 MSeries_AO_Update_Timed_Bit = 0x40, 1253 MSeries_AO_Bipolar_Bit = 0x80 /* turns on 2's complement encoding */ 1254}; 1255 1256enum MSeries_AO_Reference_Attenuation_Bits { 1257 MSeries_Attenuate_x5_Bit = 0x1 1258}; 1259 1260static inline unsigned MSeries_Cal_PWM_High_Time_Bits(unsigned count) 1261{ 1262 return (count << 16) & 0xffff0000; 1263} 1264 1265static inline unsigned MSeries_Cal_PWM_Low_Time_Bits(unsigned count) 1266{ 1267 return count & 0xffff; 1268} 1269 1270static inline unsigned MSeries_PFI_Output_Select_Mask(unsigned channel) 1271{ 1272 return 0x1f << (channel % 3) * 5; 1273}; 1274 1275static inline unsigned MSeries_PFI_Output_Select_Bits(unsigned channel, 1276 unsigned source) 1277{ 1278 return (source & 0x1f) << ((channel % 3) * 5); 1279}; 1280 1281/* inverse to MSeries_PFI_Output_Select_Bits */ 1282static inline unsigned MSeries_PFI_Output_Select_Source(unsigned channel, 1283 unsigned bits) 1284{ 1285 return (bits >> ((channel % 3) * 5)) & 0x1f; 1286}; 1287 1288static inline unsigned MSeries_PFI_Filter_Select_Mask(unsigned channel) 1289{ 1290 return 0x3 << (channel * 2); 1291} 1292 1293static inline unsigned MSeries_PFI_Filter_Select_Bits(unsigned channel, 1294 unsigned filter) 1295{ 1296 return (filter << (channel * 1297 2)) & MSeries_PFI_Filter_Select_Mask(channel); 1298} 1299 1300enum CDIO_DMA_Select_Bits { 1301 CDI_DMA_Select_Shift = 0, 1302 CDI_DMA_Select_Mask = 0xf, 1303 CDO_DMA_Select_Shift = 4, 1304 CDO_DMA_Select_Mask = 0xf << CDO_DMA_Select_Shift 1305}; 1306 1307enum CDIO_Status_Bits { 1308 CDO_FIFO_Empty_Bit = 0x1, 1309 CDO_FIFO_Full_Bit = 0x2, 1310 CDO_FIFO_Request_Bit = 0x4, 1311 CDO_Overrun_Bit = 0x8, 1312 CDO_Underflow_Bit = 0x10, 1313 CDI_FIFO_Empty_Bit = 0x10000, 1314 CDI_FIFO_Full_Bit = 0x20000, 1315 CDI_FIFO_Request_Bit = 0x40000, 1316 CDI_Overrun_Bit = 0x80000, 1317 CDI_Overflow_Bit = 0x100000 1318}; 1319 1320enum CDIO_Command_Bits { 1321 CDO_Disarm_Bit = 0x1, 1322 CDO_Arm_Bit = 0x2, 1323 CDI_Disarm_Bit = 0x4, 1324 CDI_Arm_Bit = 0x8, 1325 CDO_Reset_Bit = 0x10, 1326 CDI_Reset_Bit = 0x20, 1327 CDO_Error_Interrupt_Enable_Set_Bit = 0x40, 1328 CDO_Error_Interrupt_Enable_Clear_Bit = 0x80, 1329 CDI_Error_Interrupt_Enable_Set_Bit = 0x100, 1330 CDI_Error_Interrupt_Enable_Clear_Bit = 0x200, 1331 CDO_FIFO_Request_Interrupt_Enable_Set_Bit = 0x400, 1332 CDO_FIFO_Request_Interrupt_Enable_Clear_Bit = 0x800, 1333 CDI_FIFO_Request_Interrupt_Enable_Set_Bit = 0x1000, 1334 CDI_FIFO_Request_Interrupt_Enable_Clear_Bit = 0x2000, 1335 CDO_Error_Interrupt_Confirm_Bit = 0x4000, 1336 CDI_Error_Interrupt_Confirm_Bit = 0x8000, 1337 CDO_Empty_FIFO_Interrupt_Enable_Set_Bit = 0x10000, 1338 CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit = 0x20000, 1339 CDO_SW_Update_Bit = 0x80000, 1340 CDI_SW_Update_Bit = 0x100000 1341}; 1342 1343enum CDI_Mode_Bits { 1344 CDI_Sample_Source_Select_Mask = 0x3f, 1345 CDI_Halt_On_Error_Bit = 0x200, 1346 CDI_Polarity_Bit = 0x400, /* sample clock on falling edge */ 1347 CDI_FIFO_Mode_Bit = 0x800, /* set for half full mode, clear for not empty mode */ 1348 CDI_Data_Lane_Mask = 0x3000, /* data lanes specify which dio channels map to byte or word accesses to the dio fifos */ 1349 CDI_Data_Lane_0_15_Bits = 0x0, 1350 CDI_Data_Lane_16_31_Bits = 0x1000, 1351 CDI_Data_Lane_0_7_Bits = 0x0, 1352 CDI_Data_Lane_8_15_Bits = 0x1000, 1353 CDI_Data_Lane_16_23_Bits = 0x2000, 1354 CDI_Data_Lane_24_31_Bits = 0x3000 1355}; 1356 1357enum CDO_Mode_Bits { 1358 CDO_Sample_Source_Select_Mask = 0x3f, 1359 CDO_Retransmit_Bit = 0x100, 1360 CDO_Halt_On_Error_Bit = 0x200, 1361 CDO_Polarity_Bit = 0x400, /* sample clock on falling edge */ 1362 CDO_FIFO_Mode_Bit = 0x800, /* set for half full mode, clear for not full mode */ 1363 CDO_Data_Lane_Mask = 0x3000, /* data lanes specify which dio channels map to byte or word accesses to the dio fifos */ 1364 CDO_Data_Lane_0_15_Bits = 0x0, 1365 CDO_Data_Lane_16_31_Bits = 0x1000, 1366 CDO_Data_Lane_0_7_Bits = 0x0, 1367 CDO_Data_Lane_8_15_Bits = 0x1000, 1368 CDO_Data_Lane_16_23_Bits = 0x2000, 1369 CDO_Data_Lane_24_31_Bits = 0x3000 1370}; 1371 1372enum Interrupt_C_Enable_Bits { 1373 Interrupt_Group_C_Enable_Bit = 0x1 1374}; 1375 1376enum Interrupt_C_Status_Bits { 1377 Interrupt_Group_C_Status_Bit = 0x1 1378}; 1379 1380#define M_SERIES_EEPROM_SIZE 1024 1381 1382struct ni_board_struct { 1383 const char *name; 1384 int device_id; 1385 int isapnp_id; 1386 1387 int n_adchan; 1388 unsigned int ai_maxdata; 1389 1390 int ai_fifo_depth; 1391 unsigned int alwaysdither:1; 1392 int gainlkup; 1393 int ai_speed; 1394 1395 int n_aochan; 1396 unsigned int ao_maxdata; 1397 int ao_fifo_depth; 1398 const struct comedi_lrange *ao_range_table; 1399 unsigned ao_speed; 1400 1401 int reg_type; 1402 unsigned int has_8255:1; 1403 unsigned int has_32dio_chan:1; 1404 1405 enum caldac_enum caldac[3]; 1406}; 1407 1408#define MAX_N_CALDACS 34 1409#define MAX_N_AO_CHAN 8 1410#define NUM_GPCT 2 1411 1412struct ni_private { 1413 unsigned short dio_output; 1414 unsigned short dio_control; 1415 int aimode; 1416 unsigned int ai_calib_source; 1417 unsigned int ai_calib_source_enabled; 1418 spinlock_t window_lock; 1419 spinlock_t soft_reg_copy_lock; 1420 spinlock_t mite_channel_lock; 1421 1422 int changain_state; 1423 unsigned int changain_spec; 1424 1425 unsigned int caldac_maxdata_list[MAX_N_CALDACS]; 1426 unsigned short caldacs[MAX_N_CALDACS]; 1427 1428 unsigned short ai_cmd2; 1429 1430 unsigned short ao_conf[MAX_N_AO_CHAN]; 1431 unsigned short ao_mode1; 1432 unsigned short ao_mode2; 1433 unsigned short ao_mode3; 1434 unsigned short ao_cmd1; 1435 unsigned short ao_cmd2; 1436 unsigned short ao_trigger_select; 1437 1438 struct ni_gpct_device *counter_dev; 1439 unsigned short an_trig_etc_reg; 1440 1441 unsigned ai_offset[512]; 1442 1443 unsigned long serial_interval_ns; 1444 unsigned char serial_hw_mode; 1445 unsigned short clock_and_fout; 1446 unsigned short clock_and_fout2; 1447 1448 unsigned short int_a_enable_reg; 1449 unsigned short int_b_enable_reg; 1450 unsigned short io_bidirection_pin_reg; 1451 unsigned short rtsi_trig_direction_reg; 1452 unsigned short rtsi_trig_a_output_reg; 1453 unsigned short rtsi_trig_b_output_reg; 1454 unsigned short pfi_output_select_reg[NUM_PFI_OUTPUT_SELECT_REGS]; 1455 unsigned short ai_ao_select_reg; 1456 unsigned short g0_g1_select_reg; 1457 unsigned short cdio_dma_select_reg; 1458 1459 unsigned clock_ns; 1460 unsigned clock_source; 1461 1462 unsigned short pwm_up_count; 1463 unsigned short pwm_down_count; 1464 1465 unsigned short ai_fifo_buffer[0x2000]; 1466 uint8_t eeprom_buffer[M_SERIES_EEPROM_SIZE]; 1467 uint32_t serial_number; 1468 1469 struct mite_struct *mite; 1470 struct mite_channel *ai_mite_chan; 1471 struct mite_channel *ao_mite_chan; 1472 struct mite_channel *cdo_mite_chan; 1473 struct mite_dma_descriptor_ring *ai_mite_ring; 1474 struct mite_dma_descriptor_ring *ao_mite_ring; 1475 struct mite_dma_descriptor_ring *cdo_mite_ring; 1476 struct mite_dma_descriptor_ring *gpct_mite_ring[NUM_GPCT]; 1477 1478 /* ni_pcimio board type flags (based on the boardinfo reg_type) */ 1479 unsigned int is_m_series:1; 1480 unsigned int is_6xxx:1; 1481 unsigned int is_611x:1; 1482 unsigned int is_6143:1; 1483 unsigned int is_622x:1; 1484 unsigned int is_625x:1; 1485 unsigned int is_628x:1; 1486 unsigned int is_67xx:1; 1487 unsigned int is_6711:1; 1488 unsigned int is_6713:1; 1489}; 1490 1491#endif /* _COMEDI_NI_STC_H */ 1492