1/* 2 comedi/drivers/ni_tio.c 3 Support for NI general purpose counters 4 5 Copyright (C) 2006 Frank Mori Hess <fmhess@users.sourceforge.net> 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 2 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16*/ 17 18/* 19Driver: ni_tio 20Description: National Instruments general purpose counters 21Devices: 22Author: J.P. Mellor <jpmellor@rose-hulman.edu>, 23 Herman.Bruyninckx@mech.kuleuven.ac.be, 24 Wim.Meeussen@mech.kuleuven.ac.be, 25 Klaas.Gadeyne@mech.kuleuven.ac.be, 26 Frank Mori Hess <fmhess@users.sourceforge.net> 27Updated: Thu Nov 16 09:50:32 EST 2006 28Status: works 29 30This module is not used directly by end-users. Rather, it 31is used by other drivers (for example ni_660x and ni_pcimio) 32to provide support for NI's general purpose counters. It was 33originally based on the counter code from ni_660x.c and 34ni_mio_common.c. 35 36References: 37DAQ 660x Register-Level Programmer Manual (NI 370505A-01) 38DAQ 6601/6602 User Manual (NI 322137B-01) 39340934b.pdf DAQ-STC reference manual 40 41*/ 42/* 43TODO: 44 Support use of both banks X and Y 45*/ 46 47#include <linux/module.h> 48#include <linux/slab.h> 49 50#include "ni_tio_internal.h" 51 52/* 53 * clock sources for ni e and m series boards, 54 * get bits with GI_SRC_SEL() 55 */ 56#define NI_M_TIMEBASE_1_CLK 0x0 /* 20MHz */ 57#define NI_M_PFI_CLK(x) (((x) < 10) ? (1 + (x)) : (0xb + (x))) 58#define NI_M_RTSI_CLK(x) (((x) == 7) ? 0x1b : (0xb + (x))) 59#define NI_M_TIMEBASE_2_CLK 0x12 /* 100KHz */ 60#define NI_M_NEXT_TC_CLK 0x13 61#define NI_M_NEXT_GATE_CLK 0x14 /* Gi_Src_SubSelect=0 */ 62#define NI_M_PXI_STAR_TRIGGER_CLK 0x14 /* Gi_Src_SubSelect=1 */ 63#define NI_M_PXI10_CLK 0x1d 64#define NI_M_TIMEBASE_3_CLK 0x1e /* 80MHz, Gi_Src_SubSelect=0 */ 65#define NI_M_ANALOG_TRIGGER_OUT_CLK 0x1e /* Gi_Src_SubSelect=1 */ 66#define NI_M_LOGIC_LOW_CLK 0x1f 67#define NI_M_MAX_PFI_CHAN 15 68#define NI_M_MAX_RTSI_CHAN 7 69 70/* 71 * clock sources for ni_660x boards, 72 * get bits with GI_SRC_SEL() 73 */ 74#define NI_660X_TIMEBASE_1_CLK 0x0 /* 20MHz */ 75#define NI_660X_SRC_PIN_I_CLK 0x1 76#define NI_660X_SRC_PIN_CLK(x) (0x2 + (x)) 77#define NI_660X_NEXT_GATE_CLK 0xa 78#define NI_660X_RTSI_CLK(x) (0xb + (x)) 79#define NI_660X_TIMEBASE_2_CLK 0x12 /* 100KHz */ 80#define NI_660X_NEXT_TC_CLK 0x13 81#define NI_660X_TIMEBASE_3_CLK 0x1e /* 80MHz */ 82#define NI_660X_LOGIC_LOW_CLK 0x1f 83#define NI_660X_MAX_SRC_PIN 7 84#define NI_660X_MAX_RTSI_CHAN 6 85 86/* ni m series gate_select */ 87#define NI_M_TIMESTAMP_MUX_GATE_SEL 0x0 88#define NI_M_PFI_GATE_SEL(x) (((x) < 10) ? (1 + (x)) : (0xb + (x))) 89#define NI_M_RTSI_GATE_SEL(x) (((x) == 7) ? 0x1b : (0xb + (x))) 90#define NI_M_AI_START2_GATE_SEL 0x12 91#define NI_M_PXI_STAR_TRIGGER_GATE_SEL 0x13 92#define NI_M_NEXT_OUT_GATE_SEL 0x14 93#define NI_M_AI_START1_GATE_SEL 0x1c 94#define NI_M_NEXT_SRC_GATE_SEL 0x1d 95#define NI_M_ANALOG_TRIG_OUT_GATE_SEL 0x1e 96#define NI_M_LOGIC_LOW_GATE_SEL 0x1f 97 98/* ni_660x gate select */ 99#define NI_660X_SRC_PIN_I_GATE_SEL 0x0 100#define NI_660X_GATE_PIN_I_GATE_SEL 0x1 101#define NI_660X_PIN_GATE_SEL(x) (0x2 + (x)) 102#define NI_660X_NEXT_SRC_GATE_SEL 0xa 103#define NI_660X_RTSI_GATE_SEL(x) (0xb + (x)) 104#define NI_660X_NEXT_OUT_GATE_SEL 0x14 105#define NI_660X_LOGIC_LOW_GATE_SEL 0x1f 106#define NI_660X_MAX_GATE_PIN 7 107 108/* ni_660x second gate select */ 109#define NI_660X_SRC_PIN_I_GATE2_SEL 0x0 110#define NI_660X_UD_PIN_I_GATE2_SEL 0x1 111#define NI_660X_UD_PIN_GATE2_SEL(x) (0x2 + (x)) 112#define NI_660X_NEXT_SRC_GATE2_SEL 0xa 113#define NI_660X_RTSI_GATE2_SEL(x) (0xb + (x)) 114#define NI_660X_NEXT_OUT_GATE2_SEL 0x14 115#define NI_660X_SELECTED_GATE2_SEL 0x1e 116#define NI_660X_LOGIC_LOW_GATE2_SEL 0x1f 117#define NI_660X_MAX_UP_DOWN_PIN 7 118 119static inline unsigned GI_ALT_SYNC(enum ni_gpct_variant variant) 120{ 121 switch (variant) { 122 case ni_gpct_variant_e_series: 123 default: 124 return 0; 125 case ni_gpct_variant_m_series: 126 return GI_M_ALT_SYNC; 127 case ni_gpct_variant_660x: 128 return GI_660X_ALT_SYNC; 129 } 130} 131 132static inline unsigned GI_PRESCALE_X2(enum ni_gpct_variant variant) 133{ 134 switch (variant) { 135 case ni_gpct_variant_e_series: 136 default: 137 return 0; 138 case ni_gpct_variant_m_series: 139 return GI_M_PRESCALE_X2; 140 case ni_gpct_variant_660x: 141 return GI_660X_PRESCALE_X2; 142 } 143} 144 145static inline unsigned GI_PRESCALE_X8(enum ni_gpct_variant variant) 146{ 147 switch (variant) { 148 case ni_gpct_variant_e_series: 149 default: 150 return 0; 151 case ni_gpct_variant_m_series: 152 return GI_M_PRESCALE_X8; 153 case ni_gpct_variant_660x: 154 return GI_660X_PRESCALE_X8; 155 } 156} 157 158static inline unsigned GI_HW_ARM_SEL_MASK(enum ni_gpct_variant variant) 159{ 160 switch (variant) { 161 case ni_gpct_variant_e_series: 162 default: 163 return 0; 164 case ni_gpct_variant_m_series: 165 return GI_M_HW_ARM_SEL_MASK; 166 case ni_gpct_variant_660x: 167 return GI_660X_HW_ARM_SEL_MASK; 168 } 169} 170 171static int ni_tio_has_gate2_registers(const struct ni_gpct_device *counter_dev) 172{ 173 switch (counter_dev->variant) { 174 case ni_gpct_variant_e_series: 175 default: 176 return 0; 177 case ni_gpct_variant_m_series: 178 case ni_gpct_variant_660x: 179 return 1; 180 } 181} 182 183static void ni_tio_reset_count_and_disarm(struct ni_gpct *counter) 184{ 185 unsigned cidx = counter->counter_index; 186 187 write_register(counter, GI_RESET(cidx), NITIO_RESET_REG(cidx)); 188} 189 190static uint64_t ni_tio_clock_period_ps(const struct ni_gpct *counter, 191 unsigned generic_clock_source) 192{ 193 uint64_t clock_period_ps; 194 195 switch (generic_clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK) { 196 case NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS: 197 clock_period_ps = 50000; 198 break; 199 case NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS: 200 clock_period_ps = 10000000; 201 break; 202 case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS: 203 clock_period_ps = 12500; 204 break; 205 case NI_GPCT_PXI10_CLOCK_SRC_BITS: 206 clock_period_ps = 100000; 207 break; 208 default: 209 /* 210 * clock period is specified by user with prescaling 211 * already taken into account. 212 */ 213 return counter->clock_period_ps; 214 } 215 216 switch (generic_clock_source & NI_GPCT_PRESCALE_MODE_CLOCK_SRC_MASK) { 217 case NI_GPCT_NO_PRESCALE_CLOCK_SRC_BITS: 218 break; 219 case NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS: 220 clock_period_ps *= 2; 221 break; 222 case NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS: 223 clock_period_ps *= 8; 224 break; 225 default: 226 BUG(); 227 break; 228 } 229 return clock_period_ps; 230} 231 232static unsigned ni_tio_clock_src_modifiers(const struct ni_gpct *counter) 233{ 234 struct ni_gpct_device *counter_dev = counter->counter_dev; 235 unsigned cidx = counter->counter_index; 236 const unsigned counting_mode_bits = 237 ni_tio_get_soft_copy(counter, NITIO_CNT_MODE_REG(cidx)); 238 unsigned bits = 0; 239 240 if (ni_tio_get_soft_copy(counter, NITIO_INPUT_SEL_REG(cidx)) & 241 GI_SRC_POL_INVERT) 242 bits |= NI_GPCT_INVERT_CLOCK_SRC_BIT; 243 if (counting_mode_bits & GI_PRESCALE_X2(counter_dev->variant)) 244 bits |= NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS; 245 if (counting_mode_bits & GI_PRESCALE_X8(counter_dev->variant)) 246 bits |= NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS; 247 return bits; 248} 249 250static unsigned ni_m_series_clock_src_select(const struct ni_gpct *counter) 251{ 252 struct ni_gpct_device *counter_dev = counter->counter_dev; 253 unsigned cidx = counter->counter_index; 254 const unsigned second_gate_reg = NITIO_GATE2_REG(cidx); 255 unsigned clock_source = 0; 256 unsigned src; 257 unsigned i; 258 259 src = GI_BITS_TO_SRC(ni_tio_get_soft_copy(counter, 260 NITIO_INPUT_SEL_REG(cidx))); 261 262 switch (src) { 263 case NI_M_TIMEBASE_1_CLK: 264 clock_source = NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS; 265 break; 266 case NI_M_TIMEBASE_2_CLK: 267 clock_source = NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS; 268 break; 269 case NI_M_TIMEBASE_3_CLK: 270 if (counter_dev->regs[second_gate_reg] & GI_SRC_SUBSEL) 271 clock_source = 272 NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS; 273 else 274 clock_source = NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS; 275 break; 276 case NI_M_LOGIC_LOW_CLK: 277 clock_source = NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS; 278 break; 279 case NI_M_NEXT_GATE_CLK: 280 if (counter_dev->regs[second_gate_reg] & GI_SRC_SUBSEL) 281 clock_source = NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS; 282 else 283 clock_source = NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS; 284 break; 285 case NI_M_PXI10_CLK: 286 clock_source = NI_GPCT_PXI10_CLOCK_SRC_BITS; 287 break; 288 case NI_M_NEXT_TC_CLK: 289 clock_source = NI_GPCT_NEXT_TC_CLOCK_SRC_BITS; 290 break; 291 default: 292 for (i = 0; i <= NI_M_MAX_RTSI_CHAN; ++i) { 293 if (src == NI_M_RTSI_CLK(i)) { 294 clock_source = NI_GPCT_RTSI_CLOCK_SRC_BITS(i); 295 break; 296 } 297 } 298 if (i <= NI_M_MAX_RTSI_CHAN) 299 break; 300 for (i = 0; i <= NI_M_MAX_PFI_CHAN; ++i) { 301 if (src == NI_M_PFI_CLK(i)) { 302 clock_source = NI_GPCT_PFI_CLOCK_SRC_BITS(i); 303 break; 304 } 305 } 306 if (i <= NI_M_MAX_PFI_CHAN) 307 break; 308 BUG(); 309 break; 310 } 311 clock_source |= ni_tio_clock_src_modifiers(counter); 312 return clock_source; 313} 314 315static unsigned ni_660x_clock_src_select(const struct ni_gpct *counter) 316{ 317 unsigned clock_source = 0; 318 unsigned cidx = counter->counter_index; 319 unsigned src; 320 unsigned i; 321 322 src = GI_BITS_TO_SRC(ni_tio_get_soft_copy(counter, 323 NITIO_INPUT_SEL_REG(cidx))); 324 325 switch (src) { 326 case NI_660X_TIMEBASE_1_CLK: 327 clock_source = NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS; 328 break; 329 case NI_660X_TIMEBASE_2_CLK: 330 clock_source = NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS; 331 break; 332 case NI_660X_TIMEBASE_3_CLK: 333 clock_source = NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS; 334 break; 335 case NI_660X_LOGIC_LOW_CLK: 336 clock_source = NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS; 337 break; 338 case NI_660X_SRC_PIN_I_CLK: 339 clock_source = NI_GPCT_SOURCE_PIN_i_CLOCK_SRC_BITS; 340 break; 341 case NI_660X_NEXT_GATE_CLK: 342 clock_source = NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS; 343 break; 344 case NI_660X_NEXT_TC_CLK: 345 clock_source = NI_GPCT_NEXT_TC_CLOCK_SRC_BITS; 346 break; 347 default: 348 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) { 349 if (src == NI_660X_RTSI_CLK(i)) { 350 clock_source = NI_GPCT_RTSI_CLOCK_SRC_BITS(i); 351 break; 352 } 353 } 354 if (i <= NI_660X_MAX_RTSI_CHAN) 355 break; 356 for (i = 0; i <= NI_660X_MAX_SRC_PIN; ++i) { 357 if (src == NI_660X_SRC_PIN_CLK(i)) { 358 clock_source = 359 NI_GPCT_SOURCE_PIN_CLOCK_SRC_BITS(i); 360 break; 361 } 362 } 363 if (i <= NI_660X_MAX_SRC_PIN) 364 break; 365 BUG(); 366 break; 367 } 368 clock_source |= ni_tio_clock_src_modifiers(counter); 369 return clock_source; 370} 371 372static unsigned ni_tio_generic_clock_src_select(const struct ni_gpct *counter) 373{ 374 switch (counter->counter_dev->variant) { 375 case ni_gpct_variant_e_series: 376 case ni_gpct_variant_m_series: 377 default: 378 return ni_m_series_clock_src_select(counter); 379 case ni_gpct_variant_660x: 380 return ni_660x_clock_src_select(counter); 381 } 382} 383 384static void ni_tio_set_sync_mode(struct ni_gpct *counter, int force_alt_sync) 385{ 386 struct ni_gpct_device *counter_dev = counter->counter_dev; 387 unsigned cidx = counter->counter_index; 388 const unsigned counting_mode_reg = NITIO_CNT_MODE_REG(cidx); 389 static const uint64_t min_normal_sync_period_ps = 25000; 390 unsigned mode; 391 uint64_t clock_period_ps; 392 393 if (ni_tio_counting_mode_registers_present(counter_dev) == 0) 394 return; 395 396 mode = ni_tio_get_soft_copy(counter, counting_mode_reg); 397 switch (mode & GI_CNT_MODE_MASK) { 398 case GI_CNT_MODE_QUADX1: 399 case GI_CNT_MODE_QUADX2: 400 case GI_CNT_MODE_QUADX4: 401 case GI_CNT_MODE_SYNC_SRC: 402 force_alt_sync = 1; 403 break; 404 default: 405 break; 406 } 407 408 clock_period_ps = ni_tio_clock_period_ps(counter, 409 ni_tio_generic_clock_src_select(counter)); 410 411 /* 412 * It's not clear what we should do if clock_period is unknown, so we 413 * are not using the alt sync bit in that case, but allow the caller 414 * to decide by using the force_alt_sync parameter. 415 */ 416 if (force_alt_sync || 417 (clock_period_ps && clock_period_ps < min_normal_sync_period_ps)) { 418 ni_tio_set_bits(counter, counting_mode_reg, 419 GI_ALT_SYNC(counter_dev->variant), 420 GI_ALT_SYNC(counter_dev->variant)); 421 } else { 422 ni_tio_set_bits(counter, counting_mode_reg, 423 GI_ALT_SYNC(counter_dev->variant), 424 0x0); 425 } 426} 427 428static int ni_tio_set_counter_mode(struct ni_gpct *counter, unsigned mode) 429{ 430 struct ni_gpct_device *counter_dev = counter->counter_dev; 431 unsigned cidx = counter->counter_index; 432 unsigned mode_reg_mask; 433 unsigned mode_reg_values; 434 unsigned input_select_bits = 0; 435 /* these bits map directly on to the mode register */ 436 static const unsigned mode_reg_direct_mask = 437 NI_GPCT_GATE_ON_BOTH_EDGES_BIT | NI_GPCT_EDGE_GATE_MODE_MASK | 438 NI_GPCT_STOP_MODE_MASK | NI_GPCT_OUTPUT_MODE_MASK | 439 NI_GPCT_HARDWARE_DISARM_MASK | NI_GPCT_LOADING_ON_TC_BIT | 440 NI_GPCT_LOADING_ON_GATE_BIT | NI_GPCT_LOAD_B_SELECT_BIT; 441 442 mode_reg_mask = mode_reg_direct_mask | GI_RELOAD_SRC_SWITCHING; 443 mode_reg_values = mode & mode_reg_direct_mask; 444 switch (mode & NI_GPCT_RELOAD_SOURCE_MASK) { 445 case NI_GPCT_RELOAD_SOURCE_FIXED_BITS: 446 break; 447 case NI_GPCT_RELOAD_SOURCE_SWITCHING_BITS: 448 mode_reg_values |= GI_RELOAD_SRC_SWITCHING; 449 break; 450 case NI_GPCT_RELOAD_SOURCE_GATE_SELECT_BITS: 451 input_select_bits |= GI_GATE_SEL_LOAD_SRC; 452 mode_reg_mask |= GI_GATING_MODE_MASK; 453 mode_reg_values |= GI_LEVEL_GATING; 454 break; 455 default: 456 break; 457 } 458 ni_tio_set_bits(counter, NITIO_MODE_REG(cidx), 459 mode_reg_mask, mode_reg_values); 460 461 if (ni_tio_counting_mode_registers_present(counter_dev)) { 462 unsigned bits = 0; 463 464 bits |= GI_CNT_MODE(mode >> NI_GPCT_COUNTING_MODE_SHIFT); 465 bits |= GI_INDEX_PHASE((mode >> NI_GPCT_INDEX_PHASE_BITSHIFT)); 466 if (mode & NI_GPCT_INDEX_ENABLE_BIT) 467 bits |= GI_INDEX_MODE; 468 ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx), 469 GI_CNT_MODE_MASK | GI_INDEX_PHASE_MASK | 470 GI_INDEX_MODE, bits); 471 ni_tio_set_sync_mode(counter, 0); 472 } 473 474 ni_tio_set_bits(counter, NITIO_CMD_REG(cidx), GI_CNT_DIR_MASK, 475 GI_CNT_DIR(mode >> NI_GPCT_COUNTING_DIRECTION_SHIFT)); 476 477 if (mode & NI_GPCT_OR_GATE_BIT) 478 input_select_bits |= GI_OR_GATE; 479 if (mode & NI_GPCT_INVERT_OUTPUT_BIT) 480 input_select_bits |= GI_OUTPUT_POL_INVERT; 481 ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx), 482 GI_GATE_SEL_LOAD_SRC | GI_OR_GATE | 483 GI_OUTPUT_POL_INVERT, input_select_bits); 484 485 return 0; 486} 487 488int ni_tio_arm(struct ni_gpct *counter, int arm, unsigned start_trigger) 489{ 490 struct ni_gpct_device *counter_dev = counter->counter_dev; 491 unsigned cidx = counter->counter_index; 492 unsigned command_transient_bits = 0; 493 494 if (arm) { 495 switch (start_trigger) { 496 case NI_GPCT_ARM_IMMEDIATE: 497 command_transient_bits |= GI_ARM; 498 break; 499 case NI_GPCT_ARM_PAIRED_IMMEDIATE: 500 command_transient_bits |= GI_ARM | GI_ARM_COPY; 501 break; 502 default: 503 break; 504 } 505 if (ni_tio_counting_mode_registers_present(counter_dev)) { 506 unsigned bits = 0; 507 unsigned sel_mask; 508 509 sel_mask = GI_HW_ARM_SEL_MASK(counter_dev->variant); 510 511 switch (start_trigger) { 512 case NI_GPCT_ARM_IMMEDIATE: 513 case NI_GPCT_ARM_PAIRED_IMMEDIATE: 514 break; 515 default: 516 if (start_trigger & NI_GPCT_ARM_UNKNOWN) { 517 /* 518 * pass-through the least significant 519 * bits so we can figure out what 520 * select later 521 */ 522 bits |= GI_HW_ARM_ENA | 523 (GI_HW_ARM_SEL(start_trigger) & 524 sel_mask); 525 } else { 526 return -EINVAL; 527 } 528 break; 529 } 530 ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx), 531 GI_HW_ARM_ENA | sel_mask, bits); 532 } 533 } else { 534 command_transient_bits |= GI_DISARM; 535 } 536 ni_tio_set_bits_transient(counter, NITIO_CMD_REG(cidx), 537 0, 0, command_transient_bits); 538 return 0; 539} 540EXPORT_SYMBOL_GPL(ni_tio_arm); 541 542static unsigned ni_660x_clk_src(unsigned int clock_source) 543{ 544 unsigned clk_src = clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK; 545 unsigned ni_660x_clock; 546 unsigned i; 547 548 switch (clk_src) { 549 case NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS: 550 ni_660x_clock = NI_660X_TIMEBASE_1_CLK; 551 break; 552 case NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS: 553 ni_660x_clock = NI_660X_TIMEBASE_2_CLK; 554 break; 555 case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS: 556 ni_660x_clock = NI_660X_TIMEBASE_3_CLK; 557 break; 558 case NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS: 559 ni_660x_clock = NI_660X_LOGIC_LOW_CLK; 560 break; 561 case NI_GPCT_SOURCE_PIN_i_CLOCK_SRC_BITS: 562 ni_660x_clock = NI_660X_SRC_PIN_I_CLK; 563 break; 564 case NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS: 565 ni_660x_clock = NI_660X_NEXT_GATE_CLK; 566 break; 567 case NI_GPCT_NEXT_TC_CLOCK_SRC_BITS: 568 ni_660x_clock = NI_660X_NEXT_TC_CLK; 569 break; 570 default: 571 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) { 572 if (clk_src == NI_GPCT_RTSI_CLOCK_SRC_BITS(i)) { 573 ni_660x_clock = NI_660X_RTSI_CLK(i); 574 break; 575 } 576 } 577 if (i <= NI_660X_MAX_RTSI_CHAN) 578 break; 579 for (i = 0; i <= NI_660X_MAX_SRC_PIN; ++i) { 580 if (clk_src == NI_GPCT_SOURCE_PIN_CLOCK_SRC_BITS(i)) { 581 ni_660x_clock = NI_660X_SRC_PIN_CLK(i); 582 break; 583 } 584 } 585 if (i <= NI_660X_MAX_SRC_PIN) 586 break; 587 ni_660x_clock = 0; 588 BUG(); 589 break; 590 } 591 return GI_SRC_SEL(ni_660x_clock); 592} 593 594static unsigned ni_m_clk_src(unsigned int clock_source) 595{ 596 unsigned clk_src = clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK; 597 unsigned ni_m_series_clock; 598 unsigned i; 599 600 switch (clk_src) { 601 case NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS: 602 ni_m_series_clock = NI_M_TIMEBASE_1_CLK; 603 break; 604 case NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS: 605 ni_m_series_clock = NI_M_TIMEBASE_2_CLK; 606 break; 607 case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS: 608 ni_m_series_clock = NI_M_TIMEBASE_3_CLK; 609 break; 610 case NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS: 611 ni_m_series_clock = NI_M_LOGIC_LOW_CLK; 612 break; 613 case NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS: 614 ni_m_series_clock = NI_M_NEXT_GATE_CLK; 615 break; 616 case NI_GPCT_NEXT_TC_CLOCK_SRC_BITS: 617 ni_m_series_clock = NI_M_NEXT_TC_CLK; 618 break; 619 case NI_GPCT_PXI10_CLOCK_SRC_BITS: 620 ni_m_series_clock = NI_M_PXI10_CLK; 621 break; 622 case NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS: 623 ni_m_series_clock = NI_M_PXI_STAR_TRIGGER_CLK; 624 break; 625 case NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS: 626 ni_m_series_clock = NI_M_ANALOG_TRIGGER_OUT_CLK; 627 break; 628 default: 629 for (i = 0; i <= NI_M_MAX_RTSI_CHAN; ++i) { 630 if (clk_src == NI_GPCT_RTSI_CLOCK_SRC_BITS(i)) { 631 ni_m_series_clock = NI_M_RTSI_CLK(i); 632 break; 633 } 634 } 635 if (i <= NI_M_MAX_RTSI_CHAN) 636 break; 637 for (i = 0; i <= NI_M_MAX_PFI_CHAN; ++i) { 638 if (clk_src == NI_GPCT_PFI_CLOCK_SRC_BITS(i)) { 639 ni_m_series_clock = NI_M_PFI_CLK(i); 640 break; 641 } 642 } 643 if (i <= NI_M_MAX_PFI_CHAN) 644 break; 645 pr_err("invalid clock source 0x%lx\n", 646 (unsigned long)clock_source); 647 BUG(); 648 ni_m_series_clock = 0; 649 break; 650 } 651 return GI_SRC_SEL(ni_m_series_clock); 652}; 653 654static void ni_tio_set_source_subselect(struct ni_gpct *counter, 655 unsigned int clock_source) 656{ 657 struct ni_gpct_device *counter_dev = counter->counter_dev; 658 unsigned cidx = counter->counter_index; 659 const unsigned second_gate_reg = NITIO_GATE2_REG(cidx); 660 661 if (counter_dev->variant != ni_gpct_variant_m_series) 662 return; 663 switch (clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK) { 664 /* Gi_Source_Subselect is zero */ 665 case NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS: 666 case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS: 667 counter_dev->regs[second_gate_reg] &= ~GI_SRC_SUBSEL; 668 break; 669 /* Gi_Source_Subselect is one */ 670 case NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS: 671 case NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS: 672 counter_dev->regs[second_gate_reg] |= GI_SRC_SUBSEL; 673 break; 674 /* Gi_Source_Subselect doesn't matter */ 675 default: 676 return; 677 } 678 write_register(counter, counter_dev->regs[second_gate_reg], 679 second_gate_reg); 680} 681 682static int ni_tio_set_clock_src(struct ni_gpct *counter, 683 unsigned int clock_source, 684 unsigned int period_ns) 685{ 686 struct ni_gpct_device *counter_dev = counter->counter_dev; 687 unsigned cidx = counter->counter_index; 688 unsigned bits = 0; 689 690 /* FIXME: validate clock source */ 691 switch (counter_dev->variant) { 692 case ni_gpct_variant_660x: 693 bits |= ni_660x_clk_src(clock_source); 694 break; 695 case ni_gpct_variant_e_series: 696 case ni_gpct_variant_m_series: 697 default: 698 bits |= ni_m_clk_src(clock_source); 699 break; 700 } 701 if (clock_source & NI_GPCT_INVERT_CLOCK_SRC_BIT) 702 bits |= GI_SRC_POL_INVERT; 703 ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx), 704 GI_SRC_SEL_MASK | GI_SRC_POL_INVERT, bits); 705 ni_tio_set_source_subselect(counter, clock_source); 706 707 if (ni_tio_counting_mode_registers_present(counter_dev)) { 708 bits = 0; 709 switch (clock_source & NI_GPCT_PRESCALE_MODE_CLOCK_SRC_MASK) { 710 case NI_GPCT_NO_PRESCALE_CLOCK_SRC_BITS: 711 break; 712 case NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS: 713 bits |= GI_PRESCALE_X2(counter_dev->variant); 714 break; 715 case NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS: 716 bits |= GI_PRESCALE_X8(counter_dev->variant); 717 break; 718 default: 719 return -EINVAL; 720 } 721 ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx), 722 GI_PRESCALE_X2(counter_dev->variant) | 723 GI_PRESCALE_X8(counter_dev->variant), bits); 724 } 725 counter->clock_period_ps = period_ns * 1000; 726 ni_tio_set_sync_mode(counter, 0); 727 return 0; 728} 729 730static void ni_tio_get_clock_src(struct ni_gpct *counter, 731 unsigned int *clock_source, 732 unsigned int *period_ns) 733{ 734 uint64_t temp64; 735 736 *clock_source = ni_tio_generic_clock_src_select(counter); 737 temp64 = ni_tio_clock_period_ps(counter, *clock_source); 738 do_div(temp64, 1000); /* ps to ns */ 739 *period_ns = temp64; 740} 741 742static int ni_660x_set_gate(struct ni_gpct *counter, unsigned int gate_source) 743{ 744 unsigned int chan = CR_CHAN(gate_source); 745 unsigned cidx = counter->counter_index; 746 unsigned gate_sel; 747 unsigned i; 748 749 switch (chan) { 750 case NI_GPCT_NEXT_SOURCE_GATE_SELECT: 751 gate_sel = NI_660X_NEXT_SRC_GATE_SEL; 752 break; 753 case NI_GPCT_NEXT_OUT_GATE_SELECT: 754 case NI_GPCT_LOGIC_LOW_GATE_SELECT: 755 case NI_GPCT_SOURCE_PIN_i_GATE_SELECT: 756 case NI_GPCT_GATE_PIN_i_GATE_SELECT: 757 gate_sel = chan & 0x1f; 758 break; 759 default: 760 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) { 761 if (chan == NI_GPCT_RTSI_GATE_SELECT(i)) { 762 gate_sel = chan & 0x1f; 763 break; 764 } 765 } 766 if (i <= NI_660X_MAX_RTSI_CHAN) 767 break; 768 for (i = 0; i <= NI_660X_MAX_GATE_PIN; ++i) { 769 if (chan == NI_GPCT_GATE_PIN_GATE_SELECT(i)) { 770 gate_sel = chan & 0x1f; 771 break; 772 } 773 } 774 if (i <= NI_660X_MAX_GATE_PIN) 775 break; 776 return -EINVAL; 777 } 778 ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx), 779 GI_GATE_SEL_MASK, GI_GATE_SEL(gate_sel)); 780 return 0; 781} 782 783static int ni_m_set_gate(struct ni_gpct *counter, unsigned int gate_source) 784{ 785 unsigned int chan = CR_CHAN(gate_source); 786 unsigned cidx = counter->counter_index; 787 unsigned gate_sel; 788 unsigned i; 789 790 switch (chan) { 791 case NI_GPCT_TIMESTAMP_MUX_GATE_SELECT: 792 case NI_GPCT_AI_START2_GATE_SELECT: 793 case NI_GPCT_PXI_STAR_TRIGGER_GATE_SELECT: 794 case NI_GPCT_NEXT_OUT_GATE_SELECT: 795 case NI_GPCT_AI_START1_GATE_SELECT: 796 case NI_GPCT_NEXT_SOURCE_GATE_SELECT: 797 case NI_GPCT_ANALOG_TRIGGER_OUT_GATE_SELECT: 798 case NI_GPCT_LOGIC_LOW_GATE_SELECT: 799 gate_sel = chan & 0x1f; 800 break; 801 default: 802 for (i = 0; i <= NI_M_MAX_RTSI_CHAN; ++i) { 803 if (chan == NI_GPCT_RTSI_GATE_SELECT(i)) { 804 gate_sel = chan & 0x1f; 805 break; 806 } 807 } 808 if (i <= NI_M_MAX_RTSI_CHAN) 809 break; 810 for (i = 0; i <= NI_M_MAX_PFI_CHAN; ++i) { 811 if (chan == NI_GPCT_PFI_GATE_SELECT(i)) { 812 gate_sel = chan & 0x1f; 813 break; 814 } 815 } 816 if (i <= NI_M_MAX_PFI_CHAN) 817 break; 818 return -EINVAL; 819 } 820 ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx), 821 GI_GATE_SEL_MASK, GI_GATE_SEL(gate_sel)); 822 return 0; 823} 824 825static int ni_660x_set_gate2(struct ni_gpct *counter, unsigned int gate_source) 826{ 827 struct ni_gpct_device *counter_dev = counter->counter_dev; 828 unsigned cidx = counter->counter_index; 829 unsigned int chan = CR_CHAN(gate_source); 830 unsigned gate2_reg = NITIO_GATE2_REG(cidx); 831 unsigned gate2_sel; 832 unsigned i; 833 834 switch (chan) { 835 case NI_GPCT_SOURCE_PIN_i_GATE_SELECT: 836 case NI_GPCT_UP_DOWN_PIN_i_GATE_SELECT: 837 case NI_GPCT_SELECTED_GATE_GATE_SELECT: 838 case NI_GPCT_NEXT_OUT_GATE_SELECT: 839 case NI_GPCT_LOGIC_LOW_GATE_SELECT: 840 gate2_sel = chan & 0x1f; 841 break; 842 case NI_GPCT_NEXT_SOURCE_GATE_SELECT: 843 gate2_sel = NI_660X_NEXT_SRC_GATE2_SEL; 844 break; 845 default: 846 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) { 847 if (chan == NI_GPCT_RTSI_GATE_SELECT(i)) { 848 gate2_sel = chan & 0x1f; 849 break; 850 } 851 } 852 if (i <= NI_660X_MAX_RTSI_CHAN) 853 break; 854 for (i = 0; i <= NI_660X_MAX_UP_DOWN_PIN; ++i) { 855 if (chan == NI_GPCT_UP_DOWN_PIN_GATE_SELECT(i)) { 856 gate2_sel = chan & 0x1f; 857 break; 858 } 859 } 860 if (i <= NI_660X_MAX_UP_DOWN_PIN) 861 break; 862 return -EINVAL; 863 } 864 counter_dev->regs[gate2_reg] |= GI_GATE2_MODE; 865 counter_dev->regs[gate2_reg] &= ~GI_GATE2_SEL_MASK; 866 counter_dev->regs[gate2_reg] |= GI_GATE2_SEL(gate2_sel); 867 write_register(counter, counter_dev->regs[gate2_reg], gate2_reg); 868 return 0; 869} 870 871static int ni_m_set_gate2(struct ni_gpct *counter, unsigned int gate_source) 872{ 873 struct ni_gpct_device *counter_dev = counter->counter_dev; 874 unsigned cidx = counter->counter_index; 875 unsigned int chan = CR_CHAN(gate_source); 876 unsigned gate2_reg = NITIO_GATE2_REG(cidx); 877 unsigned gate2_sel; 878 879 /* 880 * FIXME: We don't know what the m-series second gate codes are, 881 * so we'll just pass the bits through for now. 882 */ 883 switch (chan) { 884 default: 885 gate2_sel = chan & 0x1f; 886 break; 887 } 888 counter_dev->regs[gate2_reg] |= GI_GATE2_MODE; 889 counter_dev->regs[gate2_reg] &= ~GI_GATE2_SEL_MASK; 890 counter_dev->regs[gate2_reg] |= GI_GATE2_SEL(gate2_sel); 891 write_register(counter, counter_dev->regs[gate2_reg], gate2_reg); 892 return 0; 893} 894 895int ni_tio_set_gate_src(struct ni_gpct *counter, unsigned gate_index, 896 unsigned int gate_source) 897{ 898 struct ni_gpct_device *counter_dev = counter->counter_dev; 899 unsigned cidx = counter->counter_index; 900 unsigned int chan = CR_CHAN(gate_source); 901 unsigned gate2_reg = NITIO_GATE2_REG(cidx); 902 unsigned mode = 0; 903 904 switch (gate_index) { 905 case 0: 906 if (chan == NI_GPCT_DISABLED_GATE_SELECT) { 907 ni_tio_set_bits(counter, NITIO_MODE_REG(cidx), 908 GI_GATING_MODE_MASK, 909 GI_GATING_DISABLED); 910 return 0; 911 } 912 if (gate_source & CR_INVERT) 913 mode |= GI_GATE_POL_INVERT; 914 if (gate_source & CR_EDGE) 915 mode |= GI_RISING_EDGE_GATING; 916 else 917 mode |= GI_LEVEL_GATING; 918 ni_tio_set_bits(counter, NITIO_MODE_REG(cidx), 919 GI_GATE_POL_INVERT | GI_GATING_MODE_MASK, 920 mode); 921 switch (counter_dev->variant) { 922 case ni_gpct_variant_e_series: 923 case ni_gpct_variant_m_series: 924 default: 925 return ni_m_set_gate(counter, gate_source); 926 case ni_gpct_variant_660x: 927 return ni_660x_set_gate(counter, gate_source); 928 } 929 break; 930 case 1: 931 if (!ni_tio_has_gate2_registers(counter_dev)) 932 return -EINVAL; 933 934 if (chan == NI_GPCT_DISABLED_GATE_SELECT) { 935 counter_dev->regs[gate2_reg] &= ~GI_GATE2_MODE; 936 write_register(counter, counter_dev->regs[gate2_reg], 937 gate2_reg); 938 return 0; 939 } 940 if (gate_source & CR_INVERT) 941 counter_dev->regs[gate2_reg] |= GI_GATE2_POL_INVERT; 942 else 943 counter_dev->regs[gate2_reg] &= ~GI_GATE2_POL_INVERT; 944 switch (counter_dev->variant) { 945 case ni_gpct_variant_m_series: 946 return ni_m_set_gate2(counter, gate_source); 947 case ni_gpct_variant_660x: 948 return ni_660x_set_gate2(counter, gate_source); 949 default: 950 BUG(); 951 break; 952 } 953 break; 954 default: 955 return -EINVAL; 956 } 957 return 0; 958} 959EXPORT_SYMBOL_GPL(ni_tio_set_gate_src); 960 961static int ni_tio_set_other_src(struct ni_gpct *counter, unsigned index, 962 unsigned int source) 963{ 964 struct ni_gpct_device *counter_dev = counter->counter_dev; 965 unsigned cidx = counter->counter_index; 966 unsigned int abz_reg, shift, mask; 967 968 if (counter_dev->variant != ni_gpct_variant_m_series) 969 return -EINVAL; 970 971 abz_reg = NITIO_ABZ_REG(cidx); 972 switch (index) { 973 case NI_GPCT_SOURCE_ENCODER_A: 974 shift = 10; 975 break; 976 case NI_GPCT_SOURCE_ENCODER_B: 977 shift = 5; 978 break; 979 case NI_GPCT_SOURCE_ENCODER_Z: 980 shift = 0; 981 break; 982 default: 983 return -EINVAL; 984 } 985 mask = 0x1f << shift; 986 if (source > 0x1f) 987 source = 0x1f; /* Disable gate */ 988 989 counter_dev->regs[abz_reg] &= ~mask; 990 counter_dev->regs[abz_reg] |= (source << shift) & mask; 991 write_register(counter, counter_dev->regs[abz_reg], abz_reg); 992 return 0; 993} 994 995static unsigned ni_660x_gate_to_generic_gate(unsigned gate) 996{ 997 unsigned i; 998 999 switch (gate) { 1000 case NI_660X_SRC_PIN_I_GATE_SEL: 1001 return NI_GPCT_SOURCE_PIN_i_GATE_SELECT; 1002 case NI_660X_GATE_PIN_I_GATE_SEL: 1003 return NI_GPCT_GATE_PIN_i_GATE_SELECT; 1004 case NI_660X_NEXT_SRC_GATE_SEL: 1005 return NI_GPCT_NEXT_SOURCE_GATE_SELECT; 1006 case NI_660X_NEXT_OUT_GATE_SEL: 1007 return NI_GPCT_NEXT_OUT_GATE_SELECT; 1008 case NI_660X_LOGIC_LOW_GATE_SEL: 1009 return NI_GPCT_LOGIC_LOW_GATE_SELECT; 1010 default: 1011 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) { 1012 if (gate == NI_660X_RTSI_GATE_SEL(i)) 1013 return NI_GPCT_RTSI_GATE_SELECT(i); 1014 } 1015 for (i = 0; i <= NI_660X_MAX_GATE_PIN; ++i) { 1016 if (gate == NI_660X_PIN_GATE_SEL(i)) 1017 return NI_GPCT_GATE_PIN_GATE_SELECT(i); 1018 } 1019 BUG(); 1020 break; 1021 } 1022 return 0; 1023}; 1024 1025static unsigned ni_m_gate_to_generic_gate(unsigned gate) 1026{ 1027 unsigned i; 1028 1029 switch (gate) { 1030 case NI_M_TIMESTAMP_MUX_GATE_SEL: 1031 return NI_GPCT_TIMESTAMP_MUX_GATE_SELECT; 1032 case NI_M_AI_START2_GATE_SEL: 1033 return NI_GPCT_AI_START2_GATE_SELECT; 1034 case NI_M_PXI_STAR_TRIGGER_GATE_SEL: 1035 return NI_GPCT_PXI_STAR_TRIGGER_GATE_SELECT; 1036 case NI_M_NEXT_OUT_GATE_SEL: 1037 return NI_GPCT_NEXT_OUT_GATE_SELECT; 1038 case NI_M_AI_START1_GATE_SEL: 1039 return NI_GPCT_AI_START1_GATE_SELECT; 1040 case NI_M_NEXT_SRC_GATE_SEL: 1041 return NI_GPCT_NEXT_SOURCE_GATE_SELECT; 1042 case NI_M_ANALOG_TRIG_OUT_GATE_SEL: 1043 return NI_GPCT_ANALOG_TRIGGER_OUT_GATE_SELECT; 1044 case NI_M_LOGIC_LOW_GATE_SEL: 1045 return NI_GPCT_LOGIC_LOW_GATE_SELECT; 1046 default: 1047 for (i = 0; i <= NI_M_MAX_RTSI_CHAN; ++i) { 1048 if (gate == NI_M_RTSI_GATE_SEL(i)) 1049 return NI_GPCT_RTSI_GATE_SELECT(i); 1050 } 1051 for (i = 0; i <= NI_M_MAX_PFI_CHAN; ++i) { 1052 if (gate == NI_M_PFI_GATE_SEL(i)) 1053 return NI_GPCT_PFI_GATE_SELECT(i); 1054 } 1055 BUG(); 1056 break; 1057 } 1058 return 0; 1059}; 1060 1061static unsigned ni_660x_gate2_to_generic_gate(unsigned gate) 1062{ 1063 unsigned i; 1064 1065 switch (gate) { 1066 case NI_660X_SRC_PIN_I_GATE2_SEL: 1067 return NI_GPCT_SOURCE_PIN_i_GATE_SELECT; 1068 case NI_660X_UD_PIN_I_GATE2_SEL: 1069 return NI_GPCT_UP_DOWN_PIN_i_GATE_SELECT; 1070 case NI_660X_NEXT_SRC_GATE2_SEL: 1071 return NI_GPCT_NEXT_SOURCE_GATE_SELECT; 1072 case NI_660X_NEXT_OUT_GATE2_SEL: 1073 return NI_GPCT_NEXT_OUT_GATE_SELECT; 1074 case NI_660X_SELECTED_GATE2_SEL: 1075 return NI_GPCT_SELECTED_GATE_GATE_SELECT; 1076 case NI_660X_LOGIC_LOW_GATE2_SEL: 1077 return NI_GPCT_LOGIC_LOW_GATE_SELECT; 1078 default: 1079 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) { 1080 if (gate == NI_660X_RTSI_GATE2_SEL(i)) 1081 return NI_GPCT_RTSI_GATE_SELECT(i); 1082 } 1083 for (i = 0; i <= NI_660X_MAX_UP_DOWN_PIN; ++i) { 1084 if (gate == NI_660X_UD_PIN_GATE2_SEL(i)) 1085 return NI_GPCT_UP_DOWN_PIN_GATE_SELECT(i); 1086 } 1087 BUG(); 1088 break; 1089 } 1090 return 0; 1091}; 1092 1093static unsigned ni_m_gate2_to_generic_gate(unsigned gate) 1094{ 1095 /* 1096 * FIXME: the second gate sources for the m series are undocumented, 1097 * so we just return the raw bits for now. 1098 */ 1099 switch (gate) { 1100 default: 1101 return gate; 1102 } 1103 return 0; 1104}; 1105 1106static int ni_tio_get_gate_src(struct ni_gpct *counter, unsigned gate_index, 1107 unsigned int *gate_source) 1108{ 1109 struct ni_gpct_device *counter_dev = counter->counter_dev; 1110 unsigned cidx = counter->counter_index; 1111 unsigned mode = ni_tio_get_soft_copy(counter, NITIO_MODE_REG(cidx)); 1112 unsigned gate2_reg = NITIO_GATE2_REG(cidx); 1113 unsigned gate; 1114 1115 switch (gate_index) { 1116 case 0: 1117 if ((mode & GI_GATING_MODE_MASK) == GI_GATING_DISABLED) { 1118 *gate_source = NI_GPCT_DISABLED_GATE_SELECT; 1119 return 0; 1120 } 1121 1122 gate = GI_BITS_TO_GATE(ni_tio_get_soft_copy(counter, 1123 NITIO_INPUT_SEL_REG(cidx))); 1124 1125 switch (counter_dev->variant) { 1126 case ni_gpct_variant_e_series: 1127 case ni_gpct_variant_m_series: 1128 default: 1129 *gate_source = ni_m_gate_to_generic_gate(gate); 1130 break; 1131 case ni_gpct_variant_660x: 1132 *gate_source = ni_660x_gate_to_generic_gate(gate); 1133 break; 1134 } 1135 if (mode & GI_GATE_POL_INVERT) 1136 *gate_source |= CR_INVERT; 1137 if ((mode & GI_GATING_MODE_MASK) != GI_LEVEL_GATING) 1138 *gate_source |= CR_EDGE; 1139 break; 1140 case 1: 1141 if ((mode & GI_GATING_MODE_MASK) == GI_GATING_DISABLED || 1142 !(counter_dev->regs[gate2_reg] & GI_GATE2_MODE)) { 1143 *gate_source = NI_GPCT_DISABLED_GATE_SELECT; 1144 return 0; 1145 } 1146 1147 gate = GI_BITS_TO_GATE2(counter_dev->regs[gate2_reg]); 1148 1149 switch (counter_dev->variant) { 1150 case ni_gpct_variant_e_series: 1151 case ni_gpct_variant_m_series: 1152 default: 1153 *gate_source = ni_m_gate2_to_generic_gate(gate); 1154 break; 1155 case ni_gpct_variant_660x: 1156 *gate_source = ni_660x_gate2_to_generic_gate(gate); 1157 break; 1158 } 1159 if (counter_dev->regs[gate2_reg] & GI_GATE2_POL_INVERT) 1160 *gate_source |= CR_INVERT; 1161 /* second gate can't have edge/level mode set independently */ 1162 if ((mode & GI_GATING_MODE_MASK) != GI_LEVEL_GATING) 1163 *gate_source |= CR_EDGE; 1164 break; 1165 default: 1166 return -EINVAL; 1167 } 1168 return 0; 1169} 1170 1171int ni_tio_insn_config(struct comedi_device *dev, 1172 struct comedi_subdevice *s, 1173 struct comedi_insn *insn, 1174 unsigned int *data) 1175{ 1176 struct ni_gpct *counter = s->private; 1177 unsigned cidx = counter->counter_index; 1178 unsigned status; 1179 1180 switch (data[0]) { 1181 case INSN_CONFIG_SET_COUNTER_MODE: 1182 return ni_tio_set_counter_mode(counter, data[1]); 1183 case INSN_CONFIG_ARM: 1184 return ni_tio_arm(counter, 1, data[1]); 1185 case INSN_CONFIG_DISARM: 1186 ni_tio_arm(counter, 0, 0); 1187 return 0; 1188 case INSN_CONFIG_GET_COUNTER_STATUS: 1189 data[1] = 0; 1190 status = read_register(counter, NITIO_SHARED_STATUS_REG(cidx)); 1191 if (status & GI_ARMED(cidx)) { 1192 data[1] |= COMEDI_COUNTER_ARMED; 1193 if (status & GI_COUNTING(cidx)) 1194 data[1] |= COMEDI_COUNTER_COUNTING; 1195 } 1196 data[2] = COMEDI_COUNTER_ARMED | COMEDI_COUNTER_COUNTING; 1197 return 0; 1198 case INSN_CONFIG_SET_CLOCK_SRC: 1199 return ni_tio_set_clock_src(counter, data[1], data[2]); 1200 case INSN_CONFIG_GET_CLOCK_SRC: 1201 ni_tio_get_clock_src(counter, &data[1], &data[2]); 1202 return 0; 1203 case INSN_CONFIG_SET_GATE_SRC: 1204 return ni_tio_set_gate_src(counter, data[1], data[2]); 1205 case INSN_CONFIG_GET_GATE_SRC: 1206 return ni_tio_get_gate_src(counter, data[1], &data[2]); 1207 case INSN_CONFIG_SET_OTHER_SRC: 1208 return ni_tio_set_other_src(counter, data[1], data[2]); 1209 case INSN_CONFIG_RESET: 1210 ni_tio_reset_count_and_disarm(counter); 1211 return 0; 1212 default: 1213 break; 1214 } 1215 return -EINVAL; 1216} 1217EXPORT_SYMBOL_GPL(ni_tio_insn_config); 1218 1219static unsigned int ni_tio_read_sw_save_reg(struct comedi_device *dev, 1220 struct comedi_subdevice *s) 1221{ 1222 struct ni_gpct *counter = s->private; 1223 unsigned cidx = counter->counter_index; 1224 unsigned int val; 1225 1226 ni_tio_set_bits(counter, NITIO_CMD_REG(cidx), GI_SAVE_TRACE, 0); 1227 ni_tio_set_bits(counter, NITIO_CMD_REG(cidx), 1228 GI_SAVE_TRACE, GI_SAVE_TRACE); 1229 1230 /* 1231 * The count doesn't get latched until the next clock edge, so it is 1232 * possible the count may change (once) while we are reading. Since 1233 * the read of the SW_Save_Reg isn't atomic (apparently even when it's 1234 * a 32 bit register according to 660x docs), we need to read twice 1235 * and make sure the reading hasn't changed. If it has, a third read 1236 * will be correct since the count value will definitely have latched 1237 * by then. 1238 */ 1239 val = read_register(counter, NITIO_SW_SAVE_REG(cidx)); 1240 if (val != read_register(counter, NITIO_SW_SAVE_REG(cidx))) 1241 val = read_register(counter, NITIO_SW_SAVE_REG(cidx)); 1242 1243 return val; 1244} 1245 1246int ni_tio_insn_read(struct comedi_device *dev, 1247 struct comedi_subdevice *s, 1248 struct comedi_insn *insn, 1249 unsigned int *data) 1250{ 1251 struct ni_gpct *counter = s->private; 1252 struct ni_gpct_device *counter_dev = counter->counter_dev; 1253 unsigned int channel = CR_CHAN(insn->chanspec); 1254 unsigned cidx = counter->counter_index; 1255 int i; 1256 1257 for (i = 0; i < insn->n; i++) { 1258 switch (channel) { 1259 case 0: 1260 data[i] = ni_tio_read_sw_save_reg(dev, s); 1261 break; 1262 case 1: 1263 data[i] = counter_dev->regs[NITIO_LOADA_REG(cidx)]; 1264 break; 1265 case 2: 1266 data[i] = counter_dev->regs[NITIO_LOADB_REG(cidx)]; 1267 break; 1268 } 1269 } 1270 return insn->n; 1271} 1272EXPORT_SYMBOL_GPL(ni_tio_insn_read); 1273 1274static unsigned ni_tio_next_load_register(struct ni_gpct *counter) 1275{ 1276 unsigned cidx = counter->counter_index; 1277 const unsigned bits = 1278 read_register(counter, NITIO_SHARED_STATUS_REG(cidx)); 1279 1280 return (bits & GI_NEXT_LOAD_SRC(cidx)) 1281 ? NITIO_LOADB_REG(cidx) 1282 : NITIO_LOADA_REG(cidx); 1283} 1284 1285int ni_tio_insn_write(struct comedi_device *dev, 1286 struct comedi_subdevice *s, 1287 struct comedi_insn *insn, 1288 unsigned int *data) 1289{ 1290 struct ni_gpct *counter = s->private; 1291 struct ni_gpct_device *counter_dev = counter->counter_dev; 1292 const unsigned channel = CR_CHAN(insn->chanspec); 1293 unsigned cidx = counter->counter_index; 1294 unsigned load_reg; 1295 1296 if (insn->n < 1) 1297 return 0; 1298 switch (channel) { 1299 case 0: 1300 /* 1301 * Unsafe if counter is armed. 1302 * Should probably check status and return -EBUSY if armed. 1303 */ 1304 1305 /* 1306 * Don't disturb load source select, just use whichever 1307 * load register is already selected. 1308 */ 1309 load_reg = ni_tio_next_load_register(counter); 1310 write_register(counter, data[0], load_reg); 1311 ni_tio_set_bits_transient(counter, NITIO_CMD_REG(cidx), 1312 0, 0, GI_LOAD); 1313 /* restore load reg */ 1314 write_register(counter, counter_dev->regs[load_reg], load_reg); 1315 break; 1316 case 1: 1317 counter_dev->regs[NITIO_LOADA_REG(cidx)] = data[0]; 1318 write_register(counter, data[0], NITIO_LOADA_REG(cidx)); 1319 break; 1320 case 2: 1321 counter_dev->regs[NITIO_LOADB_REG(cidx)] = data[0]; 1322 write_register(counter, data[0], NITIO_LOADB_REG(cidx)); 1323 break; 1324 default: 1325 return -EINVAL; 1326 } 1327 return 0; 1328} 1329EXPORT_SYMBOL_GPL(ni_tio_insn_write); 1330 1331void ni_tio_init_counter(struct ni_gpct *counter) 1332{ 1333 struct ni_gpct_device *counter_dev = counter->counter_dev; 1334 unsigned cidx = counter->counter_index; 1335 1336 ni_tio_reset_count_and_disarm(counter); 1337 1338 /* initialize counter registers */ 1339 counter_dev->regs[NITIO_AUTO_INC_REG(cidx)] = 0x0; 1340 write_register(counter, 0x0, NITIO_AUTO_INC_REG(cidx)); 1341 1342 ni_tio_set_bits(counter, NITIO_CMD_REG(cidx), 1343 ~0, GI_SYNC_GATE); 1344 1345 ni_tio_set_bits(counter, NITIO_MODE_REG(cidx), ~0, 0); 1346 1347 counter_dev->regs[NITIO_LOADA_REG(cidx)] = 0x0; 1348 write_register(counter, 0x0, NITIO_LOADA_REG(cidx)); 1349 1350 counter_dev->regs[NITIO_LOADB_REG(cidx)] = 0x0; 1351 write_register(counter, 0x0, NITIO_LOADB_REG(cidx)); 1352 1353 ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx), ~0, 0); 1354 1355 if (ni_tio_counting_mode_registers_present(counter_dev)) 1356 ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx), ~0, 0); 1357 1358 if (ni_tio_has_gate2_registers(counter_dev)) { 1359 counter_dev->regs[NITIO_GATE2_REG(cidx)] = 0x0; 1360 write_register(counter, 0x0, NITIO_GATE2_REG(cidx)); 1361 } 1362 1363 ni_tio_set_bits(counter, NITIO_DMA_CFG_REG(cidx), ~0, 0x0); 1364 1365 ni_tio_set_bits(counter, NITIO_INT_ENA_REG(cidx), ~0, 0x0); 1366} 1367EXPORT_SYMBOL_GPL(ni_tio_init_counter); 1368 1369struct ni_gpct_device * 1370ni_gpct_device_construct(struct comedi_device *dev, 1371 void (*write_register)(struct ni_gpct *counter, 1372 unsigned bits, 1373 enum ni_gpct_register reg), 1374 unsigned (*read_register)(struct ni_gpct *counter, 1375 enum ni_gpct_register reg), 1376 enum ni_gpct_variant variant, 1377 unsigned num_counters) 1378{ 1379 struct ni_gpct_device *counter_dev; 1380 struct ni_gpct *counter; 1381 unsigned i; 1382 1383 if (num_counters == 0) 1384 return NULL; 1385 1386 counter_dev = kzalloc(sizeof(*counter_dev), GFP_KERNEL); 1387 if (!counter_dev) 1388 return NULL; 1389 1390 counter_dev->dev = dev; 1391 counter_dev->write_register = write_register; 1392 counter_dev->read_register = read_register; 1393 counter_dev->variant = variant; 1394 1395 spin_lock_init(&counter_dev->regs_lock); 1396 1397 counter_dev->counters = kcalloc(num_counters, sizeof(*counter), 1398 GFP_KERNEL); 1399 if (!counter_dev->counters) { 1400 kfree(counter_dev); 1401 return NULL; 1402 } 1403 1404 for (i = 0; i < num_counters; ++i) { 1405 counter = &counter_dev->counters[i]; 1406 counter->counter_dev = counter_dev; 1407 spin_lock_init(&counter->lock); 1408 } 1409 counter_dev->num_counters = num_counters; 1410 1411 return counter_dev; 1412} 1413EXPORT_SYMBOL_GPL(ni_gpct_device_construct); 1414 1415void ni_gpct_device_destroy(struct ni_gpct_device *counter_dev) 1416{ 1417 if (!counter_dev->counters) 1418 return; 1419 kfree(counter_dev->counters); 1420 kfree(counter_dev); 1421} 1422EXPORT_SYMBOL_GPL(ni_gpct_device_destroy); 1423 1424static int __init ni_tio_init_module(void) 1425{ 1426 return 0; 1427} 1428module_init(ni_tio_init_module); 1429 1430static void __exit ni_tio_cleanup_module(void) 1431{ 1432} 1433module_exit(ni_tio_cleanup_module); 1434 1435MODULE_AUTHOR("Comedi <comedi@comedi.org>"); 1436MODULE_DESCRIPTION("Comedi support for NI general-purpose counters"); 1437MODULE_LICENSE("GPL"); 1438