pcmuio.c revision 1699d80aef8ba7992d5f4176aed3504db8cffaf9
1/* 2 * pcmuio.c 3 * Comedi driver for Winsystems PC-104 based 48/96-channel DIO boards. 4 * 5 * COMEDI - Linux Control and Measurement Device Interface 6 * Copyright (C) 2006 Calin A. Culianu <calin@ajvar.org> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19/* 20 * Driver: pcmuio 21 * Description: Winsystems PC-104 based 48/96-channel DIO boards. 22 * Devices: (Winsystems) PCM-UIO48A [pcmuio48] 23 * (Winsystems) PCM-UIO96A [pcmuio96] 24 * Author: Calin Culianu <calin@ajvar.org> 25 * Updated: Fri, 13 Jan 2006 12:01:01 -0500 26 * Status: works 27 * 28 * A driver for the relatively straightforward-to-program PCM-UIO48A and 29 * PCM-UIO96A boards from Winsystems. These boards use either one or two 30 * (in the 96-DIO version) WS16C48 ASIC HighDensity I/O Chips (HDIO). This 31 * chip is interesting in that each I/O line is individually programmable 32 * for INPUT or OUTPUT (thus comedi_dio_config can be done on a per-channel 33 * basis). Also, each chip supports edge-triggered interrupts for the first 34 * 24 I/O lines. Of course, since the 96-channel version of the board has 35 * two ASICs, it can detect polarity changes on up to 48 I/O lines. Since 36 * this is essentially an (non-PnP) ISA board, I/O Address and IRQ selection 37 * are done through jumpers on the board. You need to pass that information 38 * to this driver as the first and second comedi_config option, respectively. 39 * Note that the 48-channel version uses 16 bytes of IO memory and the 96- 40 * channel version uses 32-bytes (in case you are worried about conflicts). 41 * The 48-channel board is split into two 24-channel comedi subdevices. The 42 * 96-channel board is split into 4 24-channel DIO subdevices. 43 * 44 * Note that IRQ support has been added, but it is untested. 45 * 46 * To use edge-detection IRQ support, pass the IRQs of both ASICS (for the 47 * 96 channel version) or just 1 ASIC (for 48-channel version). Then, use 48 * comedi_commands with TRIG_NOW. Your callback will be called each time an 49 * edge is triggered, and the data values will be two sample_t's, which 50 * should be concatenated to form one 32-bit unsigned int. This value is 51 * the mask of channels that had edges detected from your channel list. Note 52 * that the bits positions in the mask correspond to positions in your 53 * chanlist when you specified the command and *not* channel id's! 54 * 55 * To set the polarity of the edge-detection interrupts pass a nonzero value 56 * for either CR_RANGE or CR_AREF for edge-up polarity, or a zero value for 57 * both CR_RANGE and CR_AREF if you want edge-down polarity. 58 * 59 * In the 48-channel version: 60 * 61 * On subdev 0, the first 24 channels channels are edge-detect channels. 62 * 63 * In the 96-channel board you have the following channels that can do edge 64 * detection: 65 * 66 * subdev 0, channels 0-24 (first 24 channels of 1st ASIC) 67 * subdev 2, channels 0-24 (first 24 channels of 2nd ASIC) 68 * 69 * Configuration Options: 70 * [0] - I/O port base address 71 * [1] - IRQ (for first ASIC, or first 24 channels) 72 * [2] - IRQ (for second ASIC, pcmuio96 only - IRQ for chans 48-72 73 * can be the same as first irq!) 74 */ 75 76#include <linux/interrupt.h> 77#include <linux/slab.h> 78 79#include "../comedidev.h" 80 81#include "comedi_fc.h" 82 83/* 84 * Register I/O map 85 * 86 * Offset Page 0 Page 1 Page 2 Page 3 87 * ------ ----------- ----------- ----------- ----------- 88 * 0x00 Port 0 I/O Port 0 I/O Port 0 I/O Port 0 I/O 89 * 0x01 Port 1 I/O Port 1 I/O Port 1 I/O Port 1 I/O 90 * 0x02 Port 2 I/O Port 2 I/O Port 2 I/O Port 2 I/O 91 * 0x03 Port 3 I/O Port 3 I/O Port 3 I/O Port 3 I/O 92 * 0x04 Port 4 I/O Port 4 I/O Port 4 I/O Port 4 I/O 93 * 0x05 Port 5 I/O Port 5 I/O Port 5 I/O Port 5 I/O 94 * 0x06 INT_PENDING INT_PENDING INT_PENDING INT_PENDING 95 * 0x07 Page/Lock Page/Lock Page/Lock Page/Lock 96 * 0x08 N/A POL_0 ENAB_0 INT_ID0 97 * 0x09 N/A POL_1 ENAB_1 INT_ID1 98 * 0x0a N/A POL_2 ENAB_2 INT_ID2 99 */ 100#define PCMUIO_PORT_REG(x) (0x00 + (x)) 101#define PCMUIO_INT_PENDING_REG 0x06 102#define PCMUIO_PAGE_LOCK_REG 0x07 103#define PCMUIO_LOCK_PORT(x) ((1 << (x)) & 0x3f) 104#define PCMUIO_PAGE(x) (((x) & 0x3) << 6) 105#define PCMUIO_PAGE_MASK PCMUIO_PAGE(3) 106#define PCMUIO_PAGE_POL 1 107#define PCMUIO_PAGE_ENAB 2 108#define PCMUIO_PAGE_INT_ID 3 109#define PCMUIO_PAGE_REG(x) (0x08 + (x)) 110 111#define CHANS_PER_PORT 8 112#define PORTS_PER_ASIC 6 113#define INTR_PORTS_PER_ASIC 3 114/* number of channels per comedi subdevice */ 115#define MAX_CHANS_PER_SUBDEV 24 116#define PORTS_PER_SUBDEV (MAX_CHANS_PER_SUBDEV / CHANS_PER_PORT) 117#define CHANS_PER_ASIC (CHANS_PER_PORT * PORTS_PER_ASIC) 118#define INTR_CHANS_PER_ASIC 24 119#define INTR_PORTS_PER_SUBDEV (INTR_CHANS_PER_ASIC / CHANS_PER_PORT) 120#define MAX_DIO_CHANS (PORTS_PER_ASIC * 2 * CHANS_PER_PORT) 121#define MAX_ASICS (MAX_DIO_CHANS / CHANS_PER_ASIC) 122 123/* IO Memory sizes */ 124#define ASIC_IOSIZE 0x10 125#define PCMUIO48_IOSIZE ASIC_IOSIZE 126#define PCMUIO96_IOSIZE (ASIC_IOSIZE * 2) 127 128struct pcmuio_board { 129 const char *name; 130 const int num_asics; 131}; 132 133static const struct pcmuio_board pcmuio_boards[] = { 134 { 135 .name = "pcmuio48", 136 .num_asics = 1, 137 }, { 138 .name = "pcmuio96", 139 .num_asics = 2, 140 }, 141}; 142 143struct pcmuio_subdev_private { 144 /* The below is only used for intr subdevices */ 145 struct { 146 /* if non-negative, this subdev has an interrupt asic */ 147 int asic; 148 /* 149 * subdev-relative channel mask for channels 150 * we are interested in 151 */ 152 int enabled_mask; 153 int active; 154 int stop_count; 155 int continuous; 156 spinlock_t spinlock; 157 } intr; 158}; 159 160struct pcmuio_private { 161 struct { 162 unsigned int irq; 163 spinlock_t spinlock; 164 } asics[MAX_ASICS]; 165 struct pcmuio_subdev_private *sprivs; 166}; 167 168static void pcmuio_write(struct comedi_device *dev, unsigned int val, 169 int asic, int page, int port) 170{ 171 unsigned long iobase = dev->iobase + (asic * ASIC_IOSIZE); 172 173 if (page == 0) { 174 /* Port registers are valid for any page */ 175 outb(val & 0xff, iobase + PCMUIO_PORT_REG(port + 0)); 176 outb((val >> 8) & 0xff, iobase + PCMUIO_PORT_REG(port + 1)); 177 outb((val >> 16) & 0xff, iobase + PCMUIO_PORT_REG(port + 2)); 178 } else { 179 outb(PCMUIO_PAGE(page), iobase + PCMUIO_PAGE_LOCK_REG); 180 outb(val & 0xff, iobase + PCMUIO_PAGE_REG(0)); 181 outb((val >> 8) & 0xff, iobase + PCMUIO_PAGE_REG(1)); 182 outb((val >> 16) & 0xff, iobase + PCMUIO_PAGE_REG(2)); 183 } 184} 185 186static int pcmuio_dio_insn_bits(struct comedi_device *dev, 187 struct comedi_subdevice *s, 188 struct comedi_insn *insn, unsigned int *data) 189{ 190 int asic = s->index / 2; 191 int port = (s->index % 2) ? 3 : 0; 192 unsigned long iobase = dev->iobase + (asic * ASIC_IOSIZE); 193 int byte_no; 194 195 /* NOTE: 196 reading a 0 means this channel was high 197 writine a 0 sets the channel high 198 reading a 1 means this channel was low 199 writing a 1 means set this channel low 200 201 Therefore everything is always inverted. */ 202 203 /* The insn data is a mask in data[0] and the new data 204 * in data[1], each channel cooresponding to a bit. */ 205 206 s->state = 0; 207 208 for (byte_no = 0; byte_no < s->n_chan / CHANS_PER_PORT; ++byte_no) { 209 /* bit offset of port in 32-bit doubleword */ 210 unsigned long offset = byte_no * 8; 211 /* this 8-bit port's data */ 212 unsigned char byte = 0, 213 /* The write mask for this port (if any) */ 214 write_mask_byte = (data[0] >> offset) & 0xff, 215 /* The data byte for this port */ 216 data_byte = (data[1] >> offset) & 0xff; 217 218 byte = inb(iobase + PCMUIO_PORT_REG(port + byte_no)); 219 220 if (write_mask_byte) { 221 byte &= ~write_mask_byte; 222 byte |= ~data_byte & write_mask_byte; 223 outb(byte, iobase + PCMUIO_PORT_REG(port + byte_no)); 224 } 225 /* save the digital input lines for this byte.. */ 226 s->state |= ((unsigned int)byte) << offset; 227 } 228 229 /* now return the DIO lines to data[1] - note they came inverted! */ 230 data[1] = ~s->state; 231 232 return insn->n; 233} 234 235static int pcmuio_dio_insn_config(struct comedi_device *dev, 236 struct comedi_subdevice *s, 237 struct comedi_insn *insn, unsigned int *data) 238{ 239 int asic = s->index / 2; 240 int port = (s->index % 2) ? 3 : 0; 241 unsigned long iobase = dev->iobase + (asic * ASIC_IOSIZE); 242 unsigned int chan = CR_CHAN(insn->chanspec); 243 int byte_no = chan / 8; 244 int bit_no = chan % 8; 245 unsigned char byte; 246 247 /* NOTE: 248 writing a 0 an IO channel's bit sets the channel to INPUT 249 and pulls the line high as well 250 251 writing a 1 to an IO channel's bit pulls the line low 252 253 All channels are implicitly always in OUTPUT mode -- but when 254 they are high they can be considered to be in INPUT mode.. 255 256 Thus, we only force channels low if the config request was INPUT, 257 otherwise we do nothing to the hardware. */ 258 259 switch (data[0]) { 260 case INSN_CONFIG_DIO_OUTPUT: 261 /* save to io_bits -- don't actually do anything since 262 all input channels are also output channels... */ 263 s->io_bits |= 1 << chan; 264 break; 265 case INSN_CONFIG_DIO_INPUT: 266 /* write a 0 to the actual register representing the channel 267 to set it to 'input'. 0 means "float high". */ 268 byte = inb(iobase + PCMUIO_PORT_REG(port + byte_no)); 269 byte &= ~(1 << bit_no); 270 /**< set input channel to '0' */ 271 272 /* 273 * write out byte 274 * This is the only time we actually affect the hardware 275 * as all channels are implicitly output -- but input 276 * channels are set to float-high. 277 */ 278 outb(byte, iobase + PCMUIO_PORT_REG(port + byte_no)); 279 280 /* save to io_bits */ 281 s->io_bits &= ~(1 << chan); 282 break; 283 284 case INSN_CONFIG_DIO_QUERY: 285 /* retrieve from shadow register */ 286 data[1] = 287 (s->io_bits & (1 << chan)) ? COMEDI_OUTPUT : COMEDI_INPUT; 288 return insn->n; 289 break; 290 291 default: 292 return -EINVAL; 293 break; 294 } 295 296 return insn->n; 297} 298 299static void switch_page(struct comedi_device *dev, int asic, int page) 300{ 301 outb(PCMUIO_PAGE(page), 302 dev->iobase + ASIC_IOSIZE * asic + PCMUIO_PAGE_LOCK_REG); 303} 304 305static void init_asics(struct comedi_device *dev) 306{ 307 const struct pcmuio_board *board = comedi_board(dev); 308 int asic; 309 310 for (asic = 0; asic < board->num_asics; ++asic) { 311 /* first, clear all the DIO port bits */ 312 pcmuio_write(dev, 0, asic, 0, 0); 313 pcmuio_write(dev, 0, asic, 0, 3); 314 315 /* Next, clear all the paged registers for each page */ 316 pcmuio_write(dev, 0, asic, PCMUIO_PAGE_POL, 0); 317 pcmuio_write(dev, 0, asic, PCMUIO_PAGE_ENAB, 0); 318 pcmuio_write(dev, 0, asic, PCMUIO_PAGE_INT_ID, 0); 319 } 320} 321 322static void pcmuio_stop_intr(struct comedi_device *dev, 323 struct comedi_subdevice *s) 324{ 325 struct pcmuio_subdev_private *subpriv = s->private; 326 int asic; 327 328 asic = subpriv->intr.asic; 329 if (asic < 0) 330 return; /* not an interrupt subdev */ 331 332 subpriv->intr.enabled_mask = 0; 333 subpriv->intr.active = 0; 334 s->async->inttrig = NULL; 335 336 /* disable all intrs for this subdev.. */ 337 pcmuio_write(dev, 0, asic, PCMUIO_PAGE_ENAB, 0); 338} 339 340static void pcmuio_handle_intr_subdev(struct comedi_device *dev, 341 struct comedi_subdevice *s, 342 unsigned triggered) 343{ 344 struct pcmuio_subdev_private *subpriv = s->private; 345 unsigned int len = s->async->cmd.chanlist_len; 346 unsigned oldevents = s->async->events; 347 unsigned int val = 0; 348 unsigned long flags; 349 unsigned mytrig; 350 unsigned int i; 351 352 spin_lock_irqsave(&subpriv->intr.spinlock, flags); 353 354 if (!subpriv->intr.active) 355 goto done; 356 357 mytrig = triggered; 358 mytrig &= ((0x1 << s->n_chan) - 1); 359 360 if (!(mytrig & subpriv->intr.enabled_mask)) 361 goto done; 362 363 for (i = 0; i < len; i++) { 364 unsigned int chan = CR_CHAN(s->async->cmd.chanlist[i]); 365 if (mytrig & (1U << chan)) 366 val |= (1U << i); 367 } 368 369 /* Write the scan to the buffer. */ 370 if (comedi_buf_put(s->async, ((short *)&val)[0]) && 371 comedi_buf_put(s->async, ((short *)&val)[1])) { 372 s->async->events |= (COMEDI_CB_BLOCK | COMEDI_CB_EOS); 373 } else { 374 /* Overflow! Stop acquisition!! */ 375 /* TODO: STOP_ACQUISITION_CALL_HERE!! */ 376 pcmuio_stop_intr(dev, s); 377 } 378 379 /* Check for end of acquisition. */ 380 if (!subpriv->intr.continuous) { 381 /* stop_src == TRIG_COUNT */ 382 if (subpriv->intr.stop_count > 0) { 383 subpriv->intr.stop_count--; 384 if (subpriv->intr.stop_count == 0) { 385 s->async->events |= COMEDI_CB_EOA; 386 /* TODO: STOP_ACQUISITION_CALL_HERE!! */ 387 pcmuio_stop_intr(dev, s); 388 } 389 } 390 } 391 392done: 393 spin_unlock_irqrestore(&subpriv->intr.spinlock, flags); 394 395 if (oldevents != s->async->events) 396 comedi_event(dev, s); 397} 398 399static int pcmuio_handle_asic_interrupt(struct comedi_device *dev, int asic) 400{ 401 struct pcmuio_private *devpriv = dev->private; 402 struct pcmuio_subdev_private *subpriv; 403 unsigned long iobase = dev->iobase + (asic * ASIC_IOSIZE); 404 unsigned triggered = 0; 405 int got1 = 0; 406 unsigned long flags; 407 unsigned char int_pend; 408 int i; 409 410 spin_lock_irqsave(&devpriv->asics[asic].spinlock, flags); 411 412 int_pend = inb(iobase + PCMUIO_INT_PENDING_REG) & 0x07; 413 if (int_pend) { 414 for (i = 0; i < INTR_PORTS_PER_ASIC; ++i) { 415 if (int_pend & (0x1 << i)) { 416 unsigned char val; 417 418 switch_page(dev, asic, PCMUIO_PAGE_INT_ID); 419 val = inb(iobase + PCMUIO_PAGE_REG(i)); 420 if (val) 421 /* clear pending interrupt */ 422 outb(0, iobase + PCMUIO_PAGE_REG(i)); 423 424 triggered |= (val << (i * 8)); 425 } 426 } 427 428 ++got1; 429 } 430 431 spin_unlock_irqrestore(&devpriv->asics[asic].spinlock, flags); 432 433 if (triggered) { 434 struct comedi_subdevice *s; 435 /* TODO here: dispatch io lines to subdevs with commands.. */ 436 for (i = 0; i < dev->n_subdevices; i++) { 437 s = &dev->subdevices[i]; 438 subpriv = s->private; 439 if (subpriv->intr.asic == asic) { 440 /* 441 * This is an interrupt subdev, and it 442 * matches this asic! 443 */ 444 pcmuio_handle_intr_subdev(dev, s, 445 triggered); 446 } 447 } 448 } 449 return got1; 450} 451 452static irqreturn_t interrupt_pcmuio(int irq, void *d) 453{ 454 struct comedi_device *dev = d; 455 struct pcmuio_private *devpriv = dev->private; 456 int got1 = 0; 457 int asic; 458 459 for (asic = 0; asic < MAX_ASICS; ++asic) { 460 if (irq == devpriv->asics[asic].irq) { 461 /* it is an interrupt for ASIC #asic */ 462 if (pcmuio_handle_asic_interrupt(dev, asic)) 463 got1++; 464 } 465 } 466 if (!got1) 467 return IRQ_NONE; /* interrupt from other source */ 468 return IRQ_HANDLED; 469} 470 471static int pcmuio_start_intr(struct comedi_device *dev, 472 struct comedi_subdevice *s) 473{ 474 struct pcmuio_subdev_private *subpriv = s->private; 475 476 if (!subpriv->intr.continuous && subpriv->intr.stop_count == 0) { 477 /* An empty acquisition! */ 478 s->async->events |= COMEDI_CB_EOA; 479 subpriv->intr.active = 0; 480 return 1; 481 } else { 482 unsigned bits = 0, pol_bits = 0, n; 483 int asic; 484 struct comedi_cmd *cmd = &s->async->cmd; 485 486 asic = subpriv->intr.asic; 487 if (asic < 0) 488 return 1; /* not an interrupt 489 subdev */ 490 subpriv->intr.enabled_mask = 0; 491 subpriv->intr.active = 1; 492 if (cmd->chanlist) { 493 for (n = 0; n < cmd->chanlist_len; n++) { 494 bits |= (1U << CR_CHAN(cmd->chanlist[n])); 495 pol_bits |= (CR_AREF(cmd->chanlist[n]) 496 || CR_RANGE(cmd-> 497 chanlist[n]) ? 1U : 0U) 498 << CR_CHAN(cmd->chanlist[n]); 499 } 500 } 501 bits &= ((0x1 << s->n_chan) - 1); 502 subpriv->intr.enabled_mask = bits; 503 504 /* set pol and enab intrs for this subdev.. */ 505 pcmuio_write(dev, pol_bits, asic, PCMUIO_PAGE_POL, 0); 506 pcmuio_write(dev, bits, asic, PCMUIO_PAGE_ENAB, 0); 507 } 508 return 0; 509} 510 511static int pcmuio_cancel(struct comedi_device *dev, struct comedi_subdevice *s) 512{ 513 struct pcmuio_subdev_private *subpriv = s->private; 514 unsigned long flags; 515 516 spin_lock_irqsave(&subpriv->intr.spinlock, flags); 517 if (subpriv->intr.active) 518 pcmuio_stop_intr(dev, s); 519 spin_unlock_irqrestore(&subpriv->intr.spinlock, flags); 520 521 return 0; 522} 523 524/* 525 * Internal trigger function to start acquisition for an 'INTERRUPT' subdevice. 526 */ 527static int 528pcmuio_inttrig_start_intr(struct comedi_device *dev, struct comedi_subdevice *s, 529 unsigned int trignum) 530{ 531 struct pcmuio_subdev_private *subpriv = s->private; 532 unsigned long flags; 533 int event = 0; 534 535 if (trignum != 0) 536 return -EINVAL; 537 538 spin_lock_irqsave(&subpriv->intr.spinlock, flags); 539 s->async->inttrig = NULL; 540 if (subpriv->intr.active) 541 event = pcmuio_start_intr(dev, s); 542 543 spin_unlock_irqrestore(&subpriv->intr.spinlock, flags); 544 545 if (event) 546 comedi_event(dev, s); 547 548 return 1; 549} 550 551/* 552 * 'do_cmd' function for an 'INTERRUPT' subdevice. 553 */ 554static int pcmuio_cmd(struct comedi_device *dev, struct comedi_subdevice *s) 555{ 556 struct pcmuio_subdev_private *subpriv = s->private; 557 struct comedi_cmd *cmd = &s->async->cmd; 558 unsigned long flags; 559 int event = 0; 560 561 spin_lock_irqsave(&subpriv->intr.spinlock, flags); 562 subpriv->intr.active = 1; 563 564 /* Set up end of acquisition. */ 565 switch (cmd->stop_src) { 566 case TRIG_COUNT: 567 subpriv->intr.continuous = 0; 568 subpriv->intr.stop_count = cmd->stop_arg; 569 break; 570 default: 571 /* TRIG_NONE */ 572 subpriv->intr.continuous = 1; 573 subpriv->intr.stop_count = 0; 574 break; 575 } 576 577 /* Set up start of acquisition. */ 578 switch (cmd->start_src) { 579 case TRIG_INT: 580 s->async->inttrig = pcmuio_inttrig_start_intr; 581 break; 582 default: 583 /* TRIG_NOW */ 584 event = pcmuio_start_intr(dev, s); 585 break; 586 } 587 spin_unlock_irqrestore(&subpriv->intr.spinlock, flags); 588 589 if (event) 590 comedi_event(dev, s); 591 592 return 0; 593} 594 595static int pcmuio_cmdtest(struct comedi_device *dev, 596 struct comedi_subdevice *s, 597 struct comedi_cmd *cmd) 598{ 599 int err = 0; 600 601 /* Step 1 : check if triggers are trivially valid */ 602 603 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_INT); 604 err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT); 605 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW); 606 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT); 607 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE); 608 609 if (err) 610 return 1; 611 612 /* Step 2a : make sure trigger sources are unique */ 613 614 err |= cfc_check_trigger_is_unique(cmd->start_src); 615 err |= cfc_check_trigger_is_unique(cmd->stop_src); 616 617 /* Step 2b : and mutually compatible */ 618 619 if (err) 620 return 2; 621 622 /* Step 3: check if arguments are trivially valid */ 623 624 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0); 625 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0); 626 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0); 627 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len); 628 629 switch (cmd->stop_src) { 630 case TRIG_COUNT: 631 /* any count allowed */ 632 break; 633 case TRIG_NONE: 634 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0); 635 break; 636 default: 637 break; 638 } 639 640 if (err) 641 return 3; 642 643 /* step 4: fix up any arguments */ 644 645 /* if (err) return 4; */ 646 647 return 0; 648} 649 650static int pcmuio_attach(struct comedi_device *dev, struct comedi_devconfig *it) 651{ 652 const struct pcmuio_board *board = comedi_board(dev); 653 struct comedi_subdevice *s; 654 struct pcmuio_private *devpriv; 655 struct pcmuio_subdev_private *subpriv; 656 int sdev_no, n_subdevs, asic; 657 unsigned int irq[MAX_ASICS]; 658 int ret; 659 660 irq[0] = it->options[1]; 661 irq[1] = it->options[2]; 662 663 ret = comedi_request_region(dev, it->options[0], 664 board->num_asics * ASIC_IOSIZE); 665 if (ret) 666 return ret; 667 668 devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL); 669 if (!devpriv) 670 return -ENOMEM; 671 dev->private = devpriv; 672 673 for (asic = 0; asic < MAX_ASICS; ++asic) 674 spin_lock_init(&devpriv->asics[asic].spinlock); 675 676 n_subdevs = board->num_asics * 2; 677 devpriv->sprivs = kcalloc(n_subdevs, 678 sizeof(struct pcmuio_subdev_private), 679 GFP_KERNEL); 680 if (!devpriv->sprivs) 681 return -ENOMEM; 682 683 ret = comedi_alloc_subdevices(dev, n_subdevs); 684 if (ret) 685 return ret; 686 687 for (sdev_no = 0; sdev_no < (int)dev->n_subdevices; ++sdev_no) { 688 s = &dev->subdevices[sdev_no]; 689 subpriv = &devpriv->sprivs[sdev_no]; 690 s->private = subpriv; 691 s->maxdata = 1; 692 s->range_table = &range_digital; 693 s->subdev_flags = SDF_READABLE | SDF_WRITABLE; 694 s->type = COMEDI_SUBD_DIO; 695 s->insn_bits = pcmuio_dio_insn_bits; 696 s->insn_config = pcmuio_dio_insn_config; 697 s->n_chan = 24; 698 699 /* subdevices 0 and 2 suppport interrupts */ 700 if ((sdev_no % 2) == 0) { 701 /* setup the interrupt subdevice */ 702 subpriv->intr.asic = sdev_no / 2; 703 dev->read_subdev = s; 704 s->subdev_flags |= SDF_CMD_READ; 705 s->cancel = pcmuio_cancel; 706 s->do_cmd = pcmuio_cmd; 707 s->do_cmdtest = pcmuio_cmdtest; 708 s->len_chanlist = s->n_chan; 709 } else { 710 subpriv->intr.asic = -1; 711 s->len_chanlist = 1; 712 } 713 spin_lock_init(&subpriv->intr.spinlock); 714 } 715 716 init_asics(dev); /* clear out all the registers, basically */ 717 718 for (asic = 0; irq[0] && asic < MAX_ASICS; ++asic) { 719 if (irq[asic] 720 && request_irq(irq[asic], interrupt_pcmuio, 721 IRQF_SHARED, board->name, dev)) { 722 int i; 723 /* unroll the allocated irqs.. */ 724 for (i = asic - 1; i >= 0; --i) { 725 free_irq(irq[i], dev); 726 devpriv->asics[i].irq = irq[i] = 0; 727 } 728 irq[asic] = 0; 729 } 730 devpriv->asics[asic].irq = irq[asic]; 731 } 732 733 if (irq[0]) { 734 dev_dbg(dev->class_dev, "irq: %u\n", irq[0]); 735 if (irq[1] && board->num_asics == 2) 736 dev_dbg(dev->class_dev, "second ASIC irq: %u\n", 737 irq[1]); 738 } else { 739 dev_dbg(dev->class_dev, "(IRQ mode disabled)\n"); 740 } 741 742 743 return 1; 744} 745 746static void pcmuio_detach(struct comedi_device *dev) 747{ 748 struct pcmuio_private *devpriv = dev->private; 749 int i; 750 751 for (i = 0; i < MAX_ASICS; ++i) { 752 if (devpriv->asics[i].irq) 753 free_irq(devpriv->asics[i].irq, dev); 754 } 755 if (devpriv && devpriv->sprivs) 756 kfree(devpriv->sprivs); 757 comedi_legacy_detach(dev); 758} 759 760static struct comedi_driver pcmuio_driver = { 761 .driver_name = "pcmuio", 762 .module = THIS_MODULE, 763 .attach = pcmuio_attach, 764 .detach = pcmuio_detach, 765 .board_name = &pcmuio_boards[0].name, 766 .offset = sizeof(struct pcmuio_board), 767 .num_names = ARRAY_SIZE(pcmuio_boards), 768}; 769module_comedi_driver(pcmuio_driver); 770 771MODULE_AUTHOR("Comedi http://www.comedi.org"); 772MODULE_DESCRIPTION("Comedi low-level driver"); 773MODULE_LICENSE("GPL"); 774